From owner-ibis  Fri Aug  1 08:59:08 1997
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9708011557.AA14324@rockie.nsc.com>
To: ibis@vhdl.org
Subject: IBIS Teleconference Agenda - Aug8th'97
Cc: huq@rockie.nsc.com



                       IBIS Open Forum Meeting Agenda 
                                for 8/8/97

                  Bridge Number    Reservation #   Passcode
                  (916) 356-9200   3-125343        4891173


 All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
 meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
 Reservation Number and Passcode.
 
 8:00 Check-In, Intros, Announcements                         Ross

      - Intros of New IBIS Participants, Meeting Quorum       Ross
      - Membership Update and Treasurers Report               Rusher
      - Review of Previous Meeting's Minutes (and ARs)        Peters
      - Miscellany/Announcements                              All
      - Press & Web Page Updates                              Huq, All
      - New Models Available, Library Update                  Powell, All
      - Opens for New Issues                                  All

 8:25 Administrative and Project Discussions

      International Progress                                  Rusher/Ross
      - 93/46/NP (IBIS Version 2.1)
      - 93/60/NP (IBIS Models and EMC Simulation)
      - EIAJ III (I/O Interface Model for ICs)

      Editing Committee                                       Ross/Peters

      Version 3.1 Parser                                      Ross

      Cookbook                                                Peters

      New Administrative Issues                               All

 8:50 Technical Discussion
 
      BIRD42.3 Modeling Current Waveforms                     Kumar/Ross

      BIRD44 Interpretation of Min/Max/Weak/Strong Data       Ross

      Switched Terminators                                    Muranyi

      New Technical Issues                                    All

 9:50 Wrap Up and Next Meetings Plans                         Ross

 9:55 Sign Off
 





 
From owner-ibis  Fri Aug  1 10:23:44 1997
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Date: Fri, 01 Aug 1997 10:27:00 -0700
From: Chris Rokusek <crokusek@qdt.com>
Organization: Quad Design Technology
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Hi All,

Two quick questions:

1) I would like to get an idea of when V3.0 will be supported.  I have a
number of customers interested in the features of V3.0 but the parser is
not available.  Is it true that we haven't found a parser software
developer yet?  (A customer actually sent in a file with 3.0 features in
it today).

2) Is V3.0 formally an "ANSI" spec just as V2.1 is or has it only been
approved for release to EIA (I don't know if my abbreviations are
correct)?  If no, is there a timeline or urgency to do so?

Best Regards,

-Chris Rokusek
Viewlogic
 
From owner-ibis  Fri Aug  1 11:32:27 1997
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Date: Fri, 1 Aug 97 11:30:53 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9708011830.AA18079@rockie.nsc.com>
To: ibis@vhdl.org, crokusek@qdt.com
Subject: Re: 3.0 Files

Chris,

We are in the process of finding a parser developer. We have
received information from various interested parties. On Aug8th,
during our scheduled teleconference, parser development plans
will be addressed.

v3.0 has been ratified by the forum. We will have to make some
editorial changes before submitting it as 'official' version to
ANSI. All these work will take place within the next couple of
months. We will work towards getting this out soon. At the same
time, we need to have the v3.0 parser out as well.

Stay tuned.
Regards,
Syed.
Vice-Chair ANSI/EIA-656
National Semiconductor Corp.

> From owner-ibis@server.vhdl.org Fri Aug  1 10:45:10 1997
> Sender: crokusek@qdt.com
> Date: Fri, 01 Aug 1997 10:27:00 -0700
> From: Chris Rokusek <crokusek@qdt.com>
> Organization: Quad Design Technology
> X-Mailer: Mozilla 3.01Gold (X11; I; SunOS 4.1.4 sun4m)
> To: ibis@vhdl.org
> Subject: 3.0 Files
> Content-Type> : > text/plain> ; > charset=us-ascii> 
> Content-Transfer-Encoding: 7bit
> 
> Hi All,
> 
> Two quick questions:
> 
> 1) I would like to get an idea of when V3.0 will be supported.  I have a
> number of customers interested in the features of V3.0 but the parser is
> not available.  Is it true that we haven't found a parser software
> developer yet?  (A customer actually sent in a file with 3.0 features in
> it today).
> 
> 2) Is V3.0 formally an "ANSI" spec just as V2.1 is or has it only been
> approved for release to EIA (I don't know if my abbreviations are
> correct)?  If no, is there a timeline or urgency to do so?
> 
> Best Regards,
> 
> -Chris Rokusek
> Viewlogic
> 
 
From owner-ibis  Tue Aug  5 01:54:48 1997
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From: "Eitan Medina" <eitan@galileo.co.il>
Organization: Galileo Technology Ltd.
To: ibis@vhdl.org
Date: Tue, 5 Aug 1997 10:51:47 +0200
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Subject: Package L,C values
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Hi,

The information I have from the packaging vendor contains:
	self-inductance
	mutual inductance
	bulk-capacitance
	mutual capacitance
Where the "mutual" is to adjacent leads.

How do I map this to the L and C values in the package section of the
IBIS model ? Should I add them ?

Thanks,

	Eitan
	

Eitan Medina
Email: eitan@galileo.co.il
Galileo Technology Ltd.
15 Geron st. 
P.O.Box 2786
Yehud 56217
ISRAEL
Tel:   +972-3-6320220
Fax:   +972-3-6320221 
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
* check out our new web site:   http://www.GalileoT.com *
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 
From owner-ibis  Tue Aug  5 10:22:23 1997
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Date: Tue, 10 Dec 1996 13:28:06 -0500 (EST)
From: Dan Aleksandrowicz <dan@kaw.com>
Message-Id: <199612101828.NAA10094@kaw.com>
To: ibis@vhdl.org
Subject: Analog pin definitions

Hi,

I am working on a power supply IC which has some digital pins.

Though I have finished modeling and mapping the digital pins, I am not 
sure about the analog pins, which are not PWR or GND. 

The analog pins will not be simulated in a PCB simulation tool. Yet, I would 
like to know if there is any convention about assigning models for analog pins.

I have assigned an NC model so far.

Any suggestions?

Dan Aleksandrowicz
Engineering Solutions
KAW/USA
 
From owner-ibis  Fri Aug  8 10:32:52 1997
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Message-ID: <33EB5A44.4B17@pacbell.net>
Date: Fri, 08 Aug 1997 10:41:24 -0700
From: Jon Powell <jonp@pacbell.net>
Reply-To: jonp@pacbell.net
Organization: Viewlogic Consulting Services
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Subject: IBIS 3.0 and legal questions
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Hello All,

I sent this note out last week but evidently it didn't get out over the
reflector. I hoped to at least spark some controversy.

This is my feelings on IBIS 3.0 and releasing models in this format.

The copyright for the name IBIS is owned by EIA. Until 3.0 is approved
by that body, IBIS 3.0 does not exist. If anyone publishes models
claiming to be IBIS 3.0 then they are in violation of that copyright and
EIA will probably be forced to take action. 

Besides the legal implications, anyone publishing IBIS 3.0 models before
the official approval is almost certainly to be publishing models which
will NOT be correct. We had to change things to do 2.1 and we will
probably have to change things for 3.0. I will certainly not be putting
any "IBIS OFFICIAL 3.0" models into any of the IBIS data areas until
this specification is approved. I feel very strongly about this. I do
not want what happened to EDIF to happen to IBIS. If you recal, EDIF
(the earlier versions) was almost unusable because everyone had their
own dialect of the "standard" and it was virtually impossible to support
every dialect. At the same time, everyone claim to support EDIF. 

Perhaps we need some PRELIMINARY or EXPERIMENTAL designation for these
new models but we should NOT call them IBIS 3.0.

comments, of course, are solicited.
(but don't correct my spelling).

Jon Powell
Senior Scientist, Viewlogic Consulting Services.
IBIS Librarian

 
From owner-ibis  Fri Aug  8 12:34:19 1997
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Date: Fri, 8 Aug 1997 12:31:28 -0700 (PDT)
From: bob@icx.com ( Bob Ross)
To: ibis@vhdl.org
Subject: Re:  IBIS 3.0 and legal questions
Cc: jonp@qdt.com

Jon and IBIS Committee:

Thank you for raising a concern.  We actually discussed some aspects of it
in the IBIS Open Forum meeting.

I do not agree with portions of your position.

The only official IBIS Standard remains ANSI/EIA-656 of the IBIS Version 2.1
level which is copyrighted by EIA.  In compliance with the long standing
purposes of IBIS, EIA does not copyright or approve the models themselves
which are presented using the IBIS "template".  The model provider may 
optionally copyright the IBIS model using the [Copyright] keyword, NOT EIA.

Version 3.0 has been officially approved by the EIA/IBIS Open Forum - an 
offical EIA committee.  So it will stand as a "legally" APPROVED version of
the IBIS template.  As indicated in the Statement of Intent section, IBIS
Version 3.0 supports backward compatibility to all prior versions starting
with Version 1.0.  We intend to do editorial revisions to IBIS Version 3.0 in
conjunction with developing the IBIS Version 3.0 parser to put forth an IBIS
Version 3.1 release.  Version 3.1 will most likely be forwarded for formal
EIA ratification.  Only after ratification occurs will a new level of IBIS
OFFICIALLY be STANDARDIZED (along with or replacing ANSI/EIA-656.)  In
realilty, this process may take 6 months to a year (or more) based on the 
history of IBIS Version 2.0 (June 1994) to formal ANSI/EIA-656 evolution
(Dec. 1995).

In compliance with "Committment to Backward Compatibility", Version 3.1 will
support the features of Version 3.0.  The functionality and syntax of
Version 3.0 is official.

So I disagree with the first comment.  People may issue IBIS Version 3.0
formatted data in compliance (as best as they can) with the textual content
of the Version 3.0 document.  It will be a while before a parser will be
developed to check the syntax of the new items.  I support your second 
comment that there be strong messages (disclaimers, text, etc.) indicating
that OFFICIAL VERSION 3.0 compliance cannot be VALIDATED. - along with the
usual disclaimers regarding no responsibility for the consequences of using
the model (or the data contained within it).  I see no legal restriction in
using the IBIS Version 3.0 template.  The purpose of issuing the template is
to generate usage!

Bob Ross
Interconnectix



> Date: Fri, 08 Aug 1997 10:41:24 -0700
> From: Jon Powell <jonp@pacbell.net>
> To: ibis@vhdl.org
> CC: jonp@qdt.com
> Subject: IBIS 3.0 and legal questions

> Hello All,

> I sent this note out last week but evidently it didn't get out over the
> reflector. I hoped to at least spark some controversy.

> This is my feelings on IBIS 3.0 and releasing models in this format.

> The copyright for the name IBIS is owned by EIA. Until 3.0 is approved
> by that body, IBIS 3.0 does not exist. If anyone publishes models
> claiming to be IBIS 3.0 then they are in violation of that copyright and
> EIA will probably be forced to take action. 

> Besides the legal implications, anyone publishing IBIS 3.0 models before
> the official approval is almost certainly to be publishing models which
> will NOT be correct. We had to change things to do 2.1 and we will
> probably have to change things for 3.0. I will certainly not be putting
> any "IBIS OFFICIAL 3.0" models into any of the IBIS data areas until
> this specification is approved. I feel very strongly about this. I do
> not want what happened to EDIF to happen to IBIS. If you recal, EDIF
> (the earlier versions) was almost unusable because everyone had their
> own dialect of the "standard" and it was virtually impossible to support
> every dialect. At the same time, everyone claim to support EDIF. 

> Perhaps we need some PRELIMINARY or EXPERIMENTAL designation for these
> new models but we should NOT call them IBIS 3.0.

> comments, of course, are solicited.
> (but don't correct my spelling).

> Jon Powell
> Senior Scientist, Viewlogic Consulting Services.
> IBIS Librarian



 
From owner-ibis  Fri Aug  8 13:55:39 1997
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To: ibis@vhdl.org
Subject: IBIS 3.0 and legal questions
Date: Fri, 08 Aug 1997 13:54:24 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>



Hello All:

     I concur with Jon, at least as far as vendors publishing
model which are labled IBIS 3.0.  Specifically, the IBIS forum should
strongly discourage model vendors from publishing .ibs files with
"3.0" as the parameter to the [IBIS Ver] keyword, at least until the
spec has gone thru the ballot process (and ideally until the parser is 
developed).  My fear is the same as Jon's -- a model with 3.0 syntax will
almost certainly NOT be a correct IBIS 3.0 model.  If someone wants to publish
a model with 3.0 features, then I would suggest that they either leave 
the [IBIS Ver] blank, or put in something like PRELIMINARY or EXPERIMENTAL,
or give the file something other than an .ibs extension.

Comments, or course, are welcome, and (if you absolutly, positivly must)
you can correct my spelling :)


                    Regards,
                    Stephen Peters
                    Intel Corp.


>on  Fri, 08 Aug 1997 10:41:24 Jon Powell wrote:

Hello All,

I sent this note out last week but evidently it didn't get out over the
reflector. I hoped to at least spark some controversy.

This is my feelings on IBIS 3.0 and releasing models in this format.

The copyright for the name IBIS is owned by EIA. Until 3.0 is approved
by that body, IBIS 3.0 does not exist. If anyone publishes models
claiming to be IBIS 3.0 then they are in violation of that copyright and
EIA will probably be forced to take action. 

Besides the legal implications, anyone publishing IBIS 3.0 models before
the official approval is almost certainly to be publishing models which
will NOT be correct. We had to change things to do 2.1 and we will
probably have to change things for 3.0. I will certainly not be putting
any "IBIS OFFICIAL 3.0" models into any of the IBIS data areas until
this specification is approved. I feel very strongly about this. I do
not want what happened to EDIF to happen to IBIS. If you recal, EDIF
(the earlier versions) was almost unusable because everyone had their
own dialect of the "standard" and it was virtually impossible to support
every dialect. At the same time, everyone claim to support EDIF. 

Perhaps we need some PRELIMINARY or EXPERIMENTAL designation for these
new models but we should NOT call them IBIS 3.0.

comments, of course, are solicited.
(but don't correct my spelling).

Jon Powell
Senior Scientist, Viewlogic Consulting Services.
IBIS Librarian

 
From owner-ibis  Fri Aug  8 14:22:00 1997
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Date: Fri, 8 Aug 97 14:20:58 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9708082120.AA23151@rockie.nsc.com>
To: ibis@vhdl.org
Subject: Re: IBIS 3.0 and legal questions

To all:

A lot of hard work has gone into creating the v3.0 spec. A lot
of 'bad/corrupt' models can easily find their way into the
public domain if not parsed properly thru the v3.0 parser(..which
is coming soon..).

I personally think that the IBIS community should not encourage
IBISv3.0 model distribution unless the v3.0 parser is out/debugged
and approved.

If you must create a v3.0 model, do it and contain it between you
and your EDA vendor. Do not pass this to your customer or to
the public yet....An ASCII file without properly parsed will do
more harm than good.

Regards,
Syed
Vice-Chair ANSI/EIA-656
National Semiconductor Corp.
 
From owner-ibis  Fri Aug  8 15:10:45 1997
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From: "Leonard, Mark" <Mark.Leonard@COMPAQ.com>
To: "'ibis@vhdl.org'" <ibis@vhdl.org>
Cc: "'janderson@viewlogic.com'" <janderson@viewlogic.com>
Subject: RE: IBIS 3.0 and legal questions
Date: Fri, 8 Aug 1997 17:09:26 -0500
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I've read through the responses from tool and model suppliers, and the 
perspective from a model user is very different.  We're actively 
pursuing simulation information for devices, memory modules, processor 
modules, etc. that can only be accurately represented with v3.0 
syntax.  Our choices have been limited to the following: get the 
information directly in Quad Design format, exert pressure and get it 
in a painful combination of Spice and CAD (Allegro) formats, or don't 
get it at all.

It's quite interesting to note that Quad XTK models are becoming more 
readily available for most of the devices we care about.  It's also 
interesting to see some of our competitors being forced to switch 
simulation tools for this very reason.  I'm seeing buffer technologies 
continuing to advance, simulation engines advancing along with them, 
and the IBIS spec continuing to fall behind.  V3.0 catches up to where 
we are today, but it will be behind again in very short order.

The v3.0 spec has allowed us to start pushing the "don't get it at 
all" cases.  Accordingly we're starting to see v3.0 models.  I 
certainly wouldn't trust v3.0 models from just any vendor, but I some 
level of confidence in most of these guys.  From a user perspective I 
generally don't trust v3.0 models any more than I trust v2.1 models 
(assume they're of limited value until proven otherwise).  We still 
see a surprising number of v2.1 models with various problems (syntax, 
questionable data, etc.).

The lack of a v3.0 parser and tool-specific translators is forcing us 
to write our own.  We're left with no choice.

Mark Leonard
Manager, Signal Integrity & Package Analysis
Compaq Computer Corporation


-----Original Message-----
From:	c=US;a= ;p=COMPAQ;dda:ZID=<huq(a)rockie.nsc.com>;
Sent:	Friday, August 08, 1997 4:21 PM
To:	Leonard, Mark; c=US;a= ;p=COMPAQ;dda:ZID=<ibis(a)vhdl.org>;
Subject:	Re: IBIS 3.0 and legal questions

To all:

A lot of hard work has gone into creating the v3.0 spec. A lot
of 'bad/corrupt' models can easily find their way into the
public domain if not parsed properly thru the v3.0 parser(..which
is coming soon..).

I personally think that the IBIS community should not encourage
IBISv3.0 model distribution unless the v3.0 parser is out/debugged
and approved.

If you must create a v3.0 model, do it and contain it between you
and your EDA vendor. Do not pass this to your customer or to
the public yet....An ASCII file without properly parsed will do
more harm than good.

Regards,
Syed
Vice-Chair ANSI/EIA-656
National Semiconductor Corp.

 
From owner-ibis  Fri Aug  8 15:26:43 1997
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Date: Fri, 8 Aug 1997 15:25:27 -0700 (PDT)
From: Scott McMorrow <scottmc@teleport.com>
To: ibis@vhdl.org
Subject: Re:IBIS 3.0 and legal questions
Message-ID: <Pine.GSO.3.96.970808145237.263A-100000@kelly.teleport.com>
MIME-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII

To all:

I believe I have heard some of the silliest arguments
for not distributing IBIS 3.0 models today.

Anyone who has actually dealt with IBIS models from
semiconductor vendors (including Intel and National, among
others) knows that "parser problems" are the least of
our worries. I have personally used hundreds of models, most
of which passed the "golden parser", only to discover 
fundamental problems with the underlying data.  Often I/V
curves and waveform tables are incorrect.  Often the incorrect
units are used.  Often clamp curves are extracted improperly.

It is wonderful that the IBIS committee has gotten to the point 
of publishing the version 3.0. specification.  If we wait for
a 3.0 golden parser ( which, by the way, is an aid to checking
compliance with the specification, not the specification itself),
we in the design community will be waiting for another year.  
The argument that the specification will change in the future does
not hold water.  All specifications change over time. It is 
through "real life" experience with using the results of a 
specification that is the impetus to change.

Currently, the design community requires the ability to model
multistage drivers, complex series elements, and modules.  There
is no way in IBIS 2.1 to perform these modeling tasks.  There is
currently no common public way to distribute this silicon and
packaging information amongst the design community.  We have a crisis
for designs trying to achieve 100Mhz and above bus speeds with
complex products in increasingly shortening design times.  Yet
members of the IBIS committee (and specifically representatives of
the companies that need to provide this sort of data to customers)
are afraid to release information because the specification (which
they approved) could somehow be imperfect.

Guess what?  All specifications are imperfect!  However, an imperfect
3.0 specification is far superior to a perfect IBIS 2.1 specification.
What I need as a designer is data from which I can model and 
analyze my boards and chips.  I choose to receive this data in the
IBIS 3.0 format.  I choose to receive it as soon as possible.  I
believe that most designers who actually design boards for a living
would rather have the best design information that they can have 
right now.

Semiconductor vendors, please get off the stick and provide IBIS
3.0 compliant models today.  It would be irresponsible and 
inexcusable ( that is, unless you want to impede progress) to do 
anything otherwise.  If you wish, use the IBIS Disclaimer field
to qualify the preliminary status of your models.  The field
is already used to disclaim the suitability of the models for
any purpose anyway.

I hope that other boards designers and consumers of IBIS models
will also speak up.  I look forward to your comments.


scottmc@teleport.COM 

 
From owner-ibis  Wed Aug 13 09:27:06 1997
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Message-Id: <199708131621.JAA20076@ichips.intel.com>
To: ibis@vhdl.org
Subject: IBIS Teleconference Minutes  8/8/97
Date: Wed, 13 Aug 1997 09:21:56 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>



 DATE: August 13, 1997

 SUBJECT: 8/8/97 EIA IBIS Open Forum Minutes
  
 VOTING MEMBERS AND 1997 PARTICIPANTS LIST:
 AMP                            Jeff Walden
 Applied Simulation Technology  [Dileep Divekar], Norio Matsui, Raj Raghuram,
                                Fred Balistreri*
 Cadence Design & UniCAD        C. Kumar, Don Telian, Cameron Seitz
 Cypress                        Bruce Wenniger
 Digital Equipment Corp.        Jeff Chu*
 High Design Technology         (Razvan Ene)
 HyperLynx                      Kellee Crisafulli, Steve Kaufer, Matt Flora*
 INCASES                        Olaf Rethmeier*, Werner Rissiek
 Intel Corporation              Stephen Peters*, Arpad Muranyi*, Henry Maramis,
				Will Hobbs, Frank Kern*
 Interconnectix                 Bob Ross*
 Mitsubushi                     Tam Cao, Hoang Nguyen
 Motorola                       [Ahmed Omer], Michael Desiderio, Paul Bolden,
                                Tom Myers, Rob Wenzel*
 National Semiconductor         Syed Huq*, Cheng-Yang Kao, Mike Bristol,
				Peter Laflamme, Kevin Smith
 NCR                            Dave Moxley, Richard Mellitz
 NEC                            (Hiroshi Matsumoto)
 Quantic EMC                    (Mike Ventham)
 Texas Instruments              Thomas Fisher
 Thomson-CSF/SCTF               (Jean LeBrun)
 Viewlogic                      Jon Powell, Chris Rokusek*, Peivand Tehrani
 VeriBest                       Ian Dodd, William Bell
 VLSI Technology                Harish Patel, D.C. Sessions
 
 OTHER PARTICIPANTS IN 1997:
 3M                             [Fran Hart]
 Actel                          Scott Schlachter
 Acuson & Free Model Foundation Richard Munden
 Alcatel                        John Fitzpatrick
 Ansoft                         Eric Bogatin
 Apteq Design Systems           Dan FitzPatrick 
 Compaq                         Weston Beal, Mark Leonard
 Dell Computer                  Dave Baranauskas*, Doug Wallace*
 EIA                            Patti Rusher*
 EMC                            Fabrizio Zanella
 Hewlett Packard, EEsof         Karl Kachigan, Henry Wu
 Hewlett Packard, France        Jean-Christophe Pautrat
 Hitachi                        Saburo Hojo, Yasushi Ogawa 
 IBM                            Brad Herrman
 Interface Technology           Dan Waterloo 
 Micron Technology              Brian Johnson                      
 Molex                          Gus Panella
 North Carolina State U.        (Michael Steer)
 S3, Inc.                       Porsh Shih, Sarathy Sribhashyam
 Symmetry                       Andy Hughes
 TRW                            Ray Steele
 Ultratest International        Charles Im
 Zeelan Technology              George Opsahl 

 In the list above, attendees at the meeting are indicated by *.  Principal
 members or other active members who have not attended are in parentheses.
 Participants who no longer are in the organization are in square brackets.

 Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
 follows:
     
   Date               Bridge Number     Reservation #    Passcode
   September 5, 1997  (916) 356-9200    2-177650          2591118

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each Open Forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.

 -------------------------------- MINUTES -------------------------------------

 INTRODUCTIONS AND MEETING QUORUM
 The following new participants introduced themselves:

 Fred Balistreri of Applied Simulation Technology was involved in the early
 development of IBIS and expressed his company's continued interest in IBIS.
 Raj Raghuram will be the representive calling in to replace long term 
 representative Dileep Divekar.

 Matt Flora just joined Hyperlynx is and responsible for IBIS model developemnt
 and the Visual IBIS Editor.

 Frank Kern of Intel is with the XTG Group responsible for issuing new 
 generation IBIS (and Quad) models and also supports the hardware team
 using IBIS models to convey information.  He expressed concern regarding
 no Version 3.0 Golden Parser to validate IBIS models.

 Rob Wenzel of Motorola just joined to replace Ahmed Omer and will be suporting
 internal Spice to IBIS conversions.

 Dave Baranauskas (and later Doug Wallace) called from Dell Computer.  Dave has
 several years experience using IBIS.  His interest is to leverage IBIS for
 Signal Integrity and timing issues.  He expressed a strong vested interest
 in IBIS and in requiring IBIS models for semiconductor vendors.  (Dave
 verified Fran Hart formerly with 3M is with Dell.)


 MEMBERSHIP UPDATE AND TREASURER'S REPORT
 Patti Rusher reported no membership change.  She reported committee income
 of $11,750 and an existing net of $5,272 (down from $9,433 from the last
 minutes after some DAC expenses, reprint purchases, and other expenses.  Bob
 Ross questioned whether credit was given for the latest official member.


 REVIEW OF MINUTES AND AR'S
 No Corrections.

 Stephen Peters reviewed the AR's.  The major outstanding ones are for
 examples for the Cookbook and BIRDs and will be carried forward.


 MISCELLANY/ANNOUNCEMENTS
 Bob Ross reported everyone is back from vacation and thanks Stephen Peters
 and Syed Huq for helping out with the system administration tasks.

 Congratulations to Stephen Peters for the new addition Spencer James Peters.


 PRESS AND WEB PAGE UPDATES
 Bob Ross reported that Howard Johnson's May 1997 Electronic Design article
 which references IBIS is availble from his site under Straight Talk for Serious
 Digital Designers, "Planning for Signal Integrity" under http://www.sigcon.com.

 Syed Huq reported on some EIA/IBIS Web page changes including roster updates
 and Version 3.0 access.


 NEW MODELS AVAILABLE, LIBRARY UPDATE
 Bob Ross notes that these Web sites have added models:

   Cypress Semiconductor has added many more IBIS model for FCT octals and
   16 bit logic, SRAMs, Programmable Logic, and Programmable Skew Clocks.

   IDT, Motorola and Texas Instruments have added IBIS models.


 OPENS FOR NEW ISSUES
 Bob Ross - East Coast IBIS Users Group Meeting
 Patti Rusher - EIA Matters - Budget, Design Automation 98 Booth.


 EAST COAST IBIS USERS GROUP
 Bob Ross reported that Dr. Ed Sayre of North East Systems Associates (NESA)
 is investigating hosting an East Coast IBIS Users meeting in Massachusettes.
 The tentative date will be Thursday, September 18, 1997 since Bob and others
 will be at the PCB East conference on September 17.  Bob suggested Ed send out
 information on the IBIS reflectors to see who might be interested.  The agenda
 or topics still needs to be developed.


 EIA IBIS MATTERS
 Pattie Rusher indicated that we need to work with EIA concerning next years
 budget to cover some anticipated Writer/Developer expenses.  Pattie will not
 be at the PCB East Conference, but will be in a Tokyo IEC meeting.  The
 EIA/IBIS committee plans to participate in the DAC98 Standards Booth.  The
 price/level of committment has not been determined since the possibility of
 having actual IBIS demonstrations means more booth space alocation.  This
 would also have to be considered in the budgeting discussions.
 

 INTERNATIONAL PROGRESS
 - 93/46/NP (IBIS Version 2.1) - Pattie Rusher will check the status at a
   meeting on August 21, 1997 prior to the Tokyo meeting.

 - 93/60/NP (IBIS Models and EMC Simulation) - Pattie will check the status
   at the Tokyo meeting through contacting Jean LeBrun, the IEC subcommittee
   chairman.

 - EIAJ III (I/O Interface Model for ICs - Bob Ross reported no know progress,
   but based on the presentations at the IBIS Summit, we can expect another
   release in September along with a Package Committee release.  Fred Balistreri
   reports that simulation algorithms have been incorporated and some models
   have been developed.
 

 EDITING COMMITTEE 
 Stephen Peters reported no further progress on editing IBIS Version 3.0 for
 clarity since Bob Ross and Stephen were out.  Bob reviewed briefly that the
 intent was to make IBIS Version 3.0 more readable by considering doing the
 following:

    Table of Contents and Section/Chapter headings
    Consistency of Words as suggested by Ogawa-san of the EIAJ subcommittee
    Tree diagram
    BNF Syntax
    Some Cookbook details added.
    Clarifications (BIRD44, etc.)

 Bob and Stephan still plan a first pass to be put in the work in progress
 directory (wip).

 After this first pass is completed, several issues will be addressed:

    Format - Syed Huq feels that a format other than ASCII text such as Word,
             HTML, Postscript will allow better graphics and presentation
    Professional Support - Use a professional writer.
    Editing Meeting - Set up a committee for an all day meeting.

 The existing AR is still in effect and a new one is added for Stephen and Bob
 to generate a first pass editorial review copy.

 AR - Bob Ross generate and post a BNF for IBIS Version 3.0 (and IBIS Version
 3.0 ratification AR).

 AR - Stephen Peters and Bob Ross generate an editorial revision of Version 3.0
 and place it in the eda.org/pub/ibis/wip directory.


 VERSION 3.1 PARSER
 Four individuals responded to Stephen Peters' request for development posting.
 Bob Ross suggested that Stephen, Bob and Syed Huq review the candidates and
 issue a request for a bid regarding time/money based on the scope of the
 project.  Chris Rokusek emphasized that the development should start and be
 based on the existing ibischk2+ source code with some data checking messages.
 He also stated that the existing messages be retained because they are used
 in some system. 

 In response to a question, Bob stated that there is no further ibis_chk (for
 Version 1.1 or ibischk2+) development planned.  Bug8 deferred one correction
 that existed in all parsers until Version 3.0 development.

 Syed Huq brought up the fact that some of the candidates may need to review
 the source code to provide the bid.  Bob Ross agreed and would plan to 
 provide the source code for the purposes of providing a bid only.

 Mike Flora asked how to get the ibischk2+ source code and Bob responded that
 companies (such as Hyperlynx) who have paid for the licence can get it
 directly from Bob Ross or Chris Rokusek.

 AR - Bob Ross, Stephen Peters, and Syed Huq consider the candidates and issue
 a document for the selected candidates to provide a time/money bid for the 
 ibischk3 parser development project.


 LEGAL IBIS VERSION 3.0 FILES
 Chris Rokusek indicated that Jon Powell had concerns about the legality of
 producing IBIS Version 3.0 file with having a parser to validate them and
 without formal EIA ratification of IBIS Version 3.0.  This generated a long
 discussion and debate.  Some issues related to whether the files should be
 marked PRELIMINARY or EXPERIMENTAL in place of 3.0 for the [IBIS Ver]
 keyword.  Bob felt that the Version 3.0 format was official, so it is legal
 to generate IBIS Version 3.0 files.  However, the consensus of everyone was
 to support adding some warning/disclaimer text to alert the user that the
 files were not officially validated and could have syntax errors.

 One commentor stated that even with the IBIS Version 2.1 parser, half of the 
 public IBIS files have bad syntax or data.  Patti Rusher reviewed the
 anticipated steps to reach standardization - Version 3.1 with editorial 
 review and parser completion (hopefully), then submit to EIA for a 2 month
 letter ballot review.  Based on a successful review and response to the
 contents, EIA would then ratify the document as a new Standard.

 Chris indicated that Jon will post a note on the subject to clarify his
 position and initiate discussion.


 COOKBOOK
 Stephen Peters reported that he has not received any examples.  The AR's are
 still pending below.  He would use the examples and augment them with comments.
 Stephen also mentioned that Frank Kern plans to add a mostly tutorial section
 explaining the structure (IV, VT data) and its rationale with respect to
 using behavioral models.  

 Stephen raised the question whether the preliminary version of the Cookbook
 should be made available.  After some discussion, the concensus was that
 it is a very useful document even at this early stage.  We need clear
 indication that this is preliminary and updates should be tracked by version
 number. Two ARs were generated to for this to occur.  All existing example
 AR's are carried forward.

 AR - The following people have volunteered to supply examples
  Steve Kaufer/Hyperlynx -- Example 1
  Arpad Muranyi - Example 2
  Stephen Peters - Example 3 

 AR - D.C Sessions.  Supply a paragraph or two explaining the best way to
 modify a SPICE transistor model to get realistic power and ground clamp 
 information

 AR - Bob Ross.  Supply the text for the section "Diode Transient Time Data"

 AR - Syed Huq.  Review and expand (if necessary) Section 3.3. on "Obtaining
 I/V and Switching Information via Lab Measurement".

 AR - Bob Ross submit an example of a Series MOSFET component.

 AR - Stephen Peters with Bob Ross put a copy of the Cookbook in the
 eda.org/pub/ibis/wip directory after appropriate Version number and 
 preliminary disclaimers are added.

 AR - Syed Huq provide a link to access the Cookbook document from the official
 EIA/IBIS Web Site when the Cookbook is uploaded.

 
 S2IBIS2 ISSUES (& NT)
 Bob Ross reported that the NT versions of s2ibis have not yet been put on
 the VeriBest Web site.  So the AR is still active.

 AR - Ian Dodd put s2ibis_ver1.3 and s2ibis_ver2.1 for Windows on the VeriBest
 Web site.

 
 BIRD42.3 - MODELING CURRENT WAVEFORMS
 Bob Ross summarized the status of BIRD42.3.  It was not approved at the June
 IBIS ratification meeting because of some controversial aspects.  There was no
 further discussion.  The AR is still considered open.

 AR - D.C. Sessions and Kumar get together and provide an example showing
 where the rising and falling waveform tables do not result in correct
 results.


 BIRD44 - INTERPRETATION OF MIN/MAX/WEAK/STRONG DATA
 Bob Ross proposed that BIRD44 be put in the Editorial Committee portion of the
 Agenda since it is an editorial clarification.  As discussed at the previous
 meeting, the contents of BIRD44 will be taken into account as part of the
 first editorial pass of Version 3.0.  It will continue to remain open.


 SWITCHING TERMINATORS
 Arpad Muranyi has no further work in this area, but now has more time to work
 on it.

 In response to a question by Dave Baranauskas regarding whether this was an
 extension of the IBIS scope, Arpad indicated that the funtionality was not for
 a new type of terminator, but was for some internal I/O buffer electrical
 characterization that is new.  (Some overview discussions are on the FTP sight
 under summits for the January 1997 IBIS Open Forum Summit meeting.)


 MISCELLANEOUS DISCUSSION
 The technical content of the meeting was concluded ahead of schedule.  Bob
 Ross opened the meeting up to discussions and questions on all subjects.

 As indicated above, the presentations of several previous IBIS Summits where
 the focus was primarily information presentations are available at the eda.org
 site (same as vhdl.org): http://www.eda.org/pub/ibis/summits.  They are also
 available using anonymous FTP at this location.

 The BIRD (Buffer Issue Resolution Document) process was reviewed by Bob and
 Arpad Muranyi as the method used by the committee to revise the standard.
 A key aspect is that we will argue solid proposals based on the wording of
 the proposed revision.  BIRDs go through revisions based on the discussions.
 They are available from the eda.org/pub/ibis/birds site and through other
 links.

 Dave Baranauksas asked for more details on the French IBIS Modeling and EMC
 proposal and Bob responded that he was seeking details as well.

 Dave also asked about the EIAJ III work since he had received the synopsys
 document from Fred Balistreri.  Bob and other discussed aspects of this
 proposal including the fact the transistor devices were based on the source
 table information.  This is more accurate than the (arbitrary level) equation
 data, but does not give some parameter sensitivites (such as temperature)
 that are taken into account in the assumed equations.


 NEXT MEETING:
 The next meeting is on Friday, September 5, 1997, 8:00 A.M. to 9:55 A.M.
 following the Labor day weekend.
 ==============================================================================
				       NOTES
 
 IBIS CHAIR: Bob Ross (503) 603-2523, Fax (503) 639-3469
	     bob@icx.com
	     Modeling Engineer, Interconnectix
	     10220 SW Nimbus Ave, K4, Portland, OR 97223

 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785
	     huq@rockie.nsc.com
	     Staff Applications Engineer, National Semiconductor, M/S A-2595
	     2900 Semiconductor Drive, Santa Clara, CA 95052
 
 SECRETARY:  Stephen Peters (503) 264-4108, Fax: (503) 264-4515
	     sjpeters@ichips.intel.com
	     Senior Hardware Engineer, Intel Corporation
             M/S JF1-56
	     2111 NE 25th Ave. 
             Hillsboro, Oregon 97124-5961

 LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
	     jonp@qdt.com
	     Senior Scientist, Viewlogic (formerly Quad Design)
	     1385 Del Norte Rd., Camarillo, CA 93010
  
 This meeting was conducted in accordance with the EIA Legal Guides and EIA
 Manual of Organization and Procedure.
 
 The following e-mail addresses are used:

   ibis-request@vhdl.org
       To join, change, or drop from either the IBIS Open Forum Reflector
       (ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org)
       or both.  State your request.

   ibis-info@vhdl.org
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   ibis@vhdl.org
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.  Job posting information is not permitted.

   ibis-users@vhdl.org
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.  Job posting information is not permitted.

   ibischk-bug@vhdl.org
       To report ibischk2 parser bugs.  The Bug Report Form Resides on
       vhdl.org in /pub/ibis/bugs/bugform.txt along with reported bugs.

 Information on IBIS technical contents, IBIS participants, and actual
 IBIS models are available on the IBIS Home page found by selecting the
 Electronic Information Group under:

   http://www.eia.org

 Check the pub/ibis directory on vhdl.org for more information on previous 
 discussions and results.  You can get on via FTP anonymous.
 
 "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for 
 use at trade shows.
 ==============================================================================





 
From owner-ibis  Wed Aug 20 12:41:01 1997
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Sender: dc.sessions@tempe.vlsi.com (D.C. Sessions)
Message-ID: <33FB4752.1F5A@tempe.vlsi.com>
Date: Wed, 20 Aug 1997 12:36:50 -0700
From: "D. C. Sessions" <dc.sessions@tempe.vlsi.com>
Organization: VLSI Technology Inc.
X-Mailer: Mozilla 3.0Gold (X11; I; SunOS 5.5.1 sun4m)
MIME-Version: 1.0
To: IBIS Mailing list <ibis@vhdl.org>
Subject: CMOS drain diodes
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

We use a pretty simple method to correct the parasitic
diode models for our HSPICE decks prior to doing the
IBIS extraction.

First, we replace each MOS transistor with a subcircuit
having similar characteristics and parameters; this is
handled by an AWK script:

#! /usr/local/bin/gawk -f 
BEGIN	{
	  IGNORECASE	= 1
	  }

/^M/	{
	  if( $6 ~ /^p$/ )
	    {
	      $6	= "pdt"
	      sub( /^M/, "Xmd_", $1 )
	      }
	    else if( $6 ~ /^n$/ ) {
	      $6	= "ndt"
	      sub( /^M/, "Xmd_", $1 )
	      }
	    else if( $6 ~ /^y$/ ) {
	      $6	= "ndt"
	      sub( /^M/, "Xmd_", $1 )
	      }
	    for( f = 6; f <= NF; f++ ) {
	      sub( /^L=/, "Ltc=", $f )
	      sub( /^W=/, "Wtc=", $f )
	      }
	    }
	  {
	    print
	    }

The library includes the subcircuit file for the
transistor models:

.SUBCKT	ndt	drain	gate	source	bulk
+	AS=0	AD=0	PS=0	PD=0

M1	drain	gate	source	bulk	N	L=Ltc	W=Wtc	GEO=3
*+	AS=0	AD=0	PS=0	PD=0
Dbs	bulk	drain	NDIO	AREA=AD	PJ=PD
Dbd	bulk	source	NDIO	AREA=AS	PJ=PS

.ENDS	ndt

.SUBCKT	pdt	drain	gate	source	bulk
+	AS=0	AD=0	PS=0	PD=0

M1	drain	gate	source	bulk	P	L=Ltc	W=Wtc  GEO=3
*+	AS=0	AD=0	PS=0	PD=0
Dbs	drain	bulk	PDIO	AREA=AD	PJ=PD
Dbd	source	bulk	PDIO	AREA=AS	PJ=PS

.ENDS	pdt

... which results in the area and sidewall parasitics
for the MOS devices being zeroed out (thus zeroing their
diode currents and parasitic capacitances) and in
their places are explicit diode models (NDIO and PDIO)
which have improved V/I matching and capacitances.

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com
 
From owner-ibis  Thu Aug 21 22:37:01 1997
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Date: Fri, 22 Aug 1997 07:35:15 +0200
From: Schneider Walter <schwa1@fh-landshut.de>
Organization: Fachhochschule Landshut
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Hello!

I'm trying to create an ibis-model for the tms320c31 (digital signal
processor  132 pin PQFP package).
Who can help me in creating such a model?

I don't know how to group the signals into appropriate groups for
ibis. Besides has anyone an idea how to test an ibis model for the
tms320c31  (pspice simulation with this model  -  against measure-
ments on a board with the tms320c31)?

Thank you!

mail:   Walter Schneider
        Muehlweg 25
        94513 Schoenberg
        Germany

email:  schwa1@fh-landshut.de
 
From owner-ibis  Mon Aug 25 07:54:33 1997
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From: Paul Gregory <pgregory@hpbs2933.boi.hp.com>
Message-Id: <9708251451.AA09549@hpbs2933.boi.hp.com>
Subject: PCI IBIS model
To: ibis@vhdl.org
Date: Mon, 25 Aug 97 8:51:36 MDT
Cc: pgregory@boi.hp.com (Paul Gregory)
Mailer: Elm [revision: 70.85]

I am looking for an IBIS model of a PCI spec compliant device.  I am working
with PCI v2.1 and IBIS v2.1. I would like a model that matches the min and
max requirements for a 3.3v system, assuming Vcc min =3.0 and Vcc max = 3.6
as specified in the spec.  I am not looking for a specific device 
implementation, but a generic PCI min/max device.

Is such a model already available, or do I need to create it myself?

 -- Paul Gregory

   phone: (208) 396-5086               USmail: Hewlett-Packard
     fax: (208) 396-4122                       M/S 143
   email: paul_gregory@hp.com                  11311 Chinden Blvd.
                                               Boise, ID  83714
 
From owner-ibis  Mon Aug 25 10:49:11 1997
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From: Paul Gregory <pgregory@hpbs2933.boi.hp.com>
Message-Id: <9708251746.AA10180@hpbs2933.boi.hp.com>
Subject: Re: PCI IBIS Model
To: ibis@vhdl.org
Date: Mon, 25 Aug 97 11:46:26 MDT
Cc: pgregory@boi.hp.com (Paul Gregory)
Mailer: Elm [revision: 70.85]


I apologize for not making my request more clear the 
first time.

Rather than a specific PCI implementation, I am looking for 
a PCI IBIS model that models exactly the PCI spec, that is, 
the v/i curves (and other sections) track exactly along the 
lines of the spec limits.  Usually any PCI implementation will 
be between the min/max boundaries; I want a model that is 
exactly on the boundaries. I would like a model that includes 
ramps, diodes, pull up/down, and comp/pkg parameters. Am I 
missing other parts of the model that should be in it?

Thanks for your help.

 -- Paul Gregory

   phone: (208) 396-5086               USmail: Hewlett-Packard
     fax: (208) 396-4122                       M/S 143
   email: paul_gregory@hp.com                  11311 Chinden Blvd.
                                               Boise, ID  83714
 
From owner-ibis  Mon Aug 25 13:12:21 1997
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Date: Mon, 25 Aug 97 15:50:23 EDT
From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
To: pgregory@hpbs2933.boi.hp.com
Cc: ibis@vhdl.org, ingraham@wrksys.ENET.dec.com
Apparently-To: ibis@vhdl.org, pgregory@hpbs2933.boi.hp.com
Subject: Re: PCI IBIS Model

I'm sure someone must have made one by now.  PCI devices are described
in the PCI spec in terms of V/I curves, which would make them ideal
for IBIS representation.  95% of it should be trivial.

>                            I would like a model that includes 
> ramps, diodes, pull up/down, and comp/pkg parameters. Am I 
> missing other parts of the model that should be in it?

Don't forget ramp (slew) rates.

You might want a couple of different models, since the overshoot clamp
diode in 5V PCI is optional.  One with the diode, one without.

Regards,
Andy
 
From owner-ibis  Mon Aug 25 19:27:45 1997
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9708252030.AA28357@rockie.nsc.com>
To: ibis@vhdl.org
Subject: New IBIS models from National
Cc: huq@rockie.nsc.com

IBIS fans,

National Semiconductor's Personal Systems Group has
released the following two Super I/O IBIS models on
it's web site:

pc87307.ibs
pc97307.ibs

The URL is:

http://www.national.com/models

Select 'IBIS' and then 'SuperI/O'

Best Regards,
Syed
Vice-Chair ANSI/EIA-656
National Semiconductor Corp.
 
From owner-ibis  Mon Aug 25 20:03:30 1997
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From: "Mellitz, Richard" <mellitz@xgate.columbiasc.ncr.com>
To: "'ibis@vhdl.org'" <ibis@vhdl.org>,
        "'Paul Gregory'"
	 <pgregory@hpbs2933.boi.hp.com>
Cc: "'pgregory@boi.hp.com'" <pgregory@boi.hp.com>
Subject: RE: PCI IBIS Model
Date: Mon, 25 Aug 1997 23:01:10 -0400
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Encoding: 43 TEXT

>Paul,
>
>Making an I/V curve track the maximum and minimum curves may not give you the
>corners of performance you are looking for. Instantaneous impedance, dv/di
>could theoretically be open or short. i.e. rho = +/- 1. What I've done is
>look at various chip mfgs i/v curves and make a composite of the corners.
>Incidently I only need to go to this extreme if I'm pushing reccomended PCI
practices...else I just use the models that come with Hspice. 

You also need to make some calls on the wave shape even though there are
>spec's on slew.
>
>... Richard Mellitz, NCR
>
>----------
>From: 	Paul Gregory[SMTP:pgregory@hpbs2933.boi.hp.com]
>Sent: 	Monday, August 25, 1997 12:46 PM
>To: 	ibis@vhdl.org
>Cc: 	pgregory@boi.hp.com
>Subject: 	Re: PCI IBIS Model
>
>
>I apologize for not making my request more clear the 
>first time.
>
>Rather than a specific PCI implementation, I am looking for 
>a PCI IBIS model that models exactly the PCI spec, that is, 
>the v/i curves (and other sections) track exactly along the 
>lines of the spec limits.  Usually any PCI implementation will 
>be between the min/max boundaries; I want a model that is 
>exactly on the boundaries. I would like a model that includes 
>ramps, diodes, pull up/down, and comp/pkg parameters. Am I 
>missing other parts of the model that should be in it?
>
>Thanks for your help.
>
> -- Paul Gregory
>
>   phone: (208) 396-5086               USmail: Hewlett-Packard
>     fax: (208) 396-4122                       M/S 143
>   email: paul_gregory@hp.com                  11311 Chinden Blvd.
>                                               Boise, ID  83714
>
 
From owner-ibis  Thu Aug 28 15:18:50 1997
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Date: Thu, 28 Aug 1997 15:14:07 -0700
From: "D. C. Sessions" <dc.sessions@tempe.vlsi.com>
Organization: VLSI Technology Inc.
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MIME-Version: 1.0
To: Bob Ross <bob@icx.com>
CC: IBIS Mailing list <ibis@vhdl.org>
Subject: Re: VLSI IBIS Models
References: <m0x3nPG-000GkJC@bob.icx.com>
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Bob Ross wrote:
> 
> D. C.
> 
> It looks like VLSI has taken the IBIS models off of the
> VLSI page.  Do you know anything about this?

I managed to chase it down.  I'm copying this to the list
because we owe everyone an apology.  Here's what happened:

Recently, one of our VIPs noticed that the published library
of modeled parts consisted entirely of out-of-production
devices.  (One of the consequences of a rapidly-changing
industry and the takeover of the chipset & PC motherboard
business by a single company.)   So, by management decision,
we pulled the chip-level models.

At present, we have device-level IBIS models for all of our
standard cell I/O libraries, and are producing chip-level
IBIS models for customers' chips.  We're currently
discussing the best way to publish the standard-cell IBIS
models; one camp is in favor of CD-ROM inclusion along with
the libraries, while another wants to put them on the
corporate WWW page.  When there's a decision I'll let you
know.

Once again, I apologize for not notifying the group when we
pulled our model site.
.

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com
 
From owner-ibis  Fri Aug 29 07:49:18 1997
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Date: Fri, 29 Aug 1997 07:46:26 -0700
From: Jon Powell <jonp@pacbell.net>
Reply-To: jonp@pacbell.net
Organization: Viewlogic Consulting Services
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Fellow Ibisians,

The IBIS model website (accessible off of eia.org) has been updated.

New models have been referenced from MOTOROLA and IBM.

The VLSI reference has been deleted as it is no longer active. VLSI has
no data as to when they may re-activate their site.

As always, these external models have not been officially reviewed by
the IBIS committee.

aviarily yours,
Jon Powell
Ibis Librarian.

 
From owner-ibis  Fri Aug 29 08:45:01 1997
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All,

In IBIS model, how to model the Bi-direction pins?
The situation is that I have an output buffer that
contains an input buffer as well. There is only
one buffer can be actived at one time. So, I am
not so sure which buffer's model should I put
for the pin.

-- 
Best Regards,

			Vincent Chang
			

=======================================================================
*  Vincent Chang                         TI MSG ID: hui8              *
*  Design Automation                     mailto:vchang@memh.ti.com    *
*  Memory Products Design                http://www.memh.ti.com/~mcad *
*  Texas Instruments Inc. MS 657         Phone: (281) 274-3167        *
*  PO Box 1443, Houston, TX 77251        Fax:   (281) 274-2067        *
=======================================================================
 
From owner-ibis  Fri Aug 29 10:25:01 1997
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Date: Fri, 29 Aug 1997 10:23:25 -0700 (PDT)
From: bob@icx.com ( Bob Ross)
To: ibis@eda.org
Subject: IBIS Meeting Agenda 9/5/97

                       IBIS Open Forum Meeting Agenda 
                                for 9/5/97

                  Bridge Number    Reservation #   Passcode
                  (916) 356-9200   2-177650        2591118

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
 meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
 Reservation Number and Passcode.
 
 8:00 Check-In, Intros, Announcements                         Ross

      - Intros of New IBIS Participants, Meeting Quorum       Ross
      - Membership Update and Treasurers Report               Rusher
      - Review of Previous Meeting's Minutes (and ARs)        Peters
      - Miscellany/Announcements                              All
      - Press & Web Page Updates                              Huq, All
      - New Models Available, Library Update                  Powell, All
      - Opens for New Issues                                  All

 8:25 Administrative and Project Discussions

      International Progress                                  Rusher/Ross
      - 93/46/NP (IBIS Version 2.1)
      - 93/60/NP (IBIS Models and EMC Simulation)
      - EIAJ III (I/O Interface Model for ICs)

      East Coast IBIS Users Meeting                           Ross

      Editing Committee                                       Ross/Peters
      BIRD44 Interpretation of Min/Max/Weak/Strong Data       Ross

      Version 3.1 Parser                                      Ross
      - Funding and Budget
      - Version 3.0 Models Issue

      Cookbook                                                Peters
      - Examples

      New Administrative Issues                               All

 8:50 Technical Discussion
 
      BIRD42.3 Modeling Current Waveforms                     Kumar/Ross

      Switched Terminators                                    Muranyi

      New Technical Issues                                    All

 9:50 Wrap Up and Next Meetings Plans                         Ross

 9:55 Sign Off
 







 
From owner-ibis  Fri Aug 29 12:19:47 1997
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All,

In ibis model, the package is not be used on simulation. Why?

-- 
Best Regards,

			Vincent Chang
			

=======================================================================
*  Vincent Chang                         TI MSG ID: hui8              *
*  Design Automation                     mailto:vchang@memh.ti.com    *
*  Memory Products Design                http://www.memh.ti.com/~mcad *
*  Texas Instruments Inc. MS 657         Phone: (281) 274-3167        *
*  PO Box 1443, Houston, TX 77251        Fax:   (281) 274-2067        *
=======================================================================
 
From owner-ibis  Fri Aug 29 13:22:52 1997
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Message-ID: <Fri, 29 Aug 97 13:17:22 PDT_2@ccm.fm.intel.com>
To: ibis@vhdl.org
Subject: Re: package and die


Text item: 

Vincent,

Where did you get this idea from?

Arpad Muranyi
Intel Corporation
=================================================================

All,

In ibis model, the package is not be used on simulation. Why?

--
Best Regards,

               Vincent Chang


=======================================================================
*  Vincent Chang                         TI MSG ID: hui8              *
*  Design Automation                     mailto:vchang@memh.ti.com    *
*  Memory Products Design                http://www.memh.ti.com/~mcad *
*  Texas Instruments Inc. MS 657         Phone: (281) 274-3167        *
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Subject: package and die
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