From owner-ibis Wed Feb 5 16:50:17 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id QAA00430 for ; Wed, 5 Feb 1997 16:50:12 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Wed, 5 Feb 97 16:29 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 5 Feb 97 16:29 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 5 Feb 97 16:31 PST Message-Id: Date: Wed, 5 Feb 97 16:31 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS Summit Minutes January 20, 1997 Cc: fukuda@hitachi-mc.co.jp DATE: February 5, 1997 SUBJECT: 1/20/97 EIA IBIS Summit Minutes, Santa Clara, California. VOTING MEMBERS AND 1997 PARTICIPANTS LIST: AMP (Ray Ziesse), Jeff Walden* Applied Simulation Technology Dileep Divekar*, Norio Matsui* Cadence Design C. Kumar*, Don Telian* Cypress Bruce Wenniger* Hewlett Packard, EEsof Karl Kachigan*, Henry Wu* HyperLynx Kellee Crisafulli* INCASES (Olaf Rethmeier) Intel Corporation Stephen Peters*, Arpad Muranyi*, Interconnectix (Bob Ross) Meta-Software (Sanjay Gangal) Mitsubushi Tam Cao* Motorola Ahmed Omer National Semiconductor Syed Huq*, Cheng-Yang Kao*, Mike Brisbi* Peter Laflamme*, Kevin Smith*, NCR (Dave Moxley), Richard Mellitz* NEC (Hiroshi Matsumoto) Quad Design Jon Powell*, Chris Rokusek* Quantic Laboratories (Mike Ventham) Texas Instruments (Sri Jandhyala), Thomas Fisher* Thomson-CSF/SCTF (Jean LeBrun) UniCAD Canada Ltd. (Celso Faia) Veribest Ian Dodd* VLSI Technology (Dick Ulmer), Hrish Patel*, D.C. Sessions*, Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1997: 3M Fran Hart* Actel Scott Schlachter* Acuson & Free Model Foundation Richard Munden* Alcatel John Fitzpatrick* Ansoft Eric Bogatin* Apteq Design Systems Dan FitzPatrick* Compaq Weston Beal* Digital Equipment Corp. Jeff Chu EIA Patti Rusher* EMC Fabrizio Zanella* Micron Technology Brian Johnson* Molex Gus Panella* North Carolina State U. (Michael Steer) S3, Inc. Porsh Shih*, Jarathy Jribhashyam* Ultratest International Charles Im* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Note, refer to the January 10, 1997 minutes for the last listing of the 1996 IBIS Open Forum participants. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode 2/14/97 (916) 356-9200 3-81822 3973256 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each open forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- MINUTES NOTES: These minutes are constructed from raw/unedited notes taken and distributed by Jon Powell. The minutes capture some highlights of an all day face-to-face meeting where much of the technical content is in the presentation material itself. The presenter's are welcome to submit corrections and clarifications to these minutes, as needed. Syed Huq and Jon Powell will be working on making the presentations available in computer readable formats on vhdl.org for FTP or Browser access. These minutes contain some corrections received after Jon's notes were distributed. Jon noted that this was a well attended meeting with representatives from all of the various areas of IBIS interest including IC manufacturers, connector manufacturers, EDA vendors, and end users. The presentations were informative and covered a variety of topics. Finally, we give special thanks to Syed Huq and National Semiconductor for hosting the IBIS face-to-face meeting. National provided an excellent room and superior refreshments. INTRODUCTIONS - Syed Huq, National Semiconductor Syed Huq, National Semiconductor: Presiding Jon Powell, Quad Design: Acting Secretary Patti Rusher, EIA: EIA Representative REVIEW OF SUMMIT AGENDA, OPENS FOR NEW ISSUES - Syed Huq A question was raised regarding who is providing models. Jon Powell, who is serving as Librarian, commented that he will run QA checks on any model that is e-mailed to him at jonp@qdt.com. He also is soliciting models to be added to the IBIS reflector. Jon has not received any new models for release during the last eight months (except from Arpad Muranyi). ANSI/EIA-656 (IBIS) OVERVIEW - Syed Huq Syed Huq presented an overview and IBIS roadmap and discussed the usage of the IBIS reflectors for communication. Jon Powell indicated that IBIS Open Forum Member companies can add or update your company logo on the IBIS Poster page of the EIA/IBIS home page. Send the logo to jonp@qdt.com. It should be in bmp or tiff format and have a size of about 800x200 pixels. Bigger is better since Jon can size it down. EIA MEMBERSHIP AND IEC UPDATE - Patti Rusher, Electrical Industries Association Patti Rusher reported that there are 23 Official EIA/IBIS Members to date. Committee Membership is $500.00 per year. Membership applications are available from Patti and will soon be available on EIA/IBIS Web site. Bills for 1997 were also distributed at the meeting. IBIS will be represented at the Design Automation Conference (DAC) in June, 1997 in the EIA booth. Regarding EIA Web page usage, IBIS is number two in the EIA on hits and has over 7000 hits since page inception. IEC Update: Patti reported that IBIS is going through the international technical committee. IBIS will be assigned to Hilary Kahn. The goal is to have out as a full standard in the next two years. [Update from Patti: IBIS did not pass international standardization at the last IEC TC93 US TAG meeting because only three countries agreed to work on it (USA, Japan and UK with Denmark abstaining) and five are required. Several other countries will be approached.] IBIS MODELING AT ALCATEL - John Fitzpatrick - Alcatel CIT John Fitzpatrick indicated that Alcatel makes telephone switches. Alcatel has committed to building a large library of IBIS models. They have done signal integrity analysis in the past by hand using Bergeron diagrams. The goal with IBIS is to use models for simulation and extracting information to create design rules. John has found that the IBIS he uses that are not from the vhdl.org directory contain errors in all cases (100%). Therefore Alcatel is generating and checking the IBIS models themselves in a signal integrity laboratory. They want to use IBIS models to do constraint driven routing and also to use the IBIS files in a data base to extract information for design rules. An example of a question is: Do 3 volt devices need protection? Another use is to help with crosstalk control and route constraint generation for correct-by-design routing. IBIS models would provide the component series resistance to be used in conjunction with the proper series termination. John's wish list for IBIS extensions are: 1) Series components. (Very important) 2) Non-monotonic IV curve models. 3) R,L,C description capability. 4) BUS Switch Models (This is a very important issue) Alcatel wants to keep all models in IBIS format, but right now they are being forced to keep models in multiple formats because IBIS does not support the above extensions. John's less important wishes are: 1) Easier to understand IV curves: John suggests the need for new keywords that support pure measurement derived values and formatting and let the simulator do the necessary subtractions, etc. (A comment from the audience suggests the development of a better editor on input method.) 2) More background information in the model: Contact information, Brief description of the component, or URL to the component description. 3) Unique buffer names: Guidelines on buffer naming - each supplier should use a unique meaningful name. 4) Model Verification. 5) Long term goal: Full Electrical Specification (don't need data-sheets). 6) Recommended paper data-sheet format for representing IBIS models. 7) Better specification of minimum data to have in IBIS models. 8) IBIS as a specification tool. Other suggestions include: ASICs (to allow for a choice of output buffers) Second sourcing (give us a part that matches this model) Industry-standard I/O (Golden IBIS models representative of industry standard technologies (LCT, LVC, AC, FAST, Memories etc.) VISUAL IBIS EDITOR - Kellee Chrisafulli Kellee Chrisafulli offers the HyperLynx Visual IBIS Editor free from several websites. He is seeking user inputs on how to improve the Editor. It works with Windows 3.1, 95 and NT, but runs best on 95 and NT. It has a built in IBIS Version 2.1 and 1.1 syntax checker and an IBIS Skeleton generator. Built in viewers allow displaying the various tables graphically to assist in debugging the data. However, these tables cannot be edited using the viewers. The Editor is available on http://www.hyperlynx.com. Sheets were passed out to the audience for inputs concerning feature updates and suggestions. Suggestions given by audience include: 1) Show loading conditions on waveforms. 2) Overlay multiple curves for comparison of different models. 3) Don't show clamp of data beyond data range. Just show the end of the data. 4) Veribest might provide a spice2ibis converter in Windows NT executable format. 5) Remove the Control-M characters from files because they are not allowed in IBIS. (Is this true?) - [Answer - DOS formatted data is permitted and most parsers will ignore the Control-M character.] 6) Allow graphically editing of the tables. 7) Provide a pop-up menu with blanks for all input values. Comments to Kellee can be sent directly to kellee@hyperlynx.com. One comment is that IBIS standard needs to define how to interpret data that is beyond the end of the IBIS data range. Another comment is to contact Ian Dodd regarding putting his version of spice2ibis for Windows NT on an IBIS Web Site. SIGNAL INTEGRITY AND IBIS - Don Telian, Cadence [Note, this presentation was also given at Design SuperCon97 as "Signal Integrity Engineering in High-Speed Digital Systems" and was voted the best presentation. Don's background includes authoring both the initial IBIS and initial RAIL specifications and chairing the initial public forum committees for both devepment activities.] Don Telian, a Signal Integrity Engineering in High-speed Digital Systems Surveyed 5 managers of SI groups and put their feedback in this presentation. (See Don's slides and/or the Design SuperCon97 High-Performance System Design Conference proceedings, pp. HF213-1 - HP213-17 for the actual presentation.) The goal of this presentation is to define the SI engineer. Electrical description is moving from a static form to a dynamic form. Don presented seven roles of SI engineer: 1) Pioneering and Defining 2) Partitioning and Approximating 3) Modeling and Measuring 4) Design and Optimizing 5) Quantifying and Verifying 6) Reducing and Simplifying 7) Correlating and Debugging In conclusion one must resolve to use good judgment rather than to whine. PROBLEMS REPRESENTING ABT MODELS USING IBIS - Jon Powell, Quad Design Jon Powell shared that the TI Spice models for the ABT series demonstrates a charge pumping and load dependent IV phenomena beyond what can be represented in the current IBIS format. Jon showed a simplified circuit and gave some simulation examples to illustrate the effect. Jon plans to post a full report to the IBIS reflector for further discussion. AN IBIS SURVEY - Karl Kachigan, Hewlett Packard - EEsof Karl Kachigan reported the results of a survey questionnaire he had issued earlier on the IBIS reflector. The survey asked how people develop models, and the results show: 1) Most use Spice to develop models (based on 100% of responders derived IBIS models from Spice). 2) There is opportunity for commercialization of SPICE to IBIS converter (but people are not willing to pay a high price for such a converter). 3) Four out of seven responders said they did use some measurement techniques to validate the simulation. 4) The generation of models is usually not part of the budget. MODELING EARLY CLAMPS IN IBIS - Arpad Muranyi, Intel Arpad Muranyi reported on Intel work on "Integrated Termination for Low Power, Low Cost, High Speed Signaling" to put into chips. To be competitive in the personal computer market, Intel needed to develop a a low cost desktop chip set solution for the P6. Currently the GTL bus needs two terminators. This cost too much money and uses to much current. Intel has found a good technique that works in both GTL and CMOS. It lets you get rid of the resistors. Arpad showed a worst case circuit: A Tee topology circuit with termination in the middle. Terminating it at both ends causes problems. What is needed is a termination with a special IV curves with no currents at VOH and VOL. A solution is to use Early clamps to match diodes to the desired curve. In GTL systems, VOL drifts because it varies on buffer strength (and the strength of the pullup device). Static Early clamps are easy to model by inserting IV curves into the clamps. Dynamic curves are harder. Perhaps shift a IV curve as controlled by a VT curve. But the shifted IV curve might not be the same as the original IV curve. The timing is completely dependent on the implementation of the method, which is not defined. Arpad wants to come up with a IBIS description method that encompasses all possible implementation techniques. A suggestion was made to try and fit this into the Multi-staged Outputs BIRD35.3. BIRD35.3 would have to be modified to add a multi-receiver technology with a threshold test. Arpad will open this discussion on the IBIS reflector. BIRD36.D - Stephen Peters, Intel Steven Peters introduced BIRD36.d (which is work in progress by an off-line Package Committee to develop BIRD36.1 for IBIS Open Forum) by stating its intended scope: Simple board descriptions (SIMMs) Connectors (coupled and uncoupled) Complex (coupled) board descriptions are best left to physical/layout extraction descriptions (EDIF 4 0 0 calls out IBIS models). Some highlights of Stephen's presentation are given. Bird 36.d defines interconnect boundaries. In general [Application Info] is used for connectors. The keyword arguments provide critical information that the connector vendors feel is needed such as the rise time (bandwidth?) for which the model valid. [Number of Pins] used for boards, unmated connectors and such. [Number of Pairs] supports connectors that may eventually use a matrix description. The BIRD is ambiguous about general named nodes and available interconnections, but this is being fixed. It does make clear that if the length is specified as greater than zero, then the element is to be assumed to be distributed. The coupling description and formatting issue will apply for connectors only, not for general boards. The basic approach considered is to use cascaded, named matrices in some format to be determined. One problem and question is data reduction: Do you really want to describe fully a 200 pin, 4 row connector? Another problem is accuracy. The challenge is to agree on what the data represents and how to process it. The mated model includes both male and female pins connected to form one model. The unmated model represents only one of the connector components when it is disconnected. Discussion and debate followed concerning what is an acceptable way to specify a coupling matrix for connectors. One consensus (?) was that such a matrix formulation does exist, and the syntax needs to be agreed upon. D.C. Sessions was concerned that there is no definition for the local ground on a SIMM for local ground bounce analysis. OTHER ITEMS AND GENERAL DISCUSSION - Syed Huq Next meeting will be on Friday, February 14. The topic of what needs to be done for Version 3.0 needs to be discussed. Model verification signatures in IBIS models to document passing certain validation tests was suggested. One response is that it is the responsibility of the EDA companies to service their customers. Actel asked to make the "[SOURCE]" keyword required so that all models can be traced. However, there was opposition since there is no way to enforce such a requirement. NEXT MEETING: The next meeting is on Friday, February 14, 1996, 8:00 A.M. to 9:55 A.M. BIRD40 is scheduled for a vote along with a discussion on what needs to be done for Version 3.0. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 603-2523, Fax (503) 639-3469 bob@icx.com Modeling Engineer, Interconnectix 10220 SW Nimbus Ave, K4, Portland, OR 97223 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785 huq@rockie.nsc.com Staff Applications Engineer, National Semiconductor, M/S A-2595 2900 Semiconductor Drive, Santa Clara, CA 95052 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Transmission-Line Products Manager, Quad Design 1385 Del Norte Rd., Camarillo, CA 93010 SECRETARY: Vacant This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@vhdl.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org) or both. State your request. ibis-info@vhdl.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@vhdl.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. ibis-users@vhdl.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. ibischk-bug@vhdl.org To report ibischk2 parser bugs. The Bug Report Form Resides on vhdl.org in /pub/ibis/bugs/bugform.txt along with reported bugs. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on vhdl.org for more information on previous discussions and results. You can get on via ftp anonymous, "guest" login from telnet or dial-in (415-335-0110), or send an e-mail request to the automatic archive server, archive@vhdl.org. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ============================================================================== From owner-ibis Wed Feb 5 16:50:11 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id QAA00427 for ; Wed, 5 Feb 1997 16:50:09 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Wed, 5 Feb 97 16:24 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 5 Feb 97 16:24 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 5 Feb 97 16:26 PST Message-Id: Date: Wed, 5 Feb 97 16:26 PST From: bob@icx.com ( Bob Ross) To: fukuda@cc-smtp.hitachi-mc.co.jp Subject: Re: EIAJ I/O Interface Model Cc: bob@icx.com, huq@rockie.nsc.com, ibis@vhdl.org, jonp@qdt.com, pattir@eia.org, will_hobbs@ccm2.jf.intel.com Fukuda-san Thank you very much for your update. I am looking forward to seeing your proposal. You ask how we should proceed toward productive cooperation between the IBIS Open Formum and EIAJ. My recommendation is that you provide me with an electronic copy of draft v0.0. I would like permission to be able to either circulate it to the IBIS Open Forum distribution list and/or to store a copy on the vhdl.org/pub/ibis directory for public viewing and access. At this time, without seeing the proposal, I cannot predict how it will be initially received. My expectation is that the proposal will generate a set of technical questions which will need clarification, and may possibly raise issues and challenges. So you may need to be prepared to be responsive and to either defend or modify your proposal. The IBIS Open Forum has been in existence since 1993 and has operated through public discussions. The formal EIA/IBIS Committee membership consists of 23 companies from many of the leading EDA simulator, semiconductor, and user companies (AMP, Applied Simulation Technology (formally Contec), Cadence, Cypress, Hewlett Packard, Hyperlynx, Incases, Interconnectix (now with Mentor Graphics), Meta-Software (now with Avanti), Mitsubishi, Motorola, National Semiconductor, NCR (formally with ATT), NEC, Quad Design (a Viewlogic company), Quantic Laboratories, Texas Instruments, Thomson-CSF/SCTF, Unicad (now with CCT which is part of Cadence), Veribest (formerly from Integraph), VLSI Technology, and Zuken-Redac). The meeting participation in 1996 in IBIS activities includes over 75 indivuals from most of the above companies plus many more, since participation is open to anyone. The IBIS mailing list contains over 280 names from companies all over the world. The IBIS Open Forum continues to meet regularly, both via telephone conference calls and via face-to-face meetings. Like your committee, we are driven by EDA customer analysis needs and newer Silicon developments, and we have enhancements to IBIS, either approved or underdevelopment. We also have extensive package model enhancements related to Pentium Pro hybrid chip construction and newer ideas, proposals for SIMM modules, proposals for some buffer complications including multi-staged switched buffers, and mapping and coupling considerations leading to ground/power bounce analysis. Your ideas are welcome in these areas because these all represent difficult and (in our committee) controversial extensions. While you state there is no overlap, and you stress a relationship with a Spice style format, we continue to be interested in your ideas. So we need to see what you have developed before determining whether to continue independently or to cooperate in some manner. I would like to know which companies are contributing to your proposal. Finally, we welcome you or any of your members to participate in the IBIS Open Forum discussions. Best Regards, Bob Ross IBIS Open Forum Chair Phone (503) 603-2523, Fax (503) 639-3469 bob@icx.com Interconnectix, 10220 S.W. Nimbus Ave., K4, Portland, OR 97223 > Date: Thu, 30 Jan 97 19:03:08 JST > Message-Id: <9700308546.AA85461@htc-mc2.hitachi-mc.co.jp> > To: bob@icx.com > CC: FYT46205@pcvan.or.jp, fukawa@eiaj.or.jp > Subject: EIAJI/O Interface Model > Status: RO > Dear Mr. Ross > As I informed you, We are discussing I/O interface model in EIAJ. We finished > the draft v0.0 by the end of the last year, and will be ready to release in the > coming February both in Japanese and in English. > As I showed you the scope of our activity, we do not intend to compete with > IBIS, but to propose improvements for extending application and in reducing > inconvenience in model supply from IC companies. The points of the > improvement are : > (1) Ground / power bounce > (2) Complicated circuits buffers > (3) Complicated shaped packages and modules. > Recently IC companies are required to supply both IBIS and SPICE data. This > inconvenience might be solved by the unified model adopted in our proposal. > I would like to have your idea about how to proceed toward productive > cooperation between IBIS and EIAJ. > Best regards, > Hideki Fukuda > Chairman > I/O Interface Model Project Group > Technical Standardization Committee on Semiconductor Devices > EIAJ > Hitachi Microcomputer System > Tel +81-423-25-1711 > Fax +81-423-28-1462 > E-mail fukuda@hitachi-mc.co.jp From owner-ibis Wed Feb 5 16:57:03 1997 Received: from molex_017.molex.com ([209.28.10.2]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA00496 for ; Wed, 5 Feb 1997 16:57:01 -0800 (PST) From: apanella@molex.com Received: from molex_017 (localhost [127.0.0.1]) by molex_017.molex.com (8.7.3 Version 1.1 Build 563/8.7.3) with SMTP id PAA00136 for ibis@vhdl.org; Wed, 05 Feb 1997 15:02:36 -0600 (Central Standard Time) Date: 5 Feb 97 14:50 CST X400-Trace: us*molexnet*molex; Arrival 5 Feb 97 14:50 CST Action: Relayed Priority: normal P1-Message-ID: us*molexnet*molex;0855176550/0000008580/1 Original-Encoded-Information-Types: IA5-Text To: ibis@vhdl.org Message-ID: <@m400gw.molex.com> Subject: Hello is there anybody out there?? I haven't seen anything on the reflector since SuperCon.... Have I missed anything..... _gus panella apanella@molex.com From owner-ibis Thu Feb 6 10:09:41 1997 Received: from hq15.pcmail.ingr.com (hq15.pcmail.ingr.com [129.135.251.243]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id KAA01880 for ; Thu, 6 Feb 1997 10:09:40 -0800 (PST) Received: by hq15.pcmail.ingr.com with SMTP (Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63) id <01BC1426.3F0B28E0@hq15.pcmail.ingr.com>; Thu, 6 Feb 1997 12:06:55 -0600 Message-ID: From: "Dodd, Ian" To: "'ibis@vhdl.org'" , "'awglaser@eos.ncsu.edu'" Subject: Spice to IBIS translator for NT (Comment on IBIS Summit Minutes) Date: Thu, 6 Feb 1997 12:06:11 -0600 X-Mailer: Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63 Encoding: 22 TEXT Hi all, Veribest has ported the version 1 SPICE to IBIS converter to Windows NT. We will provide it as an executable and as source to interested parties on a "as is" basis. Our source has been modified to fix a few critical bugs and to work around file access (locking) problems that occur on NT but not on UNIX. We also added an option to use our proprietary analog simulator. The executable should also work under windows 95 (to be verified!) We are actively working on porting the latest version of the program and will make it available as soon as we have done some unit testing. If someone wants the version 1 converter for NT, please contact me. In addition, do we want to put this port on vhdl.org? Obviously we are very grateful to the team at North Carolina State University that wrote this program, and hope that providing the NT port assists the IBIS cause. Ian C Dodd Veribest Inc idodd@veribest.com From owner-ibis Thu Feb 6 16:03:11 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id QAA07581 for ; Thu, 6 Feb 1997 16:03:09 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Thu, 6 Feb 97 16:01 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 6 Feb 97 16:01 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 6 Feb 97 16:03 PST Message-Id: Date: Thu, 6 Feb 97 16:03 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: Forwarded: waveform testloads For Reflector Discussion Bob Ross Interconnectix, Inc. Date: Thu, 6 Feb 97 15:52:33 +0100 From: cornelia@thesys.de (Cornelia Foss) Message-Id: <9702061452.AA11815@s01.thesys.de> To: ibis-info@vhdl.org Subject: waveform testloads Status: RO Hello all, I've been off the IBIS topic for a while, so please forgive if I come up with an "old" question. After reviewing the discussion concerning how to provide waveform- loads that model the ac- behavior most correctly there are still questions. When generating for instance [rising waveform] information I currently use a non-reactive load at high and low voltage - is that valid? These waveforms are only correct at one point each, the simulator will have to interpolate somehow. So it is quite clear that the results may differ from simulator to simulator, but to hold the differences to a minimum it was helpfull if one would know how interpolation is done, are these algorithms known? I followed Dileep Divekar's argumentation that an expected non-linear load dependence cannot be modeled uniquely with only one test load. If that is still true can I provide waveforms with different loads to give some interpolation points of load dependence of the output? (will simulators take this into account?) I wonder how simulators derive the output under arbitrary load con- ditions if only one [rising/falling waveform] table is contained by the model. Do they perhaps use parametric output characteristics and "scale" them with the given waveform? - If so, how to deal with bipolar devices that surely have a different load dependence? In the december 12th 96 meeting minutes it is noted that Mr. Rokusek is collecting simulator vendors's suggestions concerning test loads. Are the results available? (I didn`t find any, sorry if I overlooked it) I do not want to start the diskussion again (though is seems to be on, anyway) but just want to get as much information as possible to improve the models. Thank you very much for your support, I'm hopefully looking forward to reply Best regards Sascha Pawel e-mail: cornelia@thesys.de PS: In many examples the C_comp max table contains the largest C_comp values and the min table the smallest. Shouldn't it be vice versa for the entries in the max column are used to form fast/strong models? -------- End of Forwarded Message From owner-ibis Thu Feb 6 16:21:42 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id QAA07696; Thu, 6 Feb 1997 16:21:40 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Thu, 6 Feb 97 16:20 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 6 Feb 97 16:20 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 6 Feb 97 16:21 PST Message-Id: Date: Thu, 6 Feb 97 16:21 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org, ibischk_bug@vhdl.org Subject: IBIS_CHK BUG8 ****************************************************************************** ********************* IBIS GOLDEN PARSER BUG REPORT FORM ********************* ****************************************************************************** INSTRUCTIONS To report a bug in the IBIS golden parser. Please fill out the top part of the following form and send the complete form to ibischk-bug@vhdl.org. A list of reported bugs will be maintained on vhdl.org. ****************************************************************************** PARSER VERSION NUMBER: IBIS_CHK V2.1.11, and IBIS_CHK V1.1.a PLATFORM (SPARC, HP700, PC, etc.): SUN OS AND VERSION: SunOS 4.1.4 REPORTED BY: Bob Ross, Interconnectix DATE: February 6, 1997 DESCRIPTION OF BUG: Reserved keywords used as pin numbers generate errors (This bug was discovered by Arthur Wong of IDT and reported December 5, 1996.) | When pin "number" takes on the name of any of the reserved keywords | (gnd, power, nc, na), an error is reported. INSERT IBIS FILE DEMONSTRATING THE BUG: |*************************************************************** | [IBIS Ver] 2.1 | [IBIS Ver] 1.1 [File Name] prob8.ibs [File Rev] 0.1 [Date] January 22, 1997 [Source] Bob Ross, Interconnectix [Disclaimer] Provided for modeling purposes only. Results are not guaranteed. | |*************************************************************** | [Component] TEST [Manufacturer] Test File [Package] | variable typ min max R_pkg 0.0m NA NA L_pkg 0.0nH NA NA C_pkg 0.0pF NA NA | |*************************************************************** | [Pin] signal_name model_name R_pin L_pin C_pin nc One_Pin NC gnd One_Pin GND na One_Pin NC power One_Pin POWER | [End] ****************************************************************************** ******************** BELOW FOR ADMINISTRATION AND TRACKING ******************* ****************************************************************************** BUG NUMBER: 8 SEVERITY: [FATAL, SEVERE, MODERATE, ANNOYING, ENHANCEMENT] ANNOYING PRIORITY: [HIGH, MEDIUM, LOW] LOW STATUS: [OPEN, CLOSED, WILL NOT FIX, NOT A BUG] OPEN FIXED VERSION: FIXED DATE: NOTES ON BUG FIX: ****************************************************************************** ****************************************************************************** From owner-ibis Fri Feb 7 06:26:27 1997 Received: from zoom.bga.com (root@zoom.realtime.net [205.238.128.40]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id GAA01625 for ; Fri, 7 Feb 1997 06:26:26 -0800 (PST) Received: from LOCALNAME (apm1-74.realtime.net [205.238.146.74]) by zoom.bga.com (8.6.12/8.6.12) with SMTP id IAA06273 for ; Fri, 7 Feb 1997 08:25:00 -0600 Message-ID: <32FB5894.104D@realtime.net> Date: Fri, 07 Feb 1997 08:30:12 -0800 From: Russell Rapport Organization: Staktek X-Mailer: Mozilla 2.02E-KIT (Win16; U) MIME-Version: 1.0 To: ibis@vhdl.org Subject: ibis-to-spice conversion Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit My question is very basic. I need to verify signal integrity starting with vendor-supplied Hspice and IBIS models. I work for a small company with a limited simulation budget, and I have access to Pspice, Hspice, and Viewlogic, and normally work in a Windows/NT environment, but I have access to UNIX workstations. We do not use a board-layout package, and I usually model a few worst-case situations, rather than importing some netlist generated by a large CAD system. I have had serious problems with the Pspice IBIS 1.0-to-spice translator, and I can rarely get a usable conversion. I would prefer to model everything in one design environment, but I will do whatever I need to. How do most IBIS "consumers" use the IBIS files? Is there a reasonable solution for small companies? Please send me mail directly if you want to tell me about your product, since I realize competing vendors use this mailing list. From owner-ibis Fri Feb 7 07:47:15 1997 Received: from mailgw.chips.ibm.com (mailgw.chips.ibm.com [192.91.197.8]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id HAA01883 for ; Fri, 7 Feb 1997 07:47:14 -0800 (PST) Received: from mailrelay.btv.ibm.com (mailrelay.btv.ibm.com [9.66.4.12]) by mailgw.chips.ibm.com (8.8.5/8.8.5) with ESMTP id KAA07510 for ; Fri, 7 Feb 1997 10:45:18 -0500 Received: from postoffice.btv.ibm.com (postoffice.btv.ibm.com [9.66.4.40]) by mailrelay.btv.ibm.com (8.8.5/8.8.5) with ESMTP id KAA51242 for ; Fri, 7 Feb 1997 10:45:18 -0500 Received: from wind.btv.ibm.com (wind.btv.ibm.com [9.66.57.118]) by postoffice.btv.ibm.com (8.8.5/8.8.5) with SMTP id KAA73524 for ; Fri, 7 Feb 1997 10:45:19 -0500 Received: by btv.ibm.com (AIX 4.1/UCB 5.64/fs4.03) id AA27908; Fri, 7 Feb 1997 10:45:18 -0500 Message-Id: <9702071545.AA27908@btv.ibm.com> X-Mailer: exmh version 2.0gamma 1/27/96 AIX 4.1.4 To: ibis@vhdl.org X-Note-Format: RFC822 Subject: >> IBIS to SPICE Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Fri, 07 Feb 1997 10:45:17 -0500 From: "Ezra D. Hall" -- This is a good question. I would also like to see a list of vendors and software tools available for converting IBIS models into behavioral models, HSpice specific or otherwise. AVANT! (formerly Metasoft) is no longer supporting their METAIO tools for IBIS to HSPICE behavioral model conversion(It is at End Of Life). What else is out there? Do users now have to convert IBIS models by hand? I am particularly interested since I am creating IBIS models, and need to perform verification in a more efficient manner than by hand. Any feedback would greatly be appreciated. Thanks! Sincerely, Ezra Hall ------- Forwarded Message Date: Fri, 07 Feb 1997 08:30:12 -0800 From: Russell Rapport To: ibis@vhdl.org Subject: ibis-to-spice conversion My question is very basic. I need to verify signal integrity starting with vendor-supplied Hspice and IBIS models. I work for a small company with a limited simulation budget, and I have access to Pspice, Hspice, and Viewlogic, and normally work in a Windows/NT environment, but I have access to UNIX workstations. We do not use a board-layout package, and I usually model a few worst-case situations, rather than importing some netlist generated by a large CAD system. I have had serious problems with the Pspice IBIS 1.0-to-spice translator, and I can rarely get a usable conversion. I would prefer to model everything in one design environment, but I will do whatever I need to. How do most IBIS "consumers" use the IBIS files? Is there a reasonable solution for small companies? Please send me mail directly if you want to tell me about your product, since I realize competing vendors use this mailing list. ------- End of Forwarded Message -- +-------------------------------------------------------------+ | x86 Microprocessor Development | | | | Ezra D.B. Hall | Internet: ehall@btv.ibm.com | | IBM Microelectronics | VM: ehall at btvlabvm | | D/G8G B/863-2 | Phone: (802) 769-7329 | | 1000 River Street | FAX: (802) 769-6800 | | Essex Junction, VT 05452-4299 | | +-------------------------------+-----------------------------+ From owner-ibis Fri Feb 7 09:22:09 1997 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id JAA02114 for ; Fri, 7 Feb 1997 09:22:09 -0800 (PST) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id JAA07160; Fri, 7 Feb 1997 09:22:04 -0800 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (V1.3) id sma007100; Fri Feb 7 09:22:00 1997 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA01177 for ibis@vhdl.org; Fri, 7 Feb 97 09:20:39 -0800 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA10122; Fri, 7 Feb 97 09:22:52 PST Date: Fri, 7 Feb 97 09:22:52 PST From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9702071722.AA10122@rockie.nsc.com> To: ibis@vhdl.org, ehall@btv.ibm.com Subject: Re: >> IBIS to SPICE Hi, The roster listing of the EDA vendors and IBIS members may be a good starting point. You may want to try http://www.vhdl.org/pub/ibis/roster/roster.txt At least this will give you a contact name for the EDA vendors supporting IBIS. Regards, Syed National Semiconductor Corp. > Ezra Hall writes: (extracted).. > ..... > I would also like to see a list of vendors and > software tools available for converting IBIS models into behavioral models, > HSpice specific or otherwise. > Thanks! > >.... From owner-ibis Fri Feb 7 09:23:46 1997 Received: from actel.com (rigel-g.actel.com [204.33.232.16]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id JAA02119; Fri, 7 Feb 1997 09:23:45 -0800 (PST) Received: from ricky.sun_net ([190.9.2.228]) by actel.com (4.1/SMI-4.1) id AA08540; Fri, 7 Feb 97 09:24:06 PST Received: by ricky.sun_net (4.1/SMI-4.1) id AA09450; Fri, 7 Feb 97 09:23:59 PST Date: Fri, 7 Feb 97 09:23:59 PST From: scotts@actel.com (Scott Schlachter) Message-Id: <9702071723.AA09450@ricky.sun_net> To: ibis@vhdl.org, ibis-users@vhdl.org Subject: Lab data vs. Spice data Hello Ibis folks, I'd like to compare notes with those who have produced IBIS files from *BOTH* Spice and lab measurements. Please respond to me directly (not through the reflector) if you have done this, particularly if yours is a CMOS process. Thanks, -Scott Schlachter Actel Corporation scotts@actel.com Sunnyvale, CA From owner-ibis Fri Feb 7 09:30:13 1997 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id JAA02183 for ; Fri, 7 Feb 1997 09:30:11 -0800 (PST) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id JAA13007 for ; Fri, 7 Feb 1997 09:30:06 -0800 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (V1.3) id sma012228; Fri Feb 7 09:28:57 1997 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA02058 for ibis@vhdl.org; Fri, 7 Feb 97 09:27:35 -0800 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA10295; Fri, 7 Feb 97 09:29:49 PST Date: Fri, 7 Feb 97 09:29:49 PST From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9702071729.AA10295@rockie.nsc.com> To: ibis@vhdl.org Subject: IBIS Meeting Agenda Feb14th'97 Cc: huq@rockie.nsc.com IBIS Open Forum Meeting Agenda for 2/14/96 Bridge Number Reservation # Passcode (916) 356-9200 3-81822 3973256 All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the Reservation Number and Passcode. 8:00 Check-In, Intros, Announcements Ross - Intros of New IBIS Participants, Meeting Quorum Ross - Membership Update and Treasurers Report Rusher - Review of Previous Meeting's Minutes (and ARs) Ross - Miscellany/Announcements All - Press & Web Page Updates Huq, All - New Models Available, Library Update Powell, All - Opens for New Issues All 8:25 Administrative and Project Discussions Design SuperCon97 IBIS Meeting Report Huq DAC97 IBIS Meeting Planning Rusher International Progress/Developments Rusher/Ross - EIAJ I/O Interface standard update Ross Purchase National IBIS Article Reprints Huq Roster Update Ross vhdl.org changes Ross Cookbook Rokusek Model Test Load Recommendations Muranyi IBIS-to-Behavioral Model support Huq SPICE-to-IBIS translator for NT Dodd New Administrative Issues All 9:00 Technical Discussion BIRD40 - OVERSHOOT NOMENCLATURE (Vote) Ross Version 3.0 Functionality Ross - Bus and Series Models Fitzpatrick - Switched Terminators Muranyi Package Committee Report Peters Parser Status Rokusek Pin Name Ross New Technical Issues All 9:50 Wrap Up and Next Meetings Plans Ross 9:55 Sign Off From owner-ibis Fri Feb 7 10:15:50 1997 Received: from relay5.UU.NET (relay5.UU.NET [192.48.96.15]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA02310 for ; Fri, 7 Feb 1997 10:15:49 -0800 (PST) Received: from uucp5.UU.NET by relay5.UU.NET with SMTP (peer crosschecked as: uucp5.UU.NET [192.48.96.36]) id QQcbwy06003; Fri, 7 Feb 1997 13:14:24 -0500 (EST) Received: from qdt.UUCP by uucp5.UU.NET with UUCP/RMAIL ; Fri, 7 Feb 1997 13:14:24 -0500 Received: from hal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00862; Fri, 7 Feb 97 10:04:34 PST Received: from awacs by hal.qdt.com (4.1/SMI-4.1) id AA13930; Fri, 7 Feb 97 10:04:34 PST Sender: crokusek@qdt.com Message-Id: <32FB6EB1.15FB7483@qdt.com> Date: Fri, 07 Feb 1997 10:04:33 -0800 From: Chris Rokusek Organization: Quad Design Technology X-Mailer: Mozilla 3.0Gold (X11; I; SunOS 4.1.4 sun4m) Mime-Version: 1.0 To: ibis@vhdl.org Subject: Re: Forwarded: waveform testloads Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Sacha, Here is ONE simulator's (Quad Design/XTK) response. > When generating for instance [rising waveform] information I currently > use a non-reactive load at high and low voltage - is that valid? Yes. See our recommendation for test waveforms below. > These waveforms are only correct at one point each, the simulator > will have to interpolate somehow. So it is quite clear that the > results may differ from simulator to simulator, but to hold the > differences to a minimum it was helpfull if one would know how > interpolation is done, are these algorithms known? We are not planning to provide all our internal algorithms on the reflector at this time. They differ among simulation vendors. All the simulation vendor's collective customers must make the choice that best fits their accuracy requirements. > I followed Dileep Divekar's argumentation that an expected non-linear > load dependence cannot be modeled uniquely with only one test load. > If that is still true can I provide waveforms with different loads > to give some interpolation points of load dependence of the output? > (will simulators take this into account?) We partially disagree with this argument. We claim that the recommended test loads below will provide results meeting our customer's accuracy requirements (our customers are very picky!). Additional waveforms could be provided as a QA test, however they are not presently used directly in the computation. > I wonder how simulators derive the output under arbitrary load con- > ditions if only one [rising/falling waveform] table is contained by the > model. Do they perhaps use parametric output characteristics and > "scale" them with the given waveform? - If so, how to deal with > bipolar devices that surely have a different load dependence? By default, we would like to see 2 waveforms for a non-single-ended device (e.g. non- open drain) devices. Without two, only the risetime/falltime is used rather than any waveform(s). Bipolar devices DO require a differnt algorithm. > In the december 12th 96 meeting minutes it is noted that Mr. Rokusek > is collecting simulator vendors's suggestions concerning test loads. > Are the results available? (I didn`t find any, sorry if I overlooked > it) My email is crokusek@qdt.com, please send any test load recommendations to me or the reflector for discussion, I haven't received any up to this point. > I do not want to start the diskussion again (though is seems to be > on, anyway) but just want to get as much information as possible to > improve the models. > Thank you very much for your support, I'm hopefully looking forward > to reply The "improvement of models" should be the ultimate goal, it should be possible to make/keep everyone happy: model makers, simulation vendors, and most importantly our mutual customers. ------------------------------------------------------------------------ Recommended waveforms: o Single-ended Devices: 1 rising, 1 falling If the driver requires a pull-up or pull-down device to function, the termination resistor and supply used for the design should be used to terminate the driver for this test. o CMOS: 2 rising, 2 falling 50 ohms to a terminating voltage equal to the drivers negative supply voltage. 50 ohms to a terminating voltage equal to the drivers positive supply voltage. o TTL: 2 rising, 2 falling 500 ohms to a terminating voltage equal to the drivers negative supply voltage. 7 ohms to a terminating voltage equal to the drivers positive supply voltage. In terms of IBIS we are currently accepting the following... - C_fixture == 0.0pF - L_fixture == 0.0nH - V_fixture - (VCC or GND) <= 0.7V - 3.0 < R_fixture < 30.0 (TTL to VCC) - 200.0 < R_fixture < 1000.0 (TTL to GND) - 25.0 < R_fixture < 200.0 (CMOS) Of all waveforms meeting the above criteria, the two (VCC and GND) waveforms with R_fixture values closest to the recommended R_fixture values are chosen. For open-ended devices, only one (VCC or GND or Vterm) waveform is needed. If the waveforms are unusable, ramp data (edge rate only) is used. As stated in the IBIS V2.1 specification, if more than one rising or falling edge waveform table is present, then the data in each of the respective tables must be time correlated. In other words, the rising (falling) edge data in each of the rising (falling) edge waveform tables must be entered with respect to a common reference point on the input stimulus waveform. --------------------------------------------------------------------------- The above is not GOLDEN or set in stone--only ONE simulator's present opinion. Another specific simulation vendor may want e.g. reactively loaded waveforms, if so then the ibis forum can agree to a compilation of all waveform requirements. Just trying to get the ball rolling... Best Regards, Chris Rokusek Quad Design/Viewlogic (P.S. I don't know the answer to your Ccomp question.) From owner-ibis Fri Feb 7 10:24:57 1997 Received: from netcomsv.netcom.com (uucp9.netcom.com [163.179.3.9]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id KAA02325 for ; Fri, 7 Feb 1997 10:24:57 -0800 (PST) Received: from contec.UUCP by netcomsv.netcom.com with UUCP (8.6.12/SMI-4.1) id KAA05308; Fri, 7 Feb 1997 10:10:09 -0800 Received: from contec12.contec.COM by contec.COM (4.1/SMI-4.1) id AA04738; Fri, 7 Feb 97 09:34:16 PST Received: by contec12.contec.COM (5.0/SMI-SVR4) id AA02620; Fri, 7 Feb 1997 09:47:39 +0800 Date: Fri, 7 Feb 1997 09:47:39 +0800 From: fred@contec.contec.COM (Fred) Message-Id: <9702071747.AA02620@contec12.contec.COM> To: ibis@vhdl.org Subject: IBIS to Spice X-Sun-Charset: US-ASCII There are indeed other solutions. I am with Applied Simulation Technology. We just announced an ibis translator at HP Design SuperCon held in Santa Clara a couple of weeks ago. This is an automated tool which converts the model with a mouse click. It also supports IBIS 2.x (lost count) specification which has rise and fall times information in the form of V/T information. The software automactically produces a simulation ready model and testing of the model can be preformed within the software. If you specifically (Russel and Ezra) need more information you can contact me at fred@apsimtech.com or 408-434-0967 ext. 102. Best Regards, Fred Balistreri From owner-ibis Fri Feb 7 10:37:51 1997 Received: from montana.nwlink.com (kellee@montana.nwlink.com [199.242.23.13]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA02354 for ; Fri, 7 Feb 1997 10:37:51 -0800 (PST) Received: (from kellee@localhost) by montana.nwlink.com (8.8.5/8.7.3) id KAA05859; Fri, 7 Feb 1997 10:36:27 -0800 (PST) Message-Id: <3.0.32.19970207103422.00712d18@mail.nwlink.com> X-Sender: kellee@mail.nwlink.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Fri, 07 Feb 1997 10:34:23 -0800 To: ibis@vhdl.org From: Kellee Crisafulli Subject: Re:How to verify IBIS models Cc: bhargin@hyperlynx.com Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" At 10:45 AM 2/7/97 -0500, Ezra D. Hall wrote: >conversion(It is at End Of Life). What else is out there? Do users now have >to convert IBIS models by hand? I am particularly interested since I am >creating IBIS models, and need to perform verification in a more efficient >manner than by hand. Any feedback would greatly be appreciated. A better solution might be to use a simulator that runs IBIS models directly. Our LineSim package is ideal for testing IBIS models and is very low cost. See our web site at: www.hyperlynx.com From owner-ibis Fri Feb 7 10:44:03 1997 Received: from montana.nwlink.com (kellee@montana.nwlink.com [199.242.23.13]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA02369 for ; Fri, 7 Feb 1997 10:44:02 -0800 (PST) Received: (from kellee@localhost) by montana.nwlink.com (8.8.5/8.7.3) id KAA07290; Fri, 7 Feb 1997 10:42:39 -0800 (PST) Message-Id: <3.0.32.19970207104033.0071c058@mail.nwlink.com> X-Sender: kellee@mail.nwlink.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Fri, 07 Feb 1997 10:40:35 -0800 To: ibis@vhdl.org From: Kellee Crisafulli Subject: Re: IBIS_CHK BUG8 Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Hi all, It is not obvious that to me that this is really a bug. It seems that this user has the usage of Pin and signal_name reversed. Please consider removing this from the bug list. "pin" should be 1,2,3,4 or AA1, BC1 etc. There really should never be a conflict with the reserved words. >DESCRIPTION OF BUG: Reserved keywords used as pin numbers generate errors > >(This bug was discovered by Arthur Wong of IDT and reported December 5, 1996.) > >| When pin "number" takes on the name of any of the reserved keywords >| (gnd, power, nc, na), an error is reported. > >[Pin] signal_name model_name R_pin L_pin C_pin >nc One_Pin NC >gnd One_Pin GND >na One_Pin NC >power One_Pin POWER >| From owner-ibis Fri Feb 7 11:27:05 1997 Received: from fishbowl02.emc.com (fishbowl02.lss.emc.com [168.159.48.62]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id LAA02489 for ; Fri, 7 Feb 1997 11:27:04 -0800 (PST) Received: by fishbowl02.emc.com; Fri, 7 Feb 97 14:26:47 -0500 Date: Fri, 7 Feb 97 14:20:37 EST Message-ID: X-Priority: 3 (Normal) To: Cc: From: "fabrizio zanella" Subject: re: ibis-to-spice conversion Russell, Applied Simulation Technology, in San Jose, CA, makes an IBIS to SPICE converter. At my last job I had purchased it and used it (it worked well), and cost considerably less than other IBIS to SPICE translators available. (It is still supported). For information contact Fred Balistreri 408-434-0967, X102. Regards, Fabrizio Zanella _/ _/ email: zanella_fabrizio@emc.com _/_/_/_/ _/ _/ _/_/_/ _/ voice: (508) 435-1000 Ext. 4645 _/ _/_/ _/_/ _/ _/ Fax: (508) 435-8949 _/_/_/_/ _/ _/ _/ _/ _/_/_/ _/ _/ _/ _/ EMC Corporation _/_/_/_/ _/ _/ _/_/_/ 171 South Street Hopkinton, MA 01748-9103 ------------- Original Text From: Russell Rapport , on 2/7/97 8:30 AM: To: My question is very basic. I need to verify signal integrity starting with vendor-supplied Hspice and IBIS models. I work for a small company with a limited simulation budget, and I have access to Pspice, Hspice, and Viewlogic, and normally work in a Windows/NT environment, but I have access to UNIX workstations. We do not use a board-layout package, and I usually model a few worst-case situations, rather than importing some netlist generated by a large CAD system. I have had serious problems with the Pspice IBIS 1.0-to-spice translator, and I can rarely get a usable conversion. I would prefer to model everything in one design environment, but I will do whatever I need to. How do most IBIS "consumers" use the IBIS files? Is there a reasonable solution for small companies? Please send me mail directly if you want to tell me about your product, since I realize competing vendors use this mailing list. begin 666 ATTRIBS.BND M0F5Y;VYD(%!A8VME9"!!='1R:6)U=&5S```+0514*```````FEO('IA;F5L;&$````````````````````````````````````` M```````````````````````````````````X5DHX*S,P M!0``````````````````````````3W)I9VEN86P@=&5X=.X#1G)O;3H@4G5S M2!S M=&%R=&EN9R`*=VET:"!V96YD;W(M2!W;W)K(&EN(&$@5VEN9&]W2!G970@82!U2!I9B!Y M;W4@=V%N="!T;R!T96QL(&UE(&%B;W5T('EO=7(@<')O9'5C="P@`!`<`#`:`%`8`'`6`)`4`+`2`-`0`/`>`0`<`2`:`4`8`6`6`8`4`: M````````````````9``!L`$!8`,!$`4!P`8!<`@!(`H!T`L!@`T!,`\!X!`! MD!(!0!0!\!4!H!<``!$`````````!``%!``````````````````````````` M5&5X="8#4G5SF%N96QL85]F86)R M:7II;T!E;6,N8V]M"B`@("`@("!?+U\O7R]?+R`@7R\@("`@(%\O("`@7R]? M+U\O("`@("!?+R`@("!V;VEC93H@*#4P."D@-#,U+3$P,#`@17AT+B`T-C0U M"B`@("`@(%\O("`@("`@("!?+U\O(%\O7R\@(%\O("`@("`@("!?+R`@("`@ M("`@("!&87@Z("@U,#@I(#0S-2TX.30Y"B`@("`@7R]?+U\O7R\@(%\O("!? M+R!?+R`@7R\@("`@("!?+U\O7R\*("`@(%\O("`@("`@("!?+R`@("`@7R\@ M(%\O("`@("`@("`@("`@("`@("`@("`@("!%34,@0V]R<&]R871I;VX*("`@ M7R]?+U\O7R\@(%\O("`@("!?+R`@("!?+U\O7R\@("`@("`@("`@("`@("`@ M("`Q-S$@4V]U=&@@4W1R965T"B`@("`@("`@("`@("`@("`@("`@("`@("`@ M("`@("`@("`@("`@("`@("`@("`@($AO<&MI;G1O;BP@34$@,#$W-#@M.3$P M,PK9``,`)@/2``$``0````T``0`!``$`)@,```````!,_P```````)`!```` M``````!#;W5R:65R($YE=P`````````````````````````````````!``$` M`0$!``(!&0$!`!H!/@$!`#\!1P$!`$@!6`$!`%D!G`$!`)T!Z@$!`.L!+P(! M`#`"6`(!`%D"F@(!`)L"W0(!`-X")@,!`"<#)P,```````````````!D``&P M`0%@`P$0!0'`!@%P"`$@"@'0"P&`#0$P#P'@$`&0$@%`%`'P%0&@%P```!$` M````````#0!>!0``````````````````````````3W)I9VEN86P@=&5X=.X# M1G)O;3H@4G5S2!S=&%R=&EN9R`*=VET:"!V96YD;W(M2!W;W)K(&EN(&$@5VEN9&]W2!G970@82!U2!I9B!Y;W4@=V%N="!T;R!T96QL(&UE(&%B;W5T('EO=7(@<')O9'5C M="P@`!`<`#`:`%`8`'`6`)`4`+`2`-`0`/`>`0`<`2`:`4 M`8`6`6`8`4`:````````````````9``!L`$!8`,!$`4!P`8!<`@!(`H!T`L! M@`T!,`\!X!`!D!(!0!0!\!4!H!<``!$`````````!``%!``````````````` M````````````5&5X="8#4G5SF%N M96QL85]F86)R:7II;T!E;6,N8V]M"B`@("`@("!?+U\O7R]?+R`@7R\@("`@ M(%\O("`@7R]?+U\O("`@("!?+R`@("!V;VEC93H@*#4P."D@-#,U+3$P,#`@ M17AT+B`T-C0U"B`@("`@(%\O("`@("`@("!?+U\O(%\O7R\@(%\O("`@("`@ M("!?+R`@("`@("`@("!&87@Z("@U,#@I(#0S-2TX.30Y"B`@("`@7R]?+U\O M7R\@(%\O("!?+R!?+R`@7R\@("`@("!?+U\O7R\*("`@(%\O("`@("`@("!? M+R`@("`@7R\@(%\O("`@("`@("`@("`@("`@("`@("`@("!%34,@0V]R<&]R M871I;VX*("`@7R]?+U\O7R\@(%\O("`@("!?+R`@("!?+U\O7R\@("`@("`@ M("`@("`@("`@("`Q-S$@4V]U=&@@4W1R965T"B`@("`@("`@("`@("`@("`@ M("`@("`@("`@("`@("`@("`@("`@("`@("`@("`@($AO<&MI;G1O;BP@34$@ M,#$W-#@M.3$P,PK9``,`)@/2``$``0````T``0`!``$`)@,```````!,_P`` M`````)`!``````````!#;W5R:65R($YE=P`````````````````````````` M```````!``$``0$!``(!&0$!`!H!/@$!`#\!1P$!`$@!6`$!`%D!G`$!`)T! MZ@$!`.L!+P(!`#`"6`(!`%D"F@(!`)L"W0(!`-X")@,!`"<#)P,````````` M``````!D``&P`0%@`P$0!0'`!@%P"`$@"@'0"P&`#0$P#P'@$`&0$@%`%`'P '%0&@%P```&YD ` end From owner-ibis Fri Feb 7 13:56:08 1997 Received: from mpdgw2.symbios.com (mpdgw2.symbios.com [204.131.200.2]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id NAA02831 for ; Fri, 7 Feb 1997 13:56:08 -0800 (PST) Received: (from root@localhost) by mpdgw2.symbios.com (8.6.8.1/8.6.6) id OAA24322 for ; Fri, 7 Feb 1997 14:54:14 -0700 Message-Id: <199702072154.OAA24322@mpdgw2.symbios.com> Received: from chinook.co.symbios.com(153.72.234.195) by mpdgw2.symbios.com via smap (V1.3) id sma024249; Fri Feb 7 14:53:47 1997 Received: by chinook (1.38.193.4/16.2) id AA09894; Fri, 7 Feb 1997 14:53:02 -0700 From: Brian Hoffer Subject: IBIS packaging To: ibis@vhdl.org Date: Fri, 07 Feb 1997 14:53:02 MST X-Mailer: Elm [revision: 109.18] Hello, I am not sure whether this is where questions should be sent but will try anyway. I am a co-op student from Cincinnati working on IBIS with Symbios Logic, Inc. We are all kinda new with it so I have some pretty basic questions. My current problem is with the package models. I understand that the RLC matrices are representing properties of and between the pins, but do the pins have any correlation with the [Pin] list within the IBIS file. I guess my question is, how do you know what the pins within the package model are representing. I know this question is pretty vague, but I am very new at this so any feedback would be helpful. Thanks, Brian Hoffer if my return address is brianho@chinook, your reply will not get to me. It must be sent to brian.hoffer@symbios.com. Thanks again. From owner-ibis Sun Feb 9 12:21:16 1997 Received: from wile.nesa.com (8@[204.240.29.34]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id MAA07055 for ; Sun, 9 Feb 1997 12:21:12 -0800 (PST) Date: Sun, 9 Feb 1997 15:18:53 -0500 Message-Id: <199702092018.PAA11696@wile.nesa.com> Received: from petunia.nesa.com(204.240.29.131) by wile.nesa.com via smap (V1.3) id sma011694; Sun Feb 9 15:18:31 1997 X-Sender: esayre@mail.nesa.com X-Mailer: Windows Eudora Light Version 1.5.2 Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" To: ibis@vhdl.org From: "Dr. Edward P. Sayre" Subject: Seling on IBIS Internet e-mail conference I have specific problems with the following "helpful message". Please can we confine our discussions to technical subjects and leave the marketing to the marketeers!!! At 10:45 AM 2/7/97 -0500, Ezra D. Hall wrote: >conversion(It is at End Of Life). What else is out there? Do users now have >to convert IBIS models by hand? I am particularly interested since I am >creating IBIS models, and need to perform verification in a more efficient >manner than by hand. Any feedback would greatly be appreciated. A better solution might be to use a simulator that runs IBIS models directly. Our LineSim package is ideal for testing IBIS models and is very low cost. See our web site at: www.hyperlynx.com Thanks Ed Sayre +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ | NORTH EAST SYSTEMS ASSOCIATES, INC. | | ------------------------------------- | | "High Performance Engineering & Design" | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ | Dr. Ed Sayre e-mail: esayre@nesa.com | | NESA, Inc. http://www.nesa.com/ | | 636 Great Road Tel +1.508.897-8787 | | Stow, MA 01775 USA Fax +1.508.897-5359 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ From owner-ibis Mon Feb 10 07:02:13 1997 Received: from alcatel.fr (ns.alcatel.fr [194.133.58.131]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id GAA11006 for ; Mon, 10 Feb 1997 06:58:02 -0800 (PST) Received: from alcatel.fr (gatekeeper-ssn.alcatel.fr [155.132.180.244]) by mailgate.alcatel.fr (8.8.5/8.8.5) with ESMTP id RAA21649 for ; Mon, 10 Feb 1997 17:01:12 +0100 Received: from ln.cit.alcatel.fr (las40304.ln.cit.alcatel.fr [155.132.225.2]) by nsfhh5.alcatel.fr (8.7.3/8.7.3) with SMTP id PAA20306 for ; Mon, 10 Feb 1997 15:55:43 +0100 (MET) Received: from las41247.ln.cit.alcatel.fr by ln.cit.alcatel.fr (4.1/SMI-4.1) id AA20710; Mon, 10 Feb 97 15:58:05 +0100 Received: from las41247 (localhost) by las41247.ln.cit.alcatel.fr (4.1/SMI-4.1) id AA00365; Mon, 10 Feb 97 15:57:46 +0100 Sender: fitzpat1@ln.cit.alcatel.fr Message-Id: <32FF3769.167EB0E7@ln.cit.alcatel.fr> Date: Mon, 10 Feb 1997 15:57:45 +0100 From: John V Fitzpatrick Organization: Alcatel Telecom, Lannion, France X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.3_U1 sun4c) Mime-Version: 1.0 To: ibis@vhdl.org Subject: A BIRd for bus-switches Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello all, Below is a proposal for a BIRD dealing with series non-linear devices and bus switches. It is based on reflector discussions. Only one additional keyword is defined. Please note 3 features that can be criticised independently: * definition of series model between 2 pins * the addition of state information for crossbar switches * the reuse of [Pullup] and [Pulldown] curves by forcing one pin of the device to be either OPEN, GND or POWER. What's missing is information to model series L's and C's. This BIRD does not attempt to model the behavior of a bus-switch as a function of the control voltage applied to the transistor gate, a feature used in 5V-to-3.3V protection schemes. I'd appreciate your feedback before oficially submitting this BIRD. Regards, John -- John Fitzpatrick Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France Tel: +33(0)2.96.04.79.33 Fax: +33(0)2.96.04.85.09 ************************************************************************ ************************************************************************ BIRD ID#: N/A ISSUE TITLE: Modelling Series switchable devices REQUESTER: John Fitzpatrick, Alcatel DATE SUBMITTED: Pending DATE ACCEPTED BY IBIS OPEN FORUM: Pending ************************************************************************ ************************************************************************ STATEMENT OF THE ISSUE: IBIS cannot model series devices. IBIS cannot model switches. ************************************************************************ STATEMENT OF THE RESOLVED SPECIFICATIONS: One new keyword is defined under [Component]: [Series_Pin] Two additional Model_type values are allowed under the [Model] keyword: Series, Series_Switch. New measurement methods are defined for impedance tables. New text: |====================================================================== | Keyword: [Series_Pin] | Required: Optional |Description: Used to associate two pins joined by a series device. | Sub-Params: Pin1, Pin2, Model_Name, State |Usage Rules: Entries follow these rules: Only series pin pairs | are entered. The Pin1 column contains the pin number for | which input impedances are measured. The Pin2 column | contains the pin name of the other end of the series | device. The Model_Name colum contains the name of the | model corresponding to the series device. | The State column contains the optional name of the state | in which the series device, if it is a switch, can be ON. | In all other states, the device is OFF | | Column length limits are: | Pin1 5 characters max | Pin2 5 characters max | Model_Name 20 characters max | State 20 characters max | |Other Notes: | The order of the pins are important. The model | corresponds to measurements made at Pin1. | If the device is not symmetric, a different model may be | specified with the pin order swapped. | | In the case of a crossbar switch, all possible series | connections must be listed. Switching information is | contained under the State column. | If the device is not a switch, no State shall be | specified. | | The model name given here supersedes that given | under the the [Pin] keyword | [Series_Pin] |Pin1 Pin2 Buffer State 3 4 switchA AB-CD |switchA is buffer from 3 to |4 4 3 switchAneg AB-CD |Buffer from 3 to 4 is |non-symmetric 12 13 switchA AB-CD 12 14 switchB AC-BD |12 can be routed to 13 or |14 Change existing text from: | Model_type must be one of the following: | Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, | Open_sink, I/O_open_sink, Open_source, I/O_open_source, | Input_ECL, Output_ECL, I/O_ECL, and Terminator. | to: | Model_type must be one of the following: | Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, | Open_sink, I/O_open_sink, Open_source, I/O_open_source, | Input_ECL, Output_ECL, I/O_ECL, Terminator, Series or | Series_switch. | Add text to the special usage rules: | | Series This models a series device i.e. two | pins | The following impedance keywords can | be used: | [Pulldown] for through Z | [GND_clamp] for input Z | [POWER_clamp] for input Z (optional) | | Series_switch This models a series device that can | can be either ON or OFF. | The following impedance keywords can | used: | [Pulldown] for through Z when OFF | [Pullup] for through Z when ON | [GND_clamp] for input Z | [POWER_clamp] for input Z (optional) | Add the following text somewhere: | The definition of I/V tables are different for series devices. | **All measurements shall be made at Pin1.** | For [GND_Clamp], Pin2 shall be open. If the series device is a | switch, the switch shall be OFF. | A [POWER_clamp] curve may be included if a POWER clamp structure | is present. | To measure [Pulldown], Pin2 shall be shorted to ground. If the series | device is a switch, the switch shall be OFF. | If the device is a switch, [Pullup] is also needed: Pin2 shall be | shorted to POWER, the switch shall be ON. | | Note: POWER is the control voltage for the switch. If the switch | can be used for different POWER values, the different [Model]s | shall be included in the IBIS file. *********************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Bus-switches (ex: 74LVX3L383 from NS or 74CBT3383 from TI) are increasingly being used on high-speed boards. They cannot be modelled by IBIS 2.1. This BIRD allows the definition of a series device which is connected between any two pins. If this device is a non-linear resistor (e.g. a diode), then it can be described by an I/V table. This BIRD proposes to use the [Pulldown] table. To obtain this table, one of the pins of the series device is grounded. If the device is a switch, then it can be ON or OFF. This means that there needs to be an extra I/V table. This BIRD proposes to use the [Pullup] table. To avoid changing the definition of the [Pullup] table, one of the pins is connected to POWER. As suggested by Chris Reid, a state entry is added to allow crossbar switches be modelled. It is expected that the simulator detect these states, then ask the user to choose one of them. *********************************************************************** ANY OTHER BACKGROUND INFORMATION: This BIRD is designed to reuse as much as possible existing keywords. This will surely confuse model suppliers and users, but should facilitate acceptance of the BIRD by the simulator companies. (What does Pullup mean in the context of a diode???) The definition of the [Series Pin] keyword may need to be changed in order to take into account connectors, which are also series devices. This BIRD might be extendable to include linear amplifiers e.g.the 74ALB series announced by TI. Additional keywords might be defined to allow series inductors and capacitors be defined. From owner-ibis Tue Feb 11 12:34:32 1997 Received: from c11167-343dan.ece.ncsu.edu (c11167-343dan.ece.ncsu.edu [152.1.59.242]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id MAA00900; Tue, 11 Feb 1997 12:34:31 -0800 (PST) From: awglaser@eos.ncsu.edu Received: (from awglaser@localhost) by c11167-343dan.ece.ncsu.edu (8.8.4/EC02Jan97) id PAA06562; Tue, 11 Feb 1997 15:33:01 -0500 (EST) Message-Id: <199702112033.PAA06562@c11167-343dan.ece.ncsu.edu> Subject: New s2ibis2 update To: ibis-users@vhdl.org, ibis@vhdl.org Date: Tue, 11 Feb 1997 15:33:01 -0500 (EST) In-Reply-To: from "Bob Ross" at Feb 11, 97 12:03:00 pm X-Mailer: ELM [version 2.4 PL24/POP] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit S2ibis2 has now been updated to v1.1 This update is a bug-fix only, and does not provide any new functionality. It fixes the following bug: - When using Spectre for simulations, VI curves had the sign of the current value reversed (e.g. -1.2A should have been 1.2A) NOTE THAT THIS BUG ONLY APPEARED WHEN USING SPECTRE FOR SIMULATIONS. (Thanks to Ganesh Balamitran for the bug report.) The new distribution (which includes updated sources, new executables, and corrected example files) can be found at ftp://vhdl.org/pub/ibis/s2ibis/s2ibis2_v1.1/s2ibis2.tar.Z and ftp://ftp.eos.ncsu.edu/pub/vlsi/techreports/s2ibis2.tar.Z Also, please note that the new distribution does not include an AIX executable, as I no longer have access to an AIX machine. Regards, -- Alan Glaser "It's not a competition, ECE Dept. it's just a mint..." - K North Carolina State University From owner-ibis Wed Feb 12 12:25:08 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id MAA04673 for ; Wed, 12 Feb 1997 12:25:01 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Wed, 12 Feb 97 12:23 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 12 Feb 97 12:23 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 12 Feb 97 12:25 PST Message-Id: Date: Wed, 12 Feb 97 12:25 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: BIRD41 Modelling Series Switchable Devices To All: The BIRD sent out by John Fitzpatrick on February 10, 1997 is formally BIRD41. This is sent out again for the Open Forum Meeting Introduction and Discussion. Bob Ross Interconnectix ----------------------------------------------------------------------------- Hello all, Below is a proposal for a BIRD dealing with series non-linear devices and bus switches. It is based on reflector discussions. Only one additional keyword is defined. Please note 3 features that can be criticised independently: * definition of series model between 2 pins * the addition of state information for crossbar switches * the reuse of [Pullup] and [Pulldown] curves by forcing one pin of the device to be either OPEN, GND or POWER. What's missing is information to model series L's and C's. This BIRD does not attempt to model the behavior of a bus-switch as a function of the control voltage applied to the transistor gate, a feature used in 5V-to-3.3V protection schemes. I'd appreciate your feedback before oficially submitting this BIRD. Regards, John -- John Fitzpatrick Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France Tel: +33(0)2.96.04.79.33 Fax: +33(0)2.96.04.85.09 ************************************************************************ ************************************************************************ BIRD ID#: 41 ISSUE TITLE: Modelling Series Switchable Devices REQUESTER: John Fitzpatrick, Alcatel DATE SUBMITTED: February 12, 1997 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ************************************************************************ ************************************************************************ STATEMENT OF THE ISSUE: IBIS cannot model series devices. IBIS cannot model switches. ************************************************************************ STATEMENT OF THE RESOLVED SPECIFICATIONS: One new keyword is defined under [Component]: [Series_Pin] Two additional Model_type values are allowed under the [Model] keyword: Series, Series_Switch. New measurement methods are defined for impedance tables. New text: |====================================================================== | Keyword: [Series_Pin] | Required: Optional |Description: Used to associate two pins joined by a series device. | Sub-Params: Pin1, Pin2, Model_Name, State |Usage Rules: Entries follow these rules: Only series pin pairs | are entered. The Pin1 column contains the pin number for | which input impedances are measured. The Pin2 column | contains the pin name of the other end of the series | device. The Model_Name colum contains the name of the | model corresponding to the series device. | The State column contains the optional name of the state | in which the series device, if it is a switch, can be ON. | In all other states, the device is OFF | | Column length limits are: | Pin1 5 characters max | Pin2 5 characters max | Model_Name 20 characters max | State 20 characters max | |Other Notes: | The order of the pins are important. The model | corresponds to measurements made at Pin1. | If the device is not symmetric, a different model may be | specified with the pin order swapped. | | In the case of a crossbar switch, all possible series | connections must be listed. Switching information is | contained under the State column. | If the device is not a switch, no State shall be | specified. | | The model name given here supersedes that given | under the the [Pin] keyword | [Series_Pin] |Pin1 Pin2 Buffer State 3 4 switchA AB-CD |switchA is buffer from 3 to |4 4 3 switchAneg AB-CD |Buffer from 3 to 4 is |non-symmetric 12 13 switchA AB-CD 12 14 switchB AC-BD |12 can be routed to 13 or |14 Change existing text from: | Model_type must be one of the following: | Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, | Open_sink, I/O_open_sink, Open_source, I/O_open_source, | Input_ECL, Output_ECL, I/O_ECL, and Terminator. | to: | Model_type must be one of the following: | Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, | Open_sink, I/O_open_sink, Open_source, I/O_open_source, | Input_ECL, Output_ECL, I/O_ECL, Terminator, Series or | Series_switch. | Add text to the special usage rules: | | Series This models a series device i.e. two | pins | The following impedance keywords can | be used: | [Pulldown] for through Z | [GND_clamp] for input Z | [POWER_clamp] for input Z (optional) | | Series_switch This models a series device that can | can be either ON or OFF. | The following impedance keywords can | used: | [Pulldown] for through Z when OFF | [Pullup] for through Z when ON | [GND_clamp] for input Z | [POWER_clamp] for input Z (optional) | Add the following text somewhere: | The definition of I/V tables are different for series devices. | **All measurements shall be made at Pin1.** | For [GND_Clamp], Pin2 shall be open. If the series device is a | switch, the switch shall be OFF. | A [POWER_clamp] curve may be included if a POWER clamp structure | is present. | To measure [Pulldown], Pin2 shall be shorted to ground. If the series | device is a switch, the switch shall be OFF. | If the device is a switch, [Pullup] is also needed: Pin2 shall be | shorted to POWER, the switch shall be ON. | | Note: POWER is the control voltage for the switch. If the switch | can be used for different POWER values, the different [Model]s | shall be included in the IBIS file. *********************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Bus-switches (ex: 74LVX3L383 from NS or 74CBT3383 from TI) are increasingly being used on high-speed boards. They cannot be modelled by IBIS 2.1. This BIRD allows the definition of a series device which is connected between any two pins. If this device is a non-linear resistor (e.g. a diode), then it can be described by an I/V table. This BIRD proposes to use the [Pulldown] table. To obtain this table, one of the pins of the series device is grounded. If the device is a switch, then it can be ON or OFF. This means that there needs to be an extra I/V table. This BIRD proposes to use the [Pullup] table. To avoid changing the definition of the [Pullup] table, one of the pins is connected to POWER. As suggested by Chris Reid, a state entry is added to allow crossbar switches be modelled. It is expected that the simulator detect these states, then ask the user to choose one of them. *********************************************************************** ANY OTHER BACKGROUND INFORMATION: This BIRD is designed to reuse as much as possible existing keywords. This will surely confuse model suppliers and users, but should facilitate acceptance of the BIRD by the simulator companies. (What does Pullup mean in the context of a diode???) The definition of the [Series Pin] keyword may need to be changed in order to take into account connectors, which are also series devices. This BIRD might be extendable to include linear amplifiers e.g.the 74ALB series announced by TI. Additional keywords might be defined to allow series inductors and capacitors be defined. From owner-ibis Wed Feb 12 12:35:08 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id MAA04711 for ; Wed, 12 Feb 1997 12:35:06 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Wed, 12 Feb 97 12:33 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 12 Feb 97 12:33 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 12 Feb 97 12:35 PST Message-Id: Date: Wed, 12 Feb 97 12:35 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: BIRD40 Overshoot Nomenclature Retransmission for IBIS Open Forum Meeting and Vote Bob Ross Interconnectix To IBIS Committee: BIRD40 is a subparameter nomenclature change requested by the RAIL committee to the approved BIRD39 to deal with possible nomenclature confusion. The only modification is to change "Overshoot_high" to "S_overshoot_high", and "Overshoot_low" to "S_overshoot_low" for static overshoot. Bob Ross Interconnectix, Inc. ****************************************************************************** ****************************************************************************** BIRD ID#: 40 ISSUE TITLE: OVERSHOOT NOMENCLATURE REQUESTER: Bob Ross, Interconnectix, Inc. DATE SUBMITTED: 11/27/96 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: Overshoot in approved BIRD39 of IBIS uses Overshoot_high and Overshoot_low for static overshoots. The same notation is used in RAIL for any overshoot rule including maximum overshoot. To avoid confusion, the proposal here is to change the nomenclature to emphasize "static" overshoot. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The [Model Spec] subparameter nomenclature is changed as shown: BIRD39 BIRD40 Overshoot_high S_overshoot_high Overshoot_low S_overshoot_low The whole [Model Spec] keyword is presented here with changes to show the context of the revision. (Changes are noted by "|*" lines.) |============================================================================== | Keywords: [Model Spec] | Required: No |* Sub-params: Vinh, Vinl, Vinh+, Vinh-, Vinl+, Vinl-, S_overshoot_high, |* S_overshoot_low, D_overshoot_high, D_overshoot_low, | D_overshoot_time, Pulse_high, Pulse_low, Pulse_time | |Description: The [Model Spec] keyword defines four columns under which | specification subparameters are defined. | | The following subparamters are defined: | Vinh Input voltage threshold high | Vinl Input voltage threshold low | Vinh+ Hysteresis threshold high max Vt+ | Vinh- Hysteresis threshold high min Vt+ | Vinl+ Hysteresis threshold low max Vt- | Vinl- Hysteresis threshold low min Vt- |* S_overshoot_high Static overshoot high voltage |* S_overshoot_low Static overshoot low voltage | D_overshoot_high Dynamic overshoot high voltage | D_overshoot_low Dynamic overshoot low voltage | D_overshoot_time Dynamic overshoot time | Pulse_high Pulse immunity high voltage | Pulse_low Pulse immunity low voltage | Pulse_time Pulse immunity time | | Usage Rules: [Model Spec] must follow all other subparameters under the | [Model] keyword. | | For each subparameter contained in the first column, the | remaining three hold its typical, minimum and maximum values. | The entries of typical, minimum and maximum be must be placed | on a single line and must be separated by at least one white | space or tab or tab character. All four columns are required | under the [Model Spec] keyword. However, data is required | only in the typical column. If minimum and/or maximum values | are not available, the reserved word "NA" must be used | indicating the typical value by default. | | The minimum and maximum values are used for specifications | subparameter values that may track the min and max operation | conditions of the [Model]. Usually it is related to the | Voltage range settings. | | Unless noted below, each subparameter does not require having | any other subparameter. | | Vinh, Vinl rules: | The threshold subparameter lines | provide additional min and max column values, if needed. | The typ column values are still required and would be | expected to override the Vinh and Vinl subparameter values | specified elsewhere. Note: the syntax rule that require | inserting Vinh and Vinl under models remains unchanged | even if the values are defined under the [Model Spec] | keyword. | | To mimic a hysteresis effect, the values of Vinh and Vinl may | interchanged such that the Vinl value is larger than the Vinh | value. However, simulators may process this information | differently or report an error. | | Vinh+, Vinh-, Vinl+, Vinl- rules: | The four hysteresis subparmeters must all be defined before | the hysteresis threshold rules become effective. Otherwise | the standard threshold subparameters remain in effect. The | hysteresis thresholds shall be at the Vinh+ and Vinh- values | for a low-to-high transition, and at the Vinl+ and Vinl- | values for a high-to-low transition. | |* S_overshoot_high, S_overshoot_low rules: | The static overshoot sub-parameters provide the voltage values | for which the component is no longer guaranteed to function | correctly. | | D_overshoot_high, D_overshoot_low, D_overshoot_time rules: | The dynamic overshoot values provide a time window during | which the the overshoot may exceed the static overshoot limits | but be below the dynamic overshoot limits. D_overshoot_time is | required for dynamic overshoot testing. In addition, if |* D_overshoot_high is specified, then S_overshoot_high is | necessary for testing beyond the static limit. Similarly, if |* D_overshoot_low is specified, then S_overshoot_low is necessary | for testing beyond the static limit. | | Pulse_high, Pulse_low, Pulse_time rules: | The pulse immunity values provide a time window during which | a rising pulse may exceed the nearest threshold value but | be below the pulse voltage value and still not cause the | input to switch. Pulse_time is required for pulse immunity | testing. A rising response is tested only if Pulse_high is | specified. Similarly, a falling response is tested only if | Pulse_low is specified. The rising response may exceed the | Vinl value, but remain below the Pulse_high value. Similarily, | the falling response drop below the Vinh value, but remain | above the Pulse_low value. In either case the input is | regarded as immune to switching if the the responses are | within these extended windows. If the hysteresis thresholds | are defined, then the rising response shall use Vinh- as the | reference voltage, and the falling response shall use Vinl+ | as the reference voltage. | |------------------------------------------------------------------------------ [Model Spec] | Subparameter typ min max | | Thresholds | Vinh 3.5 3.15 3.85 | 70% of Vcc Vinl 1.5 1.35 1.65 | 30% of Vcc | | Vinh 3.835 3.335 4.335 | Offset from Vcc | Vinl 3.525 3.025 4.025 | for PECL | | Hysteresis | Vinh+ 2.0 NA NA | Overrides the Vinh- 1.6 NA NA | thresholds Vinl+ 1.1 NA NA Vinl- 0.6 NA NA | All 4 are required | | Overshoot | |* Next two lines are changed S_overshoot_high 5.5 5.0 6.0 | Static overshoot S_overshoot_low -0.5 NA NA D_overshoot_high 6.0 5.5 6.5 | Dynamic overshoot D_overshoot_low -1.0 -1.0 -1.0 | requires | D_overshoot_time D_overshoot_time 20n 20n 20n | & static overshoot | | Pulse Immunity | Pulse_high 3V NA NA | Pulse immunity Pulse_low 0 NA NA | requires Pulse_time 3n NA NA | Pulse_time | |============================================================================== ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Static overshoot defined as "S_overshoot_high" and "S_overshoot_low" is chosen as the best subparameter name change because it is defined as "static" overshoot in a manner parallel to "dynamic" overshoot for "D_overshoot_high" and "D_overshoot_low". It makes sense to let RAIL use the more generic "Overshoot_high" and "Overshoot_low" for absolute maximum or else for any rule setting that may be unrelated to device characteristics. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: BIRD40 replaces the approved BIRD39 text. Refer to BIRD39 for [Model Spec] Analysis. ****************************************************************************** From owner-ibis Wed Feb 12 15:27:11 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id PAA05537 for ; Wed, 12 Feb 1997 15:27:09 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Wed, 12 Feb 97 15:25 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 12 Feb 97 15:25 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 12 Feb 97 15:27 PST Message-Id: Date: Wed, 12 Feb 97 15:27 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org, kellee@hyperlynx.com Subject: Re: IBIS_CHK BUG8 Kelly: What you proposed is the realistic situation. Technically I believe it is a bug, but one can argue from some language in the specification that this is not a bug. In any case this is on the agenda for Friday's meeting. I propose this be documented rather than fixed. Best Regards, Bob Ross Interconnectix > Date: Fri, 07 Feb 1997 10:40:35 -0800 > To: ibis@vhdl.org > From: Kellee Crisafulli > Subject: Re: IBIS_CHK BUG8 > Hi all, > It is not obvious that to me that this is really a bug. It seems that > this user has the usage of > Pin and signal_name reversed. Please consider removing this from the bug > list. > "pin" should be 1,2,3,4 or AA1, BC1 etc. There really should never be a > conflict with the > reserved words. > >DESCRIPTION OF BUG: Reserved keywords used as pin numbers generate errors > > > >(This bug was discovered by Arthur Wong of IDT and reported December 5, > 1996.) > > > >| When pin "number" takes on the name of any of the reserved keywords > >| (gnd, power, nc, na), an error is reported. > > > >[Pin] signal_name model_name R_pin L_pin C_pin > >nc One_Pin NC > >gnd One_Pin GND > >na One_Pin NC > >power One_Pin POWER > >| From owner-ibis Wed Feb 12 18:40:28 1997 Received: from netcomsv.netcom.com (uucp6.netcom.com [163.179.3.6]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id SAA06977 for ; Wed, 12 Feb 1997 18:40:27 -0800 (PST) Received: from contec.UUCP by netcomsv.netcom.com with UUCP (8.6.12/SMI-4.1) id SAA09097; Wed, 12 Feb 1997 18:07:51 -0800 Received: from contec13.contec.COM by contec.COM (4.1/SMI-4.1) id AA00731; Wed, 12 Feb 97 16:34:10 PST Received: by contec13.contec.COM (5.0/SMI-SVR4) id AA10962; Wed, 12 Feb 1997 16:41:48 +0800 Date: Wed, 12 Feb 1997 16:41:48 +0800 From: dileep@contec.contec.COM (Dileep Divekar) Message-Id: <9702130041.AA10962@contec13.contec.COM> To: ibis@vhdl.org Subject: EIAJ I/O Interface Model Cc: dileep@contec.contec.COM X-Sun-Charset: US-ASCII I just wanted to follow up on Bob Ross's posting. Our sister company Applied Simulation Technology, Ltd., Japan is a member of the EIAJ I/O Interface Modeling Project Group. I have received the following short summary of the specification. EIAJ I/O Interface Model Summary 1) Model Coverage The model is not expressed as electrical characteristics at pins of IC package, but expressed as a network including internal circuits of package and I/O buffers. 2) Model Description The model is described as a circuit composed of electrical components and interconnections in SPICE format. This allows the description of ground/power circuits, complex structures of packages and modules. 3) Accurate Simulation Signals are added at input nodes of internal buffer circuits. This allows for accurate simulation by covering from internal buffer circuits to external load circuits. 4) Device Models Nonlinear device characteristics are described by 1- 2- or 3-dimensional tables. However, models such as SPICE may be used if IC companies like. 5) Separation of data of IC, Package and Module The data of IC, package and module are stored separately. It allows to make and supply data of IC, package and module independently. 6) Application Frequency The circuits of the model should be changed according to application frequency. The model can accomodate multiple model circuits for different application frequencies. 7) EMI Simulation Package data will be extended to include material and 3-dimensional shapes for accurate EMI simulation in the future. 8) Relation with IBIS The model is extended from IBIS for more complicated application. Both models might be used according to applications. Translators between both models might be developed. From owner-ibis Thu Feb 13 09:57:34 1997 Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id JAA09236 for ; Thu, 13 Feb 1997 09:57:34 -0800 (PST) Received: from ichips.intel.com (ichips.intel.com [134.134.50.200]) by ormail.intel.com (8.8.4/8.8.4) with ESMTP id JAA22033 for ; Thu, 13 Feb 1997 09:55:53 -0800 (PST) Received: from ichips.intel.com by ichips.intel.com (8.7.4/jIII) id JAA05478; Thu, 13 Feb 1997 09:51:30 -0800 (PST) Message-Id: <199702131751.JAA05478@ichips.intel.com> To: ibis@vhdl.org Subject: BIRD 36.1, Board Level Components Date: Thu, 13 Feb 1997 09:56:00 -0800 From: Stephen Peters Hello fellow IBISains: As discussed at the face to face, bird 36 (packaging and connectors), has been seperated into two birds; one dealing with board level packaginge (SIMM modules, etc.) the other dealing stricly with connector modeling. Following is BIRD36.1, which is the proposal for packaging modeling. As mentioned in the text of the bird, this proposal deals only with un-coupled transmission line descriptions of a PCB component. Boards that require full blown (coupled) analysis should be described using the EDIF physical description. Connector modeling will be described in a seperate, forthcomming, bird. Regards, Stephen Peters Intel Corp. ------------------ cut here --------------------------------- Buffer Issue Resolution Document (BIRD) BIRD ID#: 36.1 ISSUE TITLE: Electric Descriptions of Boards REQUESTER: Stephen Peters, Hank Herrmann DATE SUBMITTED: Feb 13, 1997 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: There is a need to describe SIMM modules and related type components that consist of one or more ICs mounted on a PCB board that connects them to a system thru a set of pins. The following BIRD proposes a new type of file called .ebd (Electrical Board Description) that addresses this need. This proposal does not encompass an electrical description of connectors and other interconnect devices. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The following text is placed in the specification after the .pkg file description and before the [End] keyword description. ==================== ELECTRICAL BOARD DESCRIPTION ==================== An Board Level Component is defined as a part that connects one or more IC packages to another part or board thru a set of user visible pins. For example, a SIMM module is an board level component in that it connects several DRAM packages to a PCB thru an edge connector. To provide a simple electrical description of the connection between the pins of the board level component and the IC packages, an electrical board description file (a .ebd file) is defined. A fundamental assumption regarding the electrical board description is that the inductance and capacitance parameters listed in the file are derived with respect to well defined reference plane(s) within the board. Also, this current description does not allow one to describe electrical (inductive or capacitive) coupling between paths. It is recommended that if coupling is an issue than an electrical description be extracted from the boards physical parameters. What is, and is not, included in an Electrical Board Description is defined by its boundaries. For the definition of the boundaries, see the Description section under the [Path Description] Keyword. Usage Rules: A .ebd file is intended to be a stand alone file, not associated with any .ibs file. Board level component descriptions are stored in a file whose name looks like .ebd, where must conform to the naming rules given in the general syntax section of this specification. The .ebd extension is mandatory. Contents: A .ebd file is structured similar to a standard IBIS file. It must contain the following keywords, as defined in the IBIS specification: [IBIS Ver], [File name], [File rev], and [End]. It may also contain the following optional keywords: [Comment char], [Date], [Source], [Notes], [Disclaimer] and [Copyright]. The actual board level component description is contained between the keywords [Begin Board Description] and [End Board Description], and includes the keywords listed below. [Begin Board Description] [Manufacturer] [Number of Pins] [Pin List] [Path Description] [Reference Designator Map] [End Board Description] More than one [Begin Board Description]/[End Board Description] keyword pair is allowed in a .ebd file. |============================================================================= | Keyword: [Begin Board Description] | Required: Yes |Description: Marks the beginning of an Electrical Board Description. |Usage Rules: The keyword is followed by the name of the board level | component. If the .ebd file contains more than one [Begin | Board Description] keyword, then each name must be unique. | The length of the component name must not exceed 40 characters | in length, and blank characters are allowed. For every | [Begin Board Description] keyword there must be a | matching [End Board Description] keyword. |----------------------------------------------------------------------------- [Begin Board Description] 16Meg X 8 Simm Module | |============================================================================= | Keyword: [Manufacturer] | Required: Yes |Description: Declares the manufacturer of the part(s) that use this .ebd | file. |Usage Rules: Following the keyword is the manufacturers name. It must not | exceed 40 characters, and can include blank characters. Each | manufacturer must use a consistent name in all .ebd files. |----------------------------------------------------------------------------- [Manufacturer] Quality SIMM Corp. | |============================================================================= | Keyword: [Number of Pins] | Required: Yes |Description: Tells the parser the number of pins to expect. Pins are any | externally accessible electrical connection to the part. |Usage Rules: The field must be a positive decimal integer. | Note: The simulator must not limit the Number of Pins to any | value less than 1,000. |----------------------------------------------------------------------------- [Number of Pins] 128 | |============================================================================= | Keyword: [Pin List] | Required: Yes |Description: Tells the parser the pin names of the parts user accessible | pins. It also informs the parser which pins are connected to | power and ground. |Sub-params: pin_name signal_name |Usage Rules: Following the [Pin List] keyword are two columns. The first | column lists the pin name, the second lists the data book | name of the signal connected to that pin. There must be as many | pin_name/signal_name rows as there are pins given by the | preceding [Number of Pins] keyword. Pin names must be the | alphanumeric external pin names of the part. The pin | names cannot exceed eight characters in length. Any pin | associated with a signal name that begins with "GND" or | "POWER" will be interpreted as connecting to the boards ground | or power plane. In addition, NC is a legal signal name and | indicates that the Pin is a 'no connect'. | |----------------------------------------------------------------------------- | A SIMM BOARD EXAMPLE | [Pin List] pin_name signal_name A1 GND A2 data1 A3 data2 A4 POWER5 | this pin connects to 5v A5 NC | a no connect pin | . | . A22 POWER3.3 | this pin connects to 3.3v B1 casa | . | . |etc. | |============================================================================ | Keyword: [Path Description] | Required: Yes |Description: This keyword allows the user to describe the connection | between the user accessible pins of a part and the pins of | the ICs mounted on that part. Each pin to node connection is | divided into one or more cascaded "sections", where each | section is described in terms of it's L/R/C per unit length. | The Fork and Endfork subparameters allow the path to branch | to multiple nodes, or another pin. A path description is | required for each pin who's signal name is not "GND", "POWER" | or "NC". | | BOARD DESCRIPTION AND IC BOUNDARIES: | In any system, each part interfaces with another part at some | boundary. Every part model must contain the components | necessary to represent the behavior of the part being modeled | within its boundaries. The boundary definition depends upon | the parts being represented by the model. | | For CARD EDGE CONNECTIONS such as a SIMM or a PC Daughter | Card plugged into a SIMM Socket or Edge Connector, the | boundary should be at the end of the board card edge pads as | they emerge from the connector. | | For any THROUGH-HOLE MOUNTED PART, the boundary will be at | the surface of the board on which the part is mounted. | | SURFACE MOUNTED PART models end at the outboard end of their | recommended surface mount pads. | | If the board level component contains an UNMATED CONNECTOR, | the unmated connector will be described in a separate file, | with it's boundaries being as described above for the | through-hole or surface mounted part. | | Sub-params: Len, L, R, C, Fork, Endfork, Pin, Node |Usage Rules: Each individual connection path (user pin to node(s)) | description begins with the | [Path Description] keyword and a path name, followed by the | subparameters used to describe the path topology and the | electrical characteristics of each section of the path. The | path name must not exceed 40 characters, blanks are not allowed, | and each occurrence of the [Path Description] keyword must be | followed by a unique path name. The individual subparameters | are broken up into those that describe a sections electrical | properties, and those that describe the topology of a path. | | SECTION DESCRIPTION SUBPARAMETERS: | The Len, L, R, and C subparameters specify the length, the | series inductance and resistance and the capacitance to ground | of each section in a path description. | Len The physical length of a section. Lengths are given | in terms of arbitrary 'units'. Any non-zero length | requires that the parameters that follow must be | treated as distributed elements by the simulator. | L The series inductance of a section, in terms of | 'inductance/unit length'. For example, if the total | inductance of a section is 3.0nH and the length of the | section is 2 'units', the inductance would be listed | as L = 1.5nH (i.e. 3.0 / 2). | C The capacitance to ground of a section, in terms of | capacitance per unit length. | R The series DC (ohmic) resistance of a section, in | terms of ohms per unit length. | | TOPOLOGY DESCRIPTION SUBPARAMETERS: | The Fork and Endfork subparameters denote branches from the | main pin-to-node or pin-to-pin connection path. The Node | subparameter is used to reference an external component | description file. The Pin subparameter is used to indicate | the point at which a path connects to a user visible pin. | Fork This subparameter indicates that the sections | following (up to the Endfork subparameter) are part | of a branch off of the main connection path. This | subparameter has no arguments. | Endfork This subparameter indicates the end point of a | branch. For every Fork subparameter there must be a | corresponding Endfork subparameter. As with the Fork | subparameter, the Endfork subparameter has no arguments. | Node reference_designator.pin | This subparameter is used when the connection path | connects to a pin of another, externally defined part. | The arguments of the Node subparameter indicate the pin | and reference designator of the external component. The | pin and reference designator portions of the argument are | separated by a period ("."). The reference designator is | mapped to an external component description (another .ebd | file or .ibs file) by the [Reference Designator Map] | Keyword. Note that a Node MUST reference a model of | a passive or active component. A Node is not an | arbitrary connection point between two elements or | paths. | Pin This subparameter is used to mark the point at which | a path description connects to a user accessible pin. | Every path description must contain at least one | occurrence of the Pin subparameter. It may also contain | the reserved word NC. The value of the Pin subparameter | must be one of the pin names listed in the [Pin List] | section. | | Using The Subparameters to Describe Paths: | A section description begins with the Len subparameter and | ends with the slash (/) character. The value of the Len, L, | R and C subparameters and the subparameter itself are separated | by an equals sign (=); whitespace around the equals sign is | optional. The Fork, Endfork, Node and Pin subparameters are | placed between section descriptions (i.e. between the concluding | slash of one section and the 'Len' parameters that starts | another). The arguments of the Pin and Node subparameter are | separated by white space; no equal sign nor slash (/) | character is used. | | Specifying a Len or L/R/C value of zero is allowed. If | Len = 0 is specified, then the L/R/C values are the total | for that section. If a non-zero length is specified, then | the total L/R/C for a section is calculated by multiplying | the value of the Len subparameter by the value of the L, | R or C subparameter. However, as noted below, if a non- | zero length is specified, that section MUST be treated as | distributed elements. | | Legal Subparameter Combinations for Section Descriptions: | | A) Len, and one or more of the L, R and C subparameters. If | the Len subparameter is given as zero, then the L/R/C sub- | parameters represent lumped elements. If the Len subparameter | is non-zero, then the L/R/C subparameters represent distributed | elements and both L and C must be specified, R is optional. | | B) The first subparameter following the [Path Description] | keyword must be 'Pin', followed by one or more section | descriptions. The path description can terminate in a node, | another pin or the reserved word, NC. | |--------------------------------------------------------------------------- | | | AN EXAMPLE PATH FOR A SIMM MODULE | [Path Description] CAS_2 Pin J25 Len = 0.5 L=8.35n C=3.34p R=0.01 / Node u21.15 Len = 0.5 L=8.35n C=3.34p R=0.01 / Node u22.15 Len = 0.5 L=8.35n C=3.34p R=0.01 / Node u23.15 | | A DESCRIPTION USING THE FORK AND ENDFORK SUBPARAMETERS | [Path Description] PassThru1 Pin B5 Len = 0 L=2.0n / Len = 2.1 L=6.0n C=2.0p / Fork Len = 1.0 L= 1.0 C= 2p Node u23.15 Endfork Len = 1.0 l = 6.0n C=2.0p / Pin A5 | |============================================================================= | Keyword: [Reference Designator Map] | Required: Yes, if any of the path descriptions use the Node subparameter. |Description: Indicates the linkage between a reference designator and the | external part it represents. |Usage Rules: The [Reference Designator Map] keyword must be followed by a | list of all of the reference designators defined in the Node | subparameter under the [Path Description] keyword. Each | reference designator is followed by the Name of the part to which | it is linked and the terms are separated by whitespace. The part | Name may be another .ebd or .ibs model. A referenced .ebd model | may be internal to the calling .ebd file or it may be an external | file with an appropriately given pathname. |----------------------------------------------------------------------------- [Reference Designator Map] | | EXTERNAL PART REFERENCES | u23 80286.ibs u24 SIMM.ebd u25 C:\LIBS\LS244.ibs | | AN INTERNALLY DEFINED .ebd MODEL OF A 10K RESISTOR | u26 R10K | |============================================================================= | Keyword: [End Electrical Description] | Required: Yes |Description: Marks the end of an Electrical Interconnect Description. |Usage Rules: This keyword must come at the end of each complete electrical | interconnect model description. | | Optionally, a comment may be added after the [End Electrical | Description] keyword to clarify which board model has | ended. |----------------------------------------------------------------------------- [End Electrical Description] | End: 16Meg X 8 Simm Module | ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: From owner-ibis Thu Feb 13 10:38:35 1997 Received: from marceau.fm.intel.com (marceau.fm.intel.com [132.233.247.8]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA09335 for ; Thu, 13 Feb 1997 10:38:34 -0800 (PST) Received: from fmmail.fm.intel.com by marceau.fm.intel.com (8.8.4/10.0i); Thu, 13 Feb 1997 18:37:07 GMT Received: (from ccmgate@localhost) by fmmail.fm.intel.com (8.7.4/8.7.3) id KAA14797 for ibis@vhdl.org; Thu, 13 Feb 1997 10:33:09 -0800 (PST) Received: by ccm.fm.intel.com (ccmgate 3.2 #2) Thu, 13 Feb 97 10:33:09 PST Date: Thu, 13 Feb 97 10:16:00 PST From: Arpad Muranyi Message-ID: To: scotts%actel.com_at_internet_gateway@ccm.fm.intel.com, ibis@vhdl.org Subject: Re: Lab data vs. Spice data Text item: Scott, On a few occasions I have made IBIS models from lab measurements. Arpad Muranyi Intel Corporation ============================================================================ Hello Ibis folks, I'd like to compare notes with those who have produced IBIS files from *BOTH* Spice and lab measurements. Please respond to me directly (not through the reflector) if you have done this, particularly if yours is a CMOS process. Thanks, -Scott Schlachter Actel Corporation scotts@actel.com Sunnyvale, CA Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Subject: Lab data vs. Spice data To: ibis@vhdl.org, ibis-users@vhdl.org Message-Id: <9702071723.AA09450@ricky.sun_net> From: scotts@actel.com (Scott Schlachter) Date: Fri, 7 Feb 97 09:23:59 PST Received: by ricky.sun_net (4.1/SMI-4.1) id AA09450; Fri, 7 Feb 97 09:23:59 PST Received: from ricky.sun_net ([190.9.2.228]) by actel.com (4.1/SMI-4.1) id AA08540; Fri, 7 Feb 97 09:24:06 PST Received: from actel.com (rigel-g.actel.com [204.33.232.16]) by vhdl.vhdl.org (8 .8.5/8.8.3) with SMTP id JAA02119; Fri, 7 Feb 1997 09:23:45 -0800 (PST) Received: from vhdl.vhdl.org (vhdl.vhdl.org [198.31.14.3]) by ormail.intel.com (8.8.4/8.8.4) with ESMTP id JAA12587; Fri, 7 Feb 1997 09:30:28 -0800 (PST) Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by relay.jf.i ntel.com (8.8.4/8.7.3) with ESMTP id JAA15539; Fri, 7 Feb 1997 09:30:33 -0800 (P ST) Return-Path: owner-ibis@vhdl.vhdl.org From owner-ibis Fri Feb 14 15:50:24 1997 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id PAA15618 for ; Fri, 14 Feb 1997 15:50:23 -0800 (PST) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id PAA09993 for ; Fri, 14 Feb 1997 15:50:22 -0800 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (V3.1.1) id xma009350; Fri, 14 Feb 97 15:49:29 -0800 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA10576 for ibis@vhdl.org; Fri, 14 Feb 97 15:47:54 -0800 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA01022; Fri, 14 Feb 97 15:50:14 PST Date: Fri, 14 Feb 97 15:50:14 PST From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9702142350.AA01022@rockie.nsc.com> To: ibis@vhdl.org Subject: IBIS Roster update for 1997 IBIS fans: Every year we need to take a look at the IBIS roster and update all the fields. This helps the customer, user and anyone interested in IBIS to talk to all of you. Pls take a moment to review your company information and make changes if required. You may E-mail the changes back to me and I will make the necessary updates. At least, I need a response from you so I know your information is valid. If no response is received, we make take you off the roster. Best Regards, Syed Vice-Chair ANSI/EIA-656 National Semiconductor ============================================================================ 1996 EIA IBIS Committee Participation Roster As of 2/14/97 (updated periodically) Previous participation under old95 and old96 directories Submit changes/updates to: huq@rockie.nsc.com (408) 721-4874, Fax (408) 721-4785 ============================================================================ NOTE: This roster lists companies and organizations that have either participated in creating the IBIS spec or are creating/distributing/using IBIS models. Other than the specific statements of support under each organization's name, no support nor endorsement of the specification is implied. Companies designated by * are members of the EIA IBIS Open Forum. ============================================================================ Alcatel Contact: John Fitzpatrick Email: John.Fitzpatrick@ln.cit.alcatel.fr Phone: + 33 96 04 79 33 Fax: + 33 96 04 85 09 Address: 4 rue Louis de Broglie 22304 Lannion France Support: IBIS models used in CAD tool chain. Tag-line: Telecommunication equipment manufacturer. * AMP Incorporated Contact: Martin G. Freedman Email: mgfreedm@amp.com Phone: (717) 592-6270 Fax: (717) 592-6179 Address: M.S. 210-20 P.O. Box 3608 Harrisburg, PA 17105-3608 Harrisburg, PA 17105-3608 Support: AMP Global Technology group is investigating the IBIS format for modeling connector electrical performance. We are actively supporting the work of the IBIS Open Form in this area. Tag-line: AMP is the world's largest supplier of electrical connectors. Electrical performance models, in SPICE format, are currently available for high speed interconnects. Anacad EES Contact: Steffen Rochel Email: steffen_rochel@mentorg.com Phone: (408) 451 5820 Fax: (408) 451-5554 Address: Anacad EES Mentor Graphics 1001 Ridder Park San Jose, CA 95131-2314 Support: Anacad can translate IBIS descriptions into models using their analog behavioral modeling language HDL-A. Together with Eldo and a VHDL simulator, highly accurate investigations of mixed signal designs are possible. Tag-line: * Applied Simulation Technology, Inc (formerly Contec CAE, Ltd.) Contact: Dileep Divekar Email: dileep@apsimtech.com Phone: (408) 434-0967, ext. 100, Fax: (408) 434-1003 Address: 2188 Bering Drive San Jose, CA 95131 Support: Applied Simulation Technology tools support IBIS models. Tag-line: Applied Simulation Technology offers accurate, state of the art signal integrity, EMI / EMC and circuit simulation tools. * Cadence Design Systems, Inc. Contact: C. Kumar Email: cpk@cadence.com Phone: (508) 262-6488, Fax: 508-262-6600 Address: 270 Billerica Rd, Chelmsford, MA 01824 Support: Cadence fully supports IBIS models. Cadence's DF/SigNoise product family offers a vendor-specific, IBIS compatible signal integrity library of over 7000 components. Cadence also provides a translator program enabling the conversion of IBIS 1.1 and 2.1 files to Cadence library format. Tag-line: Cadence, the worldwide leader in electronic design automation, combines leading-edge technology and a complementary set of services to accelerate and advance the overall performance engineering of high-speed electronic systems. * Cypress Semiconductor Contact: Bruce Wenniger Email: bw@cypress.com Phone: (408) 943-2688, Fax: (408) 943-2843 Address: 3901 N. First Street , MS2.2-3 San Jose, CA 95134 Support: Cypress will generate IBIS models for the integrated circuits it designs and manufactures. Tag-line: Cypress is a leader in the development and production of high- performance CMOS and BiCMOS digital integrated circuits. Digital Equipment Corp. Contact: Jeff L. Chu Email: chu@rock.enet.dec.com Phone: (508) 568-4197, Fax: (508) 568-4367 Address: 77 Reed Road, HLO2-3/K13 Hudson, MA 01749 Support: Digital will generate IBIS models for its own chip products, including the line of ALPHA AXP microprocessors, peripheral and communication chips, as needed, and support IBIS models in in-house simulation tools. Tag-line: Digital, maker of the world's fastest microprocessor, is also a leading developer of computer systems, and networking and communication products, including PCI. EIA/Electronic Information Group Contact: Patti Rusher Email: pattir@eia.org Phone: (703) 907-7545. Fax: (703) 907-7501 Address: 2500 Wilson Blvd. Arlington, VA 22201 Support: Tag-line: * Hewlett-Packard/HP EEsof Division Contact: Karl Kachigan Email: karlk@sr.hp.com Phone: (707) 577-3949, Fax: (707) 577-5260 Address: 1400 Fountaingrove Parkway Santa Rosa, CA 94503 Support: Support IBIS models in HP 85240 Picosecond Interconnect Modeling Suite for interconnect model development and analysis. Tag-line: HP EEsof is a leading supplier of high frequency analog (RF/Microwave) design and modeling tools. * HyperLynx Contact: Kellee Crisafulli Email: kellee@hyperlynx.com Phone: (206) 869-2320, Fax: (206) 881-1008 Address: 17641 N.E. 67th. Ct. Redmond, WA 98052 Support: Several signal integrity and EMC analysis tools are available: LineSim: A simulator using schematic data input, reads IBIS files as part of its native library support. Ships with a set of IBIS libraries. BoardSim: A simulator using PCB geometry data input from numerous PCB layout packages, also natively supports IBIS files. Ships with a set of IBIS libraries. SpectralSim: An add-on tool for BoardSim and LineSim that provides EMC analysis using a spectrum analyzer. Tag line: HyperLynx, Inc. is the industry's leading supplier of affordable, accurate, Windows based signal-integrity and EMC software. IBM Corporation Contact: Joseph C. (Jay) Diepenbrock Email: jayd@vnet.ibm.com Phone: (919) 543-8804 Fax: (919) 543-6552 Address: Networking Hardware. Div. PDLA/656 P.O. Box 12195 Research Triangle Park, NC 27709 Support: Tag-line: * INCASES Engineering GmbH Contact: Werner Rissiek, Olaf Rethmeier Email: wrissiek@pad.incases.com, orethmeier@pad.incases.com Phone: ++49-5251-150-620, ++49-5251-150-625, Fax: ++49-5251-150-700 Address: INCASES Engineering GmbH Vattmannstrasse 3 D-33100 Paderborn, Germany Support: INCASES provides the simulation packages INSIDE (INCASES Signal Integrity Diagnostic Environment) for signal integrity analysis and COMORAN (COMputation of RAdiatioN) for radiation analysis within its product family EMC-Workbench. INCASES provides the IBIS-to-INCASES converter that bases on the IBIS Golden Parser 2.1. The converter creates INCASES macromodels, corresponding reference lists, and further information for the components in a fully automatic way. The INCASES Library management tool EXLIN provides specific features to import the new models generated by the converter into respective libraries. EXLIN checks for consistency, supports the defintion of user specific IDs, and allows to reference the models also for other components which show a similar behaviour as the original ones. Detailed information is available on request. Tag-line: INCASES Engineering, GmbH, Germany, founded on November 1, 1994, is a supplier of design automation software and consulting services to the electronic design automation (EDA) market, focusing on EMC and 'Design for Manufacturability'. INCASES develops, sells, and supports two major product lines: THEDA, acquired from Computervision Corporation and EMC-Workbench, acquired from Siemens Nixdorf Informationssysteme AG. * Intel Corporation Contact: Will Hobbs Email: Will_Hobbs@ccm2.jf.intel.com Phone: (503) 696-4369, Fax: (503) 696-4210 Address: 5200 NE Elam Young Pkwy, JF1-57 Hillsboro, OR 97124 Support: Intel is a strong supporter of the IBIS standard, and provides IBIS models for many of its components. For a list of supported components, send the following message to archive@vhdl.org: path send pub/ibis/models/intel readme index /pub/ibis/models/intel For information on models of unannounced products, contact your local Intel field sales office. Tag-line: Intel, the world's largest chip maker, is also a leading manufacturer of personal computer networking and communications products. * Interconnectix (A Mentor Graphics Company) Contact: Bob Ross Email: bob@icx.com Phone: (503) 684-6641, Fax: (503) 639-3469 Address: 10220 S.W. Nimbus Ave., K4 Portland, Oregon 97223 Support: The Interconnect Synthesis (IS) product supports the major extensions of IBIS Version 2.1. Interface extensions for component and model selection and termination generation allow IBIS formatted data to be used in "what if" investigations and automatic synthesis operations. Tag-line: The leading Interconnect Synthesis Company KAW/USA Contact: Dan Aleksandrowicz Email: dan@kaw.com Phone: (603) 886-8711, Fax: (603) 881-8763 Address: 39 Simon Street Nashua, NH 03060 Support: Tag-line: A total concept solution for P.C.B. by design, simulation, consulting, training, analysis and schematic capture; by using Mentor-Board Station/Design Architect, Cadence/Allegro/Concept/ Boardquest, Unicad and CCT-Router. Mentor Graphics Corp. Contact: Greg Doyle Email: greg_doyle@mentorg.com Phone: (408) 451-5753, Fax: (408) 451-5538 Address: 1001 Ridder Park Drive San Jose, CA 95131 Support: Mentor supports IBIS by using Quad Design and Intel IBIS models. Tag-line: The Integrated System Design Company Meta-Software Contact: Sanjay Gangal Les Spruiell Solutions Marketing Group Product Line Group Email: sanjayg@metasw.com less@metasw.com Phone: (408) 369-5244 (408) 369-5459 Address: 1300 White Oaks Rd. Campbell, CA 95008 Support: Tag-line: MicroSim Corp. Contact: Ralph Perez Email: Phone: (714) 770-3022, Fax: (714) 455-0554 Address: 20 Fairbanks Irvine, CA 92718 Support: MicroSim can automatically generate PSpice models for vendors who provide data in a file format conforming to the IBIS Ver 1.1 specification. The models can then be simulated with PSpice. MicroSim has made IBIS models for Intel's Pentium processor 82430 PCIset available to customers. Tag-line: MicroSim Corp. - The Desktop EDA Company - provides technically sophisticated software for schematic entry, simulation, programmable logic synthesis, and signal integrity analysis. * Mitsubishi Electric Contact: Tom Cao Email: tcao@msai.mea.com Phone: (919) 479-3362, Fax: (919) 479-3309 Address: Three Diamond Lane Durham, NC 27705 Support: Tag-line: * Motorola Contact: Ahmed Omer Ron Werner Email: R28450@email.sps.mot.com p24742@email.mot.com Phone: (512) 794-4248 (602) 441-8593 Fax: (512) 794-4250 (602) 441-2363 Address: 5918 W. Courtyard Dr., Suite 200 8201 E. McDowell Road Austin, TX 78730 Scottsdale, AZ 85252 Support: Tag-line: * National Semiconductor Corp. Contact: Syed B.Huq Email: huq@rockie.nsc.com Phone: (408) 721-4874, Fax:(408)721-4785 Address: 2900 Semiconductor Drive, M/S A-2595 Santa Clara, CA 95052 Support: National Semiconductor provides IBISv1.1 and IBISv2.1 models for selected product lines. Refer to www.natonal.com for the latest available models. Tag-line: National Semiconductor provides technologies for moving and shaping information. The company focuses on communications, analog, and personal systems markets, and is the fourth largest U.S semiconductor merchant. * NCR Corporation Contact: Dave Moxley Email: David.Moxley@columbiasc.ncr.com Phone: (803) 939-6495, Fax: (803) 939-7317 Address: 3325 Platt Springs Rd. W. Columbia, SC 29170 Support: NCR supports the ANSI/EIA-656 standard and is a user of IBIS models. Tag-line: * NEC Corporation Contact: Hiroshi Sakuma Email: sakuma@lsi.tmg.nec.co.jp Phone: +81 -44-435-1501(DIR), Fax: +81 -44-435-1887 Address: Design Sys. Dept., System ASIC Div., NEC Corp. 1753 Shimonumabe, Nakahara-ku Kawasaki Japan 211 Support: NEC is willing to write some IBIS models and a model generator for some of its LSI components. Tag-line: North Carolina State University Contact: Michael Steer, Paul Franzon, Steve Lipa Email: mbs@ncsu.edu paulf@ncsu.edu slipa@eos.ncsu.edu Phone: 919-515-5191 919-515-7351 919-515-3947 FAX for all three: 919-515-5523 Address: ECE Dept. Box 7911 NC State Univ. Raleigh, NC 27695-7911 Support: (as of 2/94) A Spice to IBIS converter is being developed. A measurement based procedure is being developed for extracting IBIS models. A yacc/lex parser for IBIS models is being develped. All software and techniques will be put in the public domain. Tag-line: * Quad Design Technology, Inc. Contact: Jon Powell Email: jonp@qdt.com Phone: (805) 988-8250, Fax: (805) 988-8259 Address: 1385 Del Norte Rd. Camarillo, CA 93010 Support: Quad Design has a translation program that translates from IBIS format to Quad Design .mod format. This translator uses the Golden Parser code with enhancements to warn of malformed (yet legal) models. The translator supports user input to be able to select from the min-typ-max range of IBIS data. This program (IBIS2XTK) is available now and is distributed with XTK Crosstalk and transmission line simulation tool kit. Tag-line: Quad Design is a leading supplier of Signal Integrity and Timing tools for high speed digital designs. * Quantic Laboratories, Inc. Contact: Mike Ventham Email: ventham@quantic.mb.ca Phone: (204) 942-4000, Fax: (204) 957-1158 Address: 12th Floor, 191 Lombard Ave Winnipeg, Manitoba, R3B 0X1 Canada Support: Quantic provides an IBIS reader (based on the Golden Parser) that will read IBIS models and automatically generate data files for Phidias (our graphical VI curve device modellor) and database files that associate the component definitions with the pin models. From Phidias, both SPICE models for PCB Greenfield (our pre and post layout transmission line simulator) and models for BoardScan, (our PC board screener for signal integrity and crosstalk problems) can be created. This is available now for Quantic customers. Tag-line: Quantic Laboratories Ltd has been the leading supplier of field solvers and signal integrity tools since 1983. This expertise has now been extended to Electromagnetic Compatibility (EMC) tools. Symmetry Design Systems, Inc. Contact: Andy Hughes Email: andy@symmetry.com Phone: (415) 949-9600, Fax: (415)-949-0831 Address: 477 S. San Antonio Rd. #200 Los Altos, Ca. 94022 Support: Symmetry provides IBIS modeling tools and services. Symmetry's modeling tool MODPEX can create IBIS models based on measured device characteristics or data sheet information. MODPEX can translate IBIS models to SPICE descriptions for testing and documentation or translate SPICE models to IBIS. Tag-line: Symmetry is a dedicated supplier of tools and services for creating, testing, and documenting SPICE and IBIS component models for electronic system design. Tanner Research, Inc. Contact: Peter Parrish, Ed Miller, Scott Wedge Email: peter.parrish@tanner.com, ed.miller@tanner.com, scott.wedge@tanner.com Phone: (818) 792-3000 FAX: (818) 792-0300 Address: 180 North Vinedo Avenue Pasadena, CA 91107 Support: Tanner Research is currently developing IBIS model support for its MCM design tools. Tag-line: Affordable ASIC, MCM, and MEMS design tools from Tanner Research offer high performance and easy to use CAE solutions for PCs, Macintoshes, and UNIX workstations. Tanner Tools provide a complete design solution including schematic capture, circuit and gate level simulation, signal integrity analysis, auto place and route, layout editing and layout verification. * Texas Instruments, Inc. Contact: Ben Andresen Roger Cline (ASIC) (ASIC) Email: andresen@asic.sc.ti.com rcline@asic.sc.ti.com Phone: (972) 480-4028 (972) 480-4053 Fax: (972) 480-4400 (972) 480-4400 Address: 8505 Forest Lane 8505 Forest Lane Dallas, TX. 75243 Dallas, TX. 75243 M/S 8664 M/S 8664 Support: TI is working on a tool to automatically generate IBIS models from TI SPICE simulations (TI's proprietary SPICE dialect). TI is also evaluating various procedures for IBIS model distribution and tracking. Tag-line: * Thomson-CSF/SCTF Contact: Jean Lebrun Email: lebrun@sctf.thomson.fr Phone: 1/69 33 00 99, Fax: 1/69 33 00 10 Address: L'oree De Corberville BP 56 91401 Orsay France Support: Tag-line: * UniCAD Inc. Contact: Stephen Lum Email: lum@unicad.com Phone: (613) 596-9091 Ext. 321 Address: 2745 Iris Street Pinecrest Office Park Ottawa, Ontario K2C 3V5 Support: UniSolve, a concurrent engineering workbench currently supports IBIS v1.1 model files in native mode for signal integrity analysis. Support for IBIS v2.1 is planned for early 1995. Tag-line: UniCAD, INC. provides software used in the layout and analysis of printed circuits and multichip modules. It provides the only available concurrent Computer Aided Analysis (CAA) environment used to simultaneously monitor Emissions, Digital Signal Integrity, Analog Signal Integrity, Thermal, and Reliability throughout the design layout process. * VeriBest Inc. Contact: Mark Andres Email: mandres@veribest.com Phone: (303) 581-2409 Address: 6101 Lookout Rd. Boulder, CO 80301 Support: VeriBest Inc. fully supports the activities of the IBIS open forum and as such, is ensuring that all signal integrity development is aligned so that our customers will be able to take advantage of IBIS as the standard stabilizes. Tag-line: VeriBest Inc. provides electronic design automation tools for designers of electronic system that include PCBs, ASICs, FPGAs, and PLDs. VeriBest bridges the cost/capability gap by providing proven design flows that interoperate between Windows NT/95 and UNIX operating systems. * VLSI Technology Contact: Richard Ulmer Email: dick.ulmer@tempe.vlsi.com Phone: (602) 752-6252 Fax: (602) 752-6002 Address: 8375 South River Parkway Tempe, AZ 85284 Support: Tag-line: Zeelan Technology (A Mentor Graphics Company) Contact: George Opsahl Email: george@zeelan.com Phone: (503) 685-1000, Fax: (503) 685-1001 Address: 8005 SW Boeckman Road Wilsonville, OR 97070 Support: Standard Model Libraries (including Microprocessor, Memory, pre-silicon ASIC, FPGA, Digital Logic models) as well as Modeling service to characterize and create models conforming to the IBIS format. MasterModels(TM) are created from measurements of physical devices under a tightly controlled high frequency fixture and modeling system. These accurate models closely represent actual device behavior when used in simulation. Tag-line: * Zuken-Redac Contact: John Berrie EMail: johnb@redac.co.uk Phone: +44 1684 294161, Fax +44 1684 299754 Address: Tewkesbury, Gloucestershire GL20 8HE England Support: Zuken-Redac currently supports IBIS modelling through its interfaces to Quad Design and Quantic Labs. Further integration with IBIS is planned in future. Tag-Line: Zuken-Redac is a world leader in design automation, providing open, leading technology, standards-based CAD-CAM solutions. ============================================================================ From owner-ibis Mon Feb 17 08:30:08 1997 Received: from alcatel.fr (ns.alcatel.fr [194.133.58.131]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id IAA26902 for ; Mon, 17 Feb 1997 08:30:05 -0800 (PST) Received: from alcatel.fr (gatekeeper-ssn.alcatel.fr [155.132.180.244]) by mailgate.alcatel.fr (8.8.5/8.8.5) with ESMTP id SAA23100 for ; Mon, 17 Feb 1997 18:33:59 +0100 Received: from ln.cit.alcatel.fr (las40304.ln.cit.alcatel.fr [155.132.225.2]) by nsfhh5.alcatel.fr (8.7.3/8.7.3) with SMTP id RAA28736 for ; Mon, 17 Feb 1997 17:28:27 +0100 (MET) Received: from las41247.ln.cit.alcatel.fr by ln.cit.alcatel.fr (4.1/SMI-4.1) id AA16927; Mon, 17 Feb 97 17:30:47 +0100 Received: from las41247 (localhost) by las41247.ln.cit.alcatel.fr (4.1/SMI-4.1) id AA00450; Mon, 17 Feb 97 17:30:20 +0100 Sender: fitzpat1@ln.cit.alcatel.fr Message-Id: <3308879B.2781E494@ln.cit.alcatel.fr> Date: Mon, 17 Feb 1997 17:30:19 +0100 From: John V Fitzpatrick Organization: Alcatel Telecom, Lannion, France X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.3_U1 sun4c) Mime-Version: 1.0 To: ibis@vhdl.org Subject: BIRD 41.1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello all, Thanks to all who commented on Bird 41 during the Open Forum meeting on Friday. Based on what I heard, I've made some changes to the BIRD, which I submit as BIRD 41.1. I'll be on holidays for 3 weeks from Thursday 20th, so I'd really appreciate your comments as soon as possible.... What I'd like to know is: a) Is the definition of series pins OK? Will it be compatible with the connector pin definitions? b) Is the explanation of state understandable? Should [State] be a separate keyword? c) Will [Series Impedance] allow bus-switches to be correctly modelled? d) What are your opinions on the RLC series path as defined? Would it be better to allow an arbitrary series path be defined, as per the old 36.1? If, like me, you print out BIRD's, then scribble corrections on them, you can fax me your handwritten notes at +33 2 9604 8509 (where + stands for 011 in the USA) Regards, John p.s. And for those who heard my plea for a simpler way to define V/I curves, what about the suggestion for an [Impedance] keyword with a Mode subparameter (see Analysis Path)? ************************************************************************ ************************************************************************ BIRD ID#: 41.1 ISSUE TITLE: Modelling Series Switchable Devices REQUESTER: John Fitzpatrick, Alcatel DATE SUBMITTED: February 17, 1997 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ************************************************************************ ************************************************************************ STATEMENT OF THE ISSUE: IBIS cannot model series devices. IBIS cannot model switches. ************************************************************************ STATEMENT OF THE RESOLVED SPECIFICATIONS: One new keyword is defined under [Component]: [Series_Pin] A new keyword is defined under [Component]: [Series_Impedance] RLC series paths can be defined with: [Rseries], [C_series], [R_c_series], [L_c_series], [L_series], [R_l_series] Two additional Model_type values are allowed under the [Model] keyword: Series, Series_Switch New measurement methods are defined for impedance tables. Add the following text somewhere after the [Component] keyword: |====================================================================== | Keyword: [Series_Pin] | Required: Optional |Description: Used to associate two pins joined by a series device. | Sub-Params: Pin1, Pin2, Model_Name, State |Usage Rules: Entries follow these rules: Only series pin pairs | are entered. The Pin1 column contains the pin number for | which input impedances are measured. The Pin2 column | contains the pin name of the other end of the series | device. The Model_Name colum contains the name of the | model corresponding to the series device. | The State column contains text allowing the simulator | tool to make intelligent path configurations in the | case of, say, crossbar switches. | | Column length limits are: | Pin1 5 characters max | Pin2 5 characters max | Model_Name 20 characters max | State 20 characters max | |Other Notes: | The order of the pins is important. All V/I curves | correspond to measurements made at Pin1. | If the device is not symmetric, a different model may be | specified with the pin order swapped. | | The State column shall contain text | which can be used by the simulator to prompt the user | for configuration information: | - for a Series_Switch, the device os ON when the | corresponding state is selected, otherwise it | is OFF; | - for other devices, the device is present only | when the corresponding state is selected, or if the | state is "NA". | | In the case of a crossbar switch, all possible series | connections must be listed: switching information is | contained under the State column. | | The model name given here supersedes that given | under the the [Pin] keyword | [Series_Pin] |Pin1 Pin2 Buffer State 3 4 switchA AB |switchA is buffer from 3 to |4 4 3 switchAneg AB |Buffer from 3 to 4 is |non-symmetric 12 13 switchA AB |12 connected to 13 in state AB 12 14 switchB AC |12 connected to 14 in state AB Change existing text from: | Model_type must be one of the following: | Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, | Open_sink, I/O_open_sink, Open_source, I/O_open_source, | Input_ECL, Output_ECL, I/O_ECL, and Terminator. | to: | Model_type must be one of the following: | Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, | Open_sink, I/O_open_sink, Open_source, I/O_open_source, | Input_ECL, Output_ECL, I/O_ECL, Terminator, Series, | Series_switch and Series_path. | Add text to the special usage rules: | | Series This models a non-linear series | device e.g. a diode | [Series_Impedance]: no modes | No mode subparameter. | | Series_switch This models a series device that can | can be either ON or OFF. | Mode subparameters defined under | [Series_Impedance]: modes ON, OFF Add the following text after the [Model] keyword: |====================================================================== | Keyword: [Series_Impedance] | Required: Yes, for series devices |Description: The data points under this keyword define the V/I curves | measured at Pin1 for a given load at Pin2 and for a | given mode of operation of the device. | Pin1 and Pin2 are defined under the [Series_Pins] | keyword. | Sub-Params: R_load, Mode |Usage Rules: The first column contains the voltage value, and the | three remaining columns hold the typical, minimum, and | maximum current values. The four entries, Voltage, | I(typ), I(min), and I(max) must be placed on | a single line and must be separated by at least one white | space or tab character. | | All four columns are required under these keywords. | However, data is only required in the typical column. | If minimum and/or maximum current values | are not available, the reserved word "NA" must be used. | "NA" can be used for currents in the typical column, | but numeric values MUST be specified for the | first and last voltage points on any V/I curve. | Each V/I curve must have at least 2, but not more | than 100, voltage points. | | The R_load sub-parameter specifies the resistive load | between Pin2 and ground. If not specified, it is | assumed that Pin2 is directly connected to ground. | | The Mode subparameter is required if the | characteristics of the series device can be | configure by internal or external control logic. | Accepted values for Mode are: | ON : the series device is switched on | OFF : the series device is switched off | | Other Notes: All measurements are relative to ground. | | There is no monotonicity requirement. However | the model supplier should realise that it may | not be possible to derive a behavioural model | from non-monotonic data. | | More than one [Series_Impedance] may be included, | with different values of R_load. | Recommended values: 0, 50 and 1kohm. | Add the following text somewhere after the [Rgnd] keyword: |====================================================================== | Keywords: [Rseries], | [C_series], [R_c_series],[L_c_series], | [L_series], [R_l_series] | Required: Yes, if they exist in the device |Description: The data for these keywords allow the definition | of series R, L or C paths. | Usage Rules: For each of these keywords, the three columns hold the | typical, minimum, and maximum resistance values. The | three entries must be placed on a single line | and must be separated by at least one white space or tab | character. All three columns are required under these | keywords. However, data is only required in the typical | column. If minimum and/or maximum values are not | available, the reserved word "NA" must be used. | Other Notes: This series RLC model defined to allow IBIS to model | simple passive devices and/or parasitics. | The model is: | | | R_series | +---/\/\/\/\--------------------+ | | | | Pin1 | L_series R_l_series | Pin2 | <---+---@@@@@@@@-/\/\/\/\-----------+---> | | | | | | | | | +---| |--@@@@@@@@@---/\/\/\/\---+ | | | L_c_series R_c_series | C_series | | [R_l_series] shall be defined only | if [L_series] exists. | [R_c_series] and [L_c_series] shall be defined | only if [C_series] exists. | *********************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Bus-switches (ex: 74LVX3L383 from NS or 74CBT3383 from TI) are increasingly being used on high-speed boards. They cannot be modelled by IBIS 2.1. This BIRD allows the definition of a series device which is connected between any two pins. If this device is a non-linear resistor (e.g. a diode), then it can be described by an I/V table. One approach suggested was to force one of the pins to Vcc or ground, and then reuse the [Pullup] and [Pulldown] tables. This approach will not correctly model bus-switches. So instead, a new keword [Series_Impedance] is defined. This has a R_load keyword. For bus-switches, R_load should be set to a value >> 5ohms in order to allow the Ron vs. bias voltage (as given in application notes) curves be obtained. The author would like to suggest an extra keyword [Impedance] to "replace", or provide an alternative, to the pullup, pulldown, etc. This keyword would have a mode subparameter, with values Pullup, Pulldown and Hi-state. This would allow 3 sets of measurements be included in the IBIS file, without any fiddly subtaracting of curves, or confusing Vcc relativity. As suggested by Chris Reid, a state entry is added to allow crossbar switches be modelled. It is expected that the simulator detect these states, then ask the user to choose one of them. Is this information really in the right place?? Often a bus-switch is used to provide 3.3V to 5V translation. If this is to be modelled in IBIS, then a second model must be generated for Vcc=4.3V. Use the [Model selector] keyword to allow the correct buffer be chosen. Additional series RLC paths are defined in this BIRD. An alternative solution would be to allow an arbitrary path be defined, similar to Bird 36.1 prior to the amputation of connector support. *********************************************************************** ANY OTHER BACKGROUND INFORMATION: 41 Submitted Feb 12, 1997 41.1 Submitted Feb 17, 1997 - Better explanation of State column - Define new [Series Impedance] keyword - Define series RLC path (to model passive device + parasitics) From owner-ibis Mon Feb 17 13:27:25 1997 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id NAA27631 for ; Mon, 17 Feb 1997 13:27:25 -0800 (PST) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id NAA13186 for ; Mon, 17 Feb 1997 13:25:41 -0800 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (V3.1.1) id xma011473; Mon, 17 Feb 97 13:23:19 -0800 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA00367 for ibis@vhdl.org; Mon, 17 Feb 97 13:23:22 -0800 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA20977; Mon, 17 Feb 97 13:25:47 PST Date: Mon, 17 Feb 97 13:25:47 PST From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9702172125.AA20977@rockie.nsc.com> To: ibis@vhdl.org Subject: more on roster update IBISfans: I am getting a lot of information from you all about updating the respective company roster entries. I would like you to provide information on ALL the fields if possible. E-mail address and Web address are very important as this roster will eventually be turned into a HTML file with all the hypertext links in place. Pls also mention your involvement with IBIS using the following Category: End-user, EDA, Model supplier That is if all are applicable for your company. Pick the ones that apply. Let me know if there is any questions, Best Regards, Syed. National Semiconductor Corp. From owner-ibis Tue Feb 18 05:43:41 1997 Received: from mailgate.Cadence.COM (mailgate.Cadence.COM [158.140.2.1]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id FAA00621 for ; Tue, 18 Feb 1997 05:43:41 -0800 (PST) Received: (from smap@localhost) by mailgate.Cadence.COM (8.6.8/8.6.8) id FAA09048 for ; Tue, 18 Feb 1997 05:42:11 -0800 Received: from nakul.cadence.com(158.140.126.64) by mailgate.cadence.com via smap (V1.0mjr) id sma856273329.009044; Tue Feb 18 05:42:09 1997 Received: (from presi@localhost) by nakul.cadence.com (8.6.8/8.6.8) id TAA22650 for ibis@vhdl.org; Tue, 18 Feb 1997 19:10:08 +0531 Date: Tue, 18 Feb 1997 19:10:08 +0531 From: R Sanjeev Message-Id: <199702181339.TAA22650@nakul.cadence.com> To: ibis@vhdl.org Subject: IBIS model from Datasheets. X-Sun-Charset: US-ASCII Hi everyone, Has anyone tried to make IBIS models from Datasheets? How good can we expect such a model to be? Any reply is appreciated, Thanx regards presi From owner-ibis Tue Feb 18 07:59:32 1997 Received: from relayhost.vlsi.com (tweety.vlsi.com [134.27.20.23]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id HAA00837 for ; Tue, 18 Feb 1997 07:59:31 -0800 (PST) Received: from relayhost.tempe.vlsi.com (anubis.tempe.vlsi.com [134.27.128.1]) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) with ESMTP id IAA08210; Tue, 18 Feb 1997 08:50:29 -0800 Received: from tempepop.tempe.vlsi.com (devious.tempe.vlsi.com [134.27.128.5]) by relayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/101195) with ESMTP id IAA13769; Tue, 18 Feb 1997 08:57:29 -0700 Received: from witsend (witsend.tempe.vlsi.com [134.27.133.12]) by tempepop.tempe.vlsi.com (8.6.9/Hub-Perlotto/010296) with SMTP id JAA21381; Tue, 18 Feb 1997 09:05:24 -0700 Sender: dc.sessions@tempe.vlsi.com Message-ID: <3309D168.122E@tempe.vlsi.com> Date: Tue, 18 Feb 1997 08:57:28 -0700 From: "D.C. Sessions" Organization: VLSI Technology Inc. X-Mailer: Mozilla 3.0 (X11; I; SunOS 5.4 sun4m) MIME-Version: 1.0 To: R Sanjeev CC: ibis@vhdl.org Subject: Re: IBIS model from Datasheets. References: <199702181339.TAA22650@nakul.cadence.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit R Sanjeev wrote: > > Hi everyone, > > Has anyone tried to make IBIS models from Datasheets? > > How good can we expect such a model to be? Not. The problem is that the devices in the IC output structures are very nonlinear, but the data sheets only provide (if you're lucky) two points on the V/I curve for one case and two DIFFERENT points for another case. This is just not enough, and that'e the reason for IBIS in the first case. -- D. C. Sessions dc.sessions@tempe.vlsi.com From owner-ibis Tue Feb 18 11:14:05 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id LAA01156 for ; Tue, 18 Feb 1997 11:13:58 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Tue, 18 Feb 97 11:12 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 18 Feb 97 11:12 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 18 Feb 97 11:13 PST Message-Id: Date: Tue, 18 Feb 97 11:13 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS MINTUTES 2/14/97 DATE: February 18, 1997 SUBJECT: 2/14/97 EIA IBIS Open Forum Minutes VOTING MEMBERS AND 1997 PARTICIPANTS LIST: AMP Jeff Walden Applied Simulation Technology Dileep Divekar*, Norio Matsui Cadence Design C. Kumar, Don Telian Cypress Bruce Wenniger Hewlett Packard, EEsof Karl Kachigan, Henry Wu HyperLynx Kellee Crisafulli INCASES (Olaf Rethmeier) Intel Corporation Stephen Peters*, Arpad Muranyi*, Interconnectix Bob Ross* Mitsubushi Tam Cao Motorola Ahmed Omer* National Semiconductor Syed Huq*, Cheng-Yang Kao, Mike Brisbol, Peter Laflamme, Kevin Smith, NCR Dave Moxley*, Richard Mellitz NEC (Hiroshi Matsumoto) Quad Design/Viewlogic Jon Powell, Chris Rokusek* Quantic Laboratories (Mike Ventham) Texas Instruments Thomas Fisher Thomson-CSF/SCTF (Jean LeBrun) UniCAD Canada Ltd. (Celso Faia) Veribest Ian Dodd* VLSI Technology Harish Patel, D.C. Sessions, Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1997: 3M Fran Hart Actel Scott Schlachter Acuson & Free Model Foundation Richard Munden Alcatel John Fitzpatrick* Ansoft Eric Bogatin Apteq Design Systems Dan FitzPatrick Compaq Weston Beal Digital Equipment Corp. Jeff Chu* EIA Patti Rusher* EMC Fabrizio Zanella Micron Technology Brian Johnson Molex Gus Panella North Carolina State U. (Michael Steer) S3, Inc. Porsh Shih, Sarathy Sribhashyam Ultratest International Charles Im* Zeelan Technology George Opsahl* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Note, refer to the January 10, 1997 minutes for the last listing of the 1996 IBIS Open Forum participants. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode 3/7/97 (916) 356-9200 3-87786 1568848 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each open forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM George Opsahl, a long time participant from Zeelan Technology, joined the discussion. MEMBERSHIP UPDATE AND TREASURER'S REPORT Patti Rusher reports that Meta-Software (now Avant!) has canceled their membership. IBM will not be joining. So the membership is currently 22, but most bills are still outstanding. There will be some changes due to changing interests and some business purchases and mergers. The DAC97 participation will be deducted from the 1996 funds. Patti will supply Bob Ross current treasury status, but predicts about $10,500 income this year from membership dues. Dave Moxely asked clarification that the membership rate is $500.00 this year even if the company had purchased the IBIS_CHK2 source code license in the past. The parser/membership discount of $750.00 still applies for joint membership/parser licenses for the year of the purchase. Patti needs to supply Bob the current financial information since the last showed $9,285 in the IBIS account. REVIEW OF MINUTES AND AR'S Minutes corrections submitted privately include the following: Minor text corrections. Harish Patel spelling correction from Hrish for VLSI. Sri Jandhyala removal from Texas Instruments contacts, roster, participants list due to responsibility change. Mike Bristol from Bristi for National Semiconductor. Sarathy Sribhashyam from Jarathy Jribhashyam for S3, Inc. MISCELLANY/ANNOUNCEMENTS None. PRESS AND WEB PAGE UPDATES Syed Huq reports miscellaneous logo and company Web page link updates on the EIA/IBIS Home page Poster selection (Quantic/EMC and Applied Simulation Technology). Syed also reports that "Apsim Models IC Packages" on pg. 56 of the February 10, 1997 issue of EE Times describes Applied Simulation Technology's ApsimIBIS products for package coupled-matrix LRC extraction and IBIS to Spice conversions. NEW MODELS AVAILABLE, LIBRARY UPDATE Bob Ross reported that the Free Model Foundation has removed their models, but plans to have some new ones shortly. OPENS FOR NEW ISSUES Bob Ross for the new North Carolina State University s2ibis2 Version 1.1. REVIEW OF SUPERCON97 IBIS SUMMIT MEETING Syed Huq reported that it was a good meeting with a lot of interesting topics, and with over 35 people attending. Syed and Jon Powell will be posting the electronic copies of the presentations. Bob Ross asked that he be given copies since he will post them in a summit97 directory where he is owner. The minutes of the meetings are also stored in that directory. Syed and Jon can still work on any possible visible copies. AR - Syed Huq supply Bob Ross with electronic copies. DESIGN AUTOMATION CONFERENCE 1997 IBIS MEETING PLANNING Patti Rusher asked what day the IBIS Summit meeting will be held so she can reserve a room. Bob Ross suggested Thursday, June 12, 1997 because it is the day after the trade show portion closes. DAC97 will be held in Anaheim, California. Patti indicated that a Poster will be needed. Bob hopes to off-load this project. INTERNATIONAL PROGRESS Patti Rusher reported that IBIS did not pass international standardization at the last IEC TC93 US TAG meeting because only three countries agreed to work on the proposal per fast track. She is still pursuing getting five countries interested and expects to be successful because of some recent organizational changes. EIA JAPAN I/O INTERFACE MODEL PROPOSAL Bob Ross reported that he had just received a FAXed copy of the Electronic Industries Association of Japan (EIAJ) "Standard for I/O Interface Model", Draft Version 0.0. Committee Chair, Hideki Fukuda from Hitachi, does not want this draft circulated to the public at this time. Instead, he has proposed meeting with Bob and/or appropriate representatives of the EIA/IBIS Open Forum to investigate future areas of cooperation. Bob commented that that this is a well-written, Postscript formatted document. It is a copyrighted document, so Bob is seeking permission to provide copies to the EIA/IBIS Open Forum officers for review. Based on a quick reading, Bob provided a brief overview and his initial observations. The document was developed by a committee with representatives from seventeen Japanese companies. It was designed to extend IBIS Version 2.1 and contains the IBIS-style keyword syntax. It has a nice partitioning of a part into IC, Package, and Module Board portions. It also has a functionality level structure: Level 1 for Signal Integrity, Level 2 for Power Integrity (ground and power bounce) and Level 3 for EMI (requiring shape information). For comparison and positioning of the proposal, Bob feels that IBIS Version 2.1 is Component-centric with special application to large-sized Board-Level analysis. The Japanese proposal is more IC-centric with Spice-centric extensions to handle internal details including the electrical representation of internal metalization within an IC. With detailed internal power/ground/buffer electrical interconnection, more accurate power integrity analysis is possible. One example shows two adjacent ground pins modeled by splitting the electrical inductances between the two pins. This type of detail goes beyond what can be provided by the existing [Pin Mapping] keyword. Some standard Spice syntax is included to describe passive elements. A set of table-based behavioral MOS transistor and diode extensions are included, which Bob believes would be extensions to most, if not all Spices (this needs to be checked further). This behavioral approach gives additional accuracy, while at the same time, does not require revealing actual proprietary process information. Hideki Fukuda has suggested a March visit, and Bob is suggesting that an appropriate time and location may be centered around the PCB Design Conference in Santa Clara, California, March 18-20, 1997. Based on this discussion, the sense of the Forum is to proceed with further discussion. The EIA/IBIS Open Forum officers along with several other individuals expressed interest and volunteered to be part of the group for future discussions and advice: Bob Ross, Interconnectix Syed Huq, National Semiconductor Jon Powell, Quad Design/Viewlogic Dileep Divekar, Applied Simulation Technology (USA) Stephen Peters, Intel Bob will work out scheduling with Hideki Fukuda. ELECTRONIC DESIGN REPRINTS Syed Huq has received permission to post the article he published "Ease System Simulation With IBIS Device Models" in the December 2, 1996 issue of Electronic Design on the EIA/IBIS Home page. He is currently converting it to HTML format. Syed also raised the issue of whether the EIA/IBIS Forum should purchase reprints according to the following price schedule: 100 $2010 500 $2215 1000 $2715 They would be used as trade show handout material (particularly for DAC97) along with some remaining copies of the 1995 EDN IBIS article. Patti Rusher indicated that at least 500 copies would be needed. Bob Ross questioned whether National Semiconductor is interested in sharing the expense by purchasing some copies for National distribution. Syed will find out, and the purchase decision will be deferred until next meeting. ROSTER UPDATE Because of the acquisitions, mergers, and changing directions and personnel that is characteristic of our industry, the roster.txt document needs to be updated. Syed Huq volunteered to gather the new information by sending the current roster.txt out on the ibis@vhdl.org reflector. Please review your entries and make any changes or corrections. Also, we would like to know if the EDA vendors support IBIS as a native model input (with translation to another model format), and whether the vendor can read IBIS Version 2.1 level files (versus IBIS Version 1.1). We would like to see which silicon vendors produce IBIS models, and we would like to see which users also create or make use of IBIS models. Anyone who is involved with IBIS in any way is invited to submit roster.txt information to Syed for their organization. Use the existing roster.txt to provide the format for your entry. Official EIA/IBIS Open Forum Member organizations will always be retained on the roster. If no response is received for non-member organizations, the existing entry will be deleted. This is our way of removing obsolete references. AR - Everyone submit to Syed Huq at huq@rockie.nsc.com any roster changes or new roster information. VHDL.ORG CHANGES Bob Ross reported that a PERL script utility submitted by John Fitzpatrick is now being used in the /pub/ibis/birds directory (and also in the /pub/rail/roads directory) to create current index.html files. These index.html files allow, by default, a nicely formatted index table of all of the current IBIS BIRDs (and ROADs for RAIL) using a Browser and direct access to any specific BIRD. Bob thanked John for writing this utility. Bob also reported some other changes. The domain name "vhdl.org" will also accept more relevant aliases such as eda.org, verilog.org, etc. since vhdl.org contains directories for many different standards groups, most of which are not associated with the VHDL activities. As a result of lax security precautions associated with a wide spread need for many different groups to access to vhdl.org, a hacker group break-in occurred into vhdl.org. No known damage was found. However vhdl.org was immediately taken off the network as a defensive measure for several weeks. Tighter security measures were taken. Among these were the removal of guest login and direct line modem access. Anonymous FTP and Browser access is still available. These changes are now reflected in the information provided at the end of these Minutes. Finally, Bob has moved some of the information into subdirectories to clean up the file structure under /pub/ibis. One example is to move all of the yearly e-mail directories under one directory "email". Bob also wishes to put the documents now contained under "documents" in a directory named "docs". Currently both directories will exist containing identical information until some links to various documents from the EIA/IBIS home page are changed. IBIS COOKBOOK PROGRESS Chris Rokusek, who is heading this project, asked whether Stephen Peters has done a draft, as previously planned. Stephen reported that he recently has gotten a technical writer who will start working on the Cookbook shortly. MODEL TEST LOAD RECOMMENDATIONS Bob Ross reported that a long standing AR is for vendors to provide Chris Rokusek the information the preferred setups for [Rising Waveform] and [Falling Waveform] data that makes the simulator algorithms most effective. So far Bob and Chris have provide preferred data loads. This information will be put in the Cookbook to help guide all model developers. IBIS-TO-BEHAVIORAL MODEL SUPPORT Syed Huq raised the issue of whether there is a need for the EIA/IBIS Open Forum to pursue IBIS to Spice Behavioral translation. This has been a recent IBIS reflector topic. Syed cited several vendors who have or have had such products and again noted Applied Simulation Technologies recent entry. While some of the products are only at IBIS Version 1.1 level or have been discontinued, there still exists both some coverage and also some opportunity for providing more utilities. SPICE-TO-IBIS TRANSLATOR FOR WINDOWS NT Ian Dodd volunteered to make available the VeriBest adaptation of s2ibis compiled to work under Windows NT from the VeriBest home page. The EIA/IBIS Home page will have a direct link, as it does for the HyperLynx Visual IBIS Editor. Bob Ross endorsed the notion that free utilities available from a number of commercial sites reinforces the reality that there is widespread acceptance of IBIS. This is healthy for the IBIS community as a whole. SPICE-TO-IBIS FROM NORTH CAROLINA STATE UNIVERSITY As reported on the reflector, new version of s2ibis2_v1.1 now exists on vhdl.org under /pub/ibis/s2ibis/s2ibis2_v1.1/s2ibis2.tar.Z for FTP downloading. Alan Glaser made some polarity corrections for Spectre applications. He was not able to provide an AIX executable, as in the past, because he no longer has access to an AIX machine. BIRD40 OVERSHOOT NOMENCLATURE Bob Ross introduced BIRD40 as just a nomenclature change of Overshoot_high to S_overshoot_high and Overshoot_low to S_overshoot_low for static overshoots in the already approved BIRD39. BIRD40 was approved by unanimous vote. VERSION 3.0 FUNCTIONALITY Per discussion at the January 20, 1997 Summit, the issue of Version 3.0 functionality was introduced. Bob Ross summarized the progress since June, 1994 where Version 2.0 of IBIS was introduced through December, 1995 when Version 2.1 was stabilized through several letter ballot votes to become ANSI/EIA-656. During this period, there have been minimal technical changes. Version 2.1 continues to be the most current version. The Open Forum has already introduced (and also rejected) a number of proposals using the BIRD process. These BIRDs have been approved for Version 3.0 along with their associated categories: BIRD28.3 and BIRD37.3: Package Model Enhancements BIRD30.2: Programmable Buffers BIRD34.2: Stored Charge Effects BIRD35.3: Multi-staged Outputs (with possible revisiting) BIRD39 and BIRD40: Specification Enhancements The following BIRDs are still pending: BIRD36.1: Electrical Board Description BIRD41: Modeling Series Switchable Devices (just issued) These BIRDs have been pending, but inactive, and relate to package and connector models. Most likely, a new BIRD will be issued for this area. BIRD31.3: Mated Models BIRD32: Additional Package Model Enhancement All of these features are needed and constitute a rich set for defining the Version 3.0 functionality that will exist beyond Version 2.1 ANSI/EIA-656 functionality. The only addition beyond this might be some form of switchable terminators. that is also to be discussed later. BIRD41 - MODELING SERIES SWITCHABLE DEVICES John Fitzpatrick introduced BIRD41 to the Committee. Bob Ross had formalized the proposal as BIRD41 because there had already been sufficient reflector and face-to-face discussion on this functionality, and John had issued a well-formatted document, even while requesting more feedback. The BIRD process itself can now be the basis for making modifications and moving forward. Bob noted that the IBIS format really does not provide the necessary keywords to describe the series switch devices (Quick Switch, CBT series, etc.) that are now being used in designs. Series elements themselves are not officially defined, although there may be some vendor- specific ways of providing barely adequate work-arounds. BIRD41 defines a new keyword [Series Pin] and two subparameters: Series and Series_Switch. Under [Series Pin], John proposes reusing the existing keywords ([Pulldown] and [Pullup]) and incorporated State information as suggested by Chris Reid of Interconnectix. Bob thought that relying on existing keywords for the purpose of EDA vendor acceptance was a bad idea since the keyword definition would have differences. This would cause both specification confusion and model developer confusion. Bob prefers new keywords with names that reflect more closely what is intended. The keyword [Power Clamp] and [Gnd Clamp] appear to have retained exactly their original meaning and should continue to be used, as defined. Arpad Muranyi questioned whether the series description should contain multiple VI data to model more closely the Source to Drain characteristics as a function of Gate to Drain voltage that exists in FET based series elements. The alternative position is that just a simple series VI relationship adequately describes the characteristics needed for modeling the switch for analysis. After some technical details were suggested, Bob suggested moving this discussion on the IBIS reflector. In response to a question by Stephen Peters about the scope of BIRD41, John answered that it was designed to model the series switch device and also model series diodes. So BIRD41 provides two useful additions. Stephen also asked for clarification of the State terminology in the example. John responded that this column information (e.g., AB-CD) was for clarity and was not used. Bob suggested that John consider the verbal inputs given here and go ahead and issue BIRD41.1. MODELING EARLY CLAMPS IN IBIS Following up on recent meeting discussions, Bob Ross suggested that if Arpad Muranyi really needs the functionality of switchable input terminators soon, he needs to issue a BIRD. However, this may also be a case where this additional functionality could be a Version 3.1 addition since Arpad is currently very busy. PACKAGE COMMITTEE REPORT AND BIRD36.1 - ELECTRICAL DESCRIPTION OF BOARDS Stephen Peters summarized the February 7, 1997 Package Committee meeting position that it will focus on two separate proposals: An Electrical Board description suitable for SIMMs, but without coupling information (just issued as BIRD36.1) Connector Description which includes coupled and non-coupled lines and describes pin pairs. In BIRD36.1, Bob Ross has some minor some minor editorial comments which can be handled off-line. He also questioned whether the "R10K" in the example was really a name of a model, or whether it was an attempt to define a syntax for a resistor element directly. Stephen answered that it was a model name for a shunt resistor. When questioned about including series resistor elements, Stephen responded that it can be modeled using a zero length transmission line segment with R. Regarding connector model directions, the Package Committee appears to have achieved a consensus on using a Matrix description where the Matrix elements are defined as "partial" inductances and capacitances. Jon Powell has solicited sample matrix information from the connector manufacturers so that he can run simulations using that information and comparing the results with corresponding Spice representations using Spice simulations. He is also working on some syntax proposals to reduce the amount of data needed for the descriptions. Stephen is scheduling the next meeting for Friday, February 21, 1997. PARSER STATUS Chris Rokusek has developed an IBISCHK2 extension that generates some warning messages for a suspicious component values and waveform endpoint mismatch conditions that have been previously discussed. These situations are documented as BUG5, BUG6 and BUG7. Chris needs to know how best to provide the executables he has developed. Bob Ross suggested discussing this with Chris off-line. AR - Chris Rokusek and Bob Ross discuss how to make the extended IBISCHK2 executables available. BUG8 - RESERVED KEYWORDS USED AS PINNUMBERS GENERATE ERRORS In the brief time left, Bob Ross indicated that Author Wong of Integrated Device Technology (IDT), had discovered a bug that is now documented as BUG8. Based on a close reading of the IBIS Specification, there can be several interpretations. Regardless of the interpretation, Bob feels that BUG8 would not justify an ibischk2 (and ibis_chk) revision. Easy work-arounds exits. No decision was reached, so the discussion will be continued at the next meeting. NEXT MEETING: The next meeting is on Friday, March 7, 1996, 8:00 A.M. to 9:55 A.M. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 603-2523, Fax (503) 639-3469 bob@icx.com Modeling Engineer, Interconnectix 10220 SW Nimbus Ave, K4, Portland, OR 97223 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785 huq@rockie.nsc.com Staff Applications Engineer, National Semiconductor, M/S A-2595 2900 Semiconductor Drive, Santa Clara, CA 95052 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Transmission-Line Products Manager, Quad Design/Viewlogic 1385 Del Norte Rd., Camarillo, CA 93010 SECRETARY: Vacant This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@vhdl.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org) or both. State your request. ibis-info@vhdl.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@vhdl.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. ibis-users@vhdl.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. ibischk-bug@vhdl.org To report ibischk2 parser bugs. The Bug Report Form Resides on vhdl.org in /pub/ibis/bugs/bugform.txt along with reported bugs. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on vhdl.org for more information on previous discussions and results. You can get on via ftp anonymous, or send an e-mail request to the automatic archive server, archive@vhdl.org. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ============================================================================== From owner-ibis Tue Feb 18 12:30:27 1997 Received: from mailgate.Cadence.COM (mailgate.Cadence.COM [158.140.2.1]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id MAA01288 for ; Tue, 18 Feb 1997 12:30:26 -0800 (PST) Received: (from smap@localhost) by mailgate.Cadence.COM (8.6.8/8.6.8) id MAA15601 for ; Tue, 18 Feb 1997 12:28:56 -0800 Received: from gda.cadence.com(158.140.106.10) by mailgate.cadence.com via smap (V1.0mjr) id sma856297735.015597; Tue Feb 18 12:28:55 1997 Received: from pc-ericb.Cadence.COM (d158140102229.cadence.com [158.140.102.229]) by gda.Cadence.COM (8.6.8/8.6.8) with SMTP id PAA08012 for ; Tue, 18 Feb 1997 15:25:37 -0500 Message-Id: <2.2.32.19970218232641.00689198@gda> X-Sender: ericb@gda X-Mailer: Windows Eudora Pro Version 2.2 (32) Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Tue, 18 Feb 1997 15:26:41 -0800 To: ibis@vhdl.org From: Eric Blomberg Subject: ibis tutorials Greeting Has anyone come across an end-user IBIS tutorial which helps set expectations on measured results vs simulated. Something which explains by examples and causes (ie fab line changed, bias currents lowered ...) why measured results don't match predictions. Should be suitable for folks who thought of themselves as logic/PCB designers who, after learning a tool they might not have wanted, now have to deal with waveforms. A non-partisan source would be nice. Thanks Eric Blomberg Cadence Design From owner-ibis Tue Feb 18 17:36:40 1997 Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by vhdl.vhdl.org (8.8.5/8.8.3) with ESMTP id RAA01909; Tue, 18 Feb 1997 17:36:40 -0800 (PST) Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.8.4/8.8.4) with ESMTP id RAA12010; Tue, 18 Feb 1997 17:35:03 -0800 (PST) Received: (from ccmgate@localhost) by relay.jf.intel.com (8.7.6/8.7.3) id RAA23306; Tue, 18 Feb 1997 17:35:10 -0800 (PST) Received: by ccm.jf.intel.com (ccmgate 3.2 #6) Tue, 18 Feb 97 17:35:10 PST Date: Tue, 18 Feb 97 16:56:00 PST From: Will Hobbs Message-ID: To: owner-ibis@vhdl.vhdl.org, ibis@vhdl.org Subject: Re: ibis tutorials Text item: Eric, I am not aware of an article like that. There are a couple of articles that discuss various other IBIS, including a "Cookbook," which is a how-to guide for IBIS model developers, and an EDN article on IBIS V1.1 and how it works. These don't address your concern, but may be interesting to read anyway. They can be found on the ibis web page on eia.org. However, if you have direct experience that could contribute to such an article, I would wager you could get it published, and achieve a small degree of fame and fortune while performing a service for the SI community. I'd also wager a number of others on the IBIS reflector list would be interested in collaborating on such an article. Will Hobbs Intel Corp. Greeting Has anyone come across an end-user IBIS tutorial which helps set expectations on measured results vs simulated. Something which explains by examples and causes (ie fab line changed, bias currents lowered ...) why measured results don't match predictions. Should be suitable for folks who thought of themselves as logic/PCB designers who, after learning a tool they might not have wanted, now have to deal with waveforms. A non-partisan source would be nice. Thanks Eric Blomberg Cadence Design Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Subject: ibis tutorials From: Eric Blomberg To: ibis@vhdl.org Date: Tue, 18 Feb 1997 15:26:41 -0800 Content-Type: text/plain; charset="us-ascii" Mime-Version: 1.0 X-Mailer: Windows Eudora Pro Version 2.2 (32) X-Sender: ericb@gda Message-Id: <2.2.32.19970218232641.00689198@gda> Received: from pc-ericb.Cadence.COM (d158140102229.cadence.com [158.140.102.229] ) by gda.Cadence.COM (8.6.8/8.6.8) with SMTP id PAA08012 for ; Tu e, 18 Feb 1997 15:25:37 -0500 Received: from gda.cadence.com(158.140.106.10) by mailgate.cadence.com via smap (V1.0mjr) id sma856297735.015597; Tue Feb 18 12:28:55 1997 Received: (from smap@localhost) by mailgate.Cadence.COM (8.6.8/8.6.8) id MAA1560 1 for ; Tue, 18 Feb 1997 12:28:56 -0800 Received: from mailgate.Cadence.COM (mailgate.Cadence.COM [158.140.2.1]) by vhdl .vhdl.org (8.8.5/8.8.3) with SMTP id MAA01288 for ; Tue, 18 Feb 1 997 12:30:26 -0800 (PST) Received: from vhdl.vhdl.org (vhdl.vhdl.org [198.31.14.3]) by ormail.intel.com (8.8.4/8.8.4) with ESMTP id OAA10099; Tue, 18 Feb 1997 14:29:32 -0800 (PST) Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by relay.jf.i ntel.com (8.7.6/8.7.3) with ESMTP id OAA24580; Tue, 18 Feb 1997 14:29:41 -0800 ( PST) Return-Path: owner-ibis@vhdl.vhdl.org From owner-ibis Wed Feb 19 09:06:20 1997 Received: from bhole.cae.ca (cae.ca [142.39.200.50]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id JAA02634 for ; Wed, 19 Feb 1997 09:06:19 -0800 (PST) Received: from rome.cae.ca by poster.cae.ca (AIX 3.2/UCB 5.64/4.03) id AA10815; Wed, 19 Feb 1997 11:57:34 -0500 Received: from pcq63.cae.ca by rome.cae.ca (SMI-8.6/SMI-SVR4) id LAA04319; Wed, 19 Feb 1997 11:54:35 -0500 Message-Id: <330B306A.38EF@cae.ca> Date: Wed, 19 Feb 1997 11:55:06 -0500 From: "Real Mongrain Jr." Organization: CAE Electronics Ltd, Montreal, Canada X-Mailer: Mozilla 3.0 (Win95; I) Mime-Version: 1.0 To: ibis@vhdl.org Subject: Simulation tools Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi everyone, I want to know if anybody have tried many different signal integrity simulation tools? (IBIS compatible) Anobody compared SigNoise with XTK? Which one is the best? Is there other great tools and what are their big advantage? Any comments will be very helpful. Regards, -- =============================================================== Real Mongrain Jr. MailTo:mongrain@cae.ca CAE Electronics Ltd http://www.cae.ca 8585 Cote de Liesse St-Laurent, Qc, Canada, H4T 1G6 Tel.:(514) 341-6780 ext.3218 fax.:(514) 734-5618 =============================================================== From owner-ibis Wed Feb 19 12:41:19 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id MAA02904; Wed, 19 Feb 1997 12:41:14 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Wed, 19 Feb 97 12:39 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 19 Feb 97 12:39 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 19 Feb 97 12:40 PST Message-Id: Date: Wed, 19 Feb 97 12:40 PST From: bob@icx.com ( Bob Ross) To: ibis-users@vhdl.org, ibis@vhdl.org, mongrain@poster.cae.ca Subject: Re: Simulation tools To everyone: The IBIS reflectors are NOT to be used for discussing/ commenting on/comparing COMMERCIAL products of Silicon Vendors, CAE vendors, Connector Vendors, or Users in any manner whatsoever. The IBIS Open Forum consists of many competing companies working together based on common interests, while at the same time representing the important positions of individual companies (most of which are commercial based). If we start bickering who is best, we will destroy all cooperation. Real's questions are fair, however. If you which to respond, please respond in private directly to Real. Best Regards, Bob Ross IBIS Open Forum Chair Phone (503) 603-2523, Fax (503) 639-3469 bob@icx.com Interconnectix, 10220 S.W. Nimbus Ave., K4, Portland, OR 97223 > Date: Wed, 19 Feb 1997 11:55:06 -0500 > From: "Real Mongrain Jr." > To: ibis@vhdl.org > Subject: Simulation tools > Hi everyone, > I want to know if anybody have tried many different signal integrity > simulation tools? (IBIS compatible) > Anobody compared SigNoise with XTK? Which one is the best? > Is there other great tools and what are their big advantage? > Any comments will be very helpful. > Regards, > -- > =============================================================== > Real Mongrain Jr. MailTo:mongrain@cae.ca > CAE Electronics Ltd http://www.cae.ca > 8585 Cote de Liesse > St-Laurent, Qc, Canada, H4T 1G6 > Tel.:(514) 341-6780 ext.3218 fax.:(514) 734-5618 > =============================================================== From owner-ibis Tue Feb 25 09:31:42 1997 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id JAA17150; Tue, 25 Feb 1997 09:31:41 -0800 (PST) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Tue, 25 Feb 97 09:30 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 25 Feb 97 09:30 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 25 Feb 97 09:31 PST Message-Id: Date: Tue, 25 Feb 97 09:31 PST From: bob@icx.com ( Bob Ross) To: ibis-users@vhdl.org, ibis@vhdl.org Subject: IBIS SUMMIT MEETING To All: The IBIS Summit meeting presentations are now stored on vhdl.org under /pub/ibis/summits/summit97. Compressed versions of the presentations are contained in the z97 and zip97 subdirectories for downloading. Refer to 00readme.txt for more details. Bob Ross Interconnectix From owner-ibis Wed Feb 26 17:02:08 1997 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id RAA24967 for ; Wed, 26 Feb 1997 17:02:07 -0800 (PST) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id QAA09963 for ; Wed, 26 Feb 1997 16:59:13 -0800 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (V3.1.1) id xma008539; Wed, 26 Feb 97 16:57:19 -0800 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA21228 for ibis@vhdl.org; Wed, 26 Feb 97 16:58:29 -0800 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA04670; Wed, 26 Feb 97 17:01:03 PST Date: Wed, 26 Feb 97 17:01:03 PST From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9702270101.AA04670@rockie.nsc.com> To: ibis@vhdl.org Subject: New IBIS models from National - Interface products IBIS fans, National Semiconductor has released the following Interface IBIS model. These are available from our web site at: http://www.national.com/models/ibis/interface.html ds90lv031tm.ibs 3.3V LVDS Quad Differential Driver ds90lv032tm.ibs 3.3V LVDS Quad Differential Receiver National Semiconductor provides IBISv1.1 and IBISv2.1 models from various product lines. National Semiconductor will provide system-on-a-chip solutions for our key data highway strategic partners, exploiting our analog expertise as a starting point for forward integration. Regards, Syed National Semiconductor Corp.