From owner-ibis  Thu Jul  3 10:58:34 1997
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From: Vincent Chang <vchang@memh.ti.com>
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Hi all,

I have a question on the range of the voltage for Power and
Gnd clamps. The question is why do we need such wide range. 

Is it not true that on an actual  PCB, even if the  voltage 
at any  pin tends to go higher  than Vcc  (due to L-C  
effects   etc.), the clamping diodes will allow it to go only
till Vcc+Vf, where Vf is the forward voltage  of  the  clamping
diode?  Basically  that's what the diodes are for.

What is going to happy if we do provide that wide range of
data? Is it going to fail on QC check?

-- 
Best Regards,

			Vincent Chang
			

=======================================================================
*  Vincent Chang                         TI MSG ID: hui8              *
*  Design Automation                     mailto:vchang@memh.ti.com    *
*  Memory Products Design                http://www.memh.ti.com/~mcad *
*  Texas Instruments Inc. MS 657         Phone: (281) 274-3167        *
*  PO Box 1443, Houston, TX 77251        Fax:   (281) 274-2067        *
=======================================================================
 
From owner-ibis  Thu Jul  3 12:17:27 1997
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From: scottmc@icx.com (Scott McMorrow)
To: ibis@vhdl.org
Subject: Re:  The voltage range

Vincent,

A diode has a V/I curve that characterizes the clamping
characteristic of that device.  Discrete diodes tend to 
have extramely strong clamping characteristics, and so 
appear to have one particular Vf.  However, a real diode
actually has a finite resistance.  That resistance constitutes
what the V/I curve of the device will look like after the
diode has reached its Vf clamping voltage.  Most CMOS
clamp diodes are actually ESD structures on the die, and
are designed to have fairly large losses.  As a result,
the V/I curve should be extended in IBIS modeling to account
for the large real resistance of the device, and the imperfect
clamping that will occur as a result.

regards,

--scott

Scott McMorrow
SiQual/Stramond


> Hi all,

> I have a question on the range of the voltage for Power and
> Gnd clamps. The question is why do we need such wide range. 

> Is it not true that on an actual  PCB, even if the  voltage 
> at any  pin tends to go higher  than Vcc  (due to L-C  
> effects   etc.), the clamping diodes will allow it to go only
> till Vcc+Vf, where Vf is the forward voltage  of  the  clamping
> diode?  Basically  that's what the diodes are for.

> What is going to happy if we do provide that wide range of
> data? Is it going to fail on QC check?

> -- 
> Best Regards,

> 			Vincent Chang
>
 
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From: Vincent Chang <vchang@memh.ti.com>
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Hi all,

Sorry, I did not make myself very clearly in the last message.

Let's try again.

The first question is Why should we
do simulation  from  -Vcc  to 2Vcc   if we  have diodes  for
clamping the output to Vcc and Gnd ?  Is it not true that on
an actual  PCB, even if the  voltage at any  pin tends to go
higher  than Vcc  (due to L-C  effects   etc.), the clamping
diodes will allow it to go only till Vcc+Vf, where Vf is the
forward voltage  of  the  clamping diode?  Basically  that's
what the diodes are for.

The second question is,
Can I use the voltage range from -Vcc to 1/2Vcc for Gnd Clamp?
Is QC check going to fail on that voltage range?


-- 
Best Regards,

			Vincent Chang
			

=======================================================================
*  Vincent Chang                         TI MSG ID: hui8              *
*  Design Automation                     mailto:vchang@memh.ti.com    *
*  Memory Products Design                http://www.memh.ti.com/~mcad *
*  Texas Instruments Inc. MS 657         Phone: (281) 274-3167        *
*  PO Box 1443, Houston, TX 77251        Fax:   (281) 274-2067        *
=======================================================================
 
From owner-ibis  Thu Jul  3 14:10:04 1997
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To: Vincent Chang <vchang@memh.ti.com>, ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Re: The voltage range
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At 12:56 PM 7/3/97 -0500, Vincent Chang wrote:
>Hi all,
>
>I have a question on the range of the voltage for Power and
>Gnd clamps. The question is why do we need such wide range. 
>
One reason to have the wide range is to insure that the simulators
all extend the operating range in the same manor.  Some simulators extend
the range linearly which will clearly be in correct as the device
characteristics
always bend over some where.  Some simulators clip the data at the last point
to allow a saturation like effect to be modeled which will be incorrect if
the device
actually has extended data.  Some simulators may even attempt
some type of curve fit.  To insure the same response in this abnormal range
with
all simulators IBIS requires the data to be extended thus allowing the model
developer to insure how the abnormal operating conditions are handled.


-------------------------------------------------------------------------
Have a great day...
Kellee Crisafulli at HyperLynx Inc.
kellee@hyperlynx.com	http://www.hyperlynx.com
-------------------------------------------------------------------------
 
From owner-ibis  Thu Jul  3 14:57:09 1997
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To: ibis@vhdl.org
Subject: the range of the voltage.
Date: Thu, 03 Jul 1997 14:56:08 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>



Hello Vincent:

    The reason the IBIS specification requires the explicit ranges 
is due to differences in the way simulators extrapolate data beyond the
last data point given.  Some simulators will simply repeat the last
data point in a table, others will do a linear interpolation based
on the last two data points.  For example, suppose a ground clamp
table was given only as: 

 V     I
+0     0
-0.2  0.000
-0.4  0.002
-0.6  0.020
-0.8  0.040     

Some simulators may assume that at -1.0 volts the current
is 0.040 (repeating the last point), others may do a linear
extrapolation.  To avoid this problem the IBIS spec explicitly
requires that data be given over the worst possible ranges
and input or output may see. (This worst possible range is
based on transmission line reflections.)  Of course, if your
doing actual measurments or SPICE simulations you can always
lessen the range, then enter the full range of data in the model
itself by doing the extrapolation yourself. 

  As to your second question, the IBIS parser does not (to 
my knowledge) check the tables ranges.  I think a very 
legitimate argument can be made that it should.

          Regards,
          Stephen Peters
          Intel Corp.

=============================================================
Om Thu, 03 Jul 1997 15:59:29 -0500 Vincent Chang wrote:

Let's try again.

The first question is Why should we
do simulation  from  -Vcc  to 2Vcc   if we  have diodes  for
clamping the output to Vcc and Gnd ?  Is it not true that on
an actual  PCB, even if the  voltage at any  pin tends to go
higher  than Vcc  (due to L-C  effects   etc.), the clamping
diodes will allow it to go only till Vcc+Vf, where Vf is the
forward voltage  of  the  clamping diode?  Basically  that's
what the diodes are for.

The second question is,
Can I use the voltage range from -Vcc to 1/2Vcc for Gnd Clamp?
Is QC check going to fail on that voltage range?


-- 
Best Regards,

			Vincent Chang
			

=======================================================================
*  Vincent Chang                         TI MSG ID: hui8              *
*  Design Automation                     mailto:vchang@memh.ti.com    *
*  Memory Products Design                http://www.memh.ti.com/~mcad *
*  Texas Instruments Inc. MS 657         Phone: (281) 274-3167        *
*  PO Box 1443, Houston, TX 77251        Fax:   (281) 274-2067        *
=======================================================================
 
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subscribe
 
From owner-ibis  Thu Jul  3 17:04:39 1997
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From owner-ibis  Fri Jul  4 00:03:44 1997
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To: ibis@vhdl.org, Vincent Chang <vchang@memh.ti.com>
From: Hans M Hilbig <h-hilbig@ti.com>
Subject: re: the range of the voltage.
Date: Fri, 4 Jul 1997 09:03:49 -0700
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Vincent,
in addition to the replies made from other IBIS folks, please be
aware of the fact that recent generation 3.3V bus logic don't have
VCC clamp diodes on their I/O's to allow 3V/5V mixed logic on
one system. Also those devices that 3-state their outputs when
VCC=GND (to allow power down of parts of a system connected to a 
common bus) don't have these diodes. So it's worth to have a look
at up to +2VCC on those devices.

Hans M Hilbig
*************************************************
EMSLP Characterization Texas Instruments Freising
Phone:  +49-8161-804126  FAX:+49-8161-804909
e-mail: h-hilbig@ti.com

------------------
Original text

From: Vincent Chang <vchang@memh.ti.com>, on 7/3/97 3:59 PM:
Hi all,

Sorry, I did not make myself very clearly in the last message.

Let's try again.

The first question is Why should we
do simulation  from  -Vcc  to 2Vcc   if we  have diodes  for
clamping the output to Vcc and Gnd ?  Is it not true that on
an actual  PCB, even if the  voltage at any  pin tends to go
higher  than Vcc  (due to L-C  effects   etc.), the clamping
diodes will allow it to go only till Vcc+Vf, where Vf is the
forward voltage  of  the  clamping diode?  Basically  that's
what the diodes are for.

The second question is,
Can I use the voltage range from -Vcc to 1/2Vcc for Gnd Clamp?
Is QC check going to fail on that voltage range?


-- 
Best Regards,

			Vincent Chang
			

=======================================================================
*  Vincent Chang                         TI MSG ID: hui8              *
*  Design Automation                     mailto:vchang@memh.ti.com    *
*  Memory Products Design                http://www.memh.ti.com/~mcad *
*  Texas Instruments Inc. MS 657         Phone: (281) 274-3167        *
*  PO Box 1443, Houston, TX 77251        Fax:   (281) 274-2067        *
=======================================================================

 
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From: bob@icx.com ( Bob Ross)
To: ibis@eda.org
Subject: IBIS MEETING 7/11/97

                       IBIS Open Forum Meeting Agenda 
                                for 7/11/97

                  Bridge Number    Reservation #   Passcode
                  (916) 356-9200   2-160894        4369865

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
 meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
 Reservation Number and Passcode.
 
 8:00 Check-In, Intros, Announcements                         Ross

      - Intros of New IBIS Participants, Meeting Quorum       Ross
      - Membership Update and Treasurers Report               Rusher
      - Review of Previous Meeting's Minutes (and ARs)        Peters
      - Miscellany/Announcements                              All
      - Press & Web Page Updates                              Ross, All
      - New Models Available, Library Update                  Powell, All
      - Opens for New Issues                                  All

 8:25 Administrative and Project Discussions

      DAC97 EIA Booth Report                                  Rusher

      DAC97 IBIS Meeting Report                               Ross

      International Progress                                  Rusher/Ross
      - 93/46/NP (IBIS Version 2.1)
      - 93/60/NP (IBIS Models and EMC Simulation)
      - EIAJ III (I/O Interface Model for ICs)

      Editing Committee                                       Ross/Peters

      Version 3.1 Parser                                      Ross

      Cookbook                                                Peters

      s2ibis2 Issues (& NT)                                   Dodd

      New Administrative Issues                               All

 8:50 Technical Discussion
 
      BIRD42.3 Modeling Current Waveforms                     Kumar

      BIRD44 Interpretation of Min/Max/Weak/Strong Data       Ross

      Switched Terminators                                    Muranyi

      New Technical Issues                                    All

 9:50 Wrap Up and Next Meetings Plans                         Ross

 9:55 Sign Off
 




 
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Date: Mon, 7 Jul 1997 18:06:20 -0700 (PDT)
From: bob@icx.com ( Bob Ross)
To: ibis-users@eda.org, roland_chang@pmc-sierra.bc.ca
Subject: Re:  [model selector] keyword
Cc: ibis@eda.org

Roland:

I do not think we intended that the reserved words be used with
[Model Selector].  As it stands, it looks like they could be
used.  We will need to raise this question as a clarification
issue.

As an alternative, the same effect could be accomplished by
using a Terminator model to accomplish the same effect - 
a low resistance to ground or power for GND or POWER, and
a high resistance for NC.

In your example below, the [Model Selector] does not undo
the differential association that may exist for the differential
driver.  Either the pins 19 and 20 will always be differential
or be single ended based on the [Diff Pin] keyword.  

Best Regards,
Bob Ross
Interconnectix


> From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
> To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>
> Subject: [model selector] keyword
> Date: Mon, 7 Jul 1997 15:25:57 -0700

> Hello all,

> I was wondering, in the use of the model selector keyword, can one list
> POWER, GND, and NC?
> The reason I ask, is that in the case of pins that are usable in various
> modes, it often  involves grounding, or leaving  certain other pins
> open(NC).

> thanx,

> roland
> ******************************************
> Roland Chang ext. 2647

> PMC-Sierra 
> Applications Department
> 105-8555 Baxter Place
> Burnaby, BC
> V5A 4V7
> Tel: (604) 415-6000

> email: chang@pmc-sierra.bc.ca
> ******************************************

> eg:

> [Pin] signal_name    model_name     R_pin       L_pin      C_pin
> .
> .
> .
> 9     CLKI         crystalbuf    
> 10   CLKO       crystalbuf
> .
> .
> .
> 19  IN(+)          PECLbuf
> 20  IN(-)           PECLbuf
> .
> .
> .
> [Model Selector]    crystalbuf
> NC        |default, CLKI, CLKO attached to a crystal
> pc5x03  |if CLKO left open (NC), feed external clock signal into CLKI

> [Model Selector]    PECLbuf
> PECL_diff         |default, IN(+), IN(-) function as PECL differential
> inputs
> PECL_single    | IN(+) as single sided PECL, decouple IN(-) to ground.
> TTL_single       | IN(+) as single sided TTL, IN(-) to ground.
> GND




 
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From owner-ibis  Mon Jul 14 08:39:55 1997
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To: ibis@vhdl.org
Subject: IBIS Open Forum Meeting Minutes, 7/11
Date: Mon, 14 Jul 1997 08:38:48 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>


 DATE: July 11, 1997

 SUBJECT: 7/11/97 EIA IBIS Open Forum Minutes
  
 VOTING MEMBERS AND 1997 PARTICIPANTS LIST:
 AMP                            Jeff Walden
 Applied Simulation Technology  Dileep Divekar*, Norio Matsui, Raj Raghuram
 Cadence Design & UniCAD        C. Kumar, Don Telian, Cameron Seitz
 Cypress                        Bruce Wenniger
 Digital Equipment Corp.        Jeff Chu*
 High Design Technology         (Razvan Ene)
 HyperLynx                      Kellee Crisafulli, Steve Kaufer
 INCASES                        Olaf Rethmeier, Werner Rissiek
 Intel Corporation              Stephen Peters*, Arpad Muranyi*, Henry Maramis,
				Will Hobbs
 Interconnectix                 Bob Ross*
 Mitsubushi                     Tam Cao, Hoang Nguyen
 Motorola                       [Ahmed Omer], Michael Desiderio*, Paul Bolden*,
                                Tom Myers*
 National Semiconductor         Syed Huq, Cheng-Yang Kao, Mike Bristol,
				Peter Laflamme, Kevin Smith
 NCR                            Dave Moxley, Richard Mellitz
 NEC                            (Hiroshi Matsumoto)
 Quad Design/Viewlogic          Jon Powell, Chris Rokusek, Peivand Tehrani
 Quantic EMC                    (Mike Ventham)
 Texas Instruments              Thomas Fisher
 Thomson-CSF/SCTF               (Jean LeBrun)
 VeriBest                       Ian Dodd*, William Bell
 VLSI Technology                Harish Patel, D.C. Sessions
 
 OTHER PARTICIPANTS IN 1997:
 3M                             Fran Hart
 Actel                          Scott Schlachter
 Acuson & Free Model Foundation Richard Munden
 Alcatel                        John Fitzpatrick
 Ansoft                         Eric Bogatin
 Apteq Design Systems           Dan FitzPatrick 
 Compaq                         Weston Beal, Mark Leonard
 EIA                            Patti Rusher
 EMC                            Fabrizio Zanella
 Hewlett Packard, EEsof         Karl Kachigan, Henry Wu
 Hewlett Packard, France        Jean-Christophe Pautrat*
 Hitachi                        Saburo Hojo, Yasushi Ogawa 
 IBM                            Brad Herrman
 Interface Technology           Dan Waterloo 
 Micron Technology              Brian Johnson                      
 Molex                          Gus Panella
 North Carolina State U.        (Michael Steer)
 S3, Inc.                       Porsh Shih, Sarathy Sribhashyam
 Symmetry                       Andy Hughes
 TRW                            Ray Steele
 Ultratest International        Charles Im*
 Zeelan Technology              George Opsahl 

 In the list above, attendees at the meeting are indicated by *.  Principal
 members or other active members who have not attended are in parentheses.
 Participants who no longer are in the organization are in square brackets.

 Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
 follows:
     
   Date               Bridge Number     Reservation #    Passcode
   August 8, 1997     (916) 356-9200    3-125343         4891173

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each open forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.

 -------------------------------- MINUTES -------------------------------------

 INTRODUCTIONS AND MEETING QUORUM
 Michael Desiderio, Program Manager for the Advanced Interconnect Systems 
 Lab at Motorola, indicated that Motorola is investigating how to provide
 IBIS models.  He is filling in for Ahmed Omera who has left.  Group managers
 Paul Bolden and Tom Myers also joined in.

 Jean-Christophe Pautrat from Hewlett Packard, France is working with Intel
 processors on desktop PC projects and is interested in IBIS models.


 MEMBERSHIP UPDATE AND TREASURER'S REPORT
 Bob Ross reported that Patti Rusher submitted the ledger as of 5/31/97 of
 $9,433 after deducting some meeting expenses.

 Two companies have been removed from the Members list because no payment has
 been received.


 REVIEW OF MINUTES AND AR'S
 No Corrections.

 Stephen Peters reported on the AR's.  The major outstanding ones are for
 examples for the Cookbook and BIRDs.  Please see the cookbook discussion
 below


 MISCELLANY/ANNOUNCEMENTS
 Bob Ross announced that he will be on vacation starting Saturday, June 12
 and should be returning Monday, August 4, 1997.  The system administration
 duties will be handled by Stephen Peters and Syed Huq.

 Syed Huq should be returning from vacation on Monday, July 15, 1997.

 Stephen Peters is expecting to take off for two weeks after Friday, July 17
 and will be returning August 4, 1997.


 PRESS AND WEB PAGE UPDATES
 Bob Ross reported that as a result of a press release by Patti Rusher, "IBIS
 3.0 Gets Nod From EIA" appeared in EE Times, June 30, 1997, p. 14.   

 Bob also reported that in EE Times, June 16, 1997, pg., 72, and article
 Pacific Numerix Fields EMI-Simulation Analysis Tool mentions using IBIS
 or Spice models.

 An article "Interconnect Synthesis Methodology" in the July 1997 issue of
 Printed Circuit Design, pp. 17-21 mentions IBIS.


 NEW MODELS AVAILABLE, LIBRARY UPDATE
 Bob Ross notes that these Web sites have added models:

   Cypress Semiconductor has added an All Octal FCT model Library (68
   Components) for a total of about 102 components.


   The IDT download site has about 44 components plus another 11 that can
   be obtained from the local FAE.  

 Bob also notes that an IBIS diode terminator model from California Micro
 Devices exits at:

   http:://www.calmicor.com/prod/spice/spice.htm

 Bob also notes that one can request IBIS models for SRAMS (DRAMS under
 construction) at

   http://sec.samsung.com/Products/sram/model_request.html


 Jeff Chu asked how one submits IBIS models.  Bob Ross responded that they are
 submitted to the Librarian, Jon Powell (address at the end) and are
 checked out using ibis_chk and actual simulation for syntax correctness
 and to give feedback regarding results.  A submission authorization form
 is available on the ibis FTP site under /pub/ibis/models.  Some models on 
 company Web Sites may not have gone through such checking and may have 
 syntax flaws.


 OPENS FOR NEW ISSUES
 Bob Ross - On adding GND, POWER and NC reserved words to [Model Selector]
 choices.


 DESIGN AUTOMATION CONFERENCE (DAC) 1997 EIA BOOTH REPORT
 Bob Ross indicated from the previous report that the Booth reported good
 traffic and reprints of Syed Huq's December 1996 Article in Electronic Design:
 "Ease System Simulation With IBIS Device Models" were distributed.  The IBIS
 poster at the Booth looked very nice and listed the participating companies.

 
 DESIGN AUTOMATION CONFERENCE (DAC) 1997 EIA/IBIS SUMMIT MEETING REPORT
 Bob Ross, reported that 28 people attended the nearly all day session.  There
 were several interesting presentations in the morning.  New EIA/IBIS officers
 were elected, and IBIS Version 3.0 was ratified.


 INTERNATIONAL PROGRESS
 - 93/46/NP (IBIS Version 2.1) - No Report.  Expect about a two year process.
 - 93/60/NP (IBIS Models and EMC Simulation) - No Report.
 - EIAJ III (I/O Interface Model for ICs - Based on the presentations at the
   IBIS Summit, we expect another release in September along with a Package
   Committee release.
 

 EDITING COMMITTEE 
 Stephen Peters reported on editing IBIS Version 3.0 for clarity.  It could 
 use a table of contents and a keyword list showing when keywords were 
 introduced.  Bob Ross added other possible improvements - section or chapter
 headings, consistency of words per some of the improvements suggested by
 Ogawa-san (Vice Chair of the EIAJ subcommittee), a tree diagram, a syntax,
 etc.  In addition, some of the Cookbook points could be added into the
 Specification for clarity.  BIRD44 to be discussed later also raises some
 editorial clarification points regarding min/max and fast/slow/strong/weak
 interpretations.

 A suggested process is for Bob and Stephen and anyone else who is interested
 to make a first cut at such improvements and put them as a pending Version 3.1
 draft in the Work In Progress (wip) directory.

 One issue is whether we continue to use the text format (with crude graphics)
 or go with Word, HTML, Post Script, or some other format which will allow
 better graphics and presentation.  Bob and Stephen favored at this time
 keeping the reference standard in the text format for maximum portability.
 However, we will consider this issue when some we do some of the editorial
 changes.

 A second issue is whether we hire (or use an internal resource) a technical
 writer.  Stephen and Bob feel that we first need to make the initial editorial
 pass and maintain the historical context first before any major restructuring
 is considered.  This issue will also be considered after the initial editorial
 review.

 Bob also indicated that the parser development project also served as an
 editorial review because some unclear items were revealed.  Version 1.1
 followed Version 1.0 and Version 2.1 along with letter ballot review
 followed Version 2.0 with parser development motivated improvements.
 
 AR - Bob Ross generate and post a BNF for IBIS Version 3.0 (and IBIS Version
 3.0 ratification AR).


 VERSION 3.1 PARSER
 Bob Ross reported that Paul Munsey, who developed the ibis_chk and ibischk2
 parsers essentially no-bid on the ibischk3 parser because he is still 
 finishing the RAIL parser and is carring on full-time job/family 
 responsibilities.  He may be available for some of the work, but suggested
 that we consider other sources.

 Bob stated that there are two alternatives:  Some internal company resource
 that can be dedicated to this project, or hire another contractor.

 Stephen Peters suggested that we ask on the reflector if someone is interested
 in bidding on the project or if someone can recommend a contractor who might
 be interested.

 AR - Stephen Peters put a message for parser development interest/bidding on
 the IBIS reflector.


 COOKBOOK
 Stephen Peters reported that he has received some review comments.  However,
 he has not received any of the promised examples.  The AR's (Action
 Required) for these examples are listed below.  Some additions were
 made to the version of the cookbook handed out at DAC regarding
 recommended test loads for waveforms.  Stephen can provide private copies,
 but is not ready to put it on the FTP site yet.

 Stephen also reported that based on an internal review, a primer on behavioral
 modeling is recommended.  He has a writer who will be doing some work in 
 this introduction section.  The IBIS keywords will be illustrated in this
 context.

 AR - The following people have volunteered to supply examples
  Steve Kaufer/Hyperlynx -- Example 1
  Arpad Muranyi - Example 2
  Stephen Peters - Example 3 

 AR - D.C Sessions.  Supply a paragraph or two explaining the best way to
 modify a SPICE transistor model to get realistic power and ground clamp 
 information

 AR - Bob Ross.  Supply the text for the section "Diode Transient Time Data"

 AR - Syed Huq.  Review and expand (if necessary) Section 3.3. on "Obtaining
 I/V and Switching Information via Lab Measurement".

 AR - Bob Ross submit an example of a Series MOSFET component.

 AR - Everyone who received a copy review the document and provide comments
 to Stephen Peters (address at the end).


 S2IBIS2 ISSUES (& NT)
 Ian Dodd reported that VeriBest had withdrawn their s2ibis based on 
 Version 1.1 s2ibis since it had other errors.  VeriBest now has NT/Windows
 95 versions of
 s2ibis_ver1.3 (for Version 1.1 of IBIS) and s2ibis_ver2.1 (for Version 2.1 of
 IBIS) compiled.  In order to make them work with NT and Windows, they needed
 to deal with file loading problems and code order dependency syntax issues
 that compiled differently in Windows environments than in UNIX environments.

 Ian's concern is that the code is untested (there are no regression tests
 for UNIX versions available).  He would like to make the versions available
 AS IS for users to use and test.  VeriBest would make fixes and corrections
 on a time available basis.

 Bob Ross felt this was a good plan and VeriBest should put there files on
 the VeriBest Web site.  There will be four zip files for source and executables
 for each s2ibis version.  They will be in the location that the official 
 EIA/IBIS Web page already points to.

 AR - Ian Dodd put s2ibis_ver1.3 and s2ibis_ver2.1 for Windows on the VeriBest
 Web site.

 
 BIRD42.3 - MODELING CURRENT WAVEFORMS
 Bob Ross stated that BIRD42.2 had been considered for Version 3.0, but it was
 too controversial to be included.  It deals with describing power and ground
 current waveforms to assist in power integrity (ground and power bounce) and
 SSO (simultaneous switched outputs) detail and also may produce improved
 switching algorithm detail.  An AR is still pending regarding discussion
 on this issue between D.C. Sessions and C. Kumar.

 Bob had issued BIRD42.3 to change the keyword syntax.  This could be considered
 as a Version 3.1 technical addition if it is approved.  

 Discussion will be deferred until next meeting.

 AR - D.C. Sessions and Kumar get together and provide an example showing
 where the rising and falling waveform tables do not result in correct
 results.


 BIRD44 - INTERPRETATION OF MIN/MAX/WEAK/STRONG DATA
 Bob Ross reported that Andy Ingraham of Digital Equipment Corporation had
 submitted BIRD44 as an editorial improvement to clarify the actual usage
 of the min and max columns for data.  Bob felt that while it contained good
 material, an alternative might be an explanation section at the beginning
 of the standard.  There already is a large base of models and utilities
 (s2ibis) which use the existing min/max column headings and terms.

 BIRD44 will continue to remain open for further discussion.  We may want to
 consider how to resolve it after we do the first pass on the editorial cleanup
 of IBIS Version 3.0.


 SWITCHING TERMINATORS
 Arpad Muranyi has no further work in this area to report.  This also could be
 considered a Version 3.1 technical extension if a BIRD for this functionality
 is issued and approved.


 MODEL SELECTOR HANDING OF RESERVED WORDS
 Bob Ross introduced briefly that there had been a question regarding whether
 GND, POWER, and NC could be included as [Model Selector] choices.  Arpad
 questioned the need.  Bob stated that the Terminator models could be used
 for similar functions, especially NC.  This will be considered further as
 part of the editorial review to propose clarification of this issue.  (A
 BIRD may need to be issued.)


 FINAL ITEMS
 Because of holidays and people being on vacation, the next teleconferencing
 meeting was scheduled on Friday, August 8, 1997.
 
 
 NEXT MEETING:
 The next meeting is on Friday, August 8, 1997, 8:00 A.M. to 9:55 A.M.  
 ==============================================================================
				       NOTES
 
 IBIS CHAIR: Bob Ross (503) 603-2523, Fax (503) 639-3469
	     bob@icx.com
	     Modeling Engineer, Interconnectix
	     10220 SW Nimbus Ave, K4, Portland, OR 97223

 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785
	     huq@rockie.nsc.com
	     Staff Applications Engineer, National Semiconductor, M/S A-2595
	     2900 Semiconductor Drive, Santa Clara, CA 95052
 
 SECRETARY:  Stephen Peters (503) 264-4108, Fax: (503) 264-4515
	     sjpeters@ichips.intel.com
	     Senior Hardware Engineer, Intel Corporation
             M/S JF1-56
	     2111 NE 25th Ave. 
             Hillsboro, Oregon 97124-5961

 LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
	     jonp@qdt.com
	     Senior Scientist, Quad Design/Viewlogic
	     1385 Del Norte Rd., Camarillo, CA 93010
  
 This meeting was conducted in accordance with the EIA Legal Guides and EIA
 Manual of Organization and Procedure.
 
 The following e-mail addresses are used:

   ibis-request@vhdl.org
       To join, change, or drop from either the IBIS Open Forum Reflector
       (ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org)
       or both.  State your request.

   ibis-info@vhdl.org
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   ibis@vhdl.org
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.  Job posting information is not permitted.

   ibis-users@vhdl.org
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.  Job posting information is not permitted.

   ibischk-bug@vhdl.org
       To report ibischk2 parser bugs.  The Bug Report Form Resides on
       vhdl.org in /pub/ibis/bugs/bugform.txt along with reported bugs.

 Information on IBIS technical contents, IBIS participants, and actual
 IBIS models are available on the IBIS Home page found by selecting the
 Electronic Information Group under:

   http://www.eia.org

 Check the pub/ibis directory on vhdl.org for more information on previous 
 discussions and results.  You can get on via FTP anonymous.
 
 "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for 
 use at trade shows.
 ==============================================================================


 
From owner-ibis  Mon Jul 14 09:21:23 1997
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Received: from ichips.intel.com (ichips.intel.com [134.134.50.200])
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Message-Id: <199707141620.JAA15012@ichips.intel.com>
To: ibis@vhdl.org, ibis-users@vhdl.org
Subject: Persons needed for Golden Parser Development
Date: Mon, 14 Jul 1997 09:20:15 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>



Greetings Fellow IBIS fans and users:


     As you are probably aware, IBIS version 3.0 was approved 
at the IBIS Open Forum face to face meeting on June 7.  With 
the approval of the new IBIS version the Golden Parser 
program ("ibis_chk2") must now be upgraded.  Unfortunately,
the contractors (Paul Munsey and company) who wrote the first 
two versions of the golden parser are not available to work
on a version 3.0 of ibis_chk.  Therefore, the IBIS Open Forum 
is soliciting names of any companies or individuals who may be 
interested in bidding on this project.  If you or your company
are interested, or you know of a contractor who may be, please 
contact Stephen Peters (EIA IBIS Open Forum Secretary) at the 
address below.  An informal request for quote is available for 
the asking.  Thanks for your help.


              Best Regards,
              Stephen Peters
              EIA/IBIS Open Forum Secretary
              Intel Corp.


---------------------------------------------------------------------
Stephen J. Peters  MS JF1-55	Phone: (503) 264-4108
Intel Corporation		Internet: sjpeters@ichips.intel.com
2111 N.E. 25th Ave.     	Fax:   (503) 264-4515
Hillsboro, OR 97124-6497	Microprocessor Division 6
 
From owner-ibis  Wed Jul 16 17:23:08 1997
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From: fred@contec.apsimtech.COM (Fred)
Message-Id: <9707162119.AA01892@contec12.apsimtech.COM>
To: ibis@server.vhdl.org
Subject: IBIS simulators
X-Sun-Charset: US-ASCII

Jay Diepenbrock wrote about what options are available for standalone simulation
with ibis models. Applied Simulation Technology is an SI company that has
Spice with full ibis support. The prelayout tools also come with schematic
capture and field solvers as options. References are available upon request.
The company offers postlayout and EMI solutions as well. We have been supporting
ibis from its inception when ibis stood for Intel buffer information sheet.
We have a translator that takes in the ibis format, standard (call it what you
will its not a model at that point) and builds the proper Spice behavior model
with a mouse click. For more information contact:

Fred Balistreri
408-434-0967 ext. 102
Fax 408-434-1003
email fred@apsimtech.com
 
From owner-ibis  Fri Jul 18 09:28:24 1997
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From owner-ibis  Fri Jul 18 09:35:52 1997
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From: Ramzi Ammar <r-ammar@ti.com>
Subject: unsubscribe

please unsubscribe me from the ibis team

regards,
Ramzi Ammar

 
From owner-ibis  Fri Jul 18 12:40:11 1997
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From owner-ibis  Fri Jul 18 18:26:33 1997
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From owner-ibis  Sun Jul 20 07:10:19 1997
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From: "Eitan Medina" <eitan@galileo.co.il>
Organization: Galileo Technology Ltd.
To: ibis@vhdl.org
Date: Sun, 20 Jul 1997 16:07:04 +0200
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Subject: Pin numbering for BGA packages.
Priority: normal
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Hi,

I have a device packaged in BGA package.
In these packages the pins are not numbered from 1 to 208 (or whatever),
but in Ball# (A1,A2,...C1,C2,C3...).

IBIS ver 2.1 does not say anything on this.

Is it legal to place Ball# instead of pin# ?

Thanks,

Eitan Medina
Email: eitan@galileo.co.il
Galileo Technology Ltd.
15 Geron st. 
P.O.Box 2786
Yehud 56217
ISRAEL
Tel:   +972-3-6320220
Fax:   +972-3-6320221 
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
* check out our new web site:   http://www.GalileoT.com *
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 
From owner-ibis  Sun Jul 20 09:42:54 1997
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From: "Eitan Medina" <eitan@galileo.co.il>
Organization: Galileo Technology Ltd.
To: ibis@vhdl.org
Date: Sun, 20 Jul 1997 18:39:41 +0200
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Subject: Simulating Pulldown and pullup curves.
Priority: normal
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Hi,

I have an I/O pad with clamping-high and clamping-low circuits.
When simulating the whole pad-circuit I get non-monotonic data (My
checker wanrns about this). 
Should I simulate the pullup-curve on just the pullup-circuitry (eliminating
the clamping and other structures that exist in the pad-circuit) in order to 
get monotonic curves ?

Thanks,

	Eitan 

Eitan Medina
Email: eitan@galileo.co.il
Galileo Technology Ltd.
15 Geron st. 
P.O.Box 2786
Yehud 56217
ISRAEL
Tel:   +972-3-6320220
Fax:   +972-3-6320221 
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
* check out our new web site:   http://www.GalileoT.com *
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 
From owner-ibis  Mon Jul 21 05:08:03 1997
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From: dan@kaw.com (Dan Aleksandrowicz)
Message-Id: <199612231303.IAA01552@blazer.kaw.com>
To: eitan@galileo.co.il
Subject: Re: Pin numbering for BGA packages.
Cc: ibis@vhdl.org
X-Sun-Charset: US-ASCII


Hi Eitan.

It is legal to number pins using BGA numbering like A1, A2, A3 ... AB12.

Good luck.

 		Dan Aleksandrowicz
 		Engineering Solutions
 		KAW/USA
 		39 Simon Street
 		Nashua, NH 03060
 		http://www.kaw.com
 
From owner-ibis  Mon Jul 21 06:42:38 1997
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Date: Mon, 21 Jul 97 09:27:21 EDT
From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
To: eitan@galileo.co.il
Cc: ibis@vhdl.org, ingraham@wrksys.ENET.dec.com
Apparently-To: ibis@vhdl.org, eitan@galileo.co.il
Subject: Re: Simulating Pulldown and pullup curves.

Eitan Medina wrote:

> I have an I/O pad with clamping-high and clamping-low circuits.
> When simulating the whole pad-circuit I get non-monotonic data (My
> checker wanrns about this). 
> Should I simulate the pullup-curve on just the pullup-circuitry (eliminating
> the clamping and other structures that exist in the pad-circuit) in order to 
> get monotonic curves ?

IBIS does not require monotonicity.

If your device is non-monotonic (if the total current is
non-monotonic), there is nothing you can do to the data to make it
seem monotonic.  Some simulators will have problems simulating with
your device, others will not.  You cannot help that, except by
redesigning your IC.

When separating the total device data into pullup/pulldown/clamp
curves for IBIS, even though the total current may be monotonic, some
of the resulting curves by themselves may become non-monotonic.  This
is unimportant, because the simulator will sum the currents and the
non-monotonicity should go away.  The IBIS checker complains because
it doesn't try to sum the currents back together.  It is just being
extra cautious.

I would not bother trying to make the separate curves monotonic just
to eliminate the warning message; especially if doing so results in
a less-than-correct representation of your device.  If you simulate
the currents separately, they may not add up to the total current
when you recombine them.

Regards,
Andy
 
From owner-ibis  Mon Jul 21 08:55:56 1997
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Date: Mon, 21 Jul 1997 08:54:15 -0700
From: "D. C. Sessions" <dc.sessions@tempe.vlsi.com>
Organization: VLSI Technology Inc.
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MIME-Version: 1.0
To: Andy Ingraham <ingraham@wrksys.enet.dec.com>
CC: ibis@vhdl.org
Subject: Re: Simulating Pulldown and pullup curves.
References: <9707211323.AA23198@us8rmc.bb.dec.com>
Content-Type: text/plain; charset=us-ascii
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Andy Ingraham wrote:
> 
> Eitan Medina wrote:
> 
> > I have an I/O pad with clamping-high and clamping-low circuits.
> > When simulating the whole pad-circuit I get non-monotonic data (My
> > checker wanrns about this).
> > Should I simulate the pullup-curve on just the pullup-circuitry (eliminating
> > the clamping and other structures that exist in the pad-circuit) in order to
> > get monotonic curves ?
> 
> IBIS does not require monotonicity.
> 
> If your device is non-monotonic (if the total current is
> non-monotonic), there is nothing you can do to the data to make it
> seem monotonic.  Some simulators will have problems simulating with
> your device, others will not.  You cannot help that, except by
> redesigning your IC.
> 
> When separating the total device data into pullup/pulldown/clamp
> curves for IBIS, even though the total current may be monotonic, some
> of the resulting curves by themselves may become non-monotonic.  This
> is unimportant, because the simulator will sum the currents and the
> non-monotonicity should go away.  The IBIS checker complains because
> it doesn't try to sum the currents back together.  It is just being
> extra cautious.
> 
> I would not bother trying to make the separate curves monotonic just
> to eliminate the warning message; especially if doing so results in
> a less-than-correct representation of your device.  If you simulate
> the currents separately, they may not add up to the total current
> when you recombine them.

As a point of reference, some of our drivers have
non-monotonic I/V curves due to circuitry which
ensures that the outputs remain high-impedance when
the power is OFF; the weak devices used for this also
cause some loss of gate drive when the device drives
into a heavy load.

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com
 
From owner-ibis  Mon Jul 21 08:59:47 1997
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Date: Mon, 21 Jul 97 08:54:35 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9707211554.AA23709@rockie.nsc.com>
To: ibis@vhdl.org, eitan@galileo.co.il
Subject: Re: Pin numbering for BGA packages.

Eitan,

The IBIS standard states that the [Pin] field can have 5 characters
Max. So you can either use numbers or letters or combination of both
not to exceed 5 characters.

Regards,
Syed
National Semiconductor Corp.

> From owner-ibis@server.vhdl.org Sun Jul 20 08:37:03 1997
> Comments: Authenticated sender is <eitan@galileo21>
> From: "Eitan Medina" <eitan@galileo.co.il>
> Organization: Galileo Technology Ltd.
> To: ibis@vhdl.org
> Date: Sun, 20 Jul 1997 16:07:04 +0200
> Content-Type> : > text/plain> ; > charset=US-ASCII> 
> Content-Transfer-Encoding: 7BIT
> Subject: Pin numbering for BGA packages.
> X-Mailer: Pegasus Mail for Windows (v2.33)
> 
> Hi,
> 
> I have a device packaged in BGA package.
> In these packages the pins are not numbered from 1 to 208 (or whatever),
> but in Ball# (A1,A2,...C1,C2,C3...).
> 
> IBIS ver 2.1 does not say anything on this.
> 
> Is it legal to place Ball# instead of pin# ?
> 
> Thanks,
> 
> Eitan Medina
> Email: eitan@galileo.co.il
> Galileo Technology Ltd.
> 15 Geron st. 
> P.O.Box 2786
> Yehud 56217
> ISRAEL
> Tel:   +972-3-6320220
> Fax:   +972-3-6320221 
> *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
> * check out our new web site:   http://www.GalileoT.com *
> *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
> 
 
From owner-ibis  Mon Jul 21 09:19:03 1997
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Date: Mon, 21 Jul 1997 12:16:56 -0400 (EDT)
From: Luke Chang <chang@nexen.com>
Message-Id: <199707211616.MAA08188@bach.nexen.com>
To: huq@rockie.nsc.com
Subject: Re: Pin numbering for BGA packages.
Cc: ibis@vhdl.org

Hi Syed,

Can a pin name start with any character, such as _, !, @, #, $, 5, 6, *, and &,
or does it have to start with a letter (a-z, A-Z)?

Luke Chang
Fujitsu Nexion, Inc.
Acton, MA


----- Begin Included Message -----

From owner-ibis@server.vhdl.org Mon Jul 21 12:12:31 1997
Date: Mon, 21 Jul 97 08:54:35 PDT
From: huq@rockie.nsc.com (Syed Huq)
To: ibis@vhdl.org, eitan@galileo.co.il
Subject: Re: Pin numbering for BGA packages.
Content-Length: 1293

Eitan,

The IBIS standard states that the [Pin] field can have 5 characters
Max. So you can either use numbers or letters or combination of both
not to exceed 5 characters.

Regards,
Syed
National Semiconductor Corp.

> From owner-ibis@server.vhdl.org Sun Jul 20 08:37:03 1997
> Comments: Authenticated sender is <eitan@galileo21>
> From: "Eitan Medina" <eitan@galileo.co.il>
> Organization: Galileo Technology Ltd.
> To: ibis@vhdl.org
> Date: Sun, 20 Jul 1997 16:07:04 +0200
> Content-Type> : > text/plain> ; > charset=US-ASCII> 
> Content-Transfer-Encoding: 7BIT
> Subject: Pin numbering for BGA packages.
> X-Mailer: Pegasus Mail for Windows (v2.33)
> 
> Hi,
> 
> I have a device packaged in BGA package.
> In these packages the pins are not numbered from 1 to 208 (or whatever),
> but in Ball# (A1,A2,...C1,C2,C3...).
> 
> IBIS ver 2.1 does not say anything on this.
> 
> Is it legal to place Ball# instead of pin# ?
> 
> Thanks,
> 
> Eitan Medina
> Email: eitan@galileo.co.il
> Galileo Technology Ltd.
> 15 Geron st. 
> P.O.Box 2786
> Yehud 56217
> ISRAEL
> Tel:   +972-3-6320220
> Fax:   +972-3-6320221 
> *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
> * check out our new web site:   http://www.GalileoT.com *
> *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
> 


----- End Included Message -----

 
From owner-ibis  Mon Jul 21 09:26:58 1997
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Date: Mon, 21 Jul 97 09:25:22 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9707211625.AA24398@rockie.nsc.com>
To: huq@rockie.nsc.com, chang@nexen.com
Subject: Re: Pin numbering for BGA packages.
Cc: ibis@vhdl.org

Luke,

Yes:
I have tested the following on the ibischk2 parser and they will pass. Meaning,
you can have characters like you mentioned as the first char in the pin
field. THere is no restriction.

REgards,
Syed
National Semiconductor Corp.

[Pin]   signal_name       model_name      R_pin   L_pin    C_pin      
|
!1       RINA-            DS90LV032TM_RIN    50.0m   2.07n    0.429p
@2       RINA+            DS90LV032TM_RIN    50.0m   1.49n    0.306p
3A       ROUTA            DS90LV032TM_ROUT   50.0m   0.95n    0.146p
*4       EN               DS90LV032TM_EN     50.0m   0.95n    0.152p
_5       ROUTC            DS90LV032TM_ROUT   50.0m   0.95n    0.152p
6A       RINC+            DS90LV032TM_RIN    50.0m   0.95n    0.146p
7       RINC-            DS90LV032TM_RIN    50.0m   1.49n    0.306p
8       GND              GND                50.0m   2.07n    0.429p
9   

> From chang@nexen.com Mon Jul 21 09:18:14 1997
> Date: Mon, 21 Jul 1997 12:16:56 -0400 (EDT)
> From: Luke Chang <chang@nexen.com>
> To: huq@rockie.nsc.com
> Subject: Re: Pin numbering for BGA packages.
> Cc: ibis@vhdl.org
> 
> Hi Syed,
> 
> Can a pin name start with any character, such as _, !, @, #, $, 5, 6, *, and &,
> or does it have to start with a letter (a-z, A-Z)?
> 
> Luke Chang
> Fujitsu Nexion, Inc.
> Acton, MA
> 
> 
> ----- Begin Included Message -----
> 
> >From owner-ibis@server.vhdl.org Mon Jul 21 12:12:31 1997
> Date: Mon, 21 Jul 97 08:54:35 PDT
> From: huq@rockie.nsc.com (Syed Huq)
> To: ibis@vhdl.org, eitan@galileo.co.il
> Subject: Re: Pin numbering for BGA packages.
> Content-Length: 1293
> 
> Eitan,
> 
> The IBIS standard states that the [Pin] field can have 5 characters
> Max. So you can either use numbers or letters or combination of both
> not to exceed 5 characters.
> 
> Regards,
> Syed
> National Semiconductor Corp.
> 
> > From owner-ibis@server.vhdl.org Sun Jul 20 08:37:03 1997
> > Comments: Authenticated sender is <eitan@galileo21>
> > From: "Eitan Medina" <eitan@galileo.co.il>
> > Organization: Galileo Technology Ltd.
> > To: ibis@vhdl.org
> > Date: Sun, 20 Jul 1997 16:07:04 +0200
> > Content-Type> : > text/plain> ; > charset=US-ASCII> 
> > Content-Transfer-Encoding: 7BIT
> > Subject: Pin numbering for BGA packages.
> > X-Mailer: Pegasus Mail for Windows (v2.33)
> > 
> > Hi,
> > 
> > I have a device packaged in BGA package.
> > In these packages the pins are not numbered from 1 to 208 (or whatever),
> > but in Ball# (A1,A2,...C1,C2,C3...).
> > 
> > IBIS ver 2.1 does not say anything on this.
> > 
> > Is it legal to place Ball# instead of pin# ?
> > 
> > Thanks,
> > 
> > Eitan Medina
> > Email: eitan@galileo.co.il
> > Galileo Technology Ltd.
> > 15 Geron st. 
> > P.O.Box 2786
> > Yehud 56217
> > ISRAEL
> > Tel:   +972-3-6320220
> > Fax:   +972-3-6320221 
> > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
> > * check out our new web site:   http://www.GalileoT.com *
> > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
> > 
> 
> 
> ----- End Included Message -----
> 
> 
 
From owner-ibis  Mon Jul 21 11:58:16 1997
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Date: Mon, 21 Jul 1997 11:57:16 -0700
To: ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Re: Pin numbering for BGA packages.
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Hi Luke,
At 12:16 PM 7/21/97 -0400, you wrote:
>Can a pin name start with any character, such as _, !, @, #, $, 5, 6, *,
and &,
>or does it have to start with a letter (a-z, A-Z)?

Pin names can start with numbers and A-Z.  Using other characters is
likely to be problematic given the number of IBIS translators out there.
I would recommend against it.



-------------------------------------------------------------------------
Have a great day...
Kellee Crisafulli at HyperLynx
kellee@hyperlynx.com	http://www.hyperlynx.com
-------------------------------------------------------------------------
 
From owner-ibis  Mon Jul 21 14:20:41 1997
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From owner-ibis  Thu Jul 24 15:43:13 1997
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please unsubscribe me from this mailing list

thanks



 
From owner-ibis  Sun Jul 27 08:50:24 1997
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From: psd <psd@powermail.intouch.com>
To: ibis@vhdl.org
Message-ID: <@x400gw.infonet.com>
Subject: Some questions

     
     Dear Sir.
     
     I have read some documents on the IBIS from the internet and I have 
     some questions to ask:
     
     1- In the simulator you have two curves one for the Pull-up, Pull-down 
     and the other for the Clamp diodes, these two curves are on the same 
     pin I mean you can not get each of them individually so how can you 
     check these curves with the actual Lab measurements. ?
     
     2- When You made these measurements in the LAB ,if you have the IC pin 
     always high when you apply the VCC to that pin, how can you vary the 
     voltage to measure the current variations?
     
     3- Are you sure that the voltage change between -Vcc to 2Vcc will not 
     harm the IC pin??
     
     4- These IC characteristics (IV ,Ramp...) is measured on the pins when 
     all the IC pins are free so are these C/S will not change when the IC 
     is connected inside the circuit or some pins within the IC itself is 
     connected to another pins to the same IC ??
     
     
     Thanks for your cooperation.
     Hany Gad.
 
From owner-ibis  Sun Jul 27 21:40:39 1997
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Date: Sun, 27 Jul 1997 21:49:04 -0700
From: Jon Powell <jonp@pacbell.net>
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Organization: Viewlogic Consulting Services
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psd wrote:
> 
> 
>      Dear Sir.
> 
>      I have read some documents on the IBIS from the internet and I have
>      some questions to ask:
> 
>      1- In the simulator you have two curves one for the Pull-up, Pull-down
>      and the other for the Clamp diodes, these two curves are on the same
>      pin I mean you can not get each of them individually so how can you
>      check these curves with the actual Lab measurements. ?
There are some inherent difficulties trying to make IBIS models from
physical measurement. If you can't probe inside the chip to control or
cut out things (which is VERY expensive) then you have to make some
assumptions about how transistors work and extract your data from that.
> 
>      2- When You made these measurements in the LAB ,if you have the IC pin
>      always high when you apply the VCC to that pin, how can you vary the
>      voltage to measure the current variations?
You are varying the voltage at the input. A programmable voltage source,
CURRENT LIMITED, works good.
> 
>      3- Are you sure that the voltage change between -Vcc to 2Vcc will not
>      harm the IC pin??
It will melt it to slag. I recommend you stop your sweep very quickly
when the overshoot diodes cut on and LIMIT YOUR CURRENT to around 300ma.
> 
>      4- These IC characteristics (IV ,Ramp...) is measured on the pins when
>      all the IC pins are free so are these C/S will not change when the IC
>      is connected inside the circuit or some pins within the IC itself is
>      connected to another pins to the same IC ??
Sorry, I don't follow this. If your are asking, "can the package
parasitics mask the AC behavior of the part during transition
measurement?" the answer is "yes".
This is why I usually recommend that people make models either from high
quality SPICE like simulations (which presumably come from good
measurements made at the factory) or from raw data generated by the chip
manufacturer.

Special Note:
There are people out there making good models from measurement (I may
even be one of them) but it is very expensive and takes a lot of set up
time, measurement know-how, and spare parts (for when you slag them).


> 
> 
>      Thanks for your cooperation.
>      Hany Gad.


Your Welcome,
Jon Powell
Senior Scientist, Viewlogic Systems Consulting services 
(formally of the Quad Design group)

 
From owner-ibis  Mon Jul 28 05:45:37 1997
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From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
To: psd@powermail.intouch.com
Cc: ibis@vhdl.org, ingraham@wrksys.ENET.dec.com
Apparently-To: ibis@vhdl.org, psd@powermail.intouch.com
Subject: Re: Some questions

Hany Gad asks:

>    1- In the simulator you have two curves one for the Pull-up, Pull-down 
>    and the other for the Clamp diodes, these two curves are on the same 
>    pin I mean you can not get each of them individually so how can you 
>    check these curves with the actual Lab measurements. ?

The IBIS spec provides these four sets of curves for full flexibility,
but there are situations where not all four are either measurable, or
necessary.  In that case, one or more of the curves are zero.

For an I/O (bidirectional or tri-stateable) pin, you can measure the
clamp curves when the pin is in the OFF state.  Then measure the
characteristics in the HIGH and LOW states, and subtract the OFF state
curves to arrive at the Pull-up and Pull-down curves.

>    2- When You made these measurements in the LAB ,if you have the IC pin 
>    always high when you apply the VCC to that pin, how can you vary the 
>    voltage to measure the current variations?

Why would you apply VCC to that pin?  Is this a power pin, or a signal
pin?  I/V curves are needed for signal pins, not power pins.

If your signal pin always drives high (to VCC), then just connect a
variable voltage source to it and measure the current vs. voltage.

If this is a signal input pin that is "always" pulled high when the IC
is used, then you can either skip it (on the assumption that it "never"
needs to be simulated), or treat it just like any other input pin
(i.e., sweep its voltage and measure the current).  Remember that IBIS
models show the analog behavior of signal pins without regard to their
purpose or whether the chip works when a pin is brought low or high.

>    3- Are you sure that the voltage change between -Vcc to 2Vcc will not 
>    harm the IC pin??

It may.  But that's not the point (of IBIS modeling).  The point is
to provide expected I/V curves for what the current would be if the
voltage on a pin momentarily reached these voltages.

If you can, quickly sweep the voltage and gather data without killing
the chip.  Sweeping the voltage quickly reduces the chances of damaging
the chip.  It also better mimics what happens when an overshoot or
undershoot signal hits the IC pin, which usually don't last more than
a few nanoseconds.  DC measurements generally are not a good idea.

But not every point in the IBIS curves need to be measured.  If you
can only measure from -2V to Vcc+2V before something strange starts
happening in your IC, then take just the good data and extrapolate it
to the full -Vcc to 2Vcc range.

Regards,
Andy
 
