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From: Greg Edlund <Greg.Edlund@digital.com>
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Subject: IBIS Accuracy Sub-Committee Minutes
Date: Thu, 2 Apr 1998 15:05:09 -0500
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IBIS Accuracy Sub-Committee Minutes

Thursday, March 26, 1998
Held at Digital Equipment's PKO3 building, 129 Parker St., Maynard, MA 

Attendees

Greg Edlund, Digital Equipment (chair)
Fawn Engelmann, EMC
Bob Haller, Digital Equipment
Bruce Heilbrunn, Stratus Computer
Peter LaFlamme, Fairchild Semiconductor
Harvey Stiegler, Texas Instruments (via conference call)

Business

The chairman will be responsible for circulating the agenda the Monday
prior to the meeting and posting the minutes to the IBIS reflector and
IBIS user's group mailing list within one week.  The sub-committee
members will be responsible for circulating their homework among the
group on or before the Monday prior to the meeting.

Bob Haller has begun writing a rough draft.  He will fold other's work
into the document and circulate it among the group.  When the document
gets closer to a first release, it will go through a more formal editing
and formatting procedure.

When it becomes apparent that the group cannot agree on an issue, we
have agreed to table the issue until the next meeting to prevent
grid-lock.  In the mean time, parties will have the opportunity to
discuss the issue off-line and build a case, which will be presented
briefly at the next meeting and brought up for a vote.

Correspondence

The chairman received much positive and constructive feedback from
publishing the "Proposal for an IBIS Accuracy Specification," and we
reviewed this feedback at the meeting.  We also received some dissenting
opinions which in general ran along the lines that the work of the IBIS
Accuracy Sub-Committee did not need to carry the full weight of a
specification.  (In our discussions we maintained anonymity for those
who had negative opinions so as to avoid any flame wars.)  In addition,
there seemed to be some points of confusion in the proposal; it may need
to be reworded in some areas.  The IBIS Accuracy Sub-Committee would
like to thank all who took the time to respond.  We hope that people
will continue in the future to be liberal with their critical input.

Milestones

The group approved the setting of three milestones, to which we will add
as we work out the details.

May 15, 1998:  Post the IBIS Model Test Board to the web.
September 18, 1998: Distribute the first draft of the IBIS Accuracy
Specification
February 1999:  Present the IBIS Accuracy Specification at DesignCon99

Editing

1. Scope

Peter Laflamme successfully completed his research into IBIS
"parameters" from version 1.1 through 3.0 which might be relevant to
accuracy.  In summary, these parameters include I/O buffer capacitance,
package RLC, IV curves, and ramp rate.  He also presented a list of
other parameters which might be relevant in the future.

The discussion continued around how much of IBIS we should attempt to
cover in the first release of the IBIS Accuracy Specification.  Bruce
Heilbrunn, supported by a former colleague from Stratus, argued that the
first draft of the IBIS Accuracy Specification should cover the entirety
of IBIS 3.0.  Greg Edlund and Bob Haller argued that IBIS has evolved to
cover various new I/O buffer designs which may require different test
conditions than a generic IBIS 1.1 push-pull or open-drain buffer.  Greg
and Bob's position is that it would be too much work to attempt to cover
all possible I/O buffer designs currently covered by IBIS 3.0 in the
first draft.  The sub-committee tabled the issue for a vote at the next
meeting.

2. Test Loads

Bob Haller documented a first cut at a set of test loads in his rough
draft.  These include standard load, transmission line terminated into
its characteristic impedance (or resistive load if board layout
permits), open-ended transmission line, and output buffer driving an
input buffer on the same component.

Bob also proposed two other "optional" net topologies, but the group has
yet to decide whether these belong in the IBIS Accuracy Specification or
the IBIS Cookbook.

3. Measurement Techniques

Bob's rough draft also included an outline of measurement techniques,
including oscilloscope bandwidth, test environment characterization, and
test conditions.

4. Metrics

We did not discuss comparison metrics at this meeting.

IBIS Model Test Board

Peter Laflamme, Fawn Engelmann, and Greg Edlund have successfully
debugged everything on the test board except for the capacitance
measurement.  If anyone has experience measuring pin capacitance on a
powered-up DUT using an HP4175 LCR meter, please drop us a line!  Fawn
and Greg will be making modifications to the schematics and layout and
submitting the design for fabrication and assembly in the next two
weeks.  Peter Laflamme has graciously offered the services of
Fairchild's PC board shop to build this new revision of the board.

IBIS Developers Tool Kit

Following the lead of Hyperlynx's, Bruce Heilbrunn has drafted a letter
to the other EDA vendors requesting a similar tool be made available to
the IBIS community in the coming year.  It is our feeling that a
reduced-feature simulation engine would be a great aid in the model
development process.  Furthermore, if modeling engineers have several
simulation engines available, they can assess the magnitude of the
differences among them for various test cases.  For the purposed of the
IBIS Accuracy Sub-Committee, this may allow us to avoid any pitfalls
arguing over third-order effects.

IBIS Cookbook

Bob Haller and Stephen Peters have agreed to work together to complete
the remaining two chapters of the IBIS Cookbook related to measurement
and verification.  Clearly, there is much overlap between the work of
the IBIS Accuracy Sub-Committee and the Cookbook.

Homework

Greg Edlund - finish schematics and layout of the IBIS Model Test Board.
Build a strong case for why different driver families may require
different test loads and why the first version of the IBIS Accuracy
Specification needs to be constrained to IBIS 1.1; discuss off-line

Fawn Engelmann - finish schematics and layout of the IBIS Model Test
Board.

Peter LaFlamme - list all  IBIS 1.1 keywords that are relevant to the
IBIS Accuracy Specification.  Ask Mike Ward if he is willing to provide
input to the Measurement Techniques section.

Bob Haller - continue developing the Measurement Techniques section.
Discuss with Stephen Peters an outline of IBIS Cookbook chapters 5 and
6.

Bruce Heilbrunn - add a list of suggested features to the IBIS
Developer's Toolkit letter.  Build a strong case for how the IBIS
Accuracy Specification can cover all I/O buffers covered by IBIS 3.0
within the constraints of our milestones; discuss off-line.

Next meeting

Thursday, April 30, 1998 from 3:00 to 5:00 pm at Digital Equipment's
PKO3 building, 129 Parker St., Maynard, MA.

----------
Greg Edlund, Principal Engineer
Server Product Development
Digital Equipment Corp.
129 Parker St. PKO3-1/20C
Maynard, MA 01754
(978) 493-4157 voice
(978) 493-0941 FAX
greg.edlund@digital.com
From owner-ibis  Thu Apr  2 14:02:30 1998
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From: bobr@wv.mentorg.com (Bob Ross)
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Message-Id: <9804022158.AA07786@bob>
To: ibis@eda.org
Subject: IBIS BIRD48 - Add Model


Dear IBIS folks:

BIRD45.1 has been out for a while and there have been even some technical
suggestions for improvement.  However, one suggestion was to investigate
how it could utilize the [Driver Schedule] keyword.  This was investigated,
and after looking at some very complicated interactions at a meeting with
Arpad Muranyi, Bob Ross, and Chris Reid on March 11, 1998, we decided to
propose a more general and expandable mechanism that supports actual EDA
tool implementation modularization and also IBIS modularized reuse of
the existing structures when relevant.   This will reduce the expansion
of keywords support every new idea that comes along.

The actual details were not discussed at that meeting.  However, after some
further reflections, the [Add Model] and [Add Model Spec] keywords are 
proposed here along with BIRD49 and BIRD50 for the first two implementations

The rationale is discussed within BIRD48.  BIRD49 and BIRD50 are proposed
applications of the rationale for Dynamic Clamps and Bus Hold additions.
BIRD48, BIRD49, and BIRD50 are interrelated and should be considered
together.

This will be discussed at the April 3, 1998 IBIS meeting.

Bob Ross
Interconnectix/Mentor Graphics


******************************************************************************
******************************************************************************

BIRD ID#:      48
ISSUE TITLE:   Add Model
REQUESTER:     Neven Orhanovic, Bob Ross, Mentor G., Arpad Muranyi, Intel
DATE SUBMITTED: 4/2/98
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************
******************************************************************************

STATEMENT OF THE ISSUE:

A method is needed to add model feature details to an existing IBIS [Model]
for unanticipated technical expansion requirements.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

Following the [Model Spec] keyword will be this new keyword:

|==============================================================================
|     Keywords:     [Add Model]
|     Required:     No
|     Description:  References a special model to be added to an existing
|                   model.
|     Sub-Params:   None
|     Usage Rules:  Each [Add Model] adds to an existing model from which
|                   [Add Model] is invoked some additional model information 
|                   that is documented within another [Model] of the model
|                   listed below:
|
|                      Dynamic_clamp
|                      Bus_hold
|
|                   For example, the bus hold electrical characteristics
|                   modeled by a restrictive Bus_hold model may added to an
|                   Input or I/O model.
|
|                   More Model_types may be added in the future to deal with
|                   technological advances.
|
|                   Refer to the Add Model Section in this document for a
|                   for the rules and descriptions of models that can be
|                   added.
|
|------------------------------------------------------------------------------
[Add Model]     Bus_Hold_1          | Adds the electrical characteristics of
                                    | [Model] Bus_Hold_1 the existing [Model]
|
|==============================================================================



Add a new section:


|=============================================================================
|=============================================================================
|
|                                 Section 6a
|
|                 A D D    M O D E L    D E S C R I P T I O N
|
|=============================================================================
|=============================================================================
|
| The [Add Model] keyword is an optional extention to an existing [Model]
| for the purposes of adding some special-purpose detail.  The [Add Model]
| keyword references a new model containing this functional detail.
|
| In general, models which are used for the purposes of adding functional
| detail will still use the [Model] keyword and some subset of its associated
| keywords.  The required or allowable keywords for each type of new [Model]
| that can be invoked by the [Add Model] keyword are discussed.
|
| these subparameters which are defined under [Model] continue to be required:
|
|    Model_type
|    C_comp
|
| [Voltage Range] is required unless all four of the reference voltages
| [Pullup Reference], [Pulldown Reference], [GND Clamp Reference], and [POWER
| Clamp Reference] are provided.  These reference voltages are optional in
| as previously defined, but are all required if [Voltage Range] is not used.
|
| The Model_type subparameter will be used to determine the functional
| components that are required within that model.
|
| The [Model Spec] keyword is reserved for externally available specification
| information.  It should not appear in a model reference by [Add Model].
| Instead, the [Add Model Spec] keyword is defined to provide additional
| information that is needed, but is normally not available in any data sheet.
| The model provider may possess internal, proprietary documentation that 
| contains the information.
|
|=============================================================================
|     Keyword:  [Add Model Spec]
|    Required:  No
|  Sub-Params:  V_trig_r, V_trig_f
| Description:  The [Add Model Spec] keyword defines four columns under which
|               specification and information subparameters are defined for
|               [Model]s which are called by the [Add Model] keyword.
|
|               The [Add Model Spec] is to be used only with models for the
|               Model_type: Dynamic_clamp and Bus_hold.
|                
|               The following subparameters are defined:
|               V_trig_r           Rising edge trigger voltage
|               V_trig_f           Falling edge trigger voltage
|
| Usage Rules:  [Add Model Spec] must follow all other subparameters under the 
|               [Model] keyword.
|
|               For each subparameter contained in the first column, the 
|               remaining three hold its typical, minimum and maximum values.
|               The entries of typical, minimum and maximum be must be placed 
|               on a single line and must be separated by at least one white
|               space or tab or tab character.  All four columns are required
|               under the [Model Spec] keyword.  However, data is required
|               only in the typical column.  If minimum and/or maximum values
|               are not available, the reserved word "NA" must be used
|               indicating the typical value by default.
|
|               The minimum and maximum values are used for specifications
|               subparameter values that may track the min and max operation
|               conditions of the [Model].  Usually it is related to the
|               Voltage Range settings.
|
|               Unless noted below, each subparameter does not require having
|               any other subparameter.
|      
|               V_trigger_r, V_trigger_f rules:
| 
|               The voltage trigger values for the rising and falling edges
|               edges provide the starting time at which an action is
|               initiated.
|               
|-----------------------------------------------------------------------------
[Add Model Spec]
|   Subparameter          typ        min        max
|
| Dynamic Clamp
|
V_trigger_h               3.6        2.9        4.3 | Starts power pulse table
V_trigger_f               1.4        1.2        1.6 | Starts gnd pulse table
|
| Bus Hold
|
V_trigger_h               3.1        2.4        3.7 | Starts low to high 
                                                    | bus hold transition
V_trigger_f               1.8        1.6        2.0 | Starts high to low
                                                    | bus hold transition
|
|
|=============================================================================


******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

After considering the Dynamic Clamp and then seeing the need for a more
general mechanism for also adding "latching" in the model - to be added
to the existing Model, a new keyword is proposed for adding special purpose
models.  

New Model_types will be defined for the special purposes.  The [Model Spec]
keyword will be used to add additional control or information subparameters.

Additional keywords may be proposed that apply only to the specific model
type.  However, this model call method also allows using the existing
keywords to construct the added functionality.

One motivation for this alternative construction is based on BIRD45.1 for
Dynamic Clamps.  BIRD45.1defines some new clamping tables.  However, with a
special purpose model defined in BIRD49, the existing [GND Clamp] and [POWER
Clamp] keywords can be used along with others to add a clamp that has a
controlled reference shift over time.

A similar motivation is BIRD50 for a new Bus_hold mechanism.  The terminology
is still up for discussion.  This mechanism can be used to add to the
Input or I/O model a Bus-Hold Circuit similar to how they are being currently
implemented - via a weak output stage that switches according to thresholds.
This mechanism also models the functionally of some proprietary structures
that also produce a latching effect via some weak output stages.

An alternative that was intially considered was to lump several "related"
extensions into its own Model_type (the Model_types could even be called
Extension_1, Extension_2, etc.)  However after considering this for the
Dynamic Clamp and Bus Hold functionality, this was rejected.  The interaction
of several Model_type specific rules would be combersome and confusing to
document.

BIRD48 also defines a consistent and understandable mechanism [Add Model]
to add electrical and informational functionality of new feature that have
not been defined.

Using just [Model Spec] for some additional specification subparameters was
considered.  However, the [Model Spec] keyword should really be used for
real, external specification subparameters.  So the internal [Add Model Spec]
as added in a parallel manner to deal with internally specified parameters
that are needed for the additional model, but may not appear in data sheets
or data books.

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

BIRD48 is an evolution in thinking starting with BIRD45 for dynamic clamps.
The need to consider some output models withing the clamping structure, but
the proposals were becoming extremely complex with many new keywords, and
with possible augmentation to the already complex [Driver Schedule] keyword.

Several meetings were held on this subject.  The last meeting on March 11,
1998 with Chris Reid, Bob Ross, and Arpad Muranyi was held to consider these
complicated additions.  The outcome was essentially a proposal that new
Model_types can be defined for specific additions, the models themselves
would could contain very well-defined information including new keywords
that were allowed only with [Model]s of that type, and that the models
would be called by an [Add Model] mechanism within another model.  This seemed
to fit implementation architectures where the new model information is well
modularized (and in some cases just uses the same structures), and provided
electrical information that is additive (or subtractive) to the existing
models.

The proposal here is an extension of what was discussed at the March 11, 1998
meeting based on some further reflections to associate any new functionality
with its own Model_type.

******************************************************************************



From owner-ibis  Thu Apr  2 14:05:03 1998
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From: bobr@wv.mentorg.com (Bob Ross)
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	id AA07816; Thu, 2 Apr 98 14:01:34 PST
Date: Thu, 2 Apr 98 14:01:34 PST
Message-Id: <9804022201.AA07816@bob>
To: ibis@eda.org
Subject: IBIS BIRD50 - Add Model Bus Hold


Dear IBIS folks:

BIRD50 describes a bus hold extension which is also useful for other similar
structures.

Bob Ross
Interconnectix/Mentor Graphics

******************************************************************************
******************************************************************************

BIRD ID#:       50
ISSUE TITLE:    Add Model Dynamic Clamps
REQUESTER:      Neven Orhanovic, Bob Ross, Mentor G., Arpad Muranyi, Intel
DATE SUBMITTED: 4/2/98
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************
******************************************************************************

STATEMENT OF THE ISSUE:

New devices incorporate bus hold or other latching mechanisms to hold the
input at a particular state using some active pullup and pulldown components.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The Bus Hold functionality is added in the new Section 6a:

| Bus Hold:
|
| The bus hold functionality is defined by the Model_type 'Bus_hold'.  The
| [Pullup] and [Pulldown] tables both are used to define a weak internal 
| buffer that is triggered to be set in the opposite state of the signal.
| The transistion is defined normally by a [Ramp] keyword, but, the [Rising
| Waveform] and [Falling Waveform] keywords also may be used.
|
| The transition is triggered by action at the die using the [Add Model Spec]
| V_trigger_r and V_trigger_f subparameters as follows:
|
| If the starting voltage is below V_trigger_f, then the Bus_hold model is
| set to the low stage causing additional pulldown current.  If the starting
| voltage is above V_trigger_r, the Bus_hold model is set to the high
| state for additional pullup current.  When the input passes though
| V_trigger_f during a high to low transition at the die, the Bus_hold output
| changes to the low state.  Similarly when the input passes though
| V_trigger_r during a low to high transition at the die, the Bus_hold output
| change to the high state.
|
| No additional keywords are needed for this functionality.


|------------------------------------------------------------------------------
|
| Complete Bus_hold Model Example:
|
[Model]       Bus_hold_1
Model_type    Bus_hold
C_comp        0 0 0
|
[Add Model Spec]
|   Subparameter          typ        min        max
|
V_trigger_f               1.3        1.2        1.4  | Falling edge trigger
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger
|
[Pulldown]   
|
-5V     -100uA     -80uA     -120uA
-1V      -30uA     -25uA     -40uA
0V       0           0         0
1V       30uA       25uA     40uA
3V       50uA       45uA     50uA
5V       100uA      80uA     120uA
10v      120uA      90uA    150uA
|
[Pullup]
|
-5V      100uA      80uA     120uA
-1V      30uA       25uA     40uA
0V       0           0         0
1V       -30uA      -25uA    -40uA
3V       -50uA      -45uA    -50uA
5V       -100uA     -80uA    -120uA
10v      -120uA     -90uA    -150uA
|
|****************************************************************************
|
[Ramp]
|                       typ             min             max
dV/dt_r                 2.0/0.50n       2.0/0.75n       2.0/0.35n
dV/dt_f                 2.0/0.50n       2.0/0.75n       2.0/0.35nn
|
|****************************************************************************

|==============================================================================

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

A weak driver can be added using the [Add Model] keyword.

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

This proposal is based on a conversation with Bob Ross, Chris Reid, and
Arpad Muranyi on March 11, 1998.

******************************************************************************



From owner-ibis  Thu Apr  2 14:07:07 1998
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From: bobr@wv.mentorg.com (Bob Ross)
Received: by bob (4.1/CF5.23L)
	id AA07790; Thu, 2 Apr 98 14:00:26 PST
Date: Thu, 2 Apr 98 14:00:26 PST
Message-Id: <9804022200.AA07790@bob>
To: ibis@eda.org
Subject: IBIS BIRD49 - Add Model Dynamic Clamps


Dear IBIS folks:

BIRD49 follows BIRD48 with a specific implementation for the Dynamic
Clamp functionality of BIRD45.1.  The [Add Model Spec] keyword is used
to define the typ, min, and max threshold rules formated using 4 columns.

The [GND Clamp] and [POWER Clamp] keywords replace the new keywords
[Dynamic GND Clamp] and [Dynamic POWER Clamp] in BIRD45.1.  The [GND Pulse
Table] and [POWER Pulse Table] keyword are introduced.

BIRD49 is derived from BIRD45.1 directly, but with changes corresponding
to the Add Model construction methology and also in accordance with some
comments on BIRD45.1.

Bob Ross
Interconnectix/Mentor Graphics

******************************************************************************
******************************************************************************

BIRD ID#:       49
ISSUE TITLE:    Add Model Dynamic Clamps
REQUESTER:      Neven Orhanovic, Bob Ross, Mentor G., Arpad Muranyi, Intel
DATE SUBMITTED: 4/2/98
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************
******************************************************************************

STATEMENT OF THE ISSUE:

A novel type of termination technique is used in today's integrated circuits.
The termination consists of a pair of built in dynamic clamps whose V-I curves 
change with time. The clamp is switched "on" when needed and switched 
"off" otherwise (to conserve power). When the clamp is switched "on" its V-I 
curve provides more clamping than a regular static clamp and when it is 
turned "off" it behaves like a normal clamp. 

The "on" switching of the dynamic clamps can be triggered by an input signal 
crossing a triggering threshold or by some external clock. The "off" switching 
can be triggered by a built in timer or an external clock.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The dynamic clamp functionality is added in the new Section 6a:


| Dynamic Clamp:
|
| This section introduces the dynamic clamp add model functionality.  Two
| new keywords [GND Pulse Table] and [Power Pulse Table] are defined.  Then
| and example is provided for a complete dynamic clamp model.
|
|=============================================================================
|     Keyword:  [GND Pulse Table], [POWER Pulse Table]
|    Required:  No
| Description:  Used to dynamically specify the offset voltage of added [GND
|               Clamp] and [POWER Clamp] tables when the [Model] adds the
|               dynamic clamp functionality.
|
| Usage Rules:  Each [GND Pulse Table] and [POWER Pulse Table] keyword
|               introduces a table of time vs. voltage points that describe
|               the shape of an offset voltage from the [GND Clamp Reference]
|               voltage (or default ground) or the [POWER Clamp Reference]
|               voltage (or default [Voltage Range] voltage).  These
|               time/voltage points must start and end at the same value.
|
|               The table itself
|               consists of one column of time points, then three columns of
|               voltage points in the standard typ, min, and max format.  The
|               four entries must be placed on a single line and must be
|               separated by at least one white space or tab character.  All
|               four columns are required.  However, data is only required in
|               the typical column.  If minimum or maximum data is not
|               available, use the reserved word "NA".  The first value in the
|               time column need not be '0'.  Time values must increase as one
|               parses down the table.  The waveform table can contain a
|               maximum of 100 data points.  Only one [GND Pulse Table] and
|               one [POWER Pulse Table] are allowed per model.
|
|               A pulse table must include the entire waveform; i.e., the
|               first entry (or entries) in a voltage column must be equal
|               to the last entry.  Each table must contain at least two
|               entries.  Thus, numerical values are required for the first
|               and last entries of any column containing numerical data.
|
|              The [GND Pulse Table] and [POWER Pulse Table] keywords are used.
|              The subparameter under [Add Model Spec] for V_trigger_f checks
|              when the pulse at the die passes the trigger voltage.  At that
|              time, the [GND Pulse Table] is invoked and the 
|              dynamic [GND Clamp] shifts its reference by the specified
|              offset voltage.  Similarily, the V_trigger_f subparameter gives
|              the voltage of the rising edge of the die at which the [POWER
|              Pulse Table] is invoked and the dynamic [POWER Clamp] table 
|              begins shifting its reference by the specified offset voltage.
|
|              A dynamic clamp is modeled by a V-I curve that is offset 
|              (translated) along the voltage axis with the voltage waveform 
|              given in the [GND Pulse Table] or [POWER Pulse Table] section
|              The resulting dynamic V-I table can be expressed as
|     
|                   I = f( V - V_pulse(t) ),
|
|              where V_pulse(t) is the offset voltage waveform described by 
|              the pulse table and f(V) is the resulting V-I curve 
|              of the clamp in its off state, corresponding to the data 
|              given in the [GND Clamp] or [POWER Clamp] keyword.
|               
|              For example, once the voltage on the clamp crosses the
|              triggering threshold V_trigger_f, the [GND Pulse Table] data
|              is used to offset the V-I curve obtained 
|              from the [GND Clamp] section. The dependence of the offset
|              pulse on the clamp voltage is illustrated below.
|
|                                 V_trigger_f
|
|            o o o o           
|                    o
|                     o
|                      o -------
|                      |o       ^ 
|                      | o      | V_trigger_f
|                      |  o     v               time
|                      |    o o-------------------->
|                      |
|                      |              
|                      |             [GND Pulse Table]
|                      |      Clamp offset voltage vs. time.
|                      |
|                      |             o o o o    
|                      |            o        o     
|                      |           o           o  
|                      |          o              o 
|                      |         o                 o 
|                      |        o                    o          time
|                      o o o o o                       o o o -------->
|
|                      ^
|                      |_  Pulse data is used from this moment on
|                          to offset the V-I curve.
|
| The V_trigger_r and [POWER Pulse Table] operate in a similar manner.
| However, offset voltage which fall into the normal operation region are
| given by negative voltage values.
|
|------------------------------------------------------------------------------
|
| Example Dynamic_clamp Model with both dynamic GND and POWER clamps:
|
[Model]       Dynamic_Clamp_1
Model_type    Dynamic_clamp
C_comp        0 0 0
|
[Add Model Spec]
|   Subparameter          typ        min        max
|
V_trigger_f               1.4        1.2        1.6  | Falling edge trigger
V_trigger_r               3.6        2.9        4.3  | Rising edge trigger
|
[GND Pulse Table]                                    | GND Clamp offset table
|    Time          V(typ)       V(min)        V(max)
|
|       0             0            0             0
|    1e-9             0            0             0
|    2e-9           0.9          0.8           1.0
|   10e-9           0.9          0.8           1.0
|   11e-9             0            0             0 
|
[GND Clamp]                                          | Table to be offset
|
|  Voltage        I(typ)       I(min)        I(max)
|
    -5.000     -3.300e+01    -3.000e+01    -3.500e+01
    -4.000     -2.300e+01    -2.200e+01    -2.400e+01
    -3.000     -1.300e+01    -1.200e+01    -1.400e+01
    -2.000     -3.000e+00    -2.300e+00    -3.700e+00
    -1.900     -2.100e+00    -1.500e+00    -2.800e+00
    -1.800     -1.300e+00    -8.600e-01    -1.900e+00
    -1.700     -6.800e-01    -4.000e-01    -1.100e+00
    -1.600     -2.800e-01    -1.800e-01    -5.100e-01
    -1.500     -1.200e-01    -9.800e-02    -1.800e-01
    -1.400     -7.500e-02    -7.100e-02    -8.300e-02
    -1.300     -5.750e-02    -5.700e-02    -5.900e-02
    -1.200     -4.600e-02    -4.650e-02    -4.550e-02
    -1.100     -3.550e-02    -3.700e-02    -3.450e-02
    -1.000     -2.650e-02    -2.850e-02    -2.500e-02
    -0.900     -1.850e-02    -2.100e-02    -1.650e-02
    -0.800     -1.200e-02    -1.400e-02    -9.750e-03
    -0.700     -6.700e-03    -8.800e-03    -4.700e-03
    -0.600     -3.000e-03    -4.650e-03    -1.600e-03
    -0.500     -9.450e-04    -1.950e-03    -3.650e-04
    -0.400     -5.700e-05    -2.700e-04    -5.550e-06
    -0.300     -1.200e-06    -1.200e-05    -5.500e-08
    -0.200     -3.000e-08    -5.000e-07     0.000e+00
    -0.100      0.000e+00     0.000e+00     0.000e+00
     0.000      0.000e+00     0.000e+00     0.000e+00
     5.000      0.000e+00     0.000e+00     0.000e+00
|
[POWER Pulse Table]                                 | POWER Clamp offset table                               |
|    Time          V(typ)       V(min)        V(max)
|
|       0             0            0             0
|    1e-9             0            0             0
|    2e-9          -0.9         -1.0          -0.8
|   10e-9          -0.9         -1.0          -0.8
|   11e-9             0            0             0 
|
[POWER Clamp]                                       | Table to be offset
|
|  Voltage        I(typ)        I(min)        I(max)
|
    -5.000      1.150e+01     1.100e+01     1.150e+01
    -4.000      7.800e+00     7.500e+00     8.150e+00
    -3.000      4.350e+00     4.100e+00     4.700e+00
    -2.000      1.100e+00     8.750e-01     1.300e+00
    -1.900      8.000e-01     6.050e-01     1.000e+00
    -1.800      5.300e-01     3.700e-01     7.250e-01
    -1.700      2.900e-01     1.800e-01     4.500e-01
    -1.600      1.200e-01     6.850e-02     2.200e-01
    -1.500      3.650e-02     2.400e-02     6.900e-02
    -1.400      1.200e-02     1.100e-02     1.600e-02
    -1.300      6.300e-03     6.650e-03     6.100e-03
    -1.200      4.200e-03     4.750e-03     3.650e-03
    -1.100      2.900e-03     3.500e-03     2.350e-03
    -1.000      1.900e-03     2.450e-03     1.400e-03
    -0.900      1.150e-03     1.600e-03     7.100e-04
    -0.800      5.500e-04     9.150e-04     2.600e-04
    -0.700      1.200e-04     4.400e-04     5.600e-05
    -0.600      5.400e-05     1.550e-04     1.200e-05
    -0.500      1.350e-05     5.400e-05     1.300e-06
    -0.400      8.650e-07     7.450e-06     4.950e-08
    -0.300      6.250e-08     7.550e-07     0.000e+00
    -0.200      0.000e+00     8.400e-08     0.000e+00
    -0.100      0.000e+00     0.000e-08     0.000e+00
     0.000      0.000e+00     0.000e+00     0.000e+00
|
|==============================================================================




******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

The proposal is designed to retain as much of the existing IBIS clamp syntax 
as possible. The dynamic clamp V-I curve tables follow all of the 
conventions of the existing V-I tables. 

The overall modeling approach is to decompose the dynamic clamp into its
static and dynamic portions. The static part can be modeled by a regular
clamp. The dynamic part is connected to the same rail voltage as its static
part and modeled by a V-I curve that is shifted along the voltage axis by 
the offset voltage pulse. 

BIRD49 replaces the BIRD45.1 proposal of some new keywords shown below, but
preserves the intended functionality.  It also reponses to the comment
that some of the V_trigger subparameters should be expressed in a
typ-min-max format.  The [Model Spec] keyword structure is proposed to
do this.  The replaced structure is below.

|==============================================================================
| Keywords:    [Dynamic GND Clamp], [Dynamic POWER Clamp]
| Required:    No.
| Description: Describes ground and power clamps that are switched on and off 
|              dynamically.
|
| Subparameters: V_trigger, V_trigger_min, V_trigger_max
|
| Usage Rules: The [Dynamic GND Clamp] and [Dynamic PWR Clamp] specifications 
|              contain three subparameters and two keywords. The subparameters 
|              (V_trigger, V_trigger_min, V_trigger_max) specify the threshold 
|              clamp voltage value that causes the clamp to begin switching 
|              from "off" to "on" according to the [Pulse Table] section. 
|              These values correspond to the typical, weak (slow), and strong 
|              (fast) situations. The [Pulse Table] section describes the 
|              switching characteristics of the dynamic clamp, and the [Clamp 
|              Table] section gives the V-I table of the clamp in its "off" 
|              state. This data is used as follows.
|
|              A dynamic clamp is modeled by a V-I curve that is offset 
|              (translated) along the voltage axis with the voltage waveform 
|              given in the [Pulse Table] section. The resulting dynamic V-I 
|              curve can be expressed as
|     
|                   I = f( V - V_pulse(t) ),
|
|              where V_pulse(t) is the offset voltage waveform described by 
|              the [Pulse Table] section and f(V) is the resulting V-I curve 
|              of the clamp in its off state, corresponding to the data 
|              given in the [Clamp Table] section. The [Clamp Table] data 
|              follows the same format and rules as the V-I curve data of 
|              the corresponding regular ground or power clamp ([GND Clamp], 
|              [POWER Clamp]). The [Pulse Table] section describes the offset 
|              voltage waveform and uses the same format as the [Rising 
|              Waveform] and [Falling Waveform] sections in driver models.
|               
|              Once the voltage on the clamp crosses the triggering threshold,
|              the [Pulse Table] data is used to offset the V-I curve obtained 
|              from the [Clamp Table] section. The dependence of the offset
|              pulse on the clamp voltage is illustrated below.
|
|
|                            Clamp voltage vs. time.
|
|                           o o o o 
|                         o
|                       o
|                      o -------
|                     o|       ^ 
|                    o |       | V_trigger
|                   o  |       v            time
|               o o    | ------------------------>
|                      |
|                      |              
|                      |              
|                      |      Clamp offset voltage vs. time.
|                      |
|                      |                      o o o o    
|                      |                    o        o     
|                      |                  o           o  
|                      |          o o o o              o 
|                      |         o                      o 
|                      |        o                        o          time
|                      o o o o o                          o o o -------->
|
|                      ^
|                      |_  Pulse data is used from this moment on
|                          to offset the V-I curve.
|                      
|      
|------------------------------------------------------------------------------
|
| Example: 
|
[Dynamic GND Clamp]
|
V_trigger     = 1.4V
V_trigger_min = 1.2V
V_trigger_max = 1.6V
|
[Pulse Table]
|
|    Time          V(typ)       V(min)        V(max)
|
|       0             0            0             0
|    1e-9             0            0             0
|    2e-9           0.9          0.8           1.0
|   10e-9           0.9          0.8           1.0
|   11e-9             0            0             0 
|
[Clamp Table]
|
|  Voltage        I(typ)       I(min)        I(max)
|
    -5.000     -3.300e+01    -3.000e+01    -3.500e+01
    -4.000     -2.300e+01    -2.200e+01    -2.400e+01
    -3.000     -1.300e+01    -1.200e+01    -1.400e+01
    -2.000     -3.000e+00    -2.300e+00    -3.700e+00
    -1.900     -2.100e+00    -1.500e+00    -2.800e+00
    -1.800     -1.300e+00    -8.600e-01    -1.900e+00
    -1.700     -6.800e-01    -4.000e-01    -1.100e+00
    -1.600     -2.800e-01    -1.800e-01    -5.100e-01
    -1.500     -1.200e-01    -9.800e-02    -1.800e-01
    -1.400     -7.500e-02    -7.100e-02    -8.300e-02
    -1.300     -5.750e-02    -5.700e-02    -5.900e-02
    -1.200     -4.600e-02    -4.650e-02    -4.550e-02
    -1.100     -3.550e-02    -3.700e-02    -3.450e-02
    -1.000     -2.650e-02    -2.850e-02    -2.500e-02
    -0.900     -1.850e-02    -2.100e-02    -1.650e-02
    -0.800     -1.200e-02    -1.400e-02    -9.750e-03
    -0.700     -6.700e-03    -8.800e-03    -4.700e-03
    -0.600     -3.000e-03    -4.650e-03    -1.600e-03
    -0.500     -9.450e-04    -1.950e-03    -3.650e-04
    -0.400     -5.700e-05    -2.700e-04    -5.550e-06
    -0.300     -1.200e-06    -1.200e-05    -5.500e-08
    -0.200     -3.000e-08    -5.000e-07     0.000e+00
    -0.100      0.000e+00     0.000e+00     0.000e+00
     0.000      0.000e+00     0.000e+00     0.000e+00
     5.000      0.000e+00     0.000e+00     0.000e+00
|
|
[Dynamic POWER Clamp]
|
V_trigger     = 3.6V
V_trigger_min = 3.8V
V_trigger_max = 3.4V
|
[Pulse Table]
|
|    Time          V(typ)       V(min)        V(max)
|
|       0             0            0             0
|    1e-9             0            0             0
|    2e-9          -0.9         -1.0          -0.8
|   10e-9          -0.9         -1.0          -0.8
|   11e-9             0            0             0 
|
[Clamp Table]
|
|  Voltage        I(typ)        I(min)        I(max)
|
    -5.000      1.150e+01     1.100e+01     1.150e+01
    -4.000      7.800e+00     7.500e+00     8.150e+00
    -3.000      4.350e+00     4.100e+00     4.700e+00
    -2.000      1.100e+00     8.750e-01     1.300e+00
    -1.900      8.000e-01     6.050e-01     1.000e+00
    -1.800      5.300e-01     3.700e-01     7.250e-01
    -1.700      2.900e-01     1.800e-01     4.500e-01
    -1.600      1.200e-01     6.850e-02     2.200e-01
    -1.500      3.650e-02     2.400e-02     6.900e-02
    -1.400      1.200e-02     1.100e-02     1.600e-02
    -1.300      6.300e-03     6.650e-03     6.100e-03
    -1.200      4.200e-03     4.750e-03     3.650e-03
    -1.100      2.900e-03     3.500e-03     2.350e-03
    -1.000      1.900e-03     2.450e-03     1.400e-03
    -0.900      1.150e-03     1.600e-03     7.100e-04
    -0.800      5.500e-04     9.150e-04     2.600e-04
    -0.700      1.200e-04     4.400e-04     5.600e-05
    -0.600      5.400e-05     1.550e-04     1.200e-05
    -0.500      1.350e-05     5.400e-05     1.300e-06
    -0.400      8.650e-07     7.450e-06     4.950e-08
    -0.300      6.250e-08     7.550e-07     0.000e+00
    -0.200      0.000e+00     8.400e-08     0.000e+00
    -0.100      0.000e+00     0.000e-08     0.000e+00
     0.000      0.000e+00     0.000e+00     0.000e+00
|
|==============================================================================



******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

Based on a conversation with Arpad Muranyi on 11/14/97.  Modified per a
discussion with Bob Ross, Chris Reid and Arpad Muranyi on March 11, 1998.

******************************************************************************



From owner-ibis  Fri Apr  3 11:36:56 1998
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From: John Nemec <JohnN@calmicro.com>
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I am looking for a consultant who could generate an IBIS model of a
Schottky diode network for use in clamping bus over and undershoots.
We have an HSPICE model and characterization data.

John Nemec
Director of Applications
California Micro Devices
 
From owner-ibis  Tue Apr  7 12:15:40 1998
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 DATE: 4/7/98

 SUBJECT: 4/3/98 EIA IBIS Open Forum Minutes
     
 VOTING MEMBERS AND 1998 PARTICIPANTS LIST:
 AMP                            (Martin Freedman) 
 Applied Simulation Technology  Norio Matsui, Raj Raghuram*
 Cadence Design (& UniCAD)      C. Kumar, Don Telian, Patrick Riffault, 
				Craig Lewis, Greg Fitzgerald, Paul Galloway,
				Patrick Dos Santos, Catherine Weiss, 
				Alain Tribaudot, Geoffrey Ellis 
 Cypress                        (Bruce Wenniger)
 Digital Equipment Corp.        Jeff Chu*, Greg Edlund, Bob Haller
 Hewlett Packard (EEsof, etc.)  Karl Kachigan, Henry Wu, Paul Gregory
 High Design Technology         Razvan Ene
 HyperLynx                      Kellee Crisafulli, Matthew Flora*
 Incases                        Olaf Rethmeier*, Scott Jacobson,
				Werner Rissiek
 Intel Corporation              Stephen Peters*, Arpad Muranyi*, Frank Kern,
				Will Hobbs, Prakash Radhakrishnan
   Columbia, SC (formerly NCR)  Dave Moxley
 Mentor Graphics (Zeelan,       Bob Ross*, George Opsahl, Mark Noneman,
   Interconnectix, etc.)        Tom Dagostino, Karine Loudet, Jean Oudinot,
				Manuel De Almeida, Stephane Rousseau, 
				Nevin Orhanovic*
 Mitsubishi                     Hoang Nguyen, Tam Cao
 Motorola                       (Ron Werner)
 National Semiconductor         Syed Huq*, Cheng-Yang Kao, John Goldie,
				Ikchang Song
 North East Systems Associates  Edward Sayre, Kathy Breda
   (NESA)
 NEC                            (Hiroshi Matsumoto)
 Quantic EMC                    (Mike Ventham)
 Texas Instruments              Thomas Fisher, Harvey Stiegler,
				Vincent Chang, Jean-Claude Perrin*,
				Peter Forstner
 Thomson-CSF                    Jean-Marc Claveau, Laurent Duzaic,
				Saverio Lerose, Benoit Meyniel,
				Jean Lefebvre  
 Viewlogic                      Jon Powell, Chris Rokusek*, Guy de Burgh, 
				Gary Mandel
 VeriBest                       Ian Dodd, David Weins, Ian Gabbitas
 VLSI Technology                D.C. Sessions*
 Zuken-Redac                    (John Berrie) 

 OTHER PARTICIPANTS IN 1998:
 Actel                          Eric Tardif, Emmonvelle Gaudin 
 Aerospatiale                   Lionel Dreux, Claude Huet
 Alcatel (Bell, Espace, etc.)   John Fitzpatrick, W. Temmerman, 
				Laure Bessettes, Jean-Claude Pourtau,
				Daniel Peron
 ALS Design                     Yves Mouquet
 Ansoft                         Eric Bogatin
 Apple                          Fred Floresca, Danny Itani
 Apteq Design Systems           Dan FitzPatrick 
 Avanti                         Nik Bannov
 CERN                           Olivier Clere, Jean-Michel Sainson, 
				Rudi Zurbroken
 Compaq                         Shariq Rahma
 EIA                            Patti Rusher*
 EMC                            Fawn Engelmann
 ENST, Paris                    Jean-Jacques Charlot
 European CAD Standardization   Adam Morawiec
   Intitiative (ECSI)
 Fairchild Semiconductor        Peter LaFlamme
 H.A.S Electronics              Haruny Said
 Intracon Design Ltd.           Derek Laidlaw
 Philips Semiconductor          Todd Andersen
 Scottish Electronics           Robert Easson
   Manufacturing Center (SEMC)
 Seagate                        Vanessa Howard
 SGS-Thomson                    Philippe Lefevre
 Siemens                        Gerald Bannert, Bernhard Unger, 
				Christian Marot, Miguel Hernandez,
				Gil Russell
 Symmetry                       Andy Hughes
 Tektronix                      Nassrin Ghahyasi
 Ultratest International        Chris O'Connor
 Xilinx                         Susan Wu

 In the list above, attendees at the meeting are indicated by *.  Principal
 members or other active members who have not attended are in parentheses.
 Participants who no longer are in the organization are in square brackets.

 Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
 follows:
   
   Date               Bridge Number     Reservation #    Passcode
   April 24, 1998      (916) 356-9200    5-32911          6784438

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each Open Forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.

 -------------------------------- MINUTES -------------------------------------

 INTRODUCTIONS AND MEETING QUORUM
 No new participants


 MEMBERSHIP UPDATE AND TREASURER'S REPORT
 Patti Rusher does not have the report, but she does not know of any new
 members.


 REVIEW OF MINUTES AND AR'S
 The AR's will be discussed at the meeting.  No corrections were noted on
 the previous two sets of meeting Minutes.


 MISCELLANY/ANNOUNCEMENTS
 Bob Ross indicated that he still plans the Majordomo conversion when he has
 time.

 Bob stated that Syed Huq has requested roster updates.  Arpad Muranyi asked
 if they can still be given, and Bob said that they can be provided at any
 time.


 PRESS AND WEB PAGE UPDATES
 Bob Ross noted that the article "Free Board Tools Spun for Web" in the
 Electronic Engineering Times, March 30, 1998, pg. 92 discusses the free
 IBIS model development utility from Cadence.

 Bob also reported that two side-bar articles in Electronic Engineering Times,
 "Crosstalk-analysis Tools Roll at PCB Confab" and "Designers Clamor for
 Better IBIS Models" are on pages 73 and 74 in the March 23, 1998 issue both
 mention IBIS.

 Finally, Bob reported that Arpad Muranyi is teaching a session on "Signal
 Integrity in High-Speed CMOS Circuits" and is including IBIS Model discussion
 in a tutorial short course: Circuit Simulation and Signal Integrity in
 Micro electronic Circuits and Systems from the University of Arizona in
 Scottsdale, Arizona, May 4-6, 1998.


 NEW MODELS AVAILABLE, LIBRARY UPDATE
 Bob Ross noted that Cadence has announced its free s2ibis development utility
 and viewer and it is downloadable the location below (click on free
 software):

   http://www.cadence.com/software/pcb_info.html

 It is a very large .zip file.  The utility is configured with a windows 
 interface to run on Solaris OS machines.

 Bob noted that TI clock driver IBIS models now exist at:

   http://www.ti.com/sc/docs/msp/cdc/app_supp.htm

 Bob reported that the Motorola URL mentioned by Matthew Flora at the last
 meeting has entries for several technologies.  Currently IBIS models exist 
 for the LCX technology.  Matthew had submitted the link later as: 

   http://mot2.indirect.com/models/bin/logic_ic.html

 The IBIS models that should be stored in Word Format (.doc) which then can
 be converted to a text format as a .ibs file.  If you try to store the files
 directly as text files, they will appear to be corrupted with binary 
 characters.

 Bob noted that Jon Powell restored the had IBIS models page link from the
 IBIS home page which had inadvertently been deleted by the web page provider.


 OPENS FOR NEW ISSUES
 Syed Huq on compressing the ibischk executables
   (Discussed in the ibischk2.115 discussion)
 Bob Ross on the Design Automation Conference Summit meeting.
   (Not directly discussed)

 
 INTERNATIONAL/EXTERNAL PROGRESS
 - IEC 62014-1 (IBIS Version 2.1) - Patti Rusher still has not heard on the
   status.  It may not be resolved until the next IEC meeting in September.

 - EIAJ III (I/O Interface Model for ICs) - Raj Raghuram reported that he
   has a preliminary copy of the Version 1.1 English translation.  Bob Ross
   reported that Hideki Fukuda still expects to create a web site soon which
   will contain this document and other information for downloading.

 - IEC 93/67/NP IBIS and EMC Simulation - Jean-Claude Perrin, Chair of the
   task force gave this report.  Jean-Claude first noted that the official
   minutes of the February 27, 1998 meeting had pages 2 and 3 interchanged.
   A meeting was held on March 30, 1998.  Its purpose was to refine the
   proposal to be submitted to the next IEC meeting in September, 1998.  The
   proposal still contains an internal equivalent model square pulse generator
   representing a clock along with some internal coupling impedances to the
   pins/power supplies of the device.  The plan is to follow the IBIS model
   conventions but be formatted in a separate file such with a .emc extension.
   However, the extensions would be compatible with the corresponding .ibs
   Component in the IBIS file.  Jean-Claude briefly covered additional details
   such as capacitance on supplies, through currents, and variable coupling
   impedances.

   Jean-Claude asked whether the IBIS format supports the short circuit current
   between power rails that may exist when output devices change state.  Bob
   Ross reported that the IBIS format only supports this as a consequence of
   whatever algorithm is employed during transition.  BIRD42.3, still under
   consideration, actually can be used to format such currents.  So EMC 
   extensions could also be a consideration for supporting BIRD42.3 within
   the .ibs or possibly the .emc format.

   Jean-Claude indicated that the task force is preparing a revision for
   submission and will be sending a copy to Bob.  Bob questioned whether
   this copy could be submitted to the IBIS reflector for general review and
   comments, and Jean-Claude affirmed that this was permitted.  (Note: so
   Bob will plan to make the document available for review whenever it is
   received - either by email or by uploading it in an area where interested
   people can download it for review.  Jean-Claude will welcome comments.)

 - JC-16B - Bob Ross started the discussion by indicating that a joint IBIS
   Summit meeting in December, 1998 with the JEDEC JC-16B sub-committee had
   been proposed at the March 13, 1998 IBIS Open Forum.  This meeting would be
   held in place of the DesignCon IBIS Summit meeting planned for January,
   1999.  Bob indicated that he supported holding a joint meeting.  However,
   Bob also felt the DesignCon IBIS Summit Meeting was valuable and should
   not be dropped.  D.C. Sessions commented that he would have liked to see
   more "chalk-board" issue resolution at the IBIS Summit meeting rather than
   just presentations.  Bob responded that this has occurred in the past.  The
   format of the IBIS Summit meetings are not fixed.  Some past IBIS Summit
   meetings have been held with topics devoted to issues and have also 
   involved some small sub-group meetings beforehand to develop and present
   some agreed upon proposals.  

   Bob questioned D.C. on what he had in mind for the joint meeting - its
   purpose and how it would be structured.  For example, do the IBIS folks
   participate in the JC-16B meeting, and the JC-16B folks participate in the
   IBIS Summit as observers?  D.C. mentioned that what he had in mind was to
   co-locate a meeting where it was convenient for some cross-fertilization 
   particularly between the device developer members of the JC-16B committee
   and the EDA tool developer members of the IBIS Open Forum.  Bob and others
   felt that this was a good reason to hold such a meeting.  Bob also stated
   that the meeting did not have to be structured on just presentations.  The
   IBIS Summit Meeting might focus on a few application topics of mutual
   interest.  One such topic might be IBIS models for SSTL (Series Stub
   Terminated Logic) - a topic originating from  JC-16B.  (Other topics could
   included IBIS models for other technologies considered by JC-16B.)

   Bob asked for the dates, and Patti Rusher indicated that she has already
   booked hotel and conference space in San Diego for the December 7-9, 1998
   time frame for JEDEC.  The JC-16B meeting typically covers one-half day
   and a JC-42 meeting on Memories also typically covers one-half day and
   is attended by many JC-16B members.  These occur typically on Tuesday, so
   the plan is to add a room reservation for the an IBIS Summit Meeting the
   following day.  Patti indicated that She will reserve Wednesday, December
   9, 1998.  (Note after the meeting - the dates were not clear, but the
   intent is to hold the IBIS Summit meeting the day after the JC-16B and
   JC-42 meetings.)

   Bob asked who was going to pay for this.  Patti indicated that this could
   come out of the EIA IBIS funds.  Bob also indicated that others might want
   to serve as sponsor or co-sponsor hosts.  In particular, Viewlogic might
   be interested since the meeting is being held nearby.  Chris Rokusek will
   check if Viewlogic is interested.


 IBIS LOGO CHANGE
 Bob Ross introduced the topic by noting that the EIA (Electronic Industries
 Association) has now changed its historical lightning-bold circular logo
 to a new rectangular logo, and EIA now stands for Electronic Industries
 Alliance.  Patti Rusher indicated that this change was due to an expanded
 scope of EIA incorporating more organizations under the EIA umbrella.  As
 indicated from the revised Web page - still under revision, EIA now consists
 of the following organizations: 
   
    Consumer Electronics Manufactures Association (CEMA),
    Electronic Components, Assemblies Equipment & Supplies Association (ECA),
    Telecommunications Industry Association (TIA),
    Electronic Information Group (EIG) - where Patti is a director and under
      which the IBIS Open Forum and other organizations are positioned, 
    Government Electronics & Information Technology Association (GEIA),
    JEDEC Solid State Products Technology Division, and
    Electronic Industries Foundation (EIF).

 Since the old EIA logo is embedded within the IBIS Spoken Here!! logo (or
 placard), the IBIS logo is now retired.  Patti wants to work with a graphics
 artist to develop quickly a new IBIS logo in time for the Design Automation
 Conference.  

 Bob and others indicated that they liked the original logo with the scarlet
 IBIS birds, the IBIS Spoken Here!! and the EIA logo within.  However the
 square logo does not fit as well.  So the committee is open to considering
 changes.  A general discussion occurred.  Bob questioned whether the EIA
 logo included a black outline, and Patti indicated no.  Patti indicated that
 a few other organization are also revising their logos.

 Stephen Peters expressed interest in reviewing logo designs.  So Bob formed
 a committee consisting of the IBIS officers (Stephen Peters as the main
 contact, and Syed Huq, Jon Powell, and Bob) to review logo ideas.)  Patti
 would go ahead and get ideas from the graphics artist.  Bob also stated that
 anyone else interested is welcome to join or submit logo ideas.  Bob noted
 that he will also ask people who are using the old logo to start phasing them
 out.

  
 IBIS EAST USERS GROUP ACTIVITIES
 Bob reported that Greg Edlund issued the minutes on the ibis-users reflector
 for the Accuracy sub-group meeting held on March 26, 1998.  The next Accuracy
 sub-group meeting is scheduled on Thursday, April 30, 2998.

 Bob also expects the minutes of the March 19, 1998 IBIS (East) Users Group to
 be issued soon. 

 
 EDITING COMMITTEE 
 Bob Ross indicated that he upload an UNOFFICIAL IBIS ver3_1b.ibs document on
 eda.org under /pub/ibis/wip.  It contained only minor editorial revisions
 and the correction to [End Board Description] nomenclature.

 Later under the BIRD48 discussion, Chris Rokusek thought it would be helpful
 to have a tree diagram to show the context of the IBIS keywords and 
 subparameters.  Bob indicated that one already existed under the wip 
 directory.  This had been originally contributed by Atsushi Ogawa of NEC
 Corporation, who is serving as Vice-Chair of the EIAJ III sub-group.  Bob
 had recently updated the tree diagram to put [Model Selector] at the top 
 level along with [Component] and [Model] within a file in response to a
 comment from Atul Agarwal, who is implementing the ibischk3 parser.  So,
 tree3_0a.txt is now current.

 The BNF AR remains.

 AR - Bob Ross generate and post a BNF for IBIS Version 3.0 (an IBIS Version
 3.0 ratification AR).


 BIRD44 - INTERPRETATION OF MIN/MAX/WEAK/STRONG DATA
 Bob Ross indicated no progress.

 AR - Andy Ingraham to issue BIRD44.1 with the changes and extensions noted
 in the March 13, 1998 IBIS Open Forum meeting minutes.


 IBISCHK2+ (VER 2.115) PROGRESS
 Syed Huq indicated that he had problems downloading the ibischk2+ executables
 using Netscape since Netscape would try to execute rather than save the
 executables.  (This is not a problem using the anonymous FTP access.)  Syed
 proposed that the executables be compressed.  D.C. Sessions provided two
 Netscape workarounds: (1) click Shift, and left key on mouse before doing
 the save, and (2) change the Options - General Preference - Helpers to take 
 out any .exe helper application.

 Bob Ross and others indicated that regardless of these solutions, it probably
 was more efficient to put just compressed files that were intended for 
 downloading - .Z or .gz for Unix, and .zip for DOS Windows applications.
 This would not be difficult for the existing ibischk2+ executables.  So Bob
 will plan to do this.

 As separate item, Bob asked Matthew Flora and Chris Rokusek to continue
 maintaining the ibischk2+ source code.  In particular, keep putting in
 the changes associated with the approved BUGs that are being discovered
 and resolved in the ibischk3 project that relate to ibischk2_.  Matthew and
 Chris agreed to continue doing this in preparation for a future ibischk2+
 Version 2.1.16 release.


 BUG26 - Parser Crashes when Calling [Package Model]
 Bob Ross reported that Atul Agarwal had issued BUG26 against ibischk2+ while
 developing ibischk3, and Atul also provide the simple fix.

 Bob classified this as Severe, High, Open, and intends that this fix be
 rolled into ibischk2.1.16.


 BUG25 - Keyword as First Word in [Notes] Causes Error
 Bob Ross introduced BUG25 which was submitted by Arpad Muranyi.  A discussion
 followed as to whether this was really an error that could be fixed by
 documenting a limitation, or whether the ibischk2+ (and ibischk3) parser
 needed to be changed.  Arpad Muranyi suggested a work around of putting
 quotes around keywords that appear as the first word in a line under the 
 [Notes] keyword.  Bob indicated that the problem applies to any keyword 
 such as [Copyright] which accepts multiple lines of text information.  D.C.
 Sessions favored documenting this as a BUG and considering a fix.  While
 BUG25 could be fixed, Bob noted that the error detection itself was a source
 of ambiguity since a keyword not properly aligned to column 1 after the
 [Notes] text would then be "correctly" included within the notes text.  Only
 after subsequent keyword checking would an error of a missing required
 keyword be detected.  

 Bob classified BUG25 as ANNOYING, LOW, OPEN, and will investigate with Atul
 Agarwal on a low priority basis a possible fix.  However, the alternative
 is still open - provide a documented limitation on using bracketed keywords
 as the first word in text block lines.


 VERSION 3.1 PARSER DEVELOPMENT
 Atul Agarwal delivered Beta Versions 3.0.1 of the ibischk3 and ebdchk3
 parsers and Matthew Flora distributed on March 30, 1998 the source code to
 the twelve companies supporting the development.  Some additional test cases
 and test case results along with Windows DOS executables are included.  
 Stephen Peters will investigate if any .ebd test cases exist.

 Everyone is welcome to try the parsers and to report back on any problems.
 Bob Ross also needs to check on the status of the invoices that have been
 issued.


 COOKBOOK
 Stephen Peters reports that there is progress on the Cookbook project.  As 
 previously reported, individuals from the IBIS East Users group are writing
 the testing and validation section.


 IBIS MODEL REVIEW COMMITTEE DISCUSSION
 Bob Ross asked Matthew Flora whether anyone has approached him regarding
 reviewing IBIS models.  Matthew indicated no.  The model review committee
 has been published in previous minutes.  Bob will now just list Matthews
 address as the contact for IBIS models review:

   Matthew Flora, HyperLynx                   mbflora@hyperlynx.com

 D.C. Sessions is still waiting for Bob to provide an FTP site to upload 
 VLSI IBIS models for review.  Per VLSI policy, individuals who are want to
 review VLSI IBIS models must contact D.C. directly with a letterhead letter
 stating the request.
 

 S2IBIS2
 Matthew Flora reported that he had a question concerning the recently 
 released s2ibis2 for NT.  Matthew was given the source code to test
 the NT implementation.  Bob Ross suggested Matthew work directly with
 SiQual concerning how it can be released.  One issue is that the examples
 exist in a different file and are not included.


 S2IBIS2 BUG1
 Bob Ross reported that BUG1 was issued by Bernhard Unger dealing with the 
 problem that the HSPICE examples do not work.  Bob indicated that this was
 a known problem and was actually the subject of IBIS reflector discussions
 a while ago.  Suggestions regarding HSPICE convergence and adding some
 parasitic resistance to the clamping structures were provided.

 Bob classified BUG1 as ANNOYING, LOW, OPEN.  The s2iibs2 Version 1.1 seems
 to work with real IBIS models.  However, anyone who is interested in
 providing replacement HSPICE examples is welcome to contribute them.  The
 committee itself is too involved in other activities to develop new examples
 at this time.

 
 BIRD47 - REMOVE PIN NAME AS A SUBPARAMETER OF THE [Pin List] KEYWORD.
 Bob Ross introduced BIRD47 by stating that it removed the technical
 inconsistency associated with the pin_name subparameter defined under the
 [Pin List] keyword in the Electrical Board Description section.  BIRD47
 removes the pin_name subparameter and also moves the signal_name subparameter
 to the keyword line in a manner consistent with other pin-related keywords.
 The sense of the committee at the March 13, 1998 meeting was to approve
 BIRD47.  The ebdchk3 parser should already use the BIRD47 syntax.  Bob called
 for a vote.

 BIRD47 was approved unanimously with one abstention based on lack of 
 knowledge.


 BIRD42.3 - MODELING CURRENT WAVEFORMS
 Bob Ross indicated that we need to move on BIRD42.3.  The original BIRD42
 was introduced prior to the IBIS Version 3.0 ratification meeting in June,
 1997.  There were issues associated with BIRD42 and IBIS Version 3.0 was
 issued with the understanding that BIRD42 could be considered further and
 included in IBIS Version 3.1.  While there has been little activity on 
 BIRD42.3, it was discussed during both the DesignCon IBIS Summit on
 January 26, 1998 and the European IBIS Summit on February 26, 1998.  Also,
 as previously mentioned, BIRD42.3 may relate to some EMC concerns.  BIRD42.3
 will be scheduled for a discussion at a later meeting.

 
 BIRD46.1 - RELAXATION OF SOME IBIS FILE NAME RESTRICTIONS
 Since BIRD46.1 has not been issued, Bob Ross deferred the discussion. 
 
 AR - Matthew Flora issue BIRD46.1 to include references to the .pkg file
 and .ebd file and to change the limitation from 64 total characters to
 a <filename> limit of 20 characters and delete the references to allowing
 the period "." character.

 
 BIRD48 - ADD MODEL
 Bob Ross presented the background concerning BIRD48, BIRD49, and BIRD50.  At
 the IBIS Version 3.0 ratification meeting in June, 1997, the committee left
 the door open for adding to IBIS Version 3.1 a dynamic clamp feature.  BIRD45
 and BIRD45.1 proposed dynamic clamps.  In response to a comment, we wanted to
 investigate further whether the [Driver Schedule] keyword could be used for
 some added functionality.

 On March 11, 1998, Bob met with Arpad Muranyi and Chris Reid to do this
 investigation based on the intended functionality.  After looking at some
 of the aspects, the group moved toward a different, more general approach.
 This approach allows future extensions and also allows reusing some of the
 existing IBIS keywords in a parent-child relationship that is consistent
 actual EDA tool implementation methodologies.  Bob then took the action item
 of producing the BIRDs that were needed for this functionality.  
 
 Based on some subsequent considerations, Bob just introduced BIRD48 for [Add 
 Model] to allow calling other [Model]s only if they are of specific 
 Model_types.  The two Model_types are Dynamic_clamp and Bus_hold described 
 in BIRD49 and BIRD50, respectively.  Furthermore, Bob opted to introduce the 
 [Add Model Spec] keyword to describe subparameters associated with these 
 added models.  Normally the subparameters information is based on internal
 knowledge that is not available in the data sheets.  So Bob rejected using
 the existing [Model Spec] keyword for this purpose.  Under [Add Model Spec],
 subparameters V_trigger_r and V_trigger_f describing the rising and falling
 edge trigger voltages are introduced.  The format allows for independent
 typo-min-max column entries.

 Bob indicated that the preparation of BIRD48, BIRD49, and BIRD50 evolved
 while being written.  He did introduce these BIRDs on Thursday, April
 2, 1998, but expected to do more work on them.  The notation is completely
 open at this time.  Also, there is still some unresolved functionality that
 needs to be considered.

 
 BIRD49 - ADD MODEL DYNAMIC CLAMPS
 Bob Ross introduced BIRD49 to replace BIRD45.1.  Along with the [Add Model]
 call, Dynamic_clamp Model_type, the [Add Model Spec] trigger voltages,
 BIRD49 introduces the [POWER Pulse Table] and [GND Pulse Table] to describe
 the dynamic clamp shifting as a function of time.  Unlike the BIRD45.1 
 approach, BIRD49 reuses the [GND Clamp] and [POWER Clamp] keywords.  BIRD49
 covers the same functionality as BIRD45.1 plus uses the typ-min-max
 trigger voltages that had been discussed as an improvement to BIRD45.1.
 A complete example is provided.


 BIRD50 - ADD MODEL BUS HOLD
 Bob Ross introduced BIRD50.  It introduced only the Model_type Bus_hold.
 Output keywords for [Pullup], [Pulldown], [Ramp], and even the [Rising
 Waveform] and [Falling Waveform] tables could be used.  While positioned
 as contributing to bus hold modeling, the real reason was to deal with 
 some new latching mechanism architectures that are now being implemented.
 An example is provided showing the Bus hold implementation.

 Chris Rokusek commented that the [Add Model Spec] could be moved to the
 same location as the [Add Model] keyword since it is associated with
 information at the parent model level.  Bob responded that this might be a
 good idea, but it would then require independent trigger voltages for each
 application.  The trigger voltages were really a function of the added
 model features.

 
 BIRD45.1 - DYNAMIC CLAMPS
 Because BIRD48 and BIRD49 are intended to replace BIRD45.1, Bob Ross will
 schedule a formal vote on the rejection of BIRD45.1 at the next meeting.

 
 TECHNICAL ISSUES ON THE IBIS REFLECTOR
 In the few minutes that remained, Bob Ross indicated that there has been good
 reflector discussion, both on the Signal Integrity reflector and the IBIS
 reflectors.  Bob also has three new issues he quickly summarized:

 (1)  We may need to add the 3-state_ECL Model_type.  There exists several
      such devices, and Bob cited the National Semiconductor 100316, a
      low power quad differential line driver with cut-off, as one ECL
      3-state example.

 (2)  We may need to consider extending the [Rising Waveform] and [Falling
      Waveform] fixture loads to include a differential resistor.  Some
      technologies appear to require the physical or Spice differential 
      connection for proper extraction of IBIS information.

 (3)  Based on an e-mail from Jean-Christophe Pautrat (Hewlett Packard, 
      France) on the IBIS reflector, we may need to consider extending the 
      timing test load information and Vmeas into the typ-min-max format 
      under the [Model Spec] keyword.  For example, the APG max timings are 
      specified with Cref = 10 pF and min timings are specified with Cref =
      0 pf.  Bob felt that we currently could use only one of the Cref values,
      and extract a delta time value to modify the times for the other Cref
      setting.  However, all data values would need to be adjusted - a 
      potentially tedious process.


 NEXT MEETING:
 The next teleconference meeting is on Friday, April 24, 1998, 8:00 A.M. to 
 9:55 A.M.  BIRD45.1 and BIRD46.1 are scheduled for votes.
 ==============================================================================
				       NOTES
 
 IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
	     bob_ross@mentorg.com
	     Modeling Engineer, Interconnectix BU of Mentor Graphics
	     8005 S.W. Boeckman Road, Wilsonville, OR 97070

 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785
	     huq@rockie.nsc.com
	     Staff Applications Engineer, National Semiconductor, M/S A-2595
	     2900 Semiconductor Drive, Santa Clara, CA 95052
 
 SECRETARY:  Stephen Peters (503) 264-4108, Fax: (503) 264-4515
	     sjpeters@ichips.intel.com
	     Senior Hardware Engineer, Intel Corporation
	     M/S JF1-56
	     2111 NE 25th Ave. 
	     Hillsboro, Oregon 97124-5961

 LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
	     jonp@qdt.com
	     Senior Scientist, Viewlogic (formerly Quad Design)
	     1385 Del Norte Rd., Camarillo, CA 93010
  
 This meeting was conducted in accordance with the EIA Legal Guides and EIA
 Manual of Organization and Procedure.
 
 The following e-mail addresses are used:

   ibis-request@eda.org
       To join, change, or drop from either the IBIS Open Forum Reflector
       (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
       or both.  State your request.

   ibis-info@eda.org
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   ibis@eda.org
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.  Job posting information is not permitted.

   ibis-users@eda.org
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.  Job posting information is not permitted.

   ibischk-bug@eda.org
       To report ibischk2 parser bugs.  The Bug Report Form Resides on
       eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

       To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
       which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
       /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
       respectively.

 Information on IBIS technical contents, IBIS participants, and actual
 IBIS models are available on the IBIS Home page found by selecting the
 Electronic Information Group under:

   http://www.eia.org

 Check the pub/ibis directory on eda.org for more information on previous 
 discussions and results.  You can get on via FTP anonymous.
 
 "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for 
 use at trade shows.
 ==============================================================================


From owner-ibis  Wed Apr  8 18:14:51 1998
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From: John Lin - TAO <LinJohn@digital.com>
To: "'ibis'" <ibis@eda.org>
Cc: Dc Liu <Dc.Liu@digital.com>, Hw Cheng <chenghw@digital.com>,
        Jj Leu
	 <Jj.Leu@digital.com>, Steve Ting <Steve.Ting@digital.com>
Subject: How to do correlation with two extra Rising/Falling waveforms?
Date: Thu, 9 Apr 1998 09:08:01 +0800
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Hi IBIS fans,

In the IBIS Forum's I/O BUFFER MODELING COOKBOOK, page 12, there is a 
table - "Recommended Load Circuits and Waveforms for V/T Data 
Extraction."

In the table, there are 4 waveforms to extract V/T data for [Rising 
Waveform] and [Falling Waveform] for a standard push/pull CMOS type 
buffer.

I/O buffer+ R-fixture+V_fixture.

For falling edge, two waveforms are obtained based on
(1)	V_fixture=0, and
(2)	V_fixture=VCC.

For rising edge, two waveforms are gathered based on
(3)	V_fixture=0, and
(4)	V_fixture=VCC.


The cookbook uses (2) and (3) to extract data in [Ramp] and says (1) 
and (4) are for correlation.

How is the correlation done?
 What information can be extracted from (1) and (4)?

Inside the Quad Design XTK manual, the (1) and (4) can be used to 
generate Ground
Bounce Model.  How?

Any inputs from you are appreciated.


Thanks,

JOHNLIN
CAE Engineer of EDA Department
Digital Equipment Corp. Taiwan Branch
Email: Linjohn@mail.dec.com
TEL: 1-886-3-3900000 ext. 2152


From owner-ibis  Fri Apr 17 13:11:26 1998
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From: bobr@wv.mentorg.com (Bob Ross)
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Date: Fri, 17 Apr 98 13:08:01 PDT
Message-Id: <9804172008.AA19962@bob>
To: ibis@eda.org
Subject: IBIS AGENDA 4/24/98

                       IBIS Open Forum Meeting Agenda 
                                for 4/24/98

                  Bridge Number    Reservation #   Passcode
                  (916) 356-9200   5-32911         6784438


 All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
 meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
 Reservation Number and Passcode.
 
 8:00 Check-In, Intros, Announcements                         Ross

      - Intros of New IBIS Participants, Meeting Quorum       Ross
      - Membership Update and Treasurers Report               Rusher
      - Review of Previous Meeting's Minutes (and ARs)        Peters
      - Miscellany/Announcements                              All
      - Press & Web Page Updates                              Huq, All
      - New Models Available, Library Update                  Powell, All
      - Opens for New Issues                                  All

 8:25 Administrative and Project Discussions

      International/External Progress                         Rusher/Ross
      - IEC 62014-1 (IBIS Version 2.1)
      - EIAJ III (I/O Interface Model for ICs)
      - 93/67/NP IBIS and EMC Simulation                      Perrin
      - JC-16B                                                Sessions

      IBIS Logo Change                                        Rusher/Ross

      IBIS (East) Users Group Meetings                        Edlund

      Editing Committee                                       Ross/Peters
      BIRD44 - Interpretation of Min/Max/Weak/Strong Data     Ross

      IBISCHK2+ (Ver 2.115) PROGRESS                          Flora/Rokusek

      BUG27 - Line with 80 Spaces Cause Crash                 Flora

      Version 3.1 Parser Development                          Ross/Peters
      - Billing
      - Tests & Samples

      Cookbook Status                                         Peters

      IBIS Model Review Committee                             Flora

      New Administrative Issues                               All

 9:15 Technical Discussion

      BIRD42.3 - Modeling Current Waveforms                   Kumar/Ross
          
      BIRD48 - Add Model                            Orhanovic/Muranyi/Ross
 
      BIRD49 - Add Model Dynamic Clamps             Orhanovic/Muranyi/Ross

      BIRD50 - Add Model Bus Hold                   Orhanovic/Muranyi/Ross

      BIRD45.1 - Dynamic Clamps                     Orhanovic/Muranyi/Ross
               (Consider Replacement with BIRD48, BIRD49, BIRD50)
               Vote

      BIRD46.1 - Relaxation of Some IBIS Model File Name      Flora
                 Restrictions

      Some Technical Issues on IBIS Reflector                 Ross

      New Technical Issues                                    All

 9:50 Wrap Up and Next Meetings Plans                         Ross

 9:55 Sign Off
 







From owner-ibis  Thu Apr 23 10:19:04 1998
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From: bobr@wv.mentorg.com (Bob Ross)
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Date: Thu, 23 Apr 98 10:15:10 PDT
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To: ibis@eda.org
Subject: Forwarded: Fwd: ibis logo

To All:

Five new IBIS LOGO designs are available for viewing
in preparation for the IBIS meeting discussion on
Friday, April 24, 1998.  Comments are welcome.

Bob Ross
Interconnectix/Mentor Graphics


Date: Thu, 23 Apr 1998 12:02:24 -0500
From: Patti Rusher <Pattir@gw.eia.org>
To: bob_ross
Subject: Fwd: ibis logo


Date: Thu, 23 Apr 1998 11:32:34 -0500
From: Deanna Sikora <Deannas@gw.eia.org>
To: Pattir@gw.eia.org
Subject: ibis logo

Patti - 

Per your request, the IBIS logos are online for the members to view
and vote on. The URL is www.eia.org/eig/ibis/logo.htm. There are five
logos to choose from. Hopefully one will work.

D. Sikora

From owner-ibis  Thu Apr 23 11:25:38 1998
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From: "Hobbs, Will" <will.hobbs@intel.com>
To: "ibis@eda.org " <ibis@eda.org>,
        "bobr@wv.mentorg.com "
	 <bobr@wv.mentorg.com>
Subject: RE: Forwarded: Fwd: ibis logo
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Bob,

I suspect voting on the open forum reflector will clog up the mail
boxes, so do 
you have a proposed process for voting? Or would you like the comments
to be 
public?

Just to clog up the reflector a bit, here are my comments: I vote for
#3, as 
both IBIS and EIA are clear, and it is well balanced and aesthetically
pleasing.

Will

 To All:

Five new IBIS LOGO designs are available for viewing 
in preparation for the IBIS meeting discussion on 
Friday, April 24, 1998.  Comments are welcome.

Bob Ross
Interconnectix/Mentor Graphics


Date: Thu, 23 Apr 1998 12:02:24 -0500 
From: Patti Rusher <Pattir@gw.eia.org> 
To: bob_ross
Subject: Fwd: ibis logo


Date: Thu, 23 Apr 1998 11:32:34 -0500 
From: Deanna Sikora <Deannas@gw.eia.org> 
To: Pattir@gw.eia.org
Subject: ibis logo

Patti -

Per your request, the IBIS logos are online for the members to view 
and vote on. The URL is www.eia.org/eig/ibis/logo.htm. There are five 
logos to choose from. Hopefully one will work.

D. Sikora
From owner-ibis  Thu Apr 23 12:49:27 1998
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Date: Thu, 23 Apr 1998 12:46:30 -0700
To: ibis@eda.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: ibis logo
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Hi Bob, all,

Just to clog up the reflector a bit more: 

I vote for #3 IF EIA and IBIS switch places.
  The EIA is far to dominant and IBIS is almost lost.

My number 2 pick is #5.





-------------------------------------------------------------------------
Have a great day...
Kellee Crisafulli at HyperLynx
kellee@hyperlynx.com	http://www.hyperlynx.com
-------------------------------------------------------------------------
From owner-ibis  Thu Apr 23 13:49:57 1998
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Hello Bob and all,

My picks for IBIS logo is -->

  #1  (First choice)
  #5  (Second choice)
From owner-ibis  Thu Apr 23 14:26:04 1998
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From: rsreddy <rsreddy@micron.com>
To: "'bobr@wv.mentorg.com'" <bobr@wv.mentorg.com>, ibis@eda.org
Subject: RE: Forwarded: Fwd: ibis logo
Date: Thu, 23 Apr 1998 15:22:51 -0600
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Hi,
   I like logo #3 and logo# 5 also looks good. Either one is fine with me.

Rathna Reddy
Sr design/simulation specialist
One Chisholm Trail
Suite 3200 Round Rock, Texas 78681
 Ph:(512)248-5107
Fax (512)248-5190
Email:rsreddy@micron.com


	-----Original Message-----
	From:	bobr@wv.mentorg.com [SMTP:bobr@wv.mentorg.com]
	Sent:	Thursday, April 23, 1998 12:15 PM
	To:	ibis@eda.org
	Subject:	Forwarded: Fwd: ibis logo

	To All:

	Five new IBIS LOGO designs are available for viewing
	in preparation for the IBIS meeting discussion on
	Friday, April 24, 1998.  Comments are welcome.

	Bob Ross
	Interconnectix/Mentor Graphics


	Date: Thu, 23 Apr 1998 12:02:24 -0500
	From: Patti Rusher <Pattir@gw.eia.org>
	To: bob_ross
	Subject: Fwd: ibis logo


	Date: Thu, 23 Apr 1998 11:32:34 -0500
	From: Deanna Sikora <Deannas@gw.eia.org>
	To: Pattir@gw.eia.org
	Subject: ibis logo

	Patti - 

	Per your request, the IBIS logos are online for the members to view
	and vote on. The URL is www.eia.org/eig/ibis/logo.htm. There are
five
	logos to choose from. Hopefully one will work.

	D. Sikora
From owner-ibis  Thu Apr 23 23:08:51 1998
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 Hello,

  my first choice is #3 and second choice is #5
 
 JCP
From owner-ibis  Fri Apr 24 04:35:36 1998
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Date: Fri, 24 Apr 1998 12:33:33 +0100
From: Mike Ventham <ventham@quantic-emc.com>
Organization: Quantic EMC Inc
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My vote is for #3 with a larger IBIS text, then #5 without the 
spoken here.


-- 
Regards

Mike
________________________________________________________________
| Mike Ventham - Vice-President Engineering,Quantic EMC Inc    |
From owner-ibis  Fri Apr 24 04:44:17 1998
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Hi, all!

I made a small inquire in HDT and our choice is:
 #3



Razvan Ene                       \|||||||/
Software Manager                 _       _       e-mail:ene@edm-hdt.it
H.D.T. - Italia                   (o)-(o)           Tel: + 39 11 746.104
c.so Trapani 16                  \   O   /          Fax: + 39 11 748.109
10139 Torino - Italy ______oOO____\__0__/_____OOo_____
        __   __                  ______
       / /  / /-       __       / __   )          --
      / /__/ /_  ___ _/ /_     / /  ) /__  ____  __  ___ __ __
     / ___  / // __ `/ __ \   / /  / / _ \/   _)/ // __ `/ '_ \
    / /  / / // /_/ / / / /  / /__/ /  __/_\  \/ // /_/ / / / /
   /_/  /_/\_/\__, /_/ /_/  /______/\___/ \____)_/\__, /_/ /_/
              __/ /                               __/ /
              \__/                                \__/
      ________
     /__  ___/      __                __
       / /__  ,___ / /_  _ __  ____  / / ____   ___ __   __
      / / _ \/ __// __ \/ '_ \/ __ \/ / / __ \/ __ `/ / / /
     / /  __/ (__/ / / / / / / /_/ / /_/ /_/ / /_/ / /_/ /
    /_/\___/\___/_/ /_/_/ /_/\____/\__/\____/\__, /\ _, /
                                             __/ /  _/ /
                                             \__/   \_/


From owner-ibis  Fri Apr 24 23:06:43 1998
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My choice for proposed IBIS logo are


Candidate No 5:  First Choice

Candidate No 1:  Second choice

Thanks

Shripadaraj
From owner-ibis  Mon Apr 27 02:56:22 1998
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From: Amlan Chakrabarti <tatai@india.ti.com>
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Subject: Correlating IBIS models with actual Silicon measurements
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Hi,
 We at Texas Instruments (India) are trying to develop IBIS models for one of our
products .We have a few questions regarding the correlation of IBIS models
(generated through simulation) with actual Silicon measurements -
    
    1.How can we measure the "input die capacitance"in the lab ?
    
    2.How can we measure the output rise/fall times when the chip is available
      in a plastic package ?Unless we open the package only the enable pin of
      an output buffer is available to us(along with the output pin)-but we can't
      access the input of the buffer.
                  Can you send us any information regarding the correlation of IBIS
      models with Silicon ?Any URL's having such information will be very helpful
      for us.
                                                       Thanks and best regards,
                                                        Amlan Chakrabarti.
                                                        Texas Instruments (India) Ltd.
                                                        E-Mail : tatai@india.ti.com
      
From owner-ibis  Mon Apr 27 06:53:24 1998
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From: Greg Edlund <Greg.Edlund@digital.com>
To: "'Amlan Chakrabarti'" <tatai@india.ti.com>
Cc: "'ibis@vhdl.org'" <ibis@vhdl.org>
Subject: RE: Correlating IBIS models with actual Silicon measurements
Date: Mon, 27 Apr 1998 09:41:14 -0400
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Dear Amlan,

These are excellent questions, and I commend TI for pursuing lab
verification of IBIS datasheets (models).  This effort - and it is an
effort - results in increased user confidence in your products.  I wish
I could tell you there is one place to look for this information.  These
two chapters in the IBIS Cookbook are presently under construction, as
you probably already know.  (If you're not familiar with the Cookbook,
you can find it at the IBIS web site, www.eia.org/eig/ibis/ibis.htm.)
In addition, I am serving on an IBIS subcommittee which is writing a
specification for datasheet accuracy; we plan to have ready it for first
review in September 1998.  It is our intention to make the IBIS Accuracy
Specification a document of understanding between the component user and
vendor so that both parties know exactly what constitutes an accurate
IBIS datasheet.

In the meantime, perhaps I can offer some assistance.  (My company buys
a lot of parts from yours, so we have more than an altruistic interest!)

You won't be able to independently measure the IBIS keyword C_comp on a
packaged part.  In general, there are four components to pin
capacitance, working in from the pin:  the package, the die bond pad,
the ESD protection devices, and the FETs associated with the I/O buffer
circuit.  When you measure pin capacitance on the packaged part, you get
all of these lumped together.  (Sometimes they're not really lumped,
like when you have on-chip series termination.)  This means that you can
only verify the sum of C_comp and C_pkg (or C_pin).  Of course, if you
have a package with no die in it, you can isolate C_pkg.

We have been struggling quite a bit with capacitance measurements on a
test board that our subcommittee designed to demonstrate lab
verification of IBIS datasheets.  I am trying to make the measurements
using an HP4275A LCR meter, which employs an autobalancing bridge.
There was some excellent discussion on the SI reflector in the last two
weeks around how to measure pin capacitance.  I could forward you some
of these notes, if you're interested.

IBIS defines the ramp parameters WITHOUT the package, which is feasible
in SPICE but not in the lab.  I believe the intention is to capture the
intrinsic rise and fall times of the driver, which may then be used with
any package circuit by simply changing C_pkg, etc.  However, this
presents some difficulty when correlating hardware against the
datasheet.  If you have the SPICE model available to you, I would
recommend extracting dV/dt_r and dV/dt_f from SPICE waveforms, as
described in IBIS, with and without the package model to see how big an
effect to expect.  You can then take your lab measurements for these
sub-parameters and apply a correction factor.  Finally, when you feel
reasonably confident in your datasheet parameters, use a behavioral
simulator to generate waveforms for the IDENTICAL NETWORK that you used
to measure the waveforms in the lab.  Include probe capacitance and
bandwidth effects in your behavioral simulation.  Measure Zo and Tpd of
your transmission lines and put these values in your behavioral
simulations.

I'm not sure why you're interested in the input of the driver.  IBIS
doesn't directly address I/O buffer delays.

My colleague and I presented a paper on behavioral model accuracy at
DesignCon98 in Santa Clara, CA.  If you'd like a copy, just send me your
address.  Also, keep an eye on the IBIS reflector in the next month or
two.  Our subcommittee will be posting the design of the test board I
mentioned.

Sincerely,
Greg Edlund
----------
Greg Edlund, Principal Engineer
Server Product Development
Digital Equipment Corp.
129 Parker St. PKO3-1/20C
Maynard, MA 01754
(978) 493-4157 voice
(978) 493-0941 FAX
greg.edlund@digital.com

	----------
	From: 	Amlan Chakrabarti[SMTP:tatai@india.ti.com]
	Sent: 	Monday, April 27, 1998 5:52 AM
	To: 	ibis@vhdl.org
	Cc: 	tatai@india.ti.com
	Subject: 	Correlating IBIS models with actual Silicon
measurements

	Hi,
	 We at Texas Instruments (India) are trying to develop IBIS
models for one of our
	products .We have a few questions regarding the correlation of
IBIS models
	(generated through simulation) with actual Silicon measurements
-
	    
	    1.How can we measure the "input die capacitance"in the lab ?
	    
	    2.How can we measure the output rise/fall times when the
chip is available
	      in a plastic package ?Unless we open the package only the
enable pin of
	      an output buffer is available to us(along with the output
pin)-but we can't
	      access the input of the buffer.
	                  Can you send us any information regarding the
correlation of IBIS
	      models with Silicon ?Any URL's having such information
will be very helpful
	      for us.
	                                                       Thanks
and best regards,
	                                                        Amlan
Chakrabarti.
	                                                        Texas
Instruments (India) Ltd.
	                                                        E-Mail :
tatai@india.ti.com
	      

From owner-ibis  Mon Apr 27 09:07:22 1998
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Date: Mon, 27 Apr 1998 09:02:14 -0700
From: Jon Powell <jonp@pacbell.net>
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Organization: Viewlogic Consulting Services
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Subject: Re: Correlating IBIS models with actual Silicon measurements
References: <199804270952.EAA20342@asmhp23.india.ti.com>
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Amlan,

I have done a little work in this area and though I don't yet have a
definitive answer I can give you some data:

1) If you make you measurements in a packaged component and you know
what the parasitics of the packaged component are, you should be able to
back the parasitics out of the model. Unfortunately, this is probably
not easy.

2) I have made several models by doing the measurement and ignoring the
fact that I couldn't back the parasitics out. The QA to the actual
measurements was not perfect but it was pretty good and a lot better
that not having a model.

3) If you have SPICE models (or other internal part characterization
models), presumably these were made by correlation to bare die
measurements and as such would be good to use for creating models. Also,
if you have the raw die data it may contain the information you need for
an IBIS model.

regards,
Jon Powell
Senior Scientist, Viewlogic Consulting Services.

From owner-ibis  Mon Apr 27 10:43:30 1998
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From: sukanya@india.sps.mot.com (Sukanya Rajagopal)
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First choice is #3 & second one is #5 without the 'spoken here'.

/Sukanya Rajagopal



> From owner-ibis@server.vhdl.org Thu Apr 23 13:27 CDT 1998
> >Received: from server.vhdl.org by spsgate.sps.mot.com (4.1/SMI-4.1/Email 2.1 
10/25/93)
	id AA03700 for jonb@risc.sps.mot.com; Thu, 23 Apr 98 11:26:22 MST
> From: bobr@wv.mentorg.com (Bob Ross)
> Date: Thu, 23 Apr 98 10:15:10 PDT
> To: ibis@eda.org
> Subject: Forwarded: Fwd: ibis logo
> 
> To All:
> 
> Five new IBIS LOGO designs are available for viewing
> in preparation for the IBIS meeting discussion on
> Friday, April 24, 1998.  Comments are welcome.
> 
> Bob Ross
> Interconnectix/Mentor Graphics
> 
> 
> Date: Thu, 23 Apr 1998 12:02:24 -0500
> From: Patti Rusher <Pattir@gw.eia.org>
> To: bob_ross
> Subject: Fwd: ibis logo
> 
> 
> Date: Thu, 23 Apr 1998 11:32:34 -0500
> From: Deanna Sikora <Deannas@gw.eia.org>
> To: Pattir@gw.eia.org
> Subject: ibis logo
> 
> Patti - 
> 
> Per your request, the IBIS logos are online for the members to view
> and vote on. The URL is www.eia.org/eig/ibis/logo.htm. There are five
> logos to choose from. Hopefully one will work.
> 
> D. Sikora
> 
> 
From owner-ibis  Mon Apr 27 11:46:47 1998
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Date: Mon, 27 Apr 1998 11:43:17 -0700
From: Scott McMorrow <scottmc@teleport.com>
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#5 and ditch the "spoken here"

Scott McMorrow
Principal Engineer
SiQual



From owner-ibis  Mon Apr 27 18:11:11 1998
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <199804280110.SAA05660@rockie>
To: ibis@vhdl.org, tatai@india.ti.com
Subject: Re: Correlating IBIS models with actual Silicon measurements

Amlan,

>From item#1, we have always used a TDR approach to measuring C_comp. In this
case, we use the Tektronix 11801B with the IPA510(Interconnect Parametric Analyzer).

The reflection profile you get from launcing a fast incident wave into
the device can be analyzed using the IPA which uses a DSP algorithm to 
ret rid of multiple reflections. The IPA software allows you to get the
Z, L, C and td of the package pin. The C value will include the package as
well as the die pad. Then you need to take out the pkg number(usually available
from the pkg vendor)to get the effective C_comp for IBIS.

I have found this method to be accurate.

Regards,
Syed Huq
National Semiconductor Corp.

> 
> Hi,
>  We at Texas Instruments (India) are trying to develop IBIS models for one of our
> products .We have a few questions regarding the correlation of IBIS models
> (generated through simulation) with actual Silicon measurements -
>     
>     1.How can we measure the "input die capacitance"in the lab ?
>     
>     2.How can we measure the output rise/fall times when the chip is available
>       in a plastic package ?Unless we open the package only the enable pin of
>       an output buffer is available to us(along with the output pin)-but we can't
>       access the input of the buffer.
>                   Can you send us any information regarding the correlation of IBIS
>       models with Silicon ?Any URL's having such information will be very helpful
>       for us.
From owner-ibis  Tue Apr 28 10:20:46 1998
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To: ibis@eda.org
Subject: EIA IBIS Open Forum Minutes
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Date: Tue, 28 Apr 1998 10:17:33 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>



 DATE: 4/28/98

 SUBJECT: 4/24/98 EIA IBIS Open Forum Minutes
     
 VOTING MEMBERS AND 1998 PARTICIPANTS LIST:
 AMP                            (Martin Freedman) 
 Applied Simulation Technology  Norio Matsui, Raj Raghuram
 Cadence Design (& UniCAD)      C. Kumar, Don Telian, Patrick Riffault, 
				Craig Lewis, Greg Fitzgerald, Paul Galloway,
				Patrick Dos Santos, Catherine Weiss, 
				Alain Tribaudot, Geoffrey Ellis* 
 Cypress                        (Bruce Wenniger)
 Digital Equipment Corp.        Jeff Chu, Greg Edlund*, Bob Haller
 Hewlett Packard (EEsof, etc.)  Karl Kachigan, Henry Wu, Paul Gregory
 High Design Technology         Razvan Ene
 HyperLynx                      Kellee Crisafulli, Matthew Flora*
 Incases                        Olaf Rethmeier*, Scott Jacobson,
				Werner Rissiek
 Intel Corporation              Stephen Peters*, Arpad Muranyi*, Frank Kern,
				Will Hobbs, Prakash Radhakrishnan
   Columbia, SC (formerly NCR)  Dave Moxley
 Mentor Graphics (Zeelan,       Bob Ross*, George Opsahl, Mark Noneman,
   Interconnectix, etc.)        Tom Dagostino, Karine Loudet, Jean Oudinot,
				Manuel De Almeida, Stephane Rousseau, 
				Nevin Orhanovic
 Mitsubishi                     Hoang Nguyen*, Tam Cao
 Motorola                       (Ron Werner)
 National Semiconductor         Syed Huq*, Cheng-Yang Kao, John Goldie,
				Ikchang Song
 North East Systems Associates  Edward Sayre, Kathy Breda
   (NESA)
 NEC                            (Hiroshi Matsumoto)
 Quantic EMC                    (Mike Ventham)
 Texas Instruments              Thomas Fisher, Harvey Stiegler,
				Vincent Chang, Jean-Claude Perrin*,
				Peter Forstner
 Thomson-CSF                    Jean-Marc Claveau, Laurent Duzaic,
				Saverio Lerose, Benoit Meyniel,
				Jean Lefebvre  
 Viewlogic                      Jon Powell, Chris Rokusek*, Guy de Burgh, 
				Gary Mandel
 VeriBest                       Ian Dodd, David Weins, Ian Gabbitas
 VLSI Technology                D.C. Sessions
 Zuken-Redac                    (John Berrie) 

 OTHER PARTICIPANTS IN 1998:
 Actel                          Eric Tardif, Emmonvelle Gaudin 
 Aerospatiale                   Lionel Dreux, Claude Huet
 Alcatel (Bell, Espace, etc.)   John Fitzpatrick, W. Temmerman, 
				Laure Bessettes, Jean-Claude Pourtau,
				Daniel Peron
 ALS Design                     Yves Mouquet
 Ansoft                         Eric Bogatin
 Apple                          Fred Floresca, Danny Itani
 Apteq Design Systems           Dan FitzPatrick 
 Avanti                         Nik Bannov
 CERN                           Olivier Clere, Jean-Michel Sainson, 
				Rudi Zurbroken
 Compaq                         Shariq Rahma
 Crucial Technology             Rathna Reddy*
 EIA                            Patti Rusher*
 EMC                            Fawn Engelmann
 ENST, Paris                    Jean-Jacques Charlot
 European CAD Standardization   Adam Morawiec
   Intitiative (ECSI)
 Fairchild Semiconductor        Peter LaFlamme
 H.A.S Electronics              Haruny Said
 Intracon Design Ltd.           Derek Laidlaw
 Philips Semiconductor          Todd Andersen
 Scottish Electronics           Robert Easson
   Manufacturing Center (SEMC)
 Seagate                        Vanessa Howard
 SGS-Thomson                    Philippe Lefevre
 Siemens                        Gerald Bannert, Bernhard Unger, 
				Christian Marot, Miguel Hernandez,
				Gil Russell
 Symmetry                       Andy Hughes
 Tektronix                      Nassrin Ghahyasi
 Ultratest International        Chris O'Connor
 Xilinx                         Susan Wu

 In the list above, attendees at the meeting are indicated by *.  Principal
 members or other active members who have not attended are in parentheses.
 Participants who no longer are in the organization are in square brackets.

 Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
 follows:
   
   Date               Bridge Number     Reservation #    Passcode
   May 15, 1998       (916) 356-9200    4-167409         2939394
   June 5, 1998       (916) 356-9200    4-167410         9468535

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each Open Forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.

 -------------------------------- MINUTES -------------------------------------

 INTRODUCTIONS AND MEETING QUORUM
 Rathna Reddy from Crucial Technology (a spinoff of Micron Technology) is
 involved in memory board design using memory ICs and needs to use IBIS models
 to support EDA tools.


 MEMBERSHIP UPDATE AND TREASURER'S REPORT
 Patti Rusher reported that she sent Bob Ross a report indicating that there
 were no new members.  Bob reported that most of the members have paid and
 some special case situations will be handled off line.  For example, one
 company was double billed.  Also, some companies do not show having paid for
 the ibischk3 development project, and these issues will be traced offline.
 Bob indicated that in spite of some billing confusion and glitches, he is
 pleased with the payment progress to date.


 REVIEW OF MINUTES AND AR'S
 The AR's will be discussed at the meeting.  No corrections were noted on
 the previous two sets of meeting Minutes.


 MISCELLANY/ANNOUNCEMENTS
 Bob Ross indicated that he still plans the Majordomo conversion when he has
 time.

 Syed Huq reported that he continues to do roster updates and reports them
 to Bob as they occur to get the 1998 entries correctly reflected.


 PRESS AND WEB PAGE UPDATES
 Bob Ross noted that IBIS was mentioned briefly in "Printed-Circuit Board
 Changes Enable New Design Possibilities" by Cheryl Ajluni in the April 6, 
 1998 issue of Electronic Design, pp. 83-92.


 NEW MODELS AVAILABLE, LIBRARY UPDATE
 Bob Ross reported that Matthew Flora found that Aptos Semiconductor is
 supplying IBIS models at

   http://www.aptos.com/ibismain.htm


 OPENS FOR NEW ISSUES
 Bob Ross on meeting dates
 Bob Ross on ibischk3 and ebdchk3 distribution
 Bob Ross on 3-state ECL
 Bob Ross on Electrical Board Description issues.
 

 INTERNATIONAL/EXTERNAL PROGRESS
 - IEC 62014-1 (IBIS Version 2.1) - Patti Rusher still has not heard on the
   status.  This may not be resolved until the next IEC meeting in September.

 - pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuit 
   (IMIC) - Bob Ross noted the revised notation and the fact the the March 31,
   1998 copy designated Version 1.1 is available and downloadable in a .pdf
   format from the site below:

     http://tsc.eiaj.or.jp/tsc/SSC/IOPG.htm

   Comment deadline on this version closes on June 10, 1998.  Bob noted that
   a few pages could not be printed because of some font problems.

 - IEC 93/67/NP IBIS and EMC Simulation - Jean-Claude Perrin, Chair, reported
   that the New Work Item Proposal activity will be delayed by about four
   months due to workload conflicts and administrative delays.  He may have a
   document to show at the IEC meeting, but it will not be the formal
   proposal.

 - JC-16B - Bob Ross wanted to clarify the dates of the IBIS Summit Meeting
   planned for December, 1998.  Patti Rusher will check if it is planned for 
   Wednesday, December 9, 1998.  She also indicated that the JEDEC committee 
   was very pleased to have a co-located meeting with people from JC-16B.  
   The meeting will be mutually beneficial for the groups since they are 
   interested in the same issues from different perspectives.


 MEETING DATES
 Bob Ross inserted this new discussion topic here.  Bob indicated that the
 remaining meetings through the IBIS Summit Meeting at the Design Automation
 Conference and the other IBIS Summit meetings are listed below along with the 
 suggested emphasis:

   Friday, May 15, 1998 - Teleconference
   Friday, June 5, 1998 - Teleconference
   Thursday, June 18, 1998 - IBIS Summit Meeting (Design Automation 
			     Conference (DAC))
     Election of EIA IBIS Open Forum Officers
     Possible Final Technical Discussions regarding Open BIRDs
     Possible Ratification of Version 3.1
   Thursday, October 15, 1998 - IBIS Summit Meeting (PCB Conference East and
				IBIS Users Group)
     Educational Issues
     Accuracy and Validation Issues
   Wednesday, December 9, 1998 - IBIS Summit Meeting (JEDEC JC-16B)
     JC-16B Design/EDA Tool Simulation/Modeling Issues for configurations of
       mutual interest such as Series Stub Terminated Logic (STTL), etc.
   Monday, February 1, 1999 - IBIS Summit Meeting (DesignCon)

 Regarding the DAC IBIS meeting, Stephen Peters indicated that he would like
 to have IBIS Version 3.1 finalized, if possible.  Bob would also like this
 as a goal and will work hard to resolve and close out the open BIRDs.  Patti
 Rusher has reserved the room from 9 AM to 5 PM.  She needs to place the
 banquet order for food and plans just the morning refreshments and lunch.
 The meeting might not need to take all day.

 Greg Edlund indicated that having an IBIS Summit Meeting associated with the
 PCB Conference East had been discussed the previous day at the IBIS Users
 meeting on April 23, 1998.  There was considerable interested along with
 the interest in the educational aspects.


 IBIS EAST USERS GROUP ACTIVITIES
 Since scheduling and meetings was being discussed, Bob Ross moved this topic
 here to continue with Greg Edlunds' report on the April 23, 1998 meeting.
 Greg already reported that the interest was positive on having an IBIS Summit
 meeting at the time of the PCB Conference East.

 Greg summarized Paul Galloway's report and gave this report.  Due to job
 responsibility changes, Paul will have to pull away from chairing the Sub-
 committee on Software and Usability.  Paul reported that he and Ed Sayre
 are working on a possible two day IBIS training course.  

 Patti Rusher indicated that if it is to be associated with the PCB Conference
 East, then the proposal needs to be submitted soon to the show sponsors - 
 Miller Freeman.  The PCB magazine and Miller Freeman co-own this conference.  
 If the course were done through the conference, then the price would probably 
 be set and the profits would go the the conference organizers.  The deadline
 has already past for proposed seminars.  Bob Ross indicated that the course
 could also be set up separately.  Perhaps it could follow the IBIS Summit
 meeting as a dry run.  It could be a one-half day session after the IBIS
 Summit Meeting (although the feeling was that this would conflict with other
 IBIS Summit business).  It could also be done on a separate day.

 Greg also stated that Paul reported on other items - the Cadence s2ibis2
 windows manager was released.  The IBIS Users Group Web Page is being done by
 a group in Switzerland and is up, but information has not been put in it
 yet.

 Greg reported that he talked about the accuracy and validation activities.
 He has already sent minutes out to the ibis-user reflector.

 The meeting was held at Trilogic.  The next meeting is scheduled on Thursday,
 May 21, 1998.


 IBIS LOGO CHANGE
 Bob Ross summarized the comments to date on the 5 logos that were presented.
 Most favored #3, and some favored or listed #1 and #5 as the second choice.
 No one favored #2 or #4.  Based on this and the comments, the committee 
 agreed to pursue using #3.  The main comment is to try make the "IBIS"
 larger.  Arpad Muranyi did not see the association of the logo to the 
 of the committee.  Bob commented that most logos contain only the company
 names.  We could put "I/O Interface Specification underneath the logo in
 some instances to define "IBIS".  The EIA logo has its name, Electronic 
 Industries Alliance, under its logo on the Home page.

 Patti Rusher needs to know soon what the logo will be for preparation of the
 EIA booth at the Design Automation Conference.  Bob suggested that we are
 close enough to using #3 on the EIA IBIS Home page.  However, the suggested
 variations of the logo including a larger IBIS text could still be pursued
 on the tttp://www.eia.org/eig/ibis/ibis.html page.  We will formally decide
 on the logo at the May 15, 1998 meeting, if not sooner.

 Bob raised the issue of who is authorized to use the logo in response to
 a question by Greg Edlund on whether the new logo is downloadable from 
 a .gif file.  Syed Huq felt that the EIA IBIS Open Forum should control the
 usage of the logo since it contains the EIA logo and we do not want the IBIS
 logo to imply that unvalidated IBIS models comply with the IBIS standard.
 Patti thought that EIA IBIS Open Forum Members can use the logo (as a benefit
 for membership) to indicate that they are members of the EIA IBIS Open
 Forum.
  
 Bob stated that the previous "logo" evolved from a placard that was intended
 to be used at trade shows to promote IBIS acceptance.  This placard was given
 to anyone who might be supporting the IBIS effort.  So Bob, while aware of
 some implications, never really tried to control its usage.

 Since this is going to be the official logo, it can only be used by EIA IBIS
 Open Forum Member Companies to indicate the they are members.  It cannot be 
 used to indicate IBIS model compliance.  Any other usage such as by the IBIS 
 East Users Group) must officially be approved by the IBIS Open Forum (which 
 should not be a problem).


 EDITING COMMITTEE 
 Bob Ross indicated that he plans to upload an UNOFFICIAL IBIS ver3_1c.ibs 
 document on eda.org under /pub/ibis/wip.  It will contain the resolved
 BIRD47 change.

 The BNF AR remains.

 AR - Bob Ross generate and post a BNF for IBIS Version 3.0 (an IBIS Version
 3.0 ratification AR).


 BIRD44 - INTERPRETATION OF MIN/MAX/WEAK/STRONG DATA
 Bob Ross indicated no progress.

 AR - Andy Ingraham to issue BIRD44.1 with the changes and extensions noted
 in the March 13, 1998 IBIS Open Forum meeting minutes.


 IBISCHK2+ (VER 2.1.15) PROGRESS
 Bob Ross indicated that he will still act on compressing the existing 
 executables per last meeting - .Z for unix applications, .zip for DOS Windows
 applications.  Matthew Flora and Chris Rokusek are still controlling the
 master of the Version 2.116 release

 BUG27 - Parser Crashes when Calling [Package Model]
 Matthew Flora found another bug which causes a crash.  This occurs since 
 some code checks for line lengths of 79 characters and other code checks for
 80 characters.  Matthew located the source of the problem.

 Bob classified this as Severe, High, Open, and intends that this fix be
 rolled into ibischk2.1.16.


 VERSION 3.1 PARSER DEVELOPMENT
 Bob Ross stated that he is checking in detail the Beta Version 3.0.1 of 
 ibischk3 and ebdchk3.  So far it appears very good.  Some of the prior
 bugs have been fixed in this version, but Bob still needs to confirm that
 the BUGs have been fixed in the embedded ibischk2+ code.  Bob noted that 
 the .make files has a DEFINE -DIBIS_PRINT statement which causes all the 
 variables to be dumped.  The code can be compiled without this statement 
 for a smaller listing of just the Errors and Warnings.

 Bob raised the issue that even though the project is funded by 12 companies,
 we could release the executables.  Matthew Flora indicated that this was
 just preliminary code, so it is possible to have some undetected mistakes.
 Matthew also indicated that it would be valuable to have more people using
 to executables to help test it.  Bob cited that historically the development
 versions of the ibis_chk and ibischk2 executables were made available to 
 support testing and encourage IBIS model development.  Stephen Peters and
 others generally agreed that we should release the executables.  Bob stated
 that we could release just the executables that were convenient such as the
 DOS Windows versions and a few others.  Chris Rokusek volunteered on a one-
 time basis before the Design Automation Conference meeting to generate the
 complete set of ibischk3/ebdchk3 executables.  Bob volunteered to compress
 and post them.

 AR - Chris Rokusek generate the ibischk3 and ebdchk3 executables for Version
 3.0.1 in a timely manner and sent to Bob Ross.  Bob compress and put the
 preliminary executables on eda.org for general access.

 Chris Rokusek also stated that a company who paid for the source code 
 wants to add additional sanity checking, and Chris wondered how this may
 be folded back into the official source.  Bob stated that any
 changes of this nature have to be worked thru the full	committee.

 COOKBOOK 
 Stephen Peters reports that there no is progress on the Cookbook project.


 IBIS MODEL REVIEW COMMITTEE DISCUSSION
 Matthew Flora indicated no activity.  However, Bob Ross knows of a possible
 future testing situation. 

 For general information, the contact person is:

   Matthew Flora, HyperLynx                   mbflora@hyperlynx.com


 BIRD42.3 - MODELING CURRENT WAVEFORMS
 Bob Ross indicated no activity, but BIRD42.3 will be discussed in the near
 future.  Bob has some concern about specifying both the [Pullup Reference
 Current] and [Pulldown Reference Current] and some numerical interactions.
 Bob indicated that aspects of BIRD42.3 have been discussed at the last two
 IBIS Summit Meetings.  Bob also indicated that the EMC and IBIS Modeling
 sub-committee wanted the functionality that BIRD42.3 provides.

 
 BIRD48 - ADD MODEL
 BIRD49 - ADD MODEL DYNAMIC CLAMPS
 BIRD50 - ADD MODEL BUS HOLD
 Bob Ross made several comments on these BIRDs related to some additional 
 functionality that was known, but not included in the original proposals.
 First, there still needs to be a mechanism to bypass the edge-trigger 
 method of activating the dynamic clamps since some implementations allow the
 clamps to be invoked from an external clock so that the clamp is preset in a
 shifted clamp state.  Arpad Muranyi mentioned that it might be possible to 
 use a negative time value in the [GND Pulse Table] and [POWER Pulse Table] to 
 indicate a preset state.  This could relate to the operation to the control
 pulse used by EDA tools.  Bob will look into possible methods.

 Bob also stated that some of the Add Model functionality is active only
 for certain states.  Since the Model_type might be used for a particular
 state (such as Input, I/O or Output) another subparameter such as "State"
 might be needed.  It would indicate usage during Input, Output, or I/O
 modes.

 Bob also noted that the embedded added models may be for an Open_sink or
 Open_source state.  The [Rising Waveform] and [Falling Waveform] extensions
 could be used to explicitly give the internal loading conditions since the 
 internal added model configuration was not given.

 
 BIRD45.1 - DYNAMIC CLAMPS
 Bob Ross called for a vote on BIRD45.1 for the purpose of rejecting it since
 BIRD48 and BIRD49 were intended to replace BIRD45.1.  After some discussion
 on historical details, a vote on BIRD45.1 was held.

 BIRD45.1 was reject unanimously with two abstentions from newer members based 
 on not being familiar with the issues.

 BIRD46.1 - RELAXATION OF SOME IBIS FILE NAME RESTRICTIONS
 Since BIRD46.1 has not been issued, Bob Ross deferred the discussion. 
 
 AR - Matthew Flora issue BIRD46.1 to include references to the .pkg file
 and .ebd file and to change the limitation from 64 total characters to
 a <filename> limit of 20 characters and delete the references to allowing
 the period "." character.


 3-STATE ECL
 As a new item Bob Ross indicated that per the discussion at the last meeting,
 he may issue a BIRD on this for adding the Model_type 3-state_ECL.  He knows
 of an ECL device or two which really has a high-Z mode.


 ELECTRICAL BOARD DESCRIPTION DISCUSSION
 As a new item Bob Ross indicated that there were some Electrical Board 
 Description clarification and technical questions.  He might issue a BIRD
 for clarification.  The items are:

 (1)  We intended that circular references not be allowed, but Bob cannot find
      this being prohibited - e.g., EBD A references EBD B which references
      EBD A.  Stephen Peters indicated that he assumed that this was not 
      permitted.  Bob thought ebdchk3 might actually test for this.

 (2)  Bob questioned whether we want to keep the restriction of .ebd files
      not containing actual IBIS models.  A single file for the .ebd and all
      related IBIS models (and even other Electrical Board Descriptions) would 
      help assure that all of the related information of an Electrical Board 
      Description are included in the same file.  Bob indicated that we
      originally prohibited including IBIS data in .ebd files for some
      practical reasons.  We did not want to make the ebdchk3 utility too
      complicated in order to make its development manageable.  We also did 
      not want to impose on the user a very large utility to do just IBIS 
      model or EBD model checking.  These assumptions may not be valid.  At
      this time, a superset checker for both may be practical.  We already 
      permit a separate .pkg file and also the [Define Package Model] keyword 
      to be defined within a .ibs file, so allowing an IBIS component in a 
      .ebd file could work in a similar manner.  The reference designator 
      listing referencing the same file would needed for referenced IBIS 
      models.  Bob stated, however, that one issue could be conflicting 
      [Define Electrical Description] names and [Component] names.  

 (3)  Regarding conflicting names for [Define Electrical Description] and
      [Component], Bob recommended that the names be different in practice to 
      avoid confusion.


 NEXT MEETING:
 The next teleconference meeting is on Friday, May 15, 1998, 8:00 A.M. to 
 9:55 A.M.  BIRD46.1, if issued, is scheduled for a vote.  Final resolution
 of the IBIS logo is scheduled.
 ==============================================================================
				       NOTES
 
 IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
	     bob_ross@mentorg.com
	     Modeling Engineer, Interconnectix BU of Mentor Graphics
	     8005 S.W. Boeckman Road, Wilsonville, OR 97070

 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785
	     huq@rockie.nsc.com
	     Staff Applications Engineer, National Semiconductor, M/S A-2595
	     2900 Semiconductor Drive, Santa Clara, CA 95052
 
 SECRETARY:  Stephen Peters (503) 264-4108, Fax: (503) 264-4515
	     sjpeters@ichips.intel.com
	     Senior Hardware Engineer, Intel Corporation
	     M/S JF1-56
	     2111 NE 25th Ave. 
	     Hillsboro, Oregon 97124-5961

 LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
	     jonp@qdt.com
	     Senior Scientist, Viewlogic (formerly Quad Design)
	     1385 Del Norte Rd., Camarillo, CA 93010
  
 This meeting was conducted in accordance with the EIA Legal Guides and EIA
 Manual of Organization and Procedure.
 
 The following e-mail addresses are used:

   ibis-request@eda.org
       To join, change, or drop from either the IBIS Open Forum Reflector
       (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
       or both.  State your request.

   ibis-info@eda.org
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   ibis@eda.org
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.  Job posting information is not permitted.

   ibis-users@eda.org
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.  Job posting information is not permitted.

   ibischk-bug@eda.org
       To report ibischk2 parser bugs.  The Bug Report Form Resides on
       eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

       To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
       which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
       /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
       respectively.

 Information on IBIS technical contents, IBIS participants, and actual
 IBIS models are available on the IBIS Home page found by selecting the
 Electronic Information Group under:

   http://www.eia.org

 Check the pub/ibis directory on eda.org for more information on previous 
 discussions and results.  You can get on via FTP anonymous.
 ==============================================================================

From owner-ibis  Wed Apr 29 13:28:45 1998
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Date: Wed, 29 Apr 1998 15:12:02 -0500
From: sukanya@india.sps.mot.com (Sukanya Rajagopal)
Message-Id: <199804292012.PAA10575@india.sps.mot.com>
To: ibis@vhdl.org
Subject: Need to validate the model....
Cc: sukanya@india.sps.mot.com
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Hello!

We have an IBIS model but do not have a simulator which can run IBIS. Is there a 
way to validate the model without having to use a simulator which can run IBIS. 
I would appreciate any information or pointers to some URLs.

Thank you,
Sukanya Rajagopal.
From owner-ibis  Wed Apr 29 18:26:15 1998
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <199804300125.SAA11392@rockie>
To: ibis@vhdl.org, sukanya@india.sps.mot.com
Subject: Re: Need to validate the model....

Sukanya,

You can go to the IBIS web page(www.eia.org/EIG/IBIS/ibis.htm)and
look under 'Poster', all member EDA companies are listed there.
I am sure they will help you out with checking out the model and
simulating it for verification.

You can also send the model to the IBIS Librarian(jon@qdt.com)to
check it out and give you some feedbacks.

Regards,
Syed.
National Semiconductor Corp.

> From owner-ibis@server.vhdl.org Wed Apr 29 14:30:44 1998
> Date: Wed, 29 Apr 1998 15:12:02 -0500
> From: sukanya@india.sps.mot.com (Sukanya Rajagopal)
> To: ibis@vhdl.org
> Subject: Need to validate the model....
> Cc: sukanya@india.sps.mot.com
> Content-Type> : > text/plain> ; > charset=us-ascii> 
> Content-Transfer-Encoding: 7bit
> Content-Md5: Q+xCBvVINGiXreNk1mLNdA==
> 
> Hello!
> 
> We have an IBIS model but do not have a simulator which can run IBIS. Is there a 
> way to validate the model without having to use a simulator which can run IBIS. 
> I would appreciate any information or pointers to some URLs.
> 
> Thank you,
> Sukanya Rajagopal.
> 
From owner-ibis  Wed Apr 29 20:23:22 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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	id AA11225; Wed, 29 Apr 98 20:19:41 PDT
Date: Wed, 29 Apr 98 20:19:41 PDT
Message-Id: <9804300319.AA11225@bob>
To: huq@rockie.nsc.com, ibis@vhdl.org, sukanya@india.sps.mot.com
Subject: Re: Need to validate the model....

Sukanya:

You can also send the model to mbflora@hyperlynx.com, and Matthew
will distribute it to 6 different vendors on the Model Review
Committee to test in their products and to give you feedback
on what it may need and on how well it works.

Best Regards,
Bob Ross
Interconnectix/Mentor Graphics

> Sukanya,

> You can go to the IBIS web page(www.eia.org/EIG/IBIS/ibis.htm)and
> look under 'Poster', all member EDA companies are listed there.
> I am sure they will help you out with checking out the model and
> simulating it for verification.

> You can also send the model to the IBIS Librarian(jon@qdt.com)to
> check it out and give you some feedbacks.

> Regards,
> Syed.
> National Semiconductor Corp.

> > From owner-ibis@server.vhdl.org Wed Apr 29 14:30:44 1998
> > Date: Wed, 29 Apr 1998 15:12:02 -0500
> > From: sukanya@india.sps.mot.com (Sukanya Rajagopal)
> > To: ibis@vhdl.org
> > Subject: Need to validate the model....
> > Cc: sukanya@india.sps.mot.com
> > Content-Type> : > text/plain> ; > charset=us-ascii> 
> > Content-Transfer-Encoding: 7bit
> > Content-Md5: Q+xCBvVINGiXreNk1mLNdA==
> > 
> > Hello!
> > 
> > We have an IBIS model but do not have a simulator which can run IBIS. Is there a 
> > way to validate the model without having to use a simulator which can run IBIS. 
> > I would appreciate any information or pointers to some URLs.
> > 
> > Thank you,
> > Sukanya Rajagopal.
> > 


From owner-ibis  Thu Apr 30 07:57:37 1998
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From: sukanya@india.sps.mot.com (Sukanya Rajagopal)
Message-Id: <199804301454.JAA11100@india.sps.mot.com>
To: ibis@vhdl.org
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Hello All!

Thanks for all your responses. I am currently pursuing this matter further. I 
will get some thoughts on Kellee's offer to run it for us and I definitely do 
appreciate your offer, Kellee.

BTW, yes I did run the syntax checker on our model and it checks ok. 

Until next time,
Sukanya Rajagopal. 
