From owner-ibis Thu Dec 3 16:23:10 1998 Received: from mail-gw2.pacbell.net (mail-gw2.pacbell.net [206.13.28.53]) by server.eda.org (8.8.5/8.8.3) with ESMTP id QAA05979 for ; Thu, 3 Dec 1998 16:23:10 -0800 (PST) Received: from pacbell.net (ppp-209-79-182-169.vntrcs.pacbell.net [209.79.182.169]) by mail-gw2.pacbell.net (8.8.8/8.7.1+antispam) with ESMTP id QAA09004; Thu, 3 Dec 1998 16:18:26 -0800 (PST) Message-ID: <36672A4D.AEB989D2@pacbell.net> Date: Thu, 03 Dec 1998 16:18:21 -0800 From: Jon Powell Reply-To: jpowell@viewlogic.com Organization: Viewlogic Consulting Services X-Mailer: Mozilla 4.04 [en]C-PBI-NC404 (Win95; I) MIME-Version: 1.0 To: ibis@vhdl.org Subject: DesignCon booth and signage Content-Type: multipart/mixed; boundary="------------8FE986D7259D008F79CEF994" This is a multi-part message in MIME format. --------------8FE986D7259D008F79CEF994 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit OK, From the inputs I have received from other members it seems that the best approach to the SuperCon sign is for me to make 1 (or 2) big signs that I put everyones logo's on. If you wish to have your company logo on the IBIS sign: 1) You must be a current IBIS member (EIA etc.) 2) You must send me an electric copy of your logo that is suitable for approx. 8x10 inch printing (ie. high resolution). The picture must be in either JPEG or GIFF format. 3) You must send me a request to have your logo on the sign. (email is OK, I think) 4) All of this material must be to me by Jan 1, 1999 (really) 5) Sign background color will be WHITE. If you LOGO needs a different background color make sure that is included in the artwork. To avoid other issues, I would like to only have COMPANY LOGOs on the sign. No product logos or booth numbers. my email address is: jonp@pacbell.net If any part of this seems unworkable, please send me comments soonest. Otherwise: LET THE LOGOS FLY! regards, jon IBIS Librarian --------------8FE986D7259D008F79CEF994 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jon Powell Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Jon Powell n: Powell;Jon org: Viewlogic Consulting Services adr: 1369;;;Camarillo;CA;93010;USA email;internet: jonp@pacbell.net title: Manager High Speed Design Services tel;work: 805 988 8250 tel;fax: 805 988 8259 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------8FE986D7259D008F79CEF994-- From owner-ibis Fri Dec 4 17:18:03 1998 Received: from hebe.or.intel.com (hebe.or.intel.com [134.134.248.4]) by server.eda.org (8.8.5/8.8.3) with ESMTP id RAA09635 for ; Fri, 4 Dec 1998 17:18:03 -0800 (PST) Received: from orsmsx28.jf.intel.com (orsmsx28.jf.intel.com [192.168.65.28]) by hebe.or.intel.com (8.8.6/8.8.5) with ESMTP id RAA26663 for ; Fri, 4 Dec 1998 17:23:12 -0800 (PST) Message-Id: <199812050123.RAA26663@hebe.or.intel.com> Received: by ORSMSX28 with Internet Mail Service (5.5.2232.9) id ; Fri, 4 Dec 1998 17:13:20 -0800 From: "Muranyi, Arpad" To: ibis@vhdl.org Subject: BIRD 57 Date: Fri, 4 Dec 1998 17:12:00 -0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2232.9) Content-Type: multipart/mixed; boundary="----_=_NextPart_000_01BE1FEC.720BB21D" This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. ------_=_NextPart_000_01BE1FEC.720BB21D Content-Type: text/plain Please see attachment. ============================================================================ === ------_=_NextPart_000_01BE1FEC.720BB21D Content-Type: text/plain; name="bird57c0.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="bird57c0.txt" Content-Location: ATT-0-D5EF465FDD8BD211AC4400A0C98409CB-b ird57c0.txt IBIS folks: BIRD57 is issued at the last minute to deal with a real-life "timed = latch" implementation situation which could not be modeled with the current Bus_hold model. The proposed resolution is to add a subparameter to = the [Submodel Spec] keyword. Because these changes are required to model exisiting devices, it would = be very important to incorporate them in version 3.2 of the IBIS spec. = Since the changes are relatively minor, it would be desirable to vote on this = BIRD on the December 18, 1998 meeting provided no serious technical issues = arise. Arpad Muranyi Intel Corporation ************************************************************************= ******=20 ************************************************************************= ****** BIRD ID#: 57 ISSUE TITLE: Timed Bus Hold Extension REQUESTER: Bob Ross, Mentor Graphics, Arpad Muranyi & Stephen Peters, Intel=20 DATE SUBMITTED: December 4, 1998 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ************************************************************************= ******=20 ************************************************************************= ****** STATEMENT OF THE ISSUE: A new application of the bus hold functionality involves turning off (putting in a Hi Z state) the bus hold circuitry after a period of = time.=20 The Bus_hold submodel can be extended to support this functionality = with the addition of a delay subparameter in the [Submodel Spec] keyword. ************************************************************************= ****** STATEMENT OF THE RESOLVED SPECIFICATIONS: The unofficial IBIS Version 3.2 document that includes the BIRD48.4, = BIRD49.4=20 and BIRD50.3 extensions is used as the basis for showing how BIRD57 = would be implemented. The original [Submodel Spec] keyword is modified by the addition of a = new subparameter called Off_delay. The changes are indicated by an = asterisk at the beginning of each line (|*) that it effects. |=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=20 | Keyword: [Submodel Spec] | Required: No | Description: The [Submodel Spec] keyword defines four columns under = which=20 | specification and information subparameters are defined = for=20 | submodels. |* Sub-Params: V_trigger_r, V_trigger_f, Off_delay | | Usage Rules: The [Submodel Spec] is to be used only with submodels. | | The following subparameters are used: | V_trigger_r Rising edge trigger voltage=20 | V_trigger_f Falling edge trigger voltage=20 |* Off_delay Turn-off delay from = V_trigger_r |* or V_trigger_f |* | For each subparameter contained in the first column, = the | remaining three hold its typical, minimum and maximum = values.=20 | The entries of typical, minimum and maximum be must be = placed=20 | on a single line and must be separated by at least one = white=20 | space or tab or tab character. All four columns are = required=20 | under the [Submodel Spec] keyword. However, data is = required=20 | only in the typical column. If minimum and/or maximum = values=20 | are not available, the reserved word "NA" must be used = to | indicate the typical value by default.=20 | | The values in the minimum and maximum columns usually | correspond to the values in the same columns for the = inherited=20 | top-level voltage range or reference voltages in the = top-level=20 |* model. The V_trigger_r and V_trigger_f subparameters=20 |* should hold values in the minimum and maximum columns = that=20 |* correspond to the voltage range or reference voltages = of the |* top-level model. The Off_delay subparameter, however, = is an=20 |* exception to this rule because in some cases it may be = |* completely or partially independent from supply = voltages=20 |* and/or manufacturing process variations. Therefore = the |* minimum and maximum entries for the Off_delay = subparameter |* should be ordered simply by their magnitude. | | Unless noted, each [Submodel Spec] subparameter is = independent=20 | of any other subparameter. | | V_trigger_r, V_trigger_f rules:=20 | | The voltage trigger values for the rising and falling = edges=20 | provide the starting time when an action is initiated. | |* Off_delay rules:=20 |* |* The functionality of the Off_delay subparameter is to = provide |* an additional time related mechanism to turn off = circuit |* elements. |* |-----------------------------------------------------------------------= ------=20 | Dynamic Clamp Example: | [Submodel Spec] | Subparameter typ min max=20 | V_trigger_r 3.6 2.9 4.3 | Starts power = pulse table=20 V_trigger_f 1.4 1.2 1.6 | Starts gnd pulse = table | | Bus Hold Example: | [Submodel Spec] | Subparameter typ min max V_trigger_r 3.1 2.4 3.7 | Starts low to = high | bus hold transition V_trigger_f 1.8 1.6 2.0 | Starts high to = low | bus hold transition |** New Example added here | | Bus_hold application with pullup structure triggered on and then = clocked off:=20 | [Submodel Spec] | Subparameter typ min max V_trigger_r 3.1 2.4 3.7 | Low to high = transition | triggers the turn = on=20 | process of the = pullup V_trigger_f -10.0 -10.0 -10.0 | Not used, so = trigger | voltages are set = out=20 | of range Off_delay 5n 6n 4n | Time from rising = edge | trigger at which = the | pullup turned off | |** End of new example The revised Bus Hold Section shows modifications by |* lines to = document the new Off_delay subparameter and application information including a new example: |=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=20 | | Bus Hold: | | When the Submodel_type subparameter under the [Submodel] keyword is = set to=20 | Bus_hold, the added model describes the bus hold functionality. = However,=20 | while described in terms of bus hold functionality, active = terminators | can also be modeled. | | Existing keywords and subparameters are used to describe bus hold = models.=20 | The [Pullup] and [Pulldown] tables both are used to define an = internal | buffer that is triggered switch to its opposite state. This = switching=20 | transition is specified by a [Ramp] keyword or by the [Rising = Waveform] | and [Falling Waveform] keywords. The usage rules for these keywords = are the=20 | same as under the [Model] keyword. In particular, at least either = the | [Pullup] or [Pulldown] keyword is required. Also, the [Ramp] keyword = is | required, even if the [Rising Waveform] and [Falling Waveform] tables = exist.=20 | However, the voltage ranges and reference voltages are inherited from = the | top-level model. | |* For bus hold submodels, the [Submodel Spec] keyword, V_trigger_r, = and |* V_trigger_f are required. The Off_delay subparameter is optional, = but |* can only be used if the submodel consists of a pullup or a pulldown |* structure only, and not both. Devices which have both pullup and = pulldown |* structures controlled in this fashion can be modeled using two = submodels, |* one for each half of the circuit. | | The transition is triggered by action at the die using the [Submodel = Spec]=20 | V_trigger_r and V_trigger_f subparameters as follows: | | If the starting voltage is below V_trigger_f, then the bus hold model = is | set to the low state causing additional pulldown current. If the = starting=20 | voltage is above V_trigger_r, the bus hold model is set to the high | state for additional pullup current. When the input passes though | V_trigger_f during a high-to-low transition at the die, the bus hold = output=20 | switches to the low state. Similarly, when the input passes though | V_trigger_r during a low-to-high transition at the die, the bus hold = output=20 | switches to the high state. | |* If the bus hold submodel has a pullup structure only, V_trigger_r = provides |* the time when its pullup is turned on and V_trigger_f or Off_delay = provides |* the time when it is turned off, whichever occurs first. Similarly, = if the |* submodel has a pulldown structure only, V_trigger_f provides the = time when |* its pulldown is turned on and V_trigger_r or Off_delay provides the = time |* when it is turned off, whichever occurs first. The required = V_trigger_r |* and V_trigger_f voltage entries can be set to values outside of the = input |* signal range if the pullup or pulldown structures are to be held on = until |* the Off_delay turns them off. |* |* The starting mode for each of submodels which include the Off_delay |* subparameter of the [Submodel Spec] keyword is the off state. Also, = while |* two submodels provide the desired operation, either of the submodels = may |* exist without the other to model turning on and off only a pullup or = a |* pulldown current. |* | No additional keywords are needed for this functionality.=20 |-----------------------------------------------------------------------= ------=20 | | Complete Bus Hold Model Example: | [Submodel] Bus_hold_1 Submodel_type Bus_hold | [Submodel Spec] | Subparameter typ min max=20 | V_trigger_f 1.3 1.2 1.4 | Falling edge = trigger=20 V_trigger_r 3.1 2.6 4.6 | Rising edge = trigger=20 | | typ min max | [Voltage Range] 5.0 4.5 5.5 | Note, the actual voltage range and reference voltages are inherited = from=20 | the top-level model. | [Pulldown] | -5V -100uA -80uA -120uA -1V -30uA -25uA -40uA 0V 0 0 0 1V 30uA 25uA 40uA 3V 50uA 45uA 50uA 5V 100uA 80uA 120uA 10v 120uA 90uA 150uA | [Pullup] | -5V 100uA 80uA 120uA -1V 30uA 25uA 40uA 0V 0 0 0 1V -30uA -25uA -40uA 3V -50uA -45uA -50uA 5V -100uA -80uA -120uA 10v -120uA -90uA -150uA | |-----------------------------------------------------------------------= ------=20 | [Ramp] | typ min max=20 dV/dt_r 2.0/0.50n 2.0/0.75n 2.0/0.35n=20 dV/dt_f 2.0/0.50n 2.0/0.75n 2.0/0.35n=20 R_load =3D 500 | |** A Second Example is inserted below=20 | |-----------------------------------------------------------------------= ------=20 | | Complete Pullup Timed Latch Example:=20 | [Submodel] Timed_pullup_latch Submodel_type Bus_hold | [Submodel Spec] | Subparameter typ min max=20 | V_trigger_r 3.1 2.6 4.6 | Rising edge = trigger=20 | Values could be = set out | of range to = disable the | trigger V_trigger_f 1.3 1.2 1.4 | Falling edge = trigger Off_delay 3n 5n 2n | Delay to turn = off the | pullup table | | Note that if the input signal goes above the V_trigger_r value, the | pulldown structure will turn off even if the timer didn't expire yet. | | typ min max | [Voltage Range] 5.0 4.5 5.5 | Note, the actual voltage range and reference voltages are inherited = from=20 | the top-level model. | [Pulldown] | -5V -100uA -80uA -120uA -1V -30uA -25uA -40uA 0V 0 0 0 1V 30uA 25uA 40uA 3V 50uA 45uA 50uA 5V 100uA 80uA 120uA 10v 120uA 90uA 150uA | | [Pullup] table is omitted to signal Open_source functionality=20 | |-----------------------------------------------------------------------= ------=20 | [Ramp] | typ min max=20 dV/dt_r 2.0/0.50n 2.0/0.75n 2.0/0.35n=20 dV/dt_f 2.0/0.50n 2.0/0.75n 2.0/0.35n=20 R_load =3D 500 | |** End of Second Example |=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: BIRD57 is basically an extension of BIRD50.3. BIRD50.3 describes a = static=20 bus hold circuit which is controlled only by the pad voltage of the = device. However, some devices can have the bus hold circuits which are turned = on=20 by the pad voltage, but are turned off by an internal timer of clock=20 signal. These devices could not be modeled using the BIRD50.3 = extensions.=20 BIRD57 provides the extension to model such devices. Several approaches were considered: Modify or Enhance the [Driver Schedule] keyword for Input models (perhaps including a new keyword) Create a new Submodel_type for 'Timed_latch' as a new Submodel = extension=20 Enhance the Bus_hold Submodel The first choice builds upon an older approach versus the newer, = preferred=20 Submodel approach. The second choice was considered, but in our = discussions=20 we would have had to document mew meanings for some transition = relationships=20 related to a desired Hi-Z mode. The third choice was selected because the existing Bus Hold description = for=20 "Open_drain" or Open_source" functionality could be easily extended. = The=20 off state of an Open_* device is equivalent to a Hi-Z mode. Two Submodels are used since the off transition of each of the = Submodels=20 can be entered by the [Ramp] information or corresponding [Rising = Waveform] or [Falling Waveform] table. A single Submodel is permitted for just = turning=20 on and off a pullup or pulldown current. ************************************************************************= ****** ANY OTHER BACKGROUND INFORMATION: BIRD57 evolved from discussions between Bob Ross, Arpad Muranyi, and = Stephen=20 Peters on December 3, 1998 to resolve how IBIS Version 3.2 would handle = a=20 new active latch that is being implemented in digital buffers. ************************************************************************= ****** ------_=_NextPart_000_01BE1FEC.720BB21D-- From owner-ibis Fri Dec 4 18:00:55 1998 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id SAA09696 for ; Fri, 4 Dec 1998 18:00:55 -0800 (PST) Received: from em-wv03.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id RAA02053; Fri, 4 Dec 1998 17:55:43 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.8.8/CF5.40R) id RAA22209; Fri, 4 Dec 1998 17:55:41 -0800 (PST) From: bob_ross@mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA16906; Fri, 4 Dec 98 17:55:41 PST Date: Fri, 4 Dec 98 17:55:41 PST Message-Id: <9812050155.AA16906@bob> To: ibis@eda.org Subject: Version 3.2 Ratification Plan To All: I have uploaded an unofficial work in progress version of IBIS version 3.2 as ver3_2e.ibs on eda.org/pub/ibis/wip. It contains a Pending BIRD56. Because of the need to consider the recently issued BIRD57, we are postponing plans to consider ratifying IBIS Version 3.2 at the December 18, 1998 meeting. We will consider closing out the open BIRDs leading to the documements needed for a ratification vote at the meeting that will follow. Bob Ross Interconnectix/Mentor Graphics From owner-ibis Tue Dec 8 05:53:00 1998 Received: from emcmail.lss.emc.com (emcmail.lss.emc.com [168.159.48.78]) by server.eda.org (8.8.5/8.8.3) with ESMTP id FAA19272 for ; Tue, 8 Dec 1998 05:52:59 -0800 (PST) Received: from fishbowl02.emc.com (fishbowl02.lss.emc.com [168.159.48.62]) by emcmail.lss.emc.com (8.9.1/8.9.1) with SMTP id IAA14516 for ; Tue, 8 Dec 1998 08:45:47 -0500 (EST) Received: by fishbowl02.emc.com with VINES-ISMTP; Tue, 8 Dec 98 8:47:44 -0500 Date: Tue, 8 Dec 98 8:46:10 -0500 Message-ID: X-Priority: 3 (Normal) To: From: "fabrizio zanella" Reply-To: Errors-to: Subject: IBIS Connector model X-Incognito-SN: 1467 X-Incognito-Version: 4.11.23 MIME-Version: 1.0 Content-type: text/plain; charset=us-ascii IBIS Connector sub-group meeting minutes: Date: 12-3-98 Attended by: ************ Fabrizio Zanella (EMC), Kellee Crisafulli (Hyperlynx), Gus Panella (Molex), Mark Gailus and Mike Khusid (Teradyne) Overview: ************ The specification has improved considerably and now follows the IBIS IC format. The basic specification is nearing completion and could now be used to define and simulate connector models of up to 40 to 100 pins. It could be used as is with larger models of any size however the simulation and development aspects of the method would discourage use by many companies. Work is in progress to create a method of modeling very large connectors that is both easy to create and fast to simulate. We are assuming models will need to be created for connectors with 1000's of pins and methods need to be defined that are both acceptable to the connector companies and the speed requirements of the simulator companies. We are calling this a "swath" method. We expect to have a solid base line specification for release to the full IBIS open forum by January. Discussion: *********** 1) Discussed removing the SLM and MLM keywords since SLM models can be created with Banded_matrix and Bandwidth=0. The group agreed and the SLM/MLM type keyword is to be removed. 2) Discussed adding a new keyword Diagonal_matrix that is a simplified method of creating a Banded_matrix with Bandwidth=0. The group agreed and the keyword is to be added. 3) Discussed usage of the swath operator and decided to add additional keywords to describe the direction of the swath i.e. horizontal, vertical, and grid (both directions). 4) Discussed improvements, changes and additions to example models. Action Items: ************* Kellee: Update the specification from 0.22 to 0.23 Status: Done The specification changes per our meeting yesterday are checked in to directory 23 on the connector FTP site. I also moved the old versions 20-22 into the archive directory. Gus: Modify existing model to convert it to two models, one using swath the other just a basic multi line model. Status: Done More work remaining on the swath model as the spec. is improved. Kellee: Create one additional model showing a simple SLM connector. Status: in process Kellee: Create one additional simple model that uses SLM with multiple sections. Status: in process Kellee: Create one additional model showing a simple resistive solder joint connection between 2 circuit boards. Status: in process Gus: Create 10x10 full connector model for comparison of IBIS model to SPICE model. Status: in process Gus: Create other models of GRID type connector using swath. status: in process Regards, Fabrizio Zanella EMC, Hardware Engineering fzanella@fishbowl02.emc.com 508-435-2075, x4645 From owner-ibis Tue Dec 8 14:56:48 1998 Received: from smtp3.ny.us.ibm.com (smtp3.ny.us.ibm.com [198.133.22.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id OAA21166; Tue, 8 Dec 1998 14:56:47 -0800 (PST) From: gedlund@us.ibm.com Received: from northrelay01.pok.ibm.com (northrelay01.pok.ibm.com [9.117.200.21]) by smtp3.ny.us.ibm.com (8.8.7/8.8.7) with ESMTP id RAA88728; Tue, 8 Dec 1998 17:32:51 -0500 Received: from us.ibm.com (d51mta10.pok.ibm.com [9.117.200.38]) by northrelay01.pok.ibm.com (8.8.7/NCO v1.6) with SMTP id RAA51976; Tue, 8 Dec 1998 17:51:30 -0500 Received: by us.ibm.com(Lotus SMTP MTA Internal build v4.6.2 (651.2 6-10-1998)) id 852566D4.007D8FAC ; Tue, 8 Dec 1998 17:51:27 -0500 X-Lotus-FromDomain: IBMUS To: ibis@vhdl.org, ibis-users@vhdl.org Message-ID: <852566D4.007D8E17.00@us.ibm.com> Date: Tue, 8 Dec 1998 16:49:09 -0600 Subject: IBIS Accuracy minutes - 12/04/98 Mime-Version: 1.0 Content-type: text/plain; charset=windows-1257 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by server.eda.org id OAA21167 IBIS Accuracy Subcommittee Minutes Friday, December 4, 1998, held by conference call. Participants Greg Edlund, IBM (chair) Bob Haller, Compaq Bruce Heilbrunn Peter LaFlamme, Fairchild Semiconductor The next meeting is Friday, December 11, 1998 from 11:00 to 12:00 am EST BUSINESS The subcommittee has decided to conduct its business during a one-hour conference call on Fridays opposite the IBIS Open Forum call. Bob Haller reported that the final copy of our DesignCon99 paper, "A Tour of the IBIS Accuracy Specification," was submitted and accepted. List of work to be done: 1. Prepare the test board design files for publication – Greg, 12/31/98 2. Write an example "accuracy trailer" using test board data – Bob, Peter, 12/31/98 3. Finish writing rev 1.0 of the spec – Greg, DesignCon99 4. Write an example "accuracy datasheet" using test board data – Greg, Bob, Peter, DesignCon99 5. Write the "IBIS Accuracy Test Board Application Note" – Greg, Fawn, DesignCon99 6. Write a Perl script to compute figures of merit – Bob, Fawn, DesignCon99 TECHNICAL The subcommittee agrees on the need for some kind of accuracy trailer that would be appended to an IBIS datasheet using comments. In the very least, the accuracy trailer would contain the accuracy figures of merit for various measurements, i.e. the results of applying the correlation metrics. Peter proposed indicating the existence of an accuracy trailer in an IBIS datasheet using the [Source] keyword, which has an open-ended format. Greg favors adding a new IBIS keyword (in the long run) that could be used by EDA vendors to set a flag somewhere in the GUI, indicating to the user that the IBIS datasheet has been lab-verified. In addition to an accuracy trailer, we may also put together an "IBIS Accuracy Datasheet" that contains some of the same information as the trailer but has the potential for more detail, such as simulation vs. lab overlay plots. Examples of both the trailer and the datasheet would be based on data taken from the VCX16244 on the test board. Bruce proposed adding some text to the disclaimer in the accuracy trailer to the effect of, "accuracy does not imply syntactical correctness." If a user does not read the IBIS Accuracy Spec, he or she may have the notion that accuracy and syntactical correctness are one in the same. The subcommittee discussed the idea of amending the spec to include VT tables. This has been suggested by several people as a means for circumventing simulation vs. hardware correlation. We all agreed that we would like to add VT tables to the spec in the future, but we don't have the bandwidth to do it before DesignCon99. VT tables would not replace simulation results; they would be an alternative to simulation results. The IBIS datasheet developer would be free to choose and would be responsible for documenting this choice to the user. Adding VT tables would necessitate a BIRD to allow the three extra test loads called out in the IBIS Accuracy Spec. The subcommittee feels strongly that these loads are necessary for insuring IBIS datasheet accuracy and has data to support this statement. Agenda for the next meeting: Business 1. DesignCon99 paper and booth – 5 min. 2. Opening the conference call to interested parties after DesignCon99 – 5 min. 3. The need for EIA approval of the IBIS Accuracy Specification – 20 min. Technical Review the accuracy trailer line by line. Please read and offer comments before hand. – 30 min. Greg Edlund Advisory Engineer, Critical Net Analysis IBM 3650 Hwy. 52 N, Dept. HDC Rochester, MN 55901 gedlund@us.ibm.com From owner-ibis Wed Dec 9 16:57:39 1998 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id QAA24794 for ; Wed, 9 Dec 1998 16:57:38 -0800 (PST) Received: from em-wv03.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id QAA10951; Wed, 9 Dec 1998 16:52:23 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.8.8/CF5.40R) id QAA01751; Wed, 9 Dec 1998 16:52:21 -0800 (PST) From: bob_ross@mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA18980; Wed, 9 Dec 98 16:52:21 PST Date: Wed, 9 Dec 98 16:52:21 PST Message-Id: <9812100052.AA18980@bob> To: ibis@eda.org Subject: IBIS BIRD57 - Timed Bus Hold Extension To All: BIRD57 is being sent out again since copies received on some systems had extra characters in the text. Bob Ross Mentor Graphics IBIS folks: BIRD57 is issued at the last minute to deal with a real-life "timed latch" implementation situation which could not be modeled with the current Bus_hold model. The proposed resolution is to add a subparameter to the [Submodel Spec] keyword. Because these changes are required to model exisiting devices, it would be very important to incorporate them in version 3.2 of the IBIS spec. Since the changes are relatively minor, it would be desirable to vote on this BIRD on the December 18, 1998 meeting provided no serious technical issues arise. Arpad Muranyi Intel Corporation ****************************************************************************** ****************************************************************************** BIRD ID#: 57 ISSUE TITLE: Timed Bus Hold Extension REQUESTER: Bob Ross, Mentor Graphics, Arpad Muranyi & Stephen Peters, Intel DATE SUBMITTED: December 4, 1998 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: A new application of the bus hold functionality involves turning off (putting in a Hi Z state) the bus hold circuitry after a period of time. The Bus_hold submodel can be extended to support this functionality with the addition of a delay subparameter in the [Submodel Spec] keyword. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The unofficial IBIS Version 3.2 document that includes the BIRD48.4, BIRD49.4 and BIRD50.3 extensions is used as the basis for showing how BIRD57 would be implemented. The original [Submodel Spec] keyword is modified by the addition of a new subparameter called Off_delay. The changes are indicated by an asterisk at the beginning of each line (|*) that it effects. |============================================================================= | Keyword: [Submodel Spec] | Required: No | Description: The [Submodel Spec] keyword defines four columns under which | specification and information subparameters are defined for | submodels. |* Sub-Params: V_trigger_r, V_trigger_f, Off_delay | | Usage Rules: The [Submodel Spec] is to be used only with submodels. | | The following subparameters are used: | V_trigger_r Rising edge trigger voltage | V_trigger_f Falling edge trigger voltage |* Off_delay Turn-off delay from V_trigger_r |* or V_trigger_f |* | For each subparameter contained in the first column, the | remaining three hold its typical, minimum and maximum values. | The entries of typical, minimum and maximum be must be placed | on a single line and must be separated by at least one white | space or tab or tab character. All four columns are required | under the [Submodel Spec] keyword. However, data is required | only in the typical column. If minimum and/or maximum values | are not available, the reserved word "NA" must be used to | indicate the typical value by default. | | The values in the minimum and maximum columns usually | correspond to the values in the same columns for the inherited | top-level voltage range or reference voltages in the top-level |* model. The V_trigger_r and V_trigger_f subparameters |* should hold values in the minimum and maximum columns that |* correspond to the voltage range or reference voltages of the |* top-level model. The Off_delay subparameter, however, is an |* exception to this rule because in some cases it may be |* completely or partially independent from supply voltages |* and/or manufacturing process variations. Therefore the |* minimum and maximum entries for the Off_delay subparameter |* should be ordered simply by their magnitude. | | Unless noted, each [Submodel Spec] subparameter is independent | of any other subparameter. | | V_trigger_r, V_trigger_f rules: | | The voltage trigger values for the rising and falling edges | provide the starting time when an action is initiated. | |* Off_delay rules: |* |* The functionality of the Off_delay subparameter is to provide |* an additional time related mechanism to turn off circuit |* elements. |* |----------------------------------------------------------------------------- | Dynamic Clamp Example: | [Submodel Spec] | Subparameter typ min max | V_trigger_r 3.6 2.9 4.3 | Starts power pulse table V_trigger_f 1.4 1.2 1.6 | Starts gnd pulse table | | Bus Hold Example: | [Submodel Spec] | Subparameter typ min max V_trigger_r 3.1 2.4 3.7 | Starts low to high | bus hold transition V_trigger_f 1.8 1.6 2.0 | Starts high to low | bus hold transition |** New Example added here | | Bus_hold application with pullup structure triggered on and then clocked off: | [Submodel Spec] | Subparameter typ min max V_trigger_r 3.1 2.4 3.7 | Low to high transition | triggers the turn on | process of the pullup V_trigger_f -10.0 -10.0 -10.0 | Not used, so trigger | voltages are set out | of range Off_delay 5n 6n 4n | Time from rising edge | trigger at which the | pullup turned off | |** End of new example The revised Bus Hold Section shows modifications by |* lines to document the new Off_delay subparameter and application information including a new example: |============================================================================= | | Bus Hold: | | When the Submodel_type subparameter under the [Submodel] keyword is set to | Bus_hold, the added model describes the bus hold functionality. However, | while described in terms of bus hold functionality, active terminators | can also be modeled. | | Existing keywords and subparameters are used to describe bus hold models. | The [Pullup] and [Pulldown] tables both are used to define an internal | buffer that is triggered switch to its opposite state. This switching | transition is specified by a [Ramp] keyword or by the [Rising Waveform] | and [Falling Waveform] keywords. The usage rules for these keywords are the | same as under the [Model] keyword. In particular, at least either the | [Pullup] or [Pulldown] keyword is required. Also, the [Ramp] keyword is | required, even if the [Rising Waveform] and [Falling Waveform] tables exist. | However, the voltage ranges and reference voltages are inherited from the | top-level model. | |* For bus hold submodels, the [Submodel Spec] keyword, V_trigger_r, and |* V_trigger_f are required. The Off_delay subparameter is optional, but |* can only be used if the submodel consists of a pullup or a pulldown |* structure only, and not both. Devices which have both pullup and pulldown |* structures controlled in this fashion can be modeled using two submodels, |* one for each half of the circuit. | | The transition is triggered by action at the die using the [Submodel Spec] | V_trigger_r and V_trigger_f subparameters as follows: | | If the starting voltage is below V_trigger_f, then the bus hold model is | set to the low state causing additional pulldown current. If the starting | voltage is above V_trigger_r, the bus hold model is set to the high | state for additional pullup current. When the input passes though | V_trigger_f during a high-to-low transition at the die, the bus hold output | switches to the low state. Similarly, when the input passes though | V_trigger_r during a low-to-high transition at the die, the bus hold output | switches to the high state. | |* If the bus hold submodel has a pullup structure only, V_trigger_r provides |* the time when its pullup is turned on and V_trigger_f or Off_delay provides |* the time when it is turned off, whichever occurs first. Similarly, if the |* submodel has a pulldown structure only, V_trigger_f provides the time when |* its pulldown is turned on and V_trigger_r or Off_delay provides the time |* when it is turned off, whichever occurs first. The required V_trigger_r |* and V_trigger_f voltage entries can be set to values outside of the input |* signal range if the pullup or pulldown structures are to be held on until |* the Off_delay turns them off. |* |* The starting mode for each of submodels which include the Off_delay |* subparameter of the [Submodel Spec] keyword is the off state. Also, while |* two submodels provide the desired operation, either of the submodels may |* exist without the other to model turning on and off only a pullup or a |* pulldown current. |* | No additional keywords are needed for this functionality. |----------------------------------------------------------------------------- | | Complete Bus Hold Model Example: | [Submodel] Bus_hold_1 Submodel_type Bus_hold | [Submodel Spec] | Subparameter typ min max | V_trigger_f 1.3 1.2 1.4 | Falling edge trigger V_trigger_r 3.1 2.6 4.6 | Rising edge trigger | | typ min max | [Voltage Range] 5.0 4.5 5.5 | Note, the actual voltage range and reference voltages are inherited from | the top-level model. | [Pulldown] | -5V -100uA -80uA -120uA -1V -30uA -25uA -40uA 0V 0 0 0 1V 30uA 25uA 40uA 3V 50uA 45uA 50uA 5V 100uA 80uA 120uA 10v 120uA 90uA 150uA | [Pullup] | -5V 100uA 80uA 120uA -1V 30uA 25uA 40uA 0V 0 0 0 1V -30uA -25uA -40uA 3V -50uA -45uA -50uA 5V -100uA -80uA -120uA 10v -120uA -90uA -150uA | |----------------------------------------------------------------------------- | [Ramp] | typ min max dV/dt_r 2.0/0.50n 2.0/0.75n 2.0/0.35n dV/dt_f 2.0/0.50n 2.0/0.75n 2.0/0.35n R_load = 500 | |** A Second Example is inserted below | |----------------------------------------------------------------------------- | | Complete Pullup Timed Latch Example: | [Submodel] Timed_pullup_latch Submodel_type Bus_hold | [Submodel Spec] | Subparameter typ min max | V_trigger_r 3.1 2.6 4.6 | Rising edge trigger | Values could be set out | of range to disable the | trigger V_trigger_f 1.3 1.2 1.4 | Falling edge trigger Off_delay 3n 5n 2n | Delay to turn off the | pullup table | | Note that if the input signal goes above the V_trigger_r value, the | pulldown structure will turn off even if the timer didn't expire yet. | | typ min max | [Voltage Range] 5.0 4.5 5.5 | Note, the actual voltage range and reference voltages are inherited from | the top-level model. | [Pulldown] | -5V -100uA -80uA -120uA -1V -30uA -25uA -40uA 0V 0 0 0 1V 30uA 25uA 40uA 3V 50uA 45uA 50uA 5V 100uA 80uA 120uA 10v 120uA 90uA 150uA | | [Pullup] table is omitted to signal Open_source functionality | |----------------------------------------------------------------------------- | [Ramp] | typ min max dV/dt_r 2.0/0.50n 2.0/0.75n 2.0/0.35n dV/dt_f 2.0/0.50n 2.0/0.75n 2.0/0.35n R_load = 500 | |** End of Second Example |============================================================================= ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: BIRD57 is basically an extension of BIRD50.3. BIRD50.3 describes a static bus hold circuit which is controlled only by the pad voltage of the device. However, some devices can have the bus hold circuits which are turned on by the pad voltage, but are turned off by an internal timer of clock signal. These devices could not be modeled using the BIRD50.3 extensions. BIRD57 provides the extension to model such devices. Several approaches were considered: Modify or Enhance the [Driver Schedule] keyword for Input models (perhaps including a new keyword) Create a new Submodel_type for 'Timed_latch' as a new Submodel extension Enhance the Bus_hold Submodel The first choice builds upon an older approach versus the newer, preferred Submodel approach. The second choice was considered, but in our discussions we would have had to document mew meanings for some transition relationships related to a desired Hi-Z mode. The third choice was selected because the existing Bus Hold description for "Open_drain" or Open_source" functionality could be easily extended. The off state of an Open_* device is equivalent to a Hi-Z mode. Two Submodels are used since the off transition of each of the Submodels can be entered by the [Ramp] information or corresponding [Rising Waveform] or [Falling Waveform] table. A single Submodel is permitted for just turning on and off a pullup or pulldown current. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: BIRD57 evolved from discussions between Bob Ross, Arpad Muranyi, and Stephen Peters on December 3, 1998 to resolve how IBIS Version 3.2 would handle a new active latch that is being implemented in digital buffers. ****************************************************************************** From owner-ibis Wed Dec 9 17:07:02 1998 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id RAA24866 for ; Wed, 9 Dec 1998 17:07:01 -0800 (PST) Received: from em-wv03.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id RAA11661; Wed, 9 Dec 1998 17:01:45 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.8.8/CF5.40R) id RAA03149; Wed, 9 Dec 1998 17:01:42 -0800 (PST) From: bob_ross@mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA18999; Wed, 9 Dec 98 17:01:42 PST Date: Wed, 9 Dec 98 17:01:42 PST Message-Id: <9812100101.AA18999@bob> To: ibis@eda.org Subject: IBIS BIRD57 Example To All: Here is a BIRD57 example provided by Arpad Muranyi in response to a request by Kellee Chrisafulli. Bob Ross Mentor Graphics |************************************************************************** | [IBIS Ver] 3.2 [File name] bird57ex.ibs [File rev] 0.00 [Date] 12/9/98 [Source] From silicon level BOGUS SPICE model. [Notes] The following information uses the features of BIRD57 to describe a FICTICIOUS chip which has an active termintor. | [Disclaimer] This information is only for demonstrating how BIRD57 works and does not represent any real device in production or design. WARNING: THIS MODEL HAS NOT BEEN CHECKED USING IBISCHK3.2 WHICH IS UNDER DEVELOPMENT. IT MAY CONTAIN SYNTAX ERRORS. | [Copyright] None - public sample | |************************************************************************** | [Component] BIRD57ex [Manufacturer] Nobody [Package] | typ min max R_pkg 100.00mOhm NA NA L_pkg 8.00nH NA NA C_pkg 5.00pF NA NA | |************************************************************************** | [Pin] signal_name model_name R_pin L_pin C_pin | 1 Vcc POWER 2 GND GND 3 Data BIRD57ex | |************************************************************************** | [Model] BIRD57ex Model_type I/O_open_sink | Vinl = 800.00mV Vinh = 2.00V Vmeas = 1.50V Cref = 0.00F | | typ min max | C_comp 4.00pF 2.00pF 6.00pF [Voltage Range] 3.300V 3.135V 3.465V [Temperature Range] 50.0 100.0 0.0 | [Add Submodel] | name mode Timed_bushold_up All Timed_bushold_dn Non-Driving | |************************************************************************** | [Pulldown] | | Voltage I(typ) I(min) I(max) | -3.300E+0 -135.779E-6 -78.201E-6 -215.054E-6 -2.305E+0 NA NA -373.363E-6 -1.695E+0 NA NA -652.194E-6 -1.645E+0 -412.464E-6 NA NA -1.585E+0 NA -242.114E-6 NA -1.330E+0 NA NA -1.125E-3 -1.265E+0 -704.974E-6 NA NA -1.185E+0 NA -418.842E-6 NA -1.105E+0 NA NA -1.928E-3 -1.025E+0 -1.197E-3 NA NA -985.000E-3 NA NA -2.960E-3 -935.000E-3 NA -710.934E-6 -3.722E-3 -895.000E-3 NA NA -4.593E-3 -885.000E-3 -1.889E-3 NA NA -860.000E-3 NA NA -5.619E-3 -835.000E-3 -2.324E-3 NA NA -825.000E-3 NA NA -6.938E-3 -785.000E-3 -2.945E-3 -1.129E-3 NA -745.000E-3 -3.635E-3 NA NA -725.000E-3 NA -1.427E-3 NA -715.000E-3 NA NA -12.223E-3 -705.000E-3 -4.542E-3 NA NA -675.000E-3 NA -1.784E-3 NA -665.000E-3 NA NA -14.275E-3 -635.000E-3 NA -2.170E-3 NA -620.000E-3 NA NA -15.455E-3 -595.000E-3 -7.758E-3 -2.669E-3 -15.767E-3 -575.000E-3 NA NA -15.827E-3 -555.000E-3 -8.746E-3 NA NA -545.000E-3 NA NA -15.636E-3 -515.000E-3 -9.385E-3 NA -15.179E-3 -485.000E-3 NA -4.473E-3 NA -475.000E-3 -9.589E-3 NA NA -450.000E-3 -9.490E-3 -4.972E-3 NA -435.000E-3 NA NA -13.263E-3 -425.000E-3 -9.244E-3 NA NA -415.000E-3 NA -5.308E-3 NA -380.000E-3 NA -5.428E-3 NA -365.000E-3 -8.224E-3 NA NA -335.000E-3 NA -5.250E-3 NA -275.000E-3 NA -4.552E-3 NA -205.000E-3 NA -3.447E-3 NA 0.000E+0 -36.769E-9 -27.832E-9 -43.605E-9 275.000E-3 NA 4.434E-3 NA 280.000E-3 6.090E-3 NA NA 295.000E-3 NA NA 8.683E-3 545.000E-3 NA 8.419E-3 NA 555.000E-3 11.579E-3 NA NA 575.000E-3 NA NA 16.241E-3 805.000E-3 NA 11.886E-3 NA 825.000E-3 16.454E-3 NA NA 845.000E-3 NA NA 22.848E-3 1.055E+0 NA 14.847E-3 NA 1.085E+0 20.627E-3 NA NA 1.115E+0 NA NA 28.730E-3 1.305E+0 NA 17.411E-3 NA 1.335E+0 24.114E-3 NA NA 1.375E+0 NA NA 33.648E-3 1.460E+0 25.650E-3 NA NA 1.540E+0 NA 19.424E-3 NA 1.585E+0 27.038E-3 NA NA 1.625E+0 NA NA 37.623E-3 1.660E+0 NA 20.293E-3 NA 1.705E+0 28.226E-3 NA NA 1.770E+0 NA 20.988E-3 NA 1.825E+0 29.265E-3 NA NA 1.870E+0 NA NA 40.731E-3 1.885E+0 NA 21.607E-3 NA 1.940E+0 30.114E-3 NA NA 1.990E+0 NA NA 41.945E-3 1.995E+0 NA 22.090E-3 NA 2.055E+0 30.813E-3 NA NA 2.105E+0 NA NA 42.907E-3 2.115E+0 NA 22.492E-3 NA 2.175E+0 31.374E-3 NA NA 2.225E+0 NA NA 43.690E-3 2.230E+0 NA 22.749E-3 NA 2.290E+0 31.745E-3 NA NA 2.340E+0 NA NA 44.220E-3 2.515E+0 NA 22.969E-3 NA 2.560E+0 32.064E-3 NA NA 2.595E+0 NA NA 44.680E-3 3.155E+0 NA 23.186E-3 NA 3.225E+0 32.378E-3 NA NA 3.285E+0 NA NA 45.136E-3 4.790E+0 NA 23.480E-3 NA 4.860E+0 32.773E-3 NA NA 4.920E+0 NA NA 45.670E-3 5.415E+0 NA 23.791E-3 NA 5.470E+0 33.180E-3 NA NA 5.520E+0 NA NA 46.211E-3 5.730E+0 NA 24.093E-3 NA 5.770E+0 33.561E-3 NA NA 6.030E+0 NA 24.500E-3 NA 6.060E+0 34.082E-3 NA NA 6.080E+0 NA NA 47.348E-3 6.320E+0 NA 25.024E-3 NA 6.330E+0 34.721E-3 NA NA 6.340E+0 NA NA 48.160E-3 6.600E+0 35.525E-3 25.661E-3 49.177E-3 | [GND Clamp] | | Voltage I(typ) I(min) I(max) | -3.300E+0 -1.100E+0 -859.817E-3 -1.350E+0 -3.240E+0 -1.052E+0 NA NA -3.205E+0 NA NA -1.299E+0 -2.940E+0 NA -750.074E-3 NA -2.890E+0 -910.765E-3 NA NA -2.855E+0 NA NA -1.117E+0 -2.630E+0 NA -653.094E-3 NA -2.575E+0 -784.216E-3 NA NA -2.535E+0 NA NA -950.607E-3 -2.345E+0 NA -564.175E-3 NA -2.285E+0 -668.035E-3 NA NA -2.255E+0 NA NA -805.762E-3 -2.085E+0 NA -483.326E-3 NA -2.025E+0 -564.238E-3 NA NA -1.995E+0 NA NA -671.727E-3 -1.855E+0 NA -412.096E-3 NA -1.795E+0 -472.819E-3 NA NA -1.775E+0 NA NA -558.811E-3 -1.645E+0 NA -347.388E-3 NA -1.595E+0 -393.759E-3 NA NA -1.585E+0 NA NA -461.823E-3 -1.460E+0 NA -290.746E-3 NA -1.420E+0 -325.058E-3 NA NA -1.415E+0 NA NA -375.657E-3 -1.295E+0 NA -240.633E-3 NA -1.265E+0 -264.751E-3 NA -300.350E-3 -1.155E+0 NA -198.544E-3 NA -1.135E+0 -214.752E-3 NA -235.933E-3 -1.075E+0 -191.926E-3 NA NA -1.025E+0 NA -159.979E-3 -182.402E-3 -1.015E+0 -169.311E-3 NA NA -975.000E-3 NA NA -158.513E-3 -965.000E-3 -150.665E-3 NA NA -935.000E-3 NA NA -139.678E-3 -915.000E-3 -132.247E-3 -127.924E-3 NA -895.000E-3 NA NA -121.157E-3 -865.000E-3 -114.119E-3 -113.600E-3 NA -855.000E-3 NA NA -103.038E-3 -825.000E-3 -99.880E-3 NA NA -815.000E-3 NA -99.481E-3 NA -805.000E-3 NA NA -81.154E-3 -785.000E-3 NA NA -72.712E-3 -765.000E-3 -79.107E-3 NA NA -760.000E-3 NA NA -62.488E-3 -745.000E-3 NA -80.163E-3 NA -740.000E-3 NA NA -54.614E-3 -720.000E-3 NA NA -47.072E-3 -715.000E-3 -62.534E-3 NA NA -705.000E-3 NA NA -41.661E-3 -690.000E-3 -54.591E-3 NA NA -685.000E-3 NA -64.176E-3 -34.852E-3 -670.000E-3 NA NA -30.096E-3 -665.000E-3 -46.929E-3 NA NA -655.000E-3 NA NA -25.650E-3 -645.000E-3 -41.049E-3 NA NA -640.000E-3 NA NA -21.592E-3 -635.000E-3 NA -51.419E-3 NA -625.000E-3 -35.427E-3 NA -17.903E-3 -610.000E-3 NA -45.297E-3 -14.661E-3 -605.000E-3 -30.104E-3 NA NA -595.000E-3 NA NA -11.819E-3 -585.000E-3 -25.126E-3 -39.381E-3 NA -580.000E-3 NA NA -9.431E-3 -570.000E-3 -21.657E-3 NA NA -565.000E-3 NA -34.827E-3 -7.422E-3 -555.000E-3 -18.413E-3 NA NA -550.000E-3 NA NA -5.807E-3 -540.000E-3 NA -29.397E-3 NA -535.000E-3 -14.508E-3 NA -4.490E-3 -520.000E-3 -11.916E-3 -25.290E-3 NA -505.000E-3 -9.599E-3 NA -2.630E-3 -500.000E-3 NA -21.427E-3 NA -485.000E-3 -6.989E-3 -18.702E-3 NA -465.000E-3 NA -15.338E-3 -1.179E-3 -460.000E-3 -4.469E-3 NA NA -445.000E-3 NA -12.299E-3 NA -435.000E-3 -2.676E-3 NA NA -425.000E-3 NA -9.610E-3 -425.535E-6 -410.000E-3 NA -7.842E-3 NA -405.000E-3 -1.332E-3 NA NA -395.000E-3 NA -6.271E-3 NA -380.000E-3 NA -4.928E-3 NA -370.000E-3 -529.224E-6 NA NA -365.000E-3 NA -3.781E-3 NA -345.000E-3 NA NA -31.664E-6 -335.000E-3 -193.356E-6 -2.093E-3 NA -315.000E-3 NA -1.349E-3 NA -300.000E-3 NA -955.909E-6 NA -285.000E-3 -44.465E-6 NA NA -265.000E-3 NA -401.901E-6 NA -215.000E-3 NA -109.348E-6 NA 0.000E+0 -4.610E-9 -53.490E-9 -311.711E-12 3.300E+0 0.000E+0 0.000E+0 0.000E+0 | [POWER Clamp] | | Voltage I(typ) I(min) I(max) | -3.300E+0 370.000E-3 287.513E-3 500.000E-3 -3.230E+0 365.079E-3 NA NA -3.210E+0 NA NA 472.883E-3 -2.915E+0 NA 247.047E-3 NA -2.885E+0 312.533E-3 NA NA -2.865E+0 NA NA 402.672E-3 -2.605E+0 NA 211.302E-3 NA -2.575E+0 265.439E-3 NA NA -2.555E+0 NA NA 339.734E-3 -2.325E+0 NA 179.121E-3 NA -2.295E+0 223.037E-3 NA NA -2.285E+0 NA NA 285.078E-3 -2.075E+0 NA 150.505E-3 NA -2.045E+0 185.330E-3 NA NA -2.035E+0 NA NA 234.661E-3 -1.855E+0 NA 125.449E-3 NA -1.825E+0 152.317E-3 NA 192.515E-3 -1.655E+0 NA 102.819E-3 NA -1.635E+0 123.992E-3 NA 154.621E-3 -1.485E+0 NA 83.743E-3 NA -1.475E+0 NA NA 122.974E-3 -1.470E+0 99.602E-3 NA NA -1.335E+0 NA 67.091E-3 95.592E-3 -1.325E+0 78.410E-3 NA NA -1.275E+0 NA NA 83.986E-3 -1.260E+0 69.016E-3 NA NA -1.215E+0 NA NA 72.488E-3 -1.205E+0 NA 52.865E-3 NA -1.200E+0 60.423E-3 NA NA -1.165E+0 NA NA 63.013E-3 -1.145E+0 52.632E-3 46.392E-3 NA -1.115E+0 NA NA 53.663E-3 -1.095E+0 45.638E-3 41.057E-3 NA -1.075E+0 NA NA 46.301E-3 -1.045E+0 38.756E-3 35.791E-3 NA -1.035E+0 NA NA 39.077E-3 -1.005E+0 33.354E-3 NA NA -995.000E-3 NA 30.612E-3 32.037E-3 -965.000E-3 28.072E-3 NA 26.918E-3 -955.000E-3 NA 26.549E-3 NA -945.000E-3 NA NA 23.605E-3 -935.000E-3 24.212E-3 NA NA -925.000E-3 NA NA 20.393E-3 -915.000E-3 NA 22.576E-3 NA -895.000E-3 19.246E-3 NA 15.813E-3 -880.000E-3 NA NA 13.664E-3 -875.000E-3 16.862E-3 NA NA -865.000E-3 NA 17.780E-3 11.622E-3 -855.000E-3 14.562E-3 NA 10.336E-3 -840.000E-3 NA NA 8.543E-3 -835.000E-3 12.363E-3 NA NA -825.000E-3 NA NA 6.915E-3 -820.000E-3 10.796E-3 13.689E-3 NA -815.000E-3 NA NA 5.946E-3 -805.000E-3 9.305E-3 NA 5.073E-3 -800.000E-3 NA 11.961E-3 NA -795.000E-3 NA NA 4.301E-3 -790.000E-3 7.912E-3 NA NA -785.000E-3 NA NA 3.633E-3 -780.000E-3 NA 10.305E-3 NA -775.000E-3 6.621E-3 NA NA -770.000E-3 NA NA 2.828E-3 -765.000E-3 5.829E-3 9.116E-3 NA -755.000E-3 NA NA 2.214E-3 -750.000E-3 4.757E-3 NA NA -745.000E-3 NA 7.618E-3 1.908E-3 -735.000E-3 3.820E-3 NA NA -730.000E-3 NA 6.571E-3 NA -725.000E-3 3.282E-3 NA NA -715.000E-3 NA 5.589E-3 1.322E-3 -710.000E-3 2.604E-3 NA NA -700.000E-3 NA 4.690E-3 NA -695.000E-3 2.060E-3 NA NA -685.000E-3 1.771E-3 3.875E-3 NA -670.000E-3 NA 3.160E-3 NA -665.000E-3 NA NA 868.892E-6 -655.000E-3 1.132E-3 2.538E-3 NA -640.000E-3 NA 2.021E-3 NA -625.000E-3 762.378E-6 1.592E-3 NA -610.000E-3 NA 1.253E-3 NA -595.000E-3 NA 983.264E-6 462.220E-6 -575.000E-3 429.363E-6 NA NA -565.000E-3 NA 616.510E-6 NA -525.000E-3 NA 346.388E-6 NA -515.000E-3 217.165E-6 NA 181.831E-6 -480.000E-3 NA 189.345E-6 NA -415.000E-3 NA 76.864E-6 NA -385.000E-3 NA NA 14.929E-6 -365.000E-3 19.178E-6 NA NA -335.000E-3 NA 20.501E-6 NA 0.000E+0 34.247E-9 1.119E-6 2.144E-9 3.300E+0 0.000E+0 0.000E+0 0.000E+0 | |************************************************************************** | [Ramp] R_load = 50.00Ohm | typ min max | dV/dt_r 540.04mV/1.04ns 411.75mV/1.47ns 698.42mV/705.58ps dV/dt_f 879.96mV/936.61ps 666.10mV/1.42ns 1.12V/623.48ps | |************************************************************************** | [Falling Waveform] V_fixture = 3.300V V_fixture_min = 3.135V V_fixture_max = 3.465V R_fixture = 50.00Ohm | | Time V(typ) V(min) V(max) | 0.000E+0 3.300E+0 3.135E+0 3.465E+0 273.437E-12 NA NA 3.463E+0 304.687E-12 NA NA 3.471E+0 380.000E-12 3.299E+0 NA NA 390.625E-12 NA NA 3.509E+0 420.000E-12 3.306E+0 NA NA 476.563E-12 NA NA 3.519E+0 512.000E-12 NA 3.134E+0 NA 540.000E-12 3.338E+0 NA NA 576.000E-12 NA 3.140E+0 NA 593.750E-12 NA NA 3.518E+0 670.000E-12 3.346E+0 NA NA 671.875E-12 NA NA 3.504E+0 695.313E-12 NA NA 3.481E+0 718.750E-12 NA NA 3.440E+0 729.600E-12 NA 3.166E+0 NA 765.625E-12 NA NA 3.336E+0 820.312E-12 NA NA 3.203E+0 851.562E-12 NA NA 3.121E+0 870.000E-12 3.342E+0 NA NA 896.000E-12 NA 3.174E+0 NA 898.437E-12 NA NA 2.986E+0 940.000E-12 3.335E+0 NA NA 970.000E-12 3.324E+0 NA NA 1.000E-9 3.303E+0 NA NA 1.023E-9 NA NA 2.609E+0 1.040E-9 3.262E+0 NA NA 1.062E-9 NA NA 2.504E+0 1.109E-9 NA NA 2.398E+0 1.110E-9 3.176E+0 NA NA 1.164E-9 NA NA 2.300E+0 1.165E-9 NA 3.171E+0 NA 1.180E-9 3.084E+0 NA NA 1.234E-9 NA NA 2.198E+0 1.270E-9 2.952E+0 NA NA 1.293E-9 NA 3.163E+0 NA 1.312E-9 NA NA 2.105E+0 1.331E-9 NA 3.157E+0 NA 1.359E-9 NA NA 2.057E+0 1.370E-9 NA 3.145E+0 NA 1.406E-9 NA NA 2.016E+0 1.434E-9 NA 3.114E+0 NA 1.445E-9 NA NA 1.993E+0 1.450E-9 2.666E+0 NA NA 1.498E-9 NA 3.075E+0 NA 1.520E-9 2.566E+0 NA NA 1.578E-9 NA NA 1.941E+0 1.600E-9 2.473E+0 NA NA 1.626E-9 NA 2.990E+0 NA 1.680E-9 2.400E+0 NA NA 1.734E-9 NA NA 1.908E+0 1.754E-9 NA 2.896E+0 NA 1.780E-9 2.326E+0 NA NA 1.880E-9 2.264E+0 NA NA 1.945E-9 NA NA 1.878E+0 2.000E-9 2.201E+0 NA NA 2.022E-9 NA 2.673E+0 NA 2.086E-9 NA 2.623E+0 NA 2.120E-9 2.147E+0 NA NA 2.148E-9 NA NA 1.808E+0 2.150E-9 NA 2.578E+0 NA 2.214E-9 NA 2.539E+0 NA 2.220E-9 2.109E+0 NA NA 2.273E-9 NA NA 1.780E+0 2.278E-9 NA 2.505E+0 NA 2.300E-9 2.086E+0 NA NA 2.406E-9 NA 2.448E+0 NA 2.420E-9 2.063E+0 NA NA 2.445E-9 NA NA 1.751E+0 2.534E-9 NA 2.402E+0 NA 2.540E-9 2.047E+0 NA NA 2.675E-9 NA 2.358E+0 NA 2.780E-9 2.024E+0 NA NA 2.854E-9 NA 2.311E+0 NA 2.859E-9 NA NA 1.702E+0 3.046E-9 NA 2.267E+0 NA 3.180E-9 2.001E+0 NA NA 3.238E-9 NA 2.231E+0 NA 3.398E-9 NA NA 1.664E+0 3.430E-9 NA 2.200E+0 NA 3.520E-9 1.958E+0 NA NA 3.584E-9 NA 2.180E+0 NA 3.750E-9 NA 2.163E+0 NA 3.960E-9 1.926E+0 NA NA 4.070E-9 NA NA 1.636E+0 4.198E-9 NA 2.138E+0 NA 4.680E-9 1.893E+0 NA NA 4.941E-9 NA 2.117E+0 NA 4.945E-9 NA NA 1.618E+0 5.542E-9 NA 2.092E+0 NA 5.560E-9 1.869E+0 NA NA 6.182E-9 NA 2.075E+0 NA 6.750E-9 1.851E+0 NA NA 7.014E-9 NA 2.060E+0 NA 7.484E-9 NA NA 1.602E+0 8.102E-9 NA 2.047E+0 NA 8.300E-9 1.839E+0 NA NA 9.382E-9 NA 2.037E+0 NA 9.990E-9 1.833E+0 NA NA 12.800E-9 1.833E+0 2.025E+0 1.601E+0 | [Rising Waveform] V_fixture = 3.300V V_fixture_min = 3.135V V_fixture_max = 3.465V R_fixture = 50.00Ohm | | Time V(typ) V(min) V(max) | 0.000E+0 1.833E+0 2.025E+0 1.601E+0 273.437E-12 NA NA 1.602E+0 351.563E-12 NA NA 1.597E+0 370.000E-12 1.834E+0 NA NA 390.625E-12 NA NA 1.606E+0 414.062E-12 NA NA 1.627E+0 429.687E-12 NA NA 1.654E+0 437.500E-12 NA NA 1.675E+0 445.312E-12 NA NA 1.704E+0 460.937E-12 NA NA 1.799E+0 468.750E-12 NA NA 1.861E+0 476.563E-12 NA NA 1.931E+0 490.000E-12 1.830E+0 NA NA 499.200E-12 NA 2.026E+0 NA 507.813E-12 NA NA 2.215E+0 523.438E-12 NA NA 2.342E+0 531.250E-12 NA NA 2.399E+0 540.000E-12 1.838E+0 NA NA 546.875E-12 NA NA 2.501E+0 554.688E-12 NA NA 2.548E+0 560.000E-12 1.846E+0 NA NA 570.313E-12 NA NA 2.629E+0 580.000E-12 1.860E+0 NA NA 593.750E-12 NA NA 2.731E+0 600.000E-12 1.882E+0 NA NA 610.000E-12 1.898E+0 NA NA 617.188E-12 NA NA 2.812E+0 620.000E-12 1.920E+0 NA NA 630.000E-12 1.947E+0 NA NA 640.000E-12 1.983E+0 NA NA 660.000E-12 2.075E+0 NA NA 678.400E-12 NA 2.022E+0 NA 679.688E-12 NA NA 2.981E+0 710.000E-12 2.339E+0 NA NA 710.938E-12 NA NA 3.054E+0 729.600E-12 NA 2.026E+0 NA 730.000E-12 2.436E+0 NA NA 740.000E-12 2.480E+0 NA NA 750.000E-12 NA NA 3.127E+0 755.200E-12 NA 2.031E+0 NA 760.000E-12 2.559E+0 NA NA 770.000E-12 2.594E+0 NA NA 780.800E-12 NA 2.039E+0 NA 790.000E-12 2.658E+0 NA NA 796.875E-12 NA NA 3.193E+0 806.400E-12 NA 2.051E+0 NA 820.000E-12 2.737E+0 NA NA 832.000E-12 NA 2.069E+0 NA 843.750E-12 NA NA 3.243E+0 844.800E-12 NA 2.082E+0 NA 850.000E-12 2.802E+0 NA NA 857.600E-12 NA 2.098E+0 NA 870.000E-12 2.839E+0 NA NA 883.200E-12 NA 2.145E+0 NA 898.437E-12 NA NA 3.286E+0 908.800E-12 NA 2.212E+0 NA 921.600E-12 NA 2.250E+0 NA 945.312E-12 NA NA 3.314E+0 950.000E-12 2.950E+0 NA NA 972.800E-12 NA 2.411E+0 NA 992.187E-12 NA NA 3.335E+0 1.000E-9 3.009E+0 NA NA 1.011E-9 NA 2.521E+0 NA 1.037E-9 NA 2.584E+0 NA 1.050E-9 3.058E+0 NA NA 1.062E-9 NA 2.638E+0 NA 1.088E-9 NA 2.686E+0 NA 1.094E-9 NA NA 3.371E+0 1.110E-9 3.102E+0 NA NA 1.126E-9 NA 2.743E+0 NA 1.152E-9 NA 2.776E+0 NA 1.180E-9 3.140E+0 NA NA 1.195E-9 NA NA 3.412E+0 1.203E-9 NA 2.827E+0 NA 1.250E-9 NA NA 3.424E+0 1.280E-9 3.178E+0 NA NA 1.293E-9 NA 2.890E+0 NA 1.382E-9 NA 2.942E+0 NA 1.445E-9 NA NA 3.442E+0 1.446E-9 NA 2.973E+0 NA 1.450E-9 3.225E+0 NA NA 1.510E-9 NA 2.997E+0 NA 1.550E-9 3.249E+0 NA NA 1.600E-9 NA 3.023E+0 NA 1.620E-9 3.260E+0 NA NA 1.695E-9 NA NA 3.453E+0 1.766E-9 NA 3.059E+0 NA 1.840E-9 3.275E+0 NA NA 1.920E-9 NA 3.084E+0 NA 2.022E-9 NA 3.096E+0 NA 2.220E-9 3.287E+0 NA NA 2.278E-9 NA 3.109E+0 NA 2.523E-9 NA NA 3.463E+0 2.670E-9 3.294E+0 NA NA 2.726E-9 NA 3.120E+0 NA 3.280E-9 3.298E+0 NA NA 3.302E-9 NA 3.127E+0 NA 4.070E-9 NA 3.132E+0 NA 6.054E-9 NA 3.135E+0 NA 12.800E-9 3.300E+0 3.135E+0 3.465E+0 | |************************************************************************** | [Submodel] Timed_bushold_dn Submodel_type Bus_hold [Submodel Spec] | | typ min max V_trigger_r 15.00 15.00 15.00 V_trigger_f 1.65 1.50 1.80 Off_delay 5.00ns 3.00ns 7.00ns | |************************************************************************** | [Pulldown] | | Voltage I(typ) I(min) I(max) | -3.300E+0 -135.779E-6 -78.201E-6 -215.054E-6 -2.305E+0 NA NA -373.363E-6 -1.695E+0 NA NA -652.194E-6 -1.645E+0 -412.464E-6 NA NA -1.585E+0 NA -242.114E-6 NA -1.330E+0 NA NA -1.125E-3 -1.265E+0 -704.974E-6 NA NA -1.185E+0 NA -418.842E-6 NA -1.105E+0 NA NA -1.928E-3 -1.025E+0 -1.197E-3 NA NA -985.000E-3 NA NA -2.960E-3 -935.000E-3 NA -710.934E-6 -3.722E-3 -895.000E-3 NA NA -4.593E-3 -885.000E-3 -1.889E-3 NA NA -860.000E-3 NA NA -5.619E-3 -835.000E-3 -2.324E-3 NA NA -825.000E-3 NA NA -6.938E-3 -785.000E-3 -2.945E-3 -1.129E-3 NA -745.000E-3 -3.635E-3 NA NA -725.000E-3 NA -1.427E-3 NA -715.000E-3 NA NA -12.223E-3 -705.000E-3 -4.542E-3 NA NA -675.000E-3 NA -1.784E-3 NA -665.000E-3 NA NA -14.275E-3 -635.000E-3 NA -2.170E-3 NA -620.000E-3 NA NA -15.455E-3 -595.000E-3 -7.758E-3 -2.669E-3 -15.767E-3 -575.000E-3 NA NA -15.827E-3 -555.000E-3 -8.746E-3 NA NA -545.000E-3 NA NA -15.636E-3 -515.000E-3 -9.385E-3 NA -15.179E-3 -485.000E-3 NA -4.473E-3 NA -475.000E-3 -9.589E-3 NA NA -450.000E-3 -9.490E-3 -4.972E-3 NA -435.000E-3 NA NA -13.263E-3 -425.000E-3 -9.244E-3 NA NA -415.000E-3 NA -5.308E-3 NA -380.000E-3 NA -5.428E-3 NA -365.000E-3 -8.224E-3 NA NA -335.000E-3 NA -5.250E-3 NA -275.000E-3 NA -4.552E-3 NA -205.000E-3 NA -3.447E-3 NA 0.000E+0 -36.769E-9 -27.832E-9 -43.605E-9 275.000E-3 NA 4.434E-3 NA 280.000E-3 6.090E-3 NA NA 295.000E-3 NA NA 8.683E-3 545.000E-3 NA 8.419E-3 NA 555.000E-3 11.579E-3 NA NA 575.000E-3 NA NA 16.241E-3 805.000E-3 NA 11.886E-3 NA 825.000E-3 16.454E-3 NA NA 845.000E-3 NA NA 22.848E-3 1.055E+0 NA 14.847E-3 NA 1.085E+0 20.627E-3 NA NA 1.115E+0 NA NA 28.730E-3 1.305E+0 NA 17.411E-3 NA 1.335E+0 24.114E-3 NA NA 1.375E+0 NA NA 33.648E-3 1.460E+0 25.650E-3 NA NA 1.540E+0 NA 19.424E-3 NA 1.585E+0 27.038E-3 NA NA 1.625E+0 NA NA 37.623E-3 1.660E+0 NA 20.293E-3 NA 1.705E+0 28.226E-3 NA NA 1.770E+0 NA 20.988E-3 NA 1.825E+0 29.265E-3 NA NA 1.870E+0 NA NA 40.731E-3 1.885E+0 NA 21.607E-3 NA 1.940E+0 30.114E-3 NA NA 1.990E+0 NA NA 41.945E-3 1.995E+0 NA 22.090E-3 NA 2.055E+0 30.813E-3 NA NA 2.105E+0 NA NA 42.907E-3 2.115E+0 NA 22.492E-3 NA 2.175E+0 31.374E-3 NA NA 2.225E+0 NA NA 43.690E-3 2.230E+0 NA 22.749E-3 NA 2.290E+0 31.745E-3 NA NA 2.340E+0 NA NA 44.220E-3 2.515E+0 NA 22.969E-3 NA 2.560E+0 32.064E-3 NA NA 2.595E+0 NA NA 44.680E-3 3.155E+0 NA 23.186E-3 NA 3.225E+0 32.378E-3 NA NA 3.285E+0 NA NA 45.136E-3 4.790E+0 NA 23.480E-3 NA 4.860E+0 32.773E-3 NA NA 4.920E+0 NA NA 45.670E-3 5.415E+0 NA 23.791E-3 NA 5.470E+0 33.180E-3 NA NA 5.520E+0 NA NA 46.211E-3 5.730E+0 NA 24.093E-3 NA 5.770E+0 33.561E-3 NA NA 6.030E+0 NA 24.500E-3 NA 6.060E+0 34.082E-3 NA NA 6.080E+0 NA NA 47.348E-3 6.320E+0 NA 25.024E-3 NA 6.330E+0 34.721E-3 NA NA 6.340E+0 NA NA 48.160E-3 6.600E+0 35.525E-3 25.661E-3 49.177E-3 | |************************************************************************** | [Ramp] R_load = 50.00Ohm | typ min max | dV/dt_r 540.04mV/1.04ns 411.75mV/1.47ns 698.42mV/705.58ps dV/dt_f 879.96mV/936.61ps 666.10mV/1.42ns 1.12V/623.48ps | |************************************************************************** | [Falling Waveform] V_fixture = 3.300V V_fixture_min = 3.135V V_fixture_max = 3.465V R_fixture = 50.00Ohm | | Time V(typ) V(min) V(max) | 0.000E+0 3.300E+0 3.135E+0 3.465E+0 273.437E-12 NA NA 3.463E+0 304.687E-12 NA NA 3.471E+0 380.000E-12 3.299E+0 NA NA 390.625E-12 NA NA 3.509E+0 420.000E-12 3.306E+0 NA NA 476.563E-12 NA NA 3.519E+0 512.000E-12 NA 3.134E+0 NA 540.000E-12 3.338E+0 NA NA 576.000E-12 NA 3.140E+0 NA 593.750E-12 NA NA 3.518E+0 670.000E-12 3.346E+0 NA NA 671.875E-12 NA NA 3.504E+0 695.313E-12 NA NA 3.481E+0 718.750E-12 NA NA 3.440E+0 729.600E-12 NA 3.166E+0 NA 765.625E-12 NA NA 3.336E+0 820.312E-12 NA NA 3.203E+0 851.562E-12 NA NA 3.121E+0 870.000E-12 3.342E+0 NA NA 896.000E-12 NA 3.174E+0 NA 898.437E-12 NA NA 2.986E+0 940.000E-12 3.335E+0 NA NA 970.000E-12 3.324E+0 NA NA 1.000E-9 3.303E+0 NA NA 1.023E-9 NA NA 2.609E+0 1.040E-9 3.262E+0 NA NA 1.062E-9 NA NA 2.504E+0 1.109E-9 NA NA 2.398E+0 1.110E-9 3.176E+0 NA NA 1.164E-9 NA NA 2.300E+0 1.165E-9 NA 3.171E+0 NA 1.180E-9 3.084E+0 NA NA 1.234E-9 NA NA 2.198E+0 1.270E-9 2.952E+0 NA NA 1.293E-9 NA 3.163E+0 NA 1.312E-9 NA NA 2.105E+0 1.331E-9 NA 3.157E+0 NA 1.359E-9 NA NA 2.057E+0 1.370E-9 NA 3.145E+0 NA 1.406E-9 NA NA 2.016E+0 1.434E-9 NA 3.114E+0 NA 1.445E-9 NA NA 1.993E+0 1.450E-9 2.666E+0 NA NA 1.498E-9 NA 3.075E+0 NA 1.520E-9 2.566E+0 NA NA 1.578E-9 NA NA 1.941E+0 1.600E-9 2.473E+0 NA NA 1.626E-9 NA 2.990E+0 NA 1.680E-9 2.400E+0 NA NA 1.734E-9 NA NA 1.908E+0 1.754E-9 NA 2.896E+0 NA 1.780E-9 2.326E+0 NA NA 1.880E-9 2.264E+0 NA NA 1.945E-9 NA NA 1.878E+0 2.000E-9 2.201E+0 NA NA 2.022E-9 NA 2.673E+0 NA 2.086E-9 NA 2.623E+0 NA 2.120E-9 2.147E+0 NA NA 2.148E-9 NA NA 1.808E+0 2.150E-9 NA 2.578E+0 NA 2.214E-9 NA 2.539E+0 NA 2.220E-9 2.109E+0 NA NA 2.273E-9 NA NA 1.780E+0 2.278E-9 NA 2.505E+0 NA 2.300E-9 2.086E+0 NA NA 2.406E-9 NA 2.448E+0 NA 2.420E-9 2.063E+0 NA NA 2.445E-9 NA NA 1.751E+0 2.534E-9 NA 2.402E+0 NA 2.540E-9 2.047E+0 NA NA 2.675E-9 NA 2.358E+0 NA 2.780E-9 2.024E+0 NA NA 2.854E-9 NA 2.311E+0 NA 2.859E-9 NA NA 1.702E+0 3.046E-9 NA 2.267E+0 NA 3.180E-9 2.001E+0 NA NA 3.238E-9 NA 2.231E+0 NA 3.398E-9 NA NA 1.664E+0 3.430E-9 NA 2.200E+0 NA 3.520E-9 1.958E+0 NA NA 3.584E-9 NA 2.180E+0 NA 3.750E-9 NA 2.163E+0 NA 3.960E-9 1.926E+0 NA NA 4.070E-9 NA NA 1.636E+0 4.198E-9 NA 2.138E+0 NA 4.680E-9 1.893E+0 NA NA 4.941E-9 NA 2.117E+0 NA 4.945E-9 NA NA 1.618E+0 5.542E-9 NA 2.092E+0 NA 5.560E-9 1.869E+0 NA NA 6.182E-9 NA 2.075E+0 NA 6.750E-9 1.851E+0 NA NA 7.014E-9 NA 2.060E+0 NA 7.484E-9 NA NA 1.602E+0 8.102E-9 NA 2.047E+0 NA 8.300E-9 1.839E+0 NA NA 9.382E-9 NA 2.037E+0 NA 9.990E-9 1.833E+0 NA NA 12.800E-9 1.833E+0 2.025E+0 1.601E+0 | [Rising Waveform] V_fixture = 3.300V V_fixture_min = 3.135V V_fixture_max = 3.465V R_fixture = 50.00Ohm | | Time V(typ) V(min) V(max) | 0.000E+0 1.833E+0 2.025E+0 1.601E+0 273.437E-12 NA NA 1.602E+0 351.563E-12 NA NA 1.597E+0 370.000E-12 1.834E+0 NA NA 390.625E-12 NA NA 1.606E+0 414.062E-12 NA NA 1.627E+0 429.687E-12 NA NA 1.654E+0 437.500E-12 NA NA 1.675E+0 445.312E-12 NA NA 1.704E+0 460.937E-12 NA NA 1.799E+0 468.750E-12 NA NA 1.861E+0 476.563E-12 NA NA 1.931E+0 490.000E-12 1.830E+0 NA NA 499.200E-12 NA 2.026E+0 NA 507.813E-12 NA NA 2.215E+0 523.438E-12 NA NA 2.342E+0 531.250E-12 NA NA 2.399E+0 540.000E-12 1.838E+0 NA NA 546.875E-12 NA NA 2.501E+0 554.688E-12 NA NA 2.548E+0 560.000E-12 1.846E+0 NA NA 570.313E-12 NA NA 2.629E+0 580.000E-12 1.860E+0 NA NA 593.750E-12 NA NA 2.731E+0 600.000E-12 1.882E+0 NA NA 610.000E-12 1.898E+0 NA NA 617.188E-12 NA NA 2.812E+0 620.000E-12 1.920E+0 NA NA 630.000E-12 1.947E+0 NA NA 640.000E-12 1.983E+0 NA NA 660.000E-12 2.075E+0 NA NA 678.400E-12 NA 2.022E+0 NA 679.688E-12 NA NA 2.981E+0 710.000E-12 2.339E+0 NA NA 710.938E-12 NA NA 3.054E+0 729.600E-12 NA 2.026E+0 NA 730.000E-12 2.436E+0 NA NA 740.000E-12 2.480E+0 NA NA 750.000E-12 NA NA 3.127E+0 755.200E-12 NA 2.031E+0 NA 760.000E-12 2.559E+0 NA NA 770.000E-12 2.594E+0 NA NA 780.800E-12 NA 2.039E+0 NA 790.000E-12 2.658E+0 NA NA 796.875E-12 NA NA 3.193E+0 806.400E-12 NA 2.051E+0 NA 820.000E-12 2.737E+0 NA NA 832.000E-12 NA 2.069E+0 NA 843.750E-12 NA NA 3.243E+0 844.800E-12 NA 2.082E+0 NA 850.000E-12 2.802E+0 NA NA 857.600E-12 NA 2.098E+0 NA 870.000E-12 2.839E+0 NA NA 883.200E-12 NA 2.145E+0 NA 898.437E-12 NA NA 3.286E+0 908.800E-12 NA 2.212E+0 NA 921.600E-12 NA 2.250E+0 NA 945.312E-12 NA NA 3.314E+0 950.000E-12 2.950E+0 NA NA 972.800E-12 NA 2.411E+0 NA 992.187E-12 NA NA 3.335E+0 1.000E-9 3.009E+0 NA NA 1.011E-9 NA 2.521E+0 NA 1.037E-9 NA 2.584E+0 NA 1.050E-9 3.058E+0 NA NA 1.062E-9 NA 2.638E+0 NA 1.088E-9 NA 2.686E+0 NA 1.094E-9 NA NA 3.371E+0 1.110E-9 3.102E+0 NA NA 1.126E-9 NA 2.743E+0 NA 1.152E-9 NA 2.776E+0 NA 1.180E-9 3.140E+0 NA NA 1.195E-9 NA NA 3.412E+0 1.203E-9 NA 2.827E+0 NA 1.250E-9 NA NA 3.424E+0 1.280E-9 3.178E+0 NA NA 1.293E-9 NA 2.890E+0 NA 1.382E-9 NA 2.942E+0 NA 1.445E-9 NA NA 3.442E+0 1.446E-9 NA 2.973E+0 NA 1.450E-9 3.225E+0 NA NA 1.510E-9 NA 2.997E+0 NA 1.550E-9 3.249E+0 NA NA 1.600E-9 NA 3.023E+0 NA 1.620E-9 3.260E+0 NA NA 1.695E-9 NA NA 3.453E+0 1.766E-9 NA 3.059E+0 NA 1.840E-9 3.275E+0 NA NA 1.920E-9 NA 3.084E+0 NA 2.022E-9 NA 3.096E+0 NA 2.220E-9 3.287E+0 NA NA 2.278E-9 NA 3.109E+0 NA 2.523E-9 NA NA 3.463E+0 2.670E-9 3.294E+0 NA NA 2.726E-9 NA 3.120E+0 NA 3.280E-9 3.298E+0 NA NA 3.302E-9 NA 3.127E+0 NA 4.070E-9 NA 3.132E+0 NA 6.054E-9 NA 3.135E+0 NA 12.800E-9 3.300E+0 3.135E+0 3.465E+0 | |************************************************************************** | [Submodel] Timed_bushold_up Submodel_type Bus_hold [Submodel Spec] | | typ min max V_trigger_r 1.65 1.50 1.80 V_trigger_f -10.00 -10.00 -10.00 Off_delay 5.00ns 3.00ns 7.00ns | |************************************************************************** | [Pullup] | | Voltage I(typ) I(min) I(max) | -3.300E+0 49.304E-3 38.933E-3 61.611E-3 -3.140E+0 NA NA 58.833E-3 -3.040E+0 NA 36.007E-3 NA -3.025E+0 45.335E-3 NA NA -2.970E+0 NA NA 55.787E-3 -2.740E+0 NA 32.443E-3 NA -2.685E+0 40.215E-3 NA NA -2.570E+0 NA NA 48.359E-3 -2.350E+0 NA 27.670E-3 NA -2.335E+0 34.815E-3 NA NA -2.140E+0 NA NA 40.097E-3 -1.445E+0 NA 16.482E-3 NA -1.395E+0 20.162E-3 NA NA -1.205E+0 NA NA 21.886E-3 -1.165E+0 NA 13.078E-3 NA -1.135E+0 16.168E-3 NA NA -915.000E-3 NA 10.094E-3 NA -905.000E-3 12.695E-3 NA NA -800.000E-3 NA NA 14.174E-3 -740.000E-3 NA 8.051E-3 NA -685.000E-3 9.453E-3 NA NA -615.000E-3 NA NA 10.765E-3 -575.000E-3 NA 6.173E-3 NA -475.000E-3 6.458E-3 NA NA -415.000E-3 NA NA 7.179E-3 -240.000E-3 NA 2.510E-3 NA -235.000E-3 3.143E-3 NA NA -200.000E-3 NA NA 3.413E-3 -195.000E-3 NA 1.915E-3 NA 0.000E+0 19.797E-9 -62.620E-9 30.909E-9 140.000E-3 -1.807E-3 NA NA 145.000E-3 NA NA -2.397E-3 275.000E-3 NA -2.718E-3 NA 280.000E-3 -3.548E-3 NA NA 285.000E-3 NA NA -4.627E-3 405.000E-3 NA -3.927E-3 NA 415.000E-3 -5.159E-3 NA NA 425.000E-3 NA NA -6.769E-3 530.000E-3 NA -5.038E-3 NA 545.000E-3 -6.642E-3 NA NA 555.000E-3 NA NA -8.671E-3 655.000E-3 NA -6.096E-3 NA 675.000E-3 -8.054E-3 NA NA 685.000E-3 NA NA -10.484E-3 775.000E-3 NA -7.058E-3 NA 800.000E-3 -9.339E-3 NA NA 815.000E-3 NA NA -12.201E-3 895.000E-3 NA -7.963E-3 NA 925.000E-3 -10.549E-3 NA NA 945.000E-3 NA NA -13.817E-3 1.015E+0 NA -8.810E-3 NA 1.045E+0 -11.637E-3 NA NA 1.065E+0 NA NA -15.213E-3 1.130E+0 NA -9.564E-3 NA 1.165E+0 -12.648E-3 NA NA 1.185E+0 NA NA -16.512E-3 1.245E+0 NA -10.258E-3 NA 1.280E+0 -13.541E-3 NA NA 1.305E+0 NA NA -17.711E-3 1.355E+0 NA -10.863E-3 NA 1.395E+0 -14.357E-3 NA NA 1.425E+0 NA NA -18.804E-3 1.470E+0 NA -11.432E-3 NA 1.510E+0 -15.092E-3 NA NA 1.540E+0 NA NA -19.749E-3 1.580E+0 NA -11.912E-3 NA 1.620E+0 -15.717E-3 NA NA 1.655E+0 NA NA -20.589E-3 1.685E+0 NA -12.311E-3 NA 1.735E+0 -16.286E-3 NA NA 1.770E+0 NA NA -21.322E-3 1.790E+0 NA -12.648E-3 NA 1.845E+0 -16.746E-3 NA NA 1.880E+0 NA NA -21.918E-3 1.900E+0 NA -12.934E-3 NA 1.955E+0 -17.121E-3 NA NA 1.995E+0 NA -13.124E-3 -22.428E-3 2.055E+0 -17.385E-3 NA NA 2.095E+0 NA NA -22.776E-3 2.140E+0 NA -13.346E-3 NA 2.180E+0 -17.634E-3 NA NA 2.200E+0 NA NA -23.050E-3 2.475E+0 NA -13.752E-3 NA 2.530E+0 -18.185E-3 NA NA 2.570E+0 NA NA -23.801E-3 2.815E+0 NA -14.039E-3 NA 2.875E+0 -18.565E-3 NA NA 2.925E+0 NA NA -24.306E-3 3.205E+0 NA -14.258E-3 NA 3.270E+0 -18.855E-3 NA NA 3.325E+0 NA NA -24.686E-3 3.865E+0 NA -14.505E-3 NA 3.890E+0 -19.153E-3 NA NA 4.045E+0 NA NA -25.119E-3 4.625E+0 NA -14.714E-3 NA 4.660E+0 -19.423E-3 NA NA 4.675E+0 NA NA -25.386E-3 5.560E+0 NA -14.906E-3 NA 5.585E+0 -19.666E-3 NA NA 6.600E+0 -19.867E-3 -15.066E-3 -25.948E-3 | |************************************************************************** | [Ramp] R_load = 50.00Ohm | typ min max | dV/dt_r 540.04mV/1.04ns 411.75mV/1.47ns 698.42mV/705.58ps dV/dt_f 879.96mV/936.61ps 666.10mV/1.42ns 1.12V/623.48ps | |************************************************************************** | [Rising Waveform] V_fixture = 0.000V V_fixture_min = 0.000V V_fixture_max = 0.000V R_fixture = 50.00Ohm | | Time V(typ) V(min) V(max) | 0.000E+0 0.000E+0 0.000E+0 0.000E+0 304.687E-12 NA NA 886.292E-6 343.750E-12 NA NA -5.146E-3 390.000E-12 1.487E-3 NA NA 390.625E-12 NA NA -18.287E-3 429.687E-12 NA NA -32.870E-3 440.000E-12 -537.051E-6 NA NA 500.000E-12 -7.552E-3 NA NA 507.813E-12 NA NA -68.514E-3 524.800E-12 NA 1.248E-3 NA 560.000E-12 -18.135E-3 NA NA 570.313E-12 NA NA -62.466E-3 601.600E-12 NA -372.510E-6 NA 609.375E-12 NA NA -52.003E-3 640.625E-12 NA NA -33.248E-3 671.875E-12 NA NA -7.796E-3 718.750E-12 NA NA 37.454E-3 720.000E-12 -55.605E-3 NA NA 729.600E-12 NA -9.732E-3 NA 773.437E-12 NA NA 96.947E-3 810.000E-12 -49.651E-3 NA NA 870.000E-12 -39.038E-3 NA NA 890.625E-12 NA NA 238.220E-3 910.000E-12 -25.052E-3 NA NA 947.200E-12 NA -34.717E-3 NA 970.000E-12 2.847E-3 NA NA 1.023E-9 NA NA 411.422E-3 1.024E-9 NA -41.097E-3 NA 1.030E-9 35.369E-3 NA NA 1.088E-9 NA -39.982E-3 NA 1.100E-9 76.997E-3 NA NA 1.109E-9 NA NA 519.911E-3 1.139E-9 NA -37.407E-3 NA 1.178E-9 NA -34.318E-3 NA 1.187E-9 NA NA 611.010E-3 1.229E-9 NA -27.513E-3 NA 1.234E-9 NA NA 661.741E-3 1.280E-9 193.512E-3 -17.591E-3 NA 1.312E-9 NA NA 738.544E-3 1.331E-9 NA -5.225E-3 NA 1.359E-9 NA NA 779.652E-3 1.370E-9 NA 5.556E-3 NA 1.434E-9 NA 26.030E-3 NA 1.445E-9 NA NA 845.355E-3 1.523E-9 NA NA 894.889E-3 1.550E-9 377.613E-3 NA NA 1.609E-9 NA NA 939.684E-3 1.626E-9 NA 94.183E-3 NA 1.640E-9 434.769E-3 NA NA 1.695E-9 NA NA 975.966E-3 1.710E-9 476.433E-3 NA NA 1.800E-9 526.495E-3 NA NA 1.812E-9 NA NA 1.015E+0 1.880E-9 567.249E-3 NA NA 1.898E-9 NA NA 1.037E+0 1.960E-9 604.217E-3 NA NA 2.023E-9 NA NA 1.063E+0 2.040E-9 637.386E-3 NA NA 2.140E-9 673.720E-3 NA NA 2.148E-9 NA NA 1.082E+0 2.150E-9 NA 286.945E-3 NA 2.260E-9 710.406E-3 NA NA 2.320E-9 NA NA 1.102E+0 2.342E-9 NA 351.502E-3 NA 2.380E-9 740.595E-3 NA NA 2.484E-9 NA NA 1.115E+0 2.500E-9 765.363E-3 NA NA 2.534E-9 NA 408.751E-3 NA 2.640E-9 788.747E-3 NA NA 2.648E-9 NA NA 1.125E+0 2.662E-9 NA 442.810E-3 NA 2.739E-9 NA 461.522E-3 NA 2.800E-9 809.858E-3 NA NA 2.918E-9 NA 500.149E-3 NA 2.960E-9 826.371E-3 NA NA 3.046E-9 NA 523.649E-3 NA 3.062E-9 NA NA 1.140E+0 3.140E-9 840.754E-3 NA NA 3.174E-9 NA 544.032E-3 NA 3.315E-9 NA 563.258E-3 NA 3.494E-9 NA 583.620E-3 NA 3.500E-9 860.304E-3 NA NA 3.648E-9 NA NA 1.151E+0 3.686E-9 NA 601.249E-3 NA 3.878E-9 NA 615.449E-3 NA 3.960E-9 874.668E-3 NA NA 4.070E-9 NA 626.966E-3 NA 4.445E-9 NA NA 1.158E+0 4.467E-9 NA 644.431E-3 NA 4.540E-9 884.432E-3 NA NA 4.966E-9 NA 658.274E-3 NA 5.320E-9 891.189E-3 NA NA 5.542E-9 NA 667.754E-3 NA 6.310E-9 NA 674.836E-3 NA 6.400E-9 895.767E-3 NA NA 6.859E-9 NA NA 1.164E+0 7.270E-9 NA 679.530E-3 NA 7.890E-9 898.599E-3 NA NA 8.614E-9 NA 682.878E-3 NA 12.800E-9 900.068E-3 686.244E-3 1.164E+0 | [Falling Waveform] V_fixture = 0.000V V_fixture_min = 0.000V V_fixture_max = 0.000V R_fixture = 50.00Ohm | | Time V(typ) V(min) V(max) | 0.000E+0 900.068E-3 686.244E-3 1.164E+0 234.375E-12 NA NA 1.163E+0 312.500E-12 NA NA 1.167E+0 320.000E-12 899.560E-3 NA NA 328.125E-12 NA NA 1.164E+0 343.750E-12 NA NA 1.159E+0 367.187E-12 NA NA 1.141E+0 390.625E-12 NA NA 1.114E+0 414.062E-12 NA NA 1.078E+0 430.000E-12 902.301E-3 NA NA 435.200E-12 NA 685.794E-3 NA 437.500E-12 NA NA 1.036E+0 450.000E-12 900.268E-3 NA NA 468.750E-12 NA NA 971.878E-3 470.000E-12 896.304E-3 NA NA 500.000E-12 884.426E-3 NA NA 507.813E-12 NA NA 885.164E-3 520.000E-12 872.419E-3 NA NA 550.000E-12 849.491E-3 NA NA 562.500E-12 NA NA 758.853E-3 576.000E-12 NA 688.225E-3 NA 580.000E-12 821.272E-3 NA NA 609.375E-12 NA NA 647.473E-3 610.000E-12 789.126E-3 NA NA 627.200E-12 NA 685.274E-3 NA 640.000E-12 754.195E-3 NA NA 652.800E-12 NA 681.263E-3 NA 678.400E-12 NA 674.937E-3 NA 680.000E-12 704.541E-3 NA NA 695.313E-12 NA NA 438.558E-3 704.000E-12 NA 666.217E-3 NA 718.750E-12 NA NA 384.166E-3 734.375E-12 NA NA 350.944E-3 742.400E-12 NA 649.543E-3 NA 750.000E-12 NA NA 320.984E-3 773.437E-12 NA NA 281.432E-3 780.800E-12 NA 628.717E-3 NA 796.875E-12 NA NA 248.194E-3 819.200E-12 NA 604.933E-3 NA 820.312E-12 NA NA 219.385E-3 857.600E-12 NA 579.174E-3 NA 859.375E-12 NA NA 180.242E-3 890.000E-12 432.660E-3 NA NA 898.437E-12 NA NA 149.795E-3 908.800E-12 NA 542.544E-3 NA 953.125E-12 NA NA 117.552E-3 990.000E-12 307.038E-3 NA NA 1.000E-9 NA NA 97.292E-3 1.020E-9 273.422E-3 NA NA 1.050E-9 243.250E-3 NA NA 1.062E-9 NA 427.803E-3 78.915E-3 1.080E-9 217.097E-3 NA NA 1.100E-9 201.777E-3 NA NA 1.117E-9 NA NA 67.704E-3 1.126E-9 NA 381.097E-3 NA 1.150E-9 169.073E-3 NA NA 1.180E-9 152.601E-3 NA NA 1.195E-9 NA NA 56.114E-3 1.220E-9 133.719E-3 NA NA 1.254E-9 NA 291.209E-3 NA 1.280E-9 110.754E-3 NA NA 1.312E-9 NA NA 44.042E-3 1.318E-9 NA 248.409E-3 NA 1.350E-9 89.846E-3 NA NA 1.382E-9 NA 208.877E-3 NA 1.410E-9 75.895E-3 NA NA 1.445E-9 NA NA 34.338E-3 1.446E-9 NA 175.364E-3 NA 1.472E-9 NA 163.858E-3 NA 1.490E-9 62.735E-3 NA NA 1.536E-9 NA 139.323E-3 NA 1.570E-9 NA NA 27.760E-3 1.580E-9 52.533E-3 NA NA 1.613E-9 NA 115.774E-3 NA 1.680E-9 44.426E-3 NA NA 1.702E-9 NA 94.459E-3 NA 1.766E-9 NA 82.409E-3 NA 1.820E-9 36.085E-3 NA NA 1.894E-9 NA 63.304E-3 NA 1.945E-9 NA NA 16.219E-3 1.958E-9 NA 56.055E-3 NA 2.000E-9 28.419E-3 NA NA 2.048E-9 NA 48.206E-3 NA 2.150E-9 NA 41.580E-3 NA 2.291E-9 NA 34.950E-3 NA 2.420E-9 17.637E-3 NA NA 2.470E-9 NA 28.838E-3 NA 2.484E-9 NA NA 8.847E-3 2.944E-9 NA 18.714E-3 NA 2.980E-9 10.579E-3 NA NA 3.273E-9 NA NA 4.163E-3 3.558E-9 NA 11.781E-3 NA 3.780E-9 5.858E-3 NA NA 4.390E-9 NA 7.085E-3 NA 4.940E-9 2.757E-3 NA NA 5.542E-9 NA 3.952E-3 NA 5.734E-9 NA NA 417.798E-6 6.560E-9 969.258E-6 NA NA 7.206E-9 NA 1.833E-3 NA 12.800E-9 0.000E+0 0.000E+0 0.000E+0 | |************************************************************************** [End] From owner-ibis Thu Dec 10 05:40:35 1998 Received: from smtp3.ny.us.ibm.com (smtp3.ny.us.ibm.com [198.133.22.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id FAA26514 for ; Thu, 10 Dec 1998 05:40:34 -0800 (PST) From: gedlund@us.ibm.com Received: from northrelay01.pok.ibm.com (northrelay01.pok.ibm.com [9.117.200.21]) by smtp3.ny.us.ibm.com (8.8.7/8.8.7) with ESMTP id IAA15086 for ; Thu, 10 Dec 1998 08:14:00 -0500 Received: from us.ibm.com (d51mta10.pok.ibm.com [9.117.200.38]) by northrelay01.pok.ibm.com (8.8.7/NCO v1.7) with SMTP id IAA29700 for ; Thu, 10 Dec 1998 08:30:15 -0500 Received: by us.ibm.com(Lotus SMTP MTA Internal build v4.6.2 (651.2 6-10-1998)) id 852566D6.004A2AD1 ; Thu, 10 Dec 1998 08:30:06 -0500 X-Lotus-FromDomain: IBMUS To: ibis@vhdl.org Message-ID: <852566D6.004A28A2.00@us.ibm.com> Date: Thu, 10 Dec 1998 07:27:45 -0600 Subject: circuit origins of the non-monotonic pull-up curve Mime-Version: 1.0 Content-type: text/plain; charset=us-ascii Content-Disposition: inline We got into a discussion the other day about the origin of the non-monotonic IV curve depicted on p. 20 of the cookbook. In my mind, the "output enabled" IV curve should be a sum of the clamp (ESD diode and/or parasitic well diode) and the FET characteristics. Therefore, when you subtract the clamp curve from it, you should get the FET curve, with the possible exception of some round-off errors. However, the "hump" you really see in the pull-up or pull-down curve is much bigger than round-off error. Is this easy to explain, or is it fairly subtle? Where did my reasoning go wrong? Greg Edlund Advisory Engineer, Critical Net Analysis IBM 3650 Hwy. 52 N, Dept. HDC Rochester, MN 55901 gedlund@us.ibm.com From owner-ibis Thu Dec 10 08:31:10 1998 Received: from mail-gw5.pacbell.net (mail-gw5.pacbell.net [206.13.28.23]) by server.eda.org (8.8.5/8.8.3) with ESMTP id IAA27013 for ; Thu, 10 Dec 1998 08:31:09 -0800 (PST) Received: from pacbell.net (ppp-209-79-182-30.vntrcs.pacbell.net [209.79.182.30]) by mail-gw5.pacbell.net (8.8.8/8.7.1+antispam) with ESMTP id IAA19570; Thu, 10 Dec 1998 08:25:19 -0800 (PST) Message-ID: <366FF5F3.35CAF3C0@pacbell.net> Date: Thu, 10 Dec 1998 08:25:23 -0800 From: Jon Powell Reply-To: jpowell@viewlogic.com Organization: Viewlogic Consulting Services X-Mailer: Mozilla 4.04 [en]C-PBI-NC404 (Win95; I) MIME-Version: 1.0 To: gedlund@us.ibm.com Subject: Re: circuit origins of the non-monotonic pull-up curve References: <852566D6.004A28A2.00@us.ibm.com> Content-Type: multipart/mixed; boundary="------------5BE97992F3F68BB521D34351" This is a multi-part message in MIME format. --------------5BE97992F3F68BB521D34351 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit If this is the "hump" I think you are talking about it accurs from the subtraction of two really huge currents as they tend toward MAXFLOAT (sometimes called infinity). We had a big argument and scientific discussion about this when we were first deciding how to approach this and there were many little papers and emails sent around. I think that my final resolution on the matter was, "The hump occurs so far outside of the active region that the device would have melted anyway so it's not worth arguing about". regards, jon --------------5BE97992F3F68BB521D34351 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jon Powell Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Jon Powell n: Powell;Jon org: Viewlogic Consulting Services adr: 1369;;;Camarillo;CA;93010;USA email;internet: jonp@pacbell.net title: Manager High Speed Design Services tel;work: 805 988 8250 tel;fax: 805 988 8259 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------5BE97992F3F68BB521D34351-- From owner-ibis Thu Dec 10 08:39:54 1998 Received: from mail-gw5.pacbell.net (mail-gw5.pacbell.net [206.13.28.23]) by server.eda.org (8.8.5/8.8.3) with ESMTP id IAA27060 for ; Thu, 10 Dec 1998 08:39:54 -0800 (PST) Received: from pacbell.net (ppp-209-79-182-30.vntrcs.pacbell.net [209.79.182.30]) by mail-gw5.pacbell.net (8.8.8/8.7.1+antispam) with ESMTP id IAA23109; Thu, 10 Dec 1998 08:35:08 -0800 (PST) Message-ID: <366FF83F.98548D6A@pacbell.net> Date: Thu, 10 Dec 1998 08:35:11 -0800 From: Jon Powell Reply-To: jpowell@viewlogic.com Organization: Viewlogic Consulting Services X-Mailer: Mozilla 4.04 [en]C-PBI-NC404 (Win95; I) MIME-Version: 1.0 To: ibis@vhdl.org Subject: Logos for Supercon Content-Type: multipart/mixed; boundary="------------A2971C582BB7094F1F96E5FC" This is a multi-part message in MIME format. --------------A2971C582BB7094F1F96E5FC Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Seasons Greetings Hey, the responses back with Logos (esp. usable logos) for the designcon booth have been really sparse. It is coming fast on the holiday season and you know you won't get anything done during that time. I don't want people yelling at me because the only things on the sign at Designcon are a great big IBIS logo and a great big NEW Viewlogic logo, so get those things in to me. Really. If you are having return mail problems or something please use: jonp@pacbell.net I can also be reached by phone at 805 988 8250 if you want to talk about this. (anyone except kelle) :) Merriest Wishes ! Jon --------------A2971C582BB7094F1F96E5FC Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jon Powell Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Jon Powell n: Powell;Jon org: Viewlogic Consulting Services adr: 1369;;;Camarillo;CA;93010;USA email;internet: jonp@pacbell.net title: Manager High Speed Design Services tel;work: 805 988 8250 tel;fax: 805 988 8259 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------A2971C582BB7094F1F96E5FC-- From owner-ibis Thu Dec 10 09:37:17 1998 Received: from ganymede.or.intel.com (ganymede.or.intel.com [134.134.248.3]) by server.eda.org (8.8.5/8.8.3) with ESMTP id JAA27204 for ; Thu, 10 Dec 1998 09:37:16 -0800 (PST) Received: from ichips-jf.jf.intel.com (ichips-jf.jf.intel.com [134.134.50.200]) by ganymede.or.intel.com (8.8.6/8.8.5) with ESMTP id RAA23959; Thu, 10 Dec 1998 17:32:28 GMT Received: from xtg801.pdx.intel.com (xtg801.pdx.intel.com [134.134.114.35]) by ichips-jf.jf.intel.com (8.8.8/8.8.7) with ESMTP id JAA26135; Thu, 10 Dec 1998 09:32:25 -0800 (PST) Received: from ichips.intel.com by xtg801.pdx.intel.com (8.8.8/WW2.2 (Jones Farm)) id JAA05737; Thu, 10 Dec 1998 09:32:25 -0800 (PST) Message-Id: <199812101732.JAA05737@xtg801.pdx.intel.com> X-Mailer: exmh version 2.0delta 6/3/97 To: gedlund@us.ibm.com Cc: ibis@eda.org Subject: Re: circuit origins of the non-monotonic pull-up curve In-reply-to: Your message of "Thu, 10 Dec 1998 07:27:45 CST." <852566D6.004A28A2.00@us.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Thu, 10 Dec 1998 09:32:24 -0800 From: Stephen Peters Hello Greg, IBIS list: Ummm... this is a place where a picture is worth a thousand words, so I will try a little ANSI art. Ground Clamp Data = * Pulldown Data = + (I) | | | ++++++++++++++++ | + | + |+ -------********************** (V) * +| * + | * + | * + | point A --> * | * | | The picture above is an attempt to show a pulldown curve and ground clamp curve on the same set of axis. What I've seen many time is that at point A, the pulldown curve and the ground clamp become very close to one another, even converging so that they lie on top of each other. Physically, I'm not exactly sure what is happening, but apparently when the pulldown FET starts acting as the clamp diode is stops acting like a FET. Note that I've seen this convergence (or near to it) even in devices that have ESD protection diodes. Apparently the current in the ESD structure is small compared with the main clamping action of the pulldown FET. At any rate, when you subtract the two curves you end up with the curve shown in the cookbook. Hope this helps. Regards, Stephen Peters Intel Corp. > We got into a discussion the other day about the origin of the > non-monotonic IV curve depicted on p. 20 of the cookbook. In my mind, the > "output enabled" IV curve should be a sum of the clamp (ESD diode and/or > parasitic well diode) and the FET characteristics. Therefore, when you > subtract the clamp curve from it, you should get the FET curve, with the > possible exception of some round-off errors. However, the "hump" you > really see in the pull-up or pull-down curve is much bigger than round-off > error. Is this easy to explain, or is it fairly subtle? Where did my > reasoning go wrong? > > Greg Edlund > Advisory Engineer, Critical Net Analysis > IBM > 3650 Hwy. 52 N, Dept. HDC > Rochester, MN 55901 > gedlund@us.ibm.com > From owner-ibis Thu Dec 10 13:02:31 1998 Received: from mail.hyperlynx.com (root@mail.hyperlynx.com [209.20.148.70]) by server.eda.org (8.8.5/8.8.3) with ESMTP id NAA27808 for ; Thu, 10 Dec 1998 13:02:24 -0800 (PST) Received: from tensor ([192.168.148.75]) by mail.hyperlynx.com (8.8.5/8.8.5) with SMTP id MAA11524 for ; Thu, 10 Dec 1998 12:57:41 -0800 Message-Id: <3.0.5.32.19981210125832.0103ab20@mail.nwlink.com> X-Sender: mbflora@mail.nwlink.com X-Mailer: QUALCOMM Windows Eudora Pro Version 3.0.5 (32) Date: Thu, 10 Dec 1998 12:58:32 -0100 To: ibis@eda.org From: Matthew Flora Subject: IBIS Summit Meeting Minutes 7 Dec 1998 Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" DATE: 12/10/98 SUBJECT: 12/7/98 EIA IBIS Summit Meeting Minutes VOTING MEMBERS AND 1998 PARTICIPANTS LIST: AMP (Martin Freedman) Applied Simulation Technology Norio Matsui, Raj Raghuram* Cadence Design (& UniCAD) C. Kumar, Don Telian, Patrick Riffault, Craig Lewis, Greg Fitzgerald, Paul Galloway, Patrick Dos Santos, Catherine Weiss, Alain Tribaudot, Geoffrey Ellis, Todd Westerhoff, Ken Willis, Mike LaBonte Cisco Systems Syed Huq*, Sergio Camerlo, Irfan Elahi Compaq Shariq Rahma, Jeff Chu, Bob Haller, (Digital Equipment Corp.) Doug Burns, Steve Coe Cypress Bruce Wenniger* H.A.S. Electronics Haruny Said Hewlett Packard (EEsof, etc.) Karl Kachigan, Henry Wu, Paul Gregory, Brenda Arena, Hans Wiggers* High Design Technology Razvan Ene HyperLynx Kellee Crisafulli, Matthew Flora, Gene Garat, Dave Kohlmeier Incases Olaf Rethmeier, Scott Jacobson, Werner Rissiek Intel Corporation Stephen Peters, Arpad Muranyi, Frank Kern, (& formerly NCR) Will Hobbs, Prakash Radhakrishnan, Mohammed Hawana, Martin Chang, Dave Moxley, Tim Schreyer, Lyndell Asbenson LSI Logic (Symbios Logic) Larry Barnes Mentor Graphics (Zeelan, Bob Ross*, George Opsahl, Mark Noneman, Interconnectix, etc.) Tom Dagostino*, Karine Loudet, Jean Oudinot, Manuel De Almeida, Stephane Rousseau, Neven Orhanovic, Mohamed Mahmoud, Kevin Cohan Mitsubishi Tam Cao Motorola (Ron Werner) National Semiconductor Cheng-Yang Kao, John Goldie, Ikchang Song, Milt Schwartz* North East Systems Associates Edward Sayre, Kathy Breda, Michael Baxter, (NESA) Jon Green, Jinhua Chen NEC (Hiroshi Matsumoto) Quantic EMC (Mike Ventham) Texas Instruments Thomas Fisher, Harvey Stiegler, Vincent Chang, Jean-Claude Perrin, Peter Forstner Thomson-CSF Jean-Marc Claveau, Laurent Duzaic, Saverio Lerose, Benoit Meyniel, Jean Lefebvre Viewlogic Jon Powell, Chris Rokusek*, Guy de Burgh, Gary Mandel VeriBest Ian Dodd, David Weins, Ian Gabbitas VLSI Technology D.C. Sessions*, Derwin Mattos* Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1998: 3Com Steve Miller 3Dfx Interactive Ken Wu A.T.Sinker Tony Sinker Actel Eric Tardif, Emmonvelle Gaudin Aerospatiale Lionel Dreux, Claude Huet Alcatel (Bell, Espace, etc.) John Fitzpatrick, W. Temmerman, Laure Bessettes, Jean-Claude Pourtau, Daniel Peron ALS Design Yves Mouquet Ansoft Eric Bogatin Apple Fred Floresca, Danny Itani Apteq Design Systems Dan FitzPatrick Atmel Ali Baktashian Avanti Nik Bannov CERN Olivier Clere, Jean-Michel Sainson, Rudi Zurbroken Corning John Nieznanski Crucial Technology Rathna Reddy DIVA Corp Tieng Nguyen Dynamic Research Corporation Mike Walsh EIA Patti Rusher EMC Fawn Engelmann, Fabrizio Zanella ENST, Paris Jean-Jacques Charlot European CAD Standardization Adam Morawiec Intitiative (ECSI) Fairchild Semiconductor Peter LaFlamme Focus Technology John Salzillo, Gary Brophy, Mike Arieta, Jim Skane Hyundai Farhad Tabrizi* IBM Richard Steinle, Kevin Jackson, Greg Edlund, Douglas Stout* InRange Elliot Lipin Intracon Design Ltd. Derek Laidlaw LG Semicon America Michael Spooer*, Seung-Tae Lee* Micron Technology Terry Lee* Molex Gus Panella Philips Semiconductor Todd Andersen Rockwell Semiconductor Tim Gilbert Scottish Electronics Robert Easson Manufacturing Center (SEMC) Seagate Vanessa Howard Signal Integrity Software Barry Katz SGS-Thomson Philippe Lefevre Siemens Gerald Bannert, Bernhard Unger, Christian Marot, Miguel Hernandez, Gil Russell, Hartmud Terletzki* SSEI Tom Hawkins Stratus Bruce Heilbrunn, Steve Mango, Lewis Steiner, Karla Eignor, Rich Newell Summit Computer Systems Bob Davis Sun Microsystems Lam Dong, Kevin Ko, Tay Ansari, Ken Weiss, Derek Tsai* Symmetry Andy Hughes Tektronix Nassrin Ghahyasi, Tom Brinkoetter, Brad Weber, John Rettig Teradyne Michael Khusid Time Domain Analysis Systems Dima Smolyansky Transmeta Bill Gervasi* TranSwitch Bill Todd TRILOGIC Joe Socha Ultratest International Chris O'Connor Xilinx Susan Wu, Rob Eccles* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode December 18, 1998 (916) 356-9200 3-241993 1195347 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ----------------------------------- IBIS SUMMIT MEETING The IBIS Summit Meeting was held at the Shelter Pointe Hotel and Marina in San Diego, California at the same time as the JEDEC JC-40 and JC-16 meetings. About 19 people representing 16 organizations participated in the meeting. The food, refreshments, and the facilities were excellent. The Minutes here just briefly note some of the content of the meeting and some discussion. Some of the presentations and related documents will be uploaded at: http://www.eda.org/pub/ibis/summits/dec98 INTRODUCTIONS AND BUSINESS - Bob Ross (Mentor Graphics) After a delicious buffet lunch for attendees, Bob Ross opened the IBIS meeting by having the participants introduce themselves. There appeared to be equal representation from the IBIS and JEDEC communities. The semiconductor sector was more heavily represented than the user and EDA tool vendor sectors. An underlying theme of this meeting was to introduce and discuss possible new modeling requirements and needs. Following this theme, the EIAJ activity on I/O Interface Model for Integrated Circuits (IMIC) would be discussed because it had some possible ideas to deal with details that might not be currently handled well in IBIS. Bob noted that due to the last minute introduction of BIRD57 on Timed Bus Hold Extension, we are deferring the vote on IBIS Version 3.2 that had been scheduled for Friday, December 18, 1998 to the following meeting scheduled on Friday, January 15, 1999. That will give us time to review in the December 18, 1998 meeting the pending BIRD56 and BIRD57, initiate possible ibischk3 changes, and prepare IBIS Version 3.2 for voting with these BIRDs included. Bob also summarized that the next IBIS Summit Meeting is scheduled on Monday, February 1, 1998 at DesignCon99 in San Jose. The EIA IBIS Open Forum is an Associate Sponsor of DesignCon99 allowing DesignCon99 to provide the meeting facilities and refreshments. National Semiconductor will sponsor the luncheon. In the past, National had sponsored the whole meeting including facilities. Milt Schwartz will be the contact person for signing up meeting participants and signing up and gathering presentations. A first notice should be issued this week. The focus of that meeting will be on Accuracy issues and future IBIS features. Also, through the Associate Sponsorship arrangement, there will be an IBIS booth on the Exhibition floor that will provide IBIS information and demonstrate the IBIS User's Group accuracy test board measurements. Jon Powell is the contact person for the booth. Ad Hoc presentations and discussion topics were solicited: Active Terminations - Derek Tsai Bus Switches Functionality - Tom Dagostino Accuracy Testing of Measurement Based Models - Tom Dagostino JEDEC JC-16.2 IBIS Presentation - Bob Ross PROGRAM NOTES FOLLOW (Scheduled and Ad Hoc Presentations): INPUT THRESHOLD MODELING - D.C. Sessions (VLSI Logic) D.C. Sessions noted that as a result of tighter timing margins, the old input threshold limits such as Vinh = 2.0 V and Vinl = 0.8 V are becoming too conservative to be practical. Input signals can easily have a ledge in the in the region between Vinh and Vinl. The actual thresholds are much tighter. Also JEDEC JC-16.2 is standardizing on closer threshold limits for newer technologies. D.C. noted that for many technologies, the Input thresholds were related to the power supply voltage. So D.C. suggested a linear adjustment factor that is related to the rail to determine more accurate thresholds. Bob Ross mentioned that this might already exist indirectly using the [Model Spec] keyword. D.C. also noted that the timing delay was a function of how much the input signal went over the first threshold. D.C. showed some time shifted responses as a function of threshold overvoltage from 25 mV to about 1.6 V. The delays shrank from about 3 ns to 300 ps. For this particular simulation, D.C. fit the data to a 2/3rds power relationship: t = to + K/(Vin - Vth)**(2/3) D.C. suggested a timing table could be proposed for IBIS to capture this input resolution. To summarize, D.C. presented the following draft proposal: 1) Threshold Voltage "Add a first-order term to the exiting Vin specs. DC trip point is defined as the specified value at the specified supply voltage plus (the new value) times the difference in supply voltage. Alternately, add a table. In effect, turn the current and scaler values into lists." 2) Timing "In keeping with IBIS's preferred use of observable properties, add an [input_delay] table giving relative delay for input voltages relative to the specified thresholds. Thus, if Vinl is 800 mV under some condition, the table entry at 200 mV is the added delay for signals at 1000 mV. Simulator providers would be free to innovate with respect to dynamic algorithms for complex input waveforms. OVERVIEW OF JEDEC JC-16 ACTIVITIES - Hans Wiggers (Hewlett-Packard and Chair. of JC-16) Hans Wiggers introduced himself as Chair of the JC-16 group under which there are two subgroups. The group is involved with interface topologies. They also provide an educational function. Hans commented that the threshold and input characteristics are of interest. Also a driver specification consisting of a Max and Min IBIS style table for bounding values is a current proposal under discussion for memory devices. Hans listed a number of standards that the group has been involved with. Low Performance standards include: TTL, LVTTL, LVCMOS, 2.5 V non-terminated CMOS, 1.5 V interfaces. High performance standards include: GTL, Center Tap Terminated, (High Speed Transmission Logic) HSTL -1, -2, -3, -4, (Series Stub Terminated Line) STTL for 3.3 V, now 2.5 V and future 1.5 V. The best inputs are with a terminator to Vtt = Vddq/2 (the quiescent Vdd voltage). Hans showed some network topologies to illustrate this. One distinction is that JEDEC standardizes parameters that can be put in data sheets. Data sheet information is contractual; customers can reject the components if they do not meet the data sheet specifications. So there is a reluctance for very tight parameters which may be hard to test against. The immediate future activities of JEDEC JC-16 are modifying STTL-2, adding IBIS-like tables to driver specifications, and specifying LVCMOS for 1.5 V. ACTIVE TERMINATIONS (Ad Hoc) - Derek Tsai (Sun Microsystems) Derek Tsai showed a device/net topology with a switchable termination and asked whether IBIS Version 3.1 could cover it. The topology involved a pullup termination Rup that was active only in the driving mode. Rup and Rdn source and load terminations were equal to Zo and were switchable from up to down states. It appeared that Rup was disabled only in the receiver mode. Derek listed some characteristics: 1. Back-to-back switching 2. Rup acts as termination (active) and never turns off until it needs to drive "low" 3. Rdn drive '0' 4. Fall: Rup -> Rdn Rdn -> Rup and stays on 5. Problems: 1) transition has glitches, 2) bus contention (under work-around simulations) There was some discussion and clarification. Bob Ross indicated that pending IBIS Version 3.2 had submodel parameters both for dynamic clamps and for bus hold style circuits. While Bob thought that the bus hold extensions documented in pending IBIS Version 3.2 would model Derek's circuit, discussions during a break revealed that perhaps the dynamic clamp in the static mode was the appropriate representation. SERIES SWITCH EXTENSION (Ad Hoc) - Tom Dagostino (Mentor Graphics) Tom Dagostino drew a topology showing nets containing series switches that were turned on and off to control the connection paths. Tom asked if the turning on and off characteristics of the on/off and off/on transitions of the switch itself were important to model. Several people responded that they needed to model such effects. The series switch extension in IBIS Version 3.1 models only the static on or static off impedances in the path itself, but not the transition characteristics. IMIC DISCUSSION - Bob Ross (Mentor Graphics) Bob Ross introduced the background of why we are discussing the IMIC activity at this meeting. Bob indicated that the IBIS Committee people had been following the IMIC activity since February, 1997 through October, 1998 as a result of several private meetings and several IBIS Summit presentations on IMIC. At the London IEC meeting in September, 1998, the request was made that the IBIS committee work with the I/O Modeling Project group responsible for IMIC since the activities appeared to overlap. Bob indicated that there were subsequent meetings with Dr. Hideki Fukuda in October, 1998 on this subject and that the topic was appropriate at this meeting since it related to potential IBIS future extensions. As an introduction, the IMIC activity had begun in 1996 to extend IBIS Version 2.1. The intent was to create extensions to deal with signal integrity, power integrity (ground and power bounce and SSO simulations), and EMI simulations. Also, the extension was needed to deal with emerging buffer topologies. Bob noted that IBIS also expanded its capability leading to IBIS Version 3.X extensions. However, there could be limitations to the IBIS behavioral approach that could be solved by IMIC and SPICE approaches. Bob summarized the IMIC approach both in his presentation and copies of slides provided by Fukuda-san. IMIC formats Modules (similar to IBIS EBD), ICs (Similar to IBIS Components and Models), and Packages (similar to IBIS Packages). However, IMIC supports a SPICE netlist syntax plus some IBIS wrapper keywords. IMIC also introduces a table SPICE representation of MOSFET, Diode and Bipolar devices that allows process information to remain proprietary. The models can be complex as shown by 1D (corresponding to IBIS, 2D and 3D samples. However, there could be efficiencies associated with scaling the buffers rather than providing different models for each physical geometry variation. Bob noted that IMIC does not include some specification and informational details contained in the IBIS format that are used by many simulators used for digital circuit board design and analysis. Such information includes model type (e.g., Input, Output, I/O, etc.), threshold specifications, timing test loads, and some connection information documenting differential I/O pin connections, power rail pin connections, etc. Bob outlined some IBIS/IMIC approaches: Merge IBIS and IMIC Link from IBIS to IMIC features of interest Keep IBIS and IMIC separate, but provide IMIC to IBIS translation paths There are practical and business advantages and disadvantages to each of these approaches. The most interesting is to explore Linkage to the package extensions and to the buffer formulations. These also relate to possible SPICE linkages and to both Table Spice and BSIM Version 3.2.2 extensions being standardized by the Compact Modeling Council. Bob noted one novel feature of the IMIC format is that it might be possible to format typical, minimum and maximum package characteristics in the same document. Bob was interested in accuracy validation of the table SPICE approach, and this is a subject in the next presentation. An IBIS committee study group consists of Stephen Peters, Raj Raghuram, Norio Matsui, and Bob Ross. Others are welcome to join. The EIAJ group will also have a small group for interaction. In the subsequent discussion, Syed Huq pointed out the IMIC is not an officially approved standard - it is still in draft mode and has not gone through official acceptance processes. In contrast, IBIS is an approved ANSI/EIA standard. VALIDATION OF EIAJ IMIC MODELS - Raj Raghuram (Applied Simulation Technology) Raj Raghuram also presented an overview of IMIC using selected copies of older presentations. The multi-dimension table format is an extension of Berkeley SPICE. The approach is supported by several commercial SPICE simulators, and the tables can be automatically generated by 3D DC sweeps and selecting the options to print capacitances at each point. With generic SPICE, more analysis work is needed by doing AC analysis at each operation point to extract capacitances. The validation process was to generate a Table SPICE model from a driver SPICE model, and then compare the simulation results of each under the same set of test loads. Example 1 used the Motorola 74LCX245 low voltage CMOS Octal transceiver model as the basis. Simulations were done with these driving parameters: 1 ns Tr, 1 ns delay, 9 ns pulse width. The results were compared with these test circuit loads: 500 ohms and 5 pF to ground, 50 ohms to ground, 50 ohms to Vcc (3 V), and 500 ohms terminating a 50 ohm and 1 ns transmission line. All of the results showed very similar waveform shapes when overlayed. There was a slight delay mismatch, but Raj considered that a problem based on low Table SPICE resolution. He did not have time to investigate and provide refinements to this skew in results or to investigate the effects of 3D to 2D model simplifications. Example 2 compared a Texas Instruments CBT16233 with a Table SPICE formulation. The device was loaded with a 1 kiloohm and 5 pF at the end of a 65 ohm and 1 nS transmission line. Excellent, overlaying response was shown between the orignal SPICE model simulation and table SPICE models generated from Applied Simulation Technology and HSPICE simulators. Raj concluded that the correlation was good and that the IMIc model is a viable SPICE-like alternative that protects proprietary process information. ACCURACY TESTING OF MEASUREMENT BASED MODELS - Tom Dagostino (Mentor Graphics) Tom Dagostino raised the question and led the discussion on what is needed to test the accuracy of measurement based models. A number of points were made relating to accuracy and to what should be included in a measurement based model are captured here. One point is that measurement based models document actual characteristics of the device. However, since it was not known whether that device was really typical, the scaling of the device data for min and max characteristics should be left to the simulator tool. It should not be given in the model. D.C. Sessions was interested in a range for different processes. Tom indicated that measurements could be done on a number of devices from the same vendor for different lots over time to get a statistical spread. Milt Schwartz and others indicated that sometimes the fabrication lab does not have the process skew information. Furthermore, there is a reluctance to provide too tight of information which will result in being forced to guarantee tighter information in the data sheet. So the documentation of lots was becoming less rigorous. Tom asked if it were valid to test different devices from a same technology from the same vendor, and several people stated that this was not valid since even with what is documented as the same family, the actual devices may have different characteristics and come from different processes or die sizes. So it was not a defendable practice to infer that different characteristics were related to min and max variations. Regarding test and extraction conditions, Chris Rokusek and other people stressed that capturing the information based on the IBIS Cookbook conditions of 50 ohms to ground and to Vcc and testing against those conditions was a preferred approach. There might be some exceptions, but even if the voltage swing is not full scale, the model was still tuned to the actual transmission line connections that need to be simulated. Other test loads could be included in the IBIS model for the purposes of validating the model, although few people are doing this. Examples of a validation load are connection of 50 ohms to Vcc/2 and using some capacitive loads. D.C. Sessions commented that he expected that the contributions of process variation, temperature variations (over a 0 degrees C to 125 degrees C) and a 10 percent voltage variation to have about equal contribution effects. So if IBIS models are extracted from measurements under simultaneous voltage and temperature variations, it might be defendable to infer the process variation effect by some additional scaling by 1/2. Chris indicated classified accurate models as Level 0: ramp based Level 1: one waveform based (one rising, one falling) Level 2: two waveform based (two rising, two falling) Chris felt that the Level 0 and Level 1 models were of comparable accuracy, and Level 2 models provide a great improvement. D.C. pointed out that the two waveform extraction provided both the turn on and turn off characteristics needed for the complete characterization. Chis noted that the 50 ohm load provided a better load line for actual operating conditions. D.C. mentioned that the 50 ohm extraction took into account the buffer Miller capacitance that affects the response. IBIS PRESENTATION AT THE JEDEC JC-16 MEETING (Ad Hoc) - Bob Ross (Mentor Graphics) Bob Ross indicated that Stephen Peters had been scheduled to do a presentation both at the IBIS Summit Meeting and also at the JEDEC JC-16 meeting, but he was unable to attend. So we needed to draft a presentation for the next day JEDEC meeting. D.C. Sessions provided some general guidelines, and the action was to work out presentation details at a dinner gathering with those people who would attend the JEDEC meeting. (Bob Ross and Chris Rokusek created a mostly hand-drawn IBIS Overview and Simulation presentation for the JEDEC Meeting on Tuesday, December 8, 1998. Several other IBIS committee participants attended. The presentation appeared to be well-received and prompted several questions. As an action item D.C. Session was asked to chair a JEDEC JC- 42 and JC-16 Task Group on Formation of IBIS Models. Initially people from Hewlett-Packard, IBM, Xilinx, Western Digital, United Memories, Micron, and Samsung joined this Task Group. Participation is also open to IBIS Committee participants. Contact D.C. Sessions to join.) NEXT MEETING: The next teleconference meeting will be on Friday, December 18, 1998 from 8:00 AM to 10:00 AM. BIRD56 and BIRD57 are scheduled for votes. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentorg.com Modeling Engineer, Interconnectix BU of Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-56 2111 NE 25th Ave. Hillsboro, Oregon 97124-5961 SECRETARY: Matthew Flora (425) 869-2320, Fax: (425) 881-1008 mbflora@hyperlynx.com Senior Engineer, HyperLynx, Inc. 17641 NE 67th Court Redmond, WA 98052 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Senior Scientist, Viewlogic (formerly Quad Design) 1385 Del Norte Rd., Camarillo, CA 93010 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ============================================================================== From owner-ibis Thu Dec 10 13:15:05 1998 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id NAA27852 for ; Thu, 10 Dec 1998 13:15:04 -0800 (PST) Received: from em-wv03.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id NAA22174; Thu, 10 Dec 1998 13:09:50 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.8.8/CF5.40R) id NAA28179; Thu, 10 Dec 1998 13:09:50 -0800 (PST) From: bob_ross@mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA19862; Thu, 10 Dec 98 13:09:48 PST Date: Thu, 10 Dec 98 13:09:48 PST Message-Id: <9812102109.AA19862@bob> To: ibis@eda.org Subject: IBIS/DESIGNCON99 SUMMIT MEETING ANNOUNCEMENT To All: This is the first call for presentations and participation at the IBIS Summit Meeting held with DesignCon99. Bob Ross Mentor Graphics ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------- DESIGNCON99 IBIS SUMMIT CALL FOR PARTICIPATION, PRESENTATIONS ------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ I B I S S U M M I T M E E T I N G Time/Date: 8:30 PM - 5:00 PM, Monday, February 1, 1999 Location: Santa Clara Convention Center Santa Clara, CA Content: Exchange of ideas on IBIS accuracy, connectors, IMIC, new requirements, etc. Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: DesignCon99 & National Semiconductor Corporation IBIS Summit Signup: Milt Schwartz schwartz@rockie.nsc.com D E S I G N C O N 9 9 M E E T I N G S Time/Date: Monday - Thursday, February 1 - 4, 1999 Exhibition: Tuesday - Wednesday, 12 PM - 7 PM, February 2 - 3, 1999 IBIS Booth: #250, Exhibition Hall - Accuracy Committee Demonstration - IBIS Information - Contact Jon Powell, jonp@qdt.com, for information. URL DesignCon99: http://www.designcon.com Signup Discount: Up to 5 people from IBIS member companies may receive a 10 percent discount to DesignCon99. CALL FOR IBIS SUMMIT PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. Format of Presentation: Overhead Projections Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat. If you cannot provide an electronic format, then plan to bring 50 copies for distribution at the meeting. If you plan a presentation, please supply Title: Presenter: E-mail address: Company: Telephone: Estimate Time: Send this to: Milt Schwartz schwartz@rockie.nsc.com Deadline: Wednesday, January 27, 1999 AGENDA The agenda includes presentations, discussions, refreshments, and a free buffet luncheon for participants. In addition, we will have an opportunity for Ad Hoc presentations and extended discussions. From owner-ibis Thu Dec 10 14:05:47 1998 Received: from mail13.digital.com (mail13.digital.com [192.208.46.30]) by server.eda.org (8.8.5/8.8.3) with ESMTP id OAA28025 for ; Thu, 10 Dec 1998 14:05:46 -0800 (PST) Received: from sbuamazko2ae.zko.dec.com (sbuamazko2ae.zko.dec.com [16.29.160.92]) by mail13.digital.com (8.9.1a/8.9.1/WV2.0c) with ESMTP id RAA00097 for ; Thu, 10 Dec 1998 17:01:00 -0500 (EST) Received: by sbuamazko2ae.zko.dec.com with Internet Mail Service (5.0.1458.49) id ; Thu, 10 Dec 1998 17:00:53 -0500 Message-ID: <709745919B84D21197C40000F84AA1F70A15BC@sbuamapko3cc.eng.pko.dec.com> From: Andrew Ingraham To: gedlund@us.ibm.com Cc: ibis@eda.org Subject: RE: circuit origins of the non-monotonic pull-up curve Date: Thu, 10 Dec 1998 15:00:09 -0500 X-Priority: 3 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.0.1458.49) Content-Type: text/plain Maybe it's the common series resistance in series with both the ground clamp and the pulldown FET? Once the clamp current is big enough so that the series resistance dominates, turning on the pulldown won't add much additional current anymore. Regards, Andy Ingraham From owner-ibis Thu Dec 10 15:32:08 1998 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id PAA28259 for ; Thu, 10 Dec 1998 15:32:08 -0800 (PST) Received: from em-wv03.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id PAA03563; Thu, 10 Dec 1998 15:26:54 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.8.8/CF5.40R) id PAA18758; Thu, 10 Dec 1998 15:26:53 -0800 (PST) From: bob_ross@mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA20289; Thu, 10 Dec 98 15:26:52 PST Date: Thu, 10 Dec 98 15:26:52 PST Message-Id: <9812102326.AA20289@bob> To: ibis@eda.org Subject: IBIS AGENDA 12/18/98 IBIS Open Forum Meeting Agenda for 12/18/98 Bridge Number Reservation # Passcode (916) 356-9200 3-241993 1195347 All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the Reservation Number and Passcode. NOTE: Bob Ross will be on vacation from Dec 11, 1998 to Dec 17, 1998. Stephen Peters will conduct the meeting if Bob's return is delayed. 8:00 Check-In, Intros, Announcements Ross - Intros of New IBIS Participants, Meeting Quorum Ross - Membership Update and Treasurers Report Rusher - Review of Previous Meeting's Minutes (and ARs) Ross - Miscellany/Announcements All - Press & Web Page Updates Huq, All - New Models Available, Library Update Powell, All - Opens for New Issues All 8:15 Administrative and Project Discussions International/External Progress - IEC 62014-1 (IBIS Version 2.1) Rusher - pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits (IMIC) Raghuram/Ross - 93/67/NP IBIS and EMC Simulation Perrin - JEDEC JC-16.2 Modeling and Testing Sessions - IEEE P1537 Data Format Project Peters JEDEC/IBIS December 7, 1998 Summit Meeting Feedback All IBIS (East) Users Group Meetings Haller/Zanella DesignCon99 February 1, 1999 Summit Meeting/Booth Ross/Rokusek - Meeting - Booth/Logos DATE99 March 9, 1998 IBIS Summit Meeting Ross - Date change Version 3.2 Parser Development Ross/Flora/Rokusek - Source, Executables - Version 3.2 Document - Version 3.2 Parser Development Tektronix IPA510 Software Proposal Discussion Huq (Moved to End of Technical Discussion) Cookbook Status Peters IBIS Model Review Committee Flora New Administrative Issues All 9:00 Technical Discussion BIRD56 - Relaxation of [Series Pin Mapping] Ross Restriction (Vote) BIRD57 - Timed Bus Hold Extension (Vote) Muranyi/Peters/Ross Version 3.2 Ratification Preparation Ross BUG31 - Error for [Pulldown] Decreasing Current Should Ross be Warning (more discussion) Tektronix IPA510 Software Proposal Discussion Huq New Technical Issues All 9:50 Wrap Up and Next Meetings Plans Peters 9:55 Sign Off From owner-ibis Mon Dec 14 14:45:52 1998 Received: from mail-gw6.pacbell.net (mail-gw6.pacbell.net [206.13.28.41]) by server.eda.org (8.8.5/8.8.3) with ESMTP id OAA06669 for ; Mon, 14 Dec 1998 14:45:52 -0800 (PST) Received: from pacbell.net (ppp-209-79-182-53.vntrcs.pacbell.net [209.79.182.53]) by mail-gw6.pacbell.net (8.8.8/8.7.1+antispam) with ESMTP id OAA27070; Mon, 14 Dec 1998 14:41:05 -0800 (PST) Message-ID: <36759400.B217A5A1@pacbell.net> Date: Mon, 14 Dec 1998 14:41:04 -0800 From: Jon Powell Reply-To: jpowell@viewlogic.com Organization: Viewlogic Consulting Services X-Mailer: Mozilla 4.04 [en]C-PBI-NC404 (Win95; I) MIME-Version: 1.0 To: ibis@vhdl.org Subject: DesignCon status Content-Type: multipart/mixed; boundary="------------624752B2B57691996A6A2672" This is a multi-part message in MIME format. --------------624752B2B57691996A6A2672 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi there, Here is the interest I currently have for organizations wishing their logo to be displayed at designcon. I seem to be having a very hard time getting logos in a readable and sizeable format. If you think you should be on this list and aren't, Please let me know. regards, jon IBIS Librarian Interest LOGO LOGO-GOOD Apsim Yes NO Incases Yes NO Xilinx Yes NO NCSU Yes NO Hyperlynx Yes YES Viewlogic NO NA Cadence YES YES Mentor YES NO Intel NO NA Altera NO NA HP YES NO --------------624752B2B57691996A6A2672 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jon Powell Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Jon Powell n: Powell;Jon org: Viewlogic Consulting Services adr: 1369 Del Norte Rd.;;;Camarillo;CA;93010;USA email;internet: jonp@pacbell.net title: Manager High Speed Design Services tel;work: 805 988 8250 tel;fax: 805 988 8259 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------624752B2B57691996A6A2672-- From owner-ibis Wed Dec 16 13:48:26 1998 Received: from mail-gw.pacbell.net (mail-gw.pacbell.net [206.13.28.25]) by server.eda.org (8.8.5/8.8.3) with ESMTP id NAA14317 for ; Wed, 16 Dec 1998 13:48:26 -0800 (PST) Received: from pacbell.net (ppp-209-79-182-185.vntrcs.pacbell.net [209.79.182.185]) by mail-gw.pacbell.net (8.8.8/8.7.1+antispam) with ESMTP id NAA13041; Wed, 16 Dec 1998 13:43:33 -0800 (PST) Message-ID: <36782976.C5D975BF@pacbell.net> Date: Wed, 16 Dec 1998 13:43:19 -0800 From: Jon Powell Reply-To: jpowell@viewlogic.com Organization: Viewlogic Consulting Services X-Mailer: Mozilla 4.04 [en]C-PBI-NC404 (Win95; I) MIME-Version: 1.0 To: ibis@vhdl.org Subject: logos and Designcon Content-Type: multipart/mixed; boundary="------------77124177B7BD8DDE7AFE703F" This is a multi-part message in MIME format. --------------77124177B7BD8DDE7AFE703F Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Come now, there must be more companies out there that want to be represented! Check your status below. jon Interest LOGO LOGO GOOD Apsim Yes YES Incases Yes YES Xilinx Yes YES NCSU Yes NO Hyperlynx Yes YES Viewlogic yes YES Cadence YES YES Mentor YES YES Intel NO NA Altera NO NA HP YES NO Cypress NO NA Compaq YES YES --------------77124177B7BD8DDE7AFE703F Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jon Powell Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Jon Powell n: Powell;Jon org: Viewlogic Consulting Services adr: 1369 Del Norte Rd.;;;Camarillo;CA;93010;USA email;internet: jonp@pacbell.net title: Manager High Speed Design Services tel;work: 805 988 8250 tel;fax: 805 988 8259 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------77124177B7BD8DDE7AFE703F-- From owner-ibis Wed Dec 16 23:46:00 1998 Received: from mail.huawei.com.cn ([202.96.135.132]) by server.eda.org (8.8.5/8.8.3) with ESMTP id XAA15096 for ; Wed, 16 Dec 1998 23:45:51 -0800 (PST) Received: from [10.102.11.125] by mail.huawei.com.cn (Netscape Mail Server v2.02) with SMTP id AAA7687; Thu, 17 Dec 1998 15:39:11 +0800 Message-ID: <3677636A.CE492EFC@huawei.com.cn> Date: Wed, 16 Dec 1998 15:38:18 +0800 From: zhangjian Reply-To: zhangjian@huawei.com.cn X-Mailer: Mozilla 4.01 [en] (Win95; I) MIME-Version: 1.0 To: xtk-support@viewlogic.com, ibis-users@eda.org, ibis@vhdl.org Subject: questions about XTK X-Priority: 3 (Normal) Content-Type: multipart/mixed; boundary="------------9DEDC6A3D6F200B06F092D1D" This is a multi-part message in MIME format. --------------9DEDC6A3D6F200B06F092D1D Content-Type: text/plain; charset=us-ascii Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-Transfer-Encoding: 7bit --------------9DEDC6A3D6F200B06F092D1D Content-Type: text/plain; charset=us-ascii; name="help1.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="help1.txt" HI, sir: I am a learner of XTK. I have some questions about XTK and I hope you can give me an answer quickly. 1. What is the maximum frequency that XTK can analyze properly? 2. Could XTK be used to analyze the skin effect ? if so,which parameter describe the degree of the skin effect? 3. I have performed a system level simulation with ISF2XTK. I use a *.mxf file to match a model to a connector. When analyzed the net including the connector, XNS reported some errors such as : Could not find model name matching JB8-1O2_TO_SON_3: U10_27 may be encrypted model. And, XNS do not use the connector model I defined,but use the default connector model, what can I do with it? 4. When I translate IBIS MODEL into XTK with IBIS2XTK , the program IBIS2XTK did not report any errors.But when analyze,XNS reported some errors such as : pin name no found for part son_3: c83 2 . This prevents package capacitance connection. And package parameter has not been loaded by the program XNS . 5. How to get the *.xf3 file which used as input file for program XFX3D? --------------9DEDC6A3D6F200B06F092D1D-- From owner-ibis Thu Dec 17 11:42:17 1998 Received: from mail-gw6.pacbell.net (mail-gw6.pacbell.net [206.13.28.41]) by server.eda.org (8.8.5/8.8.3) with ESMTP id LAA17597 for ; Thu, 17 Dec 1998 11:42:16 -0800 (PST) Received: from pacbell.net (ppp-209-79-182-101.vntrcs.pacbell.net [209.79.182.101]) by mail-gw6.pacbell.net (8.8.8/8.7.1+antispam) with ESMTP id LAA27034; Thu, 17 Dec 1998 11:37:27 -0800 (PST) Message-ID: <36795D73.A782C97C@pacbell.net> Date: Thu, 17 Dec 1998 11:37:23 -0800 From: Jon Powell Reply-To: jpowell@viewlogic.com Organization: Viewlogic Consulting Services X-Mailer: Mozilla 4.04 [en]C-PBI-NC404 (Win95; I) MIME-Version: 1.0 To: ibis@vhdl.org Subject: More breaking Logo News Content-Type: multipart/mixed; boundary="------------2EDDCCF36C73064CD4BAEE86" This is a multi-part message in MIME format. --------------2EDDCCF36C73064CD4BAEE86 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, Because of some legal complications that some companies have raised I have decided to making the following offer (good for a limited time). If you provide me with a finished company logo sign we can stick it on the booth together!! This means either send me the finished thing or bring it to Supercon. I will even have Velcro(c) for you!!! catches: 1) Sign MUST be NO larger 8.5X11 (inches) . that is, it must fit on a standard 8.5x11 inch piece of paper. It can be smaller but cannot exceed any dimension (ie. No 6 x 20 logos). 2) The sign may contain ONLY your logo and any official company tag that usually goes with the logo. (ie. no product specific verbiage). 3) The sign must be mounted on something firm enough that I can add Velcro(c) backing. If it does not meet these exacting standards, we won't put it on the booth. These rules are to insure fairness, not because I'm an SOB. SPECIAL NOTE: If you have already sent me a logo file and want me to continue to do the work for you, I will. However, if you want to provide you own just so you know how it will look before hand, just let me know. My goal here is to make it as easy as possible for everyone who wants to to be represented. regards, jon Jon Powell C/O Viewlogic 1369 Del Norte Rd. Camarillo CA 93010 --------------2EDDCCF36C73064CD4BAEE86 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jon Powell Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Jon Powell n: Powell;Jon org: Viewlogic Consulting Services adr: 1369 Del Norte Rd.;;;Camarillo;CA;93010;USA email;internet: jonp@pacbell.net title: Manager High Speed Design Services tel;work: 805 988 8250 tel;fax: 805 988 8259 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------2EDDCCF36C73064CD4BAEE86-- From owner-ibis Thu Dec 17 10:00:16 1998 Received: from mail-oak-3.pilot.net (mail-oak-3.pilot.net [198.232.147.18]) by server.eda.org (8.8.5/8.8.3) with ESMTP id KAA17272; Thu, 17 Dec 1998 10:00:16 -0800 (PST) Received: from gateway1.xilinx.com ([149.199.60.201]) by mail-oak-3.pilot.net with ESMTP id JAA13154; Thu, 17 Dec 1998 09:51:08 -0800 (PST) Received: from clavin.xsj.xilinx.com (clavin [149.199.36.199]) by gateway1.xilinx.com (8.8.7/8.8.7) with ESMTP id JAA26695; Thu, 17 Dec 1998 09:55:28 -0800 (PST) Received: from newman.xilinx.com (newman [149.199.37.215]) by clavin.xsj.xilinx.com (8.8.7/8.8.7) with ESMTP id JAA13704; Thu, 17 Dec 1998 09:53:35 -0800 (PST) Received: from xilinx.com ([149.199.9.206]) by newman.xilinx.com (Netscape Messaging Server 3.0) with ESMTP id AAA14066; Thu, 17 Dec 1998 09:54:33 -0800 Sender: "Rob Eccles" Message-ID: <3679455A.17B07E3C@xilinx.com> Date: Thu, 17 Dec 1998 09:54:34 -0800 From: Rob Eccles Organization: Xilinx, Inc. X-Mailer: Mozilla 4.05 [en] (X11; I; SunOS 5.5.1 sun4m) MIME-Version: 1.0 To: ibis@eda.org, ibis-users@eda.org Subject: Characterization Conditions Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I have read with interest the latest version of the IBIS cookbook. It details recommended characterization conditions for simulating TTL, ECL, LVCMOS, etc. It does not contain recommended conditions for measuring newer I/Os, i.e. SSTL, HSTL, GTL, LVDS. What are the recommended simulation conditions for these I/Os? Rob Eccles Xilinx rob.eccles@xilinx.com From owner-ibis Thu Dec 17 12:29:42 1998 Received: from ganymede.or.intel.com (ganymede.or.intel.com [134.134.248.3]) by server.eda.org (8.8.5/8.8.3) with ESMTP id MAA17812; Thu, 17 Dec 1998 12:29:41 -0800 (PST) Received: from ichips-jf.jf.intel.com (ichips-jf.jf.intel.com [134.134.50.200]) by ganymede.or.intel.com (8.9.1a/8.9.1/d: relay.m4,v 1.6 1998/11/24 22:10:56 iwep Exp iwep $) with ESMTP id UAA23313; Thu, 17 Dec 1998 20:24:53 GMT Received: from xtg801.pdx.intel.com (xtg801.pdx.intel.com [134.134.114.35]) by ichips-jf.jf.intel.com (8.8.8/8.8.7) with ESMTP id MAA04275; Thu, 17 Dec 1998 12:24:52 -0800 (PST) Received: from ichips.intel.com by xtg801.pdx.intel.com (8.8.8/WW2.2 (Jones Farm)) id MAA00634; Thu, 17 Dec 1998 12:24:52 -0800 (PST) Message-Id: <199812172024.MAA00634@xtg801.pdx.intel.com> X-Mailer: exmh version 2.0delta 6/3/97 To: Rob Eccles cc: ibis@eda.org, ibis-users@eda.org Subject: Re: Characterization Conditions In-reply-to: Your message of "Thu, 17 Dec 1998 09:54:34 PST." <3679455A.17B07E3C@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Thu, 17 Dec 1998 12:24:51 -0800 From: Stephen Peters Hello Rob: By "recommended characterization conditions" I assume you mean the output loads/voltages use to extract V/T waveforms. Because the GTL/GTL+ outputs are open-drain, I would extract the V/T waveforms using the rules for open drain buffers -- a load resistor to Vterm, with the value of Rterm and Vterm determined by the specification or part manufacturer. As for the other standards, if the driver uses a standard push/pull structure use the rules for standard CMOS or TTL (depending on the technology of the buffer). Remember: by taking the V/T waveforms with a load tied to Vcc then to ground, one can isolate the turn-on, turn-off and overlap times of the pullup and pulldown structures, thereby allowing the simulator to construct an accurate model of the driver. This model should be accurate, even if the driver application calls for the output to be terminated to Vcc/2, or series terminated, or whatever. Regards, Stephen Peters Intel Corp. > I have read with interest the latest version of the > IBIS cookbook. It details recommended characterization > conditions for simulating TTL, ECL, LVCMOS, etc. It > does not contain recommended conditions for measuring > newer I/Os, i.e. SSTL, HSTL, GTL, LVDS. > > What are the recommended simulation conditions for these > I/Os? > > Rob Eccles > Xilinx > rob.eccles@xilinx.com From owner-ibis Thu Dec 17 19:38:48 1998 Received: from mail.hyperlynx.com (root@mail.hyperlynx.com [209.20.148.70]) by server.eda.org (8.8.5/8.8.3) with ESMTP id TAA18464 for ; Thu, 17 Dec 1998 19:38:46 -0800 (PST) Received: from Kellee98 ([192.168.148.110]) by mail.hyperlynx.com (8.8.5/8.8.5) with SMTP id TAA25893; Thu, 17 Dec 1998 19:34:00 -0800 Message-Id: <199812180334.TAA25893@mail.hyperlynx.com> X-Sender: kellee@mail.nwlink.com X-Mailer: QUALCOMM Windows Eudora Pro Version 4.0 Date: Thu, 17 Dec 1998 19:34:01 -0800 To: ibis@vhdl.org From: Kellee Crisafulli Subject: .EBD question Cc: bvodall@hyperlynx.com Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by server.eda.org id TAA18465 Hello Ibisians, This came up in a conversation recently and I did not know the answer. How do you describe a loop in a trace layout with the [Path Description] in a .EBD file? For example: Pin 1 * * **** * * **** * * Pin 2 [Path Description] LOOP Pin 1 Len = 1.0 L = 1.0n C= 2.0p / Fork Len = 1.0 L = 1.0n C= 2.0p / Len = 1.0 L = 1.0n C= 2.0p / Len = 1.0 L = 1.0n C= 2.0p Endfork | |now what do I do to close the loop? | Len = 1.0 L = 1.0n C= 2.0p / Pin 2 --------------------------------------------------------- Have a great day.... Kellee Crisafulli at HyperLynx SI,EMC,X-talk and IBIS tools for the Windows platform E-mail: web:   --------------------------------------------------------- From owner-ibis Thu Dec 17 18:05:27 1998 Received: from mail-oak-3.pilot.net (mail-oak-3.pilot.net [198.232.147.18]) by server.eda.org (8.8.5/8.8.3) with ESMTP id SAA18349; Thu, 17 Dec 1998 18:05:27 -0800 (PST) Received: from gateway1.xilinx.com ([149.199.60.201]) by mail-oak-3.pilot.net with ESMTP id RAA11005; Thu, 17 Dec 1998 17:56:13 -0800 (PST) Received: from clavin.xsj.xilinx.com (clavin [149.199.36.199]) by gateway1.xilinx.com (8.8.7/8.8.7) with ESMTP id RAA09603; Thu, 17 Dec 1998 17:58:22 -0800 (PST) Received: from newman.xilinx.com (newman [149.199.37.215]) by clavin.xsj.xilinx.com (8.8.7/8.8.7) with ESMTP id RAA27052; Thu, 17 Dec 1998 17:56:29 -0800 (PST) Received: from xilinx.com ([149.199.9.206]) by newman.xilinx.com (Netscape Messaging Server 3.0) with ESMTP id AAA20545; Thu, 17 Dec 1998 17:57:26 -0800 Sender: "Rob Eccles" Message-ID: <3679B688.B2993E9D@xilinx.com> Date: Thu, 17 Dec 1998 17:57:28 -0800 From: Rob Eccles Organization: Xilinx, Inc. X-Mailer: Mozilla 4.05 [en] (X11; I; SunOS 5.5.1 sun4m) MIME-Version: 1.0 To: Stephen Peters CC: ibis@eda.org, ibis-users@eda.org Subject: Re: Characterization Conditions References: <199812172024.MAA00634@xtg801.pdx.intel.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Steve, Thanks for your prompt reply! After reading your response, and giving it some more thought, it looks like SSTL and HSTL should use the same methodology given in Table 1 for CMOS (from the 2.0X version of the Cookbook). In practise, not all boards will use 50 Ohm loads. How sensitive are the IBIS models to termination resistance? I would expect this to be significant. Regards, Rob Eccles Xilinx Stephen Peters wrote: > > Hello Rob: > > By "recommended characterization conditions" I assume you mean > the output loads/voltages use to extract V/T waveforms. Because the > GTL/GTL+ outputs are open-drain, I would extract the V/T waveforms > using the rules for open drain buffers -- a load resistor to > Vterm, with the value of Rterm and Vterm determined by the > specification or part manufacturer. As for the other standards, > if the driver uses a standard push/pull structure use the rules for > standard CMOS or TTL (depending on the technology of the buffer). > Remember: by taking the V/T waveforms with a load tied > to Vcc then to ground, one can isolate the turn-on, turn-off and > overlap times of the pullup and pulldown structures, thereby allowing > the simulator to construct an accurate model of the driver. This > model should be accurate, even if the driver application calls for > the output to be terminated to Vcc/2, or series terminated, or whatever. > > Regards, > Stephen Peters > Intel Corp. > > > I have read with interest the latest version of the > > IBIS cookbook. It details recommended characterization > > conditions for simulating TTL, ECL, LVCMOS, etc. It > > does not contain recommended conditions for measuring > > newer I/Os, i.e. SSTL, HSTL, GTL, LVDS. > > > > What are the recommended simulation conditions for these > > I/Os? > > > > Rob Eccles > > Xilinx > > rob.eccles@xilinx.com From owner-ibis Fri Dec 18 05:16:38 1998 Received: from mailhost.pii.com (mailhost.pii.com [192.77.209.1]) by server.eda.org (8.8.5/8.8.3) with ESMTP id FAA19898 for ; Fri, 18 Dec 1998 05:16:37 -0800 (PST) Received: from nashex.pii.com (nashex.pii.com [192.168.203.242]) by mailhost.pii.com (8.9.1/8.9.1) with ESMTP id FAA22006 for ; Fri, 18 Dec 1998 05:21:31 -0800 (PST) Received: by NASHEX with Internet Mail Service (5.5.1960.3) id ; Fri, 18 Dec 1998 08:09:41 -0500 Message-ID: <31F863AE4B2DD211A01900A0C9CFAD3C062FB0@NASHEX> From: Alex Golian To: ibis@vhdl.org Subject: New IBIS user Date: Fri, 18 Dec 1998 08:09:36 -0500 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.1960.3) Content-Type: text/plain I am just learning about IBIS. Can anyone recommend a book or know where on the WEB I can download reference material about IBIS and IBIS related material. I need to learn a lot about it and fast. I appreciate your responses. Thanks, Alex Golian Alex.golian@pii.com From owner-ibis Fri Dec 18 05:51:30 1998 Received: from smtp4.ny.us.ibm.COM (smtp4.ny.us.ibm.com [198.133.22.43]) by server.eda.org (8.8.5/8.8.3) with ESMTP id FAA19949; Fri, 18 Dec 1998 05:51:29 -0800 (PST) From: gedlund@us.ibm.com Received: from northrelay01.pok.ibm.com (northrelay01.pok.ibm.com [9.117.200.21]) by smtp4.ny.us.ibm.COM (8.8.7/8.8.7) with ESMTP id IAA53690; Fri, 18 Dec 1998 08:32:32 -0500 Received: from us.ibm.com (d51mta10.pok.ibm.com [9.117.200.38]) by northrelay01.pok.ibm.com (8.8.7m1/NCO v1.7) with SMTP id IAA218048; Fri, 18 Dec 1998 08:46:13 -0500 Received: by us.ibm.com(Lotus SMTP MTA Internal build v4.6.2 (651.2 6-10-1998)) id 852566DE.004BA053 ; Fri, 18 Dec 1998 08:46:02 -0500 X-Lotus-FromDomain: IBMUS To: Rob Eccles cc: ibis@vhdl.org, ibis-users@vhdl.org Message-ID: <852566DE.004B9FB5.00@us.ibm.com> Date: Fri, 18 Dec 1998 07:43:36 -0600 Subject: Re: Characterization Conditions Mime-Version: 1.0 Content-type: text/plain; charset=us-ascii Content-Disposition: inline Rob, In the case of a classic GTL driver (which uses feedback), you may also want to sweep the resistance to Vtt (Rterm) over its effective operational range. Then compare behavioral simulation waveforms against SPICE waveforms and see how close you can get. I found that the simulator I was using wasn't able to track SPICE very well. I've been told that multiple VT tables for different values for Rterm is one approach to solving the "GTL feedback behavioral modeling problem," but I've never actually heard the circuit theory behind this. I guess all I'm saying is run some SPICE vs. behavioral correlation and "model developer beware..." Greg Edlund Advisory Engineer, Critical Net Analysis IBM 3650 Hwy. 52 N, Dept. HDC Rochester, MN 55901 gedlund@us.ibm.com Rob Eccles on 12/17/98 07:57:28 PM To: Stephen Peters cc: ibis@eda.org, ibis-users@eda.org (bcc: Gregory R Edlund/Rochester/IBM) Subject: Re: Characterization Conditions Hi Steve, Thanks for your prompt reply! After reading your response, and giving it some more thought, it looks like SSTL and HSTL should use the same methodology given in Table 1 for CMOS (from the 2.0X version of the Cookbook). In practise, not all boards will use 50 Ohm loads. How sensitive are the IBIS models to termination resistance? I would expect this to be significant. Regards, Rob Eccles Xilinx Stephen Peters wrote: > > Hello Rob: > > By "recommended characterization conditions" I assume you mean > the output loads/voltages use to extract V/T waveforms. Because the > GTL/GTL+ outputs are open-drain, I would extract the V/T waveforms > using the rules for open drain buffers -- a load resistor to > Vterm, with the value of Rterm and Vterm determined by the > specification or part manufacturer. As for the other standards, > if the driver uses a standard push/pull structure use the rules for > standard CMOS or TTL (depending on the technology of the buffer). > Remember: by taking the V/T waveforms with a load tied > to Vcc then to ground, one can isolate the turn-on, turn-off and > overlap times of the pullup and pulldown structures, thereby allowing > the simulator to construct an accurate model of the driver. This > model should be accurate, even if the driver application calls for > the output to be terminated to Vcc/2, or series terminated, or whatever. > > Regards, > Stephen Peters > Intel Corp. > > > I have read with interest the latest version of the > > IBIS cookbook. It details recommended characterization > > conditions for simulating TTL, ECL, LVCMOS, etc. It > > does not contain recommended conditions for measuring > > newer I/Os, i.e. SSTL, HSTL, GTL, LVDS. > > > > What are the recommended simulation conditions for these > > I/Os? > > > > Rob Eccles > > Xilinx > > rob.eccles@xilinx.com From owner-ibis Fri Dec 18 06:29:36 1998 Received: from redac.co.uk (mail.redac.co.uk [195.99.246.2]) by server.eda.org (8.8.5/8.8.3) with SMTP id GAA20038 for ; Fri, 18 Dec 1998 06:29:35 -0800 (PST) Received: from redpo by redac.co.uk (5.0/SMI-SVR4) id AA04212; Fri, 18 Dec 1998 14:20:50 +0000 Received: from ACOL.redac.co.uk by redpo (SMI-8.6/Redac-Interior-Gateway-V1.1) id OAA15735; Fri, 18 Dec 1998 14:25:29 GMT Message-Id: <1.5.4.32.19981218143006.00c6f408@redpo> X-Sender: johnb@redpo X-Mailer: Windows Eudora Light Version 1.5.4 (32) Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Fri, 18 Dec 1998 14:30:06 +0000 To: ibis@vhdl.org From: John Berrie Subject: unsubscribe for vacation unsubscribe John Berrie Application Engineering Consultant Dynamic Solutions Zuken-Redac Research and Design Centre 1500 Aztec West Bristol BS2 4RF U.K. Tel: +44 (0)1454 207828 Ext. 8403 From owner-ibis Fri Dec 18 08:11:52 1998 Received: from calliope1.fm.intel.com (calliope1.fm.intel.com [132.233.247.10]) by server.eda.org (8.8.5/8.8.3) with ESMTP id IAA20235 for ; Fri, 18 Dec 1998 08:11:52 -0800 (PST) Received: from fmsmsx26.fm.intel.com (fmsmsx26.fm.intel.com [132.233.42.26]) by calliope1.fm.intel.com (8.9.1a/8.9.1/d: relay.m4,v 1.6 1998/11/24 22:10:56 iwep Exp iwep $) with ESMTP id QAA09433; Fri, 18 Dec 1998 16:07:03 GMT Message-Id: <199812181607.QAA09433@calliope1.fm.intel.com> Received: by FMSMSX26 with Internet Mail Service (5.5.2232.9) id ; Fri, 18 Dec 1998 08:06:58 -0800 From: "Muranyi, Arpad" To: "\"ibis@vhdl.org\" " , "\"Alex Golian\" " Subject: RE: New IBIS user Date: Fri, 18 Dec 1998 08:06:00 -0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2232.9) Content-Type: text/plain Try this first: http://www.eia.org/eig/ibis/ibis.htm Arpad ========================================================================= I am just learning about IBIS. Can anyone recommend a book or know where on the WEB I can download reference material about IBIS and IBIS related material. I need to learn a lot about it and fast. I appreciate your responses. Thanks, Alex Golian Alex.golian@pii.com From owner-ibis Fri Dec 18 10:21:25 1998 Received: from mailgate.cadence.com (mailgate.Cadence.COM [158.140.2.1]) by server.eda.org (8.8.5/8.8.3) with ESMTP id KAA20663 for ; Fri, 18 Dec 1998 10:21:24 -0800 (PST) Received: (from smap@localhost) by mailgate.cadence.com (8.8.5/8.6.8) id KAA27047; Fri, 18 Dec 1998 10:16:29 -0800 (PST) Received: from zip.Cadence.COM(158.140.103.36) by mailgate.cadence.com via smap (mjr-v1.2) id xma914004988.027037; Fri, 18 Dec 98 10:16:28 -0800 Received: from cadence.com (d15814010549 [158.140.105.49]) by zip.Cadence.COM (8.7.3/8.7.3) with ESMTP id NAA01618; Fri, 18 Dec 1998 13:16:25 -0500 (EST) Message-ID: <367A9BF8.9FEBF65B@cadence.com> Date: Fri, 18 Dec 1998 13:16:24 -0500 From: Mike LaBonte Organization: Cadence Design Systems X-Mailer: Mozilla 4.07 [en] (WinNT; U) MIME-Version: 1.0 To: Kellee Crisafulli CC: ibis@vhdl.org, bvodall@hyperlynx.com Subject: Re: .EBD question References: <199812180334.TAA25893@mail.hyperlynx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Kellee, The Fork/Endfork notation implements what is commonly called a Directed Acyclic Graph. The key term here is "acyclic", meaning you can not have loops. Notations that allow loops, like SPICE, almost always do so by naming the nodes so that multiple references into a node are accepted. Mike LaBonte Cadence Design Systems Kellee Crisafulli wrote: > > Hello Ibisians, > > This came up in a conversation recently and I did not > know the answer. > How do you describe a loop in a trace layout with the > [Path Description] in a .EBD file? > > For example: > Pin 1 > * > * > **** > * * > **** > * > * > Pin 2 > > [Path Description] LOOP > Pin 1 > Len = 1.0 L = 1.0n C= 2.0p / > Fork > Len = 1.0 L = 1.0n C= 2.0p / > Len = 1.0 L = 1.0n C= 2.0p / > Len = 1.0 L = 1.0n C= 2.0p > Endfork > | > |now what do I do to close the loop? > | > Len = 1.0 L = 1.0n C= 2.0p / > Pin 2 > > --------------------------------------------------------- > Have a great day.... > Kellee Crisafulli at HyperLynx > SI,EMC,X-talk and IBIS tools for the Windows platform > E-mail: > web: > --------------------------------------------------------- From owner-ibis Fri Dec 18 11:05:28 1998 Received: from mail.nwlink.com (root@mail.nwlink.com [209.20.130.40]) by server.eda.org (8.8.5/8.8.3) with ESMTP id LAA20749 for ; Fri, 18 Dec 1998 11:05:27 -0800 (PST) Received: from hyperstar (ip252.usr4.usw.du.nwlink.com [209.20.133.252]) by mail.nwlink.com (8.9.1a/8.9.1) with SMTP id LAA08755; Fri, 18 Dec 1998 11:00:06 -0800 (PST) Message-Id: <199812181900.LAA08755@mail.nwlink.com> X-Sender: kellee@mail.nwlink.com X-Mailer: QUALCOMM Windows Eudora Pro Version 4.0 Date: Fri, 18 Dec 1998 11:00:28 -0800 To: Mike LaBonte , ibis@vhdl.org From: Kellee Crisafulli Subject: Re: .EBD question In-Reply-To: <367A9BF8.9FEBF65B@cadence.com> References: <199812180334.TAA25893@mail.hyperlynx.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Hi Mike, all, Thanks for the reply. Unless some disagrees I would like to consider a Bird to correct this problem. The problem I see is that the node property can not be anything other than a component. We could add another property that is a non-component interconnect and fix this. best wishes... Kellee At 01:16 PM 12/18/98 -0500, you wrote: >Kellee, > >The Fork/Endfork notation implements what is commonly called a >Directed Acyclic Graph. The key term here is "acyclic", meaning >you can not have loops. Notations that allow loops, like SPICE, >almost always do so by naming the nodes so that multiple references >into a node are accepted. > >Mike LaBonte >Cadence Design Systems > >Kellee Crisafulli wrote: >> >> Hello Ibisians, >> >> This came up in a conversation recently and I did not >> know the answer. >> How do you describe a loop in a trace layout with the >> [Path Description] in a .EBD file? >> >> For example: >> Pin 1 >> * >> * >> **** >> * * >> **** >> * >> * >> Pin 2 >> >> [Path Description] LOOP >> Pin 1 >> Len = 1.0 L = 1.0n C= 2.0p / >> Fork >> Len = 1.0 L = 1.0n C= 2.0p / >> Len = 1.0 L = 1.0n C= 2.0p / >> Len = 1.0 L = 1.0n C= 2.0p >> Endfork >> | >> |now what do I do to close the loop? >> | >> Len = 1.0 L = 1.0n C= 2.0p / >> Pin 2 >> >> --------------------------------------------------------- >> Have a great day.... >> Kellee Crisafulli at HyperLynx >> SI,EMC,X-talk and IBIS tools for the Windows platform >> E-mail: >> web: >> --------------------------------------------------------- > From owner-ibis Fri Dec 18 11:18:56 1998 Received: from thalia.fm.intel.com (thalia.fm.intel.com [132.233.247.11]) by server.eda.org (8.8.5/8.8.3) with ESMTP id LAA20788 for ; Fri, 18 Dec 1998 11:18:56 -0800 (PST) Received: from fmsmsx18.intel.com (fmsmsx18.fm.intel.com [132.233.233.232]) by thalia.fm.intel.com (8.9.1a/8.9.1/d: relay.m4,v 1.6 1998/11/24 22:10:56 iwep Exp iwep $) with ESMTP id TAA18592; Fri, 18 Dec 1998 19:14:00 GMT Message-Id: <199812181914.TAA18592@thalia.fm.intel.com> Received: by FMSMSX18 with Internet Mail Service (5.5.2232.9) id ; Fri, 18 Dec 1998 11:14:00 -0800 From: "Hobbs, Will" To: "\"Mike LaBonte\" " , "\"ibis@vhdl.org\" " , "\"Kellee Crisafulli\" " Subject: RE: .EBD question Date: Fri, 18 Dec 1998 11:12:00 -0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2232.9) Content-Type: text/plain Could a zero ohm resistor be used to bridge the gap in the current spec? Will Hi Mike, all, Thanks for the reply. Unless some disagrees I would like to consider a Bird to correct this problem. The problem I see is that the node property can not be anything other than a component. We could add another property that is a non-component interconnect and fix this. best wishes... Kellee At 01:16 PM 12/18/98 -0500, you wrote: >Kellee, > >The Fork/Endfork notation implements what is commonly called a >Directed Acyclic Graph. The key term here is "acyclic", meaning >you can not have loops. Notations that allow loops, like SPICE, >almost always do so by naming the nodes so that multiple references >into a node are accepted. > >Mike LaBonte >Cadence Design Systems > >Kellee Crisafulli wrote: >> >> Hello Ibisians, >> >> This came up in a conversation recently and I did not >> know the answer. >> How do you describe a loop in a trace layout with the >> [Path Description] in a .EBD file? >> >> For example: >> Pin 1 >> * >> * >> **** >> * * >> **** >> * >> * >> Pin 2 >> >> [Path Description] LOOP >> Pin 1 >> Len = 1.0 L = 1.0n C= 2.0p / >> Fork >> Len = 1.0 L = 1.0n C= 2.0p / >> Len = 1.0 L = 1.0n C= 2.0p / >> Len = 1.0 L = 1.0n C= 2.0p >> Endfork >> | >> |now what do I do to close the loop? >> | >> Len = 1.0 L = 1.0n C= 2.0p / >> Pin 2 >> >> --------------------------------------------------------- >> Have a great day.... >> Kellee Crisafulli at HyperLynx >> SI,EMC,X-talk and IBIS tools for the Windows platform >> E-mail: >> web: >> --------------------------------------------------------- > From owner-ibis Fri Dec 18 09:50:34 1998 Received: from relay1.UU.NET (relay1.UU.NET [192.48.96.5]) by server.eda.org (8.8.5/8.8.3) with ESMTP id JAA20609; Fri, 18 Dec 1998 09:50:33 -0800 (PST) Received: from uucp3.uu.net by relay1.UU.NET with SMTP (peer crosschecked as: uucp3.uu.net [192.48.96.83]) id QQfuhz21439; Fri, 18 Dec 1998 12:45:24 -0500 (EST) Received: from qdt.UUCP by uucp3.uu.net with UUCP/RMAIL ; Fri, 18 Dec 1998 12:45:24 -0500 Received: from viewlogic.com by qdt.viewlogic.com (4.1/SMI-4.1) id AA14261; Fri, 18 Dec 98 09:38:06 PST Received: from chris by qdt.com (4.1/SMI-4.1) id AA22444; Fri, 18 Dec 98 09:37:59 PST Message-Id: <0a3801be2aac$c7c0b7b0$97c2b58b@chris.camarillo.viewlogic.com> From: "Chris Rokusek" To: "Rob Eccles" Cc: , Subject: Re: Characterization Conditions Date: Fri, 18 Dec 1998 09:35:18 -0800 Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-Msmail-Priority: Normal X-Mailer: Microsoft Outlook Express 4.72.3110.5 X-Mimeole: Produced By Microsoft MimeOLE V4.72.3110.3 Rob, Many simulators are interested in using results of driving the TRACE IMPEDANCE seen by the driver which is where the 50 came from. Vaguely speaking--using the range of the DC V-I curves exercised by the VT loading conditions together with the AC waveform data as inputs, the driver may then be applied to arbitrary loads (termination, capacitance, diodes, ...) in simulation to produce accurate results. So as long as the load is near (e.g. within .25X to 4X) the impedance that the driver sees during switching, simulation results should be nearly identical for most devices. DISCLAIMER: Simulators are not required to use the waveform data in any particular manner so the above may not be true for all simulators. However the cookbook recommendations were developed under consensus of simulator companies on the IBIS committee. Regards, Chris Rokusek Viewlogic Systems -----Original Message----- From: Rob Eccles To: Stephen Peters Cc: ibis@eda.org ; ibis-users@eda.org Date: Thursday, December 17, 1998 6:43 PM Subject: Re: Characterization Conditions >Hi Steve, > >Thanks for your prompt reply! > >After reading your response, and giving it some more thought, >it looks like SSTL and HSTL should use the same methodology >given in Table 1 for CMOS (from the 2.0X version of the Cookbook). > >In practise, not all boards will use 50 Ohm loads. How sensitive >are the IBIS models to termination resistance? I would expect >this to be significant. > >Regards, >Rob Eccles >Xilinx From owner-ibis Fri Dec 18 13:39:08 1998 Received: from mail.hyperlynx.com (root@mail.hyperlynx.com [209.20.148.70]) by server.eda.org (8.8.5/8.8.3) with ESMTP id NAA21056 for ; Fri, 18 Dec 1998 13:39:06 -0800 (PST) Received: from Kellee98 ([192.168.148.110]) by mail.hyperlynx.com (8.8.5/8.8.5) with SMTP id NAA31331; Fri, 18 Dec 1998 13:34:17 -0800 Message-Id: <199812182134.NAA31331@mail.hyperlynx.com> X-Sender: kellee@mail.nwlink.com X-Mailer: QUALCOMM Windows Eudora Pro Version 4.0 Date: Fri, 18 Dec 1998 13:34:21 -0800 To: Scott McMorrow , ibis@vhdl.org From: Kellee Crisafulli Subject: Re: .EBD question In-Reply-To: <367AC615.8E495B73@vasthorizons.com> References: <199812180334.TAA25893@mail.hyperlynx.com> <199812181900.LAA08755@mail.nwlink.com> <199812182043.MAA31003@mail.hyperlynx.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by server.eda.org id NAA21057 Hi Scott, Will, I think you and Will both suggested the 0 ohm resistor approach. Sounds like it will work to me and I hate changing the spec. At 01:16 PM 12/18/98 -0800, you wrote: >Yep, it will be easier than changing the spec. Loops become >problematic for simulations. How may loops will you allow? Our simulator has no problem with loops. They are stable and you can have an infinite number of them. >Loops are ugly, anyway. My manufacturing engineers >always veto the use of loops, if they notice them. I agree, but many boards do have them. Thanks for the feedback. Have a happy holiday! Kellee --------------------------------------------------------- Have a great day.... Kellee Crisafulli at HyperLynx SI,EMC,X-talk and IBIS tools for the Windows platform E-mail: web:   --------------------------------------------------------- From owner-ibis Tue Dec 22 13:02:38 1998 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id NAA29788 for ; Tue, 22 Dec 1998 13:02:37 -0800 (PST) Received: from em-wv03.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id MAA13600; Tue, 22 Dec 1998 12:57:18 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.8.8/CF5.40R) id MAA28546; Tue, 22 Dec 1998 12:57:15 -0800 (PST) From: bob_ross@mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA07192; Tue, 22 Dec 98 12:57:16 PST Date: Tue, 22 Dec 98 12:57:16 PST Message-Id: <9812222057.AA07192@bob> To: ibis@eda.org Subject: IBIS Uploaded Documents To All: In preparation for an IBIS Version 3.2 ratification vote on January 15, 1999, the following documents have been uploaded: (1) In http://www.eda.org/pub/ibis/wip/ 00readme - describes documents ver3_2f.ibs - latest draft Version 3.2 document showing addtions ver3_2.txt - document for voting (2) In http://www.eda.org/pub/ibis/birds/ bird56.1 - Approved BIRD56.1 (this will also be sent out) bird57.1 - approved BIRD57.1 (this will also be sent out) (3) In http://www/eda.org/pub/ibis/birds/ver3.2/ diff_pecl_term.ibs - a sample for BIRD56.1 bird57ex.ibs - a sample for BIRD57.1 Please review the ver3_2.txt document for voting and for editorial comments. (4) Also some documents for the December 7, 1998 IBIS Summit Meeting have been uploaded at: http://www.eda.org/pub/ibis/summits/dec98/ Bob Ross Interconnectix/Mentor Graphics From owner-ibis Tue Dec 22 13:03:45 1998 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id NAA29794 for ; Tue, 22 Dec 1998 13:03:44 -0800 (PST) Received: from em-wv03.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id MAA13643; Tue, 22 Dec 1998 12:58:25 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.8.8/CF5.40R) id MAA28703; Tue, 22 Dec 1998 12:58:23 -0800 (PST) From: bob_ross@mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA07195; Tue, 22 Dec 98 12:58:24 PST Date: Tue, 22 Dec 98 12:58:24 PST Message-Id: <9812222058.AA07195@bob> To: ibis@eda.org Subject: Approved IBIS BIRD56.1 To IBIS members: BIRD56.1 was approved at the December 18, 1998 with one editorial change documented by the "|**" line. An example showing the expanded functionality will be provided separately. Bob Ross Interconnectix/Mentor Graphics ****************************************************************************** ****************************************************************************** BIRD ID#: 56.1 ISSUE TITLE: Relaxation of [Series Pin Mapping] Restriction REQUESTER: Bob Ross, Mentor Graphics DATE SUBMITTED: November 25, 1998, December 18, 1998 DATE ACCEPTED BY IBIS OPEN FORUM: December 18, 1998 ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: [Series Pin Mapping] specifies connection only to Terminator or NC pins. This restricts using the Series elements for other purposes such as providing an internal differential termination to a differential input or output. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: In the [Series Pin Mapping] keyword below, the suggested change is shown in the revised paragraph that is bracketed by |* lines: |============================================================================= | Keyword: [Series Pin Mapping] | Required: No | Description: Used to associate two pins joined by a series model. | Sub-Params: pin_2, model_name, function_table_group | Usage Rules: Enter only series pin pairs. The first column, [Series Pin | Mapping], contains the series pin for which input impedances | are measured. The second column, pin_2, contains the other | connection of the series model. Each pin must match the pin | names declared previously in the [Pin] section of the IBIS | file. The third column, model_name, associates the Series or | Series_switch model for the pair of pins in the first two | columns. The fourth column, function_table_group, contains | an alphanumeric designator string to associate those sets of | Series_switch pins that are switched together. | | Each line must contain either three or four columns. When | using four columns, the header function_table_group must be | listed. | | One possible application is to model crossbar switches where | the straight through On paths are indicated by one designator | and the cross over On paths are indicated by another | designator. If the model referenced is a Series model, then | the function_table_group entry is omitted. | | Column length limits are: | [Series Pin Mapping] 5 characters max | pin_2 5 characters max | model_name 20 characters max | function_table_group 20 characters max | | Other Notes: If the model_name is for a non-symmetrical series model, | then the order of the pins is important. The [Series Pin | Mapping] and pin_2 entries must be in the columns that | correspond with Pin 1 and Pin 2 of the referenced model. | | This mapping covers only the series paths between pins. The | package parasitics and any other elements such as additional | capacitance or clamping circuitry are defined by the | model_name that is referenced in the [Pin] keyword. The | model_names under the [Pin] keyword that are also referenced | by the [Series Pin Mapping] keyword must be either 'NC' or | reference a [Model] whose Model_type is 'Terminator'. Thus. | for example, a Series_switch model may contain Terminator | models on EACH of the pins to describe both the capacitance | on each pin and some clamping circuitry that may exist on | each pin. | | |* Replace the above Paragraph with this Paragraph: | This mapping covers only the series paths between pins. The | package parasitics and any other elements such as additional | capacitance or clamping circuitry are defined by the | model_name that is referenced in the [Pin] keyword. The | model_names under the [Pin] keyword that are also referenced | by the [Series Pin Mapping] keyword may include any legal |** model or reserved model except for Series and Series_switch | models. Normally the pins will reference a [Model] whose | Model_type is 'Terminator'. For example, a Series_switch | model may contain Terminator models on EACH of the pins to | describe both the capacitance on each pin and some clamping | circuitry that may exist on each pin. In a similar manner, | Input, I/O or Output models may exist on each pin of a Series | model that is serving as a differential termination. |* End of Revised Paragraph. |----------------------------------------------------------------------------- [Series Pin Mapping] pin_2 model_name function_table_group | 2 3 CBTSeries 1 | Four independent groups 5 6 CBTSeries 2 9 8 CBTSeries 3 12 11 CBTSeries 4 | 22 23 CBTSeries 5 | Straight through path 25 26 CBTSeries 5 22 26 CBTSeries 6 | Cross over path 25 23 CBTSeries 6 | 32 33 Fixed_series | No group needed | ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: BIRD41.8 discusses some background for the initial restriction in its ANALYSIS ... section. In particular, the evolution through BIRD41.3 and BIRD41.4 documents that simplicity was the original reason for restricting the connecting pins of [Series Pin Mapping] to Terminators and NC. It was also left as a simulator specific extension that POWER or GND Pins could also be used. (See http://www.eda.org/pub/ibis/birds and select BIRD41.8.) The fact that Input, Output, and I/O pins were excluded meant that the series element could not be used to provide differential connections between pins. BIRD56 fixes this problem. Because legal reserved words are permitted, any of the pins may be connected to POWER, GND or NC pins, as needed. The major argument for relaxing the restriction is that some of these extended cases permit additional practical connection configurations. There was not a technical reason for maintaining the restriction. BIRD56.1 has some editorial changes approved at the meeting. The language "reserved word" was changed to "reserved model" since one reserved word "NA" is not included. "Reserved model" is defined in Section 3 to include only POWER, GND, and NC, as intended. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: IBIS reflector discussion between October 7 - 12, 1998 discussed this issue. Chris Rokusek in response to some discussions with Arpad Muranyi raised the original clarification question and also supported a BIRD which would relax the restriction. At the November 20, 1998 IBIS meeting, this issue was discussed. The action was to issue this BIRD for further discussion and resolution. ****************************************************************************** From owner-ibis Tue Dec 22 13:04:40 1998 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.8.5/8.8.3) with ESMTP id NAA29802 for ; Tue, 22 Dec 1998 13:04:39 -0800 (PST) Received: from em-wv03.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id MAA13676; Tue, 22 Dec 1998 12:59:20 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.8.8/CF5.40R) id MAA28830; Tue, 22 Dec 1998 12:59:18 -0800 (PST) From: bob_ross@mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA07198; Tue, 22 Dec 98 12:59:19 PST Date: Tue, 22 Dec 98 12:59:19 PST Message-Id: <9812222059.AA07198@bob> To: ibis@eda.org Subject: Approved IBIS BIRD57.1 To IBIS members: BIRD57.1 was approved at the December 18, 1998 meeting with minor editorial changes noted by the "|**" lines. Bob Ross Interconnectix/Mentor Graphics ****************************************************************************** ****************************************************************************** BIRD ID#: 57.1 ISSUE TITLE: Timed Bus Hold Extension REQUESTER: Bob Ross, Mentor G., Arpad Muranyi & Stephen Peters, Intel DATE SUBMITTED: December 4, 1998, December 18, 1998 DATE ACCEPTED BY IBIS OPEN FORUM: December 18, 1998 ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: A new application of the bus hold functionality involves turning off (putting in a Hi Z state) the bus hold circuitry after a period of time. The Bus_hold submodel can be extended to support this functionality with the addition of a delay subparameter in the [Submodel Spec] keyword. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The unofficial IBIS Version 3.2 document that includes the BIRD48.4, BIRD49.4 and BIRD50.3 extensions is used as the basis for showing how BIRD57 would be implemented. The original [Submodel Spec] keyword is modified by the addition of a new subparameter called Off_delay. The changes are indicated by an asterisk at the beginning of each line (|*) that it effects. |============================================================================= | Keyword: [Submodel Spec] | Required: No | Description: The [Submodel Spec] keyword defines four columns under which | specification and information subparameters are defined for | submodels. |* Sub-Params: V_trigger_r, V_trigger_f, Off_delay | | Usage Rules: The [Submodel Spec] is to be used only with submodels. | | The following subparameters are used: | V_trigger_r Rising edge trigger voltage | V_trigger_f Falling edge trigger voltage |* Off_delay Turn-off delay from V_trigger_r |* or V_trigger_f |* | For each subparameter contained in the first column, the | remaining three hold its typical, minimum and maximum values. | The entries of typical, minimum and maximum be must be placed | on a single line and must be separated by at least one white |** space or tab character. All four columns are required | under the [Submodel Spec] keyword. However, data is required | only in the typical column. If minimum and/or maximum values | are not available, the reserved word "NA" must be used to | indicate the typical value by default. | | The values in the minimum and maximum columns usually | correspond to the values in the same columns for the inherited | top-level voltage range or reference voltages in the top-level |* model. The V_trigger_r and V_trigger_f subparameters |* should hold values in the minimum and maximum columns that |* correspond to the voltage range or reference voltages of the |* top-level model. The Off_delay subparameter, however, is an |* exception to this rule because in some cases it may be |* completely or partially independent from supply voltages |* and/or manufacturing process variations. Therefore the |* minimum and maximum entries for the Off_delay subparameter |* should be ordered simply by their magnitude. | | Unless noted, each [Submodel Spec] subparameter is independent | of any other subparameter. | | V_trigger_r, V_trigger_f rules: | | The voltage trigger values for the rising and falling edges | provide the starting time when an action is initiated. | |* Off_delay rules: |* |* The functionality of the Off_delay subparameter is to provide |* an additional time related mechanism to turn off circuit |* elements. |* |----------------------------------------------------------------------------- | Dynamic Clamp Example: | [Submodel Spec] | Subparameter typ min max | V_trigger_r 3.6 2.9 4.3 | Starts power pulse table V_trigger_f 1.4 1.2 1.6 | Starts gnd pulse table | | Bus Hold Example: | [Submodel Spec] | Subparameter typ min max V_trigger_r 3.1 2.4 3.7 | Starts low to high | bus hold transition V_trigger_f 1.8 1.6 2.0 | Starts high to low | bus hold transition |**** New Example added here | | Bus_hold application with pullup structure triggered on and then clocked off: | [Submodel Spec] | Subparameter typ min max V_trigger_r 3.1 2.4 3.7 | Low to high transition | triggers the turn on | process of the pullup V_trigger_f -10.0 -10.0 -10.0 | Not used, so trigger | voltages are set out | of range Off_delay 5n 6n 4n | Time from rising edge | trigger at which the | pullup turned off | |**** End of new example The revised Bus Hold Section shows modifications by |* lines to document the new Off_delay subparameter and application information including a new example: |============================================================================= | | Bus Hold: | | When the Submodel_type subparameter under the [Submodel] keyword is set to | Bus_hold, the added model describes the bus hold functionality. However, | while described in terms of bus hold functionality, active terminators | can also be modeled. | | Existing keywords and subparameters are used to describe bus hold models. | The [Pullup] and [Pulldown] tables both are used to define an internal | buffer that is triggered switch to its opposite state. This switching | transition is specified by a [Ramp] keyword or by the [Rising Waveform] | and [Falling Waveform] keywords. The usage rules for these keywords are the | same as under the [Model] keyword. In particular, at least either the | [Pullup] or [Pulldown] keyword is required. Also, the [Ramp] keyword is | required, even if the [Rising Waveform] and [Falling Waveform] tables exist. | However, the voltage ranges and reference voltages are inherited from the | top-level model. | |* For bus hold submodels, the [Submodel Spec] keyword, V_trigger_r, and |* V_trigger_f are required. The Off_delay subparameter is optional, but |* can only be used if the submodel consists of a pullup or a pulldown |* structure only, and not both. Devices which have both pullup and pulldown |* structures controlled in this fashion can be modeled using two submodels, |* one for each half of the circuit. | | The transition is triggered by action at the die using the [Submodel Spec] | V_trigger_r and V_trigger_f subparameters as follows: | | If the starting voltage is below V_trigger_f, then the bus hold model is | set to the low state causing additional pulldown current. If the starting | voltage is above V_trigger_r, the bus hold model is set to the high | state for additional pullup current. When the input passes though | V_trigger_f during a high-to-low transition at the die, the bus hold output | switches to the low state. Similarly, when the input passes though | V_trigger_r during a low-to-high transition at the die, the bus hold output | switches to the high state. | |* If the bus hold submodel has a pullup structure only, V_trigger_r provides |* the time when its pullup is turned on and V_trigger_f or Off_delay provides |* the time when it is turned off, whichever occurs first. Similarly, if the |* submodel has a pulldown structure only, V_trigger_f provides the time when |* its pulldown is turned on and V_trigger_r or Off_delay provides the time |* when it is turned off, whichever occurs first. The required V_trigger_r |* and V_trigger_f voltage entries can be set to values outside of the input |* signal range if the pullup or pulldown structures are to be held on until |* the Off_delay turns them off. |* |** The starting mode for each of the submodels which include the Off_delay |* subparameter of the [Submodel Spec] keyword is the off state. Also, while |* two submodels provide the desired operation, either of the submodels may |** exist without the other to simulate turning on and off only a pullup or a |* pulldown current. |* | No additional keywords are needed for this functionality. |----------------------------------------------------------------------------- | | Complete Bus Hold Model Example: | [Submodel] Bus_hold_1 Submodel_type Bus_hold | [Submodel Spec] | Subparameter typ min max | V_trigger_f 1.3 1.2 1.4 | Falling edge trigger V_trigger_r 3.1 2.6 4.6 | Rising edge trigger | | typ min max | [Voltage Range] 5.0 4.5 5.5 | Note, the actual voltage range and reference voltages are inherited from | the top-level model. | [Pulldown] | -5V -100uA -80uA -120uA -1V -30uA -25uA -40uA 0V 0 0 0 1V 30uA 25uA 40uA 3V 50uA 45uA 50uA 5V 100uA 80uA 120uA 10v 120uA 90uA 150uA | [Pullup] | -5V 100uA 80uA 120uA -1V 30uA 25uA 40uA 0V 0 0 0 1V -30uA -25uA -40uA 3V -50uA -45uA -50uA 5V -100uA -80uA -120uA 10v -120uA -90uA -150uA | |----------------------------------------------------------------------------- | [Ramp] | typ min max dV/dt_r 2.0/0.50n 2.0/0.75n 2.0/0.35n dV/dt_f 2.0/0.50n 2.0/0.75n 2.0/0.35n R_load = 500 | |** A Second Example is inserted below | |----------------------------------------------------------------------------- | | Complete Pullup Timed Latch Example: | [Submodel] Timed_pullup_latch Submodel_type Bus_hold | [Submodel Spec] | Subparameter typ min max | V_trigger_r 3.1 2.6 4.6 | Rising edge trigger | Values could be set out | of range to disable the | trigger V_trigger_f 1.3 1.2 1.4 | Falling edge trigger Off_delay 3n 5n 2n | Delay to turn off the | pullup table | | Note that if the input signal goes above the V_trigger_r value, the | pulldown structure will turn off even if the timer didn't expire yet. | | typ min max | [Voltage Range] 5.0 4.5 5.5 | Note, the actual voltage range and reference voltages are inherited from | the top-level model. | [Pulldown] | -5V -100uA -80uA -120uA -1V -30uA -25uA -40uA 0V 0 0 0 1V 30uA 25uA 40uA 3V 50uA 45uA 50uA 5V 100uA 80uA 120uA 10v 120uA 90uA 150uA | | [Pullup] table is omitted to signal Open_source functionality | |----------------------------------------------------------------------------- | [Ramp] | typ min max dV/dt_r 2.0/0.50n 2.0/0.75n 2.0/0.35n dV/dt_f 2.0/0.50n 2.0/0.75n 2.0/0.35n R_load = 500 | |** End of Second Example |============================================================================= ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: BIRD57 is basically an extension of BIRD50.3. BIRD50.3 describes a static bus hold circuit which is controlled only by the pad voltage of the device. However, some devices can have the bus hold circuits which are turned on by the pad voltage, but are turned off by an internal timer of clock signal. These devices could not be modeled using the BIRD50.3 extensions. BIRD57 provides the extension to model such devices. Several approaches were considered: Modify or Enhance the [Driver Schedule] keyword for Input models (perhaps including a new keyword) Create a new Submodel_type for 'Timed_latch' as a new Submodel extension Enhance the Bus_hold Submodel The first choice builds upon an older approach versus the newer, preferred Submodel approach. The second choice was considered, but in our discussions we would have had to document mew meanings for some transition relationships related to a desired Hi-Z mode. The third choice was selected because the existing Bus Hold description for "Open_drain" or Open_source" functionality could be easily extended. The off state of an Open_* device is equivalent to a Hi-Z mode. Two Submodels are used since the off transition of each of the Submodels can be entered by the [Ramp] information or corresponding [Rising Waveform] or [Falling Waveform] table. A single Submodel is permitted for just turning on and off a pullup or pulldown current. BIRD57.1 is issued with some minor editoral changes captured at the December 18, 1998 IBIS meeting. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: BIRD57 evolved from discussions between Bob Ross, Arpad Muranyi, and Stephen Peters on December 3, 1998 to resolve how IBIS Version 3.2 would handle a new active latch that is being implemented in digital buffers. ****************************************************************************** From owner-ibis Wed Dec 23 15:41:24 1998 Received: from mail.hyperlynx.com (root@mail.hyperlynx.com [209.20.148.70]) by server.eda.org (8.8.5/8.8.3) with ESMTP id PAA03119 for ; Wed, 23 Dec 1998 15:41:15 -0800 (PST) Received: from tensor ([192.168.148.75]) by mail.hyperlynx.com (8.8.5/8.8.5) with SMTP id PAA00744 for ; Wed, 23 Dec 1998 15:36:24 -0800 Message-Id: <3.0.5.32.19981223153741.010c1dc0@mail.nwlink.com> X-Sender: mbflora@mail.nwlink.com X-Mailer: QUALCOMM Windows Eudora Pro Version 3.0.5 (32) Date: Wed, 23 Dec 1998 15:37:41 -0100 To: ibis@eda.org From: Matthew Flora Subject: IBIS Summit Meeting Minutes 18 Dec 1998 Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" DATE: 12/23/98 SUBJECT: 12/18/98 EIA IBIS Open Forum Minutes VOTING MEMBERS AND 1998 PARTICIPANTS LIST: AMP (Martin Freedman) Applied Simulation Technology Norio Matsui, Raj Raghuram Cadence Design (& UniCAD) C. Kumar, Don Telian, Patrick Riffault, Craig Lewis, Greg Fitzgerald, Paul Galloway, Patrick Dos Santos, Catherine Weiss, Alain Tribaudot, Geoffrey Ellis, Todd Westerhoff*, Ken Willis, Mike LaBonte* Cisco Systems Syed Huq*, Sergio Camerlo, Irfan Elahi Compaq Shariq Rahma, Jeff Chu, Bob Haller*, (Digital Equipment Corp.) Doug Burns, Steve Coe Cypress Bruce Wenniger H.A.S. Electronics Haruny Said Hewlett Packard (EEsof, etc.) Karl Kachigan, Henry Wu, Paul Gregory, Brenda Arena, Hans Wiggers High Design Technology Razvan Ene HyperLynx Kellee Crisafulli, Matthew Flora*, Gene Garat, Dave Kohlmeier Incases Olaf Rethmeier*, Scott Jacobson, Werner Rissiek Intel Corporation Stephen Peters*, Arpad Muranyi*, Frank Kern, (& formerly NCR) Will Hobbs, Prakash Radhakrishnan, Mohammed Hawana, Martin Chang, Dave Moxley, Tim Schreyer, Lyndell Asbenson LSI Logic (Symbios Logic) Larry Barnes Mentor Graphics (Zeelan, Bob Ross*, George Opsahl, Mark Noneman, Interconnectix, etc.) Tom Dagostino, Karine Loudet, Jean Oudinot, Manuel De Almeida, Stephane Rousseau, Neven Orhanovic, Mohamed Mahmoud, Kevin Cohan Mitsubishi Tam Cao Motorola (Ron Werner) National Semiconductor Cheng-Yang Kao, John Goldie, Ikchang Song, Milt Schwartz North East Systems Associates Edward Sayre, Kathy Breda, Michael Baxter, (NESA) Jon Green, Jinhua Chen NEC (Hiroshi Matsumoto) Quantic EMC (Mike Ventham) Texas Instruments Thomas Fisher, Harvey Stiegler, Vincent Chang, Jean-Claude Perrin*, Peter Forstner Thomson-CSF Jean-Marc Claveau, Laurent Duzaic, Saverio Lerose, Benoit Meyniel, Jean Lefebvre Viewlogic Jon Powell, Chris Rokusek*, Guy de Burgh, Gary Mandel VeriBest Ian Dodd, David Weins, Ian Gabbitas VLSI Technology D.C. Sessions, Derwin Mattos Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1998: 3Com Steve Miller 3Dfx Interactive Ken Wu A.T.Sinker Tony Sinker Actel Eric Tardif, Emmonvelle Gaudin Aerospatiale Lionel Dreux, Claude Huet Alcatel (Bell, Espace, etc.) John Fitzpatrick, W. Temmerman, Laure Bessettes, Jean-Claude Pourtau, Daniel Peron ALS Design Yves Mouquet Ansoft Eric Bogatin Apple Fred Floresca, Danny Itani Apteq Design Systems Dan FitzPatrick Atmel Ali Baktashian Avanti Nik Bannov CERN Olivier Clere, Jean-Michel Sainson, Rudi Zurbroken Corning John Nieznanski Crucial Technology Rathna Reddy DIVA Corp Tieng Nguyen Dynamic Research Corporation Mike Walsh EIA Patti Rusher EMC Fawn Engelmann, Fabrizio Zanella ENST, Paris Jean-Jacques Charlot European CAD Standardization Adam Morawiec Intitiative (ECSI) Fairchild Semiconductor Peter LaFlamme Focus Technology John Salzillo, Gary Brophy, Mike Arieta, Jim Skane Hyundai Farhad Tabrizi IBM Richard Steinle, Kevin Jackson, Greg Edlund, Douglas Stout InRange Elliot Lipin Intracon Design Ltd. Derek Laidlaw LG Semicon America Michael Spooer, Seung-Tae Lee Micron Technology Terry Lee Molex Gus Panella Philips Semiconductor Todd Andersen Rockwell Semiconductor Tim Gilbert Scottish Electronics Robert Easson Manufacturing Center (SEMC) Seagate Vanessa Howard Signal Integrity Software Barry Katz SGS-Thomson Philippe Lefevre Siemens Gerald Bannert, Bernhard Unger, Christian Marot, Miguel Hernandez, Gil Russell, Hartmud Terletzki SSEI Tom Hawkins Stratus Bruce Heilbrunn, Steve Mango, Lewis Steiner, Karla Eignor, Rich Newell Summit Computer Systems Bob Davis Sun Microsystems Lam Dong, Kevin Ko, Tay Ansari, Ken Weiss, Derek Tsai Symmetry Andy Hughes Tektronix Nassrin Ghahyasi, Tom Brinkoetter, Brad Weber, John Rettig Teradyne Michael Khusid Time Domain Analysis Systems Dima Smolyansky* Transmeta Bill Gervasi TranSwitch Bill Todd TRILOGIC Joe Socha Ultratest International Chris O'Connor Xilinx Susan Wu, Rob Eccles In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode January 15, 1999 (916) 356-9200 4-213768 9879517 Monday, February 1, 1998 IBIS Summit Meeting - No Teleconference All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM No new participants. MEMBERSHIP UPDATE AND TREASURER'S REPORT No change reported. REVIEW OF MINUTES AND AR'S No corrections. The ARs will be discussed during the meeting. MISCELLANY/ANNOUNCEMENTS None. PRESS AND WEB PAGE UPDATES Syed Huq reported several logo updates on the IBIS home page Poster link. Syed also reported that he added the Accuracy Info link to the EIA IBIS Home Page. NEW MODELS AVAILABLE, LIBRARY UPDATE Bob Ross reported that the American Microsystems, Inc IBIS models can now be found at: http://www amis.com/tgp/index2.html The Cypress Link has been changed to: http://www.cypress.com/design/support/models/index.html Micron Technology is updating their site: http://www.micron.com:80/mti/msp/models/index.html Also, Micron Technology IBIS models can requested at: http://www.micron.com/mti/msp/html/sim.html Texas Instruments has changed the link for Clock Distribution models to: http://www.ti.com/sc/docs/msp/cdc/ibis.htm OPENS FOR NEW ISSUES None. INTERNATIONAL/EXTERNAL PROGRESS - IEC 62014-1 (IBIS Version 2.1) - No report. - pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits (IMIC) - Bob Ross reported that IMIC topics were discussed at the IBIS Summit Meeting on December 7, 1998. - IEC 93/67/NP IBIS and EMC Simulation - Bob Ross reports that although the task group is operating at zero level, Jean-Claude Perrin reports that he will present the document to IEC Central Office as an official document during the TC77 (all EMC domains) meeting in Geneva. Jean-Claude reported a meeting was held and the plan is to write a short file in an IBIS format for a future buffer. This work is funded by Texas instruments and sponsored by a French university. The work is expected to be completed by the end of 1999, but an initial, work in progress document is expected to be made available for review in two to three months. Bob indicated that he would put the work in the work in progress area. - JC-16.2 Subcommittee: Modeling and Test - Bob Ross noted that the co-located JEDEC JC-16.2 and IBIS Meeting will be discussed below. - IEEE P1537 Electronic Data Format Project (Previously listed as the Standard Component Data Sheet) - Stephen Peters had no further report. IBIS (EAST) USERS GROUP MEETINGS Bob Haller stated that no formal IBIS Users Group meetings have occurred. However, the Connector Committee is meeting regularly and continuing its work. Also the Accuracy Committee is continuing its work on the draft Accuracy Specification document via regular teleconference meetings held on every other Friday on dates that do not conflict with the IBIS Open Forum meeting dates. The plan is to open up these meetings to everyone after DesignCon99. Bob noted that the Accuracy Committee is interested in what is needed for formal EIA approval. Bob Ross will talk to Bob Haller off line on some of the steps. The immediate Committee goals are to finalize the trailer document format before DesignCon99 and to focus on DesignCon99 preparation. JEDEC/IBIS DECEMBER 7, 1998 SUMMIT MEETING (REVIEW) Bob Ross commented that it was beneficial to meet several active JEDEC members from semiconductor vendors who are interested in IBIS activities. Along with several planned presentations, we had several good ad hoc presentations and discussions. Bob and Chris Rokusek did an ad hoc presentation at the JEDEC committee which appears to have been well received. Added note - the IBIS Summit documents, including several presentations, are uploaded at http://www.eda.org/pub/ibis/summits/dec98 DESIGNCON99 FEBRUARY 1, 1999 SUMMIT MEETING Bob Ross summarized the activity to date that the IBIS Open Forum is an Associate Sponsor of DesignCon99. As a result, DesignCon99 is providing a meeting room, refreshments, and a booth at the exhibition. National Semiconductor will be a co-sponsor and provide the buffet lunch. Milt Schwartz will be handling the local logistics including signup, collecting and copying the presentations that are submitted beforehand. The first call for participation has been sent out. Bob Haller noted that the Accuracy Committee will provide a small demo at the booth. Hewlett-Packard has agreed to supply equipment for capturing waveforms and for taking TDR measurements. Bob noted that Jon Powell is the focal point for logistics. Based on reflector email, Jon will accept company logos directly on velcro backed 8-1/2 by 11 inch placards. DATE99 MARCH 9, 1999 SUMMIT MEETING Bob Ross stated that the meeting time had been moved from Friday, March 12, 1999 to Tuesday, March 9, 1999 to avoid conflict with the trade show. At the DATE98 show in Paris, the IBIS meeting was scheduled on Friday to avoid such conflict. At this years show in Munich, the DATE99 trade show is from Wednesday through Friday. Bob noted and Olaf Rethmeier confirmed that INCASES will be a co-sponsor. Bob will work offline with others concerning additional co-sponsorship. Bob also expects to get initial information out in early January, 1999. VERSION 3.2 PARSER DEVELOPMENT Bob Ross indicated that he communicated the BIRD55 change regarding adding a Vmeas subparameter to the [Model Spec] keyword to Atul Agarwal, and Atul will make the ibischk3 change. Matthew Flora had commented that some minor corrections were needed so that that ibischk3 would compile with GNU and Microsoft compilers without warnings. For example, some comparisons between unsigned integers and signed integers ought to be fixed. Matthew stated that these minor changes were not yet sent to Atul. Matthew wanted Atul to continue with higher priority functional changes and the minor corrections to eliminate warnings could be made later. Bob indicated that those changes could be included in the next revision of the accepted parser. Matthew indicated that he received good response to a note he sent to the parser distribution list inviting those who were not on the ibischk-bug@eda.org "reflector" to join. People on that list will be receiving the latest bug reports, details, and questions on ibischk3 development. Bob stated that he uploaded ver3_2e.ibs in the work in progress directory with BIRD55 included. He expected to upload ver3_2f.ibs based on how BIRD56 and BIRD57 are resolved later in this meeting. TEKTRONIX IPA 510 SOFTWARE DISTRIBUTION PROPOSAL Bob Ross moved this discussion to the end of the meeting to allow time for dealing with the scheduled technical issues. COOKBOOK STATUS (Not Discussed) IBIS MODEL REVIEW COMMITTEE DISCUSSION Matthew Flora reported that he distributed a Texas Instruments Version 2.1 level LVDS IBIS model with for review. The old AR remains. AR - Matthew Flora to issue to the IBIS reflector a short write-up on the IBIS Model Review Committee. BIRD56 - RELAXATION OF THE [Series Pin Mapping] RESTRICTION Bob Ross introduced BIRD56 for discussion and vote. Matthew Flora wanted an example showing the expanded functionality. Arpad Muranyi promised an example from a model which provided the original motivation for BIRD56. Bob also indicated the he might provide an example using a Series element as a differential termination. AR - Arpad Muranyi provide an IBIS model example for BIRD56. There was some discussion indicating that removing the original limitation was motivated by practical considerations with real devices. The original limitation was not based on any technical need, but on consistency with the terminator models. Matthew suggested changing "reserved words" to "reserved models" since the reserved word "NA" was not intended to be included in the list. Matthew showed in Section 3 (General Syntax Rules and Guidelines), that item 2) documents this distinction. Bob accepted this change (thereby incrementing BIRD56 to BIRD56.1). A vote was taken. BIRD56.1 was approved unanimously with one abstention. AR - Bob Ross produce BIRD56.1 with the agreed upon editorial corrections. BIRD57 - TIMED BUS HOLD EXTENSION Arpad Muranyi introduced the recently submitted BIRD57 by indicating that a current implementation of the bus hold submodel has the model turn off using an internal timer or external trigger signal. The "Off_delay" parameter provides the additional functionality to deal with this capability. Bob Ross added that the bus hold functionality has been expanded in practice to include a high-Z mode. Since transitions from an on state to/from a high-Z state is not included in any current IBIS model time transitions for totem pole topologies, an alternative way is suggested in practice. The Open_drain (Open_sink) and Open_source configurations can each be viewed as transitioning from an on state to a high-Z state. An Open_source and Open_sink submodels can be used together to describe transitions from high-Z, both from a low and high state. Arpad clarified that when the Off_delay is defined, it is for a submodel with either just a [Pullup] table (for Open_source mode) or a [Pulldown] table (for Open_sink mode). Arpad stated that both V_trigger_r and V_trigger_f are required, So the switching can occur either due to the signal at the input pad switching or due to reaching the Off_delay time, which ever comes first. If the trigger voltage is out of range, then it will not be used. Or if the Off_delay is set to a very long value, the timed mode will be disabled. Mike Lebonte asked for clarification regarding when the Off_delay begins. Arpad clarified that it begins when the signal at the input pad crosses the trigger threshold. Matthew Flora had two editorial changes to remove a redundant "tab" statement and to add a missing "the" word. Bob had an editorial change from using the the verb "model" to the verb "simulate". These changes were accepted and caused BIRD57 to be incremented to BIRD57.1. Mike suggested that Off_delay be made more specific and refer to it being referenced from a trigger voltage rather than an external clock. After further discussion we decided on no change. Rather, if the functionality were to be enhanced in the future to include a different delay mode, the new subparameter would have a more detailed name. Mike also asked for guidance on how the min and max column entries are defined. Bob found that this was discussed in BIRD57. The general guidance is to enter the values based on absolute min and max delays. The columns of the Off_delay subparameter do not correlate with process corners or voltages directly. There is a similar lack of correlation with C_comp. So Off_delay and C_comp are unique subparameters under [Submodel] and [Model] because they are entered based on magnitude rather than by association with [Voltage Range] or voltage reference values like all of the other subparameters. After this discussion, Bob called for a vote on BIRD57.1. BIRD57.1 was approved unanimously with one abstention. AR - Bob Ross produce BIRD57.1 with the agreed editorial corrections. VERSION 3.2 RATIFICATION PREPARATION Bob Ross indicated that all of the open BIRDs have been resolved. We should plan for a ratification vote at the next meeting (scheduled on January 15, 1999). A number of activities will take place. BIRD56.1 and BIRD57.1 will be uploaded. The unofficial work in progress document will be incremented to ver3_2f.ibs to include the approved BIRD56.1 and BIRD57.1. The date used in the examples will be changed from December 18, 1998 to January 15, 1999 since Bob embeds the ratification date of each release into the IBIS document. A cleaned up voting copy designated ver3_2.ibs along with ver3_2f.ibs will be uploaded for review at http://www.eda.org/pub/ibis/wip Bob noted that he had started work on ver3_2.ibs before BIRD57 was issued. Editorial corrections will be welcome. These corrections will be included in the accepted version of the document. AR - Bob Ross to upload ver3_2f.ibs and ver3_2.ibs to the work in progress directory by December 24, 1998. AR - Everyone to review these documents and provide corrections to Bob Ross or the IBIS reflector. In addition, Bob noted that some parser changes will be communicated to Atul Agarwal as a result of BIRD56.1 and BIRD57.1 adoption. Bob hopes that the updated parser will be available for voting at the next meeting. Also Chris Rokusek indicated that he will be able to make executables of this version. BUG31 - ERROR FOR [Pulldown] DECREASING CURRENT SHOULD BE WARNING Bob Ross mentioned that the main intent of BUG31 is to convert some V/I table Error messages into Warning messages. The error message was originally introduced because the polarity rules regarding when currents and voltages were positive and negative was confusing and a common source of error. This was especially true when dealing with both CMOS/TTL and ECL technologies. A newer architecture that was not anticipated allows, for example, the ground clamp to be active only in the Input mode of an I/O buffer. The ground clamp may be switched out for the output mode. One way to deal with this in Version 2.1 level IBIS models is to add a compensating current in the Pulldown and Pullup tables in the ground clamping regions to compensate for the ground clamp table that would still be in the model. This compensation would usually cause the parser to produce an error - even though the summed I/V tables are monotonic and in compliance with the overall polarity guidelines. Bob indicated that the dynamic clamp submodel in static mode would be the correct way to deal with this structure using IBIS Version 3.1. The committee voted to fix the parser based on BUG31 and change the Error message to a Warning. AR - Bob Ross to communicate ibischk3 parser changes to Atul Agarwal. TEKTRONIX IPA510 SOFTWARE PROPOSAL DISCUSSION Syed Huq indicated that he will put some new information on the IBIS reflector to update us on some additional options. NEXT MEETING: The next meeting will be on Friday, January 15, 1999 from 8:00 AM to 10:00 AM. IBIS Version 3.2 Ratification Vote is planned. Ibischk3 parser acceptance vote is also planned. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentorg.com Modeling Engineer, Interconnectix BU of Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-56 2111 NE 25th Ave. Hillsboro, Oregon 97124-5961 SECRETARY: Matthew Flora (425) 869-2320, Fax: (425) 881-1008 mbflora@hyperlynx.com Senior Engineer, HyperLynx, Inc. 17641 NE 67th Court Redmond, WA 98052 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Senior Scientist, Viewlogic Systems(formerly Quad Design) 1385 Del Norte Rd., Camarillo, CA 93010 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ============================================================================== From owner-ibis Mon Dec 28 07:52:48 1998 Received: from mail-gw2.pacbell.net (mail-gw2.pacbell.net [206.13.28.53]) by server.eda.org (8.8.5/8.8.3) with ESMTP id HAA00311 for ; Mon, 28 Dec 1998 07:52:47 -0800 (PST) Received: from pacbell.net (ppp-209-79-182-126.vntrcs.pacbell.net [209.79.182.126]) by mail-gw2.pacbell.net (8.8.8/8.7.1+antispam) with ESMTP id IAA22571; Sun, 27 Dec 1998 08:13:18 -0800 (PST) Message-ID: <36865C9B.71129AED@pacbell.net> Date: Sun, 27 Dec 1998 08:13:16 -0800 From: Jon Powell Reply-To: jpowell@viewlogic.com Organization: Viewlogic Consulting Services X-Mailer: Mozilla 4.04 [en]C-PBI-NC404 (Win95; I) MIME-Version: 1.0 To: ibis@vhdl.org Subject: Model page Content-Type: multipart/mixed; boundary="------------D98CDBD4FE0B069AF8B8765D" This is a multi-part message in MIME format. --------------D98CDBD4FE0B069AF8B8765D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit IBIS type persons: The IBIS model page is back up. If you didn't know it was down then..... maybe it wasn't. regards and Happy New Year !!! jon IBIS Librarian --------------D98CDBD4FE0B069AF8B8765D Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jon Powell Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Jon Powell n: Powell;Jon org: Viewlogic Consulting Services adr: 1369 Del Norte Rd.;;;Camarillo;CA;93010;USA email;internet: jonp@pacbell.net title: Manager High Speed Design Services tel;work: 805 988 8250 tel;fax: 805 988 8259 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------D98CDBD4FE0B069AF8B8765D--