From owner-ibis Tue Mar 3 08:45:41 1998 Received: from newsgw.mentorg.com (newsgw.mentorg.com [192.94.38.66]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id IAA12870 for ; Tue, 3 Mar 1998 08:45:40 -0800 (PST) Received: from emicx.wv.mentorg.com by newsgw.mentorg.com (8.8.8/CF5.40F) id IAA11050; Tue, 3 Mar 1998 08:42:27 -0800 (PST) Received: from bob by emicx.wv.mentorg.com (8.7.5/CF5.38R) id IAA08049; Tue, 3 Mar 1998 08:42:24 -0800 (PST) From: bobr@emicx.mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA26408; Tue, 3 Mar 98 08:42:50 PST Date: Tue, 3 Mar 98 08:42:50 PST Message-Id: <9803031642.AA26408@bob> To: ibis@eda.org Subject: IBIS MINUTES, FEB. 26, 1998 SUMMIT DATE: 3/3/98 SUBJECT: 2/26/98 EUROPEAN IBIS SUMMIT Minutes VOTING MEMBERS AND 1998 PARTICIPANTS LIST: AMP (Martin Freedman) Applied Simulation Technology Norio Matsui, Raj Raghuram Cadence Design (& UniCAD) C. Kumar*, Don Telian, Patrick Riffault, Craig Lewis, Greg Fitzgerald, Paul Galloway*, Patrick Dos Santos*, Catherine Weiss*, Alain Tribaudot*, Cypress (Bruce Wenniger) Digital Equipment Corp. Jeff Chu, Greg Edlund, Bob Haller Hewlett Packard (EEsof, etc.) Karl Kachigan, Henry Wu, Paul Gregory High Design Technology Razvan Ene* HyperLynx Kellee Crisafulli, Matthew Flora Incases Olaf Rethmeier, Scott Jacobson, Werner Rissiek* Intel Corporation Stephen Peters, Arpad Muranyi, Frank Kern, Will Hobbs*, Prakash Radhakrishnan* Columbia, SC (formerly NCR) Dave Moxley Mentor Graphics (Zeelan, Bob Ross*, George Opshal, Mark Noneman, Interconnectix, etc.) Tom Dagostino*, Karine Loudet*, Jean Oudinot*, Manuel De Almeida*, Stephane Rousseau* Mitsubishi (Hoang Nguyen), Tam Cao Motorola (Ron Werner) National Semiconductor Syed Huq*, Cheng-Yang Kao, John Goldie, Ikchang Song North East Systems Associates Edward Sayre, Kathy Breda (NESA) NEC (Hiroshi Matsumoto) Quantic EMC (Mike Ventham) Texas Instruments Thomas Fisher, Harvey Stiegler, Vincent Chang, Jean-Claude Perrin*, Peter Forstner* Thomson-CSF Jean-Marc Claveau*, Laurent Duzaic*, Saverio Lerose*, Benoit Meyniel*, Jean Lefebvre* Viewlogic Jon Powell, Chris Rokusek, Guy de Burgh*, Gary Mandel* VeriBest Ian Dodd, David Weins*, Ian Gabbitas* VLSI Technology D.C. Sessions Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1998: Actel Eric Tardif*, Emmonvelle Gaudin* Aerospatiale Lionel Dreux*, Claude Huet* Alcatel (Bell, Espace, etc.) John Fitzpatrick*, W. Temmerman*, Laure Bessettes*, Jean-Claude Pourtau*, Daniel Peron* ALS Design Yves Mouquet* Ansoft Eric Bogatin Apple Fred Floresca, Danny Itani Apteq Design Systems Dan FitzPatrick CERN Olivier Clere*, Jean-Michel Sainson*, Rudi Zurbroken* Compaq Shariq Rahma EIA Patti Rusher EMC Fawn Engelmann ENST, Paris Jean-Jacques Charlot* European CAD Standardization Adam Morawiec* Intitiative (ECSI) Fairchild Semiconductor Peter LaFlamme H.A.S Electronics Haruny Said* Intracon Design Ltd. Derek Laidlaw* Philips Semiconductor Todd Andersen Scottish Electronics Robert Easson* Manufacturing Center (SEMC) Seagate Vanessa Howard SGS-Thomson Philippe Lefevre* Siemens Gerald Bannert*, Bernhard Unger*, Christian Marot*, Miguel Hernandez* Symmetry Andy Hughes Tektronix Nassrin Ghahyasi Ultratest International Chris O'Connor Xilinx Susan Wu In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode March 13, 1998 (916) 356-9200 5-23353 2913463 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM The European IBIS Summit was held in Paris, France at the Hotel Concorde La Fayette. Bob Ross welcomed the group and introduced the officers. All the attendees introduced themselves. During the meeting Bob thanked Mentor Graphics for sponsoring the excellent facilities and equipment, Cadence Design for the outstanding buffet lunch, and High Design Technology (HDT) for providing the refreshments. Bob also thanked Razvan Ene of HDT for initially suggesting an IBIS meeting associated with the Design Automation and Testing in Europe Conference (DATE98). This suggestion was developed into this European IBIS Summit Meeting. About 50 people from 20 organizations were recorded as attending. Please submit any corrections to organizations or names to Bob. (Also Bob thanks Karine Loudet for handling the local arrangements, signup, and providing copies of the presentations.) Some brief notes taken during the presentations from the presentation material are given below. The presentations themselves will be available on eda.org under /pub/ibis/summits/feb98. WELCOME, IBIS ACTIVITIES - Bob Ross, Interconnectix/Mentor Graphics, USA Bob gave a brief overview of the EIA IBIS Open Forum. The subgroup has open, public participation to all interested parties. He described the the technical evolution of the IBIS versions. The Open Forum monitors external, international activities such as the EMC and IBIS activities in France. The Open Forum also has several projects related to ratification of Version 3.1 including BIRD42.3 and the ibischk3 parser development (the first evaluation version has been distributed to those funding the project). It also cooperates with the IBIS Users Group (IBIS East). REPORT ON IBIS USERS FORUM - Paul Galloway, Cadence, USA Paul showed the mission and history of the IBIS Users Group headed by Ed Sayre. The Group has two committees, one concerned with Accuracy and Validation of IBIS, and the other concerned with Software Aspects. Paul emphasized that the participation is open and has members from all over the USA. However, the four face-to-face meetings to date have been held in the Northeast USA, with the last three hosted on site at companies. Paul concluded by stating that the group is focusing on the users needs, has strong East Coast EDA tool vendor participation, and is coordinating its activities with the EIA IBIS Open Forum. USE OF IBIS MODELS IN ALCATEL - John Fitzpatrick, Alcatel, France John has written a simplified IBIS parser in PERL and showed pages of his Netscape browser interface for his IBIS Management Suite. It was developed last year. John uses the IBIS Management Suite to manage buffer models. He would like to have the model verification process to be robust enough to not require simulation or measurement of the buffer. A graphical datasheet shows the added curves to get the real response, and it can be used to filter out superfluous data. John also illustrated a simplified model creation process when exact information is missing, but he stressed that this is not for novices. Then entered information can be used for design rules, and he illustrated this for crosstalk for several technologies. For ASICs, John relies on the short circuit current rather than the Iol current for driver strength classification. By contract Alcatel requires IBIS models for ASICs, but in reality models are not provided. The IBIS format does not support independent [Model]s for buffers, although EDA tools do provide such support. John sees the need for IBIS package models for ASICs which are not readily provided. John stated that ASIC timing is based on Cload, but the actual load is not capacitive. He would like an exact threshold value (Vt) instead of Vinl and Vinh. He also claimed that the IBIS Model was not suitable for ground bounce simulation. John showed some examples for buffer strength and timing. While stating that IBIS support is better, John concluded with several recommendations: component and buffers may need to be managed separately, better ASIC library support - at least in the Cookbook, more emphasis on timing analysis and less on SI, good graphical tool is needed, and more package only models. IBIS MODEL DEVELOPMENT AT NATIONAL SEMICONDUCTOR CORPORATION - Syed Huq, National Semiconductor, USA Syed introduced himself as Vice Chair. and also the Web Master of the EIA IBIS Open Forum. He has been active since 1994, and National has provided the largest number of IBIS models. In the last three years National has also hosted the IBIS Summit Meetings associated with DesignCon. Syed discussed the IBIS Intranet, an internal National web page used for information, tools, training and an internal users group. National develops IBIS models from Spice using the public s2ibis2 and also an internally developed ns2spice for NaSpice. Also National develops measurement based IBIS models. Syed listed the steps he uses to validate models: visual inspection, s2iplt verification, ibischk2 parser test, simulation with two simulators under a know load, and comparison of simulation data to bench or Spice simulation. IBIS model development is a milestone step in the National digital device release process. National currently develops IBIS Version 2.1 level models and will develop IBIS Version 3.1 models when the ibischk3 parser is made available. Syed noted that Logic, Memory, and Discrete models are now handled by Fairchild Semiconductor, which spun off from National. IBIS, MEASUREMENTS VS SPICE - Tom Dagostino, Zeelan/Mentor Graphics, USA Tom compared the plots of several IBIS Model V_low tables from some publicly available components extracted form s2ibis tools with actual measured data. While the components were selected randomly, Tom's general observation was that the measurements tended to correlate with the max columns. The plots also showed some s2ibis artifacts of double counting the power clamp and some known numerical current foldback on the ground clamp side. REQUIRED IBIS ENHANCEMENTS - Gerald Bannert, Siemens, Germany Gerald shared his experiences. Along with correct logical functioning under normal operating conditions (signal integrity, crosstalk, propagation delay), he was concerned with incorrect function and failure conditions (on/off of multiple power supplies, voltage over/undershoots at inputs and outputs, and maximum operating frequencies under load condition), and long term reliability (junction temperature, breakdown voltage, and maximum currents). Gerald listed the important parameters. The group not covered by IBIS included: monotony of rising and falling edges at inputs, minimum and maximum rise and fall times at inputs, ground bounce effects, bus hold circuitry at inputs, and switching on/off conditions of multiple power supplies. Input capacitance and clamping diodes are covered by IBIS. The load normalization of data sheet delay times is an interface problem between different libraries. Gerald illustrated several of these parameters. He also concluded that the most critical parameters are difficult to define, measure and model; modeling parameters should take into account future practical needs; and the vendor interface is very important. The vendor interface includes these considerations: valid IBIS revisions, optional parameters, interpretation of IBIS parameters, feedback of simulation results to I/O (re)designs, model and/or silicon changes, and model validity and guarantee. CHALLENGES IN USING IBIS IN HIGH FREQUENCY APPLICATIONS - Prakash Radhakrishnan, Intel, USA Prakash discussed the need for an improved IBIS package model to simulate simultaneous switching noises and associated delay interactions. He showed results using the existing discrete LRC package model and using the coupled matrix model in IBIS Version 2.1. Prakash's enhanced model used a "hybrid modeling technique" developed to capture lumped and transmission line effects. It involves modeling a plane as a two-dimensional inductance array with discrete capacitive coupling between planes. This process gives more detail for ground and power planes and helps to improve the correlation between simulated and measured results. EUROPEAN CAD STANDARDIZATION INITIATIVE (ECSI) - Adam Moraweic, ECSI, France Adam began the afternoon presentations by briefly describing the ECSI as an EDA vendor funded organization to promote educational workshops and information about standards affecting the European community. IBIS could be a candidate for such a workshop. IBIS MODELS AND EMC SIMULATION STANDARDIZATION STATUS Jean-Claude Perrin, Texas Instruments, France Jean-Claude, President of the working group gave the presentation in place of Christian Marot who arrived later. The working group is affiliated with Union Technique de L'Electricite (UTE) of France and is UTE/CEF93/GT5 EMC. It is affiliated IEC TC93 WG5 to work on electromagnetic compatibility of ICs. Its objective is to create a standard for EMC integrated circuit models. Jean-Claude defined aspects of the EMC problems: signal integrity, emissions (radiated fields by PCB conducted noises on lines) and immunity (to radiated fields to conducted noises on lines). From a questionnaire issued by the group, Jean-Claude listed the conclusions and directions. Immunity was not in any software, IBIS was well adapted to the general EMC problem, but needed some improvements. For emissions, IBIS would need the following elements: coupling between I/O and power supply, coupling with the logic core, coupling between I/O, and feedback coupling between I/O. For immunity, IBIS would need these elements: equivalent decoupling impedance, impedance of supply lines, internal noise generator, internal loops, and coupling between internal logic and I/O. Measurement methodologies would have to be defined for model validation and control. The plan is to create a task force at the IEC level to present a New Working Item Proposal for September, 1998. An international experts meeting is scheduled on February 27, 1998 to disucss details. FUTURE COMPONENT CHARACTERIZATION FOR EMI ANALYSIS - Werner Rissiek, Incases, Germany Werner indicated that Incases and Viewlogic are working with the University of Missouri-Rolla on EMC component characterization. Werner described the EMC problem as an additional consideration beyond signal integrity and thermal radiation. The EMC problem involves strong magnetic fields in the area of ICs, and packages act as antennas. There exist differential and common mode effects. The general 3-dimensional solution is too large for accurate numerical analysis and for solving in a timely manner. So the proposed approach is to partition the problem and apply an expert approach with simplifying assumptions. Werner listed some geometrical and electrical parameters of interest. He further tabulated a number of electrical parameters for voltage, currents, time and clock frequencies and classified them as analysis (as an input parameter) or evaluation (of results). Tables for buffer specific parameters and derived quantities for components and buffer classification were shown. Werner concluded that the EMI analysis required behavioral models like IBIS, additional classification parameters for an expert approach, and specific geometrical package information. This information could be put into an extended IBIS. Werner stated that he is willing to help in the IEC task group. IBIS MODELS FOR EMC AND HIGH-FREQUENCY DEVICES - Razvan Ene, High Design Technology, Italy Razvan presented an architecture and Spice-like syntax sample for handling SI problems. It has time-switching functions, pullup and pulldown functions and clamping functions. Spice polynomial functions are used. Razvan showed the definition of the functions and an extension for time-varying clamping. Its data is extracted using a TDR setup. Razvan showed the results for the AC74 from two manufacturers and presented a distributed diode-inductor model for the slow clamping effect. Razvan showed some measurement versus simulation correlations. Regarding EMC, Razvan showed a measurement setup at the semi-anechoical room at Lille University and showed a test case. Even for low frequency simulations the model needs to be valid at very high frequencies. With "dft" extraction (replacing the slope given in the IBIS model), he showed EMC modeling and measurement correlation up to 400 MHz. For IBIS, Razvan recommends a number of practices and additions: use all fields (min, typ, max), introduce a field for Cout spread, use waveform tables, and introduce supplementary fields for TDR measurement and dynamic output impedance and clamping. Razvan also supports forming a European IBIS group to disseminate IBIS and IBIS know-how and to provide a forum where producers and users can express their needs. SI-ANALYSIS WITH HSPICE BASED ON IBIS BEHAVIORAL MODELS - Bernhard Unger, Siemens, Germany Bernhard showed an IBIS model architecture for analysis that uses time- varying multipliers for the pulldown and pullup tables to describe the switching from one state to another. He conducted a number of tests to generate the multipliers based on one-waveform and two-waveform test loads. These loads were based on waveforms generated with R_fixture = 50 ohms and V_fixture terminated to GND or Vcc. Bernhard's results showed good correlation with the two-waveform case or when the test loads matched the simulation loads in the one-waveform case. Bernhard presented some results of actual signal integrity simulations and comparisons with measurement of a circuit involving an IBIS based HSPICE model including package, transmission line model using the HSPICE U-model from parameters extracted using a 2-D field solver, and a vendor supplied connector model. He showed excellent agreement with measurement when he adjusted the pullup table using scaling factor of 1.3. Bernhard concludes that IBIS models with two-waveform tables extracted under two different loading conditions give results valid for a wider range of loading conditions. IBIS Version 1.1 models are not sufficient. PROBLEMS IN V-T CURVE MODELING AND SIMULATION - C. Kumar, Cadence, USA Kumar indicated that the waveform algorithm processing algorithms were still ambiguous. One waveform analysis can be handled in a arbitrary number of ways. If multiple waveforms are given, then any of the sets of choices can give different simulation results. The waveform algorithms do not address the power and ground current distributions correctly. Kumar proposed according to BIRD42.3 that V/T and I/T tables given for the same V_fixture and R_fixture load could be used unambiguously to solve for the time varying multipliers for the pulldown and pullup tables. He proposed R_fixture = 50 and V_fixture = Vcc/2 to capture the independent pulldown and pullup switching characteristics. BIRD42.3 ALGORITHM CONSIDERATIONS - Bob Ross, Interconnectix/Mentor Graphics, USA Bob indicated that he and C. Kumar were co-authors of BIRD42.3 that is still pending. An IBIS Version 2.1 reference model was presented, consistent with the prior models for waveform table processing. The BIRD42.3 additions include corresponding an optional [Pullup Reference Current] table and/or an optional [Pulldown Reference Current] table. Bob showed a possible and general enhanced structure for adding the current information to the IBIS Version 2.1 model using Idelta and Vdelta sources. With the addition current tables, there are algorithm issues. The added information can be used to revise the fundamental coefficient extraction, as Kumar proposes, or it could be also for corrections to the IBIS model. Also if both the [Pullup Reference Current] and [Pulldown Reference Curent] tables are given, they contain redundant data which needs to be resolved by the simulator. Because both the one and two voltage waveform methodology is used by simulators, the algorithms for the proposed current extensions need to be considered in detail for any of the optional extension combinations. Bob presented a table showing possible algorithm approaches for coefficient calculation and possible correction source calculatons for the allowable one and two voltage waveform cases with and without currents. In some cases either the V1,V2 information or the V,I information could be used for calculating coefficients, and the additional data used to calculate the correction sources. Bob listed several other issues associated with BIRD42.3. The added current information most likely would be available only from Spice extraction. Numerical issues may exist concerning this data. Other Model_types related to Open_* and ECL_* configurations had to be considered. The optimal set of Fixture voltages could be contradictory (Vcc and 0 for V1 and V2 tables, Vcc/2 for V1, I1 tables). Finally internal components such as internal clocks could introduce current spikes that are not included in BIRD42.3 extensions. GROUP DISCUSSION Jean-Jacques Charlot introduced himself as a Professor at ENST, Paris and he is concerned about the need for IBIS education. Bob Ross indicated that this was a general concern. Bob asked if people felt that the meeting was worthwhile, and the general consensus was very positive. The meeting was adjourned so that people could engage in individual discussions and make contacts. NEXT MEETING: The next teleconference meeting is on Friday, March 13, 1998, 8:00 A.M. to 9:55 A.M. BIRD46.1 may be scheduled for a vote. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentorg.com Modeling Engineer, Interconnectix BU of Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785 huq@rockie.nsc.com Staff Applications Engineer, National Semiconductor, M/S A-2595 2900 Semiconductor Drive, Santa Clara, CA 95052 SECRETARY: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-56 2111 NE 25th Ave. Hillsboro, Oregon 97124-5961 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Senior Scientist, Viewlogic (formerly Quad Design) 1385 Del Norte Rd., Camarillo, CA 93010 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ============================================================================== From owner-ibis Wed Mar 4 08:34:23 1998 Received: from mail-gw2.pacbell.net (mail-gw2.pacbell.net [206.13.28.53]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id IAA07143 for ; Wed, 4 Mar 1998 08:34:22 -0800 (PST) Received: from pacbell.net (ppp-206-171-248-193.vntrcs.pacbell.net [206.171.248.193]) by mail-gw2.pacbell.net (8.8.8/8.7.1+antispam) with ESMTP id IAA14684; Wed, 4 Mar 1998 08:31:39 -0800 (PST) Message-ID: <34FD81BA.A0EE4F6E@pacbell.net> Date: Wed, 04 Mar 1998 08:30:50 -0800 From: Jon Powell Reply-To: jonp@qdt.com Organization: Viewlogic Consulting Services X-Mailer: Mozilla 4.04 [en]C-PBI-NC404 (Win95; I) MIME-Version: 1.0 To: ibis@vhdl.org Subject: ibis model page Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Notification: There has been some problems at the site that hosts the IBIS models page. The ibis directory was accidently deleted. I am in the process of repairing it. Sorry for any problems. regards, jon powell ibis librarian From owner-ibis Wed Mar 4 14:46:19 1998 Received: from newsgw.mentorg.com (newsgw.mentorg.com [192.94.38.66]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id OAA13983 for ; Wed, 4 Mar 1998 14:46:18 -0800 (PST) Received: from emicx.wv.mentorg.com by newsgw.mentorg.com (8.8.8/CF5.40F) id OAA09051; Wed, 4 Mar 1998 14:43:05 -0800 (PST) Received: from bob by emicx.wv.mentorg.com (8.7.5/CF5.38R) id OAA18265; Wed, 4 Mar 1998 14:43:03 -0800 (PST) From: bobr@emicx.mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA27428; Wed, 4 Mar 98 14:43:30 PST Date: Wed, 4 Mar 98 14:43:30 PST Message-Id: <9803042243.AA27428@bob> To: ibis@eda.org Subject: European IBIS Presentations To All: The European IBIS Summit Presentations are now all uploaded to eda.org/pub/ibis/summits/feb98. Bob Ross Interconnectix B.U INDEX - EUROPEAN IBIS SUMMIT HOTEL CONCORDE LA FAFYETTE PARIS, FRANCE FEBRUARY 26, 1998 Index.txt This file a022698.txt Preliminary Agenda m022698.txt Minutes of the Meeting The Program is zipped files in HTML, Word, Power Point Formats and Acrobat formats and are listed in the order of the presentations: ross1.zip (.ppt) Welcome, IBIS Activities Bob Ross, Interconnectix/Mentor Graphics, USA galloway.ppt Report on IBIS Users Group Paul Galloway, Cadence, USA fitzpatrick.zip (.ppt) fitzpatrick.pdf Use of IBIS Models in Alcatel John Fitzpatrick, Alcatel, France huq.zip (.ppt) IBIS Model Development at National Semiconductor Corporation Syed Huq, National Semiconductor, USA dagostino.zip (.ppt) IBIS, Measurements vs. Spice Tom Dagostino, Zeelan/Mentor Graphics, USA bannert.doc bannert.ppt Required IBIS Enhancements Gerald Bannert, Siemens, Germany radhakrishnan.zip (.doc) radhakrishnan.ppt Challenges in Using IBIS in High Frequency Applications Prakash Radhakrishnan, Intel, USA perrin.ppt IBIS Models and EMC Simulation Standardization Status Jean-Claude Perrin, Texas Instruments, USA rissiek.ppt Future Component Characterization for EMI Analysis Werner Rissiek, Incases, Germany ene.zip (.ppt) IBIS Models fo EMC and High-Frequency Devices Razvan Ene, High Design Technology, Italy unger.zip (.ppt) (with notes) SI-Analysis with HSPICE Based on Behavioral Models Bernhard Unger, Siemens, Germany kumar.tar (.html) Problems in V-T Curve Modeling and Simulation C. Kumar, Cadence, USA ross2.zip (.ppt) BIRD42.3 Algorithm Considerations bob Ross, Interconnectix/Mentor Graphics, USA From owner-ibis Wed Mar 4 14:54:57 1998 Received: from relayhost.vlsi.com (relayhost.vlsi.com [134.27.20.23]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id OAA13993 for ; Wed, 4 Mar 1998 14:54:57 -0800 (PST) Received: (from nobody@localhost) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) id OAA28459 for ; Wed, 4 Mar 1998 14:51:43 -0800 Received: from anubis.tempe.vlsi.com(134.27.128.1) by tweety via smap (V2.0) id xma028430; Wed, 4 Mar 98 14:51:19 -0800 Received: from mailserver.tempe.vlsi.com (mailserver.tempe.vlsi.com [134.27.128.5]) by relayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/101195) with ESMTP id PAA26701 for ; Wed, 4 Mar 1998 15:51:12 -0700 Received: from tempe.vlsi.com ([134.27.133.12]) by mailserver.tempe.vlsi.com (Netscape Mail Server v2.02) with ESMTP id AAA29473; Wed, 4 Mar 1998 15:51:12 -0700 Sender: dc.sessions@tempe.vlsi.com (D.C. Sessions) Message-ID: <34FDDADF.9B7B1A46@tempe.vlsi.com> Date: Wed, 04 Mar 1998 15:51:11 -0700 From: "D. C. Sessions" Organization: VLSI Technology Inc. X-Mailer: Mozilla 4.03 [en] (X11; U; SunOS 5.5.1 sun4m) MIME-Version: 1.0 To: IBIS Mailing list CC: Gil Russell Subject: JEDEC meets IBIS Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Thumbnail meeting report: Yesterday I attended the quarterly JEDEC JC-16 meeting. JC-16 is the group responsible for JEDEC signalling standards such as SSTL, HSTL, etc. Among other things announced was the establishment of JC-16B, a working group chartered with modelling and testing issues. Some smartmouth in the back of the room pointed out that the JC-16 membership was rich in semiconductor manufacturers and system houses but totally lacking in EDA companies, which might be a slight handicap when addressing modelling and test issues. To the surprise of no one, said impulsive individual got the appropriate reward: assignment as liason to the EIA IBIS committee, which apparently has a complementary membership and is posessed of much-needed expertise. Note that the CC: on this message is to one Gil Russell, whose misfortune is to chair JC-16B. This could be the start of a VERY profitable collaboration. Item on the table: JC-16 meets quarterly along with a slew of other JEDEC committees. We (IBIS) should consider moving our winter face-to-face meeting to colocate with their December meeting. Some mightily interesting results could come of that. -- D. C. Sessions dc.sessions@tempe.vlsi.com From owner-ibis Wed Mar 4 16:35:43 1998 Received: from newsgw.mentorg.com (newsgw.mentorg.com [192.94.38.66]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA15785 for ; Wed, 4 Mar 1998 16:35:43 -0800 (PST) Received: from emicx.wv.mentorg.com by newsgw.mentorg.com (8.8.8/CF5.40F) id QAA18301; Wed, 4 Mar 1998 16:32:27 -0800 (PST) Received: from bob by emicx.wv.mentorg.com (8.7.5/CF5.38R) id QAA19299; Wed, 4 Mar 1998 16:32:25 -0800 (PST) From: bobr@emicx.mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA27554; Wed, 4 Mar 98 16:32:49 PST Date: Wed, 4 Mar 98 16:32:49 PST Message-Id: <9803050032.AA27554@bob> To: dc.sessions@tempe.vlsi.com, ibis@eda.org Subject: Re: JEDEC meets IBIS D. C.: Can we discuss this at the next IBIS meeting on March 13? I think we can do IBIS Models for these technologies. Bob Ross Interconnectix/Mentor Graphics > Date: Wed, 04 Mar 1998 15:51:11 -0700 > From: "D. C. Sessions" > Organization: VLSI Technology Inc. > To: IBIS Mailing list > CC: Gil Russell > Thumbnail meeting report: > Yesterday I attended the quarterly JEDEC JC-16 meeting. > JC-16 is the group responsible for JEDEC signalling > standards such as SSTL, HSTL, etc. Among other things > announced was the establishment of JC-16B, a working > group chartered with modelling and testing issues. > Some smartmouth in the back of the room pointed out > that the JC-16 membership was rich in semiconductor > manufacturers and system houses but totally lacking > in EDA companies, which might be a slight handicap > when addressing modelling and test issues. To the > surprise of no one, said impulsive individual got > the appropriate reward: assignment as liason to the > EIA IBIS committee, which apparently has a complementary > membership and is posessed of much-needed expertise. > Note that the CC: on this message is to one Gil Russell, > whose misfortune is to chair JC-16B. This could be > the start of a VERY profitable collaboration. > Item on the table: JC-16 meets quarterly along with a > slew of other JEDEC committees. We (IBIS) should > consider moving our winter face-to-face meeting to > colocate with their December meeting. Some mightily > interesting results could come of that. > -- > D. C. Sessions > dc.sessions@tempe.vlsi.com From owner-ibis Wed Mar 4 16:45:57 1998 Received: from relayhost.vlsi.com (relayhost.vlsi.com [134.27.20.23]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA15968 for ; Wed, 4 Mar 1998 16:45:57 -0800 (PST) Received: (from nobody@localhost) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) id QAA08084 for ; Wed, 4 Mar 1998 16:42:43 -0800 Received: from anubis.tempe.vlsi.com(134.27.128.1) by tweety via smap (V2.0) id xma008060; Wed, 4 Mar 98 16:42:36 -0800 Received: from mailserver.tempe.vlsi.com (mailserver.tempe.vlsi.com [134.27.128.5]) by relayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/101195) with ESMTP id RAA28319 for ; Wed, 4 Mar 1998 17:42:35 -0700 Received: from tempe.vlsi.com ([134.27.133.12]) by mailserver.tempe.vlsi.com (Netscape Mail Server v2.02) with ESMTP id AAA2698 for ; Wed, 4 Mar 1998 17:42:34 -0700 Sender: dc.sessions@tempe.vlsi.com (D.C. Sessions) Message-ID: <34FDF4FA.546C82B@tempe.vlsi.com> Date: Wed, 04 Mar 1998 17:42:34 -0700 From: "D. C. Sessions" Reply-To: ibis@vhdl.org Organization: VLSI Technology Inc. X-Mailer: Mozilla 4.03 [en] (X11; U; SunOS 5.5.1 sun4m) MIME-Version: 1.0 To: ibis@eda.org Subject: Re: JEDEC meets IBIS References: <9803050032.AA27554@bob> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Bob Ross wrote: > > D. C.: > > Can we discuss this at the next IBIS meeting on March 13? Yup. > I think we can do IBIS Models for these technologies. No doubt about it, we can do MODELS for the technologies. The interesting thing is that we can influence the process of GENERATING the standards in the first place. One of the reasons that JC-16B was formed is that some standards in the past were created with built-into-the-foundations signal integrity flaws. Part of the JC-16B charter is to improve the process and characterization of signalling standards. Personally, I'd hope to have IBIS become the syntax for characterizing signalling standards in the first place. We wouldn't HAVE to model SSTL-1.8, for instance, since the standard itself would contain an IBIS model envelope for compliant devices. > > Date: Wed, 04 Mar 1998 15:51:11 -0700 > > From: "D. C. Sessions" > > Organization: VLSI Technology Inc. > > To: IBIS Mailing list > > CC: Gil Russell > > > Thumbnail meeting report: > > > Yesterday I attended the quarterly JEDEC JC-16 meeting. > > JC-16 is the group responsible for JEDEC signalling > > standards such as SSTL, HSTL, etc. Among other things > > announced was the establishment of JC-16B, a working > > group chartered with modelling and testing issues. > > > Some smartmouth in the back of the room pointed out > > that the JC-16 membership was rich in semiconductor > > manufacturers and system houses but totally lacking > > in EDA companies, which might be a slight handicap > > when addressing modelling and test issues. To the > > surprise of no one, said impulsive individual got > > the appropriate reward: assignment as liason to the > > EIA IBIS committee, which apparently has a complementary > > membership and is posessed of much-needed expertise. > > > Note that the CC: on this message is to one Gil Russell, > > whose misfortune is to chair JC-16B. This could be > > the start of a VERY profitable collaboration. > > > Item on the table: JC-16 meets quarterly along with a > > slew of other JEDEC committees. We (IBIS) should > > consider moving our winter face-to-face meeting to > > colocate with their December meeting. Some mightily > > interesting results could come of that. > > > -- > > D. C. Sessions > > dc.sessions@tempe.vlsi.com -- D. C. Sessions dc.sessions@tempe.vlsi.com From owner-ibis Thu Mar 5 16:09:11 1998 Received: from ganymede.or.intel.com (ganymede.or.intel.com [134.134.248.3]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA10586 for ; Thu, 5 Mar 1998 16:09:11 -0800 (PST) Received: from ichips-jf.jf.intel.com (ichips-jf.jf.intel.com [134.134.50.200]) by ganymede.or.intel.com (8.8.6/8.8.5) with ESMTP id QAA00956 for ; Thu, 5 Mar 1998 16:13:49 -0800 (PST) Received: from xtg801 (xtg801.pdx.intel.com [134.134.120.169]) by ichips-jf.jf.intel.com (8.8.8/8.8.7) with ESMTP id QAA20844 for ; Thu, 5 Mar 1998 16:06:28 -0800 (PST) Received: from ichips.intel.com by xtg801 (8.8.8/WW2.1 (Jones Farm)) id QAA24347; Thu, 5 Mar 1998 16:06:27 -0800 (PST) Message-Id: <199803060006.QAA24347@xtg801> X-Mailer: exmh version 2.0delta 6/3/97 To: ibis@vhdl.org Subject: Bird 47 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Thu, 05 Mar 1998 16:06:26 -0800 From: Stephen Peters Hello All: The parser developer raised the following issue with the [Pin List] keyword syntax ([Pin List] is found in the Electrical Board Description section of IBIS ver3.0). Because it is a syntax issue, a bird is required to fix it. After confering with Bob Ross, here is the proposed change. Regards, Stephen Peters Intel Corp. Buffer Issue Resolution Document (BIRD) BIRD ID#: Bird 47 ISSUE TITLE: Remove pin name as a sub-param of the [Pin List] keyword REQUESTOR: Stephen Peters Intel Corp. DATE SUBMITTED: March 5, 1998 DATE ACCEPTED BY IBIS OPEN FORUM: ******************************************************************************* ******************************************************************************* STATEMENT OF THE ISSUE: The current [Pin List] keyword in the Electrical Board Description of the specification list two subprameters -- pin_name and signal_name. However, this syntax/format is not consistent with the [Pin] or [Pin Number] keywords in the rest of the specification. Specificaly, the 'pin name' should be what the keyword is listing, not a sub-param to the keyword. Therefore, 'pin_name' should be removed as a subparameter from the [Pin List] keyword, and the example changed. ******************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: Replace the current [Pin List] keyword description and example in the Electrical Board Description section of the specification with the following. |============================================================================= | Keyword: [Pin List] | Required: Yes | Description: Tells the parser the pin names of the user accessible pins. | It also informs the parser which pins are connected to power | and ground. | Sub-Params: signal_name | Usage Rules: Following the [Pin List] keyword are two columns. The first | column lists the pin name while the second lists the data book | name of the signal connected to that pin. There must be as | many pin_name/signal_name rows as there are pins given by the | preceding [Number Of Pins] keyword. Pin names must be the | alphanumeric external pin names of the part. The pin names | cannot exceed eight characters in length. Any pin associated | with a signal name that begins with "GND" or "POWER" will be | interpreted as connecting to the boards ground or power plane. | In addition, NC is a legal signal name and indicates that the | Pin is a 'no connect'. As per the IBIS standard "GND", | "POWER" and "NC" are case insensitive. |----------------------------------------------------------------------------- | A SIMM Board Example | [Pin List] signal_name A1 GND A2 data1 A3 data2 A4 POWER5 | this pin connects to 5v A5 NC | a no connect pin | . | . A22 POWER3.3 | this pin connects to 3.3v B1 casa | . | . |etc. | |============================================================================= ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: This problem was found while the parser for IBIS ver3.0 was being developed. Bob Ross (unofficial keeper of the ibis syntax and syle) concures with the change. ******************************************************************************* ANY OTHER BACKGROUND INFORMATION: ******************************************************************************* From owner-ibis Fri Mar 6 08:07:05 1998 Received: from wile.nesa.com ([204.240.29.30]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id IAA26817 for ; Fri, 6 Mar 1998 08:07:03 -0800 (PST) Received: from tweety.nesa.com(204.240.29.37) by wile.nesa.com via smap (V1.3) id sma009795; Fri Mar 6 11:03:28 1998 Message-Id: <3.0.3.32.19980306110327.006d32d8@mail.nesa.com> X-Sender: esayre@mail.nesa.com X-Mailer: QUALCOMM Windows Eudora Pro Version 3.0.3 (32) Date: Fri, 06 Mar 1998 11:03:27 -0500 To: dc.sessions@tempe.vlsi.com From: "Dr. Edward P. Sayre" Subject: IBIS/JEDEC-16 Cc: breda@nesa.com, ibis@eda.org Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" D. C.: I concur that IBIS and JEDEC-16 should meet periodically. You chip guys have a definite interest in device qualitative descriptions, threshold definitions and some application information is assembled and published, but interoperability, modeling (SPICE and IBIS) and other user oriented stuff is often left to the lab motorheads to complete. The result is that it often doesn't get done soon enough for our purposes. By the way does JEDEC-16 have a web site with current drafts and standards? ed sayre +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ | NORTH EAST SYSTEMS ASSOCIATES, INC. | | ------------------------------------- | | "High Performance Engineering & Design" | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ | Dr. Ed Sayre e-mail: esayre@nesa.com | | NESA, Inc. http://www.nesa.com/ | | 636 Great Road Tel +1.508.897-8787 | | Stow, MA 01775 USA Fax +1.508.897-5359 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ From owner-ibis Fri Mar 6 10:52:28 1998 Received: from newsgw.mentorg.com (newsgw.mentorg.com [192.94.38.66]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA29835 for ; Fri, 6 Mar 1998 10:52:27 -0800 (PST) Received: from emicx.wv.mentorg.com by newsgw.mentorg.com (8.8.8/CF5.40F) id KAA05729; Fri, 6 Mar 1998 10:49:13 -0800 (PST) Received: from bob by emicx.wv.mentorg.com (8.7.5/CF5.38R) id KAA00652; Fri, 6 Mar 1998 10:49:02 -0800 (PST) From: bobr@emicx.mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA28843; Fri, 6 Mar 98 10:49:31 PST Date: Fri, 6 Mar 98 10:49:31 PST Message-Id: <9803061849.AA28843@bob> To: ibis@eda.org Subject: AGENDA IBIS MEETING 3/13/98 IBIS Open Forum Meeting Agenda for 3/13/98 Bridge Number Reservation # Passcode (916) 356-9200 5-23353 2913463 All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the Reservation Number and Passcode. 8:00 Check-In, Intros, Announcements Ross - Intros of New IBIS Participants, Meeting Quorum Ross - Membership Update and Treasurers Report Rusher - Review of Previous Meeting's Minutes (and ARs) Peters - Miscellany/Announcements All - Press & Web Page Updates Huq, All - New Models Available, Library Update Powell, All - Opens for New Issues All 8:25 Administrative and Project Discussions International Progress Rusher/Ross - IEC 62014-1 (IBIS Version 2.1) - EIAJ III (I/O Interface Model for ICs) - 93/67/NP IBIS and EMC Simulation - Meeting report Ross/Perrin IBIS (East) Users Group Meeting Ross European IBIS Summit Meeting Review Ross DATE98 & PCB Symposium Review Ross Editing Committee Ross/Peters BIRD44 - Interpretation of Min/Max/Weak/Strong Data Ross IBISCHK2+ (Ver 2.115) PROGRESS Flora/Rokusek Version 3.1 Parser Development Ross/Peters - Billing - Tests - Samples BUG19 - Warning for "typ" Data Outside "min and "max" Ross Cookbook Status Peters - Examples IBIS Model Review Committee Flora JC-16B - SSTL, HSTL Modeling Sessions/Rusher New Administrative Issues All 9:15 Technical Discussion BIRD42.3 - Modeling Current Waveforms Kumar/Ross BIRD45.1 - Dynamic Clamps Orhanovic/Muranyi BIRD46.1 - Relaxation of Some IBIS Model File Name Flora Restrictions BIRD47 - Remove Pin Name as a Sub-Param of the Peters [Pin List] Keyword New Technical Issues All 9:50 Wrap Up and Next Meetings Plans Ross 9:55 Sign Off From owner-ibis Fri Mar 6 12:28:17 1998 Received: from shamu.svd.avanticorp.com (root@mailhost.avanticorp.com [207.220.204.13]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id MAA01544; Fri, 6 Mar 1998 12:28:16 -0800 (PST) Received: from arcs100.svd.avanticorp.com (root@arcs100.svd.avanticorp.com [172.16.0.170]) by shamu.svd.avanticorp.com (8.8.8/8.8.5) with ESMTP id MAA17656; Fri, 6 Mar 1998 12:25:31 -0800 (PST) Received: from iris.svd.avanticorp.com (iris.svd.avanticorp.com [172.16.5.78]) by arcs100.svd.avanticorp.com (8.8.8/8.8.5) with SMTP id MAA05286; Fri, 6 Mar 1998 12:25:29 -0800 (PST) Received: by iris.svd.avanticorp.com (SMI-8.6/SMI-SVR4) id MAA07631; Fri, 6 Mar 1998 12:16:13 -0800 Date: Fri, 6 Mar 1998 12:16:13 -0800 From: nikolai@avanticorp.com (Nikolai Bannov) Message-Id: <199803062016.MAA07631@iris.svd.avanticorp.com> To: ibis@eda.org, ibis-info@eda.org Subject: what is Vmeas X-Sun-Charset: US-ASCII Hi Ibis Gurus, Could anybody expalain me what is Vmeas. What standard says about Vmeas: | Keyword: [Model] | Sub-Params: Vmeas, Cref, Rref, Vref | The Vmeas, Cref, Rref, and Vref | subparameters are optional. | The Cref and Rref subparameters correspond to the test load | that the manufacturer uses when specifying the propagation | delay and/or output switching time of the device. The Vmeas | subparameter is the reference voltage level that the | manufacturer uses for the component. Include Cref, Rref, and | Vmeas information to facilitate board-level timing simulation. | The assumed connections for Cref, Rref, and Vref are shown in | the following diagram: | | _________ | | | | | |\ | Rref | |Driver| \|------o----/\/\/\----o Vref | | | /| | | | |/ | === Cref | |_________| | | | | GND | Other Notes: A complete [Model] description normally contains the following | keywords: [Voltage Range], [Pullup], [Pulldown], [GND Clamp], | [POWER Clamp], and [Ramp]. Does anybody know what is Vmeas? Does it have any relation to [Voltage Range] ? << The Vmeas subparameter is the reference voltage level that the manufacturer uses for the component. >> this definition doesn't seem to me specific enough . Thank you very much Nik nikolai@avanticorp.com From owner-ibis Fri Mar 6 14:54:53 1998 Received: from relayhost.vlsi.com (relayhost.vlsi.com [134.27.20.23]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id OAA04392 for ; Fri, 6 Mar 1998 14:54:52 -0800 (PST) Received: (from nobody@localhost) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) id OAA24814 for ; Fri, 6 Mar 1998 14:51:37 -0800 Received: from anubis.tempe.vlsi.com(134.27.128.1) by tweety via smap (V2.0) id xma024762; Fri, 6 Mar 98 14:51:10 -0800 Received: from mailserver.tempe.vlsi.com (mailserver.tempe.vlsi.com [134.27.128.5]) by relayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/101195) with ESMTP id PAA19595 for ; Fri, 6 Mar 1998 15:51:09 -0700 Received: from tempe.vlsi.com ([134.27.133.12]) by mailserver.tempe.vlsi.com (Netscape Mail Server v2.02) with ESMTP id AAA18637 for ; Fri, 6 Mar 1998 15:51:08 -0700 Sender: dc.sessions@tempe.vlsi.com (D.C. Sessions) Message-ID: <35007DDC.D297EE0E@tempe.vlsi.com> Date: Fri, 06 Mar 1998 15:51:08 -0700 From: "D. C. Sessions" Reply-To: ibis@vhdl.org Organization: VLSI Technology Inc. X-Mailer: Mozilla 4.03 [en] (X11; U; SunOS 5.5.1 sun4m) MIME-Version: 1.0 To: ibis@eda.org Subject: Re: IBIS/JEDEC-16 References: <3.0.3.32.19980306110327.006d32d8@mail.nesa.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dr. Edward P. Sayre wrote: > I concur that IBIS and JEDEC-16 should meet periodically. You chip guys > have a definite interest in device qualitative descriptions, threshold > definitions and some application information is assembled and published, > but interoperability, modeling (SPICE and IBIS) and other user oriented > stuff is often left to the lab motorheads to complete. The result is that > it often doesn't get done soon enough for our purposes. The result is that is often doesn't get done soon enough for ANY purposes. Keep in mind that the ICs that I design have to talk over transmission media to chips that others design, and it's not much help if their models aren't ready when I'm designing. Worse yet (and part of the reason for JC-16B) is that some of the *standards* were introduced without any upfront analysis (read modelling) and are crippled thereby. If I were feeling nasty I'd mention GTL at this point. > By the way does JEDEC-16 have a web site with current drafts and standards? Would you believe http://www.eia.org/jedec/download/freestd/jesd8-xx/ The domain should be familiar. -- D. C. Sessions dc.sessions@tempe.vlsi.com From owner-ibis Tue Mar 10 13:04:34 1998 Received: from ganymede.or.intel.com (ganymede.or.intel.com [134.134.248.3]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id NAA29474; Tue, 10 Mar 1998 13:04:33 -0800 (PST) Received: from ichips-jf.jf.intel.com (ichips-jf.jf.intel.com [134.134.50.200]) by ganymede.or.intel.com (8.8.6/8.8.5) with ESMTP id NAA05333; Tue, 10 Mar 1998 13:09:19 -0800 (PST) Received: from xtg801 (xtg801.pdx.intel.com [134.134.120.169]) by ichips-jf.jf.intel.com (8.8.8/8.8.7) with ESMTP id NAA17261; Tue, 10 Mar 1998 13:01:40 -0800 (PST) Received: from ichips.intel.com by xtg801 (8.8.8/WW2.1 (Jones Farm)) id NAA21445; Tue, 10 Mar 1998 13:01:40 -0800 (PST) Message-Id: <199803102101.NAA21445@xtg801> X-Mailer: exmh version 2.0delta 6/3/97 To: nikolai@avanticorp.com (Nikolai Bannov) cc: ibis@eda.org, ibis-info@eda.org Subject: Re: what is Vmeas Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Tue, 10 Mar 1998 13:01:39 -0800 From: Stephen Peters Hello Nick: On Fri, 06 Mar 1998 12:16:13 PST you wrote > Hi Ibis Gurus, > > Could anybody expalain me what is Vmeas. > > > Well, the best way I can explain it is thru example. Suppose you're measuring the propagation delay thru a simple gate, as shown in the example below: __________________________________________ / input / ____________/| | | | ____________|_______________________ | | \| output | \-- Vmes | |\_____________________________ | | | | |<------- Tpd --------->| The propagation delay (Tpd) is measured from a specific point on the input waveform, to when the output waveform crosses a specific voltage. This voltage is referred to a 'Vmes' (or measurement voltage). For CMOS and TTL logic Vmeas is generally 1.5v. Knowing Vmeas is important because CAE tools that perform system timing calculations use this value to determine how to derate device propagation delay due to interconnect. I hope this helps. Regards, Stephen Peters Intel Corp. From owner-ibis Wed Mar 11 17:43:29 1998 Received: from shamu.svd.avanticorp.com (root@mailhost.avanticorp.com [207.220.204.13]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id RAA26190; Wed, 11 Mar 1998 17:43:29 -0800 (PST) Received: from arcs100.svd.avanticorp.com (root@arcs100.svd.avanticorp.com [172.16.0.170]) by shamu.svd.avanticorp.com (8.8.8/8.8.5) with ESMTP id RAA10715; Wed, 11 Mar 1998 17:40:38 -0800 (PST) Received: from iris.svd.avanticorp.com (iris.svd.avanticorp.com [172.16.5.78]) by arcs100.svd.avanticorp.com (8.8.8/8.8.5) with SMTP id RAA23208; Wed, 11 Mar 1998 17:40:37 -0800 (PST) Received: by iris.svd.avanticorp.com (SMI-8.6/SMI-SVR4) id RAA09356; Wed, 11 Mar 1998 17:31:15 -0800 Date: Wed, 11 Mar 1998 17:31:15 -0800 From: nikolai@avanticorp.com (Nikolai Bannov) Message-Id: <199803120131.RAA09356@iris.svd.avanticorp.com> To: ibis@eda.org, ibis-info@eda.org Subject: what is dut? a question to ibis gurus X-Sun-Charset: US-ASCII Hi Ibis Gurus, Could anybody expalain me what is X_dut. What standard says about ..._dut | Keywords: [Rising Waveform], [Falling Waveform] | Sub-Params: R_dut, L_dut, C_dut | The 'fixture' subparameters specify the loading conditions | under which the waveform is taken. The R_dut, C_dut, and | L_dut subparameters are analogous to the package parameters | R_pkg, C_pkg, and L_pkg and are used if the waveform includes | the effects of pin inductance/capacitance. The diagram below | shows the interconnection of these elements. | | PACKAGE | TEST FIXTURE | _________ | | | DUT | L_dut R_dut | L_fixture R_fixture | | die |---@@@@@--/\/\/\--o-----|--@@@@---o---/\/\/\----- V_fixture | |_________| | | | | | | | | | | | | C_dut === | === C_fixture | | | | | | | | | GND | GND | | NOTE: The use of L_dut, R_dut, and C_dut is strongly | discouraged in developing Waveform data from simulation | models. Some simulators may ignore these parameters because | they may introduce numerical time constant artifacts. | All tables assume that the die capacitance is included. | Potential numerical problems associated with processing the | data using the effective C_comp for effective die capacitance | may be handled differently among simulators. |----------------------------------------------------------------------------- So, is it correct that --- 1 --- if L_dut, R_dut, and C_dut are not given, --- then R_pkg, C_pkg, and L_pkg should be assumed included in place of L_dut, R_dut, and C_dut --- 2 --- if L_dut, R_dut, and C_dut are given, --- then R_pkg, C_pkg, and L_pkg should be ignored (and not included in DUT die) in the figuere above --- 3 --- C_comp should be ALWAYS added to the circuit (it is a part of DUT die) --- 4 --- finally, what "dut" stands for ? (acronim, abbreviation, ibis inventor?) why "use of L_dut, R_dut, and C_dut is strongly discouraged" ? Thank you very much Nik nikolai@avanticorp.com From owner-ibis Fri Mar 13 18:34:16 1998 Received: from newsgw.mentorg.com (newsgw.mentorg.com [192.94.38.66]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id SAA11939; Fri, 13 Mar 1998 18:34:15 -0800 (PST) Received: from em-wv03.wv.mentorg.com by newsgw.mentorg.com (8.8.8/CF5.40F) id SAA17508; Fri, 13 Mar 1998 18:30:57 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.7.5/CF5.38R) id SAA25785; Fri, 13 Mar 1998 18:30:54 -0800 (PST) From: bobr@wv.mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA04866; Fri, 13 Mar 98 18:31:26 PST Date: Fri, 13 Mar 98 18:31:26 PST Message-Id: <9803140231.AA04866@bob> To: ibis-users@eda.org, ibis@eda.org Subject: New s2ibis2 executable for Win95. To All: This is to inform you that a Windows95 version of s2ibis2 has been uploaded to eda.org under /pub/ibis/s2ibis/s2ibis2_nt/s2ibis2Win95.zip. It works with HSPICE. This is contributed by Scott McMorrow of SiQual corporation. It contains some fixes including using 5 decimal digits in the tables for better resolution and also providing 251 points in the Waveform tables. A utility is provided to filter these points to 100 by taking the first 75 points and sampling the rest. In this way there is high resolution for the first part of the response where the rapid transitions should occur and also enough points to capture the convergence to the final DC value. Scott's email address and other information is contained in the .zip file if you have comments or questions. Thanks to Scott for contributing this. Bob Ross Interconnectix Business Unit/Mentor Graphics From owner-ibis Tue Mar 17 09:12:21 1998 Received: from ganymede.or.intel.com (ganymede.or.intel.com [134.134.248.3]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id JAA07736 for ; Tue, 17 Mar 1998 09:12:20 -0800 (PST) Received: from ichips-jf.jf.intel.com (ichips-jf.jf.intel.com [134.134.50.200]) by ganymede.or.intel.com (8.8.6/8.8.5) with ESMTP id JAA08613 for ; Tue, 17 Mar 1998 09:17:51 -0800 (PST) Received: from xtg801 (xtg801.pdx.intel.com [134.134.120.169]) by ichips-jf.jf.intel.com (8.8.8/8.8.7) with ESMTP id JAA04744 for ; Tue, 17 Mar 1998 09:09:24 -0800 (PST) Received: from ichips.intel.com by xtg801 (8.8.8/WW2.1 (Jones Farm)) id JAA29289; Tue, 17 Mar 1998 09:09:24 -0800 (PST) Message-Id: <199803171709.JAA29289@xtg801> X-Mailer: exmh version 2.0delta 6/3/97 To: ibis@eda.org Subject: IBIS Open Forum Minutes 3/13 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Tue, 17 Mar 1998 09:09:22 -0800 From: Stephen Peters DATE: 3/17/98 SUBJECT: 3/13/98 EIA IBIS Open Forum Minutes VOTING MEMBERS AND 1998 PARTICIPANTS LIST: AMP (Martin Freedman) Applied Simulation Technology Norio Matsui, Raj Raghuram Cadence Design (& UniCAD) C. Kumar, Don Telian, Patrick Riffault, Craig Lewis, Greg Fitzgerald, Paul Galloway, Patrick Dos Santos, Catherine Weiss, Alain Tribaudot, Geoffrey Ellis* Cypress (Bruce Wenniger) Digital Equipment Corp. Jeff Chu*, Greg Edlund*, Bob Haller Hewlett Packard (EEsof, etc.) Karl Kachigan, Henry Wu, Paul Gregory High Design Technology Razvan Ene HyperLynx Kellee Crisafulli, Matthew Flora* Incases Olaf Rethmeier*, Scott Jacobson, Werner Rissiek Intel Corporation Stephen Peters*, Arpad Muranyi*, Frank Kern*, Will Hobbs, Prakash Radhakrishnan Columbia, SC (formerly NCR) Dave Moxley* Mentor Graphics (Zeelan, Bob Ross*, George Opsahl, Mark Noneman, Interconnectix, etc.) Tom Dagostino, Karine Loudet, Jean Oudinot, Manuel De Almeida, Stephane Rousseau, Nevin Orhanovic* Mitsubishi Hoang Nguyen*, Tam Cao Motorola (Ron Werner) National Semiconductor Syed Huq*, Cheng-Yang Kao, John Goldie, Ikchang Song North East Systems Associates Edward Sayre, Kathy Breda (NESA) NEC (Hiroshi Matsumoto) Quantic EMC (Mike Ventham) Texas Instruments Thomas Fisher, Harvey Stiegler, Vincent Chang, Jean-Claude Perrin*, Peter Forstner Thomson-CSF Jean-Marc Claveau, Laurent Duzaic, Saverio Lerose, Benoit Meyniel, Jean Lefebvre Viewlogic Jon Powell, Chris Rokusek, Guy de Burgh, Gary Mandel VeriBest Ian Dodd, David Weins, Ian Gabbitas VLSI Technology D.C. Sessions* Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1998: Actel Eric Tardif, Emmonvelle Gaudin Aerospatiale Lionel Dreux, Claude Huet Alcatel (Bell, Espace, etc.) John Fitzpatrick, W. Temmerman, Laure Bessettes, Jean-Claude Pourtau, Daniel Peron ALS Design Yves Mouquet Ansoft Eric Bogatin Apple Fred Floresca, Danny Itani Apteq Design Systems Dan FitzPatrick Avanti Nik Bannov* CERN Olivier Clere, Jean-Michel Sainson, Rudi Zurbroken Compaq Shariq Rahma EIA Patti Rusher* EMC Fawn Engelmann ENST, Paris Jean-Jacques Charlot European CAD Standardization Adam Morawiec Intitiative (ECSI) Fairchild Semiconductor Peter LaFlamme H.A.S Electronics Haruny Said Intracon Design Ltd. Derek Laidlaw Philips Semiconductor Todd Andersen Scottish Electronics Robert Easson Manufacturing Center (SEMC) Seagate Vanessa Howard SGS-Thomson Philippe Lefevre Siemens Gerald Bannert, Bernhard Unger, Christian Marot, Miguel Hernandez, Gil Russell* Symmetry Andy Hughes Tektronix Nassrin Ghahyasi Ultratest International Chris O'Connor Xilinx Susan Wu In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode April 3, 1998 (916) 356-9200 5-28516 6935733 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM Geoffrey Ellis from Cadence stated that he is involved with IBIS Version 2.1 and IBIS Version 3.0 utilities development Nik Bannov of Avanti is working on resurrecting the Meta I/O product and on Version 2.1 and Version 3.0 translations. D.C. Sessions invited and introduced Gil Russell of Siemens who is Chair of the JEDEC 16B committee. Gil's interest is in developing simulation models for the components and methods considered by the subcommittee. Patti Rusher affirmed that JEDEC now has full divisional status under EIA. Jean-Claude Perrin of Texas Instruments in France participated in the European IBIS Summit and is Chair of the IEC working group on IBIS Simulation and EMC Modeling. MEMBERSHIP UPDATE AND TREASURER'S REPORT Patti Rusher had issued invoices. She reports that North East Systems Associates (NESA) is a new member and has received payment from Mitsubishi. She has gotten other payments, but the accounting system is still not functioning properly for a detailed ledger report. Bob Ross and Patti will discuss off-line some invoice duplication issues. Patti also noted that the invoices for $2084 for ibischk3 parser source code have been generated and mailed. REVIEW OF MINUTES AND AR'S The AR's will be discussed at the meeting. No corrections were noted on the previous two sets of meeting Minutes. MISCELLANY/ANNOUNCEMENTS Bob Ross indicated that he still plans the Majordomo conversion when he has time. Later, Bob stated that Syed Huq will ask on the IBIS reflector for Roster Updates for 1998. PRESS AND WEB PAGE UPDATES Bob Ross reported that the March 2, 1998 issue of EDN, pp. 14-16, has the article "EDA Companies Tackle PCB-Board Design" which discusses several companies with IBIS capability. NEW MODELS AVAILABLE, LIBRARY UPDATE Bob noted that Jon Powell had inadvertently deleted the IBIS models page that was linked from the EIA IBIS home page. Jon expects to restore it, and Syed Huq will ask Jon on how it is progressing. Matthew Flora reported that he found a new Motorola link for IBIS models. It has columns for several technologies, but currently IBIS models exist for the LCX technology. He submitted the link later as http://mot2.indirect.com/models/bin/logic_ic.html He cautioned that while the tables look good, there exists some binary data encoding or corruption in the uploaded files. Matthew has contacted Motorola regarding this. OPENS FOR NEW ISSUES Bob Ross on BUG24 - Errors not issued under first of several [Define Package Model] keywords. Bob Ross on s2ibis2 for Win95. INTERNATIONAL PROGRESS - IEC 62014-1 (IBIS Version 2.1) - Patti Rusher still has not heard on the status. - EIAJ III (I/O Interface Model for ICs) - Bob reported that the EIAJ subcommittee plans to have a web site in March 1998 with access to an English translation of the Version 1.0 document. - IEC 93/67/NP IBIS and EMC Simulation - Bob reported on the meeting of national experts held in Paris on Friday, February 27, 1998. Bob is the US representative. Other national representatives from several countries participated along with the French committee within an official French standardization body: UTE. The purpose of the meeting was to review the committee activities and to provide input to the pending IEC 93/67/NP new work item proposal. This meeting was conducted as a working group meeting under IEC TC93/WG5 which was formed after IEC pushed back on the original IEC 93/60/NP proposal. The group's charter is to produce a new work item proposal with international concurrence for a project to standardize on models for simulating EMI emissions and also for simulating susceptibility to emissions. The presentation and draft document show some standardized measurement setups and some results. The proposal is for creating equivalent models of internal noise sources within components along with describing some coupling to pins and supplies. The proposal also provides for coupling from internal EMI noise sources to the device itself. The committee had chosen the IBIS format as the basis for doing these additions because of the usage of the IBIS format in the simulators of interest. The group intends to work on the proposal to consider submitting it to IEC consideration as a new work item. Bob suggested that EDA tool vendors would need to be involved with this activity for the committee to produce and acceptable simulation model. Note, this committee is chaired by Jean-Claude Perrin who called in after this report was given. IBIS EAST USERS GROUP ACTIVITIES Greg Edlund reported on the IBIS User's Group meeting will hold a meeting on Thursday, March 19, 1998 at Digital Equipment. It will cover the pending BIRD on an Accuracy and Testing Document, some tools activities, and some reports on the European IBIS Summit. Greg also is holding a meeting of the Accuracy subgroup on Thursday, March 26, 1998 to work on the Accuracy document. Greg stated that some of the work by Greg and Bob Haller documented in the DesignCon98 paper will be applied. Bob Ross recommended that this document be generated separate to IBIS Version 3.0. It already is self-contained, comprehensive subject. There could be some controversial areas such as test loads and methodology, and Bob does not want the activity to bog down the progress toward IBIS Version 3.1. So, while a BIRD proposal would be in context of issuing an Appendix to IBIS Version 3.1, a BIRD would not be approved until the document is completed. The document itself must focus on the methodology and not make references to any commercial EDA product to remain within the scope of what is allowed within the EIA rules of operation. EUROPEAN IBIS SUMMIT REPORT Bob Ross asked if there was any feedback on the European IBIS Summit. Syed Huq felt it was a very successful meeting and thanked Mentor Graphics, Cadence, and High Design Technology for providing the support. The meeting was well attended and the 13 presentations filled the day. Syed appreciated that all the presentations had been uploaded. Bob also felt that the Summit was successful and stated that the people in Europe were critical for handling the local logistics. He stated that the next European IBIS Summit will probably be held with DATE99 in March in Munich, Germany. DATE98 AND PCB SYMPOSIUM FEEDBACK Bob Ross also asked if there was any feedback on the Design Automation and Test in Europe show. In general Bob and others felt that these were good conferences. EDITING COMMITTEE Bob Ross reported that he will upload the unofficial IBIS ver3_1b.ibs update in the /pub/ibis/wip directory of eda.org. It corrects a few editorial errors including the [End Electrical Description] and [End Board Description] nomenclature inconsistency and other issues reported by Atul Agarwal. The BNF AR remains. AR - Bob Ross generate and post a BNF for IBIS Version 3.0 (an IBIS Version 3.0 ratification AR). BIRD44 - INTERPRETATION OF MIN/MAX/WEAK/STRONG DATA Bob Ross reported that he contacted Andy Ingraham regarding submitting BIRD44.1 to capture the agreements of the February 13, 1998 meeting. The extension will use only slow/weak and fast/strong nomenclature. Andy will also state the other keywords in Version 3.0 that might be affected by this change. Andy indicated that he expected to do this. AR - Andy Ingraham to issue BIRD44.1 with the changes and extensions noted above. IBISCHK2+ (VER 2.115) PROGRESS As previously reported, Matthew Flora and Chris Rokusek worked together to produce a set of executables including a DOS32 executable for ibischk2+ Version 2.1.15 which Bob Ross Uploaded on eda.org. Also Matthew reported that fixes to BUG22 and BUG23 were added to ibischk2+ and sent to Atul Agarwal for inclusion in the ibischk3 development. Bob asked that Matthew and Chris continue adding bug fixes to the ibischk2+ code, but that we will not release executables until we have a stable set of fixes. As more bugs are discovered and fixed as part of the ibischk3 project, Bob would like Matthew, Chris, and Atul to work together to get the information for ibischk2+ updates incorporated in the ibischk2+ code. As an example, BUG8 is fixed in ibischk3, but has not been moved to ibischk2+ because we did not have the resources to fix it when it was reported. VERSION 3.1 PARSER DEVELOPMENT Around February 20, 1998, the first release of ibischk3 was distributed to the 12 companies that supported the development. Matthew Flora is doing the distribution from source code that Atul Agarwal delivers to him. Matthew has been adding a DOS32 ibischk3.exe executable so people can use the code. Atul reported that he has included the fixes to BUG22, BUG23, and also BUG8 in the first release. The first release included implementations of all of the IBIS Version 3.0 features except the package model and electrical board descriptions. Bob Ross reported that Atul has included eight comprehensive test files for testing and checking the ibischk3 functions that have been implemented so far. Bob reviewed these in detail - line by line, and provided some feedback to Atul. The ibischk-bug@eda.org reflector contains the officers and several people involved in the parser development projects, and questions regarding ibischk3 details raised by Atul are answered on this reflector. Atul is now working on the package model extensions and on the electrical board description. Atul has just reported that he has a correction release based on issues raised on the code so far. Bob asked Matthew to communicate with Atul and get a new copy for distribution. AR - Matthew Flora work with Atul Agarwal to distribute a new release of ibischk3. As previously reported, the invoices have been sent out to the companies funding the ibischk3 parser development. COOKBOOK Stephen Peters reports that Greg Edlund and Bob Haller from the IBIS East Users Group are now participating in the Cookbook update project. They will provide contributions to the Test and Validation chapter. Bob Ross suggested dropping all the ARs related to supplying examples to the Cookbook since no one has acted on these. Everyone agreed with this, so the example ARs are removed. BUG19 - WARNING FOR "typ" DATA OUTSIDE "min" AND "max" Bob Ross had been asked by Atul Agarwal whether he wanted Atul to add this enhancement in ibischk3. Atul has already implemented some value testing for the ibischk3 [Model Spec] subparameters. BUG19 also deals with checking to see if typical parameters fall between the min and max parameters. When originally issued by Paul Gregory, BUG19 was concerned with values in the I/V tables. However per the discussion at the December 17, 1998 meeting we felt that there were cases where such a test would issue warnings against correct data - particularly for BiCMOS devices. However, we felt the idea was still valid for subparameters such as C_comp, L_pkg, C_pkg and R_pkg. However, we did not authorize that this BUG be fixed at that time. Bob now suggested that we authorize its implementation for the above subparameters and also for all of the Voltage Rails. The committee agreed. AR - Bob Ross communicate to Atul Agarwal to implement the BUG19 enhancement for the keywords and subparameters above. BUG24 - ERRORS NOT ISSUED UNDER FIRST OF SEVERAL [Define Package Model] KEYWORDS Bob Ross added this new agenda item for discussion here because Atul Agarwal issued BUG24 and also provided the solution. BUG24 applies to ibischk2+, but this bug would get in the way of test case development for ibischk3. Since the provided solution was simple, Bob Ross suggested that we fix it and also add the fix to the ibischk2+ source code. Bob also suggested that BUG24 be classified as Severe, Medium since real errors can be missed. IBIS MODEL REVIEW COMMITTEE DISCUSSION Bob Ross reported that one company is interested in getting some IBIS models reviewed. Bob had asked the request be forwarded to Matthew Flora. Matthew has not yet seen the request. D.C. Sessions indicated that the VLSI IBIS models are available for review. Bob has completed the permission request, and D.C. indicated that he is ready to upload the several Megabytes of IBIS models to Bob's site for the purpose of review. Others may also receive the models if the provide D.C. a letter at the VLSI address on the roster. Bob listed the complete Model Review Committee again and the e-mail addresses are given in the minutes. The contact point is Matthew Flora. Matthew Flora, HyperLynx mbflora@hyperlynx.com Bob Ross, Interconnectix/Mentor Graphics bob_ross@mentorg.com Olaf Rethmeier, Incases orethmeier@pad.incases.com Chris Rokusek, Viewlogic crokusek@qdt.com Paul Galloway, Cadence pgjr@cadence.com Ian Dodd, VeriBest idodd@veribest.com Jon Powell, Viewlogic jonp@qdt.com JC-16B Gil Russell is serving as Chair of a JEDEC subgroup of JC-16 designated as JC-16B. Gil describes JC-16 role as standardizing on interface modeling and testing of new I/O configurations such as Series Stub Terminated Logic (STTL). However what is missing are simulation models for the devices for validating the new methodologies. Gil revealed some resulting problems in the SSTL-3 specification extensions that might have been discovered by simulation. So SSTL-2 is still the practical level. This problem provided a motivation to form the JC-16B subgroup. Gil presented the Scope statement that the committee wants to generate models related to the new technologies considered by JC-16 and to be used for verification and design support. For background, D.C. Sessions is a member of JC-16B and suggested that IBIS format was an ideal candidate for fulfilling the modeling requirements. Furthermore, he suggested that EDA vendors need to participate in such model development activities. D.C. (was) volunteered to serve as a liaison between JC-16B and the IBIS committee, and he invited Gil to participate in the IBIS Open Forum meeting. Since the Scope statement was quite lengthy, Bob Ross asked Gil to provide a text copy to be distributed to the IBIS reflector. Furthermore, Bob invited Gil to continue to participate and monitor the IBIS activities since the Open Forum participation public and is open to all interested people. D.C., Gil and Patti Rusher discussed further a suggestion that the IBIS Open Forum meet at the December, 1998 meeting in San Diego, California. D.C. proposed the IBIS Summit meeting be held with the JEDEC group to foster interaction. He proposed that this replace the semi-annual IBIS Summit meeting associated with DesignCon in January in Santa Clara. Bob Ross indicated that this would have to be considered further since the IBIS community has had very successful history working with the DesignCon staff and holding meetings in January. Bob asked about other quarterly meeting locations to see if they happened to be at other potential IBIS Summit meeting sites, but the other JEDEC quarterly meetings tended to be at international locations. Bob would also consider an additional joint meeting in San Diego in December. The possibility of a joint meeting is open to further discussion. S2IBIS2 Bob Ross reported that he uploaded a copy of s2ibis2 for Windows95 that was contributed by Scott McMorrow of SiQual corporation. It works with HSPICE. Scott extended the columns to 5 decimal points for better accuracy and resolution and increased the length of the waveform table to 251 points. He also provides a utility to keep the first 75 points and sample the rest for a total of 100 points - the IBIS limit (if it is needed by the EDA tool). In this way he can get good resolution on the first part of the response where the data is changing and also converge accurately to the final DC value. Bob indicated that the .zip file which includes documentation is located on eda.org under /pub/ibis/s2ibis/s2ibis2_nt. (Late note, with a .dll file in the documentation, this executable also works with Windows NT). Scott's e-mail is provided for comments and questions. BIRD42.3 - MODELING CURRENT WAVEFORMS Bob Ross reported that BIRD42.3 and related topics were discussed at the the European IBIS Summit. However, he was not ready to discuss this at this meeting. BIRD45.1 - DYNAMIC CLAMPS Arpad Muranyi reported that he met with Bob Ross and Chris Reid at Mentor Graphics on February 11, 1998 to agree upon a proposal. Initially the investigation was to see whether the [Driver Selection] mechanism could be used as originally suggested by Dave Moxley. After some discussion the group reached an agreement on a comprehensive extension that includes the BIRD45.1 dynamic clamp mechanism and also some active latching feature. Bob outlined the revised proposal. A new Model_type will be proposed to cover both the dynamic Clamp mechanism of BIRD45.1, but with fewer new keywords, and will also include the latching mechanism. Bob noted that the structure models is exactly the same as the Bus Hold structure that is currently being implemented in devices. Threshold subparameters for for voltage triggering would be added to the model for typ, min, and max in a four column format similar to those under [Model Spec]. Input and I/O models would call this new [Model] to be added to the existing responses. Bob agreed to issue the revision as BIRD45.2. AR - Bob Ross issue BIRD45.2 to add the dynamic clamp and latching details under a new Model_type for a model which can be called by other models. BIRD46.1 - RELAXATION OF SOME IBIS FILE NAME RESTRICTIONS Matthew Flora still needs to issue BIRD46.1 per the AR of the last meeting to extend the filename from 8 characters to 20 characters. Bob Ross raised the issue that BIRD46 explicitly adds the period "." character as an allowed character in the file name for detail such as gtl.plus.ibs. Bob felt that while such generality was possible, it was still preferred to keep the existing restrictions for format uniformity among model providers. Stephen Peters and others on the committee agreed. So the AR is modified to just extend the filename size to 20 characters without adding the comment character. Bob also noted that a BIRD must be issued two weeks before we will vote on it so that interested parties have time to review it. AR - Matthew Flora issue BIRD46.1 to include references to the .pkg file and .ebd file and to change the limitation from 64 total characters to a limit of 20 characters and delete the references to allowing the period "." character. BIRD47 - REMOVE PIN NAME AS A SUBPARAMETER OF THE [Pin List] KEYWORD. Stephen Peters issued BIRD47 to deal with an inconsistency under the Electrical Board Description section, [Pin List] keyword. As it is currently documented, two subparameters are documented on a separate line in a unique format. The typical pin subparameters such as those for [Pin], [Pin Mapping], etc., list subparameters on the same line as the keyword. BIRD47 eliminates the pin_name subparameter and moves the signal_name subparameter to the keyword line. Because this was a syntax change from IBIS Version 3.0, BIRD47 was necessary. The committee generally agreeded with BIRD47. BIRD47 will be formally voted upon at the next meeting to comply with the two week notification requirement. However, based on the sense of the Committee, Bob Ross will authorize Atul to use the syntax of BIRD47 in the ibischk3 code. KEYWORDS UNDER [NOTES] SECTION CAUSE PARSING ERRORS In the time remaining after all of the formal agenda items including new issues were discussed, Arpad Muranyi discussed a problem. If a keyword is used as part of the text under the [Notes] keyword, and it is the first entry of the line, then ibischk2+ and ibischk3 report an incorrect error. Matthew Flora stated that IBIS requires the keywords to start on the first column. If the [Notes] text was formated so that it was indented, but the line started with a bracketed keyword, then this would be a bug which could be detected and corrected. Arpad noted that there was no restriction that the [Notes] text has to be indented. Bob Ross noted that this would be a truly ambiguous case - you would not know if the notes text was intended to include the keyword name or whether it was intended to be terminated by a new keyword that was not positioned properly. Arpad stated that he would write up the problem so we could consider it further based on its specific description. AR - Arpad Muranyi document the concern and send it to ibischk-bug@eda.org [Done]. DISTINCT SIGNAL NAMES Matthew Flora asked whether it would be considered a specification violation or an error if the [Pin] signal_name entry was the same for different models. This was discussed briefly. Bob Ross felt that while IBIS documents what is intended for signal_name (the pin signal name from the component databook), the entry is for information only. EDA tools that use IBIS models do not rely on the entry, and there are cases where good IBIS models can be created by just stubbing in any entry to fill the column. In the electrical board description, the signal_name subparameter column does have some meaning for documenting the POWER, GND, and NC pins since [Path Description]s are not required for these pins. Matthew felt that this was still an error for the [Pin] keyword. Bob suggested that Matthew either issue a BIRD to suggest a clarification in the IBIS specification or a BUG to raise formally the issue that a Warning should be issued if different signal_names exist for the same model. NEXT MEETING: The next teleconference meeting is on Friday, April 3, 1998, 8:00 A.M. to 9:55 A.M. BIRD46.1 and BIRD47.1 are scheduled for votes. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentorg.com Modeling Engineer, Interconnectix BU of Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785 huq@rockie.nsc.com Staff Applications Engineer, National Semiconductor, M/S A-2595 2900 Semiconductor Drive, Santa Clara, CA 95052 SECRETARY: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-56 2111 NE 25th Ave. Hillsboro, Oregon 97124-5961 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Senior Scientist, Viewlogic (formerly Quad Design) 1385 Del Norte Rd., Camarillo, CA 93010 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ============================================================================== From owner-ibis Tue Mar 17 15:40:43 1998 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id PAA14425 for ; Tue, 17 Mar 1998 15:40:41 -0800 (PST) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id PAA13948 for ; Tue, 17 Mar 1998 15:37:51 -0800 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (3.2) id xma013768; Tue, 17 Mar 98 15:37:35 -0800 Received: from lightning2.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA09159 for ibis@vhdl.org; Tue, 17 Mar 98 15:37:34 -0800 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA10382; Tue, 17 Mar 98 15:39:52 PST Date: Tue, 17 Mar 98 15:39:52 PST From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9803172339.AA10382@rockie.nsc.com> To: ibis@vhdl.org Subject: IBIS Roster update Cc: huq@rockie.nsc.com IBISfans: Pls take a moment to review the entries in the Roster page for your company. This roster can be found in www.eia.org/EIG/IBIS/ibis.htm Click on 'Roster'. We try to keep this roster as current as possible. Some companies roster entry is incomplete with certain fields missing. An updated current roster allows IBIS interests and your customers to get hold of you easily. If you have gone thru mergers/consolidation etc, you may want to see who would best represent your new organization for IBIS. Pls provide me with your changes by FRI Mar27th. Simply E-mail them to me and I will update the roster page. Best Regards, Syed. Vice-Chair ANSI/EIA-656 IBIS National Semiconductor Corp. From owner-ibis Tue Mar 17 22:46:20 1998 Received: from ami4000.hei.co.kr (ami4000.hei.co.kr [202.30.128.30]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id WAA20522 for ; Tue, 17 Mar 1998 22:46:17 -0800 (PST) Received: from ami4000.hei.co.kr ([166.125.238.90]) by ami4000.hei.co.kr (8.8.8H1/8.8.8) with SMTP id PAA08599 for ; Wed, 18 Mar 1998 15:42:56 +0900 (KST) Message-ID: <350F6E77.7C93@hei.co.kr> Date: Wed, 18 Mar 1998 15:49:27 +0900 From: "Chun, Jung-Ryoon" Reply-To: jrchun@hei.co.kr Organization: HEI X-Mailer: Mozilla 3.01 (Win95; I) MIME-Version: 1.0 To: ibis@eda.org Subject: unsubscribe me Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8bit I want to be unsubscribed,, From owner-ibis Wed Mar 18 08:37:39 1998 Received: from newsgw.mentorg.com (newsgw.mentorg.com [192.94.38.66]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id IAA00480 for ; Wed, 18 Mar 1998 08:37:39 -0800 (PST) Received: from em-wv03.wv.mentorg.com by newsgw.mentorg.com (8.8.8/CF5.40F) id IAA06065; Wed, 18 Mar 1998 08:34:14 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.7.5/CF5.38R) id IAA12240; Wed, 18 Mar 1998 08:34:09 -0800 (PST) From: bobr@wv.mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA07569; Wed, 18 Mar 98 08:34:44 PST Date: Wed, 18 Mar 98 08:34:44 PST Message-Id: <9803181634.AA07569@bob> To: ibis@eda.org Subject: IBIS ver3_1b.ibs To All: I have uploaded an unofficial interim document on eda.org under /pub/ibis/wip/ver3_1b.ibs with minor editorial corrections. Also I uploaded a revised tree3_0a.txt which moved the [Model Selector] keyword to the top level. Bob Ross Interconnectix Business Unit Mentor Graphics From owner-ibis Wed Mar 18 15:45:53 1998 Received: from florida.melco.co.jp (florida.melco.co.jp [192.218.140.46]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id PAA07291 for ; Wed, 18 Mar 1998 15:45:52 -0800 (PST) Received: from melcoweb.melco.co.jp (melcoweb.melco.co.jp [192.218.140.36]) by florida.melco.co.jp (8.8.8+2.7Wbeta7/3.6Wbeta6-florida) with SMTP id IAA23312 for ; Thu, 19 Mar 1998 08:37:28 +0900 (JST) Received: from inetgw.melco.co.jp ([133.141.191.71]) by melcoweb.melco.co.jp (5.65+1.6W/3.5Wbeta) id AA10230; Thu, 19 Mar 98 08:40:46 JST Received: from meims by inetgw.melco.co.jp (1.38.193.5/3.6Wbeta5-inetgw) id AA01107; Thu, 19 Mar 1998 08:46:46 +0900 Received: from mspc030.asic.mei.melco.co.jp (meims [133.141.192.66]) by meims.mei.melco.co.jp (8.8.5/3.5Wpl7) with SMTP id IAA26099 for ; Thu, 19 Mar 1998 08:42:59 +0900 (JST) Received: from [10.97.61.53] (mpcya53) by mspc030.asic.mei.melco.co.jp (4.1/6.4J.6-AsicMst-96Jan9) id AA21438; Thu, 19 Mar 98 08:44:05 JST Date: Thu, 19 Mar 98 08:44:04 JST Message-Id: <9803182344.AA21438@mspc030.asic.mei.melco.co.jp> X-Mailer: Macintosh Eudora Pro Version 2.3-J Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-2022-JP" To: ibis@eda.org From: horik@asic.mei.melco.co.jp (Keiichi Hori) Subject: unsubscribe me I want to be unsubscribed,, From owner-ibis Fri Mar 20 11:14:51 1998 Received: from thinkpad.qdt.com (root@ppp-206-171-248-11.vntrcs.pacbell.net [206.171.248.11]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id LAA18420 for ; Fri, 20 Mar 1998 11:14:49 -0800 (PST) Received: from thinkpad.qdt.com (localhost [127.0.0.1]) by thinkpad.qdt.com (8.8.5/8.8.5) with SMTP id LAA01435 for ; Fri, 20 Mar 1998 11:10:28 -0800 Sender: root@thinkpad.qdt.com Message-ID: <3512BF24.5383E4A8@pacbell.net> Date: Fri, 20 Mar 1998 11:10:28 -0800 From: jon powell Organization: viewlogic X-Mailer: Mozilla 3.01Gold (X11; I; Linux 2.0.30 i586) MIME-Version: 1.0 To: ibis@vhdl.org Subject: ibis models page Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit TWIMC, The IBIS models web page is back on-line. please report any problems to me: jonp@pacbell.net ALso, if you have any new links for me to add. Please let me know. sincerely, Jon Powell Ibis Librarian From owner-ibis Mon Mar 23 15:11:07 1998 Received: from vlsi1.3dfx.com (vlsi1.3dfx.com [205.158.17.41]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id PAA26117 for ; Mon, 23 Mar 1998 15:11:07 -0800 (PST) Received: from exchange.3dfx.com (exchange.3dfx.com [205.158.17.242]) by vlsi1.3dfx.com (8.8.8/8.8.8) with SMTP id PAA02218 for ; Mon, 23 Mar 1998 15:07:46 -0800 (PST) Received: by exchange.3dfx.com with SMTP (Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63) id <01BD566D.44279270@exchange.3dfx.com>; Mon, 23 Mar 1998 15:06:33 -0800 Message-ID: From: Elias Lozano To: "'ibis@vhdl.org'" , "'jon powell'" Subject: RE: ibis models page Date: Mon, 23 Mar 1998 15:06:32 -0800 X-Mailer: Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit I have a problem: I would like to down load the golden parser and there is no way for me to do this. I have gone into the www.eda.org/pub/ibis/ibischk2/solaris and when I want to down load ibischk2 in my area, the only thing I get is just an executable file that cannot be down loaded. Can any one help me with this? or better yet, is this a good strategy to use this ibischk2 to check syntax in your document? any help will be appreciated. Also, can anyone send me any problems that they have had with Star-Hspice? I do get a number of problems when I try to running the tryme file under the directory of test. I would like to see just one easy example of a regular 3.3V 4 ma buffer. thanks a lot Elias >---------- >From: jon powell[SMTP:jonp@pacbell.net] >Sent: Friday, March 20, 1998 11:10 AM >To: ibis@vhdl.org >Subject: ibis models page > >TWIMC, > >The IBIS models web page is back on-line. >please report any problems to me: >jonp@pacbell.net > >ALso, if you have any new links for me to add. Please let me know. > >sincerely, >Jon Powell >Ibis Librarian > From owner-ibis Mon Mar 23 16:48:13 1998 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id QAA27495 for ; Mon, 23 Mar 1998 16:48:12 -0800 (PST) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id QAA28759; Mon, 23 Mar 1998 16:45:19 -0800 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (3.2) id xma028545; Mon, 23 Mar 98 16:44:57 -0800 Received: from lightning2.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA15305 for ibis@vhdl.org; Mon, 23 Mar 98 16:44:56 -0800 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA11124; Mon, 23 Mar 98 16:47:14 PST Date: Mon, 23 Mar 98 16:47:14 PST From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9803240047.AA11124@rockie.nsc.com> To: ibis@vhdl.org, jonp@pacbell.net, elias@3dfx.com Subject: RE: ibis models page - parser download Hi, You may try to ftp the executable file instead of a web download. The ftp site would be an anonymous and cd to /pub/ibis/ibischk2+/solaris You should select the ibischk2+ dir as that is the latest version of the parser. Regards, Syed. National Semiconductor Corp. > From owner-ibis@server.vhdl.org Mon Mar 23 16:24:49 1998 > From: Elias Lozano > To: "'ibis@vhdl.org'" , "'jon powell'" > Subject: RE: ibis models page > Date: Mon, 23 Mar 1998 15:06:32 -0800 > X-Mailer: Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63 > Content-Type> : > text/plain> ; > charset="us-ascii"> > Content-Transfer-Encoding: 7bit > > I have a problem: > > I would like to down load the golden parser and there is no way for me > to do this. > > I have gone into the www.eda.org/pub/ibis/ibischk2/solaris and when I > want to down load ibischk2 in my area, the only thing I get is just an > executable file that cannot be down loaded. > Can any one help me with this? or better yet, is this a good strategy to > use this ibischk2 to check syntax in your document? > any help will be appreciated. > > Also, > > can anyone send me any problems that they have had with Star-Hspice? > I do get a number of problems when I try to running the tryme file under > the directory of test. > > I would like to see just one easy example of a regular 3.3V 4 ma buffer. > > thanks a lot > > Elias > > >---------- > >From: jon powell[SMTP:jonp@pacbell.net] > >Sent: Friday, March 20, 1998 11:10 AM > >To: ibis@vhdl.org > >Subject: ibis models page > > > >TWIMC, > > > >The IBIS models web page is back on-line. > >please report any problems to me: > >jonp@pacbell.net > > > >ALso, if you have any new links for me to add. Please let me know. > > > >sincerely, > >Jon Powell > >Ibis Librarian > > > From owner-ibis Tue Mar 24 10:26:35 1998 Received: from relayhost.vlsi.com (relayhost.vlsi.com [134.27.20.23]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA14647 for ; Tue, 24 Mar 1998 10:26:34 -0800 (PST) Received: (from nobody@localhost) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) id KAA27517 for ; Tue, 24 Mar 1998 10:23:13 -0800 Received: from anubis.tempe.vlsi.com(134.27.128.1) by tweety via smap (V2.0) id xma027366; Tue, 24 Mar 98 10:22:17 -0800 Received: from mailserver.tempe.vlsi.com (mailserver.tempe.vlsi.com [134.27.128.5]) by relayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/101195) with ESMTP id LAA19096 for ; Tue, 24 Mar 1998 11:22:14 -0700 Received: from tempe.vlsi.com ([134.27.133.12]) by mailserver.tempe.vlsi.com (Netscape Mail Server v2.02) with ESMTP id AAA12520; Tue, 24 Mar 1998 11:22:13 -0700 Sender: dc.sessions@tempe.vlsi.com (D.C. Sessions) Message-ID: <3517F9D4.4506E3DE@tempe.vlsi.com> Date: Tue, 24 Mar 1998 11:22:12 -0700 From: "D. C. Sessions" Reply-To: IBIS Mailing list Organization: VLSI Technology Inc. X-Mailer: Mozilla 4.03 [en] (X11; U; SunOS 5.5.1 sun4m) MIME-Version: 1.0 To: si-list@silab.Eng.Sun.COM CC: skolli@smartm.com, IBIS Mailing list Subject: Re: [SI-LIST] : IBIS Modeling References: <882565D1.005BE011.00@smtphost.smartm.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit skolli@smartm.com wrote: > > Hello there! > The company I work for has assigned me the duty of creating IBIS > models for the > memory modules(SIMMs, DIMMs, etc) that we make. > > Is there some body out there who has done this in the past? Does IBIS > even have > capabilities of modeling this kind of modules? How do you go about doing > these kinds of > models. Is there material out there that explains how to measure all the > different I/V characteristics? > Do I just take the device models and plug them in and say here is the model > for the module? > Any help would be much appreciated. First off, this really belongs on the IBIS reflector. I've taken the liberty of copying it and directing followups there. In brief, the answer is that IBIS device models are *not* good enough. You absolutely need to model the substrate and the terminators (DIMM series resistors) on them. IBIS 3.1 includes the capability of defining Electrical Board Descriptions, which are basically simplified netlists of the PWB. The examples given are in fact memory modules. -- D. C. Sessions dc.sessions@tempe.vlsi.com From owner-ibis Tue Mar 24 12:35:20 1998 Received: from smtp3.ny.us.ibm.com (smtp3.ny.us.ibm.com [198.133.22.42]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id MAA16787 for ; Tue, 24 Mar 1998 12:35:19 -0800 (PST) Received: from relay1.server.ibm.com (relay1.server.ibm.com [9.14.2.98]) by smtp3.ny.us.ibm.com (8.8.7/8.8.7) with ESMTP id PAA72584 for ; Tue, 24 Mar 1998 15:26:13 -0500 Received: from US.IBM.COM (d03lms03.boulder.ibm.com [9.99.80.13]) by relay1.server.ibm.com (8.8.7/8.8.7) with SMTP id PAA93406 for ; Tue, 24 Mar 1998 15:30:17 -0500 Received: by US.IBM.COM (Soft-Switch LMS 2.0) with snapi via D03AU031 id 5030300019305160; Tue, 24 Mar 1998 15:38:36 -0500 From: D03NM035/03/M/IBM To: Subject: Ray Jelesky/San Jose/IBM is out of the office. Message-ID: <5030300019305160000002L002*@MHS> Date: Tue, 24 Mar 1998 15:38:36 -0500 MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by server.vhdl.org id MAA16788 I am out of the office from 03-21-98, returning 03-27-98. You will receive only this notification of my absence prior to my return, at which time I will respond. From owner-ibis Wed Mar 25 01:02:16 1998 Received: from mail.nwlink.com (alabama.nwlink.com [209.20.130.40]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id BAA28464 for ; Wed, 25 Mar 1998 01:02:16 -0800 (PST) Received: from stargate (mail.hyperlynx.com [209.20.148.70]) by mail.nwlink.com (8.8.8/8.8.8) with SMTP id AAA22550; Wed, 25 Mar 1998 00:59:17 -0800 (PST) Message-Id: <3.0.32.19980325010027.009a4ba0@mail.nwlink.com> X-Sender: kellee@mail.nwlink.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Wed, 25 Mar 1998 01:00:30 -0800 To: IBIS Mailing list , si-list@silab.Eng.Sun.COM From: Kellee Crisafulli Subject: Re: [SI-LIST] : IBIS Modeling Cc: skolli@smartm.com, IBIS Mailing list Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" At 11:22 AM 3/24/98 -0700, D. C. Sessions wrote: >In brief, the answer is that IBIS device models are *not* good enough. >You absolutely need to model the substrate and the terminators (DIMM >series resistors) on them. IBIS 3.1 includes the capability of >defining Electrical Board Descriptions, which are basically simplified >netlists of the PWB. The examples given are in fact memory modules. >D. C. Sessions >dc.sessions@tempe.vlsi.com We have built DIMM and SIMM module modules using IBIS 2.1 that do a reasonable simulation job. It requires a bit of playing with the package model and it is somewhat simulator dependant. Our simulator interpretes large RLC package values as transmission lines instead of lumped LC parameters which allows us to make a reasonable DIMM or SIMM module module using IBIS 2.1 To accomplish this we create a full circuit boad model of the DIMM or SIMM and then tweak an IBIS package model until it looks the same under several simulation conditions. The die model input capacitance must also be increased to account for the extra loading. While I agree IBIS 3.x makes this relatively easy and provides a more accurate result it is possible to get usable results with 2.1 prior to the release of the 3.x parser. From owner-ibis Wed Mar 25 01:02:13 1998 Received: from mail.nwlink.com (alabama.nwlink.com [209.20.130.40]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id BAA28461 for ; Wed, 25 Mar 1998 01:02:12 -0800 (PST) Received: from stargate (mail.hyperlynx.com [209.20.148.70]) by mail.nwlink.com (8.8.8/8.8.8) with SMTP id AAA22550; Wed, 25 Mar 1998 00:59:17 -0800 (PST) Message-Id: <3.0.32.19980325010027.009a4ba0@mail.nwlink.com> X-Sender: kellee@mail.nwlink.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Wed, 25 Mar 1998 01:00:30 -0800 To: IBIS Mailing list , si-list@silab.Eng.Sun.COM From: Kellee Crisafulli Subject: Re: [SI-LIST] : IBIS Modeling Cc: skolli@smartm.com, IBIS Mailing list Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" At 11:22 AM 3/24/98 -0700, D. C. Sessions wrote: >In brief, the answer is that IBIS device models are *not* good enough. >You absolutely need to model the substrate and the terminators (DIMM >series resistors) on them. IBIS 3.1 includes the capability of >defining Electrical Board Descriptions, which are basically simplified >netlists of the PWB. The examples given are in fact memory modules. >D. C. Sessions >dc.sessions@tempe.vlsi.com We have built DIMM and SIMM module modules using IBIS 2.1 that do a reasonable simulation job. It requires a bit of playing with the package model and it is somewhat simulator dependant. Our simulator interpretes large RLC package values as transmission lines instead of lumped LC parameters which allows us to make a reasonable DIMM or SIMM module module using IBIS 2.1 To accomplish this we create a full circuit boad model of the DIMM or SIMM and then tweak an IBIS package model until it looks the same under several simulation conditions. The die model input capacitance must also be increased to account for the extra loading. While I agree IBIS 3.x makes this relatively easy and provides a more accurate result it is possible to get usable results with 2.1 prior to the release of the 3.x parser. From owner-ibis Wed Mar 25 01:37:30 1998 Received: from exchange2.via.com.tw ([202.145.217.249]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id BAA29084 for ; Wed, 25 Mar 1998 01:37:28 -0800 (PST) Received: by exchange2.via.com.tw with Internet Mail Service (5.5.1960.3) id ; Wed, 25 Mar 1998 17:34:59 +0800 Message-ID: <4399E411E49ED111973000A0C92BD8A00257C7@exchange2.via.com.tw> From: Weber Chuang To: "'Kellee Crisafulli'" , IBIS Mailing list , si-list@silab.Eng.Sun.COM Cc: skolli@smartm.com, IBIS Mailing list Subject: RE : [SI-LIST] : IBIS Modeling Date: Wed, 25 Mar 1998 17:34:58 +0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.1960.3) Content-Type: text/plain We are PC chipset vendors, so we need to handle kinds of I/O pads and modules, so far I use real module database and then combine it with mainboard to run a backplane-style simulation for AGP and PCI and memory, though we only consider capacitance effect for connector or socket. Using lumped RLC to substitute for the trace yields odd and inaccurate waveforms. Best Regards Weber Chuang(ChingFu Chuang) SI Engineer, System Team. VIA Technologies, Inc. Taipei, Taiwan, ROC http://www.via.com.tw Very Innovative Architecture ******************** Re: [SI-LIST] : IBIS Modeling ********************* > At 11:22 AM 3/24/98 -0700, D. C. Sessions wrote: > >In brief, the answer is that IBIS device models are *not* good > enough. > >You absolutely need to model the substrate and the terminators (DIMM > >series resistors) on them. IBIS 3.1 includes the capability of > >defining Electrical Board Descriptions, which are basically > simplified > >netlists of the PWB. The examples given are in fact memory modules. > >D. C. Sessions > >dc.sessions@tempe.vlsi.com > > We have built DIMM and SIMM module modules using IBIS 2.1 that do > a reasonable simulation job. It requires a bit of playing with the > package model and it is somewhat simulator dependant. Our simulator > interpretes > large RLC package values as transmission lines instead of lumped LC > parameters > which allows us to make a reasonable DIMM or SIMM module module using > IBIS 2.1 To accomplish this we create a full circuit boad model of the > DIMM or SIMM and then tweak an IBIS package model until it looks > the same under several simulation conditions. The die model input > capacitance > must also be increased to account for the extra loading. > > While I agree IBIS 3.x makes this relatively easy and provides a more > accurate > result it is possible to get usable results with 2.1 prior to the > release of > the 3.x parser. > > > > > > > From owner-ibis Wed Mar 25 01:37:33 1998 Received: from exchange2.via.com.tw ([202.145.217.249]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id BAA29086 for ; Wed, 25 Mar 1998 01:37:31 -0800 (PST) Received: by exchange2.via.com.tw with Internet Mail Service (5.5.1960.3) id ; Wed, 25 Mar 1998 17:34:59 +0800 Message-ID: <4399E411E49ED111973000A0C92BD8A00257C7@exchange2.via.com.tw> From: Weber Chuang To: "'Kellee Crisafulli'" , IBIS Mailing list , si-list@silab.Eng.Sun.COM Cc: skolli@smartm.com, IBIS Mailing list Subject: RE : [SI-LIST] : IBIS Modeling Date: Wed, 25 Mar 1998 17:34:58 +0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.1960.3) Content-Type: text/plain We are PC chipset vendors, so we need to handle kinds of I/O pads and modules, so far I use real module database and then combine it with mainboard to run a backplane-style simulation for AGP and PCI and memory, though we only consider capacitance effect for connector or socket. Using lumped RLC to substitute for the trace yields odd and inaccurate waveforms. Best Regards Weber Chuang(ChingFu Chuang) SI Engineer, System Team. VIA Technologies, Inc. Taipei, Taiwan, ROC http://www.via.com.tw Very Innovative Architecture ******************** Re: [SI-LIST] : IBIS Modeling ********************* > At 11:22 AM 3/24/98 -0700, D. C. Sessions wrote: > >In brief, the answer is that IBIS device models are *not* good > enough. > >You absolutely need to model the substrate and the terminators (DIMM > >series resistors) on them. IBIS 3.1 includes the capability of > >defining Electrical Board Descriptions, which are basically > simplified > >netlists of the PWB. The examples given are in fact memory modules. > >D. C. Sessions > >dc.sessions@tempe.vlsi.com > > We have built DIMM and SIMM module modules using IBIS 2.1 that do > a reasonable simulation job. It requires a bit of playing with the > package model and it is somewhat simulator dependant. Our simulator > interpretes > large RLC package values as transmission lines instead of lumped LC > parameters > which allows us to make a reasonable DIMM or SIMM module module using > IBIS 2.1 To accomplish this we create a full circuit boad model of the > DIMM or SIMM and then tweak an IBIS package model until it looks > the same under several simulation conditions. The die model input > capacitance > must also be increased to account for the extra loading. > > While I agree IBIS 3.x makes this relatively easy and provides a more > accurate > result it is possible to get usable results with 2.1 prior to the > release of > the 3.x parser. > > > > > > > From owner-ibis Wed Mar 25 04:20:44 1998 Received: from lince.lander.es (qmailr@lince.lander.es [195.76.46.35]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id EAA01790 for ; Wed, 25 Mar 1998 04:20:40 -0800 (PST) Received: (qmail 9005 invoked from network); 25 Mar 1998 12:17:29 -0000 Received: from ppp-47-140.lander.es (HELO ninote) (195.76.47.140) by lince.lander.es with SMTP; 25 Mar 1998 12:17:29 -0000 Message-ID: <3518F539.A02166EB@lander.es> Date: Wed, 25 Mar 1998 13:14:50 +0100 From: "Bernardino León" Reply-To: bleon@lander.es X-Mailer: Mozilla 4.01 [en] (Win95; I) MIME-Version: 1.0 To: IBIS Mailing list , bleon@lander.es Subject: Re: [SI-LIST] : IBIS Modeling X-Priority: 3 (Normal) References: <882565D1.005BE011.00@smtphost.smartm.com> <3517F9D4.4506E3DE@tempe.vlsi.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit D. C. Sessions wrote: > skolli@smartm.com wrote: > > > > Hello there! > > The company I work for has assigned me the duty of creating > IBIS > > models for the > > memory modules(SIMMs, DIMMs, etc) that we make. > > > > Is there some body out there who has done this in the past? > Does IBIS > > even have > > capabilities of modeling this kind of modules? How do you go about > doing > > these kinds of > > models. Is there material out there that explains how to measure all > the > > different I/V characteristics? > > Do I just take the device models and plug them in and say here is > the model > > for the module? > > Any help would be much appreciated. > > First off, this really belongs on the IBIS reflector. I've taken the > liberty of copying it and directing followups there. > > In brief, the answer is that IBIS device models are *not* good enough. > > You absolutely need to model the substrate and the terminators (DIMM > series resistors) on them. IBIS 3.1 includes the capability of > defining Electrical Board Descriptions, which are basically simplified > > netlists of the PWB. The examples given are in fact memory modules. > > -- > D. C. Sessions > dc.sessions@tempe.vlsi.com From owner-ibis Wed Mar 25 08:31:34 1998 Received: from mail13.digital.com (mail13.digital.com [192.208.46.30]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id IAA05858 for ; Wed, 25 Mar 1998 08:31:34 -0800 (PST) Received: from sbuamazko2ae.zko.dec.com (sbuamazko2ae.zko.dec.com [16.29.160.92]) by mail13.digital.com (8.8.8/8.8.8/WV1.0c) with ESMTP id LAA32489 for ; Wed, 25 Mar 1998 11:28:36 -0500 (EST) Received: by sbuamazko2ae.zko.dec.com with Internet Mail Service (5.0.1458.49) id ; Wed, 25 Mar 1998 11:28:44 -0500 Message-ID: <890ED1999E9CD01197A10000F84AA1F7A2E9C7@sbuamapko3cc.eng.pko.dec.com> From: Andrew Ingraham To: "'Kellee Crisafulli'" Cc: IBIS Mailing list , si-list@silab.Eng.Sun.COM Subject: RE: [SI-LIST] : IBIS Modeling Date: Wed, 25 Mar 1998 11:28:44 -0500 X-Priority: 3 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.0.1458.49) Content-Type: text/plain >We have built DIMM and SIMM module modules using IBIS 2.1 that do >a reasonable simulation job. It requires a bit of playing with the >package model and it is somewhat simulator dependant. Our simulator >interpretes >large RLC package values as transmission lines instead of lumped LC >parameters >which allows us to make a reasonable DIMM or SIMM module module >using >IBIS 2.1 I don't mean to criticize your approach ... but this seems like a dangerous way of creating a model. In an ideal world, IBIS models *ought* to be portable such that they can be used on different platforms and different simulators and yield basically the same result, within the accuracy limits of those simulators. If there are big differences such as this (where large RLC values are treated in a fundamentally different way on some simulators), that seems like a risky thing to take advantage of. It ties your IBIS model to that simulator. How do you prevent the model from being used on another simulator? In essence, you have created a proprietary *.ibs model, similar to an Hspice model that won't work correctly on someone else's simulator. As a side note, is it even the right thing to treat large RLC package values as a transmission line? What if they represent something like a long bondwire and a big bonding pad? How do you make that choice between which way to model it in the simulator? Should the IBIS spec make such loopholes possible? Regards, Andy Ingraham From owner-ibis Wed Mar 25 12:50:11 1998 Received: from mail.nwlink.com (alabama.nwlink.com [209.20.130.40]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id MAA09922 for ; Wed, 25 Mar 1998 12:50:11 -0800 (PST) Received: from stargate (mail.hyperlynx.com [209.20.148.70]) by mail.nwlink.com (8.8.8/8.8.8) with SMTP id MAA24702; Wed, 25 Mar 1998 12:45:01 -0800 (PST) Message-Id: <3.0.32.19980325124610.009cec10@mail.nwlink.com> X-Sender: kellee@mail.nwlink.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Wed, 25 Mar 1998 12:46:12 -0800 To: Andrew Ingraham From: Kellee Crisafulli Subject: RE: [SI-LIST] : IBIS Modeling Cc: IBIS Mailing list , si-list@silab.Eng.Sun.COM Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Hi Andrew, >In an ideal world, IBIS models *ought* to be portable such that they can >be used on different platforms and different simulators and yield >basically the same result, within the accuracy limits of those >simulators. I agree completely. >If there are big differences such as this (where large RLC values are >treated in a fundamentally different way on some simulators), that seems >like a risky thing to take advantage of. It ties your IBIS model to >that simulator. How do you prevent the model from being used on another >simulator? In this instance we made the models for our own customers only. However the real issue is how good or bad it works using either method. Please try it, demonstrate the magnitude of whatever problem you are concerned. Based on comparative simulations we ran we felt the result were acceptable and useful until the version 3.x models are available and simulators are all using them. I was one of the most vocal advocates of getting modeling into IBIS for DIMM and SIMM modules and made several proposals to the IBIS committee to get this done. >In essence, you have created a proprietary *.ibs model, similar to an >Hspice model that won't work correctly on someone else's simulator. You have a valid point. However unlike Hspice it will run on all the simulators that use IBIS with slight differences in the package effects but at least they will have a model v.s. no model. Do you think it is better not to do any modeling and have users guess what the signals look like. And yes I think this sort of model is an order of magnitude better than guessing. >As a side note, is it even the right thing to treat large RLC package >values as a transmission line? What if they represent something like a >long bondwire and a big bonding pad? How do you make that choice >between which way to model it in the simulator? IBIS has never specified that the LC pin values be used as lumped values. As you may know some packages are modeled better as a lump and some model better as a transmission line. Neither is perfect for all packages. however it generally isn't possible to get devices to work if the pin is really a large lumped L so I don't see much danger here. >Should the IBIS spec make such loopholes possible? I don't see this as a loop hole. Each vendor needs to use the IBIS data to create the best results they feel possible. I don't believe we need to spend a great deal of time on this thread Andrew. I only wish to point out that it is possible to create a useable model for a DIMM or SIMM in V2.1 IBIS. I lobbied to get better SIMM and DIMM modeling into the spec. for over a year so I agree it is a much better method. I was the one that insisted that the changes proposed by Intel for their processor models also work for DIMM and SIMM modules. I understand your concerns and they are reasonable. Best wishes.. Kellee From owner-ibis Fri Mar 27 16:37:58 1998 Received: from newsgw.mentorg.com (newsgw.mentorg.com [192.94.38.66]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA27806 for ; Fri, 27 Mar 1998 16:37:57 -0800 (PST) Received: from em-wv03.wv.mentorg.com by newsgw.mentorg.com (8.8.8/CF5.40F) id QAA10291; Fri, 27 Mar 1998 16:34:34 -0800 (PST) Received: from bob by em-wv03.wv.mentorg.com (8.7.5/CF5.38R) id QAA20975; Fri, 27 Mar 1998 16:34:30 -0800 (PST) From: bobr@wv.mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA03082; Fri, 27 Mar 98 16:34:33 PST Date: Fri, 27 Mar 98 16:34:33 PST Message-Id: <9803280034.AA03082@bob> To: ibis@eda.org Subject: IBIS AGENDA 4/3/98 IBIS Open Forum Meeting Agenda for 4/3/98 Bridge Number Reservation # Passcode (916) 356-9200 5-28516 6935733 All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the Reservation Number and Passcode. 8:00 Check-In, Intros, Announcements Ross - Intros of New IBIS Participants, Meeting Quorum Ross - Membership Update and Treasurers Report Rusher - Review of Previous Meeting's Minutes (and ARs) Peters - Miscellany/Announcements All - Press & Web Page Updates Huq, All - New Models Available, Library Update Powell, All - Opens for New Issues All 8:25 Administrative and Project Discussions International/External Progress Rusher/Ross - IEC 62014-1 (IBIS Version 2.1) - EIAJ III (I/O Interface Model for ICs) - 93/67/NP IBIS and EMC Simulation Ross/Perrin - JC-16B Sessions/Russell IBIS Logo Change Rusher/Ross IBIS (East) Users Group Meetings Edlund Editing Committee Ross/Peters BIRD44 - Interpretation of Min/Max/Weak/Strong Data Ross IBISCHK2+ (Ver 2.115) PROGRESS Flora/Rokusek BUG25 - Keyword as First Word in [Notes] Causes Error Muranyi BUG26 - Parser Crashes when Calling [Package Model] Ross Version 3.1 Parser Development Ross/Peters - Billing - Tests & Samples Cookbook Status Peters IBIS Model Review Committee Flora s2ibis2 BUG1 - HSPICE Examples Do Not Work Ross/Unger New Administrative Issues All 9:15 Technical Discussion BIRD47 - Remove Pin Name as a Sub-Param of the Peters [Pin List] Keyword (Vote) BIRD42.3 - Modeling Current Waveforms Kumar/Ross BIRD46.1 - Relaxation of Some IBIS Model File Name Flora Restrictions ** BIRD48 - Add Model Orhanovic/Muranyi/Ross ** BIRD49 - Add Model Dynamic Clamps Orhanovic/Muranyi/Ross ** BIRD50 - Add Model Bus Hold Orhanovic/Muranyi/Ross ** To Be Issued BIRD45.1 - Dynamic Clamps Orhanovic/Muranyi/Ross (Consider Replacement with BIRD48, BIRD49, BIRD50) Some Technical Issues on IBIS Reflector Ross New Technical Issues All 9:50 Wrap Up and Next Meetings Plans Ross 9:55 Sign Off From owner-ibis Mon Mar 30 05:50:31 1998 Received: from tulip.com (nlheigw01.tulipcomputers.com [194.178.222.10]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id FAA20306 for ; Mon, 30 Mar 1998 05:50:19 -0800 (PST) Received: by tulip.com(Lotus SMTP MTA v1.1 (385.6 5-6-1997)) id 412565D7.00514C1F ; Mon, 30 Mar 1998 15:47:59 +0100 X-Lotus-FromDomain: TULIPTCI@TULIP@TULIPNET@TULIPINET From: "Hans Werner" To: ibis@eda.org Message-ID: <412565D7.0051FF0C.00@tulip.com> Date: Mon, 30 Mar 1998 15:57:03 +0100 Subject: IBIS Mime-Version: 1.0 Content-type: text/plain; charset=us-ascii Please Remove me from the email list. Thank you H. Werner From owner-ibis Mon Mar 30 09:47:00 1998 Received: from lsi.lsil.com (lsi.lsil.com [147.145.40.2]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id JAA24392 for ; Mon, 30 Mar 1998 09:47:00 -0800 (PST) Received: from mhbs.lsil.com ([147.145.29.36]) by lsi.lsil.com with ESMTP id JAA02292 (8.6.12/IDA-1.6 for ); Mon, 30 Mar 1998 09:43:59 -0800 Received: from sjs1.lsil.com by mhbs.lsil.com; Mon, 30 Mar 1998 09:43:58 -0800 Received: from sj65.lsil.com by sjs1 (4.1/SMI-4.1) id AA08143; Mon, 30 Mar 98 09:43:53 PST Date: Mon, 30 Mar 98 09:43:53 PST From: satishp@lsil.com (Satish Pratapneni) Message-Id: <9803301743.AA08143@sjs1> To: ibis@eda.org Subject: Re: IBIS Please Remove me from the e-mail list for now since I am switching companies in next two weeks. Thanks, -Satish Prtapneni From owner-ibis Tue Mar 31 09:05:50 1998 Received: from mail-gw5.pacbell.net (mail-gw5.pacbell.net [206.13.28.23]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id JAA18928 for ; Tue, 31 Mar 1998 09:05:50 -0800 (PST) Received: from pacbell.net (ppp-206-171-248-180.vntrcs.pacbell.net [206.171.248.180]) by mail-gw5.pacbell.net (8.8.8/8.7.1+antispam) with ESMTP id JAA03495; Tue, 31 Mar 1998 09:02:28 -0800 (PST) Message-ID: <3521214E.582D0FFC@pacbell.net> Date: Tue, 31 Mar 1998 09:01:02 -0800 From: Jon Powell Reply-To: jonp@qdt.com Organization: Viewlogic Consulting Services X-Mailer: Mozilla 4.04 [en]C-PBI-NC404 (Win95; I) MIME-Version: 1.0 To: jsynesio@us-power.com, ibis@vhdl.org Subject: Re: FW: FW: Spice Model of IBIS References: <199803310316.VAA23282@hawk.us-power.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Well, I just couldn't resist. I certainly wouldn't argue with anyone that SPICE (actually some SPICE commercial derivative) is the premier circuit simulation technology that is currently publically available. I also wouldn't argue with anyone who said that IBIS has some problems that need to be addressed. However, the market has shown that there is a need for a PCB SI simulation technology that offers features that transcend the current SPICE node based syntax. Think of the bigger problem. You need to simulate the SI and Crosstalk effects of every net on a PCB. You need MIN MAX timing from every driver to every receiver. You need SI and Noise margin numbers for every net. And you need them quickly enough so that you can use the data to turn the design a couple of times. I believe these issues are difficult to solve using SPICE as it (they) exists on the market today. Of course, I use SPICE every day. I think it is great. I just believe in using the right tool for the right job and I have more than one job to do. Here is a conceptual example: you have a 32 wire bus. Each wire couples to it's neighbors. You need to simulate every wire and the effects on that wire by it's immediate neighbors. You do not want to waste simulation time by simulating effects of the wires that are more than a couple of conductors away. How would you solve this problem using SPICE? Can it be solved automatically? How would spice represent the names of the different nets? (ie. what is the crosstalk on D13?). As for accuracy: Leave the argument of which approach is more accurate for the moment. what is the accuracy of your inputs? (PCB stack-up, SPICE model data, Dielectric constant, trace width). If you are simulating to a higher accuracy than your data inputs then you are wasting time and deceiving yourself. I think that a teacher told me this in 5th grade but I never really believed it until I started doing SI simulation. From owner-ibis Tue Mar 31 10:07:50 1998 Received: from radius1.teleport.com (radius1.teleport.com [192.108.254.35]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA19942 for ; Tue, 31 Mar 1998 10:07:49 -0800 (PST) Received: from teleport.com (pdx58-i48-38.teleport.com [204.202.167.180]) by radius1.teleport.com (8.8.7/8.7.3) with ESMTP id KAA05827; Tue, 31 Mar 1998 10:03:16 -0800 (PST) Message-ID: <35212FAE.908FD9CF@teleport.com> Date: Tue, 31 Mar 1998 10:02:22 -0800 From: Scott McMorrow X-Mailer: Mozilla 4.04 [en]C-DIAL (Win95; U) MIME-Version: 1.0 To: jonp@qdt.com CC: jsynesio@us-power.com, ibis@vhdl.org Subject: Re: FW: FW: Spice Model of IBIS References: <199803310316.VAA23282@hawk.us-power.com> <3521214E.582D0FFC@pacbell.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Jon, Well said! I agree, let's use the right tools for the job. All are appropriate within specific contexts. And lets not forget the comfort factor. Once one becomes familiar with a specific tool that does a given job, it is hard to overcome the inertia and change to a tool that might be different, if not better. You're right. If the pcb tolerance is +/- 10% and the part process tolerance is +/- 30%, simulator differences are generally inconsequential. I and my customers value my time. For my time, I generally choose a tool based upon ease of use, speed, and accuracy. In that order. Scott McMorrow SiQual Jon Powell wrote: > Well, I just couldn't resist. > > I certainly wouldn't argue with anyone that SPICE (actually some SPICE > commercial derivative) is the premier circuit simulation technology that > is currently publically available. I also wouldn't argue with anyone who > said that IBIS has some problems that need to be addressed. > > However, the market has shown that there is a need for a PCB SI > simulation technology that offers features that transcend the current > SPICE node based syntax. Think of the bigger problem. You need to > simulate the SI and Crosstalk effects of every net on a PCB. You need > MIN MAX timing from every driver to every receiver. You need SI and > Noise margin numbers for every net. And you need them quickly enough so > that you can use the data to turn the design a couple of times. I > believe these issues are difficult to solve using SPICE as it (they) > exists on the market today. > > Of course, I use SPICE every day. I think it is great. I just believe in > using the right tool for the right job and I have more than one job to > do. > > Here is a conceptual example: > you have a 32 wire bus. Each wire couples to it's neighbors. You need to > simulate every wire and the effects on that wire by it's immediate > neighbors. You do not want to waste simulation time by simulating > effects of the wires that are more than a couple of conductors away. > > How would you solve this problem using SPICE? > Can it be solved automatically? > How would spice represent the names of the different nets? (ie. what is > the crosstalk on D13?). > > As for accuracy: > Leave the argument of which approach is more accurate for the moment. > what is the accuracy of your inputs? (PCB stack-up, SPICE model data, > Dielectric constant, trace width). > If you are simulating to a higher accuracy than your data inputs then > you are wasting time and deceiving yourself. I think that a teacher told > me this in 5th grade but I never really believed it until I started > doing SI simulation. From owner-ibis Tue Mar 31 10:34:05 1998 Received: from hawk.us-power.com (hawk.us-power.com [206.147.67.2]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA20397 for ; Tue, 31 Mar 1998 10:34:04 -0800 (PST) Received: from cardinal ([209.98.11.34] (may be forged)) by hawk.us-power.com with SMTP id NAA28467; Tue, 31 Mar 1998 13:03:15 -0600 Message-Id: <199803311903.NAA28467@hawk.us-power.com> Reply-To: From: "John Synesiou" To: , Subject: RE: FW: FW: Spice Model of IBIS Date: Tue, 31 Mar 1998 12:29:42 -0600 X-Priority: 3 (Normal) X-MSMail-Priority: Normal In-Reply-To: <3521214E.582D0FFC@pacbell.net> Importance: Normal X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2106.4 Jon, You raise a good point. I raised this point originally to question the need to develop a unique syntax for IBIS, when an existing syntax would prevail. In my opinion, IBIS should describe a template using existing SPICE syntax (or XSPICE syntax) so that the engineering community can choose the best tool for their simulation and analysis, i.e. IBIS simulator or SPICE simulator. Pre PCB layout simulation could be simulated quite effectively in SPICE, with the added advantage that more extensive analysis could be done if required. IBIS simulators on the other hand have a particular purpose and hence the analysis as I understand it is limited to time domain waveforms (rise/fall time, ringing, reflections) and a simple spectral plot. For instance, I'm not sure how you would calculate the power in a termination resistor, a simple example, but you get the point. Regarding crosstalk, I'm not sure how the IBIS simulators work, but I'm sure that they don't consider crosstalk from one trace to all other traces, but instead consider only the closest traces (one or two traces). Considering that some EDA vendors IBIS simulators are actually SPICE simulators with an IBIS to SPICE translator, I would expect that this problem could also be solved in SPICE directly. I'm not sure I need to make this point, but I put it in for further discussion. My point really is that I may like to use SPICE to do more extensive analysis than is available with an IBIS simulators. I can take any IBIS model today and translate it into a SPICE model to examine various issues, SI, EMC and others. I just find the translation process time consuming and error prone. In essence, why does it have to be an either or, why can't SPICE simulators be an extension of IBIS simulators? Regards John Synesiou jsynesio@us-power.com U.S. Power, Inc Phone (612)826-1111 6497 City West Parkway Fax (612)826-1003 Eden Prairie Date: 03/31/98 MN, 55344 Time: 11:45 AM -----Original Message----- From: Jon Powell [mailto:jonp@pacbell.net] Sent: Tuesday, March 31, 1998 11:01 AM To: jsynesio@us-power.com; ibis@vhdl.org Subject: Re: FW: FW: Spice Model of IBIS Well, I just couldn't resist. I certainly wouldn't argue with anyone that SPICE (actually some SPICE commercial derivative) is the premier circuit simulation technology that is currently publically available. I also wouldn't argue with anyone who said that IBIS has some problems that need to be addressed. However, the market has shown that there is a need for a PCB SI simulation technology that offers features that transcend the current SPICE node based syntax. Think of the bigger problem. You need to simulate the SI and Crosstalk effects of every net on a PCB. You need MIN MAX timing from every driver to every receiver. You need SI and Noise margin numbers for every net. And you need them quickly enough so that you can use the data to turn the design a couple of times. I believe these issues are difficult to solve using SPICE as it (they) exists on the market today. Of course, I use SPICE every day. I think it is great. I just believe in using the right tool for the right job and I have more than one job to do. Here is a conceptual example: you have a 32 wire bus. Each wire couples to it's neighbors. You need to simulate every wire and the effects on that wire by it's immediate neighbors. You do not want to waste simulation time by simulating effects of the wires that are more than a couple of conductors away. How would you solve this problem using SPICE? Can it be solved automatically? How would spice represent the names of the different nets? (ie. what is the crosstalk on D13?). As for accuracy: Leave the argument of which approach is more accurate for the moment. what is the accuracy of your inputs? (PCB stack-up, SPICE model data, Dielectric constant, trace width). If you are simulating to a higher accuracy than your data inputs then you are wasting time and deceiving yourself. I think that a teacher told me this in 5th grade but I never really believed it until I started doing SI simulation. From owner-ibis Tue Mar 31 12:05:51 1998 Received: from InterJet.apsimtech.com (apsimtech.com [209.21.21.35]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id MAA21825 for ; Tue, 31 Mar 1998 12:05:48 -0800 (PST) Received: (from daemon@localhost) by InterJet.apsimtech.com (8.8.5/8.8.5) id LAA18931; Tue, 31 Mar 1998 11:06:39 -0800 (PST) Received: from UNKNOWN(), claiming to be "contec12" via SMTP by InterJet.apsimtech.com, id smtpd018926; Tue Mar 31 11:06:27 1998 Sender: fred@apsimtech.com Message-ID: <35213EE3.74F0@apsimtech.com> Date: Tue, 31 Mar 1998 11:07:15 -0800 From: Fred Balistreri Organization: Apsim X-Mailer: Mozilla 3.01 (X11; I; SunOS 5.3 sun4c) MIME-Version: 1.0 To: jonp@qdt.com CC: jsynesio@us-power.com, ibis@vhdl.org Subject: Re: FW: FW: Spice Model of IBIS References: <199803310316.VAA23282@hawk.us-power.com> <3521214E.582D0FFC@pacbell.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Jon Powell wrote: > > Well, I just couldn't resist. > > I certainly wouldn't argue with anyone that SPICE (actually some SPICE > commercial derivative) is the premier circuit simulation technology that > is currently publically available. I also wouldn't argue with anyone who > said that IBIS has some problems that need to be addressed. > > However, the market has shown that there is a need for a PCB SI > simulation technology that offers features that transcend the current > SPICE node based syntax. Think of the bigger problem. You need to > simulate the SI and Crosstalk effects of every net on a PCB. You need > MIN MAX timing from every driver to every receiver. You need SI and > Noise margin numbers for every net. And you need them quickly enough so > that you can use the data to turn the design a couple of times. I > believe these issues are difficult to solve using SPICE as it (they) > exists on the market today. > > Of course, I use SPICE every day. I think it is great. I just believe in > using the right tool for the right job and I have more than one job to > do. > > Here is a conceptual example: > you have a 32 wire bus. Each wire couples to it's neighbors. You need to > simulate every wire and the effects on that wire by it's immediate > neighbors. You do not want to waste simulation time by simulating > effects of the wires that are more than a couple of conductors away. > > How would you solve this problem using SPICE? > Can it be solved automatically? > How would spice represent the names of the different nets? (ie. what is > the crosstalk on D13?). > > As for accuracy: > Leave the argument of which approach is more accurate for the moment. > what is the accuracy of your inputs? (PCB stack-up, SPICE model data, > Dielectric constant, trace width). > If you are simulating to a higher accuracy than your data inputs then > you are wasting time and deceiving yourself. I think that a teacher told > me this in 5th grade but I never really believed it until I started > doing SI simulation. Surprise! Every item you mention above has been sucessfully acomplished by many of our customers and other Spice vendors as well. Using IBIS or behavioral models a whole board can be done in reasonable times using Spice. The problem of simulating wires by distance or number of conductors is related to the user interface control and the field solver not a simulator issue at all. This has been done by the way in our system since 1992 and some other SPICE vendors a bit later. Node names are not an issue in modern Spice programs. Your dealing with 2.6 from Berekley circa 1968. PCB stackups have nothing to do with Spice. It's an issue on integrating a good field solver with your simulation engine. Again its been done by several Spice vendors. You are either trying to confuse customers by these issues you raise or you truly don't understand modern day Spice tools. Of course Spice is not perfect and there are plenty of problems. But neither is IBIS. It has its place but at the moment the capabilites are a bit on the lite side...and there are plenty of problems as you yourself have raised. We'll leave accuracy aside for the moment as you mentioned. How about flexibility, capability? Can IBIS handle Analog? How about more sophisticated output stages that dynamically change current sourcing/sinking capability? Where's the information about the power supply currents? Heck some IBIS data doesn't even contain switching information. How about ground bounce? Since there is no mention of the gate or base of the transistors, once noise is introduced via the power/gnd what's the voltage on the base/ or gate of the I/O output transistors? Without that you don't even know which transistor is on or off. I'm for bringing out these issues and solving them using IBIS not covering them up or changing the argument. Spice is just a simulator. It will survive or die on its own merits. How about improving IBIS? Best Regards, -- Fred Balistreri fred@apsimtech.com http://www.apsimtech.com From owner-ibis Tue Mar 31 17:41:00 1998 Received: from webserver.intusoft.com (mail.intusoft.com [205.147.9.166]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id RAA26941 for ; Tue, 31 Mar 1998 17:41:00 -0800 (PST) Message-Id: <199804010141.RAA26941@server.vhdl.org> Received: from charles.intusoft.com by webserver.intusoft.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.0.1459.30) id 2A8C1VWC; Tue, 31 Mar 1998 17:36:17 -0800 From: "Charles Hymowitz" Organization: Intusoft To: ibis@vhdl.org Date: Tue, 31 Mar 1998 17:33:07 -0800 MIME-Version: 1.0 Content-type: text/plain; charset=US-ASCII Content-transfer-encoding: 7BIT Subject: Join reflector Priority: normal I would like to join the IBIS open forum reflector and the the IBIS users group reflector. email address charles@intusoft.com Charles Hymowitz - V.P. Prod. Dev. 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