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Subject: IBIS Summit Meeting Minutes   1 Feb 1999
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DATE: 2/10/99

SUBJECT: 2/1/99 EIA IBIS Summit Meeting Minutes
  
VOTING MEMBERS AND 1999 PARTICIPANTS LIST:
AMP                            (Martin Freedman) 
Applied Simulation Technology  Raj Raghuram*, Norio Matsui*
Cadence Design                 Mike LaBonte
Cisco Systems                  Syed Huq*
Compaq                         Bob Haller*, Steve Coe*, Shafir Rahman*,
                               Maher Elasad*
Cypress                        (Rajesh Manapat)
H.A.S. Electronics             (Haruny Said)
Hewlett Packard (EEsof, etc.)  Paul Gregory*, Henry Wu*
High Design Technology         (Razvan Ene)
HyperLynx                      Matthew Flora*, Kellee Crisafulli*
Incases                        Olaf Rethmeier
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Frank Kern,
                               Martin Chang, Dave Moxley, Kerry Nelson, 
                               Jeff Day, Richard Mellitz*, Peter Liou*
LSI Logic (Symbios Logic)      Scott King*
Mentor Graphics                Bob Ross*, Mohamed Mahmoud*
Mitsubishi                     (Tam Cao)
Motorola                       (Ron Werner)
National Semiconductor         Milt Schwartz*
North East Systems Associates  Edward Sayre*, Michael Baxter*, Kathy Breda*
NEC                            (Hiroshi Matsumoto)
Quantic EMC                    (Mike Ventham)
Texas Instruments              (Jean-Claude Perrin), Shankar Balasubramaniah*,
                               Ramzi Ammar*
Thomson-CSF                    (Jean Lebrun)
Viewlogic                      Chris Rokusek, Guy de Burgh*, (Jon Powell)
VeriBest                       Ian Dodd*
VLSI Technology                D.C. Sessions*
Zuken-Redac                    (John Berrie) 

OTHER PARTICIPANTS IN 1999:
3Dfx Interactive               Ken Wu*
Actel Corporation              Silvia Montoya*
Applied Microelectronics       Brian Sanderson*
Avanti                         Nik Bannov*
Bogatin Enterprise             Eric Bogatin*
EIA                            Patti Rusher
EMC Corporation                Fabrizio Zanella*
IBM                            Greg Edlund*, Michael Cohen, Praven Patel*
Fairchild Semiconductor        Peter LaFlamme*, Craig Klem*
FCI                            John Ellis*
Litton Systems                 Robert Bremer*
Molex Incorporated             Gus Panella*
Rockwell Collins               Susan Tweeton*, Ron Hau*
Samsung                        Jung-Gun Byun*, Cheol-Seung Choi*
Siemens AG                     Bernhard Unger*
Signals & Systems Engineering  Tom Hawkins*
SiQual                         Scott McMorrow*
StorageTek                     Nick Krull*
Sun Microsystems               Victor Chang*
Teradyne                       Mikhail Khusid*
Time Domain Analysis Systems   Dima Smolyansky
Xilinx                         Susan Wu*
(Unaffiliatied, Retired)       Bruce Wenniger*

In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are
as follows:
  
  Date               Bridge Number     Reservation #    Passcode
  February 19, 1999  (916) 356-9200    4-2245000        7252452
  Tuesday, March 9, 1999 IBIS Summit Meeting - No Teleconference

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas 
out 7 days before each Open Forum and meeting minutes out within 7 days 
after.  When you call into the meeting, ask for the IBIS Open Forum hosted 
by Will Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -----------------------------------

IBIS SUMMIT MEETING
The IBIS Summit Meeting was held at the Santa Clara Convention Center in
Santa Clara, California.

About 52 people representing 35 organizations participated in the meeting.

These minutes just briefly note some of the meeting's content and some of its
discussions.  Most of the presentations and related documents are available
on the World Wide Web at:

  http://www.eda.org/pub/ibis/summits/feb99

 
INTRODUCTIONS AND BUSINESS 
- Bob Ross (Mentor Graphics)
Bob Ross opened the IBIS meeting by introducing the officers and then having
having the participants introduce themselves.  Bob thanked Milt Schwartz of
National Semiconductor for handling the local arrangements and copying of
presentations, and thanked National Semiconductor for hosting the buffet
luncheon.

Bob also thanked Jon Powell for arranging the booth and company logo placards
(some of which were picked up at the meeting).  Bob thanked the Accuracy
Committee for providing the demo at the booth.

Finally Bob thanked the DesignCon99 organization for providing the meeting
room, the refreshments, the IBIS meeting room sign, the DesignCon99 booth, and
publicity (a full page advertisement) in the DesignCon99 brochure.  The EIA
IBIS Open Forum is an associate sponsor of DesignCon99.

Later Bob surveyed the participants and found that the semiconductor, EDA, and
user sectors were all well represented.


OPENS FOR NEW ISSUES
Bob Ross called for Ad Hoc presentations and discussion topics.  The following
topics were added and covered during the meeting:

Kellee Crisafulli - Flight Time Calculations in IBIS Simulations (Covered by 
  Stephen Peters)
Kellee Crisafulli - Who Supports the EBD Format?


IBIS USER'S GROUP TELECONFERENCE MEETING
Bob Ross indicated that there was interest by the IBIS User's Group in holding
regular teleconference meetings on weeks that the IBIS Open Forum does not
hold meetings.  Bob indicated that Mentor Graphics is willing to provide a
bridge for such meetings.

[A meeting has been set up for Friday, February 26, 1999.  More details will
be announced later.]


PROGRAM NOTES FOLLOW (Scheduled and Ad Hoc Presentations):

OVERVIEW, REVIEW OF SUMMIT AGENDA
- Bob Ross, Mentor Graphics
Bob Ross started the main meeting by giving a brief overview of what has 
occurred during the last year.  IBIS Version 3.2 was ratified and will be
forwarded for ANSI/EIA-656A ratification.  The ibischk3.2 parser is nearly
completed, but still needs some refinements.  IBIS Version 2.1 is moving
forward, but still pending ratification as IEC 62014-1.  Bob noted that over
350 people are on the IBIS reflectors.  There are 26 member companies and
over 70 organizations and over 170 people participated in IBIS meetings in
1998.  Five face-to-face Summits were held.  Bob also noted that he knew of
over 30 different companies which provide web sites where IBIS models can be
requested or downloaded.  Other companies provide IBIS models directly.

Bob stated that the meeting presentations cover Accuracy and Validation, a 
review of IBIS Version 3.2 features, and then move on to topics for potential
future IBIS extensions.  These include future requirements, a timing
extension, IMIC discussion, and the connector modeling proposal.

Bob concluded by mentioning his 5 C's for model Validation: Correct, 
Compliant, Complete, Checked, and Compared.  Checked covers the syntax check, 
graphical viewing, visual inspection, and loading the model into a simulator.  
Later Greg Edlund suggested using Correlated as discussed in the Accuracy
Specification rather than Compared .


IBIS USER'S GROUP STATUS
Ed Sayre, North East Systems Associates (NESA)
Ed Sayre briefly reviewed the history of the User's group and sited two 
accomplishments of the IBIS User's Group:  The Accuracy Specification and the 
Connector Model Specification.  Ed stated that a 1999 goal was to produce an
IBIS tutorial.  He was willing to head the effort, but asked for volunteers 
to assist in preparing the material.  Ed envisioned downloadable lesson blocks 
on IBIS and on how to use IBIS models.

A number of items were discussed.  Kellee Crisafulli mentioned that there
should be no host preference.  All EDA vendors could be represented in the
material.  Milt Schwartz stated that there should also be some basic material
such as what typical I/O plots should look like.  Susan Tweeton stated that
how to produce ASIC models needed to be covered.  Ed and D.C. Sessions noted
that students in Universities get no exposure to IBIS.  Kellee noted that a 
typical student project costs about $18,000 per student.  


THE IBIS ACCURACY SPECIFICATION: STATUS AND DIRECTION
- Greg Edlund, IBM
Greg Edlund supplied Revision 1.1 of a Draft Accuracy Specification and also 
an IBIS Accuracy Trailer draft.  In the presentation Greg noted that 
Correlation was the cornerstone of the IBIS Accuracy Specification.  Greg 
defined a figure of merit relationship for an overlay metric between 
laboratory measurements and simulation.  The Specification should be a 
reference document for purchasing semiconductor parts.  It is not a pass-fail 
standard for judging accuracy.  It needs to be user driven and flexible.

The current status of the document is to support Version 1.1 IBIS features.
A test board has been developed, and its design along with other documents
are uploaded on the http://www.eda.org/pub/ibis/accuracy site.  Revision 1.2
of the Specification will fold in V/T tables.  The goal is to pursue EIA 
approval of Revision 1.2.

Greg thanked the contributors to the document and outlined the contents.  He
discussed the proposed test structures and then showed examples of the 
envelope and correlation metrics.  Four correlation levels are proposed in
the document, but only three will be proposed in the future version based on
the availability of the component sample.  The proposed levels are 1: Random,
2: Known Typical, and 3: Known Typical, Fast and Slow.

In response to comments that the correlation needs to factor out possible
simulator differences, a judiciously chosen golden waveform will be proposed.
It might be based on a SPICE reference simulation of the SPICE model from
which the IBIS model was derived.  Such a golden waveform might require an
IBIS extension to include the test load structure.  

This led to a number of questions and discussions.  The golden waveform was
further discussed by Ed Sayre, Stephen Peters and Paul Gregory.  It could be a
correlation reference for EDA tools.  Scott King mentioned that in doing ASIC
models, the package information was introduced separately based on the ASIC
package.  Scott McMorrow cited the importance of the package information in
current devices, yet indicated that it is difficult to extract.  D.C. Sessions
cautioned against sneaking in benchmarks.  Stephen stated that the model
documentation could be used as a confidence factor.  Susan Tweeton cautioned
that the model documentation should not be mis-used as an excuse to pitch the
EDA tool.

In response to the criticism that the specification will raise the model cost
and cause too much work, Greg noted that too many simulation failures will
create the crisis that forces semiconductor vendors to document their
correlations.

Greg concluded by asking for more volunteers.  A bi-monthly teleconference
call will be initiated.  The correlation section will be revised.  The group
will propose a BIRD to support Golden Waveforms.  The plan is to forward the
updated document for EIA approval.  Also, more research is needed for test
loads to cover enhancements beyond IBIS Version 1.1 functionality.


PRACTICAL USE OF IBIS MODELS AND ACCURACY STUDIES
- Fabrizio Zanella, EMC Corporation
Fabrizio Zanella presented some results comparing measurements with
simulations using IBIS models and also comparing SPICE model and IBIS model
simulations.  Fabrizio stated the advantages of using IBIS models for board
level simulation: The board file can be imported directly without recreating
the topology, and IBIS models are easy to use, fast and accurate for board
level simulations.  

Fabrizio showed some correlation results.  One important result was to show
equivalent ring back.  Several comments were made regarding the bandwidth of
of the test equipment and probe parasitics and whether the device was really
typical to explain some differences.

Fabrizio felt that for off-board analysis, SPICE simulation was a better
option, especially for high speed clock nets, since connector models are
available and lossy lines can be handled.  He showed some measurements and
SPICE simulation correlation.

In addition, Fabrizio showed some correlation of a TTL test case with IBIS
simulation using SPICE, and direct SPICE model simulation.  There were some 
differences with overshoot and pulse widths.  Some of this was discussed and 
questions were raised.  For example, one SPICE simulation indicated that 
perhaps a clamping diode was not in the SPICE buffer model.  The pulses did
not overlay because the IBIS model may have chosen a different starting
reference for rising and falling edges.  Even so, Fabrizio concluded that
IBIS model simulation did yield accurate results compared to laboratory data
and produced similar results to SPICE simulations.


FLIGHT TIME CALCULATIONS IN IBIS SIMULATIONS (Ad Hoc Presentation)
- Stephen Peters, Intel Corporation
Stephen Peters prepared some hand-drawn foils in response to the new agenda
item.  Stephen defined flight time as a way to account for the change in
a device's propagation delay due to changes in device loading.  He illustrated
this by showing that the maximum clock period was calculated as the summation
of propagation delay, net delay and setup time: Tpd + Tdelay + Tsetup.  The
timing test load (such as 500 ohms and 50 pF) along with Vmeas was used as a 
reference to extract the internal delay information, and its loading effect 
needed to be factored out for actual timing simulations. 


VALIDATION OF IBIS BASED TWO WAVEFORM MODELS
- Bernhard Unger, Siemens AG
Bernhard Unger presented some results of a study on two-waveform based IBIS
models generated using 18 ohms, 50 ohms and 100 ohms as the fixture loads.
The 18 ohm fixture was selected to produce about one-half the Vcc swing.
Bernhard conducted the test using the Fairchild CMOS driver VCX16244 HSPICE
model supplied by Peter LaFlamme as a reference and from which the IBIS
model (also supplied by Peter LaFlamme) was generated.  Four driver conditions
were tested:  

  (1) a 50 ohm, 1 ns transmission line loaded with 5 pF, 
  (2) a lumped 500 ohm parallel 30 pF load,
  (3) a distributed 66 ohm transmission line load,
  (4) and a DIMM module 66 ohm transmission line load.

The simulations were conducted with and without the Vdd/Vss package model
parasitics.

The simulations were done using two-waveform extracted Kpur(t), Kpdr(t),
Kpuf(t) and Kpdf(t) table multipliers according to the SPICE implemented
algorithm cited in previous presentations.

Bernhard showed a number of overlaying comparisons and concluded that the
50 ohm fixture load provided a good compromise.  The 18 ohm fixture load
provided better correlation for the DIMM module test case since the effective  
impedance seen by the buffer was about 25 ohms.  When the Vdd/Vss package
effects were included, the results were not as well correlated. 

Bernhard concluded with the following points:

  (1) Two waveform behavioral model simulations provide excellent agreement
      with transistor based simulations if the IBIS V/T-table loading 
      conditions are comparable with the simulation conditions and the Vdd/Vss 
      parasitics are of minor influence.
  (2) 50 ohm V/T-table loading conditions seem to be a good compromise for 
      most purposes.
  (3) IBIS models with different R_fixture loadings are a real need if timing 
      and noise are very critical issues.
  (4) Vdd/Vss package parasitics strongly influence the simulation results
      with increasing transition times.  As present, this feedback is not
      included in the IBIS model.

Furthermore, Bernhard raised these questions:

  (1) Is there a set of IBIS V/T-table loading R_fixture loading conditions
      (four or five) that cover the range of application loading conditions
      for a given device?
  (2) What method determines the IBIS V/T-table R_fixture loading conditions
      to give the best fit with simulation loading conditions?
  (3) What are the possibilities to implement feedback caused by the Vdd/Vss
      package parasitics into IBIS behavioral models?
      
D.C. Sessions commented that the load selection and results may be impacted      
by internal Miller capacitance in the output stage.


LUNCH BREAK
A delicious buffet luncheon was hosted by National Semiconductor.


IBIS VERSION 3.2 OVERVIEW
- Stephen Peters, Intel
Stephen Peters gave an overview of the IBIS Version 3.2 extensions beyond
IBIS Version 2.1.  Version 3.2 was ratified by the IBIS Open Forum at the
January, 1999 teleconference meeting and will be forwarded for ANSI/EIA-656A
ratification.  The golden parser is uploaded (it still needs some fixes).

As background, Stephen stated that IBIS Version 2.1 supported I/V tables
and V/T tables.  It provided initially for GTL plus technology.  However, it
was limited in describing passive elements, it did not provide adequate
multi-stage I/O buffer models and cartridge packaging technology, and lumped 
L/R/C package models were a practical limitation.

Stephen gave an overview and elaborated (showing related keywords) upon four 
areas of IBIS Version 3.2 enhancements: 

  (1) Support for additional device types
      - passive (2-pin) devices, terminators, bus switches
  (2) Extended model specs and simulation hooks
      - ringback and hysteresis specs, model selectors
  (3) Support for advanced driver/receiver technology
      - multi-staged outputs, bus hold, dynamic clamps
  (4) Enhanced package descriptions
      - transmission line package stubs, .ebd files.

Stephen noted that the future enhancements include uncoupled and coupled
connector models.  The [Add Submodel] concept can be a path for future
expansion since a submodel can be used for anything.  There is consideration
of a possible merger or incorporation of the IMIC specification.

Kellee Crisafulli raised the question at this time regarding which EDA
vendors support the .ebd format.  Several vendors replied that several do
provide support or will very shortly.


IBIS FUTURES
- Stephen Peters, Intel
Stephen Peters continued the discussion by noting what IBIS does well.  It
handles CMOS/TTL/ECL technology and controlled rise time parts such as GTL.
Bus hold is now available.  The EBD and enhanced packages allow more complex
paths - as long as coupling is not required.

However, what is lacking is multiple buffer switching effects taking into
account SSO effects due to pin to pin coupling and power/ground rail bounce.
A lossy transmission line is needed.  Perhaps it is time for the G matrix 
and/or a frequency dependent loss for .ebd and .pkg files.  Non-ideal ground
return paths need to be modeled in the next generation of simulators.

Ed Sayre stated that impedance of the ground plane is a big problem, subject
to possible university work.

Stephen continued that the solution to these are important because of very 
fast processor buses and source synchronous signaling.  The timing budgets 
are tight and the second order effects are now dominant.

[Pin Mapping] is a start, but not complete.  Pin to pin coupling is almost
there, but needs improvement.  A number of participants discussed aspects of
physical databases, SPICE models and SSO effects.

Stephen concluded that the key to SSO modeling is to make the buffer power
and ground nodes available.  IMIC is interesting, but does not use the 
standard I/V and V/T description of the buffer.  Stephen also noted that
the [Add Submodel] keyword has expansion possibilities for a model consisting
of a group of buffers and for embedding package descriptions.


VALIDATION OF EIAJ IMIC MODELS
- Raj Raghuram, Applied Simulation Technology
Raj Raghuram gave the first presentation of a two part presentation on IMIC.
Raj introduced IMIC by noting that it was targeted for signal integrity,
power integrity and EMI analysis.  Such analysis requires the device model, 
the signal trace model and the ground/power plane model.  The inner core
of the IMIC model is a multi-dimensional table format as an extension to
Berkeley Spice.  Such tables can be generated by Spice2IMIC convertors.  IBIS
models can be generated from IMIC models.

Raj described the validation process for both the Motorola 74LCX245 buffer and
the Texas Instruments 74CBT16233 switch.  Raj substituted the derived IMIC
model tables for the process models.  All the results showed nearly overlaying
correlation with the original SPICE models.

Raj also gave some details on making IMIC models.  Several SPICEs support
DC sweeps for printing three-dimensional Voltage/Current and Voltage/
Capacitance table information. RD, RS, and RSH should be set to zero.  If
a more generic SPICE is used, an AC analysis is needed at each point to 
extract the capacitances.

Stephen Peters questioned how fast the IMIC model performs.  Raj estimated
that it was about twice as fast as SPICE, but such an estimate may be impacted
by the table resolution.

Scott McMorrow suggested a simplified and reduced IMIC model.  Arpad Muranyi
raised the concern that even though the process information is protected by
using the table transistor model, the structural information, which also can be
proprietary, is revealed.

Report ON EIAJ IMIC STANDARD
- Norio Matsui, Applied Simulation Technology
Norio Matsui continued the IMIC presentation.  He added that the Hitachi
ALVCH16244 was also used for validation studies.  Norio elaborated that
work was being done for advanced package models for up to 2000 pin BGAs, QFP
and CSP configurations.  Package and Module descriptions need the free network
descriptions for coupling effects, forks and loops, and frequency dependency.

Norio noted that the I/O Model Project Group is currently working on the EMI
Model Standard.  Return current paths and are considered along with ground
plane effects.  Local ground planes reduce EMI.  Some of the details in the
presentation were not covered due to time limitations.

However, Norio noted that one EDA vendor supports the IMIC format, and 
another is expected to follow.  A new EIAJ subcommittee will be formed to
consider EMI/EMC modeling for non-ICs and system level applications.  Norio
positioned the IBIS and IMIC committee activities and also considered the
relative strengths and weaknesses of each format.

Norio concluded that he would like to see a merger of activities through
a subset approach: IMIC into IBIS or IBIS into IMIC.  The EIAJ I/O Modeling
Project Group has formed a subgroup to investigate IBIS and IMIC merger.  The
formal standardization process of IMIC is currently being postponed.


INPUT THRESHOLD MODELING
- D.C. Sessions (VLSI Technology)
Note, this description is adapted from the description given for a similar 
presentation given at the December 7, 1998 IBIS Summit Meeting.

D.C. Sessions noted that as a result of tighter timing margins, the old input
threshold limits such as Vinh = 2.0 V and Vinl = 0.8 V are becoming too
conservative to be practical.  Input signals can easily have a ledge in the
region between Vinh and Vinl.  The actual thresholds are much tighter.  Also
JEDEC JC-16.2 is standardizing on closer threshold limits for newer
technologies.

D.C. noted that for many technologies, the Input thresholds were related to
the power supply voltage.  So D.C. suggested a linear adjustment factor that
is related to the rail to determine more accurate thresholds.  

D.C. also noted that the timing delay was a function of how much the input
signal went over the first threshold.  D.C. showed some time shifted responses
as a function of threshold overvoltage from 25 mV to about 1.6 V.  The delays
shrank from about 3 ns to 300 ps.  For this particular simulation, D.C.
fit the data to a 2/3rds power relationship:

  t = to + K/(Vin - Vth)**(2/3)

D.C. suggested a timing table could be proposed for IBIS to capture this
input resolution.  D.C. provided formats at the meeting for such a timing
table using the keywords [Rising Delay] and [Falling Delay].  The adjustments
to the delay would be made relative to the specification thresholds.  The
0 V value has 0 seconds of adjustments.  These tables contain typ, min, and
max columns.

To summarize, D.C. presented the following draft proposal:

1) Threshold Voltage
"Add a first-order term to the existing Vin specs.  DC trip point is defined
as the specified value at the specified supply voltage plus (the new value)
times the difference in supply voltage.  Alternately, add a table.  In effect,
turn the current and scaler values into lists."

2) Timing
"In keeping with IBIS's preferred use of observable properties, add an
[input_delay] table giving relative delay for input voltages relative to the
specified thresholds.  Thus, if Vinl is 800 mV under some condition, the table
entry at 200 mV is the added delay for signals at 1000 mV.  Simulator  
providers would be free to innovate with respect to dynamic algorithms for
complex input waveforms.

Some discussion occurred.  Arpad Muranyi stated that an equation might be 
considered instead of tables.  Scott McMorrow thought more tables might be
needed for multiple edge rates.


IBIS CONNECTOR MODEL STATUS
- Kellee Crisafulli, HyperLynx
Kellee Crisafulli along with Gus Panella gave a presentation.  Kellee supplied
CDs containing the presentation, the draft documents, and many examples of
implementation.  The presentation and other documents are planned to be
uploaded.

Kellee introduced the topic by naming the simulator vendors, connector vendors
and end users who had participated in the development of the proposed
specification.  He presented the motivation related to what is missing in
IBIS.  This includes not having a method for modeling cascaded or tee methods
for coupled matrices.  Also, the current method does not allow for a "swath"
simplification method.

Currently the concepts are determined, and the specification, examples, and
slide presentation are created.  The CD contains this information and more.

Kellee noted that the familiar keywords of the IC and .pkg specification are
used for header information and defining types of matrices.  The Connector
Specification is intended to be a stand-alone specification.  It will include
pictures (JPEG), Stub matrices, Cascaded matrices, a swath matrix, and a
Diagonal_matrix type.

Changes include pin naming methods for connectors, the .ibiscnn file name
extension naming convention, and relaxed line width restrictions.

In response to potential questions, Kellee stated that the stand-alone
document will be smaller and contain only the keywords needed for the
connector models.  The new Diagonal_matrix reduces the number of lines for
the single line, uncoupled models versus a Banded_matrix of Bandwidth 0.

Kellee and Gus showed some samples of the Connector Matrix syntax.  Matrix
sections are named.  The Swath was defined as a small matrix used to define
a much larger matrix.   The syntax allows for defining how to terminate
some end columns when the swath is used.  For the left-hand and right-hand
columns, the Swath matrix overlaps by a designated number of columns, and
these overlap columns are terminated in a designated impedance.  Other
examples of matrix construction were presented for Stub matrices, and for
the construction of the complete connector model.

The short term goal is to transfer the Specification to the IBIS archive and
solicit feedback from the IBIS Open Forum.  The goal is to adopt the .ibiscnn
as a revision to IBIS.

The longer term goal is to create a parser for syntax checking.  Also the
accuracy of the .ibiscnn model needs to be checked by comparing it with 
SPICE simulations.  Features may be added to the swath method.  Lossy models
need to be added along with support for .ebd capabilities.

Unbalanced and balanced style SPICE connector models were shown.  The 
comparison should be against the balanced type model for reflections, delay,
crosstalk and risetime degradation.

Kellee concluded by thanking Gus Panella for his time and the other
participants, EMC for the phone bridge, and HyperLynx for the specification
enhancements and CD-ROMs.

Many points were discussed during and after the presentation.  Arpad Muranyi
suggested using a Conductance Matrix for losses.  The method of Swath overlap
was clarified.  The reason is to approximate the edge effects.  

How to handle the reference ground was discussed.  Some preferred no reference
ground.  Stephen Peters asked about pad capacitances and frequency limits.
After some discussion Stephen concluded that it is reasonable for EDA tools
to handle the pad capacitances from the physical design.  The pin boundary
would stop at the board surface.

One new aspect is that unmated models would be supported.  Two unmated models
do not produce a mated model.

Raj Raghuram questioned whether the matrices are Maxwell.  He pointed out that
the diagonal matrix is not Maxwell.  The response was that the matrices for
coupled sections are Maxwell.  Uncoupled matrices are referenced implicitly to
the global ground.
 
The main action item is for the IBIS committee to review the proposal and
provide feedback.



CONCLUSION
Bob Ross concluded the meeting by noting that the next teleconference meeting
was scheduled for Friday, February 19, 1999.  The Tekronix IPA 510 software
proposal would be discussed.  Also, the following meeting would be an IBIS
Summit Meeting in Munich, Germany on March 9, 1999 along with the DATE99
conference.

Bob again thanked the participants and presenters for contributions.


NEXT MEETING:
The next teleconference meeting will be on Friday, February 19, 1999 from 
8:00 AM to 10:00 AM.  The Tektronix IPA 510 proposal will be discussed and
voted upon.
==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentorg.com
            Modeling Engineer, Interconnectix BU of Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            sjpeters@ichips.intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-56
            2111 NE 25th Ave. 
            Hillsboro, Oregon 97124-5961

SECRETARY:  Matthew Flora (425) 869-2320, Fax: (425) 881-1008
            mbflora@hyperlynx.com
            Senior Engineer, HyperLynx, Inc.
            17641 NE 67th Court
            Redmond, WA 98052

LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
            jonp@qdt.com
            Senior Scientist, Viewlogic (formerly Quad Design)
            1385 Del Norte Rd., Camarillo, CA 93010
 
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is 
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eia.org

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.
==============================================================================

From owner-ibis  Thu Feb 11 14:58:43 1999
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To: ibis-users@eda.org, ibis@eda.org, si-list@silab.eng.sun.com
Subject: EUROPEAN IBIS SUMMIT MEETING ANNOUNCEMENT

To All:

This is a second announcement of the second European IBIS Summit Meeting.
Last year we had a very successful European IBIS Summit Meeting.  This year
we are holding again a meeting along with DATE99 on Tuesday, March 9, 1999.
The purpose is to promote communication among users and developers of IBIS
models in Europe.

The meeting is open to everyone and will start with a Lunch at Noon to
allow some attendees to arrive in Munich that morning.

Below is some information on the IBIS Summit and some related events.  You
are invited to register and also to submit presentations.

Best Regards
Bob Ross
Mentor Graphics


          E U R O P E A N   I B I S   S U M M I T   M E E T I N G
                   S E C O N D   A N N O U N C E M E N T 

Time/Date:     12 PM - 6 PM, Tuesday, March 9, 1999

Location:      ASTRON HOTEL/Neue Messe
               Eggenfeldener Strasse 100
               Munich, Germany 

               This is a hotel near the DATE99 Conference

Content:       Presentations and Discussions

Purpose:       Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:      Mentor Graphics, INCASES


DATE99 Show:   DATE99 - March 9 - 12, 1999.  The IBIS meeting is scheduled
               the day before the DATE99 trade show begins.

Location:      International Congress Center, Munich, Germany

               See www.date-conference.com for more information.

PCB Symposium: An all day symposium is scheduled Thursday, March 11, 1999,
               on PCB design issues, on site at DATE99.


BACKGROUND

Last year we had a very successful European IBIS Summit Meeting.  This year
we plan to expand the scope to include:

  Submitted Presentations on IBIS Topics (See below)
  Less formal Ad Hoc Presentations and Discussions
  IBIS Questions and Answers
  
Below is an invitation to register and also to submit presentations.


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and digital
circuit design are invited to participate in the European IBIS Summit meeting.
If you plan to participate, please register with the information below
(deadline, February 26, 1999):

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Karine Loudet (karine_loudet@mentor.com)  +33 1 40 94 74 54


TENTATIVE AGENDA TOPICS TO DATE (More are Welcome):

  12:00:  LUNCH (Provided to all participants)

  13:00 - 18:00 MEETING

    Current IBIS Activities and Issues
      Bob Ross, Mentor Graphics
    IBIS Version 3.2 Update
      Stephen Peters, Intel
    IBIS Future Requirements
      Stephen Peters, Intel
    Validation of IBIS Based Two Waveform Behavioral Models
      Bernhard Unger, Siemens AG
    (Possible Presentation on IBIS Library Development Topic)
      Siemens
    General Questions and Discussions
      - IBIS Interpretation
      - Future Requirements
      - Any other topic of interest
    Ad Hoc Presentations


CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.  Some suggested subjects of interest are:

  IBIS Model Development Experiences
  Generating IBIS Models
  Validating IBIS Models
  Future IBIS Requirements
  EMC/EMI IBIS Issues

Format of Presentation:  Overhead Projections
Time:                    15-30 Minutes
Electronic Archival:     We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees.  Formats used in
                         the past have been text, Power Point, Word, 
                         Postscript, and Acrobat.  Electronic presentations
                         should be made available by February 26, 1999.
                         Otherwise the presentor will be expected to provide
                         50 copies for distribution.

If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Bob Ross (bob_ross@mentor.com)


FOR FURTHER INFORMATION:

Bob Ross,
Chair, EIA/IBIS Open Forum
Mentor Graphics
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070
USA

(503) 685-0732
bob_ross@mentor.com








From owner-ibis  Fri Feb 12 13:40:16 1999
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From: "D. C. Sessions" <dc.sessions@vlsi.com>
Organization: VLSI Technology Inc.
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To: IBIS Mailing list <ibis@eda.org>
Subject: JEDEC Gauntlet
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I've been hinting for a while that JEDEC had a standard in
the queue that couldn't be modelled by IBIS 3.2 -- now I
can point y'all to it.

http://www.jedec.org/download/freeStd/jedec/jesd67.pdf

The floor is open for suggestions.

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Fri Feb 12 14:50:28 1999
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To: ibis@eda.org
Subject: IBIS AGENDA 2/19/99

                      IBIS Open Forum Meeting Agenda 
                               for 2/19/99

                 Bridge Number    Reservation #   Passcode
                 (916) 356-9200   4-2245000       7252452

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Ross

     - Intros of New IBIS Participants, Meeting Quorum       Ross
     - Membership Update and Treasurers Report               Rusher
     - Review of Previous Meeting's Minutes (and ARs)        Ross
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Powell, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-1 (IBIS Version 2.1)                        Rusher
     - pr EIAJ ED-5302 Standard for I/O Interface Model      
          for Integrated Circuits (IMIC)                     Raghuram/Ross
     - 93/67/NP IBIS and EMC Simulation                      Perrin
     - JEDEC JC-16.2 Modeling and Testing                    Sessions
       - JEDEC/IBIS Version 3.2 Incompatibility
     - IEEE P1537 Data Format Project                        Peters

     IBIS (East) Users Group Meetings                 Haller/Zanella/Edlund

     DesignCon99 February 1, 1999 IBIS Summit Review         All
     - IBIS Meeting
     - IBIS Booth
     - DesignCon99 Presentations and Panels
     - Other

     DATE99 March 9, 1998 IBIS Summit Meeting                Ross

     IBIS Version 3.2                                        Ross/Rusher
     - EIA Standard Preparations

     IBISCHK3 Version 3.2.2/ 3.2.3                      Ross/Flora/Rokusek
     - Split off ibis_chk for Version 1.1?
     - Source, Executables

     Tektronix IPA510 Software Proposal Discussion           Huq
     - Vote

     Cookbook Status                                         Peters

     IBIS Model Review Committee                             Flora

     New Administrative Issues                               All

9:40 Technical Discussion

     Connector Proposal Review                               Flora/Crissafulli

     Accuracy Specification Review                           Edlund/Haller

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off
 






From owner-ibis  Fri Feb 12 18:55:07 1999
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Date: Fri, 12 Feb 1999 18:50:35 -0800
To: "D. C. Sessions" <dc.sessions@vlsi.com>, IBIS Mailing list <ibis@eda.org>
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Re: JEDEC Gauntlet
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Hi all,

At 02:34 PM 2/12/99 -0700, D. C. Sessions wrote:
>I've been hinting for a while that JEDEC had a standard in
>the queue that couldn't be modelled by IBIS 3.2 -- now I
>can point y'all to it.
>
>http://www.jedec.org/download/freeStd/jedec/jesd67.pdf
>
>The floor is open for suggestions.

It looks to me like "model selector" will handle everything
except "Method 1" analog impedance control through an external 
resistor.  Where Zout = N times Rexternal.  We could certainly
add a keyword to handle this.

Best wishes...
Kellee

---------------------------------------------------------
Have a great day....
Kellee Crisafulli at HyperLynx
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------

From owner-ibis  Tue Feb 16 07:34:09 1999
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Subject: IBIS switch models
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At the IBIS Summit held at DesignCon 2 weeks ago, one of the presentations 
discussed IBIS version 3.2 enhancements.  Asa part of IBIS v3.2, 
Quickswitches, FET switches, CBT switches can now be modeled in IBIS.  I 
need to simulate boards which have switches, and in speaking to a 
semiconductor vendor, they will have IBIS switch models available as soon 
as a simulator can support the models.
Does anyone know of a simulator which can support IBIS v3.2 models or when 
this feature will be available?

Thank you and regards,
Fabrizio Zanella
EMC, Hardware Engineering
fzanella@emc.com
508-435-2075, x4645

From owner-ibis  Tue Feb 16 12:51:39 1999
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To: Kellee Crisafulli <kellee@hyperlynx.com>
cc: "D. C. Sessions" <dc.sessions@vlsi.com>, IBIS Mailing list <ibis@eda.org>
Subject: Re: JEDEC Gauntlet 
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             <199902130249.SAA20748@mail.hyperlynx.com> 
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Kellie Wrote:

> Hi all,
> 
> At 02:34 PM 2/12/99 -0700, D. C. Sessions wrote:
> >I've been hinting for a while that JEDEC had a standard in
> >the queue that couldn't be modelled by IBIS 3.2 -- now I
> >can point y'all to it.
> >
> >http://www.jedec.org/download/freeStd/jedec/jesd67.pdf
> >
> >The floor is open for suggestions.
> 
> It looks to me like "model selector" will handle everything
> except "Method 1" analog impedance control through an external 
> resistor.  Where Zout = N times Rexternal.  We could certainly
> add a keyword to handle this.
> 
> Best wishes...
> Kellee
> 

The Method 1 output impedance control could also be handled by 
[Model Selector] as well.  Just create several different output models, 
each assuming some selected output impedence.  I don't think that you
would have to make very many models to cover a useful range.

Anyways, my $.02 worth.

   regards,
   Stephen


From owner-ibis  Tue Feb 16 17:30:28 1999
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From: Todd Andersen <Todd.Andersen@abq.sc.philips.com>
Organization: Philips Semiconductors -- PIC, Albuq NM
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I will be going to Europe for a while and wish to unsubscribe the
technical notes.

    Please notify me of meetings and send minutes if these can be done.

    I hope to make the Munich IBIS meeting in March.

    Todd

Todd.Andersen@nym.sc.philips.com

--
Todd Andersen           Phone:505-822-7666
IC Modeling Engineer      FAX: 505-822-7802
Standard Logic, ABQ         Todd.Andersen@abq.sc.philips.com



From owner-ibis  Thu Feb 18 08:29:31 1999
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Subject: IBIS Accuracy Specification First Draft
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(OK, so nobody is interviewing us - but we thought some of you might be
interested in this "press release.")

First Draft of IBIS Accuracy Specification Unveiled at DesignCon99

February 1, 1999 - A group of engineers from system and semiconductor
companies has been working for the past year on a specification that would
allow an IBIS datasheet (model) provider to document the results of lab
correlation.  This new effort is called the "IBIS Accuracy Specification,"
and we presented our first draft at the DesignCon99 IBIS Summit.  The
documents are available on the IBIS web site at
www.eigroup.org/ibis/ibis.htm under the heading "Accuracy Info."  The
intention of this specification is to offer the IBIS user a quantitative
method for assessing the accuracy of an IBIS datasheet.  The user can then
make a data-driven decision about whether or not an IBIS datasheet and the
component it represents are appropriate for the design application.  The
IBIS Accuracy Specification is a potentially powerful tool for specifying
the purchase of semiconductor components.

The basic idea is this:  the IBIS modeling engineer measures a set of test
loads called out in the spec and compares the results against SPICE "golden
waveforms" that are embedded in the IBIS datasheet (model).  The modeling
engineer then applies a metric that quantifies the comparison and places
the metric results in the IBIS datasheet as comments.  The user can then
run a comparison against the same "golden waveforms" using the behavioral
simulator of his or her own choosing.  So we have established a link
between behavioral simulation results and the actual hardware the IBIS
datasheet is supposed to represent.

We invite the IBIS and signal integrity communities to review the IBIS
Accuracy Specification and offer their comments and suggestions.  Please
send them to ibis-users@eda.org.  This document is a work-in-progress; we
are already working on revision 1.2.  It is our intention to take the
specification before the Electronic Industries Alliance for approval as a
formal industry standard in 1999.

Furthermore, we would like to invite any of you who has an interest in IBIS
accuracy to join us in an open teleconference call beginning February 26,
1999.  This call will be held the every third week one week after the
regular IBIS Open Forum call.  A formal announcement will be posted to the
IBIS reflector after the February 19 IBIS Open Forum conference call.  (You
may join the reflector by sending email to ibis-request@eda.org.)  The
accuracy working group will address four main topics:

1) amending IBIS to include new golden waveforms
2) revising the IBIS Accuracy Specification to 1.2
3) pursuing EIA approval
4) expanding the scope to cover contemporary I/O buffer designs.

As IBIS users, you may also be interested in a test board that we designed
as a companion to the specification.  It demonstrates test structures that
implement the measurements called out by the specification.  You can
down-load the schematics, Gerbers, and Cadence design source files.  The
board design is public domain, and we encourage you to build your own copy
or even change the design.  Please read the errata first.


From owner-ibis  Mon Feb 22 18:52:24 1999
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Date: Mon, 22 Feb 99 18:46:38 PST
Message-Id: <9902230246.AA01898@bob>
To: ibis-users@eda.org, ibis@eda.org, si-list@silab.eng.sun.com
Subject: EUROPEAN IBIS SUMMIT MEETING REMINDER

To All:

This is a third announcement of the second European IBIS Summit Meeting.
Last year we had a very successful European IBIS Summit Meeting.  This year
we are holding again a meeting along with DATE99 on Tuesday, March 9, 1999.
The purpose is to promote communication among users and developers of IBIS
models in Europe.

The meeting is open to everyone and will start with a Lunch at Noon to
allow some attendees to arrive in Munich that morning.

Below is some information on the IBIS Summit and some related events.  You
are invited to register.  The agenda is becoming formed below:

Best Regards
Bob Ross
Mentor Graphics


          E U R O P E A N   I B I S   S U M M I T   M E E T I N G
                    T H I R D  A N N O U N C E M E N T 

Time/Date:     12 PM - 6 PM, Tuesday, March 9, 1999

Location:      ASTRON HOTEL/Neue Messe
               Eggenfeldener Strasse 100
               Munich, Germany 

               This is a hotel near the DATE99 Conference

Content:       Presentations and Discussions

Purpose:       Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:      Mentor Graphics, INCASES, High Design Technology (HDT)


DATE99 Show:   DATE99 - March 9 - 12, 1999.  The IBIS meeting is scheduled
               the day before the DATE99 trade show begins.

Location:      International Congress Center, Munich, Germany

               See www.date-conference.com for more information.

PCB Symposium: An all day symposium is scheduled Thursday, March 11, 1999,
               on PCB design issues, on site at DATE99.


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and digital
circuit design are invited to participate in the European IBIS Summit meeting.
If you plan to participate, please register with the information below
(deadline, February 26, 1999):

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Karine Loudet (karine_loudet@mentor.com)  +33 1 40 94 74 54


TENTATIVE SCHEDULE TO DATE:

  12:00:  LUNCH (Provided to all participants)

  13:00 - 18:00 MEETING

    Current IBIS Activities and Issues
      Bob Ross, Mentor Graphics

    Detecting Typical Bugs in IBIS Models
      Werner Rissiek, INCASES Engineering

    Validation of IBIS Based Two Waveform Behavioral Models
      Bernhard Unger, Siemens AG

    IBIS Version 3.2 Update
      Stephen Peters, Intel

    BREAK

    IBIS Management and CHECK at Siemens ICN
      Gerald Bannert, Siemens

    DOGEN, An Internal Model Library Management Tool
      Hans Pichlmaier, Siemens

    General Questions and Discussions
      - IBIS Interpretation

    IBIS Future Requirements
      Stephen Peters, Intel

    Unconfirmed Presentation on Future Requirements

    General Questions and Discussions
      - Future Requirements
      - Any other topic of interest

    Ad Hoc Presentations


CALL FOR PRESENTATIONS

Presenters:  If you want copies made of your presentation, please send 
presentation to these addresses:

  karine_loudet@mentor.com
  bob_ross@mentor.com

Deadline is Friday, February 26, 1999, but we would prefer them as early
as possible to get a head start.  Otherwise plan to bring 50 copies for
the meeting.


FOR FURTHER INFORMATION:

Bob Ross,
Chair, EIA/IBIS Open Forum
Mentor Graphics
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070
USA

(503) 685-0732
bob_ross@mentor.com










From owner-ibis  Tue Feb 23 19:17:31 1999
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Date: Tue, 23 Feb 1999 19:12:11 -0100
To: ibis@eda.org
From: Matthew Flora <mbflora@hyperlynx.com>
Subject: IBIS Open Forum Minutes   19 Feb 1999
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

DATE: 2/23/99

SUBJECT: 2/19/99 EIA IBIS Open Forum Minutes
   
VOTING MEMBERS AND 1999 PARTICIPANTS LIST:
AMP                            (Martin Freedman) 
Applied Simulation Technology  Raj Raghuram*, Norio Matsui
Cadence Design                 Mike LaBonte
Cisco Systems                  Syed Huq*
Compaq                         Bob Haller, Steve Coe, Shafir Rahman,
                               Maher Elasad
Cypress                        (Rajesh Manapat)
H.A.S. Electronics             (Haruny Said)
Hewlett Packard (EEsof, etc.)  Paul Gregory, Henry Wu
High Design Technology         (Razvan Ene)
HyperLynx                      Matthew Flora*, Kellee Crisafulli
Incases                        Olaf Rethmeier
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Frank Kern,
                               Martin Chang, Dave Moxley, Kerry Nelson, 
                               Jeff Day, Richard Mellitz, Peter Liou
LSI Logic (Symbios Logic)      Scott King
Mentor Graphics                Bob Ross*, Mohamed Mahmoud
Mitsubishi                     (Tam Cao)
Motorola                       (Ron Werner)
National Semiconductor         Milt Schwartz*
North East Systems Associates  Edward Sayre, Michael Baxter, Kathy Breda
NEC                            (Hiroshi Matsumoto)
Philips Semiconductor          (Todd Andersen)
Quantic EMC                    (Mike Ventham)
Texas Instruments              Jean-Claude Perrin*, Shankar Balasubramaniah,
                               Ramzi Ammar
Thomson-CSF                    (Jean Lebrun)
Viewlogic                      Chris Rokusek, Guy de Burgh, (Jon Powell)
VeriBest                       Ian Dodd
VLSI Technology                D.C. Sessions*
Zuken-Redac                    (John Berrie) 

OTHER PARTICIPANTS IN 1999:
3Dfx Interactive               Ken Wu
Actel Corporation              Silvia Montoya
Applied Microelectronics       Brian Sanderson
Avanti                         Nik Bannov
Bogatin Enterprise             Eric Bogatin
EIA                            Patti Rusher
EMC Corporation                Fabrizio Zanella
IBM                            Greg Edlund*, Michael Cohen*, Praven Patel
Fairchild Semiconductor        Peter LaFlamme, Craig Klem
FCI                            John Ellis
Litton Systems                 Robert Bremer
Molex Incorporated             Gus Panella
Rockwell Collins               Susan Tweeton, Ron Hau
Samsung                        Jung-Gun Byun, Cheol-Seung Choi
Siemens AG                     Bernhard Unger
Signals & Systems Engineering  Tom Hawkins
SiQual                         Scott McMorrow
StorageTek                     Nick Krull
Sun Microsystems               Victor Chang
Tektronix                      Tom Brinkoetter*
Teradyne                       Mikhail Khusid
Time Domain Analysis Systems   Dima Smolyansky*
Xilinx                         Susan Wu
(Unaffiliatied, Retired)       Bruce Wenniger

In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:
  
  Date               Bridge Number     Reservation #    Passcode
  Tuesday, March 9, 1999 IBIS Summit Meeting - No Teleconference
  March 26, 1999     Not Yet Available

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
7 days before each Open Forum and meeting minutes out within 7 days after.  
When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------

INTRODUCTIONS AND MEETING QUORUM
Tom Brinkoetter of Tektronix, who had called in last year, joined us for the
IPA 510 discussion.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Bob Ross reported that the annual membership invoices have been sent out.

Also, Philips Semiconductor was an IBIS Member in 1998.  The December 18, 1998 
minutes have been changed to show this membership.  Last year there were 27
IBIS members.  About 33 invoices were sent out this year.  Membership is 
officially established when payment (or purchase order) is received by EIA.

Bob expects several new memberships, including some from participating IBIS 
East companies.


REVIEW OF MINUTES AND AR'S
No corrections.  The ARs will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
Bob Ross reported that the http://pub/ibis/summits/ directories now have all
the uploaded Summit material (from face-to-face meetings) indexed by month/
year of the summit.  Some Summits had no uploadable material.  The minutes for
these summits may be uploaded in the future.


PRESS AND WEB PAGE UPDATES
Syed Huq reported some minor changes to the EIA IBIS web page have been sent
to EIA.  The list of upcoming events has been updated.

Bob Ross reported the EE Times Article "EIAJ Proposes Alternative to IBIS 
Modeling Scheme" in the January 25, 1999 issue of EE Times.  This article 
discusses the IBIS committee relationship with the EIAJ I/O modeling subgroup.
It contains quotes from several IBIS committee participants.

Bob reported that the DesignCon99 brochure listed IBIS as an Associate Sponsor
and had a full page add for the IBIS Open Forum and Booth.

Bob also reported that the presentation "A Tour of the IBIS Accuracy
Specification" by Robert Haller, Peter LaFlamme was presented on Tuesday,
February 2, 1999 at DesignCon99.  This presentation is stored in the IBIS FTP
site accuracy subdirectory:

  http://www.eda.org/pub/ibis/accuracy/desconibis.zip

and is accessible using the Accuracy Info link on the EIA IBIS home page.

Bob reported that a presentation last year at DesignCon98 by Jon Powell and
Chuck Berman titled "Creating Signal Integrity Models from Physical
Measurement" appeared on pages 22-27 of the Hewlett-Packard publication
Insite, Volume 4, Issue 1, 1999.

Bob reported that Arpad Muranyi is teaching a session on "Introduction to IBIS
Models" at the Circuit Simulation and Signal Integrity in Microelectronic
Circuits and Systems tutorial short course.  Also Tim Schreyer will teach
"High Speed Interconnect Design".

Finally, EDN Magazine has an EDN on Signal Integrity section which contains
several links with IBIS content including "IBIS Links and Information":

  http://www.ednmag.com/special/si.cfm


NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross reported that Philips Semiconductor has IBIS model links:

  http://www.philipslogic.com/products/pc/
  http://www.philipslogic.com/support/ibis/

Bob also reported that Hyundai Electronics has IBIS models (registration is
required):

  http://kcs.hei.co.kr/models/model/model.html

The International Microelectronics FTP link now contains directly downloadable
IBIS models (without the need for a password):

  ftp://ftp13.ba.best.com/pub/imiweb8/ibis/


OPENS FOR NEW ISSUES
Bob Ross - Payment of Atul for parser development $4168
Bob Ross - Bug34 - No Error Reported for Missing V/I Table in Output Buffers
           (not covered)


INTERNATIONAL/EXTERNAL PROGRESS
- IEC 62014-1 (IBIS Version 2.1) - Bob Ross repeated a previous report that
  IEC has circulated IBIS Version 2.1 on November 6, 1998.  The Committee
  Draft for Vote (CDV) closes ballot on April 15, 1999.

- pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits
  (IMIC) - Bob Ross reported that Dr. Hideki Fukuda held an EIAJ I/O Project
  Group meeting on January 12, 1999.  The group discussed a relationship
  with IBIS, and almost all of the members wanted to cooperate with IBIS and
  reach a merger of IBIS and IMIC.  They decided to make a group to discuss
  the issues of the relationship with IBIS.  Another topic of the meeting was
  EMI.  They will tackle the problem of applying IMIC to EMI analysis.  Some
  of this information was also discussed at the IBIS Summit Meeting on
  February 1, 1999.

- IEC 93/67/NP IBIS and EMC Simulation - Jean-Claude Perrin reported that he
  plans an Experts meeting in March in preparation for a Working Group
  meeting later.  A presentation is planned, but some software checking will
  be needed.  Jean-Claude may not be able to attend the DATE99 IBIS Summit,
  but he expects someone from his group to attend.  Jean-Claude will contact
  Bob Ross off-line concerning details of the presentation.

- JC-16.2 Subcommittee: Modeling and Test - Bob Ross reported that D.C.
  Sessions reported on the reflector that a JEDEC standard now has
  requirements that IBIS Version 3.2 may not be able to handle.  Stephen
  Peters and Kellee Crisafulli responded that [Model Selector] could be used.
  However, D.C. stated that this could produce too many models.  Arpad
  Muranyi stated that some extension to IBIS such as equation based models
  might be used for such situations.  Bob stated that this discussion needs to
  be deferred to a later time.  This functionality could be a candidate for
  IBIS Version 4.x extensions - consistent with other input extensions.

  D.C. stated, as previously reported, that he is Chair of a JEDEC sub-group
  to standardize on a generic IBIS Model for double data rate SDRAM electrical
  characterization.  D.C. is looking for IBIS members to help out.  Contact
  D.C. at dc.sessions@vlsi.com if you are interested.

- IEEE P1537 Electronic Data Format Project (Previously listed as the Standard
  Component Data Sheet) - Stephen Peters had no further report.
  

IBIS (EAST) USERS GROUP MEETINGS
Greg Edlund reported that the IBIS User Group will be holding teleconference
meetings.  Each meeting is planned to be on Friday of the week following, and
at the same time of day as, the IBIS Open Forum meeting.  The first one is
scheduled for Friday, February 26, 1999 from 8 AM to 10 AM PST.

Greg stated that about one hour will be devoted to Accuracy Committee issues,
and Ed Sayre will be using the other hour for a general IBIS East meeting.
The agenda and meeting contact details will be sent out after the IBIS
Open Forum Meeting on the ibis-users@eda.org reflector.  Greg expects to send
out meeting minutes on that reflector.

Bob Ross reported that Mentor Graphics is hosting the meeting and providing
the dial-in number and password information for these minutes:

                                  Bridge               Access Code
  Friday Feb. 26, 8 AM to 10 AM:  1-608-250-9675       734362

Bob noted that the DesignCon99 presentation has been uploaded to the FTP
site.  It is accessible directly and through the Accuracy link noted above.

Bob also noted that the Connector activity will be covered as a separate
group and working directly with the IBIS Open Forum.  Some documents have been
uploaded at a new "connector" subdirectory on the IBIS FTP site:

  http://www.eda.org/pub/ibis/connector/


DESIGNCON99 FEBRUARY 1, 1999 SUMMIT REVIEW
Bob Ross called for feedback on the February 1, 1999 IBIS Summit meeting.
Matthew Flora stated it was a good meeting and that much of the material
should provide new BIRDs for enhancing IBIS.  Bob noted that typically some
IBIS Summit material in the past has seeded actual specification advances.
Bob thanked National Semiconductor for hosting the lunch, and Milt Schwartz
for helping in the meeting logistics and in copying the presentations.

Bob commented that the Booth went well and again thanked Viewlogic for 
providing the backdrop and Jon Powell for handling the logos and other 
details.  Jon is currently in possession and is storing the logo placards for
later use.

Bob also commented that he expects to see the DesignCon99 problems concerning
the proceedings and lack of room for many High Performance System Design
sessions to be resolved next year.

Bob expects that the IBIS Open Forum will be an Associate Sponsor again next
year.


DATE99 MARCH 9, 1999 SUMMIT MEETING
Bob Ross noted that information has been sent out on the IBIS Summit meeting
associated with the DATE99 conference in Munich, Germany.  The IBIS meeting is
scheduled for Tuesday, March 9, 1999 at the Hotel below:
   
  ASTRON HOTEL/Neue Messe
  Eggenfeldener Strasse 100
  Munich, Germany 

Lunch, provided to all participants, will start at 12 Noon, and the meeting is
expected to start at 1:00 PM.  The date was chosen to avoid conflicting with
the trade show portion of DATE99 held Wednesday through Friday.  The Noon
starting time will allow some people to fly in that morning.  Mentor Graphics,
INCASES, High Design Technology are co-sponsoring the IBIS Summit Meeting.

INCASES has sent out a press release in Europe concerning the meeting.  Bob
listed the tentative agenda:

  12:00:  LUNCH (Provided to all participants)

  13:00 - 18:00 MEETING

    Current IBIS Activities and Issues
      Bob Ross, Mentor Graphics

    Detecting Typical Bugs in IBIS Models
      Werner Rissiek, INCASES Engineering

    Validation of IBIS Based Two Waveform Behavioral Models
      Bernhard Unger, Siemens AG

    IBIS Version 3.2 Update
      Stephen Peters, Intel

    BREAK

    IBIS Management and CHECK at Siemens ICN
      Gerald Bannert, Siemens

    DOGEN, An Internal Model Library Management Tool
      Hans Pichlmaier, Siemens

    General Questions and Discussions
      - IBIS Interpretation

    IBIS Future Requirements
      Stephen Peters, Intel

    Future Requirements on Frequency Dependent Package and MCM Modeling
    (Tentative)
      Werner Rissiek, INCASES Engineering

    General Questions and Discussions
      - Future Requirements
      - Any other topic of interest

    Ad-hoc Presentations

Another flyer will be sent out early next week.  The Agenda will be sent out
one week in advance.

Presenters are requested to send electronic copies of their presentations to
karine_loudet@mentor.com for copying by February 26, 1999 or earlier.
Otherwise plan to bring 50 copies for the meeting.  Stephen Peters reported
problems with this address, and Bob will handle this offline.  (Stephen
successfully sent his presentations.)  Bob noted that some of the
presentations may be uploaded under a Mar99 subdirectory before the meeting.


IBIS VERSION 3.2 EIA STANDARD PREPARATIONS
Bob Ross stated that IBIS Version 3.2 had been ratified at the January 15,
1999 meeting and the ARs for it had been completed.

The revised document was uploaded at

  http://www.eda.org/pub/ibis/ver3.2/ver3_2.ibs

Patti Rusher supplied a link to Bob regarding an example of a JEDEC document
that is downloadable and subject to electronic balloting.  Bob plans to have
an electronic balloting mechanism set up for ratification of IBIS Version 3.2
as ANSI/EIA-656A.  However, Bob is not aware that anything has been set up
yet.


IBISCHK3 VERSION 3.2.2 AND VERSION 3.2.3
Bob Ross reported that the ibischk3 Version 3.2.2 and Version 3.2.3 have been
distributed to the companies supporting the parser development.  The
executables for ibischk3 version 3.2.2 have been uploaded.

Several issues came up.  Atul Agarwal asked if the old ibis_chk executable for
Version 1.1 should be split off.  He gave the options of deleting it from
ibischk3, accessing it by a switch, or keep as is (autodetect Version 1.1
level files to invoke the ibis_chk code.  Bob favored keeping ibischk3 as is.

Bob also noted that it was reported that the hp10 executable did not properly
handle the IBIS Version 3.2 extension on the number of characters allowed in
file names when the file name had more than 8 characters.  ibischk3 worked
fine for Sun UNIX and Windows operating systems.  Matthew Flora stated that he
tracked the location where the error is being generated.  He will work with
Chris Rokusek (and Atul) for more clarification and testing.

Bob raised the new agenda item for approving payment to Atul Agarwal.  Bob
reported that Atul had performed work beyond the scope of the work leading
to ibischk3 Version 3.1.0.  He had been paid for the original work.  The work
for the extensions to ibischk3 Version 3.2.3 had to deal with some significant
additions associate with 10 BIRDs (including the new [Submodel] mechanism)
and many BUG reports.  He had done the extension based on an agreement that
he would be compensated at a later time.  The amount of work adds up to
$4168.00.  Bob felt that that was a fair amount and called for a vote to
authorize the EIA to pay for this when the formal invoice from Atul is
received.

Payment authorization to Atul Agarwal was approved by unanimous vote.

Matthew Flora questioned whether this was a vote to ratify the parser.  Bob
stated that the parser still had the hp10 bug above, but suggested that the
ratification vote be held at the next scheduled teleconference meeting
(scheduled March 26, 1999).  Bob expects that more work and revisions will
be done to the parser as problems are reported, but it is sufficiently stable
for ratification.

Michael Cohen questioned whether ibischk3 included other versions of the 
parser.  Bob Ross and others responded that ibischk3 is also referred as a
parser, and it contains the functionality of IBIS Version 2.1 and IBIS
Version 1.1 testing within the ibischk3 executable.  Executables are available
off of the IBIS FTP site, but source code is issued only to those companies
who are funding the project.  These companies have the benefit of the first
release, and executables are not always produced for each release.


TEKTRONIX IPA 510 SOFTWARE DISTRIBUTION PROPOSAL
The remainer of the meeting was devoted to the Tektronix IPA 510 software
distribution proposal.  In order to deal with this topic, Bob Ross stated that
we would follow Syed Huq's private suggestion using the sequence below:

  Briefly introduce the background and proposal
  Hear arguments favoring the proposal
  Hear arguments opposing the proposal
  Open the meeting to discussion and more arguments
  Conduct a vote
  
Bob stated that the issue will be decided by majority vote of the official
IBIS members at the meeting.  Bob had not received notification of any new 
members.  If there were a tie vote, the issue would be brought up the next 
teleconference for more discussion and another vote. 

Bob started by presenting the background.  At the November 6, 1998
teleconference meeting Tektronix had proposed a free transfer to the IBIS Open
Forum of the IPA 510 software product for parameter extraction based on time
domain reflectometry measurements.  The Forum would distribute both the 
executable and source code and provide support.  Tektronix would retain the
right to sell products based on this code or derivatives of it.  The source
code would be distributed only to people agreeing to provide back to the IBIS
Open Forum the source code with any enhancements based on the code.  After
extensive discussion, the IBIS Open Forum approved distributing only the
executable code, but had to resolve a few questions and needed refinement of
the agreement before agreeing to distribute the source code.

While in pursuit of some of these questions, a few objections were raised.
The fundamental concern was whether it was appropriate for the IBIS Open Forum
to distribute this software.  This was discussed again at the November 20, 1998 
meeting.  The resolution was to continue discussion.  At the January 15, 1999
meeting, the issue was again discussed.  A vote was conducted with split
resolution just as the meeting time was running out.  Since these subsequent 
discussions were cut short because of other IBIS business or conducted under 
time pressure, we decided to raise the issue again at the February 19, 1999 
meeting and schedule enough time for full discussion and resolution.

Bob noted that there were no known barriers to accepting the proposal.  The
FTP site could be used for code distribution.  The EIA legal department had
given its approval.  At least one person was identified to handle the source
code distribution.  We could develop appropriate processes for source code
distribution and control.  The executable was dongle-free, and documentation
was included. in the product.  In addition, Syed had investigated some other
alternatives for source code distribution, but these did not look promising.

Syed and Matthew Flora suggested that the issue first be constrained to only
dealing with distribution of the executable.  Bob agreed, although he
expressed concern that one fundamental motivation for discussing the proposal
was to make the source code available for improvement.

Tom Brinkoetter discussed again why Tektronix was making the offer.  Tektronix 
has discontinued the IPA 510 hardware and software product and no longer can
provide support.  In order to help the existing user community, Tektronix is
interested in offering the product to the IBIS Open Forum and to help develop
a self-supporting user community.

Tom responded to a number of questions before having to leave for another
committment.  Stephen Peters questioned why the product could not just be
offered from a Tektronix web site, and Tom responded that the Tektronix logo
and location would convey implicit support.  Tom clarified Bob's understanding
that, the current product executable operates only on Windows 3.1 and
Windows 95.  It does not work on Windows NT.  

During the discussion, Bob read parts of the agreement for clarification.

The arguments in favor of and against the proposal were presented by everyone
and do not necessarily represent one's overall support or opposition to the
proposal.  Some are paraphrased to capture the essence.

The arguments in favor:

  1.  Syed stated that the IPA 510 was a widely used tool.  He found it  
      relevant to IBIS for developing measurement based IBIS models.  It was 
      particularly useful for VT tables and for extracting the capacitance 
      information.  
      
  2.  Syed also stated that the support would be through voluntary effort 
      similar to the support done for s2ibis.  It would not be a burden on
      the IBIS Open Forum.  Milt Schwartz reaffirmed this position.
  
  3.  Raj Raghuram indicated that this could be considered a free tool similar
      to s2ibis.

  4.  Matthew Flora argued that offering the utility had a positive effect on
      the market.  Free utilities did not detract from commercial operations.
      (Examples could be Berkeley Spice versus commercial Spice, or free
      linux versus commercial linux.)  Later it was argued that the free
      utility sets the "base-line" or level of expectation for commercial 
      utilities.

  5.  Milt and Bob indicated that having the utility available would be a
      factor in educating the community on TDR and parameter extraction
      technology.
  
  6.  Greg Edlund also supported the TDR method as the simpler method for
      package model parameter extraction.

  7.  Later Syed argued that the executable itself would become obsolete
      within about two years as Windows 3.1 and Windows 95 systems were
      phased out.
      
Arguments in opposition:  

  1.  Stephen Peters was concerned that the IBIS Forum should not be 
      responsible for distributing a product that competed with potential
      commercial products.  It could undercut commercial attempts.  Some
      discussion occurred that the other free utilities were issued when there
      were no commercial alternatives.
      
  2.  Stephen felt Tektronix should take direct responsibility in distributing
      the executable.
      
  3.  Bob cited a top level concern that the executable, unlike other free
      utilities, was not directly related to IBIS.

  4.  Bob was concerned that EIA and IBIS are industry funded organizations 
      with high involvement with vendor-neutral standards development.  IBIS
      should avoid situations which may favor one commercial venture over 
      another.  Distributing the utility risked having the IBIS Forum loose
      credibility by intruding into the commercial arena.
      
  5.  Dima Symolansky argued that substantial support was needed for potential
      bugs and technical issues.  So rather than seeding the market, a bad
      experience with a free utility could discourage one from investigating
      a commercial alternative.
      
  6.  Bob felt that the support could be inadequate since better support of a
      product is available from a commercial organization where funding is
      involved (such as with ibischk3)

Raj asked whether under the transfer agreement, the executable could be
used in a commercial product (such as with a wrapper around it).  This was
discussed.  Bob thought it was permissible, but was not sure.  Others thought
it might not be technically practical.

Additional discussions and clarifications occurred and some other arguments may
have been presented, but not captured.  Upon completion, Bob called for a
vote.

The Tektronix proposal to have the IBIS Open Forum distribute the executable
code was rejected by a 4 NO to 3 YES vote.

It was determined that no other issues needed to be discussed regarding the
Tektronix proposal.  The meeting was concluded as time ran out.


COOKBOOK STATUS
(Not Discussed)


IBIS MODEL REVIEW COMMITTEE DISCUSSION
(Not Discussed)  The old AR remains.

AR - Matthew Flora to issue to the IBIS reflector a short write-up on the IBIS
Model Review Committee.


OLD TOPIC - BIRD56 - RELAXATION OF THE [Series Pin Mapping] RESTRICTION
(Not discussed)  The old AR remains.

AR - Arpad Muranyi provide an IBIS model example for BIRD56.


CONNECTOR PROPOSAL REVIEW
(Not Discussed)


ACCURACY SPECIFICATION REVIEW
(Not Discussed)


BUG34 - NO ERROR REPORTED FOR MISSING V/I TABLE IN OUTPUT BUFFERS
This new item was not discussed.


NEXT MEETING:
The next meeting will be an IBIS Summit Meeting at DATE99 from 12 PM to 
to 6 PM on Tuesday, March 9, 1999 at the Astron Hotel in Munich, Germany.

The following teleconference meeting will be on Friday, March 26, 1999 from
8:00 AM to 10:00 AM.
==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentorg.com
            Modeling Engineer, Interconnectix BU of Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            sjpeters@ichips.intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-56
            2111 NE 25th Ave. 
            Hillsboro, Oregon 97124-5961

SECRETARY:  Matthew Flora (425) 869-2320, Fax: (425) 881-1008
            mbflora@hyperlynx.com
            Senior Engineer, HyperLynx, Inc.
            17641 NE 67th Court
            Redmond, WA 98052

LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
            jonp@qdt.com
            Senior Scientist, Viewlogic Systems (formerly Quad Design)
            1385 Del Norte Rd., Camarillo, CA 93010
 
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is 
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eia.org

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.
==============================================================================

From owner-ibis  Wed Feb 24 16:49:31 1999
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Received: from Kellee98 ([192.168.148.110])
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	Wed, 24 Feb 1999 16:44:08 -0800
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Date: Wed, 24 Feb 1999 16:44:16 -0800
To: ibis@eda.org, ibiscnn@mail.hyperlynx.com
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: IBIS Connector group status.
In-Reply-To: <3.0.5.32.19990223191211.00b377c0@hyperwall>
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Update on IBIS connector sub-group activities.

  At the presentation at DesignCon99 earlier this month
we had a few questions come up.  Most notable were the following:

1) The documentation about the type of matrix data needs a better
   description.  We agreed to add more documentation in this area:
   We have not completed this A.I. yet.

2) There is no way to describe lossy R,L,C,G effects.
   The sub-group responded by saying we had considered it but felt
   is was too complex to include in the first version of the specification.
   We agreed to reopen this for discussion in the sub-group.
   See below for details.

We have not gotten the full connector sub-group back together 
since DesignCon but we plan to do so next week.  I felt we owed
an update since we have not reported back on the IBIS meeting
inputs.

Please feel free to forward any comments for the connector 
sub-group to me.  We are very interested in creating a standard
that works for the majority of users.

In the mean time we had a discussion between Teradyne
and HyperLynx Electromagnetic guru's and begun discussions of
methods to describe lossy information in the specification.


HyperLynx-Teradyne meeting summary:
1) How do we describe the 3 major types of resistive loss
across frequency (R matrix).  General methods in use today only focus
on one or two and require geometric data as input.
2) How do we describe L,C frequency effects
3) How do we describe dielectric loss v.s. frequency (G matrix).

We discussed several methods and agreed that a full loss model
was very complex.  We determined 3 possible courses of action:
1) Continue without loss in the first release (follow up later)
2) Create a very simplified loss method for the first release
3) Continue discussions until a full featured loss model is found.

It was mentioned several times that because connectors are very short
typically less than an inch the loss with todays uses is very small
and we could probably get by without including loss until the next release.
It was also mentioned that acquiring the data from real connector models
to describe several aspects of loss is very difficult.
We also discussed the possibility of using the IBIS connector model for
doing cable models.

We will be discussing these options in the next connector sub-group meeting
and report our suggestions at that time to the full IBIS group.
We want to give serious consideration for method a simplified model at
that time.
More of the meeting details will be sent from Mikhail at Teradyne
to sub-committee along with a first cut at the proposed simplified loss model.

Kellee


---------------------------------------------------------
Have a great day....
Kellee Crisafulli at HyperLynx
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------

From owner-ibis  Wed Feb 24 16:57:43 1999
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 24 Feb 1999 16:52:14 -0800 (PST)
Date: Wed, 24 Feb 1999 16:51:12 -0800
From: Jon Powell <jonp@pacbell.net>
Subject: IBIS model page update
To: ibis@vhdl.org
Reply-to: jpowell@viewlogic.com
Message-id: <36D49E80.41791877@pacbell.net>
Organization: Viewlogic Consulting Services
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Hi IBIS type persons,

I have update the IBIS MODEL PAGE (http://www.eia.org/EIG/IBIS/ibis.htm
and select "models").
There are several new model references there but a couple pages have
disappeared.

As always, if you know where more models are, please send me email:
jonp@pacbell.net

sincerely,
Jon Powell
IBIS Librarian

From owner-ibis  Wed Feb 24 20:50:41 1999
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Date: Wed, 24 Feb 1999 20:45:21 -0800
From: Scott McMorrow <scott@vasthorizons.com>
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To: Kellee Crisafulli <kellee@hyperlynx.com>, ibis@eda.org
Subject: Re: IBIS Connector group status concerning ac losses
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Kellee,

It is in the area of extending the model for use with packages (which can be
quite lossy), cables (which do have significant losses), and pcboard traces
(as an extension to the current ebd non-lossless model) that some
sort of frequency dependent loss model is needed.  The Hspice W-element
model with a frequency dependent dielectric and skin effect loss is generally
good to the 1 to 2 GHz range, within a small margin of error.  Yes, there are
frequency dependent changes in L and C, however, they are quite small
in the frequency ranges where IBIS simulations are generally run.

AC losses are a significant factor in real systems with sub-400ps edge rates,
and high frequencies.  I see these effects in source synchronous bus simulations
in the 200 to 400MHz range, where the edge rate harmonics approach 1.5 to
2 GHz.  They significantly effect noise margins and timing of high speed signals,
and
definitely effect the eye patterns of fiber channel and gigabit ethernet signals.

I would suggest that the committee take the lead and define an extensible method
of describing ac losses.  One that could be enhanced by different methods of
modeling
in the future.  For example, using the current matrix models that you have for
lossless transmission line sections, you could easily extend this to an RLGC
matrix
with an Rs, which is the frequency dependent skin effect resistance, and Gd, which

is the frequency dependent dielectric loss.  Other, possibly more advanced,
modeling
types could be included in the standard in the future.

I agree that, in general, ac losses are insignificant for most connectors.
However, if
we are creating a coupled matrix template to be used in other areas, as I have
suggested above, then it makes sense to consider inclusion of frequency dependent
losses in this standard.  Otherwise, it will be years before the chance will occur
again.

If we think of this as a way to enhance ebd and package modeling, then I believe
adding ac losses to the coupled matrix descriptions makes undeniable sense.

If you don't beleive, then try to correlate a 400MHz memory bus simulation to
measurements using an IBIS simulator with currentebd models of the RIMM modules.
It can't be done.

Regards,

Scott

> 2) There is no way to describe lossy R,L,C,G effects.
>    The sub-group responded by saying we had considered it but felt
>    is was too complex to include in the first version of the specification.
>    We agreed to reopen this for discussion in the sub-group.
>    See below for details.
> HyperLynx-Teradyne meeting summary:
> 1) How do we describe the 3 major types of resistive loss
> across frequency (R matrix).  General methods in use today only focus
> on one or two and require geometric data as input.
> 2) How do we describe L,C frequency effects
> 3) How do we describe dielectric loss v.s. frequency (G matrix).
>
> We discussed several methods and agreed that a full loss model
> was very complex.  We determined 3 possible courses of action:
> 1) Continue without loss in the first release (follow up later)
> 2) Create a very simplified loss method for the first release
> 3) Continue discussions until a full featured loss model is found.
>
> It was mentioned several times that because connectors are very short
> typically less than an inch the loss with todays uses is very small
> and we could probably get by without including loss until the next release.
> It was also mentioned that acquiring the data from real connector models
> to describe several aspects of loss is very difficult.
> We also discussed the possibility of using the IBIS connector model for
> doing cable models.
>

From owner-ibis  Thu Feb 25 15:02:44 1999
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "\"ibis@eda.org\" " <ibis@eda.org>,
        "\"ibiscnn@mail.hyperlynx.com\" "
	 <ibiscnn@mail.hyperlynx.com>,
        "\"Kellee Crisafulli\" "
	 <kellee@hyperlynx.com>
Subject: RE: IBIS Connector group status.
Date: Thu, 25 Feb 1999 14:56:00 -0800
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Kellee,

Thanks for the update.  I agree that the losses for a connector may be 
negligible, because they are fairly short.  However, it was also brought up
at 
DesignCon99 that whatever you do for the connector should be generalized for
EBD
and package, if possible, since they are so similar.  If that can be done, 
losses would become much more important.

Could an HSPICE-like method (W-element's matrix format with Rs and Gd) be 
adopted as an interim solution?

If possible at all, I would like to see the connector spec to be extended to
the
package at least since we have burning needs there, for which it would be
good 
to have the losses.

Arpad
============================================================================
====



Update on IBIS connector sub-group activities.

  At the presentation at DesignCon99 earlier this month
we had a few questions come up.  Most notable were the following:

1) The documentation about the type of matrix data needs a better
   description.  We agreed to add more documentation in this area:
   We have not completed this A.I. yet.

2) There is no way to describe lossy R,L,C,G effects.
   The sub-group responded by saying we had considered it but felt
   is was too complex to include in the first version of the specification.
   We agreed to reopen this for discussion in the sub-group.
   See below for details.

We have not gotten the full connector sub-group back together
since DesignCon but we plan to do so next week.  I felt we owed
an update since we have not reported back on the IBIS meeting
inputs.

Please feel free to forward any comments for the connector
sub-group to me.  We are very interested in creating a standard
that works for the majority of users.

In the mean time we had a discussion between Teradyne
and HyperLynx Electromagnetic guru's and begun discussions of
methods to describe lossy information in the specification.


HyperLynx-Teradyne meeting summary:
1) How do we describe the 3 major types of resistive loss
across frequency (R matrix).  General methods in use today only focus
on one or two and require geometric data as input.
2) How do we describe L,C frequency effects
3) How do we describe dielectric loss v.s. frequency (G matrix).

We discussed several methods and agreed that a full loss model
was very complex.  We determined 3 possible courses of action:
1) Continue without loss in the first release (follow up later)
2) Create a very simplified loss method for the first release
3) Continue discussions until a full featured loss model is found.

It was mentioned several times that because connectors are very short
typically less than an inch the loss with todays uses is very small
and we could probably get by without including loss until the next release.
It was also mentioned that acquiring the data from real connector models
to describe several aspects of loss is very difficult.
We also discussed the possibility of using the IBIS connector model for
doing cable models.

We will be discussing these options in the next connector sub-group meeting
and report our suggestions at that time to the full IBIS group.
We want to give serious consideration for method a simplified model at
that time.
More of the meeting details will be sent from Mikhail at Teradyne
to sub-committee along with a first cut at the proposed simplified loss
model.

Kellee


---------------------------------------------------------
Have a great day....
Kellee Crisafulli at HyperLynx
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------
From owner-ibis  Fri Feb 26 09:15:38 1999
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Date: Fri, 26 Feb 1999 09:10:57 -0800 (PST)
From: Scott Lin <scottlin@yahoo.com>
Reply-To: scottlin@pacbell.net
Subject: SUBSCRIBE
To: ibis@eda.org
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

SUBSCRIBE




==

Scott Lin

Project Manager
Foxconn International, Inc
Direct:  408-919-6175   Main: 408-919-6100  Fax: 408-330-6988
Email:  scottlin@pacbell.net
_________________________________________________________
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