******************************************************************************
* Main Circuit Netlist:
*
* Library: test  Cell: package_test
******************************************************************************
.subckt  package_test vddq_ball_a1 dq_ball_a2 vssq_ball_a3 vddq_pad_a1 dq_pad_a2 vssq_pad_a3 pkg_ref_gnd
ca1 vddq_ball_a1 pkg_ref_gnd 0.2p
ca2   dq_ball_a2 pkg_ref_gnd 0.2p
ca3 vssq_ball_a3 pkg_ref_gnd 0.2p
ca1a2 vddq_ball_a1 vddq_ball_a2 0.2p
ca2a3   dq_ball_a2 vddq_ball_a3 0.2p
ca1a3 vssq_ball_a1 vddq_ball_a3 0.2p
la1   vddq_ball_a1 net1 2n
la2   vddq_ball_a2 net2 2n
la3   vddq_ball_a3 net3 2n
k12 la1 la2 0.5
k23 la2 la3 0.5
k13 la1 la3 0.5
r1 net1 vddq_pad_a1 0.2
r1 net2   dq_pad_a2 0.2
r1 net3 vssq_pad_a3 0.2
.ends package_test