***************************************************************************** ***************************************************************************** ***************************************************************************** BUFFER ISSUE RESOLUTION DOCUMENT (BIRD) BIRD ID#: 85.2 ISSUE TITLE: Slew Time Estimate Clarifications REQUESTOR: John Angulo, Mentor Graphics Corp. DATE SUBMITTED: October 3, 2003 DATE REVISED: November 7, 2003 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ***************************************************************************** ***************************************************************************** STATEMENT OF THE ISSUE: IBIS models have always provided EDA tools with a first-order estimate of driver slew time through the [Ramp] keyword. This BIRD proposes to continue this practice for models using the [External Model] keyword. It clarifies the purpose and method of [Ramp] data measurment with language in the Usage Rules of the [External Model] keyword to: a) Specify [Ramp] as a required keyword within a [Model] that calls an [External Model]. b) Explain that in such models, [Ramp] data are to provide estimated slew characteristics only, and should be measured with a load that conforms to the driver's intended operation, rather than that recommended in Section 9: Notes on Data Derivation Method. Lines changed in the first revision of the BIRD are preceeded by *. Lines changed in the second revision are preceeded by **. Lines changed in the third revision are preceeded by ***. **************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: |============================================================================= | Keyword: [External Model], [End External Model] | Required: No | Description: Used to reference an external file written in one of the | supported languages containing an arbitrary circuit | definition, but having ports that are compatible with the | [Model] keyword, or having ports that are compatible with | the [Model] keyword plus an additional signal port for true | differential buffers. | | Sub-Params: Language, Corner, Parameters, Ports, D_to_A, A_to_D | Usage Rules: The [External Model] keyword must be positioned within a | [Model] section and it may only appear once for each [Model] | keyword in a .ibs file. It is not permitted under the | [Submodel] keyword. | | [Circuit Call] may not be used to connect an [External Model]. | | A native IBIS [Model]'s data may be incomplete if the [Model] | correctly references an [External Model]. Any native IBIS | keywords that are used in such a case must contain syntactically | correct data and subparameters according to native IBIS rules. | In all cases, [Model]s which reference [External Model]s must | include the following keywords and subparameters: | | Model_type | Vinh, Vinl (as appropriate to Model_type) | [Voltage Range] and/or [Pullup Reference], | [Pulldown Reference], [POWER Clamp Reference], | [GND Clamp Reference], [External Reference] *| [Ramp] *| ***| In models without the [External Model] keyword, data for [Ramp] ***| should be measured using a load that conforms to the ***| recommendations in Section 9: Notes on Data Derivation Method. ***| However, when used within the scope of [External Model], the ***| [Ramp] keyword is intended strictly to provide EDA tools with a ***| quick first-order estimate of driver switching characteristics. ***| When using [External Model], therefore, data for [Ramp] may be ***| measured using a different load, if it results in data that ***| better represent the driver's behavior in standard operation. ***| Also in this case, the R_load subparameter is optional and will ***| be ignored by EDA simulators. For example, the 20% to 80% **| voltage and time intervals for a differential buffer may be **| measured using the typical differential operating load **| appropriate to that buffer's technology. Note that voltage and **| time intervals must always be recorded explicitly rather than **| as a reduced fraction, in accordance with [Ramp] usage rules. *| *| The following keywords and subparameters may be omitted, *| regardless of Model_type, from a [Model] using [External Model]: *| **| C_comp, C_comp_pullup, C_comp_pulldown, C_comp_power, **| C_comp_gnd *| [Pulldown], [Pullup], [POWER Clamp], [GND Clamp] | | Subparameter Definitions: | < skipping unchanged text...> | | |----------------------------------------------------------------------------- | Example [External Model] using SPICE: |-------------------------------------- | [Model] ExBufferSPICE Model_type I/O Vinh = 2.0 Vinl = 0.8 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 *| *[Ramp] *dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n *dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | [External Model] Language SPICE | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ buffer_typ.spi buffer_io_typ Corner Min buffer_min.spi buffer_io_min Corner Max buffer_max.spi buffer_io_max | | Parameters - Not supported in SPICE | | Ports List of port names (in same order as in SPICE) Ports A_signal my_drive my_enable my_receive my_ref Ports A_puref A_pdref A_pcref A_gcref A_extref | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable my_enable A_gcref 0.0 3.3 0.5n 0.3n Typ | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive my_receive my_ref 0.8 2.0 Typ | | Note: A_signal might also be used instead of a user-defined interface port | for measurements taken at the die pads | [End External Model] | |----------------------------------------- | Example [External Model] using VHDL-AMS: |----------------------------------------- | [Model] ExBufferVHDL Model_type I/O Vinh = 2.0 Vinl = 0.8 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 *| *[Ramp] *dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n *dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | [External Model] Language VHDL-AMS | | Corner corner_name file_name circuit_name entity(architecture) Corner Typ buffer_typ.vhd buffer(buffer_io_typ) Corner Min buffer_min.vhd buffer(buffer_io_min) Corner Max buffer_max.vhd buffer(buffer_io_max) | | Parameters List of parameters Parameters delay rate Parameters preemphasis | | Ports List of port names (in same order as in VHDL-AMS) Ports A_signal A_puref A_pdref A_pcref A_gcref Ports D_drive D_enable D_receive | [End External Model] | |-------------------------------------------- | Example [External Model] using Verilog-AMS: |-------------------------------------------- | [Model] ExBufferVerilog Model_type I/O Vinh = 2.0 Vinl = 0.8 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 *| *[Ramp] *dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n *dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | [External Model] Language Verilog-AMS | | Corner corner_name file_name circuit_name (module) Corner Typ buffer_typ.v buffer_io_typ Corner Min buffer_min.v buffer_io_min Corner Max buffer_max.v buffer_io_max | | Parameters List of parameters Parameters delay rate Parameters preemphasis | | Ports List of port names (in same order as in Verilog-AMS) Ports A_signal A_puref A_pdref A_pcref A_gcref Ports D_drive D_enable D_receive | [End External Model] | |----------------------------------------------------------- | Example of True Differential [External Model] using SPICE: |----------------------------------------------------------- | [Model] Ext_SPICE_Diff_Buff Model_type I/O_diff Rref_diff = 100 | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 | *| *[Ramp] *dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n *dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | [External Model] Language SPICE | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ diffio.spi diff_io_typ Corner Min diffio.spi diff_io_min Corner Max diffio.spi diff_io_max | | Ports List of port names (in same order as in SPICE) Ports A_signal_pos A_signal_neg my_receive my_drive my_enable Ports A_puref A_pdref A_pcref A_gcref A_extref my_ref A_gnd | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive my_drive my_ref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive my_drive my_ref 0.0 3.6 0.4n 0.3n Max D_to_A D_enable my_enable my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable my_enable my_ref 0.0 3.0 0.6n 0.3n Min D_to_A D_enable my_enable my_ref 0.0 3.6 0.4n 0.3n Max | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive A_signal_pos A_signal_neg -200m 200m Typ A_to_D D_receive A_signal_pos A_signal_neg -200m 200m Min A_to_D D_receive A_signal_pos A_signal_neg -200m 200m Max | [End External Model] | | |-------------------------------------------------------------- | Example of True Differential [External Model] using VHDL-AMS: |-------------------------------------------------------------- | [Model] Ext_VHDL_Diff_Buff Model_type I/O_diff Rref_diff = 100 | | typ min max [Voltage Range] 3.3 3.0 3.6 *| *[Ramp] *dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n *dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | | Other model subparameters are optional | [External Model] Language VHDL-AMS | | Corner corner_name file_name circuit_name entity(architecture) Corner Typ diffio_typ.vhd buffer(diff_io_typ) Corner Min diffio_min.vhd buffer(diff_io_min) Corner Max diffio_max.vhd buffer(diff_io_max) | | Parameters List of parameters Parameters delay rate Parameters preemphasis | | Ports List of port names (in same order as in VHDL-AMS) Ports A_signal_pos A_signal_neg D_receive D_drive D_enable Ports A_puref A_pdref A_pcref A_gcref | [End External Model] | |------------------------------------------------------------- | Example of Pseudo-Differential [External Model] using SPICE: |------------------------------------------------------------- | | Note that [Pin] and [Diff Pin] declarations are shown for clarity | | [Pin] signal_name model_name R_pin L_pin C_pin 1 Example_pos Ext_SPICE_PDiff_Buff 2 Example_neg Ext_SPICE_PDiff_Buff | | ... | [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max 1 2 200mV 0ns 0ns 0ns | | ... | [Model] Ext_SPICE_PDiff_Buff Model_type I/O | | Other model subparameters are optional | | typ min max [Voltage Range] 3.3 3.0 3.6 *| *[Ramp] *dV/dt_r 1.57/0.36n 1.44/0.57n 1.73/0.28n *dV/dt_f 1.57/0.35n 1.46/0.44n 1.68/0.28n | [External Model] Language SPICE | | Corner corner_name file_name circuit_name (.subckt name) Corner Typ diffio.spi diff_io_typ Corner Min diffio.spi diff_io_min Corner Max diffio.spi diff_io_max | | Ports List of port names (in same order as in SPICE) Ports A_signal my_drive my_enable my_ref Ports A_puref A_pdref A_pcref A_gcref A_gnd A_extref | | D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive my_ref 0.0 3.3 0.5n 0.3n Typ D_to_A D_drive my_drive my_ref 0.0 3.0 0.6n 0.3n Min D_to_A D_drive my_drive my_ref 0.0 3.6 0.4n 0.3n Max D_to_A D_enable my_enable A_pcref 0.0 3.3 0.5n 0.3n Typ D_to_A D_enable my_enable A_pcref 0.0 3.0 0.6n 0.3n Min D_to_A D_enable my_enable A_pcref 0.0 3.6 0.4n 0.3n Max | | A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive A_signal my_ref 0.8 2.0 Typ A_to_D D_receive A_signal my_ref 0.8 2.0 Min A_to_D D_receive A_signal my_ref 0.8 2.0 Max | | This example shows the evaluation of the received signals at the die | pads. [Diff Pin] defines the interpretation of the A_to_D output | polarity and levels and overrides the A_to_D settings shown above. | [End External Model] | |============================================================================= ***************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: In IBIS version 1.0, the [Ramp] keyword was the sole source of buffer slew information, recording the driver's 20% to 80% slew voltage and slew time. The specification's data derivation notes recommended measuring these data using resistive loads similar to those expected with the most prevalent CMOS or ECL drivers on typical printed circuit boards. When [Rising Waveform] and [Falling Waveform] keywords containing V-T tables were added with IBIS version 2.1, the [Ramp] keyword was retained, and continues to provide tools with a concise figure for buffer slew time important for estimating driver strength and speed prior to simulation. As new driver technologies have proliferated, particularly LVDS and other methods of differential signaling, the originally recommended load for [Ramp] extraction has become obsolete for some cases. However, EDA tools continue to use the [Ramp] keyword for a quick first-order estimate of driver slew time, rather than directly in simulation. In differential models, for example, model makers still extract useful data for the [Ramp] keyword by measuring slew voltage and time under a differential load appropriate for the technology. The EDA tools need not know the particular load used, because they no longer use the [Ramp] to generate buffer waveforms when V-T tables are present. Multi-lingual models using the [External Model] keyword rely on an external SPICE or VHDL-AMS module to generate buffer waveforms. Yet they still document important behavioral data like logic switching thresholds and voltage supply range with existing, familiar IBIS constructs. This BIRD makes the necessary text changes and clarifications to include estimated slew time with these behavioral data using the [Ramp] keyword. ***************************************************************************** ANY OTHER BACKGROUND INFORMATION: BIRD 85 changes are marked with the * character. BIRD 85.1 changes are marked with ** characters. These changes tighten the language specifying when and how a different load may be used for [Ramp] under [External Model]. They also include a minor editorial change: under optional keywords for [External Model], C_comp_pullup, C_comp_pulldown, C_comp_power and C_comp_gnd are listed explicitly, rather than through the use of "C_comp_*". *****************************************************************************