From: owner-ibis-users@ (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #2 Reply-To: Sender: owner-ibis-users@ Errors-To: owner-ibis-users@ Precedence: bulk ibis-users Friday, February 15 2002 Volume 01 : Number 002 ---------------------------------------------------------------------- Date: Fri, 19 Oct 2001 17:07:24 -0400 From: "Ingraham, Andrew" Subject: RE: High frequency performance of IBIS model > IBIS models have only a constant capacitance to account for > the die capacitance, which means that there is no frequency > dependency in their impedance. No voltage dependency either. And various other second-order effects that are missing, which don't bite you until you push the frequencies high enough. Also, most IBIS models you will find, have just the simple package model which consists of simple RLC parameters, and no specified way in which they are connected, i.e., lumped vs. distributed, pi vs. tee vs. ell ... which may be OK for lower speeds but not so hot at higher frequencies. And no couplings either. Finally, many IBIS models are garbage simply because the people who made them, didn't really know what they were doing. It's easy to throw together an IBIS model using s2ibis, and not understand the first thing about IBIS, nothing about SPICE modeling, and very little about using SPICE. It's real hard to make a SPICE model without a solid grounding in both SPICE usage and SPICE modeling. Andy ------------------------------ Date: Fri, 19 Oct 2001 16:19:33 -0700 From: "Raj Raghuram" Subject: RE: High frequency performance of IBIS model This is a multi-part message in MIME format. - ------=_NextPart_000_0055_01C158B9.D6DC4B40 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit High frequency performance of IBIS modelDear Chao, What you have raised is a question many people are asking these days. Here is my two cents worth. I feel that all components of the system you are trying to model need to be modelled to the same degree of accuracy. It may be that your IBIS model is not accurate enough for some of the reasons mentioned such as (absence of) frequency dependent parameters, fixed Ccomp etc. However, you may be making bigger assumptions in the rest of your simulation. For example, you may not be taking into account the power/ground noise in your system or the characteristics of the power delivery system. And even if you had a model which had everything - frequency dependent dielectric constant, frequency dependent loss tangent, skin effect, nonlinear circuit elements with the latest MOS model, full wave effects, etc. etc. - you probably would not find a simulator which can handle all this. I believe that IBIS models are far from being the weakest link in system simulation. Of course, I would still ensure that my IBIS models are reasonable. I would then ensure that I am simulating the rest of the system (planes, traces, vias, package pins, connectors, etc) to a sufficient degree of accuracy before trying to improve on the IBIS models. Best Regards, Raj Raghuram Sigrity, Inc. "Achieve what others can't" raghu@sigrity.com http://www.sigrity.com 4675 Stevens Creek Blvd. , Ste 130 Santa Clara, CA-95051 PH: 408-260-9344 x116 CELL: 408-390-7614 FAX: 408-260-9342 -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf Of Chao Su Sent: Friday, October 19, 2001 12:41 PM To: ibis-users@eda.org Subject: High frequency performance of IBIS model Hi, I'm working in signal integrity of optical transceivers. I'm considering of using IBIS model for my simulation, our optical transciever is operated at 2.5Gb/s. Somebody told me that IBIS model is not good to predict high frequency behavior for the device. I would like you can give me advice about what issue I need to concern when I get my IBIS model from vendors and how I can make sure the model is good in high frequency simulations. Thanks Chao Su Optical Systems Design (Dept. QF11) Nortel Networks P. O. Box 3511 Station C, Ottawa, ON, K1Y 4H7 Canada ---------------------------------------------------------------- (Phone: (613) 765-7688 (ESN 395-7688) *E-mail: csu@nortelnetworks.com +Mail Stop: 045/12/E06 - ------=_NextPart_000_0055_01C158B9.D6DC4B40 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable High frequency performance of IBIS model
Dear=20 Chao,
 
What=20 you have raised is a question many people are asking these days. Here is = my two=20 cents worth.
 
I feel=20 that all components of the system you are trying to model need to be = modelled to=20 the same degree of accuracy. It may be that your IBIS model is not = accurate=20 enough for some of the reasons mentioned such as (absence of) frequency=20 dependent parameters, fixed Ccomp etc. However, you may be making bigger = assumptions in the rest of your simulation. For example, you may not be = taking=20 into account the power/ground noise in your system or the = characteristics of the=20 power delivery system. And even if you had a model which had everything = - -=20 frequency dependent dielectric constant, frequency dependent loss = tangent, skin=20 effect, nonlinear circuit elements with the latest MOS model, full wave = effects,=20 etc. etc. - you probably would not find a simulator which can handle all = this.
 
I=20 believe that IBIS models are far from being the weakest link in system=20 simulation. Of course, I would still ensure that my IBIS models are = reasonable.=20 I would then ensure that I am simulating the rest of the system (planes, = traces,=20 vias, package pins,  connectors, etc) to a sufficient degree of = accuracy=20 before trying to improve on the IBIS models.
 
Best=20 Regards,
 

Raj Raghuram
Sigrity, Inc.
"Achieve what others=20 can't"
raghu@sigrity.com
http://www.sigrity.com
4675 Stevens Creek Blvd. , = Ste=20 130
Santa Clara, CA-95051
PH: 408-260-9344 x116
CELL:=20 408-390-7614
FAX: 408-260-9342

-----Original Message-----
From: = owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org]On Behalf Of Chao = Su
Sent:=20 Friday, October 19, 2001 12:41 PM
To:=20 ibis-users@eda.org
Subject: High frequency performance of = IBIS=20 model

Hi,

I'm working in signal integrity of = optical=20 transceivers. I'm considering of using IBIS model for my simulation, = our=20 optical transciever is operated at 2.5Gb/s. Somebody told me that IBIS = model=20 is not good to predict high frequency behavior for the device. I would = like=20 you can give me advice about what issue I need to concern when I get = my IBIS=20 model from vendors and how I can make sure the model is good in high = frequency=20 simulations.

Thanks

Chao = Su=20
Optical Systems = Design (Dept.=20 QF11)
Nortel=20 Networks
P. O. = Box=20 3511
Station C, = Ottawa, ON,=20 K1Y 4H7
Canada=20
----------------------------------------------------------------= =20
(Phone: (613) 765-7688 (ESN 395-7688)
*E-mail:       =20 csu@nortelnetworks.com
+Mail=20 Stop:     045/12/E06=20


- ------=_NextPart_000_0055_01C158B9.D6DC4B40-- ------------------------------ Date: Mon, 22 Oct 2001 12:15:40 -0700 From: tliu@semtech.com Subject: ibischk3 Hi, Can anyone tell me where I could download ibischk3.2.7? How to use it? Thanks Tina Liu Semtech Corp. 858-547-6615 ------------------------------ Date: Mon, 22 Oct 2001 16:21:08 -0700 From: Bob Ross Subject: Re: ibischk3 Tina: There are several links to ibischk3.2.7. The most direct is: http://www.eda.org/pub/ibis/ibischk3/ for the platform that you are using. Bob Ross Mentor Grapics tliu@semtech.com wrote: > > Hi, > Can anyone tell me where I could download ibischk3.2.7? How to use it? > > Thanks > > Tina Liu > Semtech Corp. > 858-547-6615 ------------------------------ Date: Tue, 23 Oct 2001 09:16:39 -0400 From: Adam.Tambone@fairchildsemi.com Subject: GND/PWR Clamp Data Collection Hello All, I have noticed slight differences in ground clamp curves for 3-state buffers dependent on whether the data was gathered when the device is driven high or low ( output hi-Z ). I have found the same to be true for power clamp curves. Should this be of concern? I have not found a standard in the Cookbook or the Spec with regard to whether the device should be driven high or low when GND and PWR clamp curves are gained. Is there a standard? Thanks, Adam Tambone ------------------------------ Date: Tue, 23 Oct 2001 11:04:20 -0400 From: "Ingraham, Andrew" Subject: RE: GND/PWR Clamp Data Collection > I have noticed slight differences in ground clamp curves for 3-state > buffers dependent on whether the data was gathered when the device is > driven high or low ( output hi-Z ). I have found the same to be true > for > power clamp curves. > You can only gather GND Clamp data when the device is (externally) driven Low; and you can only gather POWER Clamp data when the device is driven High; right? I am not sure I understand your question. For 3-state devices, the GND and POWER Clamp curves should be taken with the device in the hi-Z state. The Clamp curves are the only ones used to represent the device when simulated in the hi-Z state, so they need to be accurate. It may be true that the GND Clamp characteristic change when the device is enabled and drives High, or that the POWER Clamp characteristics change when the device is enabled and drives Low. But since the device spends very little, if any, of its time in these regions, I think those differences can always be ignored. Regards, Andy ------------------------------ Date: Tue, 23 Oct 2001 08:03:09 -0700 From: "Muranyi, Arpad" Subject: RE: GND/PWR Clamp Data Collection Adam, The buffers should be 3-stated when measuring clamps. Arpad Muranyi Intel Corporation ===================================================== - -----Original Message----- From: Adam.Tambone@fairchildsemi.com [mailto:Adam.Tambone@fairchildsemi.com] Sent: Tuesday, October 23, 2001 6:17 AM To: ibis-users@eda.org Subject: GND/PWR Clamp Data Collection Hello All, I have noticed slight differences in ground clamp curves for 3-state buffers dependent on whether the data was gathered when the device is driven high or low ( output hi-Z ). I have found the same to be true for power clamp curves. Should this be of concern? I have not found a standard in the Cookbook or the Spec with regard to whether the device should be driven high or low when GND and PWR clamp curves are gained. Is there a standard? Thanks, Adam Tambone ------------------------------ Date: Tue, 23 Oct 2001 12:32:48 -0400 From: Adam.Tambone@fairchildsemi.com Subject: RE: GND/PWR Clamp Data Collection Forgot to copy the list with the below response... thanks for the replies I have received. Adam - ---------------------- Forwarded by Adam Tambone/SouthPortland/Fairchild on 10/23/2001 12:29 PM --------------------------- Adam Tambone 10/23/2001 11:27 AM To: "Muranyi, Arpad" cc: Subject: RE: GND/PWR Clamp Data Collection (Document link: Adam Tambone) Hello again, yes the buffer is three stated, but there is a slight difference in the gnd/pwr clamp data dependent upon what source if any is placed on the input pin. For instance, I have found that the gnd/pwr clamp data is slightly different in each case where the input is hi, lo, or floating. The differences are small enough such that it is probably inconsequential, just thought someone would have an opinion. Adam "Muranyi, Arpad" @eda.org on 10/23/2001 11:03:09 AM Sent by: owner-ibis-users@eda.org To: ibis-users@eda.org cc: Subject: RE: GND/PWR Clamp Data Collection Adam, The buffers should be 3-stated when measuring clamps. Arpad Muranyi Intel Corporation ===================================================== - -----Original Message----- From: Adam.Tambone@fairchildsemi.com [mailto:Adam.Tambone@fairchildsemi.com] Sent: Tuesday, October 23, 2001 6:17 AM To: ibis-users@eda.org Subject: GND/PWR Clamp Data Collection Hello All, I have noticed slight differences in ground clamp curves for 3-state buffers dependent on whether the data was gathered when the device is driven high or low ( output hi-Z ). I have found the same to be true for power clamp curves. Should this be of concern? I have not found a standard in the Cookbook or the Spec with regard to whether the device should be driven high or low when GND and PWR clamp curves are gained. Is there a standard? Thanks, Adam Tambone ------------------------------ Date: Tue, 23 Oct 2001 13:40:44 -0400 From: "Ingraham, Andrew" Subject: RE: GND/PWR Clamp Data Collection Tom Dagostino points out another angle on this question. Perhaps the difference in Clamp curves is seen when the buffer is hi-Z, and the internal node that would have been used to drive the buffer, is pulled high or low. You'd think that this shouldn't have very much effect on the static characteristics of a CMOS buffer. But perhaps some buffers have lots of leakage or something, where you do see this effect. In that case, I figure you ought to take the extremes of both situations and incorporate them into your IBIS curves. After all, both cases will happen in real life. If you are working from a SPICE model, hopefully the model represents reality! Regards, Andy ------------------------------ Date: Tue, 23 Oct 2001 15:01:26 -0600 From: rrwolff Subject: EBD to SPICE conversion Hi all, Does anyone know of any tools for converting IBIS EBD files into SPICE netlists? Thanks, Randy Wolff ------------------------------ Date: 24 Oct 2001 08:55:42 +0200 From: Sebastien Poste Subject: MPC 755 Ibis Model The current IBIS model of the MPC 755 processor provided on the Web doesn't seem to be fully functionnal. We have detected the following problems : - RLC package parameters : Typical value is less than minimal value. - gf_io driver model seems to be bad : fall time close to 10ns. - Very high ground clamp current (higher than 200A). Is a new model of the MPC 755 avaible ? Or could we have the list of the corrections to be applicated on this model in order to make it work. Thanks for you answers. ------------------------------ Date: Wed, 24 Oct 2001 10:28:55 -0700 From: "Peters, Stephen" Subject: RE: MPC 755 Ibis Model Hi Sebastien: Your best course of action would be to contact the manufacture directly. Regards, Stephen Peters Intel Corp. - -----Original Message----- From: Sebastien Poste [mailto:sebastien.poste@matra-def.fr] Sent: Tuesday, October 23, 2001 11:56 PM To: ibis-info@eda.org; ibis-users@eda.org Subject: MPC 755 Ibis Model The current IBIS model of the MPC 755 processor provided on the Web doesn't seem to be fully functionnal. We have detected the following problems : - RLC package parameters : Typical value is less than minimal value. - gf_io driver model seems to be bad : fall time close to 10ns. - Very high ground clamp current (higher than 200A). Is a new model of the MPC 755 avaible ? Or could we have the list of the corrections to be applicated on this model in order to make it work. Thanks for you answers. ------------------------------ Date: Mon, 29 Oct 2001 07:59:28 -0500 From: Peter LaFlamme Subject: Re: GND/PWR Clamp Data Collection Adam, It is possible that the input pin is acting as an extra power or ground pin and could thus change your expected output data. When you step the output pin into to the extreme conditions Vout >> VDD or Vout << Gnd, the input pin may act as a parallel path to gnd or Vdd. This is all dependent on the design of the buffer and the esd structures. What you could do to test this is to tie a large value resistor 1K to 10K in series to the input (value should be determined by the leakage spec of the input). Then do your tri-state measurements. You should notice that the data would be pretty constant for either input "high" or input "low" conditions. I hope this helps, Peter Adam.Tambone@fairchildsemi.com wrote: > > Forgot to copy the list with the below response... thanks for the replies > I have received. > > Adam > > ---------------------- Forwarded by Adam Tambone/SouthPortland/Fairchild on > 10/23/2001 12:29 PM --------------------------- > > Adam Tambone > 10/23/2001 11:27 AM > > To: "Muranyi, Arpad" > cc: > > Subject: RE: GND/PWR Clamp Data Collection (Document link: Adam Tambone) > > Hello again, yes the buffer is three stated, but there is a slight > difference in the gnd/pwr clamp data dependent upon what source if any is > placed on the input pin. For instance, I have found that the gnd/pwr clamp > data is slightly different in each case where the input is hi, lo, or > floating. The differences are small enough such that it is probably > inconsequential, just thought someone would have an opinion. > > Adam > > "Muranyi, Arpad" @eda.org on 10/23/2001 11:03:09 > AM > > Sent by: owner-ibis-users@eda.org > > To: ibis-users@eda.org > cc: > > Subject: RE: GND/PWR Clamp Data Collection > > Adam, > > The buffers should be 3-stated when measuring clamps. > > Arpad Muranyi > Intel Corporation > ===================================================== > > -----Original Message----- > From: Adam.Tambone@fairchildsemi.com > [mailto:Adam.Tambone@fairchildsemi.com] > Sent: Tuesday, October 23, 2001 6:17 AM > To: ibis-users@eda.org > Subject: GND/PWR Clamp Data Collection > > Hello All, > > I have noticed slight differences in ground clamp curves for 3-state > buffers dependent on whether the data was gathered when the device is > driven high or low ( output hi-Z ). I have found the same to be true for > power clamp curves. Should this be of concern? I have not found a > standard in the Cookbook or the Spec with regard to whether the device > should be driven high or low when GND and PWR clamp curves are gained. Is > there a standard? > > Thanks, > Adam Tambone - -- Peter LaFlamme Applied Micro Circuits Corp. Staff System Applications Engineer 200 Minuteman Rd, 3rd Floor Andover, MA 01810 978-247-8470 phone 978-623-0055 Fax ------------------------------ Date: Wed, 31 Oct 2001 20:10:14 -0800 (PST) From: whiz kid Subject: New Member Hi, I would really appreciate if you can add my name to the IBIS user mailing list. Thanks, Rahul. __________________________________________________ Do You Yahoo!? Make a great connection at Yahoo! Personals. http://personals.yahoo.com ------------------------------ Date: Wed, 31 Oct 2001 20:10:14 -0800 (PST) From: whiz kid Subject: New Member Hi, I would really appreciate if you can add my name to the IBIS user mailing list. Thanks, Rahul. __________________________________________________ Do You Yahoo!? Make a great connection at Yahoo! Personals. http://personals.yahoo.com ------------------------------ Date: Thu, 1 Nov 2001 19:27:28 -0800 (PST) From: whiz kid Subject: Question about IBIS model. Hi Folks, I have a open drain model with built in pullup resistor. I need to create a similar model but with out the internal pullup. I would really appreciate if any of you can suggest as to how I need to approach this. Thanks in Advance. Rahul. __________________________________________________ Do You Yahoo!? Find a job, post your resume. http://careers.yahoo.com ------------------------------ Date: Thu, 1 Nov 2001 19:27:28 -0800 (PST) From: whiz kid Subject: Question about IBIS model. Hi Folks, I have a open drain model with built in pullup resistor. I need to create a similar model but with out the internal pullup. I would really appreciate if any of you can suggest as to how I need to approach this. Thanks in Advance. Rahul. __________________________________________________ Do You Yahoo!? Find a job, post your resume. http://careers.yahoo.com ------------------------------ Date: Fri, 2 Nov 2001 11:29:25 -0500 From: "Sathish K Krishnamurthi" Subject: requirements of ibis generation tools Hello All, I am a new user of ibis generation tools. I got some information that, a committe had been set up for defining the requirements of the ibis generation tool( probably an enhancement of s2ibis2) and also there was some documentation on the web regarding that. But now I am unable to get to that documentation. I would greatly appreciate if anyone could guide me as to where I can find the documentation defining the requirements of IBIS generation tools. Thanks Sathish Krishnamurthi ASIC Timing and Methodology IBM Microelectronics, Burlington Tel: 1-802-769-3509 Tieline : 446-3509 Fax: 1-802-769-7509 email: sathish@us.ibm.com ------------------------------ Date: Fri, 2 Nov 2001 08:31:40 -0800 From: "Jon Powell" Subject: RE: Question about IBIS model. If you know the value of the internal pull-up, you can just subtract the linear thevinen values from the IV curve of the total component. jon > -----Original Message----- > From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On > Behalf Of whiz kid > Sent: Thursday, November 01, 2001 7:27 PM > To: ibis_users@eda.org > Cc: ibis-users@eda.org > Subject: Question about IBIS model. > > > Hi Folks, > I have a open drain model with built in pullup > resistor. I need to create a similar model but with > out the internal pullup. I would really appreciate if > any of you can suggest as to how I need to approach > this. > > Thanks in Advance. > Rahul. > > __________________________________________________ > Do You Yahoo!? > Find a job, post your resume. > http://careers.yahoo.com > ------------------------------ Date: Fri, 2 Nov 2001 11:12:13 -0800 (PST) From: Syed Huq Subject: Re: requirements of ibis generation tools - --Clutter_of_Cats_185_000 Content-Type: TEXT/plain; charset=us-ascii Content-MD5: ORxZ03N4F3PeQ3v719630g== The link was removed from the IBIS site. Here is the doc. Syed > Importance: Normal > Subject: requirements of ibis generation tools > To: "ibis-users@eda.org": > From: "Sathish K Krishnamurthi" > Date: Fri, 2 Nov 2001 11:29:25 -0500 > X-MIMETrack: Serialize by Router on D01ML253/01/M/IBM(Release 5.0.8 |June 18, 2001) at 11/02/2001 11:29:29 AM > MIME-Version: 1.0 > > > Hello All, > > I am a new user of ibis generation tools. I got some information that, a > committe had been set up for defining the requirements of the ibis > generation tool( probably an enhancement of s2ibis2) and also there was > some documentation on the web regarding that. But now I am unable to get to > that documentation. I would greatly appreciate if anyone could guide me as > to where I can find the documentation defining the requirements of IBIS > generation tools. > > Thanks > > Sathish Krishnamurthi > ASIC Timing and Methodology > IBM Microelectronics, Burlington > Tel: 1-802-769-3509 Tieline : 446-3509 > Fax: 1-802-769-7509 > email: sathish@us.ibm.com > - --Clutter_of_Cats_185_000 Content-Type: TEXT/plain; name="s2ibis3_PR_1_00.txt"; charset=us-ascii; x-unix-mode=0664 Content-Description: s2ibis3_PR_1_00.txt Content-MD5: QFEwfeXJlGe8w0InGN1jWg== PROJECT REQUIREMENTS FOR SPICE-TO-IBIS TRANSLATOR ------------------------------------------------- Rev1.0 Nov19th, 1999 1.0 Scope of Project: - --------------------- Generate a user friendly IBISv3.2 complaint SPICE-to-IBIS translator that can run on multiple OS platforms and be easily upgradable to meet the requirements of future IBIS standards. This project will be identified as s2ibis3. 2.0 General Requirements: - ------------------------- 2.1 OS platform independence ---------------------------- 2.1.1 s2ibis3 must be developed for UNIX (Solaris 2.x) and NT4.0 (sp5) at a minimum. Recent stable OS versions should be used. s2ibis3 should eventually support Linux, AIX, HP among other platforms using a single Makefile. 2.1.2 A Java based development scheme or C or C++ is preferred. 2.1.3 Avoid using LEX, YACC, FLEX and BISON as there are portability issues with future upgrades. 2.2 Modular coding for future upgrade Code generation should be done with the intent in mind that future IBIS specification be easily integratable without rewriting the core code sets. 2.3 Hooks to other SPICE engines -------------------------------- 2.3.1 Contractor to test s2ibis3 on Berkeley SPICE2G.6, SPICE3 and HSPICE at a minimum. 2.3.2 s2ibis3 to have hooks to SPICE2G.6, SPICE3 and commercial SPICE simulators through configuration files. 2.3.3 The IBIS forum will co-ordinate testing of s2ibis3 on the all the simulators mentioned above. 2.4 SpiTran GUI SpiTran GUI is a Java based freeware from Cadence. The usage of the SpiTran GUI along with all the above requirements needs to be investigated. If possible, the SpiTran GUI needs to be incorporated into s2ibis3. All source code regarding SpiTran will be made available upon request. 2.5 Graphical Viewer (Optional - This is a highly desired feature and separate quote is strongly requested) A graphical viewer needs to be created that will plot out the V/I and V/T tables showing all three Typ, Min and Max tables and the [Model] name displayed on the graph. The Graphical Viewer needs to include GOOD zooming (auto and fixed) and cursor capabilities with dual cursor and x, dx and y, dy displays. Also have a feature to superimpose load lines over IV curves with selectable slope, reference voltage, and display cross points. (For reference, see s2iplt perl script from NCSU using GNUplot). 2.6 Parser integration (Optional) The IBIS parser is to be embedded into s2ibis3 and invoked automatically after the completion of the IBIS model. Output of parser can be displayed on stdout or to a machine readable file (user selectable). 2.7 Project Manager (Optional - separate quote requested) A project manager needs to be implemented that tracks all intermediate files, error messages etc. This could further assist in maintaining IBIS buffer libraries. Model developers could use this project manager to link various buffer models to make a complete IBIS component model. 3.0 Specific Requirements: - -------------------------- 3.1 Extrapolation The user will have the flexibility to extrapolate the V/I data or not to extrapolate the data to the IBIS required end points. 3.2 Sweep range The user will have the flexibility to define the sweep range to any value he/she chooses for each V/I tables irrespective of the defined [Voltage range]. Allow selection of sweeping direction and multi-section sweeps starting at 0 volts and going outwards. Add features to clock buffers with F/F to get them into a known output state. This could be a user selectable 'time delay' before sweep. These are necessary to avoid non-convergence issues on sensitive circuits and particularly useful when data is generated from measurements. 3.3 Clamp subtraction [Pullup] and [Pulldown] V/I tables for tri-stateable buffers will NOT include the [*_clamp] structures. First, disable the output structure and perform a sweep. This will capture the V/I data of the two clamp structure(if present). Then, Enable the output structre and perform a sweep one more time. This second sweep with capture the V/I data of the [Pullup] and [Pulldown](if present). For non-tri-stateable buffers, the [Pullup] and [Pulldown] V/I tables includes the [*_clamp] data. (refer to s2ibis2 problem on this) 3.4 Vdd ramping The user will have the flexibility to ramp up Vdd (or any other sensitive nodes) with SPICE supported PULSE or other methods. Example- Instead of this: VCCS2I VDDIO 0 DC 3.3 Be able to do this: VCCS2I VDDIO 0 PULSE 0.0 +3.00E+00 0.0 10E-9 10E-9 50E-6 55E-6 3.5 .OPTIONS feature For simulations with non-convergence issues, the user should be able to add various .OPTIONS parameters supported by SPICE compatible simulators to solve problem. This will allow users to change the default settings of control cards. One suggested scheme would be to implement this feature through simulator specific configuration files. 3.6 Flow Control 3.6.1If a test fails during the translation flow, a user selectable option needs to be provided to continue with the rest of the translation if the user choose to do so. A failure to generate a particular V/I table should not stop the user from continuing and generate the V/T tables or other V/I tables instead. Debug of a failed test through GUI control is recommended. 3.6.2 Use of [Iterate] feature in s2ibis2 should be implemented. If a Spice output file for the curve in question already exists, s2ibis3 will read the data from that file without re-running the simulation. In this way, you can make incremental changes to your s2ibis2 files without having to re-simulate the entire set of models. 3.7 File Naming Convention It is recommended to follow the s2ibis2 file naming convention for simulation input/output files (except for Rising/Falling waveforms). Alternate proposals for Filenaming convention are also welcome. Example - put7.spi: Pullup Typical rdn7.spi: Ramp Down Min ddx7.spi: Disabled Pulldown Max 3.8 User selectable voltage step and time step For DC and Transient analysis, the user should be able to change the voltage or time steps and other fields supported by the respective control cards. A user selectable sweep speed support is also required. 3.9 User selectable number of data points. As a minimum the tool should extract the most points from the regions where data changes rapidly and fewer points where it is linear, according to the requirements of the IBIS v3.2 specification. Optionally (separate quote requested), the number of extracted points, the axis on which the counting should be performed (x or y), and whether the routine should be count or error limited should be user selectable. User selectable number of digits after the decimal. 3.10 Choice of Process Simulation s2ibis3 should be flexible to create a TYP only IBIS model if the model developer choose to do so instead of all three TYP, MIN and MAX process corners. 3.11[C_comp] extraction (Optional-separate quote requested) The translator should simulate the value of [C_comp] by having a reserved keyword "Calc" for the value of [C_comp] By default, no simulations would then be done, as a real value would be present. 3.12 Buffer with on-die resistor or termination require a specific correction algorithm to avoid double counting. The tool should be able to handle these kids of buffers. This may also require flexible Clamp IV curve range intelligence. 3.13 Starting and ending points of Vt curves should be checked against the IV curve - load line intersection and corrected based on user response. (This should include non zero clamp curve currents for cases when the buffer has on-die resistors or terminators). 3.14 Non monotonocity of IV curves should be checked after summation of IV curves (if done by the tool). 3.15 Guardbanding feature for IV and Vt curves. (Optional-separate quote requested) 3.16 Intelligent pin list based model concatanation routine to avoid electrically identical models being repeated. (Optional-separate quote requested) 4.0 IBISv3.2 specifics: - ----------------------- 4.1 Text extensions It is desirable that the interface allow including text extensions for IBIS Version 3.2 keywords and features such as [Model Selector],[Model Spec], etc., even if they do not relate directly to the actual Spice to IBIS extraction process. These features can also include [Driver Schedule], [Add Submodel] and [Submodel] definitions as text only extensions where no direct extraction is specified. Normally these elements may be added "by construction" or may be based on a knowledgable individual decomposing a non-available, proprietary Spice model to extract partial IBIS information. 4.2.0 Spice to IBIS Extraction and full formatting is expected for the keywords listed below. However, a separate utility dedicated to Series and Series_switch extractions (as a minimum) could be proposed. The elements below do not involve V-T table extractions 4.2.1 [Series MOSFET]: At least a two terminal, [Series MOSFET] model without the associated elements at each pin (terminators, i/o models, etc.)- which are covered already covered in other sections. The extraction will support the syntax for a Series_switch and for multiple [Series MOSFET] tables for different Vds selections. Both the [On] and [Off] characteristics shall be covered, but the [Off] table may also be implemented (by default) using a high value [R Series] element and no extraction. 4.2.2 [Series Current]: At least a two terminal [Series Current] without the associated elements at each pin (terminators, i/o models, etc.) - which are covered in other sections. 5.0 Documentation: - ------------------ 5.1 README File ---------------------- A text README file describing the contents of the software package and installation instructions must be provided. 5.1.1 Installation Guide The procedure for installing the software on each supported platform must be described. The instructions should assume that the files have been unpacked from an archive file, with a file hierarchy exactly as provided by the developer. It is also recommended to provide a decent installer/uninstaller software if it is not a simple installation, such as unzipping/copying all files into a directory. Installation software should be flexible and allow for user selectable location, etc... 5.1.2 Directory Tree The README file should describe the contents of each sub-directory within the directory tree structure. Detailed explanation to be provided if required. (see /doc/README) Suggested sub-directory structure could be: /bin /doc /examples /src /plot etc (see /s2ibis2 dir structure) 5.2 User Guide -------------- A user guide document describing how to use s2ibis3 must be provided. The source document (word processor format) of the user guide along with a pdf format is required. This user guide will be the first documentation a user may consult to understand the usage of the translator and the steps required to run the translator. The user guide must include the following items. 5.2.1 Contents A table of contents must be included. 5.2.2 Reference The format, meaning, usage, and default values for the control file accepted by the program. Also the program invocation and usage of all command line parameters, if any. The data file format generated by the simulators should also be explained including how they are parsed, so that one could "fake" them from other sources. A definition for how simulation output files are searched and processed so that someone could "fake" data from other non-supported simulators and/or measurements. 5.2.3 Error/Warning messages A detailed explanation of each Error/Warning message that may be issued by the program needs to be described sufficiently so as to enable the user to take corrective action. The Error/Warning messages themselves should be as clear and descriptive as is practical. 5.2.4 Algorithms A detailed description of the algorithms used to generate the V/I and V/T tables, and other calculated values needs to be included as an appendix. (see /doc/curves.txt). 5.2.5 Tutorial (quoted separately) Optionally, a tutorial description of step by step program operation may be provided. This should reference supplied example data, and should explain how to obtain required data. Examples of debugging problems should be included, also. 5.3 Software Coding Standards and Documentation ----------------------------------------------- 5.3.1 Code explanation Every function needs to have comments describing what it does. All variables within a function needs to be defined as to what it contains. Additional comments should be provided for any loops and other areas of the code. (see src/s2ianlyz.c) 5.3.2 Flow Chart A flow chart of the project is suggested that describes all the paths the software takes if it encounters an error or how it searches through each program to generate the final IBIS model. 5.3.3 Code Maintenance The code should be easily maintainable by any volunteer from The IBIS forum. This may require minor changes, compilation of code for specific platform. Minor bug fixes may be required. Bug fixes and code maintenance will be coordinated with the software contractor. (see /src/sources and src/tags files) 6.0 Acceptance Criteria: - ------------------------ 6.1 The software design must meet or exceed the functional requirements above. 6.2 Successful operation must be demonstrated by converting a test suite of SPICE files to IBIS. The test suite will consist of not more than 10 SPICE files, to be supplied by the s2ibis3 subcommittee of the IBIS committee. Each SPICE file will be accompanied by all instructions needed for simulation, including identification of which simulator(s)the SPICE file will run on. All SPICE files will be compatible with one of the simulators specified in 2.3.1. The resulting IBIS files are to be checked using ibischk3. The requirement is a clean check, with no syntax warnings or errors. It is recommended that test be performed on 6.3 The software and documentation will be reviewed by members of the s2ibis3 subcommittee of the IBIS committee. Additional SPICE conversion testing may be performed by the s2ibis3 subcommittee. Resolution of issues will be coordinated with the developer. An understanding of the usage/features/limitations of NCSU's s2ibis2 is preferred. An itemized quote is also welcome. This may allow modification to the project requirement if the initial cost exceeds budgetary constraints. Regards, IBIS sub-committee Michael Cohen(Chairperson) IBM Personal Systems Group Syed Huq Cisco Systems Christian Klein Fairchild Semiconductors Mike LaBonte Cadence Design Systems Arpad Muranyi Intel Corporation Bob Ross Mentor Graphics Mohamed Nasef Mentor Graphics Jerry Hayes IBM Sherif Hammad Mentor Graphics ============================================================================ - --Clutter_of_Cats_185_000-- ------------------------------ Date: Mon, 5 Nov 2001 12:31:09 -0500 From: "GUILLORY,DOUG (HP-Boise,ex1)" Subject: Meaning of time in IBIS I am having problems understanding what time=0 means in IBIS models. Can anybody, please, tell me how time is referenced? I don't see an explicit statement of what the reference is and it seems to vary from one model supplier to another. Thanks. ------------------------------ Date: Mon, 5 Nov 2001 12:54:14 -0600 From: "Gregory R Edlund" Subject: Re: Meaning of time in IBIS Doug, Just like Einstein said, time is relative. (Sorry, you have to forgive an old physics geek his "warped" sense of humor.) Since behavioral models concern themselves only with the off-chip node of an I/O circuit, you can't really talk about the delay _through_ a behavioral model like you can in a SPICE model. You need to talk about the time that the I/O crosses a reference voltage (Vmeas) when it drives a reference load (Cref, Rref, Vref). This is the same load that's called out in the component datasheet. Behavioral simulators report net delays relative to this crossing point. They throw out the whole notion of T=0 from the VT tables. Therefore, it's not impossible to have a negative net delay if your actual load is lighter than the reference load. But watch out - most IBIS datasheets don't even have these parameters defined. If you're looking for a nice checklist of things to look out for when you get a new IBIS datasheet from a vendor, have a look at: http://www.vhdl.org/pub/ibis/accuracy/checklist.txt Greg Edlund Electronic Packaging & Integration IBM Server Technology Development 3605 Hwy. 52 N, Dept. HDC Rochester, MN 55901 gedlund@us.ibm.com "GUILLORY,DOUG (HP-Boise,ex1) To: "'ibis-users@eda.org'" " cc: Sent by: owner-ibis-use rs@eda.org 11/05/01 11:31 AM I am having problems understanding what time=0 means in IBIS models. Can anybody, please, tell me how time is referenced? I don't see an explicit statement of what the reference is and it seems to vary from one model supplier to another. Thanks. ------------------------------ Date: Mon, 5 Nov 2001 16:24:23 -0800 From: "Jon Powell" Subject: RE: Meaning of time in IBIS If you are talking about the RISING and FALLING curves, the time 0 is meant only as an internal reference in that all of the RISING curves (for a given driver) have the same 0 time. All of the FALLING curves (for a given driver) have the same 0 time. what that time is in reference to doesn't matter as long as it is the same for the curves mentioned. This is a necessary condition to be able to properly calculate Rise Time Control properties of drivers. There have been several papers given on this at users groups and IBIS meetings, one may be in the archives. Jon Powell > -----Original Message----- > From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On > Behalf Of GUILLORY,DOUG (HP-Boise,ex1) > Sent: Monday, November 05, 2001 9:31 AM > To: 'ibis-users@eda.org' > Subject: Meaning of time in IBIS > > > I am having problems understanding what time=0 means in IBIS > models. Can > anybody, please, tell me how time is referenced? I don't see > an explicit > statement of what the reference is and it seems to vary from one model > supplier to another. Thanks. > ------------------------------ Date: Thu, 08 Nov 2001 10:50:32 +0100 From: Alexander Loehr Subject: Input model with Pullup-/Pulldown-Reference Hi! I've got an IBIS input model without a [Voltage Range]. Take a look at the IBIS Specification 3.2: [Voltage Range] -> Other Notes: If the [Voltage Range] keyword is not present, then all four of the keywords described below must be present: [Pullup Reference], [Pulldown Reference], [POWER Clamp Reference], and [GND Clamp Reference]. If the [Voltage Range] is present, the other keywords are optional and may or may not be used as required. It is legal (although redundant) for an optional keyword to specify the same voltage as specified by the [Voltage Range] keyword. But it is not possible that an "input" model has [Pullup Reference] and [Pulldown Reference]. Is the IBIS specification correct? Thanks, Alex. - -- Alexander Loehr ZUKEN GmbH Phone: +49-(0)5251-150622 Senior Software Vattmannstrasse 3 Fax: +49-(0)5251-150700 Engineer D-33100 Paderborn eMail: alex@pad.zuken.de PGP key: http://mail.pad.zuken.de/~alex/aloehr.asc ------------------------------ Date: Thu, 8 Nov 2001 08:43:35 -0800 From: "Muranyi, Arpad" Subject: RE: Input model with Pullup-/Pulldown-Reference Alex, Your observation is correct, strictly speaking it doesn't make sense for an input model type. I don't remember whether we did it this way because we wanted to avoid the complications of these ifs and buts, or whether we didn't think about this case. However, the reason these keywords were introduced was to allow independent referencing of the oullup and power clamp, or pulldown and gnd clamp IV curves. When you have an input buffer only, you won't really need that capability, so you should be able to just use the [Voltage Range] keyword. The only problem is that this keyword assumes that your gnd clamp is at zero volts. If you had a gnd clamp at -2V you would have to use the reference keyword, and according to the rules, all of them, even if there are no pullups and pulldowns. Even though this should not effect the simulations, it is misleading to the reader or maker of a model, and should be cleaned up in the spec. Thanks, Arpad Muranyi Intel Corporation =================================================================== - -----Original Message----- From: Alexander Loehr [mailto:alex@pad.zuken.de] Sent: Thursday, November 08, 2001 1:51 AM To: ibis-users@eda.org Subject: Input model with Pullup-/Pulldown-Reference Hi! I've got an IBIS input model without a [Voltage Range]. Take a look at the IBIS Specification 3.2: [Voltage Range] -> Other Notes: If the [Voltage Range] keyword is not present, then all four of the keywords described below must be present: [Pullup Reference], [Pulldown Reference], [POWER Clamp Reference], and [GND Clamp Reference]. If the [Voltage Range] is present, the other keywords are optional and may or may not be used as required. It is legal (although redundant) for an optional keyword to specify the same voltage as specified by the [Voltage Range] keyword. But it is not possible that an "input" model has [Pullup Reference] and [Pulldown Reference]. Is the IBIS specification correct? Thanks, Alex. - -- Alexander Loehr ZUKEN GmbH Phone: +49-(0)5251-150622 Senior Software Vattmannstrasse 3 Fax: +49-(0)5251-150700 Engineer D-33100 Paderborn eMail: alex@pad.zuken.de PGP key: http://mail.pad.zuken.de/~alex/aloehr.asc ------------------------------ Date: Fri, 9 Nov 2001 08:40:30 -0800 From: "Peters, Stephen" Subject: Agenda, IBIS Open Forum Meeting 11/16 IBIS Open Forum Meeting Agenda for 11/16/01 Bridge Number Reservation # Passcode 1-877-299-1938 None 8906706 1-617-801-9666 (International Dial-In) All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the Reservation Number and Passcode. 8:00 Check-In, Intros, Announcements Peters - Intros of New IBIS Participants, Meeting Quorum Peters - Membership Update and Treasurers Report Fleming/Ross - Review of Previous Meeting's Minutes (and ARs) Peters - Miscellany/Announcements All - Press & Web Page Updates Huq, All - New Models Available, Library Update Leventhal, All - Opens for New Issues All 8:15 Administrative and Project Discussions International/External Progress - pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits (IMIC) Peters - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters - JEDEC JC-16 Modeling and Testing Sessions - T10, Project 1414-DT - SCSI Signal Modeling Barnes s2ibis3 Meeting Report Peters Future Summit Meeting Plans Peters/Ross - DesignCon2002 - Date2002 - Future JEDEC/IBIS Meeting IBIS Model Review Committee Ross Majordomo Update Angulo New Administrative Issues All 8:45 Technical Discussion Connector Proposal Report Peters/Ross IBIS Futures Group Report Peters/Green BIRD73.3 - Fall Back Submodel Ross ibischk3 Status Ross - BUG62 - Not All Non-Monotonic Points Reported Green/Wang/Ross - BUG63 - Some BUG47 Reported Waveform Percentages Ross Wrong XML for IBIS Ross New Technical Issues All - Use of [Pullup Reference] and [Pulldown Reference] in input models 9:50 Wrap Up and Next Meetings Plans Peters 9:55 Sign Off ------------------------------ Date: Wed, 14 Nov 2001 10:06:44 -0600 From: Gang Huo Subject: Timing parameters Hello all, I am wondering what can be put in these parameters (Vref, Rref, Cref and Vmeas) if there is no spec. or the spec. does not specifying the delay and/or output switching time? And if there is multi-cases in the spec.? For example, a device's spec. specified/characterized the delay for a capacitor load to ground ranging from 15pF to 100pF with 4 cases of 15pF, 30pF, 66pF and 100pF. Thanks. Huo,Gang ------------------------------ Date: Wed, 14 Nov 2001 10:02:54 -0800 From: "Dagostino, Tom" Subject: RE: Timing parameters If there is no spec why are you considering using the part? How will you know if the part will work in your design? Very few parts spec an output switching time. If there are multiple timing specs for different loads then pick the load that best matches the circuit you have and put that load into the IBIS model. Then use the timing for that load in your analysis. Tom Dagostino Modeling Manager Mentor Graphics Corp. SAE tom_dagostino@mentor.com 503-685-1613 - -----Original Message----- From: Gang Huo [mailto:ghuo@lsil.com] Sent: Wednesday, November 14, 2001 8:07 AM To: ibis-users@eda.org Subject: Timing parameters Hello all, I am wondering what can be put in these parameters (Vref, Rref, Cref and Vmeas) if there is no spec. or the spec. does not specifying the delay and/or output switching time? And if there is multi-cases in the spec.? For example, a device's spec. specified/characterized the delay for a capacitor load to ground ranging from 15pF to 100pF with 4 cases of 15pF, 30pF, 66pF and 100pF. Thanks. Huo,Gang ------------------------------ Date: Wed, 14 Nov 2001 12:22:17 -0600 From: Gang Huo Subject: Re: Timing parameters The problem is the I/O is a very Bi-direction I/O whose spec. has only DC parameters. But the customers want to use some tools to check the timing which need these parameters. Under these conditions, what should i put in there or just leave it empty? On the second case, besides these timing parameters, what else need to change in the model to reflect the different load? If no, then there will be models that are identical except these parameters, will this cause confusion for the simulators? I read somewhere that certain simulator will use these values for time analysis. Can someone tell me how these simulators use these values for that purpose? For example, if i have two identical models except in one model Cref=10pF,Rref=0,Vref=0, and in the other Cref=50pF, Rref=0 and Vref=0, will the simulator see these two models the same, or they will have different timing "properties"? Thanks. Huo,Gang "Dagostino, Tom" wrote: > If there is no spec why are you considering using the part? How will you know if the part will work in your design? Very few parts spec an output switching time. > > If there are multiple timing specs for different loads then pick the load that best matches the circuit you have and put that load into the IBIS model. Then use the timing for that load in your analysis. > > Tom Dagostino > Modeling Manager > Mentor Graphics Corp. > SAE > tom_dagostino@mentor.com > 503-685-1613 > > -----Original Message----- > From: Gang Huo [mailto:ghuo@lsil.com] > Sent: Wednesday, November 14, 2001 8:07 AM > To: ibis-users@eda.org > Subject: Timing parameters > > Hello all, > > I am wondering what can be put in these parameters (Vref, Rref, Cref and > Vmeas) if there is no spec. or the spec. does not specifying the delay > and/or output switching time? And if there is multi-cases in the spec.? > For example, a device's spec. specified/characterized the delay for a > capacitor load to ground ranging from 15pF to 100pF with 4 cases of > 15pF, 30pF, 66pF and 100pF. > > Thanks. > > Huo,Gang ------------------------------ Date: Wed, 14 Nov 2001 11:38:18 -0800 (PST) From: Syed Huq Subject: RE: Timing parameters You could also use the [Model selector] keyword and enter all the various models with it's test load and let the user select which ones to use.. Syed > From: "Dagostino, Tom" > To: "'Gang Huo'" , ibis-users@eda.org > Subject: RE: Timing parameters > Date: Wed, 14 Nov 2001 10:02:54 -0800 > MIME-Version: 1.0 > > If there is no spec why are you considering using the part? How will you know if the part will work in your design? Very few parts spec an output switching time. > > If there are multiple timing specs for different loads then pick the load that best matches the circuit you have and put that load into the IBIS model. Then use the timing for that load in your analysis. > > Tom Dagostino > Modeling Manager > Mentor Graphics Corp. > SAE > tom_dagostino@mentor.com > 503-685-1613 > > > -----Original Message----- > From: Gang Huo [mailto:ghuo@lsil.com] > Sent: Wednesday, November 14, 2001 8:07 AM > To: ibis-users@eda.org > Subject: Timing parameters > > > Hello all, > > I am wondering what can be put in these parameters (Vref, Rref, Cref and > Vmeas) if there is no spec. or the spec. does not specifying the delay > and/or output switching time? And if there is multi-cases in the spec.? > For example, a device's spec. specified/characterized the delay for a > capacitor load to ground ranging from 15pF to 100pF with 4 cases of > 15pF, 30pF, 66pF and 100pF. > > Thanks. > > Huo,Gang ------------------------------ Date: Wed, 14 Nov 2001 12:14:32 -0800 From: Lynne Green Subject: Re: Timing parameters Hello, Gang, Every EDA vendor provides "time-of-flight" results for delay time for signal to travel between the driver and a receiver. The data sheet should contain a mention of the voltage at which delay was measured (so you can add internal delay to time-of-flight" delay); this is the value of VMEAS. (RREF and VREF are not used for a capacitor test load.) Every EDA vendor has a different way of setting their time=0 reference, since the reference time=0 is not specified in the IBIS standard. The IBIS standard also does not specify the time=0 reference for building models, so any arbitrary (positive or negative) time offset could be added to a model without changing its "correctness" according to the standard. What distinguishes vendors is how they help you correct for these time offsets to calculate the internal buffer delay. Many tools, including Cadence's SPECCTRAQuest, help you correct for time offsets. You can also do this using a spreadsheet. - - Lynne Green At 12:22 PM 11/14/2001 -0600, you wrote: >The problem is the I/O is a very Bi-direction I/O whose spec. has only DC >parameters. But the customers want to use some tools to check the timing >which need these parameters. Under these conditions, what >should i put in there or just leave it empty? > >On the second case, besides these timing parameters, what else need to >change in the model to reflect the different load? If no, then there will >be models that are identical except these parameters, will >this cause confusion for the simulators? I read somewhere that certain >simulator will use these values for time analysis. Can someone tell me how >these simulators use these values for that purpose? For >example, if i have two identical models except in one model >Cref=10pF,Rref=0,Vref=0, and in the other Cref=50pF, Rref=0 and Vref=0, >will the simulator see these two models the same, or they will have >different timing "properties"? > >Thanks. > >Huo,Gang > >"Dagostino, Tom" wrote: > > > If there is no spec why are you considering using the part? How will > you know if the part will work in your design? Very few parts spec an > output switching time. > > > > If there are multiple timing specs for different loads then pick the > load that best matches the circuit you have and put that load into the > IBIS model. Then use the timing for that load in your analysis. > > > > Tom Dagostino > > Modeling Manager > > Mentor Graphics Corp. > > SAE > > tom_dagostino@mentor.com > > 503-685-1613 > > > > -----Original Message----- > > From: Gang Huo [mailto:ghuo@lsil.com] > > Sent: Wednesday, November 14, 2001 8:07 AM > > To: ibis-users@eda.org > > Subject: Timing parameters > > > > Hello all, > > > > I am wondering what can be put in these parameters (Vref, Rref, Cref and > > Vmeas) if there is no spec. or the spec. does not specifying the delay > > and/or output switching time? And if there is multi-cases in the spec.? > > For example, a device's spec. specified/characterized the delay for a > > capacitor load to ground ranging from 15pF to 100pF with 4 cases of > > 15pF, 30pF, 66pF and 100pF. > > > > Thanks. > > > > Huo,Gang ------------------------------ Date: Wed, 21 Nov 2001 17:50:17 -0000 From: "sundip-patel" Subject: IBIS Model This is a multi-part message in MIME format. - ------=_NextPart_000_000A_01C172B4.FAE86AE0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi, I have created an IBIS model for a testpad in the design called EPAD47. = I have imported the model into ICX and can see it as a part when i open = up 'DESIGN DATA', but when i go into the design and click on any test = pad it is still using a technology model called default_in from = default.tch. Only when i go and insert the pin model for every testpad does it use = the EPAD47 model (EPAD47_IN - pin model). Could you tell me what i am doing wrong?? Sundip - ------=_NextPart_000_000A_01C172B4.FAE86AE0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Hi,
 
I have created an IBIS model for a = testpad in the=20 design called EPAD47. I have imported the model into ICX and can see it = as a=20 part when i open up 'DESIGN DATA', but when i go into the design and = click on=20 any test pad it is still using a technology model called = default_in=20 from default.tch.
 
Only when i go and insert the pin model = for every=20 testpad does it use the EPAD47 model (EPAD47_IN - pin = model).
 
Could you tell me what i am doing=20 wrong??
 
Sundip
- ------=_NextPart_000_000A_01C172B4.FAE86AE0-- ------------------------------ Date: Wed, 21 Nov 2001 14:42:24 -0800 From: Bob Ross Subject: IBIS - New ibischk3 executables To All: New execuables for ibischk3 Version 3.2.8 have been uploaded under: http:://www.eda.org/pub/ibis/ibischk3/ Thanks to Matthew Flora for the windows executable and Guy de Burgh for the Unix executables. The linux executable should be uploaded next week. This version fixes BUG48-56 and BUG59. Bob Ross Mentor Graphics ------------------------------ Date: Wed, 21 Nov 2001 16:22:28 -0800 From: "Ross, Bob" Subject: Re: IBIS Model Hello Sundip: You need to contact Mentor Graphics directly on this problem. We generally do not discuss vendor-specific issues on this reflector under EIA rules. Or someone from the vendor can contact you directly, off-line on this issue. Bob Ross Mentor Graphics sundip-patel wrote: > > Hi, > > I have created an IBIS model for a testpad in the design called EPAD47. I have > imported the model into ICX and can see it as a part when i open up 'DESIGN > DATA', but when i go into the design and click on any test pad it is still > using a technology model called default_in from default.tch. > > Only when i go and insert the pin model for every testpad does it use the > EPAD47 model (EPAD47_IN - pin model). > > Could you tell me what i am doing wrong?? > > Sundip ------------------------------ Date: Fri, 23 Nov 2001 12:35:08 +0530 From: Ramesh Karmungi Subject: Execution of s2ibis2 - --Boundary_(ID_e8ZegSVSrPnV6QH439UGLA) Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7BIT Hello, I am new user of IBIS tools. I have downloaded Spitran to develop ibis models. Spitran gives me .s2i file. This was used as input file to run s2ibis2.exe. However, am unable to run s2ibis2. Following lines will appear on screen and stops execution of s2ibis2.. s2ibis2: Analyzing component MCM Driver . s2ibis2: Starting HSpice job with input putout.spi. failure!!!!! I have noticed it creates a .spi file in the process. I work on PC with windows 2000 or windows NT system. I have Avanti HSPICE 99.4. Could anyone help me out to sort out the problem. Thanks and Regards with anticipation Ramesh K - --Boundary_(ID_e8ZegSVSrPnV6QH439UGLA) Content-type: text/html; charset=us-ascii Content-transfer-encoding: 7BIT Hello,

I am new user of  IBIS tools. I have downloaded Spitran to develop ibis models. Spitran gives me .s2i file. This was used as input file to run s2ibis2.exe.  However, am unable to run s2ibis2. Following lines will appear on screen and stops execution of s2ibis2..

s2ibis2: Analyzing component MCM Driver .
s2ibis2: Starting HSpice job with input putout.spi.
failure!!!!!

I have noticed it creates a .spi file in the process.

I work on PC with windows 2000 or windows NT system. I have Avanti HSPICE 99.4.  
Could anyone help me out to sort out the problem.

Thanks and Regards with anticipation

Ramesh K - --Boundary_(ID_e8ZegSVSrPnV6QH439UGLA)-- ------------------------------ Date: Fri, 23 Nov 2001 00:35:44 -0800 From: Abdulrahman A Rafiq Subject: Re: Execution of s2ibis2 - --=====================_141694926==_.ALT Content-Type: text/plain; charset="us-ascii"; format=flowed Ramesh, Is there an output file generated ? Can you open it in your basic text editor and see what error message its flaging ? Also see if you can open the .spi file and see if there are any messages in there ? Abbey A. Rafiq At 12:35 PM 11/23/2001 +0530, Ramesh Karmungi wrote: >Hello, > >I am new user of IBIS tools. I have downloaded Spitran to develop ibis >models. Spitran gives me .s2i file. This was used as input file to run >s2ibis2.exe. However, am unable to run s2ibis2. Following lines will >appear on screen and stops execution of s2ibis2.. > >s2ibis2: Analyzing component MCM Driver . >s2ibis2: Starting HSpice job with input putout.spi. >failure!!!!! > >I have noticed it creates a .spi file in the process. > >I work on PC with windows 2000 or windows NT system. I have Avanti HSPICE >99.4. >Could anyone help me out to sort out the problem. > >Thanks and Regards with anticipation > >Ramesh K - --=====================_141694926==_.ALT Content-Type: text/html; charset="us-ascii" Ramesh,

Is there an output file generated ? Can you open it in your basic text editor and see what error message its flaging ?
Also see if you can open the .spi file and see if there are any messages in there ?

Abbey A. Rafiq




At 12:35 PM 11/23/2001 +0530, Ramesh Karmungi wrote:

Hello,

I am new user of  IBIS tools. I have downloaded Spitran to develop ibis models. Spitran gives me .s2i file. This was used as input file to run s2ibis2.exe.  However, am unable to run s2ibis2. Following lines will appear on screen and stops execution of s2ibis2..

s2ibis2: Analyzing component MCM Driver .
s2ibis2: Starting HSpice job with input putout.spi.
failure!!!!!

I have noticed it creates a .spi file in the process.

I work on PC with windows 2000 or windows NT system. I have Avanti HSPICE 99.4.  
Could anyone help me out to sort out the problem.

Thanks and Regards with anticipation

Ramesh K
- --=====================_141694926==_.ALT-- ------------------------------ Date: Sat, 24 Nov 2001 12:36:33 -0800 From: "Abdulrahman A. Rafiq" Subject: Re: Execution of s2ibis2 This is a multi-part message in MIME format. - --------------088FEF9DC7053EC8BD2D4179 Content-Type: multipart/alternative; boundary="------------169D5D8C0FC68DFEBADEAFE1" - --------------169D5D8C0FC68DFEBADEAFE1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Ramesh Karmungi wrote: > Hello Abbey, > > Thanks for quick reply. Outfile is not generated. It has generated 10 > (.spi) files, whereas in putout.spi netlist and model parameters are > given and no error message. However, in other .spi files only header > without netlist. > I am herewith attaching tristate.s2i and putout.spi files. > when i have run the tristate.s2i as downloaded (it has spice type: > Spectra), it runs s2ibis2 without error and creates .ibs but without > any I/V or V/T data. > I would be thankful if you could give me suggestions. > > Thanks and Regards > Ramesh > > Abdulrahman A Rafiq wrote: > >> Ramesh, >> >> Is there an output file generated ? Can you open it in your basic >> text editor and see what error message its flaging ? >> Also see if you can open the .spi file and see if there are any >> messages in there ? >> >> Abbey A. Rafiq >> >> >> >> >> At 12:35 PM 11/23/2001 +0530, Ramesh Karmungi wrote: >> >> > Hello, >> > >> > I am new user of IBIS tools. I have downloaded Spitran to develop >> > ibis models. Spitran gives me .s2i file. This was used as input >> > file to run s2ibis2.exe. However, am unable to run s2ibis2. >> > Following lines will appear on screen and stops execution of >> > s2ibis2.. >> > >> > s2ibis2: Analyzing component MCM Driver . >> > s2ibis2: Starting HSpice job with input putout.spi. >> > failure!!!!! >> > >> > I have noticed it creates a .spi file in the process. >> > >> > I work on PC with windows 2000 or windows NT system. I have Avanti >> > HSPICE 99.4. >> > Could anyone help me out to sort out the problem. >> > >> > Thanks and Regards with anticipation >> > >> > Ramesh K >> > ---------------------------------------------------------------- > * Typ pullup curve for model tristate_driver > * > * Spice deck created by s2ibis v 1.1 > * North Carolina State University > * > minva vdd enable nena vdd pfet w=3.6e-06 l=6e-07 ad=2.1015e-11 as=5.4e-12 > +pd=2.355e-05 ps=6.6e-06 > minvb gnd enable nena gnd nfet w=1.8e-06 l=6e-07 ad=1.107e-11 as=2.7e-12 > +pd=1.35e-05 ps=4.8e-06 > > mx33 n5 enable vdd vdd pfet w=3.84e-05 l=6e-07 ad=5.76e-11 as=5.76e-11 > +pd=4.14e-05 ps=4.14e-05 > mx24 n5 in n2 vdd pfet w=3.6e-06 l=6e-07 ad=2.1015e-11 as=5.4e-12 pd=2.355e-05 > +ps=6.6e-06 > mx25 n3 n2 n5 vdd pfet w=1.41e-05 l=6e-07 ad=2.115e-11 as=2.1015e-11 > +pd=1.71e-05 ps=2.355e-05 > mx27 n5 n3 n4 vdd pfet w=3.21e-05 l=6e-07 ad=9.3915e-11 as=2.889e-11 > +pd=1.0125e-05 ps=1.8e-06 > mx26 n4 n3 n5 vdd pfet w=3.21e-05 l=6e-07 ad=2.889e-11 as=4.815e-11 pd=1.8e-06 > +ps=3.51e-05 > mx32 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=1.0116e-10 as=7.587e-11 > +pd=4.695e-05 ps=3.6e-06 > mx31 n5 n4 out vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11 > +pd=3.6e-06 ps=3.6e-06 > mx30 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11 > +pd=3.6e-06 ps=3.6e-06 > mx29 n5 n4 out vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11 > +pd=3.6e-06 ps=3.6e-06 > mx28 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=9.3915e-11 > +pd=3.6e-06 ps=1.0125e-05 > mx14 n7 in n2 gnd nfet w=1.8e-06 l=6e-07 ad=1.107e-11 as=2.7e-12 pd=1.35e-05 > +ps=4.8e-06 > mx23 gnd nena n7 gnd nfet w=3.6e-05 l=6e-07 ad=5.4e-11 as=5.4e-11 pd=3.9e-05 > +ps=3.9e-05 > mx15 n3 n2 n7 gnd nfet w=7.2e-06 l=6e-07 ad=1.08e-11 as=1.107e-11 pd=1.02e-05 > +ps=1.35e-05 > mx17 n7 n3 n4 gnd nfet w=1.62e-05 l=6e-07 ad=4.725e-11 as=1.458e-11 > +pd=7.575e-06 ps=1.8e-06 > mx16 n4 n3 n7 gnd nfet w=1.62e-05 l=6e-07 ad=1.458e-11 as=2.43e-11 pd=1.8e-06 > +ps=1.92e-05 > mx22 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=5.076e-11 as=3.807e-11 > +pd=2.595e-05 ps=3.6e-06 > mx21 n7 n4 out gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11 > +pd=3.6e-06 ps=3.6e-06 > mx20 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11 > +pd=3.6e-06 ps=3.6e-06 > mx19 n7 n4 out gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11 > +pd=3.6e-06 ps=3.6e-06 > mx18 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=4.725e-11 > +pd=3.6e-06 ps=7.575e-06 > * N56S SPICE BSIM1 (Berkeley Level 4; HSPICE Level 13) PARAMETERS > * Modified to use regular SPICE (not HSPICE) names for Spectre > * > *NMOS PARAMETERS > * > .MODEL nfet NMOS level=4 > +vfb0=-6.67767E-01 > +lvfb=-9.88313E-03 > +wvfb=-3.29367E-02 > +phi0=8.60647E-01 > +lphi=0.00000E+00 > +wphi=0.00000E+00 > +k1=8.17935E-01 > +lk1=-4.65708E-02 > +wk1=4.75791E-02 > +k2=4.25774E-02 > +lk2=3.52629E-02 > +wk2=-2.77046E-03 > +eta0=-6.14649E-05 > +leta=1.89078E-02 > +weta=-1.18479E-02 > +muz=5.83829E+02 > +dl0=1.40291E-001 > +dw0=5.07562E-001 > +u00=3.29586E-01 > +lu0=9.77520E-02 > +wu0=-9.32319E-02 > +u1=1.99382E-02 > +lu1=3.61973E-02 > +wu1=-2.86830E-03 > +x2m=1.29121E+01 > +lx2m=-8.28086E+00 > +wx2m=6.90864E+00 > +x2e=7.54028E-04 > +lx2e=-3.43366E-03 > +wx2e=5.18763E-04 > +x3e=2.37991E-04 > +lx3e=-1.61033E-03 > +wx3e=-5.39861E-03 > +x2u0=-6.35761E-03 > +lx2u0=-3.86200E-03 > +wx2u0=5.33022E-03 > +x2u1=-5.68012E-04 > +lx2u1=1.22523E-03 > +wx2u1=2.85097E-04 > +mus=6.84165E+02 > +lms=-2.54285E+01 > +wms=9.21339E-01 > +x2ms=4.89160E+00 > +lx2ms=-1.90933E+00 > +wx2ms=7.94142E+00 > +x3ms=4.83048E+00 > +lx3ms=4.02423E+00 > +wx3ms=-5.33716E+00 > +x3u1=7.20765E-03 > +lx3u1=-1.37194E-04 > +wx3u1=-3.70674E-03 > +tox=1.00000E-008 > +tempm=2.70000E+01 > +vddm=5.00000E+00 > +cgdom=3.63E-010 > +cgsom=3.63E-010 > +cgbom=4.52505E-010 > +xpart=1.00000E+000 > +n0=1.00000E+000 > +ln0=0.00000E+000 > +wn0=0.00000E+000 > +nb0=0.00000E+000 > +lnb=0.00000E+000 > +wnb=0.00000E+000 > +nd0=0.00000E+000 > +lnd=0.00000E+000 > +wnd=0.00000E+000 > * > *N+ diffusion:: > * > +rsh=2.4 > +cj=7.732100e-04 > +cjw=2.900000e-10 > +ijs=1e-08 > +pj=0.8 > +pjw=0.8 > +mj=1.10106 > +mjw=0.26 > +wdf=0 > * > *PMOS PARAMETERS > * > .MODEL pfet PMOS level=4 > +vfb0=-6.59693E-02 > +lvfb=-1.78327E-02 > +wvfb=-2.45473E-03 > +phi0=7.68179E-01 > +lphi=0.00000E+00 > +wphi=0.00000E+00 > +k1=2.85648E-01 > +lk1=-1.64579E-02 > +wk1=3.08917E-02 > +k2=-6.62532E-02 > +lk2=2.49518E-02 > +wk2=4.62778E-04 > +eta0=-7.90844E-03 > +leta=1.92294E-02 > +weta=-2.34646E-03 > +muz=1.41704E+02 > +dl0=2.14000E-001 > +dw0=5.34406E-001 > +u00=1.95407E-01 > +lu0=6.22059E-02 > +wu0=-5.94668E-02 > +u1=8.56390E-03 > +lu1=1.39477E-02 > +wu1=7.65802E-04 > +x2m=6.79470E+00 > +lx2m=-1.43654E+00 > +wx2m=6.56475E-01 > +x2e=1.08483E-04 > +lx2e=-1.24539E-03 > +wx2e=9.77240E-05 > +x3e=4.33468E-04 > +lx3e=1.42453E-04 > +wx3e=-1.71650E-03 > +x2u0=8.73535E-03 > +lx2u0=-1.31646E-03 > +wx2u0=4.78072E-04 > +x2u1=3.06834E-04 > +lx2u1=4.41194E-04 > +wx2u1=3.49198E-04 > +mus=1.47746E+02 > +lms=1.78644E+01 > +wms=1.24739E-01 > +x2ms=6.09155E+00 > +lx2ms=-1.61404E-01 > +wx2ms=1.24507E+00 > +x3ms=-3.18656E-01 > +lx3ms=2.79732E+00 > +wx3ms=1.71058E+00 > +x3u1=-1.22826E-03 > +lx3u1=1.06181E-04 > +wx3u1=1.07711E-03 > +tox=1.00000E-008 > +tempm=2.70000E+01 > +vddm=5.00000E+00 > +cgdom=5.540E-010 > +cgsom=5.54E-010 > +cgbom=4.67045E-010 > +xpart=1.00000E+000 > +n0=1.00000E+000 > +ln0=0.00000E+000 > +wn0=0.00000E+000 > +nb0=0.00000E+000 > +lnb=0.00000E+000 > +wnb=0.00000E+000 > +nd0=0.00000E+000 > +lnd=0.00000E+000 > +wnd=0.00000E+000 > * > *P+ diffusion:: > * > +rsh=2.1 > +cj=9.319100e-04 > +cjw=1.563700e-10 > +ijs=1e-08 > +pj=0.85 > +pjw=0.85 > +mj=0.487073 > +mjw=0.47848 > +wdf=0 > > * simple diode model > .model clamp d vj=0.7 rs=100 > VOUTS2I out 0 DC 0 > VCCS2I vdd 0 DC 3.3 > VGNDS2I gnd 0 DC 0 > VENAS2I enable 0 DC 0 > VINS2I in 0 DC 3.3 > .TEMP 27 > .OPTIONS INGOLD=2 > .DC VOUTS2I -3.3 6.6 0.1 > .PRINT DC I(VOUTS2I) > .END > > ---------------------------------------------------------------- > * > * simple inverter > * > minva vdd enable nena vdd pfet w=3.6e-06 l=6e-07 ad=2.1015e-11 as=5.4e-12 > +pd=2.355e-05 ps=6.6e-06 > minvb gnd enable nena gnd nfet w=1.8e-06 l=6e-07 ad=1.107e-11 as=2.7e-12 > +pd=1.35e-05 ps=4.8e-06 > > * > * tristate buffer model > * > mx33 n5 enable vdd vdd pfet w=3.84e-05 l=6e-07 ad=5.76e-11 as=5.76e-11 > +pd=4.14e-05 ps=4.14e-05 > mx24 n5 in n2 vdd pfet w=3.6e-06 l=6e-07 ad=2.1015e-11 as=5.4e-12 pd=2.355e-05 > +ps=6.6e-06 > mx25 n3 n2 n5 vdd pfet w=1.41e-05 l=6e-07 ad=2.115e-11 as=2.1015e-11 > +pd=1.71e-05 ps=2.355e-05 > mx27 n5 n3 n4 vdd pfet w=3.21e-05 l=6e-07 ad=9.3915e-11 as=2.889e-11 > +pd=1.0125e-05 ps=1.8e-06 > mx26 n4 n3 n5 vdd pfet w=3.21e-05 l=6e-07 ad=2.889e-11 as=4.815e-11 pd=1.8e-06 > +ps=3.51e-05 > mx32 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=1.0116e-10 as=7.587e-11 > +pd=4.695e-05 ps=3.6e-06 > mx31 n5 n4 out vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11 > +pd=3.6e-06 ps=3.6e-06 > mx30 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11 > +pd=3.6e-06 ps=3.6e-06 > mx29 n5 n4 out vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11 > +pd=3.6e-06 ps=3.6e-06 > mx28 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=9.3915e-11 > +pd=3.6e-06 ps=1.0125e-05 > mx14 n7 in n2 gnd nfet w=1.8e-06 l=6e-07 ad=1.107e-11 as=2.7e-12 pd=1.35e-05 > +ps=4.8e-06 > mx23 gnd nena n7 gnd nfet w=3.6e-05 l=6e-07 ad=5.4e-11 as=5.4e-11 pd=3.9e-05 > +ps=3.9e-05 > mx15 n3 n2 n7 gnd nfet w=7.2e-06 l=6e-07 ad=1.08e-11 as=1.107e-11 pd=1.02e-05 > +ps=1.35e-05 > mx17 n7 n3 n4 gnd nfet w=1.62e-05 l=6e-07 ad=4.725e-11 as=1.458e-11 > +pd=7.575e-06 ps=1.8e-06 > mx16 n4 n3 n7 gnd nfet w=1.62e-05 l=6e-07 ad=1.458e-11 as=2.43e-11 pd=1.8e-06 > +ps=1.92e-05 > mx22 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=5.076e-11 as=3.807e-11 > +pd=2.595e-05 ps=3.6e-06 > mx21 n7 n4 out gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11 > +pd=3.6e-06 ps=3.6e-06 > mx20 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11 > +pd=3.6e-06 ps=3.6e-06 > mx19 n7 n4 out gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11 > +pd=3.6e-06 ps=3.6e-06 > mx18 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=4.725e-11 > +pd=3.6e-06 ps=7.575e-06 > > ---------------------------------------------------------------- > | > | ex2 - An example of how a tristate buffer model is built. This > | example uses the [NoModel] switch to create "dummy" input > | and enable pins that have no corresponding models in the > | IBIS file. > | > > | > | Specify the IBIS version and file revision number. > | > [IBIS Ver] 2.1 > [File rev] 0 > > | > | Add some comments to identify the file. > | > [date] April 1, 2001 > [source] From MegaFLOPS Inc. layout and silicon models. > [notes] I really wouldn't try to use this driver. It's really bad. > [disclaimer] This file is only for demonstration purposes. It describes > a really crummy tri-state driver. > > You can put blank lines in any of these sections. (But s2ibis2 won't > print them.) > > Of course, as noted in the documentation, any text in these sections is > truncated at 1KB. > > [Copyright] Copyright 2001 MegaFLOPS Inc. > > | > | Give the spice type. Allowable values are hspice, pspice, spice2, > | spice3 and spectre. > | > [Spice type] hspice > > | > | Now specify some global parameters. These parameters will apply to > | _all_ the models in this file. > | > | Note on the [Temperature range] keyword: Since this is a CMOS circuit, > | the min column contains the highest temperature, since this temperature > | causes or amplifies the "min" (slow, weak) behavior, while the max > | column contains the lowest temperature, since this temperature causes or > | amplifies the "max" (fast, strong) behavior. If this were a bipolar > | circuit, these temperature values would be reversed. > | > [temperature range] 27 100 0 > [voltage range] 3.3 3 3.6 > [sim time] 3ns > [vil] 0 0 0 > [vih] 3.3 3 3.6 > [rload] 500 > > | > | Specify the default pin parasitics > | > [R_pkg] 2.0m 1.0m 4.0m > [L_pkg] 0.2nH 0.1nH 0.4nH > [C_pkg] 2pF 1pF 4pF > > | > | Component Description > | > [Component] MCM Trisate Driver > [manufacturer] MegaFLOPS Inc. > > | > | Specify the SPICE file where the circuit is located. > | > [Spice file] tristate.sp > > | > | Now specify the pin list. Since we're just creating an IBIS file for > | the driver, we'll use a very short pin list. > | > | The pin list formats can be found in doc/s2ibis2.txt. Briefly, the > | first line of each pin is of the form > | > | pin_name spice_node signal_name model_name > | > | If a pin description has more than one line (e.g. the first pin in the > | pin list below), the second line is of the form > | > | -> input_pin enable_pin > | > | Note that the second line must begin with the symbol "->". > | > | Therefore, a "translation" of the pin list below would read: > | > | - The first pin is pin number "out". It corresponds to node "out" in > | the given SPICE file. The signal carried on this pin is named > | "out". This pin is represented by the model "tristate_driver"; > | it is driven by pin number "in" and is enabled by pin number > | "enable". > | - The second pin is pin number "in", which corresponds to node "in" > | in the SPICE file; its signal is named "in". The model for this > | pin is "dummy". > | - The third pin is pin number "enable", which corresponds to node > | "enable" in the SPICE file; its signal is named "enable". The > | model for this pin is "dummy" (the same model as the input pin). > | - The fourth pin is pin number "gnd", which corresponds to node "gnd" > | in the SPICE file; it carries the "gnd" signal. The model for this > | pin is "GND", which is an s2ibis2 reserved word that denotes a > | ground supply pin. > | - The fifth pin is pin number "vdd", which corresponds to node "vdd" > | in the SPICE file; it carries the "vdd" signal. The model for this > | pin is "POWER", which is an s2ibis2 reserved word that denotes a > | power supply pin. > | > [Pin] > out out out tristate_driver > -> in ena > in in in dummy > ena enable enable dummy > gnd gnd gnd GND > vdd vdd vdd POWER > > | > | Now we give the particulars of the model "tristate_driver". It is of > | type "3-State" (allowable types may be found in doc/s2ibis2.txt) and is > | non-inverting. We want to use models from the file "spectre.mod" for > | typ, min and max simulations, and we want to include both a rising and > | falling waveform in our IBIS model. Both the rising and falling > | wveforms have a 500 ohm load; the rising waveform has the load > | grounded, while the falling waveform has the load connected to 3.3V. > | Neither waveform includes any other test fixture or package parasitics. > | > [Model] tristate_driver > [Model type] 3-state > [Polarity] Non-inverting > [Enable] active-low > [Model file] spectre.mod spectre.mod spectre.mod > [Rising waveform] 500 0 NA NA NA NA NA NA NA > [Falling waveform] 500 3.3 NA NA NA NA NA NA NA > > | > | Now specify stuff for the model "dummy". Since we only wanted to model > | the driver, we use the [NoModel] switch to tell s2ibis2 not to create > | this model. > | > [Model] dummy > [nomodel] > - --------------169D5D8C0FC68DFEBADEAFE1 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit  

Ramesh Karmungi wrote:

Hello Abbey,

Thanks for quick reply. Outfile is not generated. It has generated 10 (.spi) files, whereas in putout.spi netlist and model parameters are given and no error message.  However, in other .spi files only header without netlist.
I am herewith attaching tristate.s2i and putout.spi files.
when i have run the tristate.s2i as downloaded (it has spice type: Spectra), it runs s2ibis2 without error and creates .ibs but without any I/V or V/T data.
I would be thankful if you could give me suggestions.

Thanks and Regards
Ramesh

Abdulrahman A Rafiq wrote:

 Ramesh,

Is there an output file generated ? Can you open it in your basic text editor and see what error message its flaging ?
Also see if you can open the .spi file and see if there are any messages in there ?

Abbey A. Rafiq
 
 
 

At 12:35 PM 11/23/2001 +0530, Ramesh Karmungi wrote:

Hello,

I am new user of  IBIS tools. I have downloaded Spitran to develop ibis models. Spitran gives me .s2i file. This was used as input file to run s2ibis2.exe.  However, am unable to run s2ibis2. Following lines will appear on screen and stops execution of s2ibis2..

s2ibis2: Analyzing component MCM Driver .
s2ibis2: Starting HSpice job with input putout.spi.
failure!!!!!

I have noticed it creates a .spi file in the process.

I work on PC with windows 2000 or windows NT system. I have Avanti HSPICE 99.4.
Could anyone help me out to sort out the problem.

Thanks and Regards with anticipation

Ramesh K

* Typ pullup curve for model tristate_driver
*
* Spice deck created by s2ibis v 1.1
* North Carolina State University
*
minva vdd enable nena vdd pfet w=3.6e-06 l=6e-07 ad=2.1015e-11 as=5.4e-12 
+pd=2.355e-05 ps=6.6e-06
minvb gnd enable nena gnd nfet w=1.8e-06 l=6e-07 ad=1.107e-11 as=2.7e-12 
+pd=1.35e-05 ps=4.8e-06

mx33 n5 enable vdd vdd pfet w=3.84e-05 l=6e-07 ad=5.76e-11 as=5.76e-11
+pd=4.14e-05 ps=4.14e-05
mx24 n5 in n2 vdd pfet w=3.6e-06 l=6e-07 ad=2.1015e-11 as=5.4e-12 pd=2.355e-05
+ps=6.6e-06
mx25 n3 n2 n5 vdd pfet w=1.41e-05 l=6e-07 ad=2.115e-11 as=2.1015e-11
+pd=1.71e-05 ps=2.355e-05
mx27 n5 n3 n4 vdd pfet w=3.21e-05 l=6e-07 ad=9.3915e-11 as=2.889e-11
+pd=1.0125e-05 ps=1.8e-06
mx26 n4 n3 n5 vdd pfet w=3.21e-05 l=6e-07 ad=2.889e-11 as=4.815e-11 pd=1.8e-06
+ps=3.51e-05
mx32 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=1.0116e-10 as=7.587e-11
+pd=4.695e-05 ps=3.6e-06
mx31 n5 n4 out vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11
+pd=3.6e-06 ps=3.6e-06
mx30 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11
+pd=3.6e-06 ps=3.6e-06
mx29 n5 n4 out vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11
+pd=3.6e-06 ps=3.6e-06
mx28 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=9.3915e-11
+pd=3.6e-06 ps=1.0125e-05
mx14 n7 in n2 gnd nfet w=1.8e-06 l=6e-07 ad=1.107e-11 as=2.7e-12 pd=1.35e-05
+ps=4.8e-06
mx23 gnd nena n7 gnd nfet w=3.6e-05 l=6e-07 ad=5.4e-11 as=5.4e-11 pd=3.9e-05
+ps=3.9e-05
mx15 n3 n2 n7 gnd nfet w=7.2e-06 l=6e-07 ad=1.08e-11 as=1.107e-11 pd=1.02e-05
+ps=1.35e-05
mx17 n7 n3 n4 gnd nfet w=1.62e-05 l=6e-07 ad=4.725e-11 as=1.458e-11
+pd=7.575e-06 ps=1.8e-06
mx16 n4 n3 n7 gnd nfet w=1.62e-05 l=6e-07 ad=1.458e-11 as=2.43e-11 pd=1.8e-06
+ps=1.92e-05
mx22 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=5.076e-11 as=3.807e-11
+pd=2.595e-05 ps=3.6e-06
mx21 n7 n4 out gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11
+pd=3.6e-06 ps=3.6e-06
mx20 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11
+pd=3.6e-06 ps=3.6e-06
mx19 n7 n4 out gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11
+pd=3.6e-06 ps=3.6e-06
mx18 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=4.725e-11
+pd=3.6e-06 ps=7.575e-06
* N56S SPICE BSIM1 (Berkeley Level 4; HSPICE Level 13) PARAMETERS
* Modified to use regular SPICE (not HSPICE) names for Spectre
*
*NMOS PARAMETERS
*
.MODEL nfet NMOS level=4
+vfb0=-6.67767E-01
+lvfb=-9.88313E-03
+wvfb=-3.29367E-02
+phi0=8.60647E-01
+lphi=0.00000E+00
+wphi=0.00000E+00
+k1=8.17935E-01
+lk1=-4.65708E-02
+wk1=4.75791E-02
+k2=4.25774E-02
+lk2=3.52629E-02
+wk2=-2.77046E-03
+eta0=-6.14649E-05
+leta=1.89078E-02
+weta=-1.18479E-02
+muz=5.83829E+02
+dl0=1.40291E-001
+dw0=5.07562E-001
+u00=3.29586E-01
+lu0=9.77520E-02
+wu0=-9.32319E-02
+u1=1.99382E-02
+lu1=3.61973E-02
+wu1=-2.86830E-03
+x2m=1.29121E+01
+lx2m=-8.28086E+00
+wx2m=6.90864E+00
+x2e=7.54028E-04
+lx2e=-3.43366E-03
+wx2e=5.18763E-04
+x3e=2.37991E-04
+lx3e=-1.61033E-03
+wx3e=-5.39861E-03
+x2u0=-6.35761E-03
+lx2u0=-3.86200E-03
+wx2u0=5.33022E-03
+x2u1=-5.68012E-04
+lx2u1=1.22523E-03
+wx2u1=2.85097E-04
+mus=6.84165E+02
+lms=-2.54285E+01
+wms=9.21339E-01
+x2ms=4.89160E+00
+lx2ms=-1.90933E+00
+wx2ms=7.94142E+00
+x3ms=4.83048E+00
+lx3ms=4.02423E+00
+wx3ms=-5.33716E+00
+x3u1=7.20765E-03
+lx3u1=-1.37194E-04
+wx3u1=-3.70674E-03
+tox=1.00000E-008
+tempm=2.70000E+01
+vddm=5.00000E+00
+cgdom=3.63E-010
+cgsom=3.63E-010
+cgbom=4.52505E-010
+xpart=1.00000E+000
+n0=1.00000E+000
+ln0=0.00000E+000
+wn0=0.00000E+000
+nb0=0.00000E+000
+lnb=0.00000E+000
+wnb=0.00000E+000
+nd0=0.00000E+000
+lnd=0.00000E+000
+wnd=0.00000E+000
*
*N+ diffusion:: 
*
+rsh=2.4 
+cj=7.732100e-04 
+cjw=2.900000e-10 
+ijs=1e-08 
+pj=0.8 
+pjw=0.8 
+mj=1.10106 
+mjw=0.26 
+wdf=0 
*
*PMOS PARAMETERS
*
.MODEL pfet PMOS level=4
+vfb0=-6.59693E-02
+lvfb=-1.78327E-02
+wvfb=-2.45473E-03
+phi0=7.68179E-01
+lphi=0.00000E+00
+wphi=0.00000E+00
+k1=2.85648E-01
+lk1=-1.64579E-02
+wk1=3.08917E-02
+k2=-6.62532E-02
+lk2=2.49518E-02
+wk2=4.62778E-04
+eta0=-7.90844E-03
+leta=1.92294E-02
+weta=-2.34646E-03
+muz=1.41704E+02
+dl0=2.14000E-001
+dw0=5.34406E-001
+u00=1.95407E-01
+lu0=6.22059E-02
+wu0=-5.94668E-02
+u1=8.56390E-03
+lu1=1.39477E-02
+wu1=7.65802E-04
+x2m=6.79470E+00
+lx2m=-1.43654E+00
+wx2m=6.56475E-01
+x2e=1.08483E-04
+lx2e=-1.24539E-03
+wx2e=9.77240E-05
+x3e=4.33468E-04
+lx3e=1.42453E-04
+wx3e=-1.71650E-03
+x2u0=8.73535E-03
+lx2u0=-1.31646E-03
+wx2u0=4.78072E-04
+x2u1=3.06834E-04
+lx2u1=4.41194E-04
+wx2u1=3.49198E-04
+mus=1.47746E+02
+lms=1.78644E+01
+wms=1.24739E-01
+x2ms=6.09155E+00
+lx2ms=-1.61404E-01
+wx2ms=1.24507E+00
+x3ms=-3.18656E-01
+lx3ms=2.79732E+00
+wx3ms=1.71058E+00
+x3u1=-1.22826E-03
+lx3u1=1.06181E-04
+wx3u1=1.07711E-03
+tox=1.00000E-008
+tempm=2.70000E+01
+vddm=5.00000E+00
+cgdom=5.540E-010
+cgsom=5.54E-010
+cgbom=4.67045E-010
+xpart=1.00000E+000
+n0=1.00000E+000
+ln0=0.00000E+000
+wn0=0.00000E+000
+nb0=0.00000E+000
+lnb=0.00000E+000
+wnb=0.00000E+000
+nd0=0.00000E+000
+lnd=0.00000E+000
+wnd=0.00000E+000
*
*P+ diffusion:: 
*
+rsh=2.1
+cj=9.319100e-04
+cjw=1.563700e-10
+ijs=1e-08
+pj=0.85
+pjw=0.85
+mj=0.487073
+mjw=0.47848
+wdf=0

* simple diode model
.model clamp d vj=0.7 rs=100
VOUTS2I out 0 DC 0
VCCS2I vdd 0 DC 3.3
VGNDS2I gnd 0 DC 0
VENAS2I enable 0 DC 0
VINS2I in 0 DC 3.3
.TEMP 27
.OPTIONS INGOLD=2
.DC VOUTS2I -3.3 6.6 0.1
.PRINT DC I(VOUTS2I)
.END
*
* simple inverter
*
minva vdd enable nena vdd pfet w=3.6e-06 l=6e-07 ad=2.1015e-11 as=5.4e-12 
+pd=2.355e-05 ps=6.6e-06
minvb gnd enable nena gnd nfet w=1.8e-06 l=6e-07 ad=1.107e-11 as=2.7e-12 
+pd=1.35e-05 ps=4.8e-06

*
* tristate buffer model
*
mx33 n5 enable vdd vdd pfet w=3.84e-05 l=6e-07 ad=5.76e-11 as=5.76e-11
+pd=4.14e-05 ps=4.14e-05
mx24 n5 in n2 vdd pfet w=3.6e-06 l=6e-07 ad=2.1015e-11 as=5.4e-12 pd=2.355e-05
+ps=6.6e-06
mx25 n3 n2 n5 vdd pfet w=1.41e-05 l=6e-07 ad=2.115e-11 as=2.1015e-11
+pd=1.71e-05 ps=2.355e-05
mx27 n5 n3 n4 vdd pfet w=3.21e-05 l=6e-07 ad=9.3915e-11 as=2.889e-11
+pd=1.0125e-05 ps=1.8e-06
mx26 n4 n3 n5 vdd pfet w=3.21e-05 l=6e-07 ad=2.889e-11 as=4.815e-11 pd=1.8e-06
+ps=3.51e-05
mx32 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=1.0116e-10 as=7.587e-11
+pd=4.695e-05 ps=3.6e-06
mx31 n5 n4 out vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11
+pd=3.6e-06 ps=3.6e-06
mx30 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11
+pd=3.6e-06 ps=3.6e-06
mx29 n5 n4 out vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=7.587e-11
+pd=3.6e-06 ps=3.6e-06
mx28 out n4 n5 vdd pfet w=4.215e-05 l=9e-07 ad=7.587e-11 as=9.3915e-11
+pd=3.6e-06 ps=1.0125e-05
mx14 n7 in n2 gnd nfet w=1.8e-06 l=6e-07 ad=1.107e-11 as=2.7e-12 pd=1.35e-05
+ps=4.8e-06
mx23 gnd nena n7 gnd nfet w=3.6e-05 l=6e-07 ad=5.4e-11 as=5.4e-11 pd=3.9e-05
+ps=3.9e-05
mx15 n3 n2 n7 gnd nfet w=7.2e-06 l=6e-07 ad=1.08e-11 as=1.107e-11 pd=1.02e-05
+ps=1.35e-05
mx17 n7 n3 n4 gnd nfet w=1.62e-05 l=6e-07 ad=4.725e-11 as=1.458e-11
+pd=7.575e-06 ps=1.8e-06
mx16 n4 n3 n7 gnd nfet w=1.62e-05 l=6e-07 ad=1.458e-11 as=2.43e-11 pd=1.8e-06
+ps=1.92e-05
mx22 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=5.076e-11 as=3.807e-11
+pd=2.595e-05 ps=3.6e-06
mx21 n7 n4 out gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11
+pd=3.6e-06 ps=3.6e-06
mx20 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11
+pd=3.6e-06 ps=3.6e-06
mx19 n7 n4 out gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=3.807e-11
+pd=3.6e-06 ps=3.6e-06
mx18 out n4 n7 gnd nfet w=2.115e-05 l=9e-07 ad=3.807e-11 as=4.725e-11
+pd=3.6e-06 ps=7.575e-06
| 
| ex2 -   An example of how a tristate buffer model is built. This
|         example uses the [NoModel] switch to create "dummy" input
|         and enable pins that have no corresponding models in the
|         IBIS file.
| 

|
| Specify the IBIS version and file revision number.
|
[IBIS Ver]              2.1
[File rev]              0

|
| Add some comments to identify the file.
|
[date]  April 1, 2001
[source] From MegaFLOPS Inc. layout and silicon models.
[notes] I really wouldn't try to use this driver.  It's really bad.
[disclaimer] This file is only for demonstration purposes. It describes
a really crummy tri-state driver.

You can put blank lines in any of these sections. (But s2ibis2 won't
print them.)

Of course, as noted in the documentation, any text in these sections is
truncated at 1KB.

[Copyright] Copyright 2001 MegaFLOPS Inc.

|
| Give the spice type.  Allowable values are hspice, pspice, spice2,
| spice3 and spectre.
|
[Spice type]            hspice

|
| Now specify some global parameters. These parameters will apply to
| _all_ the models in this file.
|
| Note on the [Temperature range] keyword: Since this is a CMOS circuit,
| the min column contains the highest temperature, since this temperature
| causes or amplifies the "min" (slow, weak) behavior, while the max
| column contains the lowest temperature, since this temperature causes or
| amplifies the "max" (fast, strong) behavior.  If this were a bipolar
| circuit, these temperature values would be reversed.
|
[temperature range] 27 100 0
[voltage range] 3.3 3 3.6
[sim time] 3ns
[vil] 0 0 0
[vih] 3.3 3 3.6
[rload] 500

| 
| Specify the default pin parasitics
| 
[R_pkg]                 2.0m    1.0m    4.0m
[L_pkg]                 0.2nH   0.1nH   0.4nH
[C_pkg]                 2pF     1pF     4pF

|
| Component Description
|
[Component] MCM Trisate Driver
[manufacturer] MegaFLOPS Inc.

|
| Specify the SPICE file where the circuit is located.
|
[Spice file]    tristate.sp

|
| Now specify the pin list.  Since we're just creating an IBIS file for
| the driver, we'll use a very short pin list.
|
| The pin list formats can be found in doc/s2ibis2.txt.  Briefly, the
| first line of each pin is of the form
|
|  pin_name  spice_node  signal_name  model_name
|
| If a pin description has more than one line (e.g. the first pin in the
| pin list below), the second line is of the form
|
| -> input_pin  enable_pin
|
| Note that the second line must begin with the symbol "->".
|
| Therefore, a "translation" of the pin list below would read:
|
|   - The first pin is pin number "out". It corresponds to node "out" in
|     the given SPICE file. The signal carried on this pin is named
|     "out". This pin is represented by the model "tristate_driver"; 
|     it is driven by pin number "in" and is enabled by pin number 
|     "enable".
|   - The second pin is pin number "in", which corresponds to node "in"
|     in the SPICE file; its signal is named "in". The model for this
|     pin is "dummy".
|   - The third pin is pin number "enable", which corresponds to node 
|     "enable" in the SPICE file; its signal is named "enable". The 
|     model for this pin is "dummy" (the same model as the input pin).
|   - The fourth pin is pin number "gnd", which corresponds to node "gnd"
|     in the SPICE file; it carries the "gnd" signal. The model for this
|     pin is "GND", which is an s2ibis2 reserved word that denotes a
|     ground supply pin.
|   - The fifth pin is pin number "vdd", which corresponds to node "vdd"
|     in the SPICE file; it carries the "vdd" signal. The model for this
|     pin is "POWER", which is an s2ibis2 reserved word that denotes a
|     power supply pin.
|
[Pin]
out out out tristate_driver 
- -> in ena
in in in dummy
ena enable enable dummy
gnd gnd gnd GND
vdd vdd vdd POWER

|
| Now we give the particulars of the model "tristate_driver".  It is of 
| type "3-State" (allowable types may be found in doc/s2ibis2.txt) and is
| non-inverting. We want to use models from the file "spectre.mod" for
| typ, min and max simulations, and we want to include both a rising and
| falling waveform in our IBIS model. Both the rising and falling
| wveforms have a 500 ohm load; the rising waveform has the load
| grounded, while the falling waveform has the load connected to 3.3V.
| Neither waveform includes any other test fixture or package parasitics.
|
[Model] tristate_driver
[Model type] 3-state
[Polarity] Non-inverting
[Enable] active-low
[Model file] spectre.mod spectre.mod spectre.mod
[Rising waveform] 500 0 NA NA NA NA NA NA NA
[Falling waveform] 500 3.3 NA NA NA NA NA NA NA

|
| Now specify stuff for the model "dummy". Since we only wanted to model
| the driver, we use the [NoModel] switch to tell s2ibis2 not to create
| this model. 
|
[Model]         dummy
[nomodel]
- --------------169D5D8C0FC68DFEBADEAFE1-- - --------------088FEF9DC7053EC8BD2D4179 Content-Type: text/x-vcard; charset=us-ascii; name="arafiq.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Abdulrahman A. Rafiq Content-Disposition: attachment; filename="arafiq.vcf" begin:vcard n:Rafiq;Abdulrahman A. tel;pager:(408) 301-8880 tel;cell:(805) 708-19XX tel;fax:(408) 526-6603 tel;home:(408) 615-8427 tel;work:(408) 527-5540 x-mozilla-html:FALSE url:wwwin-people.cisco.com/~arafiq org:Cisco Systems, Inc. ISBU;Signal Integrity and Packaging Design Group version:2.1 email;internet:arafiq@cisco.com title:Hardware Engineer, Behavioral Models Engineer adr;quoted-printable:;;170 West Tasman Drive=0D=0ABldg. G, 2nd Floor=0D=0AMail Stop: SJ/C/G/2/3;San Jose;Ca;95134;U.S.A. note;quoted-printable:Manager: Syed B. Huq=0D=0Aemail: shuq@cisco.com =0D=0APhone: (408) 525-3399 fn:Abdulrahman A. Rafiq end:vcard - --------------088FEF9DC7053EC8BD2D4179-- ------------------------------ Date: Tue, 27 Nov 2001 12:07:23 -0800 (PST) From: Syed Huq Subject: Re: Execution of s2ibis2 Ramesh, I have not used the PC version but let me ask you a few questions: 1) Are you able to run HSPICE from a command line ? 2) Can you try: % hspice putout.spi and see if you get an error. If you get an error, open the output file and see what it is all about. s2ibis2 works on all versions of HSPICE so that should not be a problem My 'guess' at this point is you call to HSPICE from s2ibis2 may not be working properly.. Since s2ibis2 creates an .spi file, that is good but as it tries to run HSPICE on this .spi file it crashes(that is the reason to do test#1 and #2 above) Let me know.. Syed > Date: Fri, 23 Nov 2001 12:35:08 +0530 > From: Ramesh Karmungi > Subject: Execution of s2ibis2 > To: ibis-users@eda.org > MIME-version: 1.0 > X-Accept-Language: en > > Hello, > > I am new user of IBIS tools. I have downloaded Spitran to develop ibis > models. Spitran gives me .s2i file. This was used as input file to run > s2ibis2.exe. However, am unable to run s2ibis2. Following lines will > appear on screen and stops execution of s2ibis2.. > > s2ibis2: Analyzing component MCM Driver . > s2ibis2: Starting HSpice job with input putout.spi. > failure!!!!! > > I have noticed it creates a .spi file in the process. > > I work on PC with windows 2000 or windows NT system. I have Avanti > HSPICE 99.4. > Could anyone help me out to sort out the problem. > > Thanks and Regards with anticipation > > Ramesh K ------------------------------ Date: Wed, 28 Nov 2001 08:48:59 -0800 (PST) From: Syed Huq Subject: Re: Execution of s2ibis2 Ramesh, The only NT version that is on the web only supports IBISv1.1. There is a Win95 version also on the web for IBISv2.1. Unfortunately, I don't see any 2000 or NT version for s2ibis2. I am not sure how difficult it is to download the source code and recompile on your particular OS. Maybe other Windoze users can comment on this. Syed > Date: Wed, 28 Nov 2001 10:26:09 +0530 > From: Ramesh Karmungi > Subject: Re: Execution of s2ibis2 > To: Syed Huq , ibis-users@eda.org > MIME-version: 1.0 > X-Accept-Language: en > > Hello Syed Huq, > > Thanks for reply, as suggested i have tried and found HSPICE works on command line > with > > start /w c:\path of HSPICE -i -b > > It is creating .lis file (output) and its OK. However, when I run s2ibis2 ver1.1, > HSPICE doesn't run. > Could you please suggest. > > I have one more query, I have downloaded S2IBIS2 ver 2.0. In read me document, it > is mentioned that it work on the following os: > > bin/ contains the following executables: > > s2ibis2.ultrix executable for DECstations (Ultrix 4.3) > s2ibis2.hpux executable for HPUX > s2ibis2.aix32 executable for RS6000 (AIX 3.2) > s2ibis2.sun4 executable for SPARCstation (SunOS 4) > s2ibis2.solaris executable for SPARCstation (Solaris) > > Please let me know whether s2ibis2 ver 2.0 supports on windows 2000 or NT and is > it available. > > Thanks > Ramesh > > > Syed Huq wrote: > > > Ramesh, > > > > I have not used the PC version but let me ask you a few questions: > > > > 1) Are you able to run HSPICE from a command line ? > > 2) Can you try: > > > > % hspice putout.spi > > > > and see if you get an error. > > > > If you get an error, open the output file and see what it is all > > about. > > > > s2ibis2 works on all versions of HSPICE so that should not be a problem > > My 'guess' at this point is you call to HSPICE from s2ibis2 may not be > > working properly.. > > > > Since s2ibis2 creates an .spi file, that is good but as it tries to run HSPICE > > on this .spi file it crashes(that is the reason to do test#1 and #2 above) > > > > Let me know.. > > > > Syed > > > > > Date: Fri, 23 Nov 2001 12:35:08 +0530 > > > From: Ramesh Karmungi > > > Subject: Execution of s2ibis2 > > > To: ibis-users@eda.org > > > MIME-version: 1.0 > > > X-Accept-Language: en > > > > > > Hello, > > > > > > I am new user of IBIS tools. I have downloaded Spitran to develop ibis > > > models. Spitran gives me .s2i file. This was used as input file to run > > > s2ibis2.exe. However, am unable to run s2ibis2. Following lines will > > > appear on screen and stops execution of s2ibis2.. > > > > > > s2ibis2: Analyzing component MCM Driver . > > > s2ibis2: Starting HSpice job with input putout.spi. > > > failure!!!!! > > > > > > I have noticed it creates a .spi file in the process. > > > > > > I work on PC with windows 2000 or windows NT system. I have Avanti > > > HSPICE 99.4. > > > Could anyone help me out to sort out the problem. > > > > > > Thanks and Regards with anticipation > > > > > > Ramesh K ------------------------------ Date: Fri, 30 Nov 2001 10:54:59 -0800 From: "Peters, Stephen" Subject: Agenda, IBIS Open Forum Teleconference 12/07/01 IBIS Open Forum Meeting Agenda for 12/07/01 Bridge Number Reservation # Passcode 1-877-299-1938 None 6467862 1-617-801-9666 (International Dial-In) All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the Reservation Number and Passcode. 8:00 Check-In, Intros, Announcements Peters - Intros of New IBIS Participants, Meeting Quorum Peters - Membership Update and Treasurers Report Fleming/Ross - Review of Previous Meeting's Minutes (and ARs) Peters - Miscellany/Announcements All - Press & Web Page Updates Huq, All - New Models Available, Library Update Leventhal, All - Opens for New Issues All 8:15 Administrative and Project Discussions International/External Progress - pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits (IMIC) Peters - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters - JEDEC JC-16 Modeling and Testing Sessions - T10, Project 1414-DT - SCSI Signal Modeling Barnes IBIS Summit Meeting DesignCon 2002 Peters/Ross Future Summit Meeting Plans Peters/Ross - Date2002 IBIS Model Review Committee Ross Majordomo Update Angulo New Administrative Issues All 8:45 Technical Discussion Connector Proposal Report Peters/Ross IBIS Futures Group Report Peters/Green BIRD73.4 - Fall Back Submodel (Vote) Ross ibischk3 Status Ross s2ibis2 - BUG2 - Cannot Read IBIS File Using Spitran Ross XML for IBIS Ross New Technical Issues All 9:50 Wrap Up and Next Meetings Plans Peters 9:55 Sign Off ------------------------------ Date: Thu, 06 Dec 2001 14:56:02 -0500 From: Mike LaBonte Subject: Re: IBIS/XML Hint: View XML files using Internet Explorer 5 or later for a more usable display. It uses color, and allows you to expand/collapse sections. Mike LaBonte John Angulo wrote: > > Posting on behalf of Bob Ross: > > > To IBIS Community: > > > > Atul Agarwal has provided some XML/IBIS format tranformation > > and utilities and much inforamtion. > > > > This is still work in progress. This information is located > > under: > > > > http://www.eda.org/pub/ibis/xml/ > > > > Contact Atul (see the 00readme.txt file) for feedback. You > > do need to be familar with XML and related utilities to use > > this material. > > > > Bob Ross > > Mentor Graphics ------------------------------ Date: Thu, 13 Dec 2001 10:58:41 -0800 From: "John Angulo" Subject: IBIS/XML Posting on behalf of Bob Ross: > > To IBIS Community: > > Atul Agarwal has provided some XML/IBIS format tranformation > and utilities and much inforamtion. > > This is still work in progress. This information is located > under: > > http://www.eda.org/pub/ibis/xml/ > > Contact Atul (see the 00readme.txt file) for feedback. You > do need to be familar with XML and related utilities to use > this material. > > Bob Ross > Mentor Graphics > ------------------------------ Date: Fri, 14 Dec 2001 11:53:21 +0100 From: Michael Schulte Subject: ibis models Hello Group, I am searching ibis models for two devices: CS8900A Cirrus Logic / Crystal S1D13806 Epson Does anyone know how I can get these models. They are not provided by their manufacturers. Thanks in advance, Michael Schulte ------------------------------ Date: Fri, 14 Dec 2001 18:34:21 -0800 From: "Ross, Bob" Subject: IBIS Uploads and Free Pass To All: COMPLIMENTARY (FREE) DESIGNCON2002 VIP EXHIBITION REGISTRATION: DesignCon2002 is offering a Complimentary VIP Exhibits Pass to the IBIS mailing lists and other colleagues. You can register under: http://www.designcon.com/2002/promo.asp S2IBIS2NT: Scott McMorrow of SiQual has contributed another version of s2ibis2 to support Windows NT and 2000. It is located under: http://www.eda.org/pub/ibis/s2ibis/s2ibis2_nt/s2ibis2WinNT.zip An earlier version is also located under http://www.eda.org/pub/ibis/s2ibis/s2ibis2_nt/s2ibis2Win95.zip Check the 00readme.txt file for information about both utilities. Both work only with HSPICE. IBIS/XML A new html.zip has been provided by Atul Agarwal of Apt Software Avenues and uploaded along with a new xml.tar.Z file under: http://www.eda.org/pub/ibis/xml/ Bob Ross Mentor Graphics ------------------------------ Date: Mon, 7 Jan 2002 13:08:44 -0500 From: "Todd Westerhoff" Subject: New "Kumar Was Right" Product Items Hi all, Just a short note to let you know we've added new items to the "Kumar Was Right" on-line memorabilia store: Microfiber Cap - $12.99 Tote Bag - $12.99 Boxer Shorts - $12.99 The Kumar memorabilia on-line store is found at: http://www.cafepress.com/kumar_right For those of you who have no idea what I'm talking about - well, it's a long story. One of those inside-joke deals ... Todd. Todd Westerhoff SI Engineer - Hammerhead Networks 5 Federal Street - Billerica, MA - 01821 email:twester@hhnetwk.com - ph: 978-671-5084 ============================================ "Oh, but ain't that America, for you and me Ain't that America, we're something to see Ain't that America, Home of the Free Little pink houses, for you and me" - - John Mellencamp ------------------------------ Date: Mon, 7 Jan 2002 14:29:15 -0800 From: "Peters, Stephen" Subject: Agenda, IBIS Teleconferance 1/11 Sorry if you have already received this - we are having some mailer difficulties with messages to ibis@eda.org. IBIS Open Forum Meeting Agenda for 1/11/02 Bridge Number Reservation # Passcode 1-916-356-2663 2 8295945 (International Dial-in the same) All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the Reservation Number and Passcode. 8:00 Check-In, Intros, Announcements Peters - Intros of New IBIS Participants, Meeting Quorum Peters - Membership Update and Treasurers Report Fleming/Ross - Review of Previous Meeting's Minutes (and ARs) Peters - Miscellany/Announcements All - Press & Web Page Updates Huq, All - New Models Available, Library Update Leventhal, All - Opens for New Issues All 8:15 Administrative and Project Discussions International/External Progress - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters - JEDEC JC-16 Modeling and Testing Sessions - T10, Project 1414-DT - SCSI Signal Modeling Barnes IBIS Summit Meeting DesignCon 2002 Peters/Ross IBIS Summit Meeting Plans DATE 2002 Peters/Ross IBIS Model Review Committee Ross Majordomo Update Angulo New Administrative Issues All 8:45 Technical Discussion Connector Proposal Report Peters/Ross IBIS Futures Group Report Peters/Green BIRD73.4 - Fall Back Submodel (Vote) Ross ibischk3 Status Ross New Technical Issues All 9:50 Wrap Up and Next Meetings Plans Peters 9:55 Sign Off ------------------------------ Date: Mon, 7 Jan 2002 15:41:22 -0800 (PST) From: Milton Schwartz x3261 Subject: Third IBIS Summit Call To All, We currently have a full, all day program with presentations. So now we are just calling for official signup at the meeting. Signup will be required to receive the free, hot lunch hosted by National Semiconductor. We need an accurate count. Please let us know if you are planning to attend. Milt Schwartz National Semiconductor ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------- DESIGNCON 2002 THIRD IBIS SUMMIT CALL FOR PARTICIPATION ------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ I B I S S U M M I T M E E T I N G Time/Date: 8:00 PM - 5:00 PM, Monday, January 28, 2002 Location: Santa Clara Convention Center Santa Clara, CA Content: IBIS Future Requirements is the main topic of this meeting These include an exchange of ideas on IBIS accuracy, connectors, and new requirements under discussion. Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: DesignCon 2002 & National Semiconductor Corporation IBIS Summit Signup: Milt Schwartz schwartz@galaxy.nsc.com (SIGNUP REQUIRED FOR FREE HOT LUNCH) D E S I G N C O N 2 0 0 2 M E E T I N G S Time/Date: Monday - Thursday, January 28 - January 31, 2002 Exhibition: Tuesday - Wednesday, January 29-30, 2002 IBIS Booth: Booth 704, Exhibition Hall - IBIS Information URL DesignCon2002: http://www.designcon.com/ FREE Exhibition Pass: http://www.designcon.com/2002/promo.asp CALL FOR IBIS SUMMIT PRESENTATIONS (We are fully booked) We already have several presentations/discussion topics planned. However, we are also seeking presentations from individuals who have IBIS experiences or issues. Format of Presentation: Overhead foils preferred, LCD projection available Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat. If you cannot provide an electronic format, then plan to bring 50 copies for distribution at the meeting. If you plan a presentation, please supply as early as possible for program planning: Title: Presenter: E-mail address: Company: Telephone: Estimate Time: Send this to: Milt Schwartz schwartz@galaxy.nsc.com Bob Ross bob_ross@mentor.com Deadline: Wednesday, January 23, 2002 for receiving presentations for copying. AGENDA The agenda includes presentations, discussions, refreshments, and a free buffet luncheon for participants. In addition, we will have an opportunity for Ad Hoc presentations and extended discussions. So far we plan the following topics (titles may change): "IBIS Users Experience, Barry Katz, Signal Integrity Software "A Critique of IBIS Models Available for Download on the Web", Jim Bell, SiQual "IBIS Accuracy at IBM", Greg Edlund, IBM "JEITA Activity Report", Atsuji Ito, Panasonic "Connector Specification Discussion", Gus Panella, Molex "IBIS-ML Futures and Discussion", Stephen Peters, Intel "EMC Presentation", Guy de Burgh, Innoveda "Lossy Line Characterization and Modeling for Spice and IBIS, Steve Corey, Time Domain Analysis Systems "IBIS/XML", Atul Agarwal, Apt Software Avenues "IBIS Version 4.0", Bob Ross, Mentor Graphics ------------------------------ Date: Tue, 8 Jan 2002 01:26:47 -0800 (PST) From: Milton Schwartz x3261 Subject: Third IBIS Summit Call To All, We currently have a full, all day program with presentations. So now we are just calling for official signup at the meeting. Signup will be required to receive the free, hot lunch hosted by National Semiconductor. We need an accurate count. Please let us know if you are planning to attend. Milt Schwartz National Semiconductor ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------- DESIGNCON 2002 THIRD IBIS SUMMIT CALL FOR PARTICIPATION ------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ I B I S S U M M I T M E E T I N G Time/Date: 8:00 PM - 5:00 PM, Monday, January 28, 2002 Location: Santa Clara Convention Center Santa Clara, CA Content: IBIS Future Requirements is the main topic of this meeting These include an exchange of ideas on IBIS accuracy, connectors, and new requirements under discussion. Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: DesignCon 2002 & National Semiconductor Corporation IBIS Summit Signup: Milt Schwartz schwartz@galaxy.nsc.com (SIGNUP REQUIRED FOR FREE HOT LUNCH) D E S I G N C O N 2 0 0 2 M E E T I N G S Time/Date: Monday - Thursday, January 28 - January 31, 2002 Exhibition: Tuesday - Wednesday, January 29-30, 2002 IBIS Booth: Booth 704, Exhibition Hall - IBIS Information URL DesignCon2002: http://www.designcon.com/ FREE Exhibition Pass: http://www.designcon.com/2002/promo.asp CALL FOR IBIS SUMMIT PRESENTATIONS (We are fully booked) We already have several presentations/discussion topics planned. However, we are also seeking presentations from individuals who have IBIS experiences or issues. Format of Presentation: Overhead foils preferred, LCD projection available Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat. If you cannot provide an electronic format, then plan to bring 50 copies for distribution at the meeting. If you plan a presentation, please supply as early as possible for program planning: Title: Presenter: E-mail address: Company: Telephone: Estimate Time: Send this to: Milt Schwartz schwartz@galaxy.nsc.com Bob Ross bob_ross@mentor.com Deadline: Wednesday, January 23, 2002 for receiving presentations for copying. AGENDA The agenda includes presentations, discussions, refreshments, and a free buffet luncheon for participants. In addition, we will have an opportunity for Ad Hoc presentations and extended discussions. So far we plan the following topics (titles may change): "IBIS Users Experience, Barry Katz, Signal Integrity Software "A Critique of IBIS Models Available for Download on the Web", Jim Bell, SiQual "IBIS Accuracy at IBM", Greg Edlund, IBM "JEITA Activity Report", Atsuji Ito, Panasonic "Connector Specification Discussion", Gus Panella, Molex "IBIS-ML Futures and Discussion", Stephen Peters, Intel "EMC Presentation", Guy de Burgh, Innoveda "Lossy Line Characterization and Modeling for Spice and IBIS, Steve Corey, Time Domain Analysis Systems "IBIS/XML", Atul Agarwal, Apt Software Avenues "IBIS Version 4.0", Bob Ross, Mentor Graphics ------------------------------ Date: Tue, 08 Jan 2002 08:50:06 -0800 From: "Ross, Bob" Subject: IBIS European Summit Meeting Announcment 3/8/02 To All: This is the first announcement of the European IBIS Summit meeting held during DATE 2002 in Paris for presentations and participation. Bob Ross Mentor Graphics E U R O P E A N I B I S S U M M I T M E E T I N G F I R S T A N N O U N C E M E N T Time/Date: 8:30 AM - 2 PM, Friday, March 8, 2002 Location: Concorde-Lafayette Hotel (adjacent to Le Palais des Congress de Paris Prote Mailot - site of the DATE2002 Conference) in Paris, France Rooms: Salon Van Gogh/Pissarro Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: EADS, Innoveda, Mentor Graphics and Zuken DATE2000: March 4-8, 2002. The IBIS meeting is scheduled the day following the trade show portion of the Conference See http://www.date-conference.com for more information. BACKGROUND For the last several years we have been holding very successful European IBIS Summit Meetings. We plan a combination of the following: Submitted Presentations on IBIS Topics (See below) Less formal Ad Hoc Presentations and Discussions IBIS Questions and Answers Below is an invitation to register and also to submit presentations. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the European IBIS Summit meeting. If you plan to participate, please supply the information below: Name: E-mail address: Company: Telephone: Send to: Karine Loudet (karine_loudet@mentor.com) CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. Some suggested subjects of interest are: IBIS Model Development Experiences Company IBIS Standards and Requirements Generating and Validating IBIS Models Future IBIS Requirements EMC/EMI IBIS Issues Format of Presentation: Overhead Projections Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat. Please plan to bring copies of your presentation to distribute at the meeting. If you plan a presentation, please supply Title: Presenter: E-mail address: Company: Telephone: Estimate Time: Send this to: Bob Ross (bob_ross@mentor.com) AGENDA The agenda includes presentations, discussions, and a free lunch. FOR FURTHER INFORMATION: Bob Ross, Vice Chair, EIA/IBIS Open Forum Mentor Graphics 8005 S.W. Boeckman Road Wilsonville, Oregon 97070 USA (503) 685-0732 bob_ross@mentor.com ------------------------------ Date: Wed, 9 Jan 2002 11:12:24 +0200 From: "Alon Levi" Subject: s2ibis problems This is a multi-part message in MIME format. - ------=_NextPart_000_015A_01C198FE.83E54380 Content-Type: text/plain; charset="windows-1255" Content-Transfer-Encoding: quoted-printable Hello, I have some problems with s2ibis input file,I would like to now if some = of you is dealing with that and can help me,if not I will glad to know where can I find support for that. Thank You,Alon - ------=_NextPart_000_015A_01C198FE.83E54380 Content-Type: text/html; charset="windows-1255" Content-Transfer-Encoding: quoted-printable
Hello,
I have some problems with = s2ibis input=20 file,I would like to now if some of you  is dealing with that and = can help=20 me,if not
I will glad to know where = can I find=20 support for that.
Thank You,Alon
 
- ------=_NextPart_000_015A_01C198FE.83E54380-- ------------------------------ Date: Wed, 9 Jan 2002 09:40:10 -0800 From: "Mohan, Prabhu" Subject: RE: s2ibis problems This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. - ------_=_NextPart_001_01C19934.AF8E1D00 Content-Type: text/plain; charset="windows-1255" Hi Alon, Can you explain what your problem is? Prabhu - -----Original Message----- From: Alon Levi [mailto:alon@silicon-value.com] Sent: Wednesday, January 09, 2002 1:12 AM To: ibis-users@eda.org Subject: s2ibis problems Hello, I have some problems with s2ibis input file,I would like to now if some of you is dealing with that and can help me,if not I will glad to know where can I find support for that. Thank You,Alon - ------_=_NextPart_001_01C19934.AF8E1D00 Content-Type: text/html; charset="windows-1255"
Hi Alon,
 
Can you explain what your problem is?
 
Prabhu
-----Original Message-----
From: Alon Levi [mailto:alon@silicon-value.com]
Sent: Wednesday, January 09, 2002 1:12 AM
To: ibis-users@eda.org
Subject: s2ibis problems

Hello,
I have some problems with s2ibis input file,I would like to now if some of you  is dealing with that and can help me,if not
I will glad to know where can I find support for that.
Thank You,Alon
 
- ------_=_NextPart_001_01C19934.AF8E1D00-- ------------------------------ Date: Thu, 10 Jan 2002 14:18:37 +0900 From: Takanobu Ura Subject: ibischk3 ver 3.2.8 and Open_drain I have two question. a/ When POWERCLamp/GNDClamp is indicated to the IBIS file of Open_drain Buffer, why is it that an error is displayed? ERROR - Model NOD: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture]=3.3V has TYP column DC endpoints of 1.15V and 3.30v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.61V and 1.15V), a difference of 87.39% and 187.07%, respectively. b/ Is it bad if the table of POWERClamp/GNDClamp exists in the IBIS file of Open_drain Buffer? - - T.ura ------------------------------ Date: Thu, 10 Jan 2002 10:51:13 -0500 From: "Ingraham, Andrew" Subject: Re: ibischk3 ver 3.2.8 and Open_drain Looking at your data, I suspect there is something wrong with the I-V tables. I would expect an open-drain output to go to V_fixture (3.3V) when OFF. Yet the I-V curves suggest it only reaches 1.15V when OFF. Also it is very suspicious that the waveform starts at 1.15V (with the output steady-state ON), but the I-V curves suggest the same exact value when OFF. Sounds to me like something is backwards. I don't think there is anything wrong about having both [POWER Clamp] and [GND Clamp] with an open-drain output. Regards, Andy ------------------------------ Date: Thu, 10 Jan 2002 11:13:28 -0500 From: "Todd Westerhoff" Subject: "Kumar Was Right" store items updated Boy, am I embarrassed! When I added the new items to the "Kumar Was Right" store - Microfiber Cap - $12.99 Tote Bag - $12.99 Boxer Shorts - $12.99 ... I forgot to add images to them. Since you can buy a blank white pair of boxer shorts, ball cap or tote bag just about anywhere, that didn't seem like a very good idea. So - the new items have been updated with images. The Kumar memorabilia on-line store is found at: http://www.cafepress.com/kumar_right For those of you who rushed out and bought the new items - if they arrive blank - please contact me about a refund. Please note that we cannot provide a full refund for the boxer shorts, although pro-rating is negotiable. Todd ;-) Todd Westerhoff SI Engineer - Hammerhead Networks 5 Federal Street - Billerica, MA - 01821 email:twester@hhnetwk.com - ph: 978-671-5084 ============================================ "Oh, but ain't that America, for you and me Ain't that America, we're something to see Ain't that America, Home of the Free Little pink houses, for you and me" - - John Mellencamp ------------------------------ Date: Fri, 11 Jan 2002 19:20:31 +0900 From: Takanobu Ura Subject: Re: ibischk3 ver 3.2.8 and Open_drain Dear Tom Dagostino Dear Ingraham, Andrew Thank you for advice. I have misstaken I-V table of GNDClamp. GNDClamp was not measured in the state of High Impedance. Thank you very much. Regards, T.Ura "Dagostino, Tom" wrote: > > Power and ground clamps should be OK. I'm curious about the error, can I have a look at the file? I've seen similar errors when there were repeated voltage values in the IV tables. "Ingraham, Andrew" wrote: > > Looking at your data, I suspect there is something wrong with the I-V > tables. > > I would expect an open-drain output to go to V_fixture (3.3V) when OFF. > Yet the I-V curves suggest it only reaches 1.15V when OFF. > > Also it is very suspicious that the waveform starts at 1.15V (with the > output steady-state ON), but the I-V curves suggest the same exact value > when OFF. Sounds to me like something is backwards. > > I don't think there is anything wrong about having both [POWER Clamp] > and [GND Clamp] with an open-drain output. > > Regards, > Andy ------------------------------ Date: Mon, 14 Jan 2002 13:38:40 -0800 (PST) From: Syed Huq Subject: Cleanup/update of IBIS Roster page 2002 Hi, Pls take some time to review your company entries in the IBIS Roster at : http://www.vhdl.org/pub/ibis/roster/roster.html Some of the entries may be old/missing etc. We would like to keep these records as current as possible and your help is needed. If we do not hear back from you in 2 weeks, the company entry may be removed and archieved. Thanks in advance for your prompt response. Regards, Syed webmaster ------------------------------ Date: Mon, 14 Jan 2002 15:35:26 -0800 (PST) From: Syed Huq Subject: Cleanup/update of IBIS Roster - resending Hi, Pls take a moment to review your company entries in the IBIS roster at: http://www.vhdl.org/pub/ibis/roster/roster.html Some information may have changed or are missing. We want this roster to have the most updated information so your review is essential. Pls provide your inputs so I can update the page. If I don't hear from you in 2 weeks, your entry may be removed and archieved. Thanks in advance, Syed webmaster ------------------------------ Date: Wed, 16 Jan 2002 15:25:40 -0800 From: Khalid Ansari Subject: Errors while running runs2i Hi all, I am new to IBIS. I have a macro for which basically I have created a directory and put in the directory the .sp file and .inc file, these are my hspice files. The macro is for a bi-directional I/O. I run the mks2i script and generate a .s2i file. I polish up the .s2i with the right package RLC and the other values and then do the runs2i script. I did the same for one other input cell and the curves were generated right. With this bi-directional one I get errors and the script doesn't generate any curves. I went through all the .out files created by running the script and I found in two different .out files that there were errors: File name= rdxpad.out...error = "could not close save file = rdxpad.ic". File name= runpad.out...error = "could not close save file = runpad.ic". Anybody know what these errors mean? How do you go about troubleshooting when running these scripts...what are the things to look for? Thanks in advance, Khalid ------------------------------ Date: Thu, 17 Jan 2002 18:11:55 -0800 (PST) From: Syed Huq Subject: Re: Errors while running runs2i Khalid, The two filenames indicate: rdxpad.out: Ramp Down Max Pad runpad.out: Ramp Up Min Pad Look at the .spi files for each and make sure the setup looks correct for a Ramp simulation. If your rdtpad.out or rutpad.out had no errors(this is for Typ case), you can compare that to the ones that failed to see what happened. My guess is your .s2i file for a I/O is not set correctly or.. Which SPICE are you running and on what platform ? Syed > X-Sender: khalida@mailhost-sv > Date: Wed, 16 Jan 2002 15:25:40 -0800 > To: ibis-users@eda.org > From: Khalid Ansari > Subject: Errors while running runs2i > Cc: ibis-support > Mime-Version: 1.0 > > Hi all, > > I am new to IBIS. I have a macro for which basically I have > created a directory and put in the directory the .sp file and .inc file, > these are my hspice files. The macro is for a bi-directional I/O. I > run the mks2i script and generate a .s2i file. I polish up the .s2i > with the right package RLC and the other values and then > do the runs2i script. I did the same for one other input cell and the > curves were generated right. With this bi-directional one I get errors > and the script doesn't generate any curves. I went through all the .out > files created by running the script and I found in two different .out files > that there were errors: > > File name= rdxpad.out...error = "could not close save file = rdxpad.ic". > File name= runpad.out...error = "could not close save file = runpad.ic". > > Anybody know what these errors mean? How do you go about > troubleshooting when running these scripts...what are the things > to look for? > > Thanks in advance, > Khalid > ------------------------------ Date: Fri, 18 Jan 2002 16:35:52 -0800 From: "Peters, Stephen" Subject: IBIS DesignCon2002 Summit Meeting Agenda To IBIS Summit Meeting Attendees: We will have a full day of great presentations and interesting discussions. If you are planning to attend and have lunch, please sign up with Milt Schwartz, if you have not done so, at schwartz@galaxy.nsc.com We are looking forward to seeing you at the Summit. Regards, Stephen Peters Intel Corp. Chair, EIA/IBIS Open Forum - ------------------------------------------------------------------ AGENDA, IBIS SUMMIT MEETING JANUARY 28, 2002 Westin Hotel Santa Clara Convention Center Santa Clara, California Room: Magnolia Room, Weston Hotel (check signs at site) - ------------------------------------------------------------------ 8:00 AM Refreshments & Sign In 8:30 AM Introductions - Welcome to Summit - Introductions - IBIS Booth #704 Placards - Opens for Issues, Discussion Topics 8:45 AM IBIS Users Experience Barry Katz, Signal Integrity Software 9:15 AM A Critique of IBIS Models Available for Download on the Web Jim Bell, SiQual 9:45 AM IBIS Accuracy at IBM Greg Edlund, IBM 10:15 AM Break 10:30 AM JEITA EDA Activity and Proposal Atsuji Ito, Panasonic 11:15 PM Lossy Line Characterization and Modeling for SPICE and IBIS Steve Corey, Time Domain Analysis Systems 11:45 AM Connector Specification Discussion Gus Panella, Molex 12:00 PM Lunch - (Hosted by National Semiconductor) Westin Hotel 1:00 PM IBIS/XML Atul Agarwal, Apt Software Avenues 1:30 PM EMC Presentation Guy de Burgh, Innoveda 2:00 PM ICEM Model Sebastien Calvet, Motorola Semiconductor 2:30 PM Break 2:45 AM IBIS Version 4.0 Bob Ross, Mentor Graphics 3:00 PM Multi-lingual Model Support within IBIS Bob Ross, Mentor Graphics 3:30 PM IBIS Futures and Discussion Stephen Peters, Intel 4:30 PM Open Discussion and Ad Hoc Topics All 4:45 PM Concluding Items - Next Meeting February 22, 2002 - Date 2002 IBIS Summit March 8, 2002 5:00 PM End of IBIS Summit Meeting - ------------------------------------------------------------------ ------------------------------ Date: Mon, 21 Jan 2002 10:59:14 -0500 From: "Pritchard, Jason" Subject: PV/PT Tables IBIS Hello all, When creating an IBIS model, how does the test resistor chosen to create the PV/PT tables affect the rising and falling waveforms in simulation? If i use a 500 ohm resistor vs. a 50 ohm resistor, the pv/pt tables generated will be much different. What is the simulator doing with this data, and what are the correct values to use when creating an IBIS or XTK model? Thanks, Jason ------------------------------ Date: Mon, 21 Jan 2002 08:16:08 -0800 From: "Muranyi, Arpad" Subject: RE: [SI-LIST] PV/PT Tables IBIS Jason, The resistor value should be a value close to the transmission line impedance the buffer is designed to drive. This is how the model is most accurate. Most algorithms use these waveforms as if they were a percentage vs. time table, scaling the IV curves with respect to time. So the actual voltage values are not as important as some may think. Arpad Muranyi Intel Corporation ==================================================================== - -----Original Message----- From: Pritchard, Jason [mailto:jasonp@tenornetworks.com] Sent: Monday, January 21, 2002 7:59 AM To: si-list@freelists.org; 'ibis-users@eda.org' Subject: [SI-LIST] PV/PT Tables IBIS Hello all, When creating an IBIS model, how does the test resistor chosen to create the PV/PT tables affect the rising and falling waveforms in simulation? If i use a 500 ohm resistor vs. a 50 ohm resistor, the pv/pt tables generated will be much different. What is the simulator doing with this data, and what are the correct values to use when creating an IBIS or XTK model? Thanks, Jason - ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@freelists.org with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@freelists.org with 'help' in the Subject field List archives are viewable at: http://www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------ Date: Mon, 21 Jan 2002 09:51:08 -0800 From: Khalid Ansari Subject: Re: Errors while running runs2i Syed, I was able to execute runs2i successfully. The reason why I was running into all kinds of errors was that my disk space was full. Thanks a lot for your response. By the way I just started using IBIS and got a chance to read the IBIS documents floating around on the net, created by you. They were very helpful. Thanks, Khalid At 06:11 PM 1/17/02 -0800, Syed Huq wrote: >Khalid, > >The two filenames indicate: > >rdxpad.out: Ramp Down Max Pad >runpad.out: Ramp Up Min Pad > >Look at the .spi files for each and make sure the setup looks correct >for a Ramp simulation. > >If your rdtpad.out or rutpad.out had no errors(this is for Typ case), >you can compare that to the ones that failed to see what happened. > >My guess is your .s2i file for a I/O is not set correctly or.. > >Which SPICE are you running and on what platform ? > >Syed > > > X-Sender: khalida@mailhost-sv > > Date: Wed, 16 Jan 2002 15:25:40 -0800 > > To: ibis-users@eda.org > > From: Khalid Ansari > > Subject: Errors while running runs2i > > Cc: ibis-support > > Mime-Version: 1.0 > > > > Hi all, > > > > I am new to IBIS. I have a macro for which basically I have > > created a directory and put in the directory the .sp file and .inc file, > > these are my hspice files. The macro is for a bi-directional I/O. I > > run the mks2i script and generate a .s2i file. I polish up the .s2i > > with the right package RLC and the other values and then > > do the runs2i script. I did the same for one other input cell and the > > curves were generated right. With this bi-directional one I get errors > > and the script doesn't generate any curves. I went through all the .out > > files created by running the script and I found in two different .out >files > > that there were errors: > > > > File name= rdxpad.out...error = "could not close save file = rdxpad.ic". > > File name= runpad.out...error = "could not close save file = runpad.ic". > > > > Anybody know what these errors mean? How do you go about > > troubleshooting when running these scripts...what are the things > > to look for? > > > > Thanks in advance, > > Khalid > > ------------------------------ Date: Mon, 21 Jan 2002 16:03:20 -0800 From: Khalid Ansari Subject: Simulating IBIS models using XTK Hi all, I have my IBIS model created. Now, I need to run simulations on this model. XTK is available to me to run the simulations but I don't have any experience running XTK. Something quick has come up and I need to run some simulations. Is there any literature somewhere that can bring me upto speed on running simulations on IBIS models using XTK quickly. Thanks in advance, Khalid ------------------------------ Date: Mon, 21 Jan 2002 17:31:19 -0800 From: Alan Hilton-Nickel Subject: Re: Simulating IBIS models using XTK Khalid, If you're talking about running XTK in native mode (writing text-file topologies and all that) there is a fairly big learning curve. If you also have access to Scratchpad (part of the ePlanner module) you can easily hack your files into something useable. Scratchpad has standard Transmission line, driver, receiver and terminator elements, with a drag and drop interface. You can use it to set up a topology, and then substitute in the required IBIS model for the driver and receiver. Other than that, there is only the XTK User's Manual, which does have some decent, simple examples. Alan Hilton-Nickel Transmeta Corp. Khalid Ansari wrote: > > Hi all, > > I have my IBIS model created. Now, I need to run simulations on > this model. XTK is available to me to run the simulations but > I don't have any experience running XTK. Something quick has > come up and I need to run some simulations. Is there any > literature somewhere that can bring me upto speed on running > simulations on IBIS models using XTK quickly. > > Thanks in advance, > Khalid ------------------------------ Date: Wed, 23 Jan 2002 11:07:10 -0500 From: Mark Bossard Subject: Ibis Tools? Hi, What tools are available (and for what operating systems) to use and verify IBIS models? Thanks in advance, Mark Bossard - -- ======================================================================== | Mark Bossard | Atmel Corporation | | Direct Phone: (410) 423-4352 | Chesapeake Design Center | | Main Phone: (410) 423-4300 | 8820 Columbia 100 Parkway | | Fax: (410) 423-4302 | Suite 300 | | Email: mbossard@atmel.com | Columbia, MD 21045 | ======================================================================== ------------------------------ Date: Wed, 23 Jan 2002 08:26:54 -0800 From: "Muranyi, Arpad" Subject: RE: Ibis Tools? Mark, I am not sure if I understood your question correctly, but there are many tools that can use IBIS models. HSPICE, Cadence, Interconnectix, XTK, just to name a few. Regarding verification, you can use these tools to run simulations that have the same conditions as your measurements in the lab, and then you can overlay the waveforms either in these tools, or using EXCEL, or other graphical plotting tools. Arpad Muranyi Intel Corporation ====================================================== - -----Original Message----- From: Mark Bossard [mailto:mbossard@atmel.com] Sent: Wednesday, January 23, 2002 8:07 AM To: ibis-users@server.eda.org Subject: Ibis Tools? Hi, What tools are available (and for what operating systems) to use and verify IBIS models? Thanks in advance, Mark Bossard - -- ======================================================================== | Mark Bossard | Atmel Corporation | | Direct Phone: (410) 423-4352 | Chesapeake Design Center | | Main Phone: (410) 423-4300 | 8820 Columbia 100 Parkway | | Fax: (410) 423-4302 | Suite 300 | | Email: mbossard@atmel.com | Columbia, MD 21045 | ======================================================================== ------------------------------ Date: Wed, 23 Jan 2002 10:22:39 -0800 From: Khalid Ansari Subject: Re: Simulating IBIS models using XTK Alan, Bill, Tadashi and others, Thank you all for your responses. I use HSpice quite a bit. I guess I can run the simulations in Hspice too since I don't have Scratchpad. When converting IBIS models to Hspice compatible using ibis2spice is there any chances of me loosing any important part of the IBIS model? Khalid At 05:31 PM 1/21/02 -0800, Alan Hilton-Nickel wrote: >Khalid, > >If you're talking about running XTK in native mode (writing text-file >topologies >and all that) there is a fairly big learning curve. If you also have access to >Scratchpad (part of the ePlanner module) you can easily hack your files into >something useable. Scratchpad has standard Transmission line, driver, receiver >and terminator elements, with a drag and drop interface. You can use it to set >up a topology, and then substitute in the required IBIS model for the >driver and >receiver. > >Other than that, there is only the XTK User's Manual, which does have some >decent, simple examples. > >Alan Hilton-Nickel >Transmeta Corp. > >Khalid Ansari wrote: > > > > Hi all, > > > > I have my IBIS model created. Now, I need to run simulations on > > this model. XTK is available to me to run the simulations but > > I don't have any experience running XTK. Something quick has > > come up and I need to run some simulations. Is there any > > literature somewhere that can bring me upto speed on running > > simulations on IBIS models using XTK quickly. > > > > Thanks in advance, > > Khalid ------------------------------ Date: Wed, 23 Jan 2002 12:08:16 -0800 (PST) From: Syed Huq Subject: Re: Simulating IBIS models using XTK You could use the B-element in HSPICE to simulate IBIS. So no need to use ibis2spice.. Syed > X-Sender: khalida@mailhost-sv > Date: Wed, 23 Jan 2002 10:22:39 -0800 > To: Alan Hilton-Nickel > From: Khalid Ansari > Subject: Re: Simulating IBIS models using XTK > Cc: ibis-users@eda.org, ibis-support@nqesv1.nms.nec.co.jp > Mime-Version: 1.0 > > Alan, Bill, Tadashi and others, > > Thank you all for your responses. > > I use HSpice quite a bit. I guess I can run the simulations in > Hspice too since I don't have Scratchpad. When converting IBIS > models to Hspice compatible using ibis2spice is there any chances > of me loosing any important part of the IBIS model? > > Khalid > > At 05:31 PM 1/21/02 -0800, Alan Hilton-Nickel wrote: > >Khalid, > > > >If you're talking about running XTK in native mode (writing text-file > >topologies > >and all that) there is a fairly big learning curve. If you also have access to > >Scratchpad (part of the ePlanner module) you can easily hack your files into > >something useable. Scratchpad has standard Transmission line, driver, receiver > >and terminator elements, with a drag and drop interface. You can use it to set > >up a topology, and then substitute in the required IBIS model for the > >driver and > >receiver. > > > >Other than that, there is only the XTK User's Manual, which does have some > >decent, simple examples. > > > >Alan Hilton-Nickel > >Transmeta Corp. > > > >Khalid Ansari wrote: > > > > > > Hi all, > > > > > > I have my IBIS model created. Now, I need to run simulations on > > > this model. XTK is available to me to run the simulations but > > > I don't have any experience running XTK. Something quick has > > > come up and I need to run some simulations. Is there any > > > literature somewhere that can bring me upto speed on running > > > simulations on IBIS models using XTK quickly. > > > > > > Thanks in advance, > > > Khalid > ------------------------------ Date: Wed, 23 Jan 2002 15:26:50 -0500 From: Mark Bossard Subject: Re: Ibis Tools? Arpad, I apologize for not stating my question more clearly. I work with ASICs, so my involvement with IBIS is generating IBIS models for I/O using HSPICE simulations. For our purposes, we don't generate models on the chip scale with package parameters because the packages and buffer pinout change from project to project. What I am looking for are leads to investigate what tools are available to simulatate using IBIS models and/or assist in the tasks of verifying that the models we generate. I am trying to make sure our IBIS models are usable by our customers as well as accurate. I do use HSPICE to do some IBIS model simulations, but I am interested at looking at other tools as well. - -Mark Bossard "Muranyi, Arpad" wrote: > > Mark, > > I am not sure if I understood your question correctly, > but there are many tools that can use IBIS models. > HSPICE, Cadence, Interconnectix, XTK, just to name a > few. Regarding verification, you can use these tools > to run simulations that have the same conditions as > your measurements in the lab, and then you can > overlay the waveforms either in these tools, or using > EXCEL, or other graphical plotting tools. > > Arpad Muranyi > Intel Corporation > ====================================================== > > -----Original Message----- > From: Mark Bossard [mailto:mbossard@atmel.com] > Sent: Wednesday, January 23, 2002 8:07 AM > To: ibis-users@server.eda.org > Subject: Ibis Tools? > > Hi, > > What tools are available (and for what operating systems) to use and > verify IBIS models? > > Thanks in advance, > > Mark Bossard > > -- > > ======================================================================== > | Mark Bossard | Atmel Corporation | > | Direct Phone: (410) 423-4352 | Chesapeake Design Center | > | Main Phone: (410) 423-4300 | 8820 Columbia 100 Parkway | > | Fax: (410) 423-4302 | Suite 300 | > | Email: mbossard@atmel.com | Columbia, MD 21045 | > ======================================================================== - -- ======================================================================== | Mark Bossard | Atmel Corporation | | Direct Phone: (410) 423-4352 | Chesapeake Design Center | | Main Phone: (410) 423-4300 | 8820 Columbia 100 Parkway | | Fax: (410) 423-4302 | Suite 300 | | Email: mbossard@atmel.com | Columbia, MD 21045 | ======================================================================== ------------------------------ Date: Wed, 23 Jan 2002 12:42:16 -0800 From: "Muranyi, Arpad" Subject: RE: Simulating IBIS models using XTK Khalid, You don't need to do any conversion if you want to use HSPICE with IBIS models. They have now a B-element which can read IBIS files directly. Arpad Muranyi Intel Corporation ============================================================== - -----Original Message----- From: Khalid Ansari [mailto:khalida@vitesse.com] Sent: Wednesday, January 23, 2002 10:23 AM To: Alan Hilton-Nickel Cc: ibis-users@eda.org; ibis-support@nqesv1.nms.nec.co.jp Subject: Re: Simulating IBIS models using XTK Alan, Bill, Tadashi and others, Thank you all for your responses. I use HSpice quite a bit. I guess I can run the simulations in Hspice too since I don't have Scratchpad. When converting IBIS models to Hspice compatible using ibis2spice is there any chances of me loosing any important part of the IBIS model? Khalid ------------------------------ Date: Wed, 23 Jan 2002 19:16:23 -0800 From: "Ross, Bob" Subject: European IBIS Summmit - Second Announcement To All: This is the second announcement of the European IBIS Summit meeting held during DATE 2002 in Paris for presentations and participation. Bob Ross Mentor Graphics E U R O P E A N I B I S S U M M I T M E E T I N G S E C O N D A N N O U N C E M E N T Time/Date: 8:30 AM - 2 PM, Friday, March 8, 2002 Location: Concorde-Lafayette Hotel (adjacent to Le Palais des Congress de Paris Prote Mailot - site of the DATE2002 Conference) in Paris, France Rooms: Salon Van Gogh/Pissarro Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: EADS, Innoveda, Mentor Graphics DATE2000: March 4-8, 2002. The IBIS meeting is scheduled the day following the trade show portion of the Conference See http://www.date-conference.com for more information. BACKGROUND For the last several years we have been holding very successful European IBIS Summit Meetings. We plan a combination of the following: Submitted Presentations on IBIS Topics (See below) Less formal Ad Hoc Presentations and Discussions IBIS Questions and Answers Below is an invitation to register and also to submit presentations. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the European IBIS Summit meeting. If you plan to participate, please supply the information below: Name: E-mail address: Company: Telephone: Send to: Karine Loudet (karine_loudet@mentor.com) CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. Some suggested subjects of interest are: IBIS Model Development Experiences Company IBIS Standards and Requirements Generating and Validating IBIS Models Future IBIS Requirements EMC/EMI IBIS Issues Format of Presentation: Overhead Projections Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat. Please plan to bring copies of your presentation to distribute at the meeting. If you plan a presentation, please supply Title: Presenter: E-mail address: Company: Telephone: Estimate Time: Send this to: Bob Ross (bob_ross@mentor.com) AGENDA The agenda includes presentations, discussions, and a free lunch. FOR FURTHER INFORMATION: Bob Ross, Vice Chair, EIA/IBIS Open Forum Mentor Graphics 8005 S.W. Boeckman Road Wilsonville, Oregon 97070 USA (503) 685-0732 bob_ross@mentor.com ------------------------------ Date: Thu, 24 Jan 2002 14:35:56 -0800 From: Khalid Ansari Subject: RE: Simulating IBIS models using XTK Hi all, I am using the B element of HSPICE ( as recommended by the gurus) to simulate my IBIS model that I created. This IBIS model is for TTL I/Os that I created using the s2ibis utility. The complete model looks fine but when I simulate one of the macro models I see a digital signal rather than an analog signal that I should see at the output. When I take the hspice deck for the TTL I/O and simulate it I see a nice analog signal at the end. This, I believe but the B element simulation of the IBIS model I do not believe. Basically this is what it looks like: --------------- * * * - -------------------------------- for the hspice output and -------------- * * * - ------------------------------------- for the IBIS output. What could I be doing wrong here? Any inputs will be appreciated. My hspice deck with the b element looks like this: .option post probe .option accurate .opt dv=1 vin nd_in 0 pulse(0.8 2.0 2.0ns 1ns 1ns 2ns 6ns) b1 nd_pc nd_gc nd_in nd_out_of_in + file = '871.ibs' model = 'pnl_it2nn8' rpadx nd_in nd_inx 2 .op all cload nd_out_of_in 0 20ff .probe tran v(nd_in) .probe tran v(nd_out_of_in) .tran 5ps 5ns .end Thanks, Khalid At 12:42 PM 1/23/02 -0800, Muranyi, Arpad wrote: >Khalid, > >You don't need to do any conversion if you want to use HSPICE >with IBIS models. They have now a B-element which can read IBIS >files directly. > >Arpad Muranyi >Intel Corporation >============================================================== > >-----Original Message----- >From: Khalid Ansari [mailto:khalida@vitesse.com] >Sent: Wednesday, January 23, 2002 10:23 AM >To: Alan Hilton-Nickel >Cc: ibis-users@eda.org; ibis-support@nqesv1.nms.nec.co.jp >Subject: Re: Simulating IBIS models using XTK > > >Alan, Bill, Tadashi and others, > >Thank you all for your responses. > >I use HSpice quite a bit. I guess I can run the simulations in >Hspice too since I don't have Scratchpad. When converting IBIS >models to Hspice compatible using ibis2spice is there any chances >of me loosing any important part of the IBIS model? > >Khalid ------------------------------ Date: Thu, 24 Jan 2002 16:35:23 -0500 From: "ruston, matt" Subject: SpectraQuest timing measurement All: Hi. I have a specific question regarding Spectraquest SigXplorer. Under analysis/measurement modes, they give me the option to "measure delays at" either Input Thresholds or Vmeasure. It seems to me that I want a hybrid of these two options. I want to measure the driver output at the Vmeasure point of the driver to correlate to standard load timing. I then want to use the Input threshold of the receiver (either Vil or Vih, depending on low-to-high or high-to-low transition). Am I mis-reading what my options are? Does what I want make sense? Any and all thoughts and experiences are welcome. Regards, Matt ------------------------------ Date: Thu, 24 Jan 2002 14:44:01 -0800 From: Khalid Ansari Subject: RE: Simulating IBIS models using XTK Hi all, I am using the B element of HSPICE ( as recommended by the gurus) to simulate my IBIS model that I created. This IBIS model is for TTL I/Os that I created using the s2ibis utility. The complete model looks fine but when I simulate one of the macro models I see a digital signal rather than an analog signal that I should see at the output. When I take the hspice deck for the TTL I/O and simulate it I see a nice analog signal at the end. This, I believe but the B element simulation of the IBIS model I do not believe. Basically this is what it looks like: --------------- * * * - ----------------------------- for the hspice output and -------------- * * * - ---------------------------------- for the IBIS output. What could I be doing wrong here? Any inputs will be appreciated. My hspice deck with the b element looks like this: .option post probe .option accurate .opt dv=1 vin nd_in 0 pulse(0.8 2.0 2.0ns 1ns 1ns 2ns 6ns) b1 nd_pc nd_gc nd_in nd_out_of_in + file = '871.ibs' model = 'pnl_it2nn8' rpadx nd_in nd_inx 2 .op all cload nd_out_of_in 0 20ff .probe tran v(nd_in) .probe tran v(nd_out_of_in) .tran 5ps 5ns .end Thanks, Khalid At 12:42 PM 1/23/02 -0800, Muranyi, Arpad wrote: Khalid, You don't need to do any conversion if you want to use HSPICE with IBIS models. They have now a B-element which can read IBIS files directly. Arpad Muranyi Intel Corporation ============================================================== - -----Original Message----- From: Khalid Ansari [mailto:khalida@vitesse.com] Sent: Wednesday, January 23, 2002 10:23 AM To: Alan Hilton-Nickel Cc: ibis-users@eda.org; ibis-support@nqesv1.nms.nec.co.jp Subject: Re: Simulating IBIS models using XTK Alan, Bill, Tadashi and others, Thank you all for your responses. I use HSpice quite a bit. I guess I can run the simulations in Hspice too since I don't have Scratchpad. When converting IBIS models to Hspice compatible using ibis2spice is there any chances of me loosing any important part of the IBIS model? Khalid ------------------------------ Date: Thu, 24 Jan 2002 15:03:46 -0800 From: "Muranyi, Arpad" Subject: RE: Simulating IBIS models using XTK Khalid, The B-element is kind of like a mixed mode model, it has digital-like control signals, input, enable and the analog node that connects to the world, such as T-line, etc. If you have an input or I/O type model, there is another digital-like node, the "out of in" which represents the core side of the receiver. The meaning of this signal is a "0" or "1" based on what the threshold and the waveform in puts analog input was. You need to study the manual a little more in detail to get all this cleared up... Arpad ========================================================== - -----Original Message----- From: Khalid Ansari [mailto:khalida@vitesse.com] Sent: Thursday, January 24, 2002 2:36 PM To: Muranyi, Arpad; ibis-users@eda.org; ibis-support@nqesv1.nms.nec.co.jp Subject: RE: Simulating IBIS models using XTK Hi all, I am using the B element of HSPICE ( as recommended by the gurus) to simulate my IBIS model that I created. This IBIS model is for TTL I/Os that I created using the s2ibis utility. The complete model looks fine but when I simulate one of the macro models I see a digital signal rather than an analog signal that I should see at the output. When I take the hspice deck for the TTL I/O and simulate it I see a nice analog signal at the end. This, I believe but the B element simulation of the IBIS model I do not believe. Basically this is what it looks like: --------------- * * * - -------------------------------- for the hspice output and -------------- * * * - ------------------------------------- for the IBIS output. What could I be doing wrong here? Any inputs will be appreciated. My hspice deck with the b element looks like this: .option post probe .option accurate .opt dv=1 vin nd_in 0 pulse(0.8 2.0 2.0ns 1ns 1ns 2ns 6ns) b1 nd_pc nd_gc nd_in nd_out_of_in + file = '871.ibs' model = 'pnl_it2nn8' rpadx nd_in nd_inx 2 .op all cload nd_out_of_in 0 20ff .probe tran v(nd_in) .probe tran v(nd_out_of_in) .tran 5ps 5ns .end Thanks, Khalid At 12:42 PM 1/23/02 -0800, Muranyi, Arpad wrote: >Khalid, > >You don't need to do any conversion if you want to use HSPICE >with IBIS models. They have now a B-element which can read IBIS >files directly. > >Arpad Muranyi >Intel Corporation >============================================================== > >-----Original Message----- >From: Khalid Ansari [mailto:khalida@vitesse.com] >Sent: Wednesday, January 23, 2002 10:23 AM >To: Alan Hilton-Nickel >Cc: ibis-users@eda.org; ibis-support@nqesv1.nms.nec.co.jp >Subject: Re: Simulating IBIS models using XTK > > >Alan, Bill, Tadashi and others, > >Thank you all for your responses. > >I use HSpice quite a bit. I guess I can run the simulations in >Hspice too since I don't have Scratchpad. When converting IBIS >models to Hspice compatible using ibis2spice is there any chances >of me loosing any important part of the IBIS model? > >Khalid ------------------------------ Date: Thu, 24 Jan 2002 16:04:35 -0800 From: "Chris Rokusek" Subject: RE: Simulating IBIS models using XTK Khalid, Perhaps your timestep isn't small enough when generating the waveform that is used to create the IBIS model? Check that there is are at least 10 points capturing the "shape" of the transition within the IBIS .ibs model itself. Also try decreasing time step when simulating the .ibs model. Just guessing... Chris Rokusek Innoveda > -----Original Message----- > From: owner-ibis-users@eda.org > [mailto:owner-ibis-users@eda.org] On Behalf Of Khalid Ansari > Sent: Thursday, January 24, 2002 2:44 PM > To: ibis-support@nqesv1.nms.nec.co.jp; ibis-users@eda.org > Subject: RE: Simulating IBIS models using XTK > > > Hi all, > > I am using the B element of HSPICE ( as recommended by > the gurus) to simulate my IBIS model that I created. This > IBIS model is for TTL I/Os that I created using the s2ibis > utility. The complete model looks fine but when I simulate > one of the macro models I see a digital signal rather than an > analog signal that I should see at the output. When I take > the hspice deck for the TTL I/O and simulate it I see a nice > analog signal at the end. This, I believe but the B element > simulation of the IBIS model I do not believe. Basically this > is what it looks like: > > --------------- > * > * > * > ----------------------------- > for the hspice output and > > -------------- > * > * > * > ---------------------------------- > for the IBIS output. > > What could I be doing wrong here? Any inputs will be appreciated. > > My hspice deck with the b element looks like this: > > .option post probe > .option accurate > .opt dv=1 > vin nd_in 0 pulse(0.8 2.0 2.0ns 1ns 1ns 2ns 6ns) > b1 nd_pc nd_gc nd_in nd_out_of_in > + file = '871.ibs' model = 'pnl_it2nn8' > rpadx nd_in nd_inx 2 > .op all > cload nd_out_of_in 0 20ff > .probe tran v(nd_in) > .probe tran v(nd_out_of_in) > .tran 5ps 5ns > .end > > > Thanks, > Khalid > > > At 12:42 PM 1/23/02 -0800, Muranyi, Arpad wrote: > Khalid, > > You don't need to do any conversion if you want to use HSPICE > with IBIS models. They have now a B-element which can read > IBIS files directly. > > Arpad Muranyi > Intel Corporation > ============================================================== > > -----Original Message----- > From: Khalid Ansari [mailto:khalida@vitesse.com] > Sent: Wednesday, January 23, 2002 10:23 AM > To: Alan Hilton-Nickel > Cc: ibis-users@eda.org; ibis-support@nqesv1.nms.nec.co.jp > Subject: Re: Simulating IBIS models using XTK > > > Alan, Bill, Tadashi and others, > > Thank you all for your responses. > > I use HSpice quite a bit. I guess I can run the simulations > in Hspice too since I don't have Scratchpad. When converting > IBIS models to Hspice compatible using ibis2spice is there > any chances of me loosing any important part of the IBIS model? > > Khalid > > > > > > > ------------------------------ Date: Fri, 25 Jan 2002 14:27:28 +0530 From: GaneshThantry Subject: Fw: convergence problem This is a multi-part message in MIME format. - --Boundary_(ID_0Bn804wIPsUDbRsmZXy4SQ) Content-type: text/plain; charset=iso-8859-1 Content-transfer-encoding: 7BIT Hi all I am facing problem related to convergence. I even modified the (.options),but iam still facing a problem. I am using HSPICE simulator,s2ibis2 tool. I even used converge in the option but the problem was still there. some of the specification i used are: 1. pull-up vg -- 1.8v 2.pulldown -- 0v 3.powerclamp -- 3.3v 4.gndclamp 0v 5.voltagerange 1.8v 6.vih 1.8v 7.vil 0v I really wanna know ,whether the convergence problem occurs due to spice-model . regards with anticipation Thantry - --Boundary_(ID_0Bn804wIPsUDbRsmZXy4SQ) Content-type: text/html; charset=iso-8859-1 Content-transfer-encoding: 7BIT
 
Hi all
 
        I am facing problem related to convergence. I even modified the
(.options),but iam still facing a problem.
 
I am  using HSPICE simulator,s2ibis2 tool. I even used converge in the option  but  the problem was still there.
 
some of the specification i used are:
 
1. pull-up vg       -- 1.8v
 2.pulldown        -- 0v
 3.powerclamp   - -- 3.3v
 4.gndclamp            0v
 5.voltagerange    1.8v
 6.vih                        1.8v
 7.vil                           0v
 
I really wanna know ,whether the convergence problem occurs due
to spice-model .
 
regards with anticipation
 
Thantry
    
- --Boundary_(ID_0Bn804wIPsUDbRsmZXy4SQ)-- ------------------------------ Date: Fri, 25 Jan 2002 07:48:52 -0500 From: "Ingraham, Andrew" Subject: Re: convergence problem SPICE convergence problems (and HSPICE is no exception here) do happen, and can be difficult to get around. There are some suggestions in the HSPICE manuals which may help, but there is no single solution that always works. If there was, they would have hard-coded it into SPICE and nobody would have convergence problems. HSPICE is said to have several algorithmic enhancements that were added to help. Alas, we still have non-convergence problems, some small, some major. Sometimes it is due to mathematical difficulties, but often it is because the models you are using, have something bad like discontinuities in them, which can be next to impossible to avoid (without fixing the models). Occasionally, you get devices which work just fine by themselves, but which fail to converge when combined into the same simulation. SPICE has a number of tolerances (options with *TOL) that you can try to make looser, but the risk then is that the results become less accurate. Regards, Andy ------------------------------ Date: Fri, 25 Jan 2002 08:09:42 -0600 From: "John Horner" Subject: RE: SPECCTRAQuest timing measurement Matt, You can get the behavior you are looking for by using the buffer delay "on the fly" measurement, and the standard "measure at input thresholds". When you use on the fly measurement, the measurement waveforms are generated for: 1) The driver into the circuit being driven 2) The waveform of the driver into the test fixture (seen as driver-bufdelay in the waveforms) 3) All the receivers. Look for buffer delay in the help documentation, it explains it pretty well. Regards, John Horner - -----Original Message----- From: ruston, matt [mailto:ruston_matt@emc.com] Sent: Thursday, January 24, 2002 3:35 PM To: ibis-users@eda.org Subject: SpectraQuest timing measurement All: Hi. I have a specific question regarding SPECCTRAQUEST SigXplorer. Under analysis/measurement modes, they give me the option to "measure delays at" either Input Thresholds or Vmeasure. It seems to me that I want a hybrid of these two options. I want to measure the driver output at the Vmeasure point of the driver to correlate to standard load timing. I then want to use the Input threshold of the receiver (either Vil or Vih, depending on low-to-high or high-to-low transition). Am I mis-reading what my options are? Does what I want make sense? Any and all thoughts and experiences are welcome. Regards, Matt ------------------------------ Date: Fri, 25 Jan 2002 12:09:02 -0500 From: "Todd Westerhoff" Subject: RE: SpectraQuest timing measurement Matt, You ALWAYS want to measure the driver output into the test load at Vmeas, because you're using that measurement to compensate for the loading condition the semiconductor vendor uses to measure Tco. SPECCTRAQuest calls that measurement "Buffer Delay", other tools call it other things. SPECCTRAQuest ALWAYS measures Buffer Delay to the Vmeas threshold, no matter how you set the "measure delays at" option. "Measure delays at" refers to the way the simulator measures flight times, BEFORE the buffer delay adjustment is made. How you set this depends on methodology and philosophy. Nominally, you'd measure flight times to Vil/Vih and subtract the buffer delay measured to Vmeas. That is the "hybrid" option you refer to, and how the SPECCTRAQuest software works by default. There is another school of thought in SI - that simply measuring flight times to Vil/Vih is too conservative. It's based on the observation that setup/hold specs for a part are measured the same way Tco is - with reference to a specific threshold. Therefore, the reasoning goes, you can measure flight times to the point where the receiver crosses the reference threshold, and, as long as the signal is within certain quality (i.e. non-monotonic) and slew-rate limits, the flight time measurement is valid. The required slew-rate is (or should be) part of the receiving device's input spec. If the input signal does NOT meet the quality/slew rate requirements, well, then you still have to use Vil/Vih, or in some cases, a derating formula. SPECCTRAQuest allows you to use either technique, and that's what the "measure delays to" switch is for. SPECCTRAQuest makes the assumption that the Vmeas voltage is the same as the input reference voltage (in the "single point" case) - not a bad assumption, and it's the only "single point" measurement voltage in the IBIS model anyway. Other tools support the two different methodologies in their own ways - I don't happen to remember. The issue is a generic one, though, and that's why I've posted it here. Which technique you use is up to you and your assessment of your design, suppliers and the accuracy of your models. Using the "measure delays to Vmeas" method certainly makes your timing equations look better, as it removes uncertainty in the flight times. However, given the number of issues SI tools typically DON'T model (like, power/ground noise), you may to use the conservative approach, to have a little timing margin left over for some of those things that go "bump" in the night. Hope that helps, Todd. Todd Westerhoff SI Engineer - Hammerhead Networks 5 Federal Street - Billerica, MA - 01821 email:twester@hhnetwk.com - ph: 978-671-5084 ============================================ "Oh, but ain't that America, for you and me Ain't that America, we're something to see Ain't that America, Home of the Free Little pink houses, for you and me" - - John Mellencamp - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org]On Behalf Of ruston, matt Sent: Thursday, January 24, 2002 4:35 PM To: ibis-users@server.eda.org Subject: SpectraQuest timing measurement All: Hi. I have a specific question regarding Spectraquest SigXplorer. Under analysis/measurement modes, they give me the option to "measure delays at" either Input Thresholds or Vmeasure. It seems to me that I want a hybrid of these two options. I want to measure the driver output at the Vmeasure point of the driver to correlate to standard load timing. I then want to use the Input threshold of the receiver (either Vil or Vih, depending on low-to-high or high-to-low transition). Am I mis-reading what my options are? Does what I want make sense? Any and all thoughts and experiences are welcome. Regards, Matt ------------------------------ Date: Wed, 30 Jan 2002 10:50:02 -0500 From: Yueming Jiang Subject: differential buffer model Hi. I'm trying to make some IBIS models for our ICs upon customer request. But I couldn't find much info as to how to deal with and differential PECL buffer. The examples in Cookbook can't really apply to differential signals. Can someone provide some information/example of differential PECL buffer modeling? Thanks a lot, Y. Jiang Tality Corp ------------------------------ Date: Wed, 30 Jan 2002 17:14:46 -0500 From: Punitha Kandasamy Subject: Request for source code of ibischk3 This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. - ------_=_NextPart_001_01C1A9DB.86BF71F0 Content-Type: text/plain; charset="iso-8859-1" Hello, I would like to request for ibischk3 source code or information about what are being checked by ibis checker3. Regards, Punitha - ------_=_NextPart_001_01C1A9DB.86BF71F0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Request for source code of ibischk3

Hello,
I would like to request for ibischk3 = source code or information about what are being checked by ibis = checker3.

Regards,
Punitha

- ------_=_NextPart_001_01C1A9DB.86BF71F0-- ------------------------------ Date: Thu, 31 Jan 2002 20:09:21 +0900 From: Takanobu Ura Subject: Warning Message (ibischk3 V3.2.x) Dear all. I have a question. What dose the following warning mean? WARNING - Model xxx: POWER Clamp : Typical value never becomes zero The below is PowerClamp infomation. [Power Clamp] 0 4.957u 5.049u 4.825u -76m 5.07u 5.376u 4.918u -152m 5.348u 6.904u 5.053u -227m 7.611u 15.19u 6.135u Is there somthing wrong with the PowerClamp? Best Regards. T.Ura ------------------------------ Date: Thu, 31 Jan 2002 20:56:14 +0900 From: Takanobu Ura Subject: Re: Warning Message (ibischk3 V3.2.x) Dear all. It is additional question. If the current of 0V becomes below 1uA, although warning will be lost, why is it? Best Regards. T.Ura Takanobu Ura wrote: > > Dear all. > > I have a question. > What dose the following warning mean? > > WARNING - > Model xxx: POWER Clamp : Typical value never becomes zero > > The below is PowerClamp infomation. > > [Power Clamp] > 0 4.957u 5.049u 4.825u > -76m 5.07u 5.376u 4.918u > -152m 5.348u 6.904u 5.053u > -227m 7.611u 15.19u 6.135u > > Is there somthing wrong with the PowerClamp? > > Best Regards. > T.Ura ------------------------------ Date: Thu, 31 Jan 2002 07:17:24 -0500 From: Mike LaBonte Subject: Re: Warning Message (ibischk3 V3.2.x) It is expected that clamps behave like diodes, and conduct no current within some voltage range. A diode certainly conducts no current with zero volts across it. If a clamp curve shows current flow with zero volts across it, there may have been an error separating the clamp curve from the output curves. It is common to force the 0V currents to 0mA. Or, there may be a terminator resistor that someone has chosen to add into the wrong clamp curve. I think it is customary to add resistors to the curve of the same rail they are attached to. Mike LaBonte Takanobu Ura wrote: > > Dear all. > > I have a question. > What dose the following warning mean? > > WARNING - > Model xxx: POWER Clamp : Typical value never becomes zero > > The below is PowerClamp infomation. > > [Power Clamp] > 0 4.957u 5.049u 4.825u > -76m 5.07u 5.376u 4.918u > -152m 5.348u 6.904u 5.053u > -227m 7.611u 15.19u 6.135u > > Is there somthing wrong with the PowerClamp? > > Best Regards. > T.Ura ------------------------------ Date: Fri, 1 Feb 2002 10:47:32 +0900 From: akimoto@lsi.nec.co.jp Subject: Re: Warning Message (ibischk3 V3.2.x) Hello, What is "diode"? Is it only "ESD diode"? Or, does it include the leak current at Hi-Z state of P-ch transistor? If the first case, we can not separate only this effect from the measurement curve. If the last case, how did you decide the limitation value as like 1uA? I cannot understand what does this WARNING warn to us. Can I ignore this WARNING? Best regards, Akimoto >It is expected that clamps behave like diodes, and conduct no >current within some voltage range. A diode certainly conducts >no current with zero volts across it. If a clamp curve shows >current flow with zero volts across it, there may have been an >error separating the clamp curve from the output curves. It is >common to force the 0V currents to 0mA. > >Or, there may be a terminator resistor that someone has chosen >to add into the wrong clamp curve. I think it is customary to >add resistors to the curve of the same rail they are attached to. > >Mike LaBonte > >Takanobu Ura wrote: >> >> Dear all. >> >> I have a question. >> What dose the following warning mean? >> >> WARNING - >> Model xxx: POWER Clamp : Typical value never becomes zero >> >> The below is PowerClamp infomation. >> >> [Power Clamp] >> 0 4.957u 5.049u 4.825u >> -76m 5.07u 5.376u 4.918u >> -152m 5.348u 6.904u 5.053u >> -227m 7.611u 15.19u 6.135u >> >> Is there somthing wrong with the PowerClamp? >> >> Best Regards. >> T.Ura > - ------------------------------------------------------ Akimoto Tetsuya Design systems Grp. System LSI Design Engineering Div. NEC Electron Devices, NEC Corporation Email:akimoto@lsi.nec.co.jp Phone:044-435-1511 ------------------------------ Date: Thu, 31 Jan 2002 23:22:36 -0500 From: Mike LaBonte Subject: Re: Warning Message (ibischk3 V3.2.x) Yes the ESD diode, or whatever circuit is used for over-voltage protection. It may be fair to propose having ibischk allow clamp currents to not quite reach zero, since real circuits show zero current only if: - - you use insensitive measuring equipment - - you simulate using approximate models - - there is no power supplied If you are an IC vendor, it may be helpful to take advantage of the Free Model Review Service described at http://www.eigroup.org/ibis/support.htm The reviewers may be able to give information on how well the various IBIS simulators will tolerate clamp curves that do not reach zero current. Mike LaBonte akimoto@lsi.nec.co.jp wrote: > > Hello, > > What is "diode"? > > Is it only "ESD diode"? > Or, does it include the leak current at Hi-Z state of > P-ch transistor? > > If the first case, we can not separate only this effect > from the measurement curve. > If the last case, how did you decide the limitation value > as like 1uA? > > I cannot understand what does this WARNING warn to us. > Can I ignore this WARNING? > > Best regards, > Akimoto > > >It is expected that clamps behave like diodes, and conduct no > >current within some voltage range. A diode certainly conducts > >no current with zero volts across it. If a clamp curve shows > >current flow with zero volts across it, there may have been an > >error separating the clamp curve from the output curves. It is > >common to force the 0V currents to 0mA. > > > >Or, there may be a terminator resistor that someone has chosen > >to add into the wrong clamp curve. I think it is customary to > >add resistors to the curve of the same rail they are attached to. > > > >Mike LaBonte > > > >Takanobu Ura wrote: > >> > >> Dear all. > >> > >> I have a question. > >> What dose the following warning mean? > >> > >> WARNING - > >> Model xxx: POWER Clamp : Typical value never becomes zero > >> > >> The below is PowerClamp infomation. > >> > >> [Power Clamp] > >> 0 4.957u 5.049u 4.825u > >> -76m 5.07u 5.376u 4.918u > >> -152m 5.348u 6.904u 5.053u > >> -227m 7.611u 15.19u 6.135u > >> > >> Is there somthing wrong with the PowerClamp? > >> > >> Best Regards. > >> T.Ura > > > ------------------------------------------------------ > Akimoto Tetsuya > Design systems Grp. System LSI Design Engineering Div. > NEC Electron Devices, NEC Corporation > Email:akimoto@lsi.nec.co.jp Phone:044-435-1511 ------------------------------ Date: Fri, 1 Feb 2002 08:00:53 -0800 From: Matthew Flora Subject: RE: ibischk3 V3.2.8 [Warning] Dear T.Ura, The warning is meant to alert you that the data in your clamp table indicates that the clamp never turns off, regardless of voltage. I know that you're probably thinking that if the data in the table is extrapolated, then the current will stop flowing at some voltage outside of the table. That is a problem, because the simulator is forced to guess the behavior of the device outside of the boundaries of the table. The simulator might use linear extrapolation, cubic-spline extrapolation, quadratic, etc. In fact, the simulator may not extrapolate at all and may use the first and last currents in the table for all voltages beyond the table (since extrapolation can result in ridiculous currents like 1e+26A). The I-V tables are supposed to include data for all of the "interesting" voltages of the buffer. The voltage at which current stops flowing is certainly "interesting" and should be included in the table. Since there may exist some technology for which current never stops or to allow for measurement/calculation inaccuracies, IBISCHK3 will not report a warning if the current get very close to zero. Very close was arbitrarily chosen to be within 1uA. It seemed reasonable. Best regards, Matthew Flora > -----Original Message----- > From: Takanobu Ura [mailto:t-ura@pb.jp.nec.com] > Sent: Friday, February 01, 2002 2:43 AM > To: ibischk-bug@eda.org > Cc: akimoto@lsi.nec.co.jp; t-ura@pb.jp.nec.com > Subject: ibischk3 V3.2.8 [Warning] > > > > Dear all: > > I have checked our model with ibisckk3. > > As for model of xxx,The following WARNING is reported. > > WARNING - > Model xxx: POWER Clamp : Typical value never becomes zero > > [Power Clamp] <- model of xxx > 0 4.957u 5.049u 4.825u > -76m 5.07u 5.376u 4.918u > -152m 5.348u 6.904u 5.053u > -227m 7.611u 15.19u 6.135u > > But,As for model of yyy, The above WARNING is not reported. > > [Power Clamp] <- model of yyy > 0 0.557u 0.949u 0.225u > -76m 0.567u 0.976u 0.229u > -152m 0.548u 0.984u 0.253u > -227m 0.611u 1.190u 0.335u > > What is the reason of this difference? > Therefore,I have any question. > a/ How did you decide the limitation value as like 1uA? > b/ I cannot understand what this WARNING warns to us. > Can I ignore this WARNING? > Because,I think that clamp current is not surely zero. > > Regards, > T.Ura > ------------------------------ Date: Mon, 4 Feb 2002 10:14:13 +0500 (GMT+0500) From: Sunil Kumar Subject: VT curves Hello, Please tell me how a simulation tool uses VT (rising and falling) curves in the simulation. Thanks Sunil Kumar Senior Research Engineer ATM Group, Switching-B2 Centre for Development of Telematics (C-DOT) 71/1 Millers Road Bangalore-52 INDIA Ph: 91-80-2263399 Ext. 217, 279 91-80-2282119 (Direct) Fax: 91-80-2282119 Email: sunilb@cdotb.ernet.in sunilb@ieee.org On Mon, 4 Feb 2002, Sunil Kumar wrote: > > ------------------------------ Date: Mon, 4 Feb 2002 15:54:57 -0500 From: "Ingraham, Andrew" Subject: Re: ibischk3 V3.2.8 [Warning] > The I-V tables are supposed to include data for all of the > "interesting" > voltages of the buffer. I wish this were so. I really do wish that IBIS had required ALL I-V tables to completely cover all normal voltages of the buffer. What is the current from the [POWER Clamp] table when the buffer voltage is 0V? Or +1.0V, or -1.0V? It doesn't say. The [POWER Clamp] table doesn't cover these voltages. It apparently assumes that the current due to the POWER Clamp should be negligible there and doesn't need to be tabulated. But what if it isn't? Or what if ... for whatever reason ... the values in the [POWER Clamp] table do not asymptotically approach zero as the buffer voltage approaches POWER? There are no IBIS rules for extrapolation. Therefore, the results are entirely unpredictable. Ugh! As noted, one simulator might continue the last current value indefinitely, another might extrapolate with a constant slope. Yet another might assume ZERO current beyond the defined I-V tables, causing a rather large discontinuity. Sure, the IBIS spec claims that "this data must not be left for the simulator to provide," but that is, unfortunately, a false statement. ------------------------------ Date: Mon, 4 Feb 2002 13:11:40 -0800 From: "Muranyi, Arpad" Subject: RE: ibischk3 V3.2.8 [Warning] Andy, The IBIS rules for the clamp curves are not saying that you cannot provide more data for your clamps (than what the rules say). This has been discussed a long time ago when I first saw the need for the POWER clamp curve needing to cover a wider range to include the currents of an on die pullup device that is used as an always on terminator. At that time the consensus in the Open Forum Committee was that we can make models covering -Vcc to 2Vcc in the clamp curves also, the spec doesn't prohibit it, it only says that the required range is what it is. So you should be able to make models for what you describe in your posting without any difficulty. Arpad Muranyi Intel Corporation ============================================================ - -----Original Message----- From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com] Sent: Monday, February 04, 2002 12:55 PM To: ibis-users@server.eda.org; ibischk-bug@server.eda.org Subject: Re: ibischk3 V3.2.8 [Warning] > The I-V tables are supposed to include data for all of the > "interesting" > voltages of the buffer. I wish this were so. I really do wish that IBIS had required ALL I-V tables to completely cover all normal voltages of the buffer. What is the current from the [POWER Clamp] table when the buffer voltage is 0V? Or +1.0V, or -1.0V? It doesn't say. The [POWER Clamp] table doesn't cover these voltages. It apparently assumes that the current due to the POWER Clamp should be negligible there and doesn't need to be tabulated. But what if it isn't? Or what if ... for whatever reason ... the values in the [POWER Clamp] table do not asymptotically approach zero as the buffer voltage approaches POWER? There are no IBIS rules for extrapolation. Therefore, the results are entirely unpredictable. Ugh! As noted, one simulator might continue the last current value indefinitely, another might extrapolate with a constant slope. Yet another might assume ZERO current beyond the defined I-V tables, causing a rather large discontinuity. Sure, the IBIS spec claims that "this data must not be left for the simulator to provide," but that is, unfortunately, a false statement. ------------------------------ End of ibis-users V1 #2 ***********************