From: owner-ibis-users@ (ibis-users)
To: ibis-users-digest@eda.org
Subject: ibis-users V1 #20
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ibis-users          Wednesday, April 30 2003          Volume 01 : Number 020




----------------------------------------------------------------------

Date: Thu, 3 Apr 2003 14:40:04 -0500
From: "Lynne Green" <lgreen@cadence.com>
Subject: RE: [IBIS-Users] IBIS connector Models

Hi, Peter,

Your question is valid for published specifications.  However, this is
still a DRAFT spec (with
major revisions over the past 5 years).  An updated draft is expected to
be released to the
IBIS Open Forum sometime in April.

Historically, EDA support for IBIS features has depended on several
things:
* A specification approved in an IBIS Open Forum vote
* Publicly available parser executable
* Vendor models using those features (and that pass the parser)
* What Marketing calls "customer demand" (i.e. people using those vendor
models).

By definition, none of those things exists for a draft spec.  (Since you
brought it up, there is
not yet a parser for IBIS 4.0.)

Now is a good time to let your favorite vendor know if you plan to use
IBIS Interconnect
models.  This gives the tool makers a "heads-up".  Also, as Sudheer
pointed out, people
might not use the new format if vendors or tools support alternate
models.

Best regards,
Lynne

Lynne Green
Cadence Design Systems

- -----Original Message-----
From: Peter LaFlamme [mailto:plaflamm@amcc.com] 
Sent: Thursday, April 03, 2003 10:50 AM
To: Lynne Green
Cc: sudheer@ecadtech.com; ibis-users@eda.org
Subject: Re: [IBIS-Users] IBIS connector Models


I think the question about which vendors support of ibis features is
valid. Maybe it should be phrased as "Does any vendor's softward support
this?" or "Does any software vendor plan to support these connector
models". 

New ibis specs and features are being added, however the software
programs that I have used still do not even support all of the features
in the IBIS 3.2 Specification, and we are at IBIS 4... Users of IBIS
models and IC vendors need to know this information since IBIS models
can be very time consuming and difficult to create. It can certainly be
a waste of time if all of the software that is available is still only
IBIS 2.1 compatible.

Regards,
Peter

- -- 
Peter LaFlamme

Applied Micro Circuits Corp.
System Applications Engineer
200 Minuteman Rd, 3rd Floor
Andover, MA 01810



Lynne Green wrote:
> 
> At this time, the IBIS Interconnect/Connector specification is still 
> in draft form.  The support of S-parameter models in Touchstone format

> might be of particular interest
> for those building models from test data .
> 
> This reflector is not a suitable place to discuss product-specific 
> details.  Vendors should be contacted for product information.
> 
> Best regards,
> Lynne
> 
> Lynne Green
> Cadence Design Systems
> 
> -----Original Message-----
> From: Sudheer B S [mailto:sudheer@ecadtech.com]
> Sent: Thursday, April 03, 2003 3:37 PM
> To: ibis-users@eda.org
> Subject: [IBIS-Users] IBIS connector Models
> 
> I have  some quections  regarding  the  IBIS connector Models
> 
> How  these  IBIS connector Models  will be helpful to  Specctraquest 
> Users ?? (because in Specctraquest  Package models will be used  for 
> connectors )
> 
> Which tool will support  these Connector Models ??
> 
> Does   these models will be helpful in Multiboard analysis ??  since
> it  takes signal name  instead of  UNSPEC
> 
>  Thank you
> 
> SUDHEER  B S
> 
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------------------------------

Date: Tue, 08 Apr 2003 10:46:03 +0300
From: Lior Aviv <RM18440@email.sps.mot.com>
Subject: [IBIS-Users] About Vmeas

Hello,

Recently, I was asked to add the Vmeas parameter to an ibis model i'm
running.
It's definition is not clear at the ibis spec.
[ Reference voltage for timing measurements ] .
Is it the total output voltage the signal should climb to
or just a part of it?

Thanks ahead for your responses

Lior Aviv,
Motorola Semiconductor Israel.

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------------------------------

Date: Tue, 8 Apr 2003 10:07:20 -0400
From: "Ingraham, Andrew" <Andrew.Ingraham@hp.com>
Subject: [IBIS-Users] RE: [IBIS] About Vmeas

Typically, Vmeas is somewhere in the middle of the waveform.  You should get its value directly from the device's data sheet.

On many data sheets, you will see timing diagrams showing input and output signals.  Quantities such as tPLH, tPHL, etc. are indicated, and are specified at specific voltages.  For TTL, and CMOS devices that use TTL levels, this voltage is usually 1.5V.  For some CMOS it may be 50% of VDD.

Andy


> Recently, I was asked to add the Vmeas parameter to an ibis model i'm
> running.
> It's definition is not clear at the ibis spec.
> [ Reference voltage for timing measurements ] .
> Is it the total output voltage the signal should climb to
> or just a part of it?
> 
> Thanks ahead for your responses
> 
> Lior Aviv,
> Motorola Semiconductor Israel.
> 
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------------------------------

Date: Fri, 11 Apr 2003 08:25:50 -0700
From: "Peters, Stephen" <stephen.peters@intel.com>
Subject: [IBIS-Users] Minutes, IBIS Open Forum Teleconference  4/18

This message is in MIME format. Since your mail reader does not understand
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                      IBIS Open Forum Meeting Agenda
                              for 4/18/03
 
               Bridge Number    Reservation #   Passcode
               1-916-356-2663       2           1139683
               (International Dial-In: 1-617-801-9781)
 
All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the 
Reservation Number and Passcode.
 
8:00 Check-In, Intros, Announcements                         Peters
 
     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Call for Patents                                      Peters
     - Membership Update and Treasurers Report               Peters
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All
 
8:15 Administrative and Project Discussions
 
     International/External Progress
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC Committee Report                                Green
 
     DAC2003 and DesignCon2003 East Meeting Planning         Peters
     - Election of Officers
 
     IBIS Version 4.0 Parser Funding and Status              Peters
 
     IBIS Quality Committee                                  Katz
 
     IBIS Model Review Committee                             Green
 
     New Administrative Issues                               All
 
8:45 Technical Discussion
 
     IBIS Connector Group Report                             Peters/Green
 
     BIRD74.2 - EMI Parameters                               de Burgh
 
     IBISCHK3 Status                                         Ross
     - BUG71 - Monotonic Checking for Combined I-V Tables    Haller
     - BUG74 - Missing Timing Test Load Warning Messages     Haller
 
     New Technical Issues                                    All
 
9:50 Wrap Up and Next Meetings Plans                         Peters
 
9:55 Sign Off

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<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<TITLE>Message</TITLE>

<META content=3D"MSHTML 6.00.2722.900" name=3DGENERATOR></HEAD>
<BODY>
<DIV align=3Dleft><FONT face=3D"Courier New"><FONT size=3D2><SPAN=20
class=3D367452315-11042003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;=20
</SPAN>IBIS Open Forum Meeting Agenda</FONT></FONT></DIV>
<DIV align=3Dleft><FONT face=3D"Courier New"><FONT size=3D2><SPAN=20
class=3D367452315-11042003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
&nbsp;</SPAN>for 4/18/03</FONT></FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;<SPAN=20
class=3D367452315-11042003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;=20
</SPAN>Bridge Number&nbsp;&nbsp;&nbsp; Reservation #&nbsp;&nbsp;=20
Passcode<BR><SPAN=20
class=3D367452315-11042003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;=20
</SPAN>&nbsp;&nbsp;&nbsp;1-916-356-2663&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;=20
2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
1139683<BR><SPAN=20
class=3D367452315-11042003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;=20
</SPAN>&nbsp;&nbsp;<SPAN class=3D367452315-11042003> =
</SPAN>(International=20
Dial-In: 1-617-801-9781)</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>All meetings are 8:00 AM to =
9:55 AM Pacific=20
Time.&nbsp; When you call into the <BR>meeting, ask for the IBIS Open =
Forum=20
hosted by Stephen Peters and give the </FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2>Reservation Number and=20
Passcode.</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>8:00 Check-In, Intros,=20
Announcements&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;=20
Peters</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp; - =
Intros of New=20
IBIS Participants, Meeting Quorum&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Peters<BR>&nbsp;&nbsp;&nbsp;&nbsp; - Call for=20
Patents&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;=20
Peters<BR>&nbsp;&nbsp;&nbsp;&nbsp; - Membership Update and Treasurers=20
Report&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;=20
Peters<BR>&nbsp;&nbsp;&nbsp;&nbsp; - Review of Previous Meeting's =
Minutes (and=20
ARs)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Peters<BR>&nbsp;&nbsp;&nbsp;&nbsp; -=20
Miscellany/Announcements&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
All<BR>&nbsp;&nbsp;&nbsp;&nbsp; - Press &amp; Web Page=20
Updates&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Huq, All<BR>&nbsp;&nbsp;&nbsp;&nbsp; - New Models Available, Library=20
Update&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Leventhal, All<BR>&nbsp;&nbsp;&nbsp;&nbsp; - Opens for New=20
Issues&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
All</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>8:15 Administrative and =
Project=20
Discussions</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp;=20
International/External Progress<BR>&nbsp;&nbsp;&nbsp;&nbsp; - IEC =
62014-3 (ICEM)=20
Integrated Circuits Electromagnetic =
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Model Proposal (IEC 93/67/NP IBIS and EMC Simulation)=20
Perrin/Peters<BR>&nbsp;&nbsp;&nbsp;&nbsp; - JEDEC Committee=20
Report&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Green</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp; =
DAC2003 and=20
DesignCon2003 East Meeting=20
Planning&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Peters<BR>&nbsp;&nbsp;&nbsp;&nbsp; - Election of Officers</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp; IBIS =
Version 4.0=20
Parser Funding and=20
Status&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;=20
Peters</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp; IBIS =
Quality=20
Committee&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Katz</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp; IBIS =
Model Review=20
Committee&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Green</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp; New =
Administrative=20
Issues&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
All</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>8:45 Technical =
Discussion</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp; IBIS =
Connector=20
Group=20
Report&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Peters/Green</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp; =
BIRD74.2 - EMI=20
Parameters&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
de Burgh<BR>&nbsp;<BR>&nbsp;&nbsp;&nbsp;&nbsp; IBISCHK3=20
Status&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Ross<BR>&nbsp;&nbsp;&nbsp;&nbsp; - BUG71 - Monotonic Checking for =
Combined I-V=20
Tables&nbsp;&nbsp;&nbsp; Haller<BR>&nbsp;&nbsp;&nbsp;&nbsp; - BUG74 - =
Missing=20
Timing Test Load Warning Messages&nbsp;&nbsp;&nbsp;&nbsp; =
Haller</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>&nbsp;&nbsp;&nbsp;&nbsp; New =
Technical=20
Issues&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
=20
All</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>9:50 Wrap Up and Next Meetings =

Plans&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;=20
Peters</FONT></DIV>
<DIV><FONT face=3D"Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2>9:55 Sign =
Off</FONT></DIV></BODY></HTML>

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------------------------------

Date: Mon, 14 Apr 2003 16:50:15 -0700
From: Wil Ngan <wngan@idt.com>
Subject: [IBIS-Users] Ibis generation problem

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Hi,

I'm having problem generating an ibis file, and was wondering
if I can get ideas in how to approach this.

1) The problem:

I get the following error when running  spice to ibis:
% s2ibis2.11 gold_7xxx.s2i
s2ibis2.11_real v1.1 -- North Carolina State University
s2ibis2.11_real: Reading input file gold_7xxx..done
s2ibis2.11_real: Analyzing component idt7xxx .
s2ibis2.11_real: Starting HSpice job with input put7.spi.
:
etc
:
s2ibis2.11_real: Starting HSpice job with input y017.spi.
s2ibis2.11_real: Starting HSpice job with input z017.spi.
s2ibis2.11_real: Opening file gold_7xxx.ibs for writing...Bus error

- -----

2) My attempt at solving this:

And so  I examine the  gold_7xxx .ibs file, and  I see the following:
:
etc
:
[Pulldown]
| voltage     I(typ)              I(min)              I(max)
|
  -3.30      -9.001A             -9.160A             -8.914A
  -3.10      -8.255A             -8.415A             -8.168A
:
etc
:
   3.50       0.178A              0.117A              0.241A
   3.60       0.179A              0.117A              0.242A
   3.70       0.179A

(The ibis file ends here, which is far from being complete.)

I have examined all the *out files (especially the pdt.out, pdx.out,
pdn.out files)
in detail and see that all hspice data has been generated and dumped
into  the
*out files with  no problem whatsoever. And yet s2ibis is apparently
having
problem extracting  the data from the  *out files to place in the *ibs
file.

Any idea how to approach or solve this problem?
Has anyone ever encountered this?
Any help or hints would be appreciated.  Thanks so much,

- - Wil
IDT  sram design
(408) 330-1623



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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hi,
<p>I'm having problem generating an ibis file, and was wondering
<br>if I can get ideas in how to approach this.
<p><b><u>1) The problem:</u></b>
<p>I get the following error when running&nbsp; spice to ibis:
<br>% s2ibis2.11 gold_7xxx.s2i
<br>s2ibis2.11_real v1.1 -- North Carolina State University
<br>s2ibis2.11_real: Reading input file gold_7xxx..done
<br>s2ibis2.11_real: Analyzing component idt7xxx .
<br>s2ibis2.11_real: Starting HSpice job with input put7.spi.
<br>:
<br>etc
<br>:
<br>s2ibis2.11_real: Starting HSpice job with input y017.spi.
<br>s2ibis2.11_real: Starting HSpice job with input z017.spi.
<br>s2ibis2.11_real: Opening file gold_7xxx.ibs for writing...Bus error
<p>-----
<p><b><u>2) My attempt at solving this:</u></b>
<p>And so&nbsp; I examine the&nbsp; gold_7xxx .ibs file, and&nbsp; I see
the following:
<br>:
<br>etc
<br>:
<br>[Pulldown]
<br>| voltage&nbsp;&nbsp;&nbsp;&nbsp; I(typ)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
I(min)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
I(max)
<br>|
<br>&nbsp; -3.30&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -9.001A&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
- -9.160A&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
- -8.914A
<br>&nbsp; -3.10&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -8.255A&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
- -8.415A&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
- -8.168A
<br>:
<br>etc
<br>:
<br>&nbsp;&nbsp; 3.50&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.178A&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
0.117A&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
0.241A
<br>&nbsp;&nbsp; 3.60&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.179A&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
0.117A&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
0.242A
<br>&nbsp;&nbsp; 3.70&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.179A
<p>(The ibis file ends here, which is far from being complete.)
<p>I have examined <b>all </b>the *out files (especially the pdt.out, pdx.out,
pdn.out files)
<br>in detail and see that <u>all hspice data<b> </b>has been generated
and dumped into&nbsp; the</u>
<br><u>*out files with&nbsp; <b>no problem </b>whatsoever</u>. <u>And yet
s2ibis is apparently having</u>
<br><b><u>problem extracting</u></b><u>&nbsp; the data from the&nbsp; *out
files to place in the *ibs file.</u>
<p>Any idea how to approach or solve this problem?
<br>Has anyone ever encountered this?
<br>Any help or hints would be appreciated.&nbsp; Thanks so much,
<p>- Wil
<br>IDT&nbsp; sram design
<br>(408) 330-1623
<br>&nbsp;
<br>&nbsp;</html>

- --------------7B4E906C5B020EAD00AD59C3--

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------------------------------

Date: Mon, 14 Apr 2003 18:05:16 -0700
From: Wil Ngan <wngan@idt.com>
Subject: [IBIS-Users] Re: Ibis generation problem

Thanks for your reply Lynne.

As I mentioned earlier, I have already looked at ALL the *out file
(these files are equivalent to *.lis in hspice, lists the entire netlist,
all model info, output data), and  I do not see any SPICE non-
convergence issues, or any other problems whatsoever.

In addition, my  diskspace are not full, max file size limit isn't
the issue, and there are no network problems.

Additionally, I have taken each *spi file (these are hspice input files
generated by s2ibis) and ran them in separate directories,
and those ran fine, too, generating *lis files that match
the *out files.

It looks like I would have to resort to parsing each *lis file
out and manually create the *.ibs file, though I don't prefer
this since it would be a very tedious and error prone process!

- - Wil



Lynne Green wrote:

> Hello, Wil,
>
> Many possible causes: SPICE convergence problem, full disk, maximum file
> size limit reached, network or system hang/crash.
>
> Best way to debug this is to look at the *.lis file for error/warning
> messages.  (If s2ibis2 deleted these files, you might need to disable
> that option.)
>
> Good luck.
>
> - Lynne
>
> Dr. Lynne Green
> Senior Member of Consulting Staff
> Cadence Design Systems, Inc.
>
> -----Original Message-----
> From: Wil Ngan [mailto:wngan@idt.com]
> Sent: Monday, April 14, 2003 4:50 PM
> Cc: ibis@eda.org; ibis-users@eda.org; ibis-info@eda.org
> Subject: Ibis generation problem
>
> Hi,
> I'm having problem generating an ibis file, and was wondering
> if I can get ideas in how to approach this.
> 1) The problem:
> I get the following error when running  spice to ibis:
> % s2ibis2.11 gold_7xxx.s2i
> s2ibis2.11_real v1.1 -- North Carolina State University
> s2ibis2.11_real: Reading input file gold_7xxx..done
> s2ibis2.11_real: Analyzing component idt7xxx .
> s2ibis2.11_real: Starting HSpice job with input put7.spi.
> :
> etc
> :
> s2ibis2.11_real: Starting HSpice job with input y017.spi.
> s2ibis2.11_real: Starting HSpice job with input z017.spi.
> s2ibis2.11_real: Opening file gold_7xxx.ibs for writing...Bus error
> -----
> 2) My attempt at solving this:
> And so  I examine the  gold_7xxx .ibs file, and  I see the following:
> :
> etc
> :
> [Pulldown]
> | voltage     I(typ)              I(min)              I(max)
> |
>   -3.30      -9.001A             -9.160A             -8.914A
>   -3.10      -8.255A             -8.415A             -8.168A
> :
> etc
> :
>    3.50       0.178A              0.117A              0.241A
>    3.60       0.179A              0.117A              0.242A
>    3.70       0.179A
> (The ibis file ends here, which is far from being complete.)
> I have examined all the *out files (especially the pdt.out, pdx.out,
> pdn.out files)
> in detail and see that all hspice data has been generated and dumped
> into  the
> *out files with  no problem whatsoever. And yet s2ibis is apparently
> having
> problem extracting  the data from the  *out files to place in the *ibs
> file.
> Any idea how to approach or solve this problem?
> Has anyone ever encountered this?
> Any help or hints would be appreciated.  Thanks so much,
> - Wil
> IDT  sram design
> (408) 330-1623

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------------------------------

Date: Mon, 14 Apr 2003 18:14:50 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Subject: [IBIS-Users] Re: [IBIS] Ibis generation problem

Wil,

Are you translating multiple buffers at the same time ? Try running the 
s2ibis2 only on an Input model or only on an Output model. There is an 
issue of creating too many .spi and .out files..

Next, you should be using s2ibis2_fix version. Your data shows you are 
using an older version..

Syed

>Date: Mon, 14 Apr 2003 16:50:15 -0700
>From: Wil Ngan <wngan@idt.com>
>X-Accept-Language: en
>MIME-Version: 1.0
>CC: ibis@eda.org, ibis-users@eda.org, ibis-info@eda.org
>Subject: [IBIS] Ibis generation problem
>
>Hi,
>
>I'm having problem generating an ibis file, and was wondering
>if I can get ideas in how to approach this.
>
>1) The problem:
>
>I get the following error when running  spice to ibis:
>% s2ibis2.11 gold_7xxx.s2i
>s2ibis2.11_real v1.1 -- North Carolina State University
>s2ibis2.11_real: Reading input file gold_7xxx..done
>s2ibis2.11_real: Analyzing component idt7xxx .
>s2ibis2.11_real: Starting HSpice job with input put7.spi.
>:
>etc
>:
>s2ibis2.11_real: Starting HSpice job with input y017.spi.
>s2ibis2.11_real: Starting HSpice job with input z017.spi.
>s2ibis2.11_real: Opening file gold_7xxx.ibs for writing...Bus error
>
>-----
>
>2) My attempt at solving this:
>
>And so  I examine the  gold_7xxx .ibs file, and  I see the following:
>:
>etc
>:
>[Pulldown]
>| voltage     I(typ)              I(min)              I(max)
>|
>  -3.30      -9.001A             -9.160A             -8.914A
>  -3.10      -8.255A             -8.415A             -8.168A
>:
>etc
>:
>   3.50       0.178A              0.117A              0.241A
>   3.60       0.179A              0.117A              0.242A
>   3.70       0.179A
>
>(The ibis file ends here, which is far from being complete.)
>
>I have examined all the *out files (especially the pdt.out, pdx.out,
>pdn.out files)
>in detail and see that all hspice data has been generated and dumped
>into  the
>*out files with  no problem whatsoever. And yet s2ibis is apparently
>having
>problem extracting  the data from the  *out files to place in the *ibs
>file.
>
>Any idea how to approach or solve this problem?
>Has anyone ever encountered this?
>Any help or hints would be appreciated.  Thanks so much,
>
>- Wil
>IDT  sram design
>(408) 330-1623
>
>

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------------------------------

Date: Mon, 14 Apr 2003 18:20:51 -0700
From: Wil Ngan <wngan@idt.com>
Subject: [IBIS-Users] Re: [IBIS] Ibis generation problem

Syed Huq wrote:

> Wil,
>
> Are you translating multiple buffers at the same time ? Try running the
> s2ibis2 only on an Input model or only on an Output model. There is an
> issue of creating too many .spi and .out files..
>

hi Syed, I'm translating only one buffer, it's an output circuit.

>
> Next, you should be using s2ibis2_fix version. Your data shows you are
> using an older version..
>

My workstation is on a sun solaris system,  I suppose the new
program/binaries
are posted on the  eda.org website?

Wil


>
> Syed
>
> >Date: Mon, 14 Apr 2003 16:50:15 -0700
> >From: Wil Ngan <wngan@idt.com>
> >X-Accept-Language: en
> >MIME-Version: 1.0
> >CC: ibis@eda.org, ibis-users@eda.org, ibis-info@eda.org
> >Subject: [IBIS] Ibis generation problem
> >
> >Hi,
> >
> >I'm having problem generating an ibis file, and was wondering
> >if I can get ideas in how to approach this.
> >
> >1) The problem:
> >
> >I get the following error when running  spice to ibis:
> >% s2ibis2.11 gold_7xxx.s2i
> >s2ibis2.11_real v1.1 -- North Carolina State University
> >s2ibis2.11_real: Reading input file gold_7xxx..done
> >s2ibis2.11_real: Analyzing component idt7xxx .
> >s2ibis2.11_real: Starting HSpice job with input put7.spi.
> >:
> >etc
> >:
> >s2ibis2.11_real: Starting HSpice job with input y017.spi.
> >s2ibis2.11_real: Starting HSpice job with input z017.spi.
> >s2ibis2.11_real: Opening file gold_7xxx.ibs for writing...Bus error
> >
> >-----
> >
> >2) My attempt at solving this:
> >
> >And so  I examine the  gold_7xxx .ibs file, and  I see the following:
> >:
> >etc
> >:
> >[Pulldown]
> >| voltage     I(typ)              I(min)              I(max)
> >|
> >  -3.30      -9.001A             -9.160A             -8.914A
> >  -3.10      -8.255A             -8.415A             -8.168A
> >:
> >etc
> >:
> >   3.50       0.178A              0.117A              0.241A
> >   3.60       0.179A              0.117A              0.242A
> >   3.70       0.179A
> >
> >(The ibis file ends here, which is far from being complete.)
> >
> >I have examined all the *out files (especially the pdt.out, pdx.out,
> >pdn.out files)
> >in detail and see that all hspice data has been generated and dumped
> >into  the
> >*out files with  no problem whatsoever. And yet s2ibis is apparently
> >having
> >problem extracting  the data from the  *out files to place in the *ibs
> >file.
> >
> >Any idea how to approach or solve this problem?
> >Has anyone ever encountered this?
> >Any help or hints would be appreciated.  Thanks so much,
> >
> >- Wil
> >IDT  sram design
> >(408) 330-1623
> >
> >

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------------------------------

Date: Mon, 14 Apr 2003 19:16:39 -0700
From: "Eric Hsu" <ehsu@netlogicmicro.com>
Subject: [IBIS-Users] What's the "s2ibis2_fix version"?

Hi,

How do I know the version of s2ibis2 is correct or not? From the Syed's mail, it mention about the log file show the wrong version message, is any one how do I tell it? Does it suppose to be "s2ibi2 v1.1 --North Carolina State University"? or "s2ibi2_fix v1.1 --North Carolina State University"?

Best Regards,

Eric Hsu
Interface Technologies
NetLogic Microsystems, Inc.
450 National Ave.
Mountain View, CA 94043
650-961-6676 x198
This e-mail contains NetLogic Microsystems, Inc. Confidential information



- -----Original Message-----
From: Syed Huq [mailto:shuq@cisco.com]
Sent: Monday, April 14, 2003 6:15 PM
To: wngan@idt.com
Cc: ibis@server.eda.org; ibis-users@server.eda.org;
ibis-info@server.eda.org
Subject: [IBIS-Users] Re: [IBIS] Ibis generation problem


Wil,

Are you translating multiple buffers at the same time ? Try running the 
s2ibis2 only on an Input model or only on an Output model. There is an 
issue of creating too many .spi and .out files..

Next, you should be using s2ibis2_fix version. Your data shows you are 
using an older version..

Syed

>Date: Mon, 14 Apr 2003 16:50:15 -0700
>From: Wil Ngan <wngan@idt.com>
>X-Accept-Language: en
>MIME-Version: 1.0
>CC: ibis@eda.org, ibis-users@eda.org, ibis-info@eda.org
>Subject: [IBIS] Ibis generation problem
>
>Hi,
>
>I'm having problem generating an ibis file, and was wondering
>if I can get ideas in how to approach this.
>
>1) The problem:
>
>I get the following error when running  spice to ibis:
>% s2ibis2.11 gold_7xxx.s2i
>s2ibis2.11_real v1.1 -- North Carolina State University
>s2ibis2.11_real: Reading input file gold_7xxx..done
>s2ibis2.11_real: Analyzing component idt7xxx .
>s2ibis2.11_real: Starting HSpice job with input put7.spi.
>:
>etc
>:
>s2ibis2.11_real: Starting HSpice job with input y017.spi.
>s2ibis2.11_real: Starting HSpice job with input z017.spi.
>s2ibis2.11_real: Opening file gold_7xxx.ibs for writing...Bus error
>
>-----
>
>2) My attempt at solving this:
>
>And so  I examine the  gold_7xxx .ibs file, and  I see the following:
>:
>etc
>:
>[Pulldown]
>| voltage     I(typ)              I(min)              I(max)
>|
>  -3.30      -9.001A             -9.160A             -8.914A
>  -3.10      -8.255A             -8.415A             -8.168A
>:
>etc
>:
>   3.50       0.178A              0.117A              0.241A
>   3.60       0.179A              0.117A              0.242A
>   3.70       0.179A
>
>(The ibis file ends here, which is far from being complete.)
>
>I have examined all the *out files (especially the pdt.out, pdx.out,
>pdn.out files)
>in detail and see that all hspice data has been generated and dumped
>into  the
>*out files with  no problem whatsoever. And yet s2ibis is apparently
>having
>problem extracting  the data from the  *out files to place in the *ibs
>file.
>
>Any idea how to approach or solve this problem?
>Has anyone ever encountered this?
>Any help or hints would be appreciated.  Thanks so much,
>
>- Wil
>IDT  sram design
>(408) 330-1623
>
>

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|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Tue, 15 Apr 2003 12:22:16 +0100
From: Mike Ventham <ventham@quantic-emc.co.uk>
Subject: [IBIS-Users] Re: [IBIS] Re: Ibis generation problem

Wil,

Typically a bus error is caused by a program problem which may be a memory
corruption or overflow. Normally this would produce a core dump unless your
environment is set to limit core dump sizes to zero.

If you have s2ibis and Hspice on another platform you could see if it
is platform specific.

The IBIS output file will not show what the program was working on at the
time as output is buffered unless the output buffer is specifically
flushed by a program call, which it was not in this case.

Normally a debugger is used to look at the traceback of the function calls
in the program at the point it crashed and then the programmer fixes it.
This obviously requires access to the source code and some programming
ability. You may need to supply the data to NCSU and see if they can fix
it. I'm not sure of the level of support as this is a "free" software tool.
Someone else may care to comment on this.


At 02:05 15/04/2003, Wil Ngan wrote:
>Thanks for your reply Lynne.
>
>As I mentioned earlier, I have already looked at ALL the *out file
>(these files are equivalent to *.lis in hspice, lists the entire netlist,
>all model info, output data), and  I do not see any SPICE non-
>convergence issues, or any other problems whatsoever.
>
>In addition, my  diskspace are not full, max file size limit isn't
>the issue, and there are no network problems.
>
>Additionally, I have taken each *spi file (these are hspice input files
>generated by s2ibis) and ran them in separate directories,
>and those ran fine, too, generating *lis files that match
>the *out files.
>
>It looks like I would have to resort to parsing each *lis file
>out and manually create the *.ibs file, though I don't prefer
>this since it would be a very tedious and error prone process!
>
>- Wil
>
>
>
>Lynne Green wrote:
>
> > Hello, Wil,
> >
> > Many possible causes: SPICE convergence problem, full disk, maximum file
> > size limit reached, network or system hang/crash.
> >
> > Best way to debug this is to look at the *.lis file for error/warning
> > messages.  (If s2ibis2 deleted these files, you might need to disable
> > that option.)
> >
> > Good luck.
> >
> > - Lynne
> >
> > Dr. Lynne Green
> > Senior Member of Consulting Staff
> > Cadence Design Systems, Inc.
> >
> > -----Original Message-----
> > From: Wil Ngan [mailto:wngan@idt.com]
> > Sent: Monday, April 14, 2003 4:50 PM
> > Cc: ibis@eda.org; ibis-users@eda.org; ibis-info@eda.org
> > Subject: Ibis generation problem
> >
> > Hi,
> > I'm having problem generating an ibis file, and was wondering
> > if I can get ideas in how to approach this.
> > 1) The problem:
> > I get the following error when running  spice to ibis:
> > % s2ibis2.11 gold_7xxx.s2i
> > s2ibis2.11_real v1.1 -- North Carolina State University
> > s2ibis2.11_real: Reading input file gold_7xxx..done
> > s2ibis2.11_real: Analyzing component idt7xxx .
> > s2ibis2.11_real: Starting HSpice job with input put7.spi.
> > :
> > etc
> > :
> > s2ibis2.11_real: Starting HSpice job with input y017.spi.
> > s2ibis2.11_real: Starting HSpice job with input z017.spi.
> > s2ibis2.11_real: Opening file gold_7xxx.ibs for writing...Bus error
> > -----
> > 2) My attempt at solving this:
> > And so  I examine the  gold_7xxx .ibs file, and  I see the following:
> > :
> > etc
> > :
> > [Pulldown]
> > | voltage     I(typ)              I(min)              I(max)
> > |
> >   -3.30      -9.001A             -9.160A             -8.914A
> >   -3.10      -8.255A             -8.415A             -8.168A
> > :
> > etc
> > :
> >    3.50       0.178A              0.117A              0.241A
> >    3.60       0.179A              0.117A              0.242A
> >    3.70       0.179A
> > (The ibis file ends here, which is far from being complete.)
> > I have examined all the *out files (especially the pdt.out, pdx.out,
> > pdn.out files)
> > in detail and see that all hspice data has been generated and dumped
> > into  the
> > *out files with  no problem whatsoever. And yet s2ibis is apparently
> > having
> > problem extracting  the data from the  *out files to place in the *ibs
> > file.
> > Any idea how to approach or solve this problem?
> > Has anyone ever encountered this?
> > Any help or hints would be appreciated.  Thanks so much,
> > - Wil
> > IDT  sram design
> > (408) 330-1623
>
>-----------------------------------------------------------------
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>|with the appropriate command message(s) in the body:
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Regards

Mike
________________________________________________________________
| Mike Ventham - Vice-President Engineering,                   |
| Quantic EMC Inc.                  Headquarters               |
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------------------------------

Date: Tue, 15 Apr 2003 09:47:17 -0400
From: "Todd Westerhoff" <twesterh@cisco.com>
Subject: [IBIS-Users] RE: [IBIS] Re: Ibis generation problem

I think I remember this one.

I think it's a memory corruption (bad pointer) problem (as Mike said).  Take
a close look at your .s2i file - if memory serves, you'll find out that the
model name you called out in the [Pin] section doesn't exactly match the
model name you have in the [Model] section.  That drives s2ibis2 nuts.

Another thing that has perplexed me in the past has been when I used pin
names longer than 5 characters.  S2ibis2 wants to be able to append 3
characters to the pin name, add a ".spi" extension, and still end up with a
legal 8.3 character file name.  Use a 6 or more character pin name, and you
get another set of weird problems that are hard to diagnose.

Hope that helps,

Todd.

Todd Westerhoff
High Speed Design Specialist
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@cisco.com
ph: 978-936-2149
============================================

"When did the choices get so hard, with so much more at stake?
 Life gets mighty precious when there's less of it to waste"

- - Bonnie Raitt, "Nick of Time"

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------------------------------

Date: Tue, 15 Apr 2003 11:19:36 -0400
From: "Todd Westerhoff" <twesterh@cisco.com>
Subject: [IBIS-Users] RE: [IBIS] Re: Ibis generation problem

I think I remember this one.

I think it's a memory corruption (bad pointer) problem (as Mike said).  Take
a close look at your .s2i file - if memory serves, you'll find out that the
model name you called out in the [Pin] section doesn't exactly match the
model name you have in the [Model] section.  That drives s2ibis2 nuts.

Another thing that has perplexed me in the past has been when I used pin
names longer than 5 characters.  S2ibis2 wants to be able to append 3
characters to the pin name, add a ".spi" extension, and still end up with a
legal 8.3 character file name.  Use a 6 or more character pin name, and you
get another set of weird problems that are hard to diagnose.

Hope that helps,

Todd.

Todd Westerhoff
High Speed Design Specialist
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@cisco.com
ph: 978-936-2149
============================================

"When did the choices get so hard, with so much more at stake?
 Life gets mighty precious when there's less of it to waste"

- - Bonnie Raitt, "Nick of Time"

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------------------------------

Date: Tue, 15 Apr 2003 09:05:11 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Subject: [IBIS-Users] Re: What's the "s2ibis2_fix version"?

The _fix version will display 4 digits after the decimal for all V/I 
curves.

The older version will display 2 digits.

All the _fix version fixed some bugs as well..

Syed

>content-class: urn:content-classes:message
>MIME-Version: 1.0
>Content-Transfer-Encoding: quoted-printable
>Subject: What's the "s2ibis2_fix version"?
>X-MimeOLE: Produced By Microsoft Exchange V6.0.6249.0
>Date: Mon, 14 Apr 2003 19:16:39 -0700
>Thread-Topic: [IBIS-Users] Re: [IBIS] Ibis generation problem
>Thread-Index: AcMC7d62nTmSdUF3TIybysokNUAyIwAApJOA
>From: "Eric Hsu" <ehsu@netlogicmicro.com>
>To: "Syed Huq" <shuq@cisco.com>
>Cc: <ibis@eda.org>, <ibis-users@eda.org>, <ibis-info@eda.org>
>
>Hi,
>
>How do I know the version of s2ibis2 is correct or not? From the Syed's 
mail, it mention about the log file show the wrong version message, is any 
one how do I tell it? Does it suppose to be "s2ibi2 v1.1 --North Carolina 
State University"? or "s2ibi2_fix v1.1 --North Carolina State University"?
>
>Best Regards,
>
>Eric Hsu
>Interface Technologies
>NetLogic Microsystems, Inc.
>450 National Ave.
>Mountain View, CA 94043
>650-961-6676 x198
>This e-mail contains NetLogic Microsystems, Inc. Confidential information
>
>
>
>-----Original Message-----
>From: Syed Huq [mailto:shuq@cisco.com]
>Sent: Monday, April 14, 2003 6:15 PM
>To: wngan@idt.com
>Cc: ibis@server.eda.org; ibis-users@server.eda.org;
>ibis-info@server.eda.org
>Subject: [IBIS-Users] Re: [IBIS] Ibis generation problem
>
>
>Wil,
>
>Are you translating multiple buffers at the same time ? Try running the 
>s2ibis2 only on an Input model or only on an Output model. There is an 
>issue of creating too many .spi and .out files..
>
>Next, you should be using s2ibis2_fix version. Your data shows you are 
>using an older version..
>
>Syed
>
>>Date: Mon, 14 Apr 2003 16:50:15 -0700
>>From: Wil Ngan <wngan@idt.com>
>>X-Accept-Language: en
>>MIME-Version: 1.0
>>CC: ibis@eda.org, ibis-users@eda.org, ibis-info@eda.org
>>Subject: [IBIS] Ibis generation problem
>>
>>Hi,
>>
>>I'm having problem generating an ibis file, and was wondering
>>if I can get ideas in how to approach this.
>>
>>1) The problem:
>>
>>I get the following error when running  spice to ibis:
>>% s2ibis2.11 gold_7xxx.s2i
>>s2ibis2.11_real v1.1 -- North Carolina State University
>>s2ibis2.11_real: Reading input file gold_7xxx..done
>>s2ibis2.11_real: Analyzing component idt7xxx .
>>s2ibis2.11_real: Starting HSpice job with input put7.spi.
>>:
>>etc
>>:
>>s2ibis2.11_real: Starting HSpice job with input y017.spi.
>>s2ibis2.11_real: Starting HSpice job with input z017.spi.
>>s2ibis2.11_real: Opening file gold_7xxx.ibs for writing...Bus error
>>
>>-----
>>
>>2) My attempt at solving this:
>>
>>And so  I examine the  gold_7xxx .ibs file, and  I see the following:
>>:
>>etc
>>:
>>[Pulldown]
>>| voltage     I(typ)              I(min)              I(max)
>>|
>>  -3.30      -9.001A             -9.160A             -8.914A
>>  -3.10      -8.255A             -8.415A             -8.168A
>>:
>>etc
>>:
>>   3.50       0.178A              0.117A              0.241A
>>   3.60       0.179A              0.117A              0.242A
>>   3.70       0.179A
>>
>>(The ibis file ends here, which is far from being complete.)
>>
>>I have examined all the *out files (especially the pdt.out, pdx.out,
>>pdn.out files)
>>in detail and see that all hspice data has been generated and dumped
>>into  the
>>*out files with  no problem whatsoever. And yet s2ibis is apparently
>>having
>>problem extracting  the data from the  *out files to place in the *ibs
>>file.
>>
>>Any idea how to approach or solve this problem?
>>Has anyone ever encountered this?
>>Any help or hints would be appreciated.  Thanks so much,
>>
>>- Wil
>>IDT  sram design
>>(408) 330-1623
>>
>>
>
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------------------------------

Date: Tue, 15 Apr 2003 10:08:46 -0700
From: Wil Ngan <wngan@idt.com>
Subject: [IBIS-Users] Re: [IBIS] Re: Ibis generation problem

Todd Westerhoff wrote:

> I think I remember this one.
>
> I think it's a memory corruption (bad pointer) problem (as Mike said).  Take
> a close look at your .s2i file - if memory serves, you'll find out that the
> model name you called out in the [Pin] section doesn't exactly match the
> model name you have in the [Model] section.  That drives s2ibis2 nuts.

Thanks for you reply Todd. I've double checked, the model names
in [Pin] and [Model] section match exactly,  plus all the characters are in
capitals.

> Another thing that has perplexed me in the past has been when I used pin
> names longer than 5 characters.  S2ibis2 wants to be able to append 3
> characters to the pin name, add a ".spi" extension, and still end up with a
> legal 8.3 character file name.  Use a 6 or more character pin name, and you
> get another set of weird problems that are hard to diagnose.

I'm using only one character (the number "7") as pin name.
I'm currently having our system admin guys download the s2bis_fix version
and see if that works.

>
> Hope that helps,
>
> Todd.
>
> Todd Westerhoff
> High Speed Design Specialist
> Cisco Systems
> 1414 Massachusetts Ave - Boxboro, MA - 01719
> email:twesterh@cisco.com
> ph: 978-936-2149

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------------------------------

Date: Tue, 15 Apr 2003 17:17:46 -0700
From: Wil Ngan <wngan@idt.com>
Subject: [IBIS-Users] Re: [IBIS] Ibis generation problem

FYI, using the new _fix program I was able to generate the *ibs file.
For a moment there I thought I had to manually parse all the data...
Thanks so much for your help, Syed!
- - Wil

** FYI: the s2ibis fix program is located at:
www.eda.org/pub/ibis/s2ibis/s2ibis2_v1.1
There are two *.Z files. Get the one with _fix.


Syed Huq wrote:

> Wil,
>
> Are you translating multiple buffers at the same time ? Try running the
> s2ibis2 only on an Input model or only on an Output model. There is an
> issue of creating too many .spi and .out files..
>
> Next, you should be using s2ibis2_fix version. Your data shows you are
> using an older version..
>
> Syed
>
> >Date: Mon, 14 Apr 2003 16:50:15 -0700
> >From: Wil Ngan <wngan@idt.com>
> >X-Accept-Language: en
> >MIME-Version: 1.0
> >CC: ibis@eda.org, ibis-users@eda.org, ibis-info@eda.org
> >Subject: [IBIS] Ibis generation problem
> >
> >Hi,
> >
> >I'm having problem generating an ibis file, and was wondering
> >if I can get ideas in how to approach this.
> >
> >1) The problem:
> >
> >I get the following error when running  spice to ibis:
> >% s2ibis2.11 gold_7xxx.s2i
> >s2ibis2.11_real v1.1 -- North Carolina State University
> >s2ibis2.11_real: Reading input file gold_7xxx..done
> >s2ibis2.11_real: Analyzing component idt7xxx .
> >s2ibis2.11_real: Starting HSpice job with input put7.spi.
> >:
> >etc
> >:
> >s2ibis2.11_real: Starting HSpice job with input y017.spi.
> >s2ibis2.11_real: Starting HSpice job with input z017.spi.
> >s2ibis2.11_real: Opening file gold_7xxx.ibs for writing...Bus error
> >
> >-----
> >
> >2) My attempt at solving this:
> >
> >And so  I examine the  gold_7xxx .ibs file, and  I see the following:
> >:
> >etc
> >:
> >[Pulldown]
> >| voltage     I(typ)              I(min)              I(max)
> >|
> >  -3.30      -9.001A             -9.160A             -8.914A
> >  -3.10      -8.255A             -8.415A             -8.168A
> >:
> >etc
> >:
> >   3.50       0.178A              0.117A              0.241A
> >   3.60       0.179A              0.117A              0.242A
> >   3.70       0.179A
> >
> >(The ibis file ends here, which is far from being complete.)
> >
> >I have examined all the *out files (especially the pdt.out, pdx.out,
> >pdn.out files)
> >in detail and see that all hspice data has been generated and dumped
> >into  the
> >*out files with  no problem whatsoever. And yet s2ibis is apparently
> >having
> >problem extracting  the data from the  *out files to place in the *ibs
> >file.
> >
> >Any idea how to approach or solve this problem?
> >Has anyone ever encountered this?
> >Any help or hints would be appreciated.  Thanks so much,
> >
> >- Wil
> >IDT  sram design
> >(408) 330-1623
> >
> >

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------------------------------

Date: Thu, 17 Apr 2003 11:16:52 -0400
From: "Lynne Green" <lgreen@cadence.com>
Subject: [IBIS-Users] First Call for Papers for DAC IBIS Summit 

- -----------------------------------------------------------------------
                       IBIS SUMMIT
                     FIRST CALL FOR
               PARTICIPATION & PRESENTATIONS
- -----------------------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

              I B I S   S U M M I T   M E E T I N G

Time/Date:  Thursday June 5, 2003,  8:00 AM to 5:00 PM

Location:   Marriot Hotel
            Anaheim, CA

Content:    Presentations and Discussions

Purpose:    Solicit and Exchange IBIS Model Related Information and
Ideas.

Sponsors:   If your company would be interested in sponsoring this
event,
            please contact Lynne Green <lgreen@cadence.com>.
Sponsorship
            is available for the room, lunch, and coffee breaks.

DAC:        June 2-6, 2003
            Anaheim Convention Center
		Anaheim, California
		See <http://www.dac.com/> for more information.

BACKGROUND

DesignCon is the premier annual Silicon Valley event for the electronic
design
automation (EDA) and semiconductor industry.  Topics of current interest
to the
EIA IBIS Open Forum are addressed at DesignCon.

This meeting will be conducted as a formal IBIS Summit Meeting.
Presentations
are expected to be available and archived in an electronic format, and
minutes of
the meeting will be issued.  Any pending formal decisions (votes) will
be announced
at least two weeks prior to the meeting.

The annual election of officers will be held.  Nominations can be sent
to Stephen
Peters <stephen.peters@intel.com> or made at the meeting.


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and
digital
circuit design are invited to participate to the Summit meeting. If you
plan to
participate, please register with the information below:

   Name:
   E-mail address:
   Company:
   Telephone:

Send to:

    Guy de Burgh at Mentor Graphics (guy_deburgh@mentor.com)


CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.

Format of Presentation:  LCD Projection with Windows laptop.
Time:			15-30 Minutes
Electronic Archival: We request electronic versions so that the
			presentations can be archived and also made
			available to non-attendees.  Formats used in
			the past have been text, Power Point, Word,
			Postscript, and Acrobat.  Electronic
presentations
			should be made available by May 30, 2003
			for uploading and copying to the presentation
laptop.

If you plan a presentation, please supply

   Title:
   Presenter:
   E-mail address:
   Company:
   Telephone:

   Estimate Time:

Also, please indicate if you are also interested in presenting this
presentation at
DesignCon East, Marlborough, MA, on June 23, 2003.

Send this to:

  Lynne Green (lgreen@cadence.com)


AGENDA

The agenda includes presentations, discussions, breaks, and a luncheon
(which
will be provided).  This will be developed as presentation proposals are
received.


LIST OF NEARBY HOTELS

See <http://www.dac.com/40th/travel.html> for travel directions, hotels
and other information.
- -----------------------------------------------------------------
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------------------------------

Date: Fri, 18 Apr 2003 10:26:46 -0400
From: Robert Haller <rhaller@sisoft.com>
Subject: [IBIS-Users] IBIS Bug 71 - updated

This is a multi-part message in MIME format.
- --------------000707080007030303040907
Content-Type: text/plain; charset=us-ascii; format=flowed
Content-Transfer-Encoding: 7bit

Attached is updated IBIS bug 71

Regards,
Bob

- -- 
Robert J. Haller (rhaller@sisoft.com)
Principal Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 15


- --------------000707080007030303040907
Content-Type: text/plain;
 name="bug71_updated.txt"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="bug71_updated.txt"

******************************************************************************
********************* IBIS GOLDEN PARSER BUG REPORT FORM *********************
******************************************************************************

INSTRUCTIONS

To report a bug in the IBIS golden parser.  Please fill out the top part
of the following form and send the complete form to ibischk-bug@vhdl.org.

A list of reported bugs will be maintained on vhdl.org.

******************************************************************************

PARSER VERSION NUMBER:
      Found in IBISCHK3 V3.2.5  (Rechecked with IBISCHK3 V3.2.9)

PLATFORM (SPARC, HP700, PC, etc.):
      Checked on SPARC

OS AND VERSION:
      Soloris

REPORTED BY:
      Bob Haller SiSoft

DATE:
      8 Aug 2002 original report

DESCRIPTION OF BUG:
      IBIS parser reports non-monotonic warnings when combined curve IS
monotonic.


INSERT IBIS FILE DEMONSTRATING THE BUG:

     The attached IBIS file generates non-monotic warnings.
The subtracted curves are non-monotonic, but the combined curves ARE
monotonic.

The new parser monotonic checks outlined below will replace the old 
parser monotonic checks.
The old parser previously checked monotonicity of the V/I tables only 
one at a time (Pullup, Pulldown, Power Clamp and Ground clamp).

For the various model types the parser should;
Combine the PULLDOWN curve with CLAMPS then check for monotonicity.
Combine the PULLUP curve with CLAMPS then check for monotonicity.
The parser will NOT check PULLUP and PULLDOWN V/I tables independently.

A missing table is treated as having values 0.0 for all entries.
Typ, Min, and Max should be treated seperately
All tables should have there voltages "de-referenced" back to true 
GROUND prior to summing. Linear interpolation should be used if rows 
do not line up between tables being summed.

The ttable below of the model types illustrates the required checks. 
The Ibis parser will ONLY issue a warning if Clamp Curves or 
combined curves are Non-monotonic (see examples checked below).

MODEL_TYPE PULLUP  PULLDOWN  POWER_CLAMP  GND_CLAMP  COMBINED   COMBINDED
                                                     PULLUP+    PULLDOWN+
                                                     POWERCLAMP GND_CLAMP+
                                                     +GND_CLAMP POWERCLAMP 

Input							XXX          XXX

I/O                             XXX          XXX      XXX        XXX

Output                                                XXX        XXX

3-state                         XXX          XXX      XXX        XXX

I/O_Open_Drain                  XXX          XXX                 XXX

I/O_Open_Sink                   XXX          XXX                 XXX

I/O_Open_Source                 XXX          XXX      XXX

Open_Drain                      XXX          XXX                 XXX

Open_Sink                       XXX          XXX                 XXX

Open_Source                     XXX          XXX      XXX

Input_ECL                       XXX          XXX

I/O_ECL                         XXX          XXX      XXX        XXX

3-state_ECL                     XXX          XXX      XXX        XXX

Terminator                      XXX          XXX     

Series

Series_switch



This file generates the following incorrect warning messages:

IBISCHK3 V3.2.9

Checking bug71.ibs for IBIS 3.2 Compatibility...

WARNING (line   70) - Pulldown Minimum data is non-monotonic
WARNING (line   89) - Pulldown Maximum data is non-monotonic
WARNING (line   90) - Pulldown Typical data is non-monotonic
WARNING (line  188) - Pullup Maximum data is non-monotonic
WARNING (line  189) - Pullup Typical data is non-monotonic
WARNING (line  191) - Pullup Minimum data is non-monotonic

Errors  : 0
Warnings: 6

File Passed



|###############################################################
|                   Signal Integrity Software, INC.
|                     IBIS Model for non-monotonic PARSER_BUG
|###############################################################
|
[IBIS Ver]    3.2
[File Name]   bug71.ibs
[File Rev]    1.0
[Date]        7/16/2002
[Source]      Developed by:
                       Signal Integrity Software, Inc.
                       6 Clock Tower Place, Suite 250
                       Maynard, MA 01754
                       support@sisoft.com

|
[Notes]
|###############################################################
                           Revision History
|###############################################################
                  Rev 1.0
                        - 7/17/02 Inital Release. RJH
|###############################################################

[Disclaimer]    THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
                   WHATSOEVER AND SIGNAL INTEGRITY SOFTWARE SPECIFICALLY
                   DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY,
                   FITNESS FOR A PARTICULAR PURPOSE, OR AGAINST
                   INFRINGEMENT.
|
[Copyright]     Copyright 2002, Signal Integrity Software, Inc.,
                   All Rights Reserved

|****************************************************************
|
[Component] SISOFT
[Manufacturer] SiSoft
|
[Package]

R_pkg 284m   NA      NA
L_pkg 7.89nH NA      NA
C_pkg 1.35pF NA      NA
|
[Pin]   signal_name      model_name        R_pin L_pin C_pin
|Ball   Pad Name         CellName
1      parser_bug    DATA         NA NA NA
|
|****************************************************************
|                         DATA
|****************************************************************
|
[Model]     DATA
Model_type  I/O
Polarity    Non-Inverting
Enable      Active-Low
Cref = 10pF
Vmeas = 1.25V
Vinh = 1.6V
Vinl = 0.9V
C_comp 2.1454p 2.0873p 2.2382p
|
[Voltage Range] 2.5 2.25 2.75
|
[Temperature Range]       25            125           0
|
[Pulldown]
- -2.5                -.0012              -700.01e-6          -.0016
- -2.4224             -.0013              -755.2e-6           -.0016
- -2.3448             -.0014              -710.42e-6          -.0018
- -2.2672             -.0015              -799.99e-6          -.002
- -2.1895             -.0017              -900.e-6            -.0023
- -2.1119             -.0019              -900.e-6            -.0027
- -2.0343             -.0021              -.001               -.0031
- -1.9567             -.0024              -.0011              -.0037
- -1.8791             -.0028              -.0012              -.0047
- -1.8015             -.0034              -.0013              -.006
- -1.7239             -.0042              -.0014              -.008
- -1.6463             -.0054              -.0016              -.0104
- -1.5687             -.0073              -.0018              -.0128
- -1.4911             -.0095              -.0021              -.0152
- -1.4135             -.012               -.0025              -.0177
- -1.3359             -.0145              -.003               -.02
- -1.2583             -.017               -.0038              -.0223
- -1.1807             -.0193              -.005               -.0245
- -1.1031             -.0216              -.0066              -.0264
- -1.0255             -.0237              -.0087              -.0279
- -.9479              -.0253              -.0111              -.0289
- -.8703              -.0262              -.0134              -.0286
- -.7927              -.0261              -.0154              -.0276
- -.7151              -.0249              -.0166              -.0262
- -.6375              -.023               -.0169              -.0244
- -.5599              -.0207              -.0159              -.0221
- -.4823              -.0179              -.014               -.0194
- -.4047              -.015               -.0118              -.0163
- -.327               -.0121              -.0095              -.0131
- -.2494              -.0092              -.0071              -.01
- -.1718              -.0064              -.0049              -.0069
- -.0942              -.0034              -.0026              -.0037
- -.0166              -600.e-6            -466.66e-6          -666.66e-6
0.                  0.                  0.                  0.
.0609               .0022               .0017               .0024
.1385               .0051               .0038               .0055
.2161               .0078               .0059               .0086
.2937               .0106               .008                .0116
.3713               .0134               .01                 .0147
.4489               .0161               .0119               .0177
.5265               .0188               .0139               .0207
.6041               .0214               .0157               .0237
.6817               .024                .0175               .0267
.7593               .0266               .0192               .0296
.8369               .0291               .0208               .0325
.9145               .0316               .0224               .0353
.9922               .034                .0239               .0382
1.0698              .0364               .0253               .041
1.1474              .0387               .0266               .0438
1.225               .041                .0279               .0465
1.3026              .0432               .029                .0492
1.3802              .0453               .03                 .0519
1.4578              .0474               .0309               .0545
1.5354              .0494               .0316               .0571
1.613               .0513               .0323               .0596
1.6906              .0531               .0328               .0621
1.7682              .0548               .0332               .0645
1.8458              .0564               .0335               .0669
1.9234              .0578               .0338               .0692
2.001               .0591               .0341               .0715
2.0786              .0601               .0342               .0737
2.1562              .0609               .0344               .0757
2.2338              .0615               .0345               .0777
2.3114              .062                .0347               .0796
2.389               .0625               .0348               .0813
2.4666              .0628               .035                .0829
2.5442              .0631               .0351               .0842
2.6218              .0634               .0352               .0852
2.6994              .0636               .0353               .0862
2.777               .0638               .0354               .0868
2.8547              .064                .0355               .0873
2.9323              .0641               .0356               .0878
3.0099              .0643               .0359               .0882
3.0875              .0644               .0362               .0885
3.1651              .0646               .0366               .0888
3.2427              .0648               .037                .089
3.3203              .0649               .0378               .0892
3.3979              .0653               .0395               .0895
3.4755              .0656               .0428               .0897
3.5531              .066                .0472               .09
3.6307              .0664               .0521               .0902
3.7083              .0668               .0573               .0906
3.7859              .0672               .0629               .091
3.8635              .0676               .0685               .0914
3.9411              .0682               .0742               .0918
4.0187              .0689               .08                 .0923
4.0963              .0699               .0857               .0927
4.1739              .0717               .0916               .0932
4.2515              .0749               .0975               .0936
4.3291              .0794               .1034               .094
4.4067              .0845               .1093               .0945
4.4843              .0899               .1153               .0949
4.5619              .0956               .1212               .0956
4.6395              .1013               .1272               .0966
4.7172              .1071               .1332               .098
4.7948              .113                .1392               .0998
4.8724              .1189               .1452               .1027
4.95                .1248               .1512               .1069
[Pullup]
- -2.45               .0016               900.e-6             .0037
- -2.3724             .0017               .001                .0037
- -2.2948             .0019               .0011               .0037
- -2.2172             .002                .0011               .0037
- -2.1395             .0023               .0012               .0037
- -2.0619             .0024               .0013               .0044
- -1.9843             .0028               .0014               .0055
- -1.9067             .0033               .0015               .0071
- -1.8291             .0039               .0016               .0092
- -1.7515             .0047               .0017               .0115
- -1.6739             .006                .0019               .0138
- -1.5963             .0079               .0022               .0162
- -1.5187             .0102               .0025               .0184
- -1.4411             .0126               .0028               .0207
- -1.3635             .0152               .0034               .023
- -1.2859             .0177               .0041               .0252
- -1.2083             .0201               .0052               .0272
- -1.1307             .0223               .0068               .0292
- -1.0531             .0246               .0088               .0309
- -.9755              .0264               .0112               .0323
- -.8979              .0279               .0137               .0328
- -.8203              .028                .0158               .0319
- -.7427              .0269               .0174               .0299
- -.6651              .0246               .0178               .0276
- -.5875              .022                .0166               .0248
- -.5099              .0192               .0146               .0216
- -.4323              .0162               .0124               .0183
- -.3547              .0132               .0101               .015
- -.277               .0103               .0078               .0117
- -.1994              .0073               .0056               .0083
- -.1218              .0045               .0033               .0051
- -.0442              .0016               .0011               .0018
0.                  0.                  0.                  0.
.0333               -.0012              -866.67e-6          -.0014
.1109               -.004               -.0028              -.0045
.1885               -.0067              -.0049              -.0077
.2661               -.0094              -.0069              -.0109
.3437               -.0121              -.0086              -.014
.4213               -.0146              -.0104              -.0171
.4989               -.0171              -.0121              -.02
.5765               -.0195              -.0138              -.023
.6541               -.0219              -.0153              -.0259
.7317               -.0242              -.0168              -.0288
.8093               -.0264              -.0181              -.0316
.8869               -.0285              -.0194              -.0343
.9645               -.0305              -.0206              -.037
1.0422              -.0325              -.0217              -.0396
1.1198              -.0343              -.0226              -.0422
1.1974              -.036               -.0233              -.0446
1.275               -.0377              -.0241              -.047
1.3526              -.0391              -.0247              -.0493
1.4302              -.0404              -.0251              -.0515
1.5078              -.0417              -.0255              -.0537
1.5854              -.0428              -.0259              -.0557
1.663               -.0437              -.0262              -.0576
1.7406              -.0445              -.0265              -.0594
1.8182              -.0452              -.0268              -.061
1.8958              -.0458              -.027               -.0626
1.9734              -.0464              -.0273              -.0639
2.051               -.047               -.0275              -.0652
2.1286              -.0473              -.0276              -.0663
2.2062              -.0478              -.0278              -.0673
2.2838              -.0481              -.028               -.0682
2.3614              -.0485              -.0281              -.069
2.439               -.0487              -.0282              -.0698
2.5166              -.049               -.0284              -.0704
2.5942              -.0493              -.0286              -.0709
2.6718              -.0496              -.0286              -.0715
2.7494              -.0498              -.0288              -.072
2.827               -.0499              -.0288              -.0724
2.9047              -.0502              -.0291              -.0728
2.9823              -.0503              -.0293              -.0732
3.0599              -.0505              -.0296              -.0735
3.1375              -.0506              -.0301              -.0738
3.2151              -.0509              -.031               -.0741
3.2927              -.0511              -.0329              -.0744
3.3703              -.0514              -.0361              -.0746
3.4479              -.0518              -.0402              -.075
3.5255              -.0521              -.045               -.0753
3.6031              -.0525              -.0501              -.0757
3.6807              -.0529              -.0555              -.076
3.7583              -.0536              -.061               -.0764
3.8359              -.0546              -.0666              -.0768
3.9135              -.0562              -.0723              -.0772
3.9911              -.0584              -.078               -.0777
4.0687              -.0616              -.0839              -.0782
4.1463              -.0659              -.0897              -.0786
4.2239              -.0708              -.0956              -.0791
4.3015              -.0762              -.1015              -.0797
4.3791              -.0817              -.1074              -.0808
4.4567              -.0874              -.1133              -.0824
4.5343              -.0931              -.1193              -.0844
4.6119              -.0989              -.1253              -.0867
4.6895              -.1048              -.1313              -.0895
4.7672              -.1107              -.1313              -.0935
4.8448              -.1166              -.1313              -.0982
4.9224              -.1225              -.1313              -.1035
5.                  -.1285              -.1313              -.109
[GND Clamp]
- -2.5                -.1273              -.1352              -.1254
- -2.4266             -.1215              -.1294              -.1196
- -2.3532             -.1158              -.1238              -.1139
- -2.2799             -.1101              -.1181              -.1082
- -2.2065             -.1044              -.1124              -.1025
- -2.1332             -.0987              -.1068              -.0968
- -2.0598             -.093               -.101               -.091
- -1.9864             -.0873              -.0954              -.0854
- -1.9131             -.0817              -.0898              -.0797
- -1.8397             -.076               -.0842              -.0741
- -1.7664             -.0703              -.0785              -.0684
- -1.693              -.0647              -.0729              -.0627
- -1.6196             -.0591              -.0674              -.0572
- -1.5463             -.0535              -.0618              -.0516
- -1.4729             -.048               -.0562              -.046
- -1.3996             -.0424              -.0507              -.0405
- -1.3262             -.037               -.0453              -.0351
- -1.2528             -.0316              -.0399              -.0297
- -1.1795             -.0263              -.0345              -.0244
- -1.1061             -.0211              -.0292              -.0194
- -1.0328             -.0161              -.0241              -.0147
- -.9594              -.0114              -.019               -.0106
- -.886               -.0074              -.0142              -.0075
- -.8127              -.0044              -.0097              -.0051
- -.7393              -.0025              -.0059              -.0033
- -.666               -.0012              -.0028              -.0019
- -.5926              -449.9e-6           -.001               -776.18e-6
- -.5192              -115.48e-6          -279.81e-6          -211.34e-6
- -.4459              -17.917e-6          -58.299e-6          -30.002e-6
- -.3725              -2.9724e-6          -14.08e-6           -4.2557e-6
- -.2992              -278.52e-9          -2.5647e-6          -295.33e-9
- -.2258              -37.248e-9          -568.11e-9          -31.843e-9
- -.1524              -3.0189e-9          -93.474e-9          -1.9346e-9
- -.0791              -441.02e-12         -20.779e-9          -288.53e-12
- -.0057              -162.03e-12         -5.9921e-9          -150.91e-12
.0676               -133.39e-12         -3.6993e-9          -135.9e-12
.1409               -123.67e-12         -3.4025e-9          -127.59e-12
.2143               -114.78e-12         -3.249e-9           -119.54e-12
.2877               -106.02e-12         -3.1128e-9          -111.54e-12
.361                -97.288e-12         -2.9825e-9          -103.54e-12
.4344               -88.554e-12         -2.8545e-9          -95.552e-12
.5077               -79.828e-12         -2.7272e-9          -87.55e-12
.5811               -71.1e-12           -2.5993e-9          -79.551e-12
.6545               -62.329e-12         -2.4703e-9          -71.535e-12
.7278               -53.551e-12         -2.3394e-9          -63.507e-12
.8012               -44.695e-12         -2.2067e-9          -55.468e-12
.8745               -35.838e-12         -2.0713e-9          -47.412e-12
.9479               -26.903e-12         -1.9334e-9          -39.347e-12
1.0213              -17.985e-12         -1.7923e-9          -31.271e-12
1.0946              -9.051e-12          -1.6481e-9          -23.162e-12
1.168               0.                  -1.5003e-9          -15.064e-12
1.3039              0.                  -1.2165e-9          0.
1.8167              0.                  0.                  0.
4.95                0.                  0.                  0.
[Power Clamp]
- -2.45               .1231               .131                .0987
- -2.3923             .1186               .1265               .0987
- -2.3346             .1141               .122                .0987
- -2.277              .1096               .1175               .0987
- -2.2193             .1051               .1131               .0987
- -2.1616             .1006               .1086               .0987
- -2.104              .0961               .1041               .0942
- -2.0463             .0917               .0997               .0898
- -1.9886             .0872               .0952               .0853
- -1.931              .0827               .0907               .0808
- -1.8733             .0782               .0863               .0763
- -1.8156             .0738               .0819               .0719
- -1.758              .0693               .0775               .0674
- -1.7003             .0649               .073                .063
- -1.6427             .0605               .0686               .0585
- -1.585              .056                .0642               .0541
- -1.5273             .0516               .0598               .0497
- -1.4697             .0473               .0555               .0454
- -1.412              .0429               .0511               .041
- -1.3543             .0385               .0468               .0366
- -1.2967             .0342               .0424               .0323
- -1.239              .03                 .0382               .0281
- -1.1813             .0257               .0339               .0238
- -1.1237             .0216               .0297               .0197
- -1.066              .0175               .0256               .0158
- -1.0083             .0135               .0215               .0119
- -.9507              .0098               .0175               .0084
- -.893               .0064               .0136               .0056
- -.8353              .0038               .01                 .0036
- -.7777              .0021               .0067               .0024
- -.72                .0011               .0038               .0014
- -.6623              579.51e-6           .0018               810.31e-6
- -.6047              236.03e-6           713.25e-6           344.36e-6
- -.547               75.573e-6           256.35e-6           105.9e-6
- -.4893              21.942e-6           94.408e-6           27.389e-6
- -.4317              5.8433e-6           33.794e-6           6.2294e-6
- -.374               1.4363e-6           11.799e-6           1.2733e-6
- -.3164              317.94e-9           3.9895e-6           228.16e-9
- -.2587              61.758e-9           1.2739e-6           34.906e-9
- -.201               10.086e-9           371.98e-9           4.3329e-9
- -.1434              2.0015e-9           115.73e-9           762.62e-12
- -.0857              499.48e-12          36.361e-9           241.56e-12
- -.028               214.34e-12          10.994e-9           161.52e-12
.0296               157.08e-12          2.5521e-9           146.54e-12
.0872               145.72e-12          747.63e-12          141.26e-12
.1449               140.64e-12          506.23e-12          136.97e-12
.2026               136.22e-12          407.79e-12          133.03e-12
.2602               131.75e-12          328.09e-12          128.88e-12
.3179               127.13e-12          244.4e-12           124.61e-12
.3756               121.7e-12           135.14e-12          120.05e-12
.4332               114.88e-12          0.                  114.53e-12
1.3319              0.                  0.                  12.709e-12
1.446               0.                  0.                  0.
5.                  0.                  0.                  0.
[Ramp]
dV/dt_r .9201/203.57p .6785/334.7p 1.0863/153.65p
dV/dt_f .9507/110.26p .7187/186.76p 1.0916/92.507p
| End [Component] sisoft
[END]


******************************************************************************
******************** BELOW FOR ADMINISTRATION AND TRACKING *******************
******************************************************************************

BUG NUMBER: 71

SEVERITY: [FATAL, SEVERE, MODERATE, ANNOYING, ENHANCEMENT]  ENHANCEMENT

PRIORITY: [HIGH, MEDIUM, LOW]                               LOW

STATUS: [OPEN, CLOSED, WILL NOT FIX, NOT A BUG]             OPEN

FIXED VERSION:

FIXED DATE:

NOTES ON BUG FIX:  Classified at the August 30, 2002 IBIS Meeting
                   Needed more specific description of the exact tests
                     with respect to each Model_type.  E.g., would clamp
                     test for Input, Terminator be combined [Power Clamp]
                     and [Gnd Clamp]?, Would Clamp test be omitted for
                     Output?
                   Needed to agree on a proposed resolution
                     - keep existing Warnings and add more?
                     - amend existing Warnings with statement that combined
                       table us non-monotonic
                     - delete existing Warnings, and add new Warning if
                       combined tables are non-monotonic

                   Revised BUG71 submitted 10/2/02

                   Discussed further at the November 1, 2002 IBIS Meeting
                   Further revision - combined clamps with pullup or pulldown
                   Submit as delete existing Warnings and add new Warnings
                     (third option)

                   Discussed at the December 13, 2002 IBIS Meeting
                     - still need corrections to previously issued BUG71
 
******************************************************************************
******************************************************************************


- --------------000707080007030303040907--

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------------------------------

Date: Fri, 18 Apr 2003 16:13:08 -0700
From: "Mirmak, Michael" <michael.mirmak@intel.com>
Subject: [IBIS-Users] Sticky problem in [Driver Schedule]

All,

We have just noted a strange issue when using the [Driver Schedule] keyword.  

The specification clearly states that, for a "top-level" model under [Driver Schedule], keywords such as [Pulldown], [Rising Waveform], [Ramp], etc. are ignored.  [Power Clamp] and [GND Clamp], however, are not (they would be ignored in the scheduled buffers).

In order to ensure a minimum of issues with tool interpretations of [Driver Schedule], I recently created a model which uses a top-level Model_type of "Input," while using scheduled models of "Open_source," "Open_sink," etc.  An input-only top-level model is not explicitly prohibited by the specification, and, indeed, the parser flagged no errors or warnings with this construction.

Unfortunately, many tools, especially those for which users must explicitly create input stimulus nodes, will probably not be able to use this kind of construction successfully (where, for example, do you tie the input stimulus from the core on an input-only top-level buffer model?).  

At this point, I can only conclude that a clarification BIRD should be written to add restrictions on the Model_type of [Driver Schedule] models.  A parser bug would be inappropriate, since the parser is faithfully following the language of the specification.

Any thoughts?

- - Michael Mirmak, Intel Corp.
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|with just the appropriate command message(s) in the body:
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------------------------------

Date: Fri, 18 Apr 2003 17:12:04 -0700
From: "Beal, Weston" <weston_beal@mentorg.com>
Subject: RE: [IBIS-Users] Sticky problem in [Driver Schedule]

Michael,

The IBIS specification used to say that the scheduled models must be of the same type as the master model.  I think the intent was that they should all be outputs, but when some of this was clarified then that statement was clarified clear out of the spec.  You dilemma shows the implied condition that the master and the scheduled models must be of some output type because all the timing relationships are based on the digital stimulus.  Most people just don't push the spec THAT hard. :)

Regards,
Weston


- -----Original Message-----
From: Mirmak, Michael [mailto:michael.mirmak@intel.com]
Sent: Friday, April 18, 2003 4:13 PM
To: ibis-users@server.eda.org
Subject: [IBIS-Users] Sticky problem in [Driver Schedule]



All,

We have just noted a strange issue when using the [Driver Schedule] keyword.  

The specification clearly states that, for a "top-level" model under [Driver Schedule], keywords such as [Pulldown], [Rising Waveform], [Ramp], etc. are ignored.  [Power Clamp] and [GND Clamp], however, are not (they would be ignored in the scheduled buffers).

In order to ensure a minimum of issues with tool interpretations of [Driver Schedule], I recently created a model which uses a top-level Model_type of "Input," while using scheduled models of "Open_source," "Open_sink," etc.  An input-only top-level model is not explicitly prohibited by the specification, and, indeed, the parser flagged no errors or warnings with this construction.

Unfortunately, many tools, especially those for which users must explicitly create input stimulus nodes, will probably not be able to use this kind of construction successfully (where, for example, do you tie the input stimulus from the core on an input-only top-level buffer model?).  

At this point, I can only conclude that a clarification BIRD should be written to add restrictions on the Model_type of [Driver Schedule] models.  A parser bug would be inappropriate, since the parser is faithfully following the language of the specification.

Any thoughts?

- - Michael Mirmak, Intel Corp.
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------------------------------

Date: Fri, 18 Apr 2003 17:29:27 -0700
From: "Mirmak, Michael" <michael.mirmak@intel.com>
Subject: RE: [IBIS-Users] Sticky problem in [Driver Schedule]

Weston,

Good points!  This is an esoteric case, for many reasons, but I wasn't just being pedantic (at least, not here :) ).  This is actually a lead-in to a larger issue. 

My actual intent was to try and separate out the top-level effects from the scheduled effects to investigate the treatment of different delays, plus clamps and c_comp, by various simulation engines.  In order to ensure I wasn't seeing the top-level effects "poison" the scheduling, I wanted to build the simplest top-level models possible -- a 0 mA clamp input model seemed the most simple way to start, even if it breaks the intent of the spec.  

We have a suspicion here that the scheduling instructions in the spec are written in such a way as to be easily misinterpreted by users and tools (for example, each delay parameter is described using a single sentence seven lines long!).  This case was just a crude illustration of some of the unintentional side-effects of the way the current text is put together.

We'll be preparing some test cases and perhaps even a presentation or paper on this issue in the near future.  Stay tuned...

- - Michael Mirmak, Intel Corp.

- -----Original Message-----
From: Beal, Weston [mailto:weston_beal@mentorg.com]
Sent: Friday, April 18, 2003 5:12 PM
To: ibis-users@eda.org
Subject: RE: [IBIS-Users] Sticky problem in [Driver Schedule]


Michael,

The IBIS specification used to say that the scheduled models must be of the same type as the master model.  I think the intent was that they should all be outputs, but when some of this was clarified then that statement was clarified clear out of the spec.  You dilemma shows the implied condition that the master and the scheduled models must be of some output type because all the timing relationships are based on the digital stimulus.  Most people just don't push the spec THAT hard. :)

Regards,
Weston


- -----Original Message-----
From: Mirmak, Michael [mailto:michael.mirmak@intel.com]
Sent: Friday, April 18, 2003 4:13 PM
To: ibis-users@server.eda.org
Subject: [IBIS-Users] Sticky problem in [Driver Schedule]



All,

We have just noted a strange issue when using the [Driver Schedule] keyword. 

The specification clearly states that, for a "top-level" model under [Driver Schedule], keywords such as [Pulldown], [Rising Waveform], [Ramp], etc. are ignored.  [Power Clamp] and [GND Clamp], however, are not (they would be ignored in the scheduled buffers).

In order to ensure a minimum of issues with tool interpretations of [Driver Schedule], I recently created a model which uses a top-level Model_type of "Input," while using scheduled models of "Open_source," "Open_sink," etc.  An input-only top-level model is not explicitly prohibited by the specification, and, indeed, the parser flagged no errors or warnings with this construction.

Unfortunately, many tools, especially those for which users must explicitly create input stimulus nodes, will probably not be able to use this kind of construction successfully (where, for example, do you tie the input stimulus from the core on an input-only top-level buffer model?). 

At this point, I can only conclude that a clarification BIRD should be written to add restrictions on the Model_type of [Driver Schedule] models.  A parser bug would be inappropriate, since the parser is faithfully following the language of the specification.

Any thoughts?

- - Michael Mirmak, Intel Corp.
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------------------------------

Date: Fri, 18 Apr 2003 19:23:22 -0700
From: Bob Ross <bob@teraspeed.com>
Subject: Re: [IBIS-Users] Sticky problem in [Driver Schedule]

Michael:

[Driver Schedule] was added to IBIS so that IBIS could handle some common
buffer extensions (pre-emphasis (including P-channel kicker) and some
scheduled driver topologies).  The implementation addressed these practical
concerns by adding scheduled FIRST-ORDER adjustments.  However,
the architecture is technically flawed and inconsistent with the
rest of IBIS, when pushed to limit.  So, I do not think it is worth
investing too much time to fix [Driver Schedule].

Here are some background thoughts:

- - The specification and information content (Model_Type,
clamps, C_comp, Polarity, etc) was moved to the top level
model so that it was available in a known, convenient location,
especially for Input and High-Z operation.  (Otherwise, it
would have been distributed in all scheduled models.)

- - We did not add scheduling controls from a separate clock
or input control pins because of the single-pin I/O architecture
structure of an IBIS [Model].

- - The intent of the scheduled models was to provide a behavioral
approximation to the model the first order effect.  The scheduled
models are assumed to be totally independent of each other.  In
real parts, I would expect some interaction.

- - For simplicity, scheduled models were put in the existing [Model]
keyword to avoid introducing many new keywords and subparameters.

- - However, all driver operation is handled only by the scheduled
models.  For simplicity, the Top level model still contained
unscheduled set of I-V and [Ramp] or V-T characteristic for the
buffer for two reasons: (1) It was contained in the [Model] keyword,
and such information was already "required", (2) such
information provided a default approximation for tools that did
not have the [Driver Schedule] keyword implements - this was
probably a mistake, but consistent with the migration of IBIS
philosophy at that time.  (We did not follow the master/slave
architecture where the master information also is used in
the driver simulation, and the slave models provide adjustments.)

- - Clamps in scheduled models created separate issues.  Do clamps
get switched in and out, or do they always remain active?  This
was the reason for moving the total clamp information to the
top level where clamps are always active.  The scheduled models
could have different Model_types, than the top level model, so
this was not helpful. (Since some of the capacitance is
introduced in clamps, the same questions would apply for
C_comp - below.)

- - The biggest problem is C_comp.  If it is truely distributed
within the scheduled models, does this capacitance also get
switched in and out?  Or does it remain forever as a "load"
on other buffers.  How do you really find out of how C_comp
is partitioned?  The safest recommendation is to revert
to a behavioral philosophy and simply set C_comp = 0 in any
scheduled model.  In that way, the top level C_comp is just
a passive load.  This works in a consistent manner among tools
that handled C_comp differently, but this is still an area of
ambiguity.

All of these and perhaps other issues have created interpretation
issues, and probably inconsistent implementions.  [Driver
Schedule] is useful as a practical first order adjustment.
However, its structure is flawed and not worth the effort
of trying to fix or improve it.

Bob Ross

(P.S., I cannot help noting that BIRD58.3 from your company
provide "improved" editorial revisions including some long
sentences.)



Mirmak, Michael wrote:

> Weston,
> 
> Good points!  This is an esoteric case, for many reasons, but I wasn't just being pedantic (at least, not here :) ).  This is actually a lead-in to a larger issue. 
> 
> My actual intent was to try and separate out the top-level effects from the scheduled effects to investigate the treatment of different delays, plus clamps and c_comp, by various simulation engines.  In order to ensure I wasn't seeing the top-level effects "poison" the scheduling, I wanted to build the simplest top-level models possible -- a 0 mA clamp input model seemed the most simple way to start, even if it breaks the intent of the spec.  
> 
> We have a suspicion here that the scheduling instructions in the spec are written in such a way as to be easily misinterpreted by users and tools (for example, each delay parameter is described using a single sentence seven lines long!).  This case was just a crude illustration of some of the unintentional side-effects of the way the current text is put together.
> 
> We'll be preparing some test cases and perhaps even a presentation or paper on this issue in the near future.  Stay tuned...
> 
> - Michael Mirmak, Intel Corp.
> 
> -----Original Message-----
> From: Beal, Weston [mailto:weston_beal@mentorg.com]
> Sent: Friday, April 18, 2003 5:12 PM
> To: ibis-users@eda.org
> Subject: RE: [IBIS-Users] Sticky problem in [Driver Schedule]
> 
> 
> Michael,
> 
> The IBIS specification used to say that the scheduled models must be of the same type as the master model.  I think the intent was that they should all be outputs, but when some of this was clarified then that statement was clarified clear out of the spec.  You dilemma shows the implied condition that the master and the scheduled models must be of some output type because all the timing relationships are based on the digital stimulus.  Most people just don't push the spec THAT hard. :)
> 
> Regards,
> Weston
> 
> 
> -----Original Message-----
> From: Mirmak, Michael [mailto:michael.mirmak@intel.com]
> Sent: Friday, April 18, 2003 4:13 PM
> To: ibis-users@server.eda.org
> Subject: [IBIS-Users] Sticky problem in [Driver Schedule]
> 
> 
> 
> All,
> 
> We have just noted a strange issue when using the [Driver Schedule] keyword. 
> 
> The specification clearly states that, for a "top-level" model under [Driver Schedule], keywords such as [Pulldown], [Rising Waveform], [Ramp], etc. are ignored.  [Power Clamp] and [GND Clamp], however, are not (they would be ignored in the scheduled buffers).
> 
> In order to ensure a minimum of issues with tool interpretations of [Driver Schedule], I recently created a model which uses a top-level Model_type of "Input," while using scheduled models of "Open_source," "Open_sink," etc.  An input-only top-level model is not explicitly prohibited by the specification, and, indeed, the parser flagged no errors or warnings with this construction.
> 
> Unfortunately, many tools, especially those for which users must explicitly create input stimulus nodes, will probably not be able to use this kind of construction successfully (where, for example, do you tie the input stimulus from the core on an input-only top-level buffer model?). 
> 
> At this point, I can only conclude that a clarification BIRD should be written to add restrictions on the Model_type of [Driver Schedule] models.  A parser bug would be inappropriate, since the parser is faithfully following the language of the specification.
> 
> Any thoughts?
> 
> - Michael Mirmak, Intel Corp.


- -- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
2926 SE Yamhill St.                Device Modeling Division
Portland, OR 97214                 13610 SW Harness Lane
503-239-5536                       Beaverton, OR 97008
http://www.teraspeed.com           503-430-1065
bob@teraspeed.com                  503-246-8048 Direct

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------------------------------

Date: Mon, 21 Apr 2003 09:09:04 -0600
From: "rrwolff" <rrwolff@micron.com>
Subject: [IBIS-Users] [IBIS] Open forum minutes (04/18/03)

DATE: 04/21/03

SUBJECT: April 18, 2003 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2003 PARTICIPANTS LIST:
Ansoft Corporation             (Eric Bracken)
Apple Computer                 Kim Helliwell
Applied Simulation Technology  Fred Balistreri
Cadence Design                 Lynne Green*
Cisco Systems                  Syed Huq, Val Mandruson, Hung Pham 
Cypress Semiconductor          (Rajesh Manapat)
Fairchild Semiconductor        (Graham Connolly)
Hitachi ULSI Systems           Kazuyoshi Shoji
Huawei Technologies            (Jiang Xiang Zhong)
IBM                            (Pravin Patel)
Intel Corporation              Stephen Peters*, Michael Mirmak*,
                               Arpad Muranyi*
LSI Logic                      Frank Gasparik
Matsushita (Panasonic)         Atsuji Ito
Mentor Graphics                [Bob Ross], Ian Dodd, Guy de Burgh*,
                               John Angulo*, Mike Donnelly, Weston Beal 
Micron Technology              Randy Wolff*
Mitsubishi                     (Pat Hefferan)
Molex Incorporated             Gus Panella
Motorola                       (Rick Kingen)
National Semiconductor         [Milt Schwartz], Tim Coyle
NEC Electric Corporation       (Itsuki Yamada)
North East Systems Associates  Edward Sayre 
Philips Semiconductor          (D.C. Sessions), Stephanie Goedecke
Quantic EMC                    (Mike Ventham)
Siemens (& Automotive) AG      Eckhard Lenski, Michael Kindij, 
                               Burkhard Muller, Katja Koller, 
                               Andre Goerisch, Manfred Maurer, 
                               Bernard Unger, Amir Motamedi, 
                               Hartmut Ibowski, Gerald Bannert
Signal Integrity Software      Bob Haller*, Barry Katz, Doug Burns
Sigrity                        Raj Raghuram
SiQual                         (Rob Hinz)
Texas Instruments              Thomas Fisher
Teraspeed                      Scott McMorrow, Tom Dagostino,
                               Kevin Simpson, Bob Ross*
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Via Technologies               (Weber Chuang)
Zuken (& Incases)              Michael Schaeder, Ralf Bruning,

OTHER PARTICIPANTS IN 2003:
Agilent Technologies           Herbert Lage
Brocade                        Frank Yuan, Yongrue Yu
Conexant                       Gary Felker
EADS CCR                       Alix de la Villeguerin
EFM                            Ekkehard Miersch
EMC Corporation                Brian Arsenault
Fraunhofer IZM                 Ege Engin
Fujitsu                        Tadashi Arai
GEIA                           (Chris Denham)
Independent                    Kelly Green, Luca Giacotto
Infineon Tech AG               Christian Sporrer
Marvell Semiconductor          Itzik Peleg
NetLogic Microsystems          Eric Hsu
Plexus                         Joseph Socha
Politechnico de Torino         Igor Stievano
Sintecs BV                     Hans Klos, Bob te Nijenhuis
Xilinx                         Susan Wu


In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses. 
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are 
as follows:

  Date                Bridge Number    Reservation #    Passcode
  May 9, 2003         (916) 356-2663        1           8390090

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas 
out 7 days before each Open Forum, and meeting minutes out within 7 days 
after.  When you call into the meeting, ask for the IBIS Open Forum hosted 
by Stephen Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
No new members


CALL FOR PATENTS
Stephen Peters called for any patents or pending patents related to the 
IBIS Version 4.0 Standard. No companies declared a patent.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Stephen Peters reported that he has received a financial and ledger
statement for February 2003, but nothing more current. So far as Stephen is
aware, the total paid membership remains at 16 members. Stephen continues to
work with GEIA to obtain a current financial and dues payment report.


REVIEW OF MINUTES AND AR'S
Stephen Peters noted two minor corrections to the March 28, 2003 minutes.
The JEDEX class taught by Lynne Green was held in San Jose, not San Diego.  
Also, under the discussion of BUG73 (IBISCHK3 status agenda item) John 
Angulo requested that the following sentence be revised from:

"In brief, non-monotonic points in the clamp table cause the parser to
extrapolate the table endpoints incorrectly, thus the end point test fails."

to:
 
"In brief, the parser extrapolates non-monotonic end-points in the clamp 
table correctly, but the V-T end point test fails because of the 
non-monotonicity."


The March 28, 2003 minutes were approved with the above changes and Michael
Mirmack will upload the corrected minutes.

ARs will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
None.


PRESS AND WEB PAGE UPDATES
Bob Ross indicated that he will attend the Signal Propagation on
Interconnects (SPI2003) workshop as a keynote speaker on "IBIS Present
and Future" on Wednesday, May 14, 2003.

Stephen Peters reported that Syed Huq is making ongoing updates to the IBIS
roster and upcoming events link. 


NEW MODELS AVAILABLE, LIBRARY UPDATE
None.


OPENS FOR NEW ISSUES
None.


INTERNATIONAL/EXTERNAL PROGRESS
- - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) - No report.
- - JEDEC Activity Report. Nothing to report.


DAC2003 MEETING PLANNING
Stephen Peters reported that planning continues for the June 5, 2003 IBIS 
summit meeting, which will be held in conjunction with DAC2003 in Anaheim, 
California at the Anaheim Marriot hotel. Lynne Green has posted the first 
announcement to the reflector.  Stephen also noted that attendees should 
sign up with Guy de Burgh and start making their travel arrangements. 

Cost for the meeting is estimated to be between $2,300 and $2,500 depending 
on the number of attendees and the lunch selected. A vegetarian option would 
be about $30 a plate, a meat entree would be about $35 a plate. To reduce 
cost Stephen suggested eliminating the afternoon refreshments, which will 
save approximately $15 a person.  After discussion the group agreed to forgo
the afternoon refreshments and go with the vegetarian option for lunch.
John Angulo will follow up with the hotel. Stephen again mentioned that we
are looking for co-sponsors to fund part of or all of the lunch. 

Guy de Burgh indicated that he will supply an LCD projector. In response to
a question from John Angulo, we agreed to drop the overhead projector and
go with a flip chart package instead. Stephen asked Arpad Muranyi to inquire
if a local Intel office can be used as the dial-in point for a 
teleconference bridge.  

Stephen noted that the following presentations are planned (titles are 
tentative). 

IBIS Status Update, Stephen Peters (Intel Corp)
VHDL AMS Modeling, Arpad Muranyi (Intel Corp)  
Quality Committee Update, Barry Katz (SiSoft)

Lynne Green indicated that either herself or Michael Mirmak will be 
presenting an ICM specification update. 

In addition to presentations and discussion we will also be conducting
the annual election of officers.  The current slate of nominees and their 
positions are:

Chair           Michael Mirmak, Intel Corp.
Vice-Chair      Lynne Green, Cadence
Secretary       Randy Wolff, Micron
Librarian       Roy Leventhal, Leventhal Design and Communications
Webmaster       Syed Huq, Cisco
Postmaster      John Angulo, Mentor

Additional nominations are being accepted for all positions.  E-mail nominee
names to Stephen Peters.  Nominations will also be accepted at the summit
meeting.


DESIGNCON2003 EAST MEETING PLANNING
Stephen Peters reported that planning for an IBIS summit meeting at 
Designcon2003 East in continues. The summit is scheduled for June 23, 2003
in the Royal Plaza Hotel in Marlborough, Massachusetts. The meeting room
has yet to be determined. Stephen noted that we are also a co-sponsor of 
DesignCon2003 East. Barry Katz from SiSoft is serving as the contact for 
registration and sign-up, so if you are planning on attending please let 
Barry know. Stephen mentioned that we have traded refreshments for a
telephone line so that the meeting can be web telecast.   

It was noted that we will need to obtain an LCD projector for the room at
DAC. Stephen will inquire with potential attendees. Finally, Stephen noted
that the first meeting announcement has been posted to the reflector, and 
that a second announcement should follow in the coming week.


IBIS VERSION 4.0 PARSER FUNDING AND STATUS
Stephen Peters reported that he received an e-mail from Huawei confirming 
that they have sent in payment for the parser.  Stephen is still awaiting 
confirmation from GEIA that they have received the payment.  This brings
the total companies that have paid to six, with three more pending.

Stephen has not heard back from Atul Agarwal on parser progress. It was 
noted that when we do receive the prototype code John Angulo and Matthew 
Flora will be in charge of testing. 


IBIS QUALITY COMMITTEE
Bob Haller reported on the IBIS Quality Committee meeting held on April 8, 
2003. The quality committee is about half way through its document review 
and is currently working on the model section. The next meeting is 
scheduled for April 22, 2003.  


IBIS MODEL REVIEW COMMITTEE
Lynne Green reported that they have received and distributed a model from
Phillips.


NEW ADMINISTRATIVE ISSUES
None.


IBIS FUTURES AND CONNECTOR WORKING GROUP REPORT
Stephen Peters reported that the IBIS connector working group met on April
4, 2003 and again on April 10, 2003. The editorial comments on the
Touchstone specification have been addressed, although the document itself 
has yet to be updated. On the ICM specification itself a 'Draft E' has been 
issued, however there remain two open issues. One issue involves the exact
definition of "text block". The other issue involves the proper way to
designate AC return paths in the matrices. After discussion the connector
working group members agreed to hold a meeting on April 24, 2003 to resolve
these final issues, with the expectation that they would then release the
final draft 1.0 ICM specification to the IBIS Open Forum.


BIRD74.2 - EMI Parameters
Stephen Peters opened the discussion by noting that Guy de Burgh posted to 
the IBIS reflector a recap of BIRD74.2 for discussion.  Guy stated that it 
has been almost a year since we have had technical discussions on this BIRD.

After a short overview of the BIRD's history a technical discussion ensued. 
Stephen asked what was the intent of the "Family" keyword. Guy replied that
this keyword was intended to cover cases in which critical information about
a part was not available, but could be estimated if one knew the logic
family type. After discussion Guy agreed that if information is critical it
should be present, and he is in favor of removing this keyword. Guy also
clarified that the frequency parameter was meant to specify the operating
frequency of the I/O pins as a ratio of the highest internal frequency. 

There were several questions on the 'heatsink capacitance' parameter. 
Stephen asked how to derive this parameter. Guy stated that the intent
is to estimate heatsink capacitance assuming a traditional parallel plate
configuration between the heatsink and PCB power/gnd plane. Bob Ross and
others asked how this parameter would be used in cases where a heatsink
is optional.  The consensus was that two IBIS models would be required,
depending on if the heatsink is present or not. However, there may be
other issues that need to be explored. 

Finally, Stephen suggested renaming the proposed voltage range parameter to
"signal swing".  Several folks pointed out that signal swing could be derived
from the existing I-V tables, and that may be even more applicable. 
(However, it was later noted that in IBIS 4.1, I-V tables might not always
be available). Stephen asked what would be entered for voltage swing for a
serial bus that employs equalization techniques such as de-emphasis.  Guy
replied that the intent was to capture the average signal swing. No
conclusion was reached on what was meant by average. 

Guy will issue BIRD74.3 with changes for more discussion at the next
teleconference. 


IBISCHK3 & BUG TRACKING STATUS
John Angulo reported that he has looked into a proposed fix for BUG73,
"Extreme Non-monotonic I-V Tables Cause End Point Test to Fail". In brief,
John proposed that the parser should ignore any intersection points that
lie beyond the ground or power rail values.  John noted that BUG73 was
actually introduced by the fix for BUG57, and the proposed fix for BUG73
was actually a better fix for BUG57.  John will prototype this bug fix and,
if it works, forward it to Atul Agarwal for incorporation into the IBIS
4.0 parser. 

- - BUG71 - Monotonic Checking for Combined I-V Tables
  Bob Haller posted to the reflector an updated table for BUG 71 that added
  entries for ECL models and terminators.  Stephen noted that by combining 
  curves, interpolation of voltage points may be required, and he wondered
  if this might introduce unintended non-monotonic errors. No one was sure
  if the current parser has a limit that prevents very small voltage
  differences from causing non-monotonic errors. It was also noted by
  several individuals that the first row of the posted table ('Input'
  model type) has a TAB error that causes the 'XXX' values to show up in
  the wrong column.  Michael Mirmak will fix this error before uploading 
  the table to the BUG report. After discussion we decided we needed more
  time to verify the table.  We will assign a final resolution at the
  next meeting. 

- - BUG74 - Missing Timing Test Load Warning Messages
  Stephen Peters posted the clarification text to the IBIS reflector. After
  discussion we agreed to accept the revised table and classify the
  BUG as 'to be fixed'.  Michael Mirmak will upload the updated bug report.


NEXT MEETING:
The next teleconference meeting is scheduled for May 9, 2003 from 8:00
AM to 10:00 AM Pacific Daylight Time.
============================================================================
                               NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            stephen.peters@intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Lynne Green (425) 788-0412, Fax: (425) 788-4289
            lgreen@cadence.com
            Senior Modeling Engineer, Cadence Design Systems
            20 120th Ave NE, Suite 103, Bellevue, WA 98005-3016

SECRETARY:  Randy Wolff (208) 363-1764, Fax: (208) 368-3475
            rrwolff@micron.com
            Simulation Engineer, Micron Technology, Inc.
            8000 S. Federal Way
            Mail Stop: 711
            Boise, ID 83707-0006
        
LIBRARIAN:  Roy Leventhal (847) 590-9398
            roy.leventhal@ieee.org
            Consultant, Leventhal Design and Communications
            1924 North Burke Drive
            Arlington Heights, Illinois 60004

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
            John_angulo@mentor.com
            Development Engineer, Mentor Graphics
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA 
Manual of Organization and Procedure.

The following e-mail addresses are used:

  majordomo@eda.org
      In the body, for the IBIS Open Forum Reflector:
      subscribe ibis <your e-mail address>

      In the body, for the IBIS Users' Group Reflector:
      subscribe ibis-users <your e-mail address>

      Help and other commands:
      help

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
      bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
      /pub/ibis/bugs/s2iplt/bugsplt.txt respectively.

Information on IBIS technical contents, IBIS participants, and actual IBIS 
models are available on the IBIS Home page found by selecting the Electronic 
Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.

============================================================================
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|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Mon, 21 Apr 2003 08:37:54 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] Sticky problem in [Driver Schedule]

OK, I admit, I was an idiot to write those long sentences that no one
can figure out, but I guess the fact that everyone on the Open Forum
who voted on it and didn't request a better wording are the same...

Arpad
=====================================================================

Bob Ross

(P.S., I cannot help noting that BIRD58.3 from your company
provide "improved" editorial revisions including some long
sentences.)
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------------------------------

Date: Mon, 21 Apr 2003 10:35:47 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: [IBIS-Users] RE: [IBIS] Open forum minutes (04/18/03)

I had an AR to check whether the Hotel in Anaheim and our Intel office
in Irvine are local calls distance from each other.  The Anaheim Marriott
phone number is (714) 750-8000 and the Intel Irvine phone number is 
(949) 567-xxxx.  From this and looking at the map I believe that it
will be long distance call to Intel from Anaheim.

Arpad
========================================================================

- -----Original Message-----
From: rrwolff [mailto:rrwolff@micron.com]
Sent: Monday, April 21, 2003 8:09 AM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS] Open forum minutes (04/18/03)

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------------------------------

Date: Thu, 24 Apr 2003 13:44:27 -0700
From: "Angulo, John" <john_angulo@mentorg.com>
Subject: [IBIS-Users] IBIS models for ECLinPS

The following is posted on behalf of Kirti Barpande.  Please send any private replies to kirti@cat.ernet.in only.

- ----------
Hello!
 I want IBIS models for few ECLinPS series ICs, Make Micrel-Synergy. From 
where I can down load these models? Micrel is not supplying these models.
Kirti,
CAT,INDORE,INDIA
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------------------------------

Date: Thu, 24 Apr 2003 16:54:09 -0700
From: Wil Ngan <wngan@idt.com>
Subject: [IBIS-Users] IBIS generation w/ two power supplies

hi,

I'm trying to generate an ibis file from a circuit with two power supplies,
vcc and vccq. Vcc is fixed at 5v, while vccq is either 3.3 or 5v,
depending on what we would like the output high to be. How do I going
about doing this?

In the past, I've used [Pullup reference], [Power clamp reference] to
set vcc to 5v, vccq to 3.3v, respectively. However,  I just realized
that I cannot set vccq using [power clamp reference], since there's actually

NO power clamp in my circuit. (The ckt only has ground clamp transistors,
which protects the device from overly low input voltages, at same time, that

same device works to protect high input  voltages through breakdown.)
I had been generating [Power clamp] current table while in fact there is no
power clamp circuit. Not good. Furthermore, this causes [Pullup] current
table
to be wrong, since [Pullup]currents =  I(pullup generated by hspice) -
I(power clamp), so the numbers in  my [Pullup] table are actually lower
than they should be.

So, going back to the original question, without using [Pullup reference] or

[Power clamp reference], how should I go about in providing two power
supplies to this circuit to generate ibis file?

- - Wil
idt sram, 408/330-1623.


|------------------------------------------------------------------
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|with just the appropriate command message(s) in the body:
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------------------------------

Date: Thu, 24 Apr 2003 17:38:16 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: [IBIS-Users] RE: [IBIS] IBIS generation w/ two power supplies

Wil,

It sounds that your pullup's reference voltage is programmable,
correct?

In that case, you should use the model selector and make two
models, on with [Pullup Reference] = 3.3 V, and the other with
[Pullup Reference] = 5 V.

Arpad Muranyi
Intel Corporation
=============================================================

- -----Original Message-----
From: Wil Ngan [mailto:wngan@idt.com] 
Sent: Thursday, April 24, 2003 4:54 PM
To: ibis@eda.org; ibis-users@eda.org; ibis-info@eda.org
Subject: [IBIS] IBIS generation w/ two power supplies


hi,

I'm trying to generate an ibis file from a circuit with two power
supplies, vcc and vccq. Vcc is fixed at 5v, while vccq is either 3.3 or
5v, depending on what we would like the output high to be. How do I
going about doing this?

In the past, I've used [Pullup reference], [Power clamp reference] to
set vcc to 5v, vccq to 3.3v, respectively. However,  I just realized
that I cannot set vccq using [power clamp reference], since there's
actually

NO power clamp in my circuit. (The ckt only has ground clamp
transistors, which protects the device from overly low input voltages,
at same time, that

same device works to protect high input  voltages through breakdown.) I
had been generating [Power clamp] current table while in fact there is
no power clamp circuit. Not good. Furthermore, this causes [Pullup]
current table to be wrong, since [Pullup]currents =  I(pullup generated
by hspice) - I(power clamp), so the numbers in  my [Pullup] table are
actually lower than they should be.

So, going back to the original question, without using [Pullup
reference] or

[Power clamp reference], how should I go about in providing two power
supplies to this circuit to generate ibis file?

- - Wil
idt sram, 408/330-1623.


- -----------------------------------------------------------------
|For help or to subscribe/unsubscribe, email majordomo@eda.org with the 
|appropriate command message(s) in the body:
|
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|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Fri, 25 Apr 2003 09:54:57 -0700
From: Wil Ngan <wngan@idt.com>
Subject: [IBIS-Users] Re: [IBIS] IBIS generation w/ two power supplies

Arpad,

I could set [Pullup reference] to 3.3v or 5v, but with what
parameter do I set the main power supply at 5v? (in both
case)

Wil

"Muranyi, Arpad" wrote:

> Wil,
>
> It sounds that your pullup's reference voltage is programmable,
> correct?
>
> In that case, you should use the model selector and make two
> models, on with [Pullup Reference] = 3.3 V, and the other with
> [Pullup Reference] = 5 V.
>
> Arpad Muranyi
> Intel Corporation
> =============================================================
>
> -----Original Message-----
> From: Wil Ngan [mailto:wngan@idt.com]
> Sent: Thursday, April 24, 2003 4:54 PM
> To: ibis@eda.org; ibis-users@eda.org; ibis-info@eda.org
> Subject: [IBIS] IBIS generation w/ two power supplies
>
> hi,
>
> I'm trying to generate an ibis file from a circuit with two power
> supplies, vcc and vccq. Vcc is fixed at 5v, while vccq is either 3.3 or
> 5v, depending on what we would like the output high to be. How do I
> going about doing this?
>
> In the past, I've used [Pullup reference], [Power clamp reference] to
> set vcc to 5v, vccq to 3.3v, respectively. However,  I just realized
> that I cannot set vccq using [power clamp reference], since there's
> actually NO power clamp in my circuit. (The ckt only has ground clamp
> transistors, which protects the device from overly low input voltages,
> at same time, that same device works to protect high input  voltages
> through breakdown.) I

> had been generating [Power clamp] current table while in fact there is

> no power clamp circuit. Not good. Furthermore, this causes [Pullup]

> current table to be wrong, since [Pullup]currents =  I(pullup generated
> by hspice) - I(power clamp), so the numbers in  my [Pullup] table are
> actually lower than they should be.
>
> So, going back to the original question, without using [Pullup
> reference] or
>
> [Power clamp reference], how should I go about in providing two power
> supplies to this circuit to generate ibis file?
>
> - Wil
> idt sram, 408/330-1623.
>
> -----------------------------------------------------------------
> |For help or to subscribe/unsubscribe, email majordomo@eda.org with the
> |appropriate command message(s) in the body:
> |
> |  help
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------------------------------

Date: Fri, 25 Apr 2003 10:05:11 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: [IBIS-Users] RE: [IBIS] IBIS generation w/ two power supplies

Wil,

If your "main power supply" is basically the core voltage of
your chip, then you don't need to mention it in the IBIS model.
IBIS only cares about the I/O supply voltage(s).  In other words,
you only need to define those voltages in IBIS to which the
pullup, puldown and the clamp devices are connected in the
circuit.

Arpad
=================================================================

- -----Original Message-----
From: Wil Ngan [mailto:wngan@idt.com]
Sent: Friday, April 25, 2003 9:55 AM
To: Muranyi, Arpad
Cc: ibis@eda.org; ibis-users@eda.org; ibis-info@eda.org
Subject: Re: [IBIS] IBIS generation w/ two power supplies


Arpad,

I could set [Pullup reference] to 3.3v or 5v, but with what
parameter do I set the main power supply at 5v? (in both
case)

Wil

"Muranyi, Arpad" wrote:

> Wil,
>
> It sounds that your pullup's reference voltage is programmable,
> correct?
>
> In that case, you should use the model selector and make two
> models, on with [Pullup Reference] = 3.3 V, and the other with
> [Pullup Reference] = 5 V.
>
> Arpad Muranyi
> Intel Corporation
> =============================================================
>
> -----Original Message-----
> From: Wil Ngan [mailto:wngan@idt.com]
> Sent: Thursday, April 24, 2003 4:54 PM
> To: ibis@eda.org; ibis-users@eda.org; ibis-info@eda.org
> Subject: [IBIS] IBIS generation w/ two power supplies
>
> hi,
>
> I'm trying to generate an ibis file from a circuit with two power
> supplies, vcc and vccq. Vcc is fixed at 5v, while vccq is either 3.3 or
> 5v, depending on what we would like the output high to be. How do I
> going about doing this?
>
> In the past, I've used [Pullup reference], [Power clamp reference] to
> set vcc to 5v, vccq to 3.3v, respectively. However,  I just realized
> that I cannot set vccq using [power clamp reference], since there's
> actually NO power clamp in my circuit. (The ckt only has ground clamp
> transistors, which protects the device from overly low input voltages,
> at same time, that same device works to protect high input  voltages
> through breakdown.) I

> had been generating [Power clamp] current table while in fact there is

> no power clamp circuit. Not good. Furthermore, this causes [Pullup]

> current table to be wrong, since [Pullup]currents =  I(pullup generated
> by hspice) - I(power clamp), so the numbers in  my [Pullup] table are
> actually lower than they should be.
>
> So, going back to the original question, without using [Pullup
> reference] or
>
> [Power clamp reference], how should I go about in providing two power
> supplies to this circuit to generate ibis file?
>
> - Wil
> idt sram, 408/330-1623.
>
> -----------------------------------------------------------------
> |For help or to subscribe/unsubscribe, email majordomo@eda.org with the
> |appropriate command message(s) in the body:
> |
> |  help
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> |
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> -----------------------------------------------------------------
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|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Mon, 28 Apr 2003 20:56:11 -0400
From: "Lynne Green" <lgreen@cadence.com>
Subject: [IBIS-Users] DAC Summit, Second Call for Papers

- -----------------------------------------------------------------------
                       IBIS SUMMIT
                     SECOND CALL FOR
               PARTICIPATION & PRESENTATIONS
- -----------------------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

              I B I S   S U M M I T   M E E T I N G

Time/Date:  Thursday June 5, 2003,  8:00 AM to 5:00 PM

Location:   Marriot Hotel
            Anaheim, CA

Content:    Presentations and Discussions

Purpose:    Solicit and Exchange IBIS Model Related Information and
Ideas.

Sponsors:   If your company would be interested in helping to
            sponsor this event, please contact Lynne Green
            <lgreen@cadence.com>.  Sponsors are needed for the lunch
            and coffee breaks.

DAC:        June 2-6, 2003
            Anaheim Convention Center
            Anaheim, California
            See <http://www.dac.com/> for more information.

BACKGROUND

DesignCon is the premier annual Silicon Valley event for the
electronic design automation (EDA) and semiconductor industry.
Topics of current interest to the EIA IBIS Open Forum are
addressed at DAC.

This meeting will be conducted as a formal IBIS Summit Meeting.
Presentations are expected to be available and archived in an
electronic format, and minutes of the meeting will be issued.
Any pending formal decisions (votes) will be announced at least
two weeks prior to the meeting.

The annual election of officers will be held.  Nominations can
be sent to Stephen Peters <stephen.peters@intel.com> or made at
the meeting.


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development,
and digital circuit design are invited to participate to the
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Send to:

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Format of Presentation:  LCD Projection with Windows laptop.
Time:			15-30 Minutes
Electronic Archival: We request electronic versions so that the
                  presentations can be archived and also made
                  available to non-attendees.  Formats used in
                  the past have been text, Power Point, Word,
                  Postscript, and Acrobat.  Electronic copies
                  of presentations should be made available by
                  May 30, 2003 for uploading and copying to the
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If you plan a presentation, please supply

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Also, please indicate if you are also interested in presenting
this presentation at DesignCon East, Marlborough, MA, on June
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Send this to:

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AGENDA

The agenda includes presentations, discussions, breaks, and a
luncheon (which will be provided).  This will be developed as
presentation proposals are received.

The following individuals have signed up to present at the
summit (presentation titles are tentative).
* Atsuji Ito, Observations on Problems Encountered
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LIST OF NEARBY HOTELS

See <http://www.dac.com/40th/travel.html> for travel directions,
hotels and other information.
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------------------------------

Date: Tue, 29 Apr 2003 17:44:12 +0300
From: Lior Aviv <RM18440@email.sps.mot.com>
Subject: [IBIS-Users] about Vref

Hello,

I have IO that works with 3.3v +-10%.
The output resistance is 50 Ohm.
My questions are regarding the Vref parameter -
1. Who should set it and how?
2. While running the ibis checker3, I have noticed that there is a
relation
    between the Vref and the Vmeas but could not understand what does
the
    checker exactly check with these parameters.
    The  warnings I get are not so clear -
    " Model 'xxx': MIN VI curves cannot drive through Vmeas=1.5V
      given load Rref=50 Ohms to Vref=zzzV ".

Thanks,
Lior Aviv,
               MSIL.

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------------------------------

Date: Tue, 29 Apr 2003 08:52:02 -0700
From: "Tom Dagostino" <tom@teraspeed.com>
Subject: [IBIS-Users] RE: [IBIS] about Vref

Vref is part of the Timing Test Load.  This is the load that the
manufacturer guarantees the timing of the component.  The Timing Test Load
is made up of three parts, Vref, Rref and Cref.  Rref is a resistor tied
between the output of the device and the reference voltage Vref. Cref is
connected to the output and to ground.  These values are selected by the
manufacturer or are specified in some cases by the standard interface the
logic drives.

Vmeas is the voltage value that timing is measured to.  It is also part of
the timing specification.

Usually when you get the warning listed in your note either the driver is
too weak to drive the Timing Test Load or the wrong Timing Test Load was
included.  I've also seen Timing Test Loads for open sink drivers (open
drain/open collector) that have Vref = 0.  This will not work at all.  An
open sink needs a Vref usually at Vdd.

Tom Dagostino
Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
2926 SE Yamhill St.                Device Modeling Division
Portland, OR 97214                 13610 SW Harness Lane
                                   Beaverton, OR 97008
http://www.teraspeed.com           503-430-1065
tom@teraspeed.com


- -----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org]On
Behalf Of Lior Aviv
Sent: Tuesday, April 29, 2003 7:44 AM
To: ibis@server.eda.org; ibis-users@server.eda.org;
ibis-info@server.eda.org
Subject: [IBIS] about Vref



Hello,

I have IO that works with 3.3v +-10%.
The output resistance is 50 Ohm.
My questions are regarding the Vref parameter -
1. Who should set it and how?
2. While running the ibis checker3, I have noticed that there is a
relation
    between the Vref and the Vmeas but could not understand what does
the
    checker exactly check with these parameters.
    The  warnings I get are not so clear -
    " Model 'xxx': MIN VI curves cannot drive through Vmeas=1.5V
      given load Rref=50 Ohms to Vref=zzzV ".

Thanks,
Lior Aviv,
               MSIL.

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------------------------------

Date: Wed, 30 Apr 2003 15:32:49 -0700
From: "Eric Hsu" <ehsu@netlogicmicro.com>
Subject: [IBIS-Users] model issue for input receiver

This is a multi-part message in MIME format.

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Hi

Can I choose "terminator" as my [model type] if I have an input receiver =
with on die terminator? If true, can I also use subparameters [Vinh] and =
[Vinl] to define input threshold voltage? If true, then what is the =
meaning of "...but has no digital logic thresholds..." for terminator =
model in IBIS spec. 3.2 version, page20?

Best Regards,

Eric Hsu
Interface Technologies
NetLogic Microsystems, Inc.
450 National Ave.
Mountain View, CA 94043
650-961-6676 x198

CONFIDENTIALITY NOTICE
This message is intended only for the individual or entity to which it =
is=20
addressed and may contain information that is privileged, confidential =
and=20
exempt from disclosure under applicable law or contract. If you are not=20
the intended recipient, or the employee or agent responsible for=20
delivering the message to the intended recipient, you are hereby =
notified=20
that any dissemination, distribution or copying of this communication is =

strictly prohibited, and we ask that you delete this message and notify =
us=20
by return email. Thank you for your cooperation.
This e-mail contains NetLogic Microsystems, Inc. Confidential =
information



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------------------------------

Date: Wed, 30 Apr 2003 15:40:38 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: [IBIS-Users] RE: model issue for input receiver

Eric,

No.  The reason is because the difference between a terminator and an input is
that the first one just terminates, and doesn't have Vinh and Vinl.  If you
want to make an input model that also has an on-die terminator, you have to
put the terminator's characteristics into one or the other clamp IV curves.

Arpad
==============================================================================

>  -----Original Message-----
> From: 	Eric Hsu [mailto:ehsu@netlogicmicro.com] 
> Sent:	Wednesday, April 30, 2003 3:33 PM
> To:	Ibis-Users (E-mail)
> Cc:	Frank Dunlap
> Subject:	model issue for input receiver
> 
> Hi
> 
> Can I choose "terminator" as my [model type] if I have an input receiver with on die terminator? If true, can I also use subparameters [Vinh] and [Vinl] to define input threshold voltage? If true, then what is the meaning of "...but has no digital logic thresholds..." for terminator model in IBIS spec. 3.2 version, page20?
> 
> Best Regards,
> 
> Eric Hsu
> Interface Technologies
> NetLogic Microsystems, Inc.
> 450 National Ave.
> Mountain View, CA 94043
> 650-961-6676 x198
> 
> CONFIDENTIALITY NOTICE
> This message is intended only for the individual or entity to which it is 
> addressed and may contain information that is privileged, confidential and 
> exempt from disclosure under applicable law or contract. If you are not 
> the intended recipient, or the employee or agent responsible for 
> delivering the message to the intended recipient, you are hereby notified 
> that any dissemination, distribution or copying of this communication is 
> strictly prohibited, and we ask that you delete this message and notify us 
> by return email. Thank you for your cooperation.
> This e-mail contains NetLogic Microsystems, Inc. Confidential information
> 
> 
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------------------------------

Date: Wed, 30 Apr 2003 16:10:43 -0700
From: "Eric Hsu" <ehsu@netlogicmicro.com>
Subject: [IBIS-Users] RE: model issue for input receiver

This is a multi-part message in MIME format.

- ------_=_NextPart_001_01C30F6D.B98C8A0B
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	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi Tom and Muranyi,

Do you mean there is no difference for input receiver when generating =
ibis model? No matter it has or not terminator resistor on chip, I =
always can use the same model type like input?
Thanks for your guidance!

Best Regards,

Eric Hsu
Interface Technologies
NetLogic Microsystems, Inc.
450 National Ave.
Mountain View, CA 94043
650-961-6676 x198

CONFIDENTIALITY NOTICE
This message is intended only for the individual or entity to which it =
is=20
addressed and may contain information that is privileged, confidential =
and=20
exempt from disclosure under applicable law or contract. If you are not=20
the intended recipient, or the employee or agent responsible for=20
delivering the message to the intended recipient, you are hereby =
notified=20
that any dissemination, distribution or copying of this communication is =

strictly prohibited, and we ask that you delete this message and notify =
us=20
by return email. Thank you for your cooperation.
This e-mail contains NetLogic Microsystems, Inc. Confidential =
information


>  -----Original Message-----
> From: 	Tom Dagostino [mailto:tom@teraspeed.com]=20
> Sent:	Wednesday, April 30, 2003 3:54 PM
> To:	Eric Hsu
> Subject:	RE: model issue for input receiver
>=20
> If you use terminator you do not have an input model but a model of a =
resistor. An input model is what you want with the characteristic of the =
on die resistor embedded in one of the clamp curves.
>=20
> Tom Dagostino
>=20
> Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
>=20
> 2926 SE Yamhill St.                Device Modeling Division
>=20
> Portland, OR 97214                 13610 SW Harness Lane
>=20
>                                    Beaverton, OR 97008
>=20
> http://www.teraspeed.com           503-430-1065=20
>=20
> tom@teraspeed.com
>=20
> 	 -----Original Message-----
> 	From: 	Eric Hsu [mailto:owner-ibis-users@server.eda.org]  On Behalf =
Of Eric Hsu
> 	Sent:	Wednesday, April 30, 2003 3:33 PM
> 	To:	Ibis-Users (E-mail)
> 	Cc:	Frank Dunlap
> 	Subject:	model issue for input receiver
>=20
> 	Hi
>=20
> 	Can I choose "terminator" as my [model type] if I have an input =
receiver with on die terminator? If true, can I also use subparameters =
[Vinh] and [Vinl] to define input threshold voltage? If true, then what =
is the meaning of "...but has no digital logic thresholds..." for =
terminator model in IBIS spec. 3.2 version, page20?
>=20
> 	Best Regards,
>=20
> 	Eric Hsu
> 	Interface Technologies
> 	NetLogic Microsystems, Inc.
> 	450 National Ave.
> 	Mountain View, CA 94043
> 	650-961-6676 x198
>=20
> 	CONFIDENTIALITY NOTICE
> 	This message is intended only for the individual or entity to which =
it is=20
> 	addressed and may contain information that is privileged, =
confidential and=20
> 	exempt from disclosure under applicable law or contract. If you are =
not=20
> 	the intended recipient, or the employee or agent responsible for=20
> 	delivering the message to the intended recipient, you are hereby =
notified=20
> 	that any dissemination, distribution or copying of this communication =
is=20
> 	strictly prohibited, and we ask that you delete this message and =
notify us=20
> 	by return email. Thank you for your cooperation.
> 	This e-mail contains NetLogic Microsystems, Inc. Confidential =
information
>=20
>=20

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------------------------------

Date: Wed, 30 Apr 2003 16:55:23 -0700
From: "Tom Dagostino" <tom@teraspeed.com>
Subject: [IBIS-Users] RE: model issue for input receiver

This is a multi-part message in MIME format.

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Jeff

An input has several characteristics.  One is input C or C_comp, another is
the input thresholds such as Vinh and Vinl.  A third characteristic are the
clamp characteristics.  Another is the DC input resistance.  For most CMOS
inputs this input resistance is very high, so high that we can neglect it
(OK, it shows up as nAmps or pAmps).  But for the case where the input
resistance of the receiver is finite, like a 50 Ohm termination, we need to
model it.  We place that model in one of the clamp tables.

A terminator has input C and input R but has no ability to differentiate
between a logic low and a logic high.  Thus a terminator model cannot be
used for an input which has thresholds it needs to let the simulator
understand.

So, input and terminator models are not interchangeable.  They have
different applications.  But inside the input model we can describe a
termination.


Tom Dagostino
Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
2926 SE Yamhill St.                Device Modeling Division
Portland, OR 97214                 13610 SW Harness Lane
                                   Beaverton, OR 97008
http://www.teraspeed.com           503-430-1065 
tom@teraspeed.com 


- -----Original Message-----
From: Eric Hsu [mailto:ehsu@netlogicmicro.com]
Sent: Wednesday, April 30, 2003 4:11 PM
To: tom@teraspeed.com; Muranyi, Arpad
Cc: Ibis-Users (E-mail)
Subject: RE: model issue for input receiver


Hi Tom and Muranyi,

Do you mean there is no difference for input receiver when generating ibis
model? No matter it has or not terminator resistor on chip, I always can use
the same model type like input?
Thanks for your guidance!

Best Regards,

Eric Hsu
Interface Technologies
NetLogic Microsystems, Inc.
450 National Ave.
Mountain View, CA 94043
650-961-6676 x198

CONFIDENTIALITY NOTICE
This message is intended only for the individual or entity to which it is 
addressed and may contain information that is privileged, confidential and 
exempt from disclosure under applicable law or contract. If you are not 
the intended recipient, or the employee or agent responsible for 
delivering the message to the intended recipient, you are hereby notified 
that any dissemination, distribution or copying of this communication is 
strictly prohibited, and we ask that you delete this message and notify us 
by return email. Thank you for your cooperation.
This e-mail contains NetLogic Microsystems, Inc. Confidential information


>  -----Original Message-----
> From: 	Tom Dagostino [mailto:tom@teraspeed.com] 
> Sent:	Wednesday, April 30, 2003 3:54 PM
> To:	Eric Hsu
> Subject:	RE: model issue for input receiver
> 
> If you use terminator you do not have an input model but a model of a
resistor. An input model is what you want with the characteristic of the on
die resistor embedded in one of the clamp curves.
> 
> Tom Dagostino
> 
> Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
> 
> 2926 SE Yamhill St.                Device Modeling Division
> 
> Portland, OR 97214                 13610 SW Harness Lane
> 
>                                    Beaverton, OR 97008
> 
> http://www.teraspeed.com           503-430-1065 
> 
> tom@teraspeed.com
> 
> 	 -----Original Message-----
> 	From: 	Eric Hsu [mailto:owner-ibis-users@server.eda.org]  On Behalf
Of Eric Hsu
> 	Sent:	Wednesday, April 30, 2003 3:33 PM
> 	To:	Ibis-Users (E-mail)
> 	Cc:	Frank Dunlap
> 	Subject:	model issue for input receiver
> 
> 	Hi
> 
> 	Can I choose "terminator" as my [model type] if I have an input
receiver with on die terminator? If true, can I also use subparameters
[Vinh] and [Vinl] to define input threshold voltage? If true, then what is
the meaning of "...but has no digital logic thresholds..." for terminator
model in IBIS spec. 3.2 version, page20?
> 
> 	Best Regards,
> 
> 	Eric Hsu
> 	Interface Technologies
> 	NetLogic Microsystems, Inc.
> 	450 National Ave.
> 	Mountain View, CA 94043
> 	650-961-6676 x198
> 
> 	CONFIDENTIALITY NOTICE
> 	This message is intended only for the individual or entity to which
it is 
> 	addressed and may contain information that is privileged,
confidential and 
> 	exempt from disclosure under applicable law or contract. If you are
not 
> 	the intended recipient, or the employee or agent responsible for 
> 	delivering the message to the intended recipient, you are hereby
notified 
> 	that any dissemination, distribution or copying of this
communication is 
> 	strictly prohibited, and we ask that you delete this message and
notify us 
> 	by return email. Thank you for your cooperation.
> 	This e-mail contains NetLogic Microsystems, Inc. Confidential
information
> 
> 

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Date: Wed, 30 Apr 2003 17:32:42 -0700
From: "Eric Hsu" <ehsu@netlogicmicro.com>
Subject: [IBIS-Users] RE: model issue for input receiver

Hi Tom, Muranyi, and Bob,

Thanks for your clear answer. It's really helpful for me.
There is the other related question. When characterizing C_comp, should spice netlist consider every thing on die, including clamping diode (or transistor) and terminator resistor?
Bob, do you mind also providing your professional comment for that? (I still remember you had a very good and practical presentation mention about C_comp characterization in designcon2003, such as "Frequency domain" or "Time domain" Techniques.)

Best Regards,

Eric Hsu
Interface Technologies
NetLogic Microsystems, Inc.
450 National Ave.
Mountain View, CA 94043
650-961-6676 x198

CONFIDENTIALITY NOTICE
This message is intended only for the individual or entity to which it is 
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- -----Original Message-----
From: Tom Dagostino [mailto:tom@teraspeed.com]
Sent: Wednesday, April 30, 2003 4:55 PM
To: Eric Hsu; 'Muranyi, Arpad'
Cc: 'Ibis-Users (E-mail)'
Subject: RE: model issue for input receiver


Jeff

An input has several characteristics.  One is input C or C_comp, another is the input thresholds such as Vinh and Vinl.  A third characteristic are the clamp characteristics.  Another is the DC input resistance.  For most CMOS inputs this input resistance is very high, so high that we can neglect it (OK, it shows up as nAmps or pAmps).  But for the case where the input resistance of the receiver is finite, like a 50 Ohm termination, we need to model it.  We place that model in one of the clamp tables.

A terminator has input C and input R but has no ability to differentiate between a logic low and a logic high.  Thus a terminator model cannot be used for an input which has thresholds it needs to let the simulator understand.

So, input and terminator models are not interchangeable.  They have different applications.  But inside the input model we can describe a termination.


Tom Dagostino
Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
2926 SE Yamhill St.                Device Modeling Division
Portland, OR 97214                 13610 SW Harness Lane
                                   Beaverton, OR 97008
http://www.teraspeed.com           503-430-1065 
tom@teraspeed.com 


- -----Original Message-----
From: Eric Hsu [mailto:ehsu@netlogicmicro.com]
Sent: Wednesday, April 30, 2003 4:11 PM
To: tom@teraspeed.com; Muranyi, Arpad
Cc: Ibis-Users (E-mail)
Subject: RE: model issue for input receiver


Hi Tom and Muranyi,

Do you mean there is no difference for input receiver when generating ibis model? No matter it has or not terminator resistor on chip, I always can use the same model type like input?
Thanks for your guidance!

Best Regards,

Eric Hsu
Interface Technologies
NetLogic Microsystems, Inc.
450 National Ave.
Mountain View, CA 94043
650-961-6676 x198

CONFIDENTIALITY NOTICE
This message is intended only for the individual or entity to which it is 
addressed and may contain information that is privileged, confidential and 
exempt from disclosure under applicable law or contract. If you are not 
the intended recipient, or the employee or agent responsible for 
delivering the message to the intended recipient, you are hereby notified 
that any dissemination, distribution or copying of this communication is 
strictly prohibited, and we ask that you delete this message and notify us 
by return email. Thank you for your cooperation.
This e-mail contains NetLogic Microsystems, Inc. Confidential information


>  -----Original Message-----
> From: 	Tom Dagostino [mailto:tom@teraspeed.com] 
> Sent:	Wednesday, April 30, 2003 3:54 PM
> To:	Eric Hsu
> Subject:	RE: model issue for input receiver
> 
> If you use terminator you do not have an input model but a model of a resistor. An input model is what you want with the characteristic of the on die resistor embedded in one of the clamp curves.
> 
> Tom Dagostino
> 
> Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
> 
> 2926 SE Yamhill St.                Device Modeling Division
> 
> Portland, OR 97214                 13610 SW Harness Lane
> 
>                                    Beaverton, OR 97008
> 
> http://www.teraspeed.com           503-430-1065 
> 
> tom@teraspeed.com
> 
> 	 -----Original Message-----
> 	From: 	Eric Hsu [mailto:owner-ibis-users@server.eda.org]  On Behalf Of Eric Hsu
> 	Sent:	Wednesday, April 30, 2003 3:33 PM
> 	To:	Ibis-Users (E-mail)
> 	Cc:	Frank Dunlap
> 	Subject:	model issue for input receiver
> 
> 	Hi
> 
> 	Can I choose "terminator" as my [model type] if I have an input receiver with on die terminator? If true, can I also use subparameters [Vinh] and [Vinl] to define input threshold voltage? If true, then what is the meaning of "...but has no digital logic thresholds..." for terminator model in IBIS spec. 3.2 version, page20?
> 
> 	Best Regards,
> 
> 	Eric Hsu
> 	Interface Technologies
> 	NetLogic Microsystems, Inc.
> 	450 National Ave.
> 	Mountain View, CA 94043
> 	650-961-6676 x198
> 
> 	CONFIDENTIALITY NOTICE
> 	This message is intended only for the individual or entity to which it is 
> 	addressed and may contain information that is privileged, confidential and 
> 	exempt from disclosure under applicable law or contract. If you are not 
> 	the intended recipient, or the employee or agent responsible for 
> 	delivering the message to the intended recipient, you are hereby notified 
> 	that any dissemination, distribution or copying of this communication is 
> 	strictly prohibited, and we ask that you delete this message and notify us 
> 	by return email. Thank you for your cooperation.
> 	This e-mail contains NetLogic Microsystems, Inc. Confidential information
> 
> 
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End of ibis-users V1 #20
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