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Subject: ibis-users V1 #25
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ibis-users            Friday, June 20 2003            Volume 01 : Number 025




----------------------------------------------------------------------

Date: Wed, 28 May 2003 11:35:44 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] Measurement deratings?

Tim,

IBIS doesn't have to provide this derating construct in order
for you to make an IBIS model with derating.  You measure your
data, import it into your favorite spreadsheet, and massage it.
After that you can make your IBIS model with the massaged data.

Arpad
===============================================================

- -----Original Message-----
From: Timothy Coyle [mailto:timothy.coyle@sun.com]
Sent: Wednesday, May 28, 2003 8:48 AM
To: John Phillippe
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] Measurement deratings?


John Phillippe wrote:
> 
> Hello,
>    I am wondering how people match their IBIS simulations to silicon
> measurements.  I read through the spec, and didn't see anything that
> looked like a derating type construct.  So it is my understanding that
> when someone takes lab measurements of an I/O buffer, those data points
> are directly inserted into the ibis file, replacing the simulated data.
>   Does this sound correct?  Is there another way, to get simulations to
> more closely match measurements?
> 
> --
> John Phillippe
> SPS, 32 Bit Embedded Controller Division, IC Creation
> Motorola      -  512-895-1835
> Austin, TX    -  john.phillippe@motorola.com
> 
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Hi John,
Not sure if you are talking about transmission line simulations or just the
IBIS data itself, but here is my 2 cents. If your IBIS file was created from
SPICE models, the real correlation should be between your SPICE simulations
and real silicon. A good methodology might be to correlate your SPICE models
to silicon, then translate your SPICE models to IBIS, and correlate your
IBIS file to your SPICE model. If your SPICE models do not correlate well to
silicon, you could extract IBIS data from
the bench and insert into your IBIS file. This should make your IBIS file
correlate better to silicon. It will be more difficult to get your min and
max
data from the lab than from simulation. 

Regards,
Tim
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------------------------------

Date: Wed, 28 May 2003 11:59:24 -0700
From: Suhail Zain <suhail@lightspeed.com>
Subject: [IBIS-Users] S2IBIS2 Issue

Hi:

I am trying to use the S2IBIS2 script to generate an LVCMOS2 I/O IBIS 
model. However,
my voltage & temperature ranges are as follows:

VCC : 2.25 Volts
Temp: 125, 110, 85
Corner: SS

In other words, I want a slow corner, low VCC but a temperature sweep. I 
tried the following:

[Voltage Range] = 2.25, 2.25, 2.25 for (typ, min, max)
[Temperature Range] = 110, 125, 85  (typ, min, max)


I also set all the spice deck to SS corner in the max1, min1, & typ1 files.

However, S2IBIS2 upon completion places NA in Power & Ground Clamps.
I looked at the spice results and there are current values in the output 
files.

Does anybody have any ideas on how to get an IBIS model using the
S2IBIS2 script for a temperature sweep? Or any clue as to what I am
doing wrong?


Suhail

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------------------------------

Date: Wed, 28 May 2003 17:59:34 -0700
From: "Peters, Stephen" <stephen.peters@intel.com>
Subject: [IBIS-Users] Agenda, IBIS Open Forum Summit at DAC

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C3257D.91EC0650
Content-Type: text/plain

 
- ------------------------------------------------------------------
AGENDA, IBIS SUMMIT MEETING
June 5, 2003 At DAC
 
Anaheim Marriot Hotel
700 W. Convention Way 
Anaheim, CA
 
Room: Grand Ballroom Salons C & D
      (check signs at site)
 
- ------------------------------------------------------------------
 
8:00 AM     Refreshments & Sign In
 
8:30 AM     Introductions
            - Welcome to Summit
            - Introductions
            - Opens for New Issues, Discussion Topics
 
8:45 AM     IBIS Chair's Report
            Stephen Peters, Intel Corporation
 
9:00 AM     IBIS Quality Committee Update
            Kim Helliwell, Apple Computer
 
9:30 AM     ICM Status and Update
            Michael Mirmak, Intel Corp.
 
10:00 AM    Break
 

10:15 AM    Election of Officers
            
 
10:30 AM    IBIS 4.1 Status and Update
            Lynne Green, Cadence Design Systems
 
11:00 AM    Behavioral VHDL-AMS I/O buffer model using IBIS
            Arpad Muranyi, Intel Corporation
 
11:45 AM    Lunch - (Hosted by IBIS and Cadence Design Systems)
            Marriot Hotel
 
1:00 PM     IBIS Algorithms Revisited
            Bob Ross and Tom Dagostino, Teraspeed 
 
1:30 PM     Modeling On-die Terminatons
            Arpad Muranyi, Intel Corp.
 
2:00 PM     Open Discussion and Ad Hoc Topics
            All
 
4:45 PM     Concluding Items
            - Next Open Forum Meeting June 27, 2003
 
5:00 PM     End of IBIS Summit Meeting
 
- ------------------------------------------------------------------
 

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<BODY>
<DIV><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" 
size=2>------------------------------------------------------------------</FONT></DIV>
<DIV align=center><FONT face="Courier New" size=2>AGENDA, IBIS SUMMIT 
MEETING<BR>June 5, 2003 At DAC</FONT></DIV>
<DIV align=center><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV align=center><FONT face="Courier New" size=2>Anaheim Marriot Hotel<BR>700 
W. Convention Way&nbsp;<BR>Anaheim, CA</FONT></DIV>
<DIV align=center><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV align=center><FONT face="Courier New" size=2>Room: Grand Ballroom Salons C 
&amp; D<BR><SPAN class=392225700-29052003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
</SPAN>(check signs at site)</FONT></DIV>
<DIV><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" 
size=2>------------------------------------------------------------------</FONT></DIV>
<DIV><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2>8:00 AM&nbsp;&nbsp;&nbsp;&nbsp; 
Refreshments &amp; Sign In</FONT></DIV>
<DIV><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2>8:30 AM&nbsp;&nbsp;&nbsp;&nbsp; 
Introductions<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
- - Welcome to 
Summit<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - 
Introductions<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
- - Opens for New Issues, Discussion Topics</FONT></DIV>
<DIV><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2>8:45 AM&nbsp;&nbsp;&nbsp;&nbsp; IBIS 
Chair's Report</FONT></DIV>
<DIV><FONT><FONT face="Courier New"><FONT size=2><SPAN 
class=392225700-29052003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
</SPAN>Stephen Peters, Intel Corporation</FONT></FONT></FONT></DIV>
<DIV><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2>9:00 AM&nbsp;&nbsp;&nbsp;&nbsp; IBIS 
Quality Committee 
Update<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Kim 
Helliwell, Apple Computer</FONT></DIV>
<DIV><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2>9:30 AM&nbsp;&nbsp;&nbsp;&nbsp; ICM Status 
and Update<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
Michael Mirmak, Intel Corp.</FONT></DIV>
<DIV><FONT face="Courier New" size=2></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2>10:00 AM&nbsp;&nbsp;&nbsp; 
Break</FONT></DIV>
<DIV><FONT face="Courier New" size=2></FONT>&nbsp;</DIV><FONT size=2>
<DIV><FONT face=Arial></FONT><FONT face=Arial></FONT><FONT 
face=Arial></FONT><FONT face=Arial></FONT><BR><FONT face="Courier New">10:15 
AM&nbsp;&nbsp;&nbsp; Election of 
Officers<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">10:30 AM&nbsp;&nbsp;&nbsp; IBIS 4.1 Status and 
Update<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
Lynne Green, Cadence Design Systems</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">11:00 AM&nbsp;&nbsp;&nbsp; Behavioral VHDL-AMS I/O 
buffer model using 
IBIS<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Arpad 
Muranyi, Intel Corporation</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">11:45 AM&nbsp;&nbsp;&nbsp; Lunch - (Hosted by IBIS 
and Cadence Design 
Systems)<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
Marriot Hotel</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">1:00 PM&nbsp;&nbsp;&nbsp;&nbsp; IBIS Algorithms 
Revisited<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
Bob Ross and Tom Dagostino, Teraspeed </FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">1:30 PM&nbsp;&nbsp;&nbsp;&nbsp; Modeling On-die 
Terminatons<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
Arpad Muranyi, Intel Corp.</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">2:00 PM&nbsp;&nbsp;&nbsp;&nbsp; Open Discussion 
and Ad Hoc 
Topics<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
All</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">4:45 PM&nbsp;&nbsp;&nbsp;&nbsp; Concluding 
Items<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - 
Next Open Forum Meeting June 27, 2003</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">5:00 PM&nbsp;&nbsp;&nbsp;&nbsp; End of IBIS Summit 
Meeting</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT 
face="Courier New">------------------------------------------------------------------</FONT></DIV>
<DIV><FONT face=Arial></FONT></FONT>&nbsp;</DIV></BODY></HTML>

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------------------------------

Date: Thu, 29 May 2003 17:13:50 -0700
From: "Duane Mattheisen" <duane.mattheisen@onsemi.com>
Subject: Re: [IBIS-Users] Measurement deratings?

Hello All
    All of my AC data tables are measured.  But if I simulate an output
of an IBIS model with a  4pF load I get a jittery edge.  Even after
putting more points in the data (20 to 50 points in the edge).  I've
tried smoothing the wave form and taking out any over/under shoot but
the simulations still have a jittery edge.  If I take out the AC data
table and leave in the DV/DT information the wave forms look fine.  Is
there a fix  to my problem?  I work with CMOS logic devices.

                               Thanks Duane M
"Muranyi, Arpad" wrote:
> 
> Tim,
> 
> IBIS doesn't have to provide this derating construct in order
> for you to make an IBIS model with derating.  You measure your
> data, import it into your favorite spreadsheet, and massage it.
> After that you can make your IBIS model with the massaged data.
> 
> Arpad
> ===============================================================
> 
> -----Original Message-----
> From: Timothy Coyle [mailto:timothy.coyle@sun.com]
> Sent: Wednesday, May 28, 2003 8:48 AM
> To: John Phillippe
> Cc: ibis-users@eda.org
> Subject: Re: [IBIS-Users] Measurement deratings?
> 
> John Phillippe wrote:
> >
> > Hello,
> >    I am wondering how people match their IBIS simulations to silicon
> > measurements.  I read through the spec, and didn't see anything that
> > looked like a derating type construct.  So it is my understanding that
> > when someone takes lab measurements of an I/O buffer, those data points
> > are directly inserted into the ibis file, replacing the simulated data.
> >   Does this sound correct?  Is there another way, to get simulations to
> > more closely match measurements?
> >
> > --
> > John Phillippe
> > SPS, 32 Bit Embedded Controller Division, IC Creation
> > Motorola      -  512-895-1835
> > Austin, TX    -  john.phillippe@motorola.com
> >
> > |------------------------------------------------------------------
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> > |
> > |IBIS reflector archives exist under:
> > |
> > |  http://www.eda.org/pub/ibis/email_archive/  Recent
> > |  http://www.eda.org/pub/ibis/users_archive/  Recent
> > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
> 
> Hi John,
> Not sure if you are talking about transmission line simulations or just the
> IBIS data itself, but here is my 2 cents. If your IBIS file was created from
> SPICE models, the real correlation should be between your SPICE simulations
> and real silicon. A good methodology might be to correlate your SPICE models
> to silicon, then translate your SPICE models to IBIS, and correlate your
> IBIS file to your SPICE model. If your SPICE models do not correlate well to
> silicon, you could extract IBIS data from
> the bench and insert into your IBIS file. This should make your IBIS file
> correlate better to silicon. It will be more difficult to get your min and
> max
> data from the lab than from simulation.
> 
> Regards,
> Tim
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------------------------------

Date: Thu, 29 May 2003 18:45:04 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] Measurement deratings?

Duane,

It is not clear to me whether it is your measured data that is jittery,
or the simulation results (with clean data in the IBIS file).  If it is
the former, you need to find ways to filter it before you put it into
the
IBIS model.  If it is the latter, this could be a simulation tool issue.
Which is it?  Which tool are you using?

Arpad
========================================================================
=

- -----Original Message-----
From: Duane Mattheisen [mailto:duane.mattheisen@onsemi.com] 
Sent: Thursday, May 29, 2003 5:14 PM
To: Muranyi, Arpad
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] Measurement deratings?


Hello All
    All of my AC data tables are measured.  But if I simulate an output
of an IBIS model with a  4pF load I get a jittery edge.  Even after
putting more points in the data (20 to 50 points in the edge).  I've
tried smoothing the wave form and taking out any over/under shoot but
the simulations still have a jittery edge.  If I take out the AC data
table and leave in the DV/DT information the wave forms look fine.  Is
there a fix  to my problem?  I work with CMOS logic devices.

                               Thanks Duane M
"Muranyi, Arpad" wrote:
> 
> Tim,
> 
> IBIS doesn't have to provide this derating construct in order for you 
> to make an IBIS model with derating.  You measure your data, import it

> into your favorite spreadsheet, and massage it. After that you can 
> make your IBIS model with the massaged data.
> 
> Arpad ===============================================================
> 
> -----Original Message-----
> From: Timothy Coyle [mailto:timothy.coyle@sun.com]
> Sent: Wednesday, May 28, 2003 8:48 AM
> To: John Phillippe
> Cc: ibis-users@eda.org
> Subject: Re: [IBIS-Users] Measurement deratings?
> 
> John Phillippe wrote:
> >
> > Hello,
> >    I am wondering how people match their IBIS simulations to silicon

> > measurements.  I read through the spec, and didn't see anything that

> > looked like a derating type construct.  So it is my understanding 
> > that when someone takes lab measurements of an I/O buffer, those 
> > data points are directly inserted into the ibis file, replacing the
simulated data.
> >   Does this sound correct?  Is there another way, to get simulations

> > to more closely match measurements?
> >
> > --
> > John Phillippe
> > SPS, 32 Bit Embedded Controller Division, IC Creation
> > Motorola      -  512-895-1835
> > Austin, TX    -  john.phillippe@motorola.com
> >
> > |------------------------------------------------------------------
> > |For help or to subscribe/unsubscribe, email majordomo@eda.org with 
> > |just the appropriate command message(s) in the body:
> > |
> > |  help
> > |  subscribe   ibis       <optional e-mail address, if different>
> > |  subscribe   ibis-users <optional e-mail address, if different>
> > |  unsubscribe ibis       <optional e-mail address, if different>
> > |  unsubscribe ibis-users <optional e-mail address, if different>
> > |
> > |or email a written request to ibis-request@eda.org.
> > |
> > |IBIS reflector archives exist under:
> > |
> > |  http://www.eda.org/pub/ibis/email_archive/  Recent  
> > | http://www.eda.org/pub/ibis/users_archive/  Recent
> > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
> 
> Hi John,
> Not sure if you are talking about transmission line simulations or 
> just the IBIS data itself, but here is my 2 cents. If your IBIS file 
> was created from SPICE models, the real correlation should be between 
> your SPICE simulations and real silicon. A good methodology might be 
> to correlate your SPICE models to silicon, then translate your SPICE 
> models to IBIS, and correlate your IBIS file to your SPICE model. If 
> your SPICE models do not correlate well to silicon, you could extract 
> IBIS data from the bench and insert into your IBIS file. This should 
> make your IBIS file correlate better to silicon. It will be more 
> difficult to get your min and max data from the lab than from 
> simulation.
> 
> Regards,
> Tim
> |------------------------------------------------------------------
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------------------------------

Date: Fri, 30 May 2003 10:50:38 -0700
From: "Duane Mattheisen" <duane.mattheisen@onsemi.com>
Subject: Re: [IBIS-Users] Measurement deratings?

Muranyi
   The IBIS file is clean, no jitter but, when I use Hyperlink 6.1
simulation software with a 4pF load to simulate the clean IBIS files I
get a jittery simulation.  If I put a bigger load on the simulation the
jitter goes away.
 
               Thanks Duane M

"Muranyi, Arpad" wrote:
> 
> Duane,
> 
> It is not clear to me whether it is your measured data that is jittery,
> or the simulation results (with clean data in the IBIS file).  If it is
> the former, you need to find ways to filter it before you put it into
> the
> IBIS model.  If it is the latter, this could be a simulation tool issue.
> Which is it?  Which tool are you using?
> 
> Arpad
> ========================================================================
> =
> 
> -----Original Message-----
> From: Duane Mattheisen [mailto:duane.mattheisen@onsemi.com]
> Sent: Thursday, May 29, 2003 5:14 PM
> To: Muranyi, Arpad
> Cc: ibis-users@eda.org
> Subject: Re: [IBIS-Users] Measurement deratings?
> 
> Hello All
>     All of my AC data tables are measured.  But if I simulate an output
> of an IBIS model with a  4pF load I get a jittery edge.  Even after
> putting more points in the data (20 to 50 points in the edge).  I've
> tried smoothing the wave form and taking out any over/under shoot but
> the simulations still have a jittery edge.  If I take out the AC data
> table and leave in the DV/DT information the wave forms look fine.  Is
> there a fix  to my problem?  I work with CMOS logic devices.
> 
>                                Thanks Duane M
> "Muranyi, Arpad" wrote:
> >
> > Tim,
> >
> > IBIS doesn't have to provide this derating construct in order for you
> > to make an IBIS model with derating.  You measure your data, import it
> 
> > into your favorite spreadsheet, and massage it. After that you can
> > make your IBIS model with the massaged data.
> >
> > Arpad ===============================================================
> >
> > -----Original Message-----
> > From: Timothy Coyle [mailto:timothy.coyle@sun.com]
> > Sent: Wednesday, May 28, 2003 8:48 AM
> > To: John Phillippe
> > Cc: ibis-users@eda.org
> > Subject: Re: [IBIS-Users] Measurement deratings?
> >
> > John Phillippe wrote:
> > >
> > > Hello,
> > >    I am wondering how people match their IBIS simulations to silicon
> 
> > > measurements.  I read through the spec, and didn't see anything that
> 
> > > looked like a derating type construct.  So it is my understanding
> > > that when someone takes lab measurements of an I/O buffer, those
> > > data points are directly inserted into the ibis file, replacing the
> simulated data.
> > >   Does this sound correct?  Is there another way, to get simulations
> 
> > > to more closely match measurements?
> > >
> > > --
> > > John Phillippe
> > > SPS, 32 Bit Embedded Controller Division, IC Creation
> > > Motorola      -  512-895-1835
> > > Austin, TX    -  john.phillippe@motorola.com
> > >
> > > |------------------------------------------------------------------
> > > |For help or to subscribe/unsubscribe, email majordomo@eda.org with
> > > |just the appropriate command message(s) in the body:
> > > |
> > > |  help
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> > > |  unsubscribe ibis       <optional e-mail address, if different>
> > > |  unsubscribe ibis-users <optional e-mail address, if different>
> > > |
> > > |or email a written request to ibis-request@eda.org.
> > > |
> > > |IBIS reflector archives exist under:
> > > |
> > > |  http://www.eda.org/pub/ibis/email_archive/  Recent
> > > | http://www.eda.org/pub/ibis/users_archive/  Recent
> > > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
> >
> > Hi John,
> > Not sure if you are talking about transmission line simulations or
> > just the IBIS data itself, but here is my 2 cents. If your IBIS file
> > was created from SPICE models, the real correlation should be between
> > your SPICE simulations and real silicon. A good methodology might be
> > to correlate your SPICE models to silicon, then translate your SPICE
> > models to IBIS, and correlate your IBIS file to your SPICE model. If
> > your SPICE models do not correlate well to silicon, you could extract
> > IBIS data from the bench and insert into your IBIS file. This should
> > make your IBIS file correlate better to silicon. It will be more
> > difficult to get your min and max data from the lab than from
> > simulation.
> >
> > Regards,
> > Tim
> > |------------------------------------------------------------------
> > |For help or to subscribe/unsubscribe, email majordomo@eda.org with
> > |just the appropriate command message(s) in the body:
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------------------------------

Date: Fri, 30 May 2003 12:27:22 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] Measurement deratings?

Duane,

I would suggest that you talk to the Mentor support guys.
It seems that this is done by the simulator, and I am not
familiar with its intricacies.

Arpad
=========================================================

- -----Original Message-----
From: Duane Mattheisen [mailto:duane.mattheisen@onsemi.com]
Sent: Friday, May 30, 2003 10:51 AM
To: Muranyi, Arpad
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] Measurement deratings?


Muranyi
   The IBIS file is clean, no jitter but, when I use Hyperlink 6.1
simulation software with a 4pF load to simulate the clean IBIS files I
get a jittery simulation.  If I put a bigger load on the simulation the
jitter goes away.
 
               Thanks Duane M

"Muranyi, Arpad" wrote:
> 
> Duane,
> 
> It is not clear to me whether it is your measured data that is jittery,
> or the simulation results (with clean data in the IBIS file).  If it is
> the former, you need to find ways to filter it before you put it into
> the
> IBIS model.  If it is the latter, this could be a simulation tool issue.
> Which is it?  Which tool are you using?
> 
> Arpad
> ========================================================================
> =
> 
> -----Original Message-----
> From: Duane Mattheisen [mailto:duane.mattheisen@onsemi.com]
> Sent: Thursday, May 29, 2003 5:14 PM
> To: Muranyi, Arpad
> Cc: ibis-users@eda.org
> Subject: Re: [IBIS-Users] Measurement deratings?
> 
> Hello All
>     All of my AC data tables are measured.  But if I simulate an output
> of an IBIS model with a  4pF load I get a jittery edge.  Even after
> putting more points in the data (20 to 50 points in the edge).  I've
> tried smoothing the wave form and taking out any over/under shoot but
> the simulations still have a jittery edge.  If I take out the AC data
> table and leave in the DV/DT information the wave forms look fine.  Is
> there a fix  to my problem?  I work with CMOS logic devices.
> 
>                                Thanks Duane M
> "Muranyi, Arpad" wrote:
> >
> > Tim,
> >
> > IBIS doesn't have to provide this derating construct in order for you
> > to make an IBIS model with derating.  You measure your data, import it
> 
> > into your favorite spreadsheet, and massage it. After that you can
> > make your IBIS model with the massaged data.
> >
> > Arpad ===============================================================
> >
> > -----Original Message-----
> > From: Timothy Coyle [mailto:timothy.coyle@sun.com]
> > Sent: Wednesday, May 28, 2003 8:48 AM
> > To: John Phillippe
> > Cc: ibis-users@eda.org
> > Subject: Re: [IBIS-Users] Measurement deratings?
> >
> > John Phillippe wrote:
> > >
> > > Hello,
> > >    I am wondering how people match their IBIS simulations to silicon
> 
> > > measurements.  I read through the spec, and didn't see anything that
> 
> > > looked like a derating type construct.  So it is my understanding
> > > that when someone takes lab measurements of an I/O buffer, those
> > > data points are directly inserted into the ibis file, replacing the
> simulated data.
> > >   Does this sound correct?  Is there another way, to get simulations
> 
> > > to more closely match measurements?
> > >
> > > --
> > > John Phillippe
> > > SPS, 32 Bit Embedded Controller Division, IC Creation
> > > Motorola      -  512-895-1835
> > > Austin, TX    -  john.phillippe@motorola.com
> > >
> > > |------------------------------------------------------------------
> > > |For help or to subscribe/unsubscribe, email majordomo@eda.org with
> > > |just the appropriate command message(s) in the body:
> > > |
> > > |  help
> > > |  subscribe   ibis       <optional e-mail address, if different>
> > > |  subscribe   ibis-users <optional e-mail address, if different>
> > > |  unsubscribe ibis       <optional e-mail address, if different>
> > > |  unsubscribe ibis-users <optional e-mail address, if different>
> > > |
> > > |or email a written request to ibis-request@eda.org.
> > > |
> > > |IBIS reflector archives exist under:
> > > |
> > > |  http://www.eda.org/pub/ibis/email_archive/  Recent
> > > | http://www.eda.org/pub/ibis/users_archive/  Recent
> > > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
> >
> > Hi John,
> > Not sure if you are talking about transmission line simulations or
> > just the IBIS data itself, but here is my 2 cents. If your IBIS file
> > was created from SPICE models, the real correlation should be between
> > your SPICE simulations and real silicon. A good methodology might be
> > to correlate your SPICE models to silicon, then translate your SPICE
> > models to IBIS, and correlate your IBIS file to your SPICE model. If
> > your SPICE models do not correlate well to silicon, you could extract
> > IBIS data from the bench and insert into your IBIS file. This should
> > make your IBIS file correlate better to silicon. It will be more
> > difficult to get your min and max data from the lab than from
> > simulation.
> >
> > Regards,
> > Tim
> > |------------------------------------------------------------------
> > |For help or to subscribe/unsubscribe, email majordomo@eda.org with
> > |just the appropriate command message(s) in the body:
> > |
> > |  help
> > |  subscribe   ibis       <optional e-mail address, if different>
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> > |
> > |or email a written request to ibis-request@eda.org.
> > |
> > |IBIS reflector archives exist under:
> > |
> > |  http://www.eda.org/pub/ibis/email_archive/  Recent
> > |  http://www.eda.org/pub/ibis/users_archive/  Recent
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> > |
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> > |
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------------------------------

Date: Fri, 30 May 2003 13:52:59 -0700
From: "Angulo, John" <john_angulo@mentorg.com>
Subject: RE: [IBIS-Users] Measurement deratings?

Duane,

You're using an older version of Hyperlynx prior to some significant IBIS improvements.  Please contact me off-line, and I'll work with you to make sure this is resolved quickly.

Thanks,

John Angulo
Hyperlynx Products
Mentor Graphics Corp.
john_angulo@mentor.com
425-869-2320



- -----Original Message-----
From: Duane Mattheisen [mailto:duane.mattheisen@onsemi.com]
Sent: Friday, May 30, 2003 10:51 AM
To: Muranyi, Arpad
Cc: ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Measurement deratings?


Muranyi
   The IBIS file is clean, no jitter but, when I use Hyperlink 6.1
simulation software with a 4pF load to simulate the clean IBIS files I
get a jittery simulation.  If I put a bigger load on the simulation the
jitter goes away.
 
               Thanks Duane M

"Muranyi, Arpad" wrote:
> 
> Duane,
> 
> It is not clear to me whether it is your measured data that is jittery,
> or the simulation results (with clean data in the IBIS file).  If it is
> the former, you need to find ways to filter it before you put it into
> the
> IBIS model.  If it is the latter, this could be a simulation tool issue.
> Which is it?  Which tool are you using?
> 
> Arpad
> ========================================================================
> =
> 
> -----Original Message-----
> From: Duane Mattheisen [mailto:duane.mattheisen@onsemi.com]
> Sent: Thursday, May 29, 2003 5:14 PM
> To: Muranyi, Arpad
> Cc: ibis-users@eda.org
> Subject: Re: [IBIS-Users] Measurement deratings?
> 
> Hello All
>     All of my AC data tables are measured.  But if I simulate an output
> of an IBIS model with a  4pF load I get a jittery edge.  Even after
> putting more points in the data (20 to 50 points in the edge).  I've
> tried smoothing the wave form and taking out any over/under shoot but
> the simulations still have a jittery edge.  If I take out the AC data
> table and leave in the DV/DT information the wave forms look fine.  Is
> there a fix  to my problem?  I work with CMOS logic devices.
> 
>                                Thanks Duane M
> "Muranyi, Arpad" wrote:
> >
> > Tim,
> >
> > IBIS doesn't have to provide this derating construct in order for you
> > to make an IBIS model with derating.  You measure your data, import it
> 
> > into your favorite spreadsheet, and massage it. After that you can
> > make your IBIS model with the massaged data.
> >
> > Arpad ===============================================================
> >
> > -----Original Message-----
> > From: Timothy Coyle [mailto:timothy.coyle@sun.com]
> > Sent: Wednesday, May 28, 2003 8:48 AM
> > To: John Phillippe
> > Cc: ibis-users@eda.org
> > Subject: Re: [IBIS-Users] Measurement deratings?
> >
> > John Phillippe wrote:
> > >
> > > Hello,
> > >    I am wondering how people match their IBIS simulations to silicon
> 
> > > measurements.  I read through the spec, and didn't see anything that
> 
> > > looked like a derating type construct.  So it is my understanding
> > > that when someone takes lab measurements of an I/O buffer, those
> > > data points are directly inserted into the ibis file, replacing the
> simulated data.
> > >   Does this sound correct?  Is there another way, to get simulations
> 
> > > to more closely match measurements?
> > >
> > > --
> > > John Phillippe
> > > SPS, 32 Bit Embedded Controller Division, IC Creation
> > > Motorola      -  512-895-1835
> > > Austin, TX    -  john.phillippe@motorola.com
> > >
> > > |------------------------------------------------------------------
> > > |For help or to subscribe/unsubscribe, email majordomo@eda.org with
> > > |just the appropriate command message(s) in the body:
> > > |
> > > |  help
> > > |  subscribe   ibis       <optional e-mail address, if different>
> > > |  subscribe   ibis-users <optional e-mail address, if different>
> > > |  unsubscribe ibis       <optional e-mail address, if different>
> > > |  unsubscribe ibis-users <optional e-mail address, if different>
> > > |
> > > |or email a written request to ibis-request@eda.org.
> > > |
> > > |IBIS reflector archives exist under:
> > > |
> > > |  http://www.eda.org/pub/ibis/email_archive/  Recent
> > > | http://www.eda.org/pub/ibis/users_archive/  Recent
> > > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
> >
> > Hi John,
> > Not sure if you are talking about transmission line simulations or
> > just the IBIS data itself, but here is my 2 cents. If your IBIS file
> > was created from SPICE models, the real correlation should be between
> > your SPICE simulations and real silicon. A good methodology might be
> > to correlate your SPICE models to silicon, then translate your SPICE
> > models to IBIS, and correlate your IBIS file to your SPICE model. If
> > your SPICE models do not correlate well to silicon, you could extract
> > IBIS data from the bench and insert into your IBIS file. This should
> > make your IBIS file correlate better to silicon. It will be more
> > difficult to get your min and max data from the lab than from
> > simulation.
> >
> > Regards,
> > Tim
> > |------------------------------------------------------------------
> > |For help or to subscribe/unsubscribe, email majordomo@eda.org with
> > |just the appropriate command message(s) in the body:
> > |
> > |  help
> > |  subscribe   ibis       <optional e-mail address, if different>
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> > |  unsubscribe ibis       <optional e-mail address, if different>
> > |  unsubscribe ibis-users <optional e-mail address, if different>
> > |
> > |or email a written request to ibis-request@eda.org.
> > |
> > |IBIS reflector archives exist under:
> > |
> > |  http://www.eda.org/pub/ibis/email_archive/  Recent
> > |  http://www.eda.org/pub/ibis/users_archive/  Recent
> > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
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> > |
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> > |
> > |IBIS reflector archives exist under:
> > |
> > |  http://www.eda.org/pub/ibis/email_archive/  Recent
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------------------------------

Date: Fri, 30 May 2003 19:41:31 -0400
From: "Lynne Green" <lgreen@cadence.com>
Subject: [IBIS-Users] Third Call for Papers for IBIS Summit at DesignCon East

- -----------------------------------------------------------------------
               IBIS SUMMIT at DESIGNCON EAST
                     THIRD CALL FOR
               PARTICIPATION & PRESENTATIONS
- -----------------------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

              I B I S   S U M M I T   M E E T I N G

Time/Date:  Monday, June 23, 2003,  8:00 AM to 5:00 PM

Location:   Best Western Royal Plaza Hotel and Trade Center
            Marlboro, Massachusetts

            A phone bridge will be available.  The number
            will be announced on the Agenda.

Content:    Presentations and Discussions

Purpose:    Solicit and Exchange IBIS Model Related Information
            and Ideas.

Sponsors:   DesignCon East, IBIS Open Forum, and
            Signal Integrity Software, Inc. (SiSoft)

            If your company would be interested in being a sponsor,
            please contact Lynne Green <lgreen@cadence.com>.
            Sponsorships are needed for the teleconference phone
            line, lunch, and coffee breaks.

DesignCon East: June 23-25, 2003
            Best Western Royal Plaza Hotel and Trade Center
            Marlborough Massachusetts

            DesignCon offers a 30% discount for IBIS members who
            register for the technical program at
            http://www.iec.org/events/2003/designcon_east/ibis.html.

            See <http://www.iec.org/events/2003/designcon_east/>
            for more information.


BACKGROUND

DesignCon is the premier annual Silicon Valley event for the electronic
design automation (EDA) and semiconductor industry.  Topics of current
interest to the EIA IBIS Open Forum are addressed at DesignCon.

This meeting will be conducted as a formal IBIS Summit Meeting.
Presentations are expected to be available and archived in an
electronic format, and minutes of the meeting will be issued.
Any pending formal decisions (votes) will be announced at least
two weeks prior to the meeting.


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development,
and digital circuit design are invited to participate to the
Summit meeting. If you plan to participate, please register with the
information below:

   Name:
   E-mail address:
   Company:
   Telephone:

Send to:

   Terry Roulic <troulic@sisoft.com>
    


CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS
experiences or issues.

Format of Presentation:  LCD Projection with Windows laptop.
Time:        15-30 Minutes
Electronic Archival: We request electronic versions so that the
             presentations can be archived and also made
             available to non-attendees.  Formats used in
             the past have been text, Power Point, Word,
             Postscript, and Acrobat.  Electronic
             presentations should be made available by
             June 18, 2003 for uploading and copying to
             the presentation laptop.

If you plan a presentation, please supply

   Title:
   Presenter:
   E-mail address:
   Company:
   Telephone:

   Estimate Time:


Send this to:

  Lynne Green (lgreen@cadence.com)


AGENDA

The agenda includes presentations, discussions, breaks, and a
luncheon (which will be provided).  This will be developed as
presentation proposals are received.

The following individuals have signed up to present at the
summit (presentation titles are tentative).
* IBIS Status Update, Stephen Peters (Intel Corp)
* Behavioral VHDL-AMS I/O buffer model using IBIS, Arpad
Muranyi (Intel Corp)  
* Quality Committee Update, Barry Katz (SiSoft)
* Observations on Problems Encountered, Atsuji Ito (Panasonic) 
* ICM Status and Update, Michael Mirmak (Intel Corp.)
* Modeling On-die Terminations, Arpad Muranyi (Intel Corp.)



LIST OF NEARBY HOTELS

Please see
<http://www.iec.org/events/2003/designcon_east/attendee/hotel.html>
for travel directions, hotels and other information.
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------------------------------

Date: Mon, 2 Jun 2003 00:53:11 -0700 (PDT)
From: yuan longhui <yuanlonghui@yahoo.com>
Subject: [IBIS-Users] Who can provide the IBIS file of LXT905(LEVEL ONE)?

Or please tell me how to get the file?

__________________________________
Do you Yahoo!?
Yahoo! Calendar - Free online calendar with sync to Outlook(TM).
http://calendar.yahoo.com
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------------------------------

Date: Mon, 2 Jun 2003 09:49:47 -0600
From: rrwolff@micron.com
Subject: [IBIS-Users] [IBIS] Open forum minutes (05/30/03)

DATE: 06/2/03

SUBJECT: May 30, 2003 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2003 PARTICIPANTS LIST:
Ansoft Corporation             (Eric Bracken)
Apple Computer                 Kim Helliwell
Applied Simulation Technology  Fred Balistreri
Cadence Design                 Lynne Green*
Cisco Systems                  Syed Huq, Val Mandruson, Hung Pham 
Cypress Semiconductor          (Rajesh Manapat)
Fairchild Semiconductor        (Graham Connolly)
Hitachi ULSI Systems           Kazuyoshi Shoji
Huawei Technologies            (Jiang Xiang Zhong)
IBM                            (Pravin Patel)
Intel Corporation              Stephen Peters*, Michael Mirmak*,
                               Arpad Muranyi*, Eric Magnusson
LSI Logic                      Frank Gasparik
Matsushita (Panasonic)         Atsuji Ito
Mentor Graphics                [Bob Ross], Ian Dodd, Guy de Burgh*,
                               John Angulo*, Mike Donnelly, Weston Beal 
Micron Technology              Randy Wolff*
Mitsubishi                     (Pat Hefferan)
Molex Incorporated             Gus Panella
Motorola                       (Rick Kingen)
National Semiconductor         [Milt Schwartz], [Tim Coyle]
NEC Electric Corporation       (Itsuki Yamada)
North East Systems Associates  Edward Sayre 
Philips Semiconductor          (D.C. Sessions), Stephanie Goedecke
Quantic EMC                    (Mike Ventham)
Siemens (& Automotive) AG      Eckhard Lenski, Michael Kindij, 
                               Burkhard Muller, Katja Koller, 
                               Andre Goerisch, Manfred Maurer, 
                               Bernard Unger, Amir Motamedi, 
                               Hartmut Ibowski, Gerald Bannert
Signal Integrity Software      Bob Haller*, Barry Katz, Doug Burns
Sigrity                        [Raj Raghuram]
SiQual                         (Rob Hinz)
Texas Instruments              Thomas Fisher
Teraspeed                      Scott McMorrow, Tom Dagostino,
                               Kevin Simpson, Bob Ross*
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Via Technologies               (Weber Chuang)
Zuken (& Incases)              Michael Schaeder, Ralf Bruning,

OTHER PARTICIPANTS IN 2003:
Agilent Technologies           Herbert Lage
Brocade                        Frank Yuan, Yongrue Yu
Conexant                       Gary Felker
EADS CCR                       Alix de la Villeguerin
EFM                            Ekkehard Miersch
EMC Corporation                Brian Arsenault
Fraunhofer IZM                 Ege Engin
Fujitsu                        Tadashi Arai
GEIA                           (Chris Denham)
Independent                    Kelly Green, Luca Giacotto
Infineon Tech AG               Christian Sporrer
Marvell Semiconductor          Itzik Peleg
NetLogic Microsystems          Eric Hsu
Plexus                         Joseph Socha
Politechnico de Torino         Igor Stievano
Qlogic                         Larry Barnes*
Sintecs BV                     Hans Klos, Bob te Nijenhuis
Sun Microsystems               Tim Coyle*
Xilinx                         Susan Wu


In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses. 
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are 
as follows:

  Date                Bridge Number    Reservation #    Passcode
  June 27, 2003       (916) 356-2663        1           1321085

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas 
out 7 days before each Open Forum, and meeting minutes out within 7 days 
after.  When you call into the meeting, ask for the IBIS Open Forum hosted 
by Stephen Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
No new introductions.


CALL FOR PATENTS
Stephen Peters called for any patents or pending patents related to the 
IBIS Version 4.0 Standard. No companies declared a patent.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Stephen Peters reported that, based on EIA confirmation of payment, the
current paid membership stands at 20.  In addition, the EIA is awaiting
confirmation from one additional company and Stephen is expecting three
more companies to join.  This total is much better than the 16 paid members 
reported previously, but still down from the 30 members at the end of last 
year. Stephen reminded the group that if a company has not paid its dues by 
mid-June, we would begin the process of removing their name from the voting 
member list on the minutes.


REVIEW OF MINUTES AND AR'S
The May 9, 2003 minutes were approved without changes.

ARs will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
Bob Ross reported that his presentation at the SPI 2003 IEEE Workshop on 
Signal Processing on Interconnects was a success. Bob enlightened 
his audience on the accuracy and usefulness of IBIS models.  A copy
of his presentation "IBIS Past and Future" is available at the following
URL:

  http://www.spi.uni-hannover.de/


PRESS AND WEB PAGE UPDATES
Stephen Peters reported that Syed Huq is making ongoing updates to the IBIS
roster and upcoming events link. 


NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross reported that Renesas Technology is offering some IBIS models that 
were formerly offered by Mitsubishi and Hitachi. These models are available
at

  http://www.renesas.com/eng/


OPENS FOR NEW ISSUES
Bob Ross asked to discuss spice2ibis3.


INTERNATIONAL/EXTERNAL PROGRESS
- - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) - No report.
- - JEDEC Activity Report. Nothing to report.


DAC2003 MEETING PLANNING
Stephen Peters reported that planning continues for the June 5, 2003 IBIS 
summit meeting which will be held in conjunction with DAC2003 in Anaheim, 
California at the Anaheim Marriot hotel in Grand Ballroom Salons C & D.
Cadence Design Systems is co-sponsoring the IBIS summit along with the IBIS 
Open Forum. Stephen noted that attendees should sign up with Guy de Burgh 
immediately if they have not already done so. Currently 15 persons have
indicated that they will attend. John Angulo asked for a final head count
to forward to the hotel and caterers. Finally, Stephen noted that this
summit meeting will not be webcast.  

Stephen reminded the presenters that they should email their electronic 
presentations to Guy De Burgh by the end of the day Monday, June 2, 2003 so
that hard copies can be made. If they are not available by that time, then
the presenter is requested to bring 20 hard copies to the meeting. Lynne
Green requested that presenters also email her a copy of their presentation,
as she will be loading them on her laptop for use at the summit. Stephen
Peters indicated that he will also bring his laptop as a backup. Guy will
supply the LCD projector. 

Stephen noted that the following presentations are planned (titles are 
tentative). 

IBIS Chair's Report, Stephen Peters (Intel Corp.)
IBIS Quality Committee Update, Kim Helliwell, (Apple Computer)
ICM Status and Update, Michael Mirmak (Intel Corp.)
IBIS 4.1 Status and Update, Lynne Green (Cadence Design Systems)
Behavioral VHDL-AMS I/O buffer model using IBIS, Arpad Muranyi (Intel Corp.)  
IBIS Algorithms Revisited, Bob Ross and Tom Dagostino (Teraspeed)
Modeling On-Die Terminations, Arpad Muranyi (Intel Corp.)
 
In addition to presentations and discussion we will also be conducting
the annual election of officers.  The current slate of nominees and their 
positions are:

Chair           Michael Mirmak, Intel Corp.
Vice-Chair      Lynne Green, Cadence
Secretary       Randy Wolff, Micron
Librarian       Roy Leventhal, Leventhal Design and Communications
Webmaster       Syed Huq, Cisco
Postmaster      John Angulo, Mentor

Additional nominations are being accepted for all positions. E-mail nominee
names to Stephen Peters. Nominations will also be accepted at the summit
meeting.


DESIGNCON2003 EAST MEETING PLANNING
Stephen Peters reported that planning for an IBIS summit meeting at 
Designcon2003 East in Marlborough, Massachusetts continues. The summit is 
scheduled for June 23, 2003 in the Royal Plaza Hotel in Marlborough, 
Massachusetts. Sisoft and the IBIS Open Forum are co-sponsoring the 
event. The meeting room is yet to be determined. Stephen noted that we are
also a co-sponsor of DesignCon2003 East. Barry Katz from SiSoft is serving
as the contact for registration and sign-up, so if you are planning on
attending please let Barry know. Stephen mentioned that we have traded the
booth for a telephone line so that the meeting can be audio or web telecast.
It is expected that presentations given at the DAC2003 Summit will also be
given at this meeting.

Bob Haller indicated that Sisoft may be able to supply the LCD projector.
Stephen has the AR to find a sponsor for lunch. 

Stephen asked for a rough head count of who will attend. SiSoft will have
a couple of representatives in attendance, and Tim Coyle indicated that
he plans on attending in person.  Most west coast individuals indicated
that they will phone in for at least a part of the meeting.


IBIS VERSION 4.0 PARSER FUNDING AND STATUS
Stephen Peters reported that he has received word from EIA that a parser
payment has been received from LSI logic. This brings the total companies 
that have paid to seven, with two more pending.

Atul Agarwal has sent the alpha release of the IBIS 4.0 parser to Stephen,
who has forwarded it on to John Angulo, Matthew Flora and Arpad Muranyi
for testing. The alpha release incorporates all BIRDS approved for IBIS
4.0 with the exception of BIRD70 (Golden Waveforms). John noted that
he has run a few test models, but has not yet gone through all the supplied
test cases for bug fixes. Looking through the file, John noted that there
appears to be test cases for BUGS 57, 58, 60, 61, and 63 through 67.  John
will verify the bug fixes then send a note to Michael Mirmak to close the
bugs.

Stephen stated that Atul asked if any numerical checks needed to performed
on the Test Load waveforms analogous to those which are performed on the
[Rising Waveform] and [Falling Waveform] tables.  The consensus is that
because these are composite waveforms and the end points could assume
wide values, the end point checks are not required.
 

IBIS VERSION 4.1 DISCUSSION
Stephen Peters introduced the second discussion of IBIS version 4.1 by
listing the BIRDS that have been approved since IBIS 4.0 was voted on. These
BIRDS are as follows:
  BIRD 75.8 - Multi Lingual Modeling Support
  BIRD 77.2 - Differential subparameter additions 
  BIRD 78.1 - comment line length limit
  BIRD 80.1 - Add External Reference Column to Pin Mapping Keyword
  BIRD 81.1 - Clarify Usage Rules for [Pin] I/O Model Assignment
 
There are also several minor editorial corrections that will be included.
Stephen asked the group if clarification language on summing clamp currents
and allowing extension of the clamp table ranges was important enough to
warrant a BIRD. Lynne Green stated that she feels this is important, and 
after discussion Lynne and Bob Haller agreed to author a BIRD for review
at the next teleconference meeting. 
 
Stephen also asked if it was worth adding language to the [Driver 
Schedule] keyword that made it illegal to use [Driver Schedule] with a
model type of 'Input'. After discussion it was decided to defer this change
until we have had a chance to look at the [Driver Schedule] section as a
whole. 


IBIS QUALITY COMMITTEE
Bob Haller reported on the IBIS Quality Committee meetings held on May 20,
2003. They have completed review of the I-V document, and are now working
on reviewing Mike Labonte's ramp and waveform processing document. Meetings
are scheduled for June 10 and June 17, 2003 to wrap up the documentation
reviews.


IBIS MODEL REVIEW COMMITTEE
Lynne Green reported that they have received and distributed models from 
Intersil and Intel.


NEW ADMINISTRATIVE ISSUES
Larry Barnes indicated that the T11 Fiber Channel committee is starting a 
modeling subgroup in which he is involved. Larry stated that he has been
struggling with the T11 committee about the usefulness and accuracy of
IBIS models, and Larry suggested that it would be helpful if he or someone
from the IBIS Open Forum could present material at the next T11 meeting
regarding IBIS.  Several folks noted that Scott McMorrow and Tim Coyle
(among others) have published presentations demonstrating IBIS accuracy at
Ghz speeds. After further discussion Larry decided to pursue this further
offline with Lynne Green.  Finally, in response to a question from Bob Ross,
Larry indicated that the T10 document Larry was working on previously is
now an ANSI standard. 


IBIS FUTURES AND CONNECTOR WORKING GROUP REPORT
Stephen Peters reported that, after a final review by email, the IBIS
connector working group released the final draft of the Interconnect
Modeling (ICM) specification to the IBIS Open Forum. A copy of the draft
specification is available for review on the IBIS web site at
 
 http://www.eda.org/pub/ibis/connector/

The only remaining item is a minor update to the Touchstone specification. 
At this point the futures committee has no meetings planned. 

IBIS ICM SPECIFICATION REVIEW
Michael Mirmak introduced the ICM specification for review. In brief,
the ICM specification permits model authors to model a wide variety of
interconnect, including connectors and packages. Topologies can be
described via a tree or nodal connection, and connector swathing is 
supported. Coupling can be represented by RLGC matrices or S-parameter
data formatted in Touchstone format. Michael indicated that an in depth
look at the specification will be presented at the upcoming DAC summit,
and in the mean time interested persons may reference the presentation
given at the January 2003 IBIS summit. 

On a related topic Stephen Peters inquired about ICM parser progress. Lynne
Green indicated that the parser is being developed as a two pass parser.
Coding for the first pass is done and the second pass is in development.
Lynne estimates that an alpha release could happen two to three weeks after
the ICM specification is accepted.  However, Kelly Green (the parser
developer) will need models for testing.  Bob Ross indicated that Teraspeed
can provide a couple of test cases.  Stephen will also ask Gus Panella to
provide any test cases he has. 

Bob asked if the currently posted Word and .pdf documents can be modified
to include a table of contents.  Michael Mirmak will look into this.


BIRD74.4 - EMI Parameters
Guy de Burgh opened the discussion on BIRD74.4 by noting the changes from
the previous version. Per Arpad Muranyi's suggestion the [Signal Swing]
keyword has been removed.  Connector related information has also been
removed and will be re-introduced as part of the ICM specification.  The 
syntax of keywords and subparameters has been updated to be consistent 
throughout the BIRD, and Guy asked for another person to review them to 
verify that they follow the standard IBIS rules. Finally, a subparemeter 
that indicates the heatsink condition (grounded or floating) has been added.

Based on comments from Siemens and others Guy believes that all the 
outstanding technical issues have been addressed and that the BIRD is ready
for a formal vote.  Stephen indicated that he would schedule a vote on this
BIRD at the June 27, 2003 teleconference meeting.


IBISCHK3 & BUG TRACKING STATUS
John Angulo reported no progress on prototyping the fix for BUG73, "Extreme
Non-monotonic I-V Tables Cause End Point Test to Fail".  John indicated
that he will be rolling this in with the testing he is doing on the IBIS
4.0 parser. 
 
Stephen Peters stated that we need to eventually decide if we should do a 
final release of IBISCHK3.2 that includes the bug fixes now incorporated 
into IBIS 4.0. In the following discussion it was pointed out that the 
answer depends a lot on Atul Agarwal's availability.  Stephen also noted 
that BUG68 thru BUG77 and BUG79 have yet to be implemented. Stephen will 
contact Atul and ask him if he plans to implement the fixes for these bugs. 


NEW ISSUES:
Bob Ross Noted that he has received an email from North Carolina State 
University (NCSU) stating that they have a beta copy of a new SPICE to IBIS3
program. NCSU would like to limit the distribution of this beta version, but
if you are interested in beta testing contact Lynne Green or Bob Ross.
Bob will ask NCSU if they will consider sending a copy to Syed Huq, as he is
the prime reflector resource for S2IBIS2 assistance.


NEXT MEETINGS:
The next IBIS meeting will be the IBIS Summit on June 5, 2003 at the Design
Automation Conference (DAC) in Anaheim, California.  No audio bridge or 
webcast is planned.

The next teleconference meeting is scheduled for June 27, 2003 from 8:00
AM to 10:00 AM Pacific Daylight Time. A vote on BIRD 74.4 is planned.
============================================================================
                               NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            stephen.peters@intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Lynne Green (425) 788-0412, Fax: (425) 788-4289
            lgreen@cadence.com
            Senior Modeling Engineer, Cadence Design Systems
            20 120th Ave NE, Suite 103, Bellevue, WA 98005-3016

SECRETARY:  Randy Wolff (208) 363-1764, Fax: (208) 368-3475
            rrwolff@micron.com
            Simulation Engineer, Micron Technology, Inc.
            8000 S. Federal Way
            Mail Stop: 711
            Boise, ID 83707-0006
        
LIBRARIAN:  Roy Leventhal (847) 590-9398
            roy.leventhal@ieee.org
            Consultant, Leventhal Design and Communications
            1924 North Burke Drive
            Arlington Heights, Illinois 60004

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
            John_angulo@mentor.com
            Development Engineer, Mentor Graphics
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA 
Manual of Organization and Procedure.

The following e-mail addresses are used:

  majordomo@eda.org
      In the body, for the IBIS Open Forum Reflector:
      subscribe ibis <your e-mail address>

      In the body, for the IBIS Users' Group Reflector:
      subscribe ibis-users <your e-mail address>

      Help and other commands:
      help

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
      bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
      /pub/ibis/bugs/s2iplt/bugsplt.txt respectively.

Information on IBIS technical contents, IBIS participants, and actual IBIS 
models are available on the IBIS Home page found by selecting the Electronic 
Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.

============================================================================
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------------------------------

Date: Wed, 04 Jun 2003 15:26:32 -0700
From: Suhail Zain <suhail@lightspeed.com>
Subject: [IBIS-Users] Differential I/O IBIS Models

Hi:

What is the best way to generate IBIS models fro Differential I/Os? 
 When I use S2IBIS2 to generate the model
(single ended approach), the IBISCHK3 fails. Any suggestions.

Suhail Zain




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------------------------------

Date: Thu, 5 Jun 2003 14:08:46 +0200
From: erik.van.der.ven@philips.com
Subject: [IBIS-Users] monotonic waveforms

This is a multipart message in MIME format.
- --=_alternative 0042E9E5C1256D3C_=
Content-Type: text/plain; charset="us-ascii"

Hello,


Should the rising and falling waveforms be monotonic as well?

When I simulate a differential (PECL) output with internal feedback I see 
that the falling waveform has some undershoot and has some damped 
oscillation behavior.
Is this allowed in a V-T table? If not,  how do I have to deal with it.

I did a simulation with HSPICE2002.2 and Hyperlynx 6.0 and see that both 
simulators react differently and both results are not correct (perhaps 
newer versions are?).

With kind regards,

Ir. Erik van der Ven
Room DB1032
Business Line Networking Infrastructure
Philips Semiconductors BV
Gerstweg 2
6534 AE Nijmegen
The Netherlands
Phone: +31-24-3534334
- --=_alternative 0042E9E5C1256D3C_=
Content-Type: text/html; charset="us-ascii"


<br><font size=2 face="sans-serif">Hello,</font>
<br>
<br>
<br><font size=2 face="sans-serif">Should the rising and falling waveforms be monotonic as well?</font>
<br>
<br><font size=2 face="sans-serif">When I simulate a differential (PECL) output with internal feedback I see that the falling waveform has some undershoot and has some damped oscillation behavior.</font>
<br><font size=2 face="sans-serif">Is this allowed in a V-T table? If not, &nbsp;how do I have to deal with it.</font>
<br>
<br><font size=2 face="sans-serif">I did a simulation with HSPICE2002.2 and Hyperlynx 6.0 and see that both simulators react differently and both results are not correct (perhaps newer versions are?).</font>
<br>
<br><font size=2 face="sans-serif">With kind regards,</font>
<br><font size=2 face="sans-serif"><br>
Ir. Erik van der Ven<br>
Room DB1032<br>
Business Line Networking Infrastructure<br>
Philips Semiconductors BV<br>
Gerstweg 2<br>
6534 AE Nijmegen<br>
The Netherlands<br>
Phone: +31-24-3534334</font>
- --=_alternative 0042E9E5C1256D3C_=--
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------------------------------

Date: Fri, 6 Jun 2003 15:35:07 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] Who can provide the IBIS file of LXT905(LEVEL ONE)?

Yuan,

Sorry for the delayed response.  You should try the normal Intel Sales
representative in your area first.  They are the ones who distribute
IBIS models to customers.  Please contact me directly if you are
running into complications or difficulties.

Thanks,

Arpad Muranyi
Intel Corporation
=======================================================================

- -----Original Message-----
From: yuan longhui [mailto:yuanlonghui@yahoo.com] 
Sent: Monday, June 02, 2003 12:53 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Who can provide the IBIS file of LXT905(LEVEL
ONE)?


Or please tell me how to get the file?

__________________________________
Do you Yahoo!?
Yahoo! Calendar - Free online calendar with sync to Outlook(TM).
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------------------------------

Date: Mon, 9 Jun 2003 12:52:46 -0400
From: "Lynne Green" <lgreen@cadence.com>
Subject: [IBIS-Users] Final Call for Papers, IBIS Summit at DesignCon East 2003

- -----------------------------------------------------------------------
               IBIS SUMMIT at DESIGNCON EAST
                     FINAL CALL FOR
               PARTICIPATION & PRESENTATIONS
- -----------------------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

              I B I S   S U M M I T   M E E T I N G

Time/Date:  Monday, June 23, 2003,  8:00 AM to 5:00 PM

Location:   Westborough Room
            Best Western Royal Plaza Hotel and Trade Center
            Marlboro, Massachusetts

            A phone bridge will be available.  The number
            will be announced on the Agenda.

Content:    Presentations and Discussions

Purpose:    Solicit and Exchange IBIS Model Related Information
            and Ideas.

Sponsors:   DesignCon East, IBIS Open Forum, and
            Signal Integrity Software, Inc. (SiSoft)

            If your company would be interested in being a sponsor,
            please contact Lynne Green <lgreen@cadence.com>.
            Sponsorships are needed for the teleconference phone
            line, lunch, and coffee breaks.

DesignCon East: June 23-25, 2003
            Best Western Royal Plaza Hotel and Trade Center
            Marlborough Massachusetts

            DesignCon offers a 30% discount for IBIS members who
            preregister by June 18th for the technical program at
            http://www.iec.org/events/2003/designcon_east/ibis.html.

            See <http://www.iec.org/events/2003/designcon_east/>
            for more information.


BACKGROUND

DesignCon is the premier annual Silicon Valley event for the electronic
design automation (EDA) and semiconductor industry.  Topics of current
interest to the EIA IBIS Open Forum are addressed at DesignCon.

This meeting will be conducted as a formal IBIS Summit Meeting.
Presentations are expected to be available and archived in an
electronic format, and minutes of the meeting will be issued.
Any pending formal decisions (votes) will be announced at least
two weeks prior to the meeting.


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development,
and digital circuit design are invited to participate to the
Summit meeting. If you plan to participate, please register with the
information below:

   Name:
   E-mail address:
   Company:
   Telephone:

Send to:

   Terry Roulic <troulic@sisoft.com>
    


CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS
experiences or issues.

Format of Presentation:  LCD Projection with Windows laptop.
Time:        15-30 Minutes
Electronic Archival: We request electronic versions so that the
             presentations can be archived and also made
             available to non-attendees.  Formats used in
             the past have been text, Power Point, Word,
             Postscript, and Acrobat.  Electronic
             presentations should be made available by
             June 18, 2003 for uploading and copying to
             the presentation laptop.

If you plan a presentation, please supply

   Title:
   Presenter:
   E-mail address:
   Company:
   Telephone:

   Estimate Time:


Send this to:

  Lynne Green (lgreen@cadence.com)


AGENDA

The agenda includes presentations, discussions, breaks, and a
luncheon (which will be provided).  This will be developed as
presentation proposals are received.

The following individuals have signed up to present at the
summit (presentation titles are tentative).
* IBIS Chair's Report, Stephen Peters, Intel Corp.
* IBIS Quality Committee Update, Barry Katz, SiSoft
* ICM Status and Update, Michael Mirmak, Intel Corp.
* IBIS 4.1 Status and Update, Lynne Green, Cadence Design Systems
* Behavioral VHDL-AMS I/O buffer model using IBIS, Arpad Muranyi,
Intel Corp.
* IBIS Algorithms Revisited, Bob Ross and Tom Dagostino, Teraspeed 
* Modeling On-die Terminations, Arpad Muranyi, Intel Corp.



LIST OF NEARBY HOTELS

Please see
<http://www.iec.org/events/2003/designcon_east/attendee/hotel.html>
for travel directions, hotels and other information.
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------------------------------

Date: Mon, 9 Jun 2003 10:09:44 -0700 (PDT)
From: Ray Anderson <Raymond.Anderson@sun.com>
Subject: [IBIS-Users] Pr-emphasis/De-emphasis modeling in IBIS

A search of the archives showed up only a couple messages related to
modeling pre-emphasis using IBIS (and those were from several years
ago). I've downloaded the Hegazy paper on the subject.

Can anyone comment on the current capabilities of IBIS as releated to
modeling pre and de emphasized drivers (for say backplane or IB applications)

- -Ray Anderson
Staff SI Engineer
Sun Microsystems Inc.

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------------------------------

Date: Mon, 9 Jun 2003 11:22:17 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: [IBIS-Users] RE: [IBIS] Pr-emphasis/De-emphasis modeling in IBIS

Ray,

Try this link:

http://www.eda.org/pub/ibis/summits/jan03/muranyi.pdf

Arpad
======================================================

- -----Original Message-----
From: Ray Anderson [mailto:Raymond.Anderson@sun.com]
Sent: Monday, June 09, 2003 10:10 AM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS] Pr-emphasis/De-emphasis modeling in IBIS



A search of the archives showed up only a couple messages related to
modeling pre-emphasis using IBIS (and those were from several years
ago). I've downloaded the Hegazy paper on the subject.

Can anyone comment on the current capabilities of IBIS as releated to
modeling pre and de emphasized drivers (for say backplane or IB applications)

- -Ray Anderson
Staff SI Engineer
Sun Microsystems Inc.

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------------------------------

Date: Mon, 9 Jun 2003 18:06:02 -0600
From: rrwolff@micron.com
Subject: [IBIS-Users] [IBIS] IBIS Summit minutes (06/05/03)

DATE: 6/9/02

SUBJECT: June 5, 2003 EIA IBIS Summit Meeting Minutes

VOTING MEMBERS AND 2003 PARTICIPANTS LIST:
Ansoft Corporation             (Eric Bracken)
Apple Computer                 Kim Helliwell*
Applied Simulation Technology  Fred Balistreri
Cadence Design                 Lynne Green*
Cisco Systems                  Syed Huq*, Val Mandruson, Hung Pham 
Cypress Semiconductor          (Rajesh Manapat)
Fairchild Semiconductor        (Graham Connolly)
Hitachi ULSI Systems           Kazuyoshi Shoji
Huawei Technologies            (Jiang Xiang Zhong)
IBM                            (Pravin Patel)
Intel Corporation              Stephen Peters*, Michael Mirmak*,
                               Arpad Muranyi*, Eric Magnusson
LSI Logic                      Frank Gasparik
Matsushita (Panasonic)         Atsuji Ito*
Mentor Graphics                [Bob Ross], Ian Dodd, Guy de Burgh*,
                               John Angulo*, Mike Donnelly, Weston Beal 
Micron Technology              Randy Wolff
Mitsubishi                     (Pat Hefferan)
Molex Incorporated             Gus Panella
Motorola                       (Rick Kingen)
National Semiconductor         [Milt Schwartz], [Tim Coyle]
NEC Electric Corporation       (Itsuki Yamada)
North East Systems Associates  Edward Sayre 
Philips Semiconductor          (D.C. Sessions), Stephanie Goedecke
Quantic EMC                    (Mike Ventham)
Siemens (& Automotive) AG      Eckhard Lenski, Michael Kindij, 
                               Burkhard Muller, Katja Koller, 
                               Andre Goerisch, Manfred Maurer, 
                               Bernard Unger, Amir Motamedi, 
                               Hartmut Ibowski, Gerald Bannert
Signal Integrity Software      Bob Haller, Barry Katz, Doug Burns
Sigrity                        [Raj Raghuram]
SiQual                         (Rob Hinz)
Synopsys                       Warren Wong*, Edmund Cheng*
Texas Instruments              Thomas Fisher*
Teraspeed                      Scott McMorrow, Tom Dagostino,*
                               Kevin Simpson, Bob Ross*
Time Domain Analysis Systems   Dima Smolyansky*, Steve Corey*
Via Technologies               (Weber Chuang)
Zuken (& Incases)              Michael Schaeder, Ralf Bruning*

OTHER PARTICIPANTS IN 2003:
Agilent Technologies           Herbert Lage
Brocade                        Frank Yuan, Yongrue Yu
Conexant                       Gary Felker
EADS CCR                       Alix de la Villeguerin
EFM                            Ekkehard Miersch
EMC Corporation                Brian Arsenault
Fraunhofer IZM                 Ege Engin
Fujitsu                        Tadashi Arai
GEIA                           (Chris Denham)
Idaho State University         Al Davis*
Independent                    Kelly Green, Luca Giacotto*
Infineon Tech AG               Christian Sporrer
Marvell Semiconductor          Itzik Peleg
NetLogic Microsystems          Eric Hsu
Plexus                         Joseph Socha
Politechnico de Torino         Igor Stievano
Qlogic                         Larry Barnes
Sintecs BV                     Hans Klos, Bob te Nijenhuis
Sun Microsystems               Tim Coyle
Xilinx                         Susan Wu



In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences
are as follows:

  Date                Bridge Number    Reservation #    Passcode
  June 23, 2003        DesignCon East Summit, teleconference TBA
  June 27, 2003       (916) 356-2663        1           1321085


All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after.  When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES -----------------------------------

INTRODUCTIONS AND MEETING QUORUM
The IBIS Summit Meeting was held in Anaheim, California at the Anaheim
Marriot Hotel in conjunction with the Design Automation Conference
(DAC2003). The summit was co-sponsored by IBIS and Cadence Design Systems.
About 19 people representing 12 organizations attended.

The notes below capture some of the content and discussions.  The meeting
presentations and other documents are uploaded at:

  http://www.eda.org/pub/ibis/summits/jun03a/

Stephen Peters asked everyone in the room to introduce themselves.  The
group was well-attended by semiconductor vendors and model providers,
EDA tool vendors and users of IBIS models.  Stephen thanked Cadence Design
Systems for co-sponsoring the summit as well as Mentor Graphics for making
the hotel room arrangements and supplying the LCD projector.  Finally,
Stephen thanked the presenters and participants for attending.

Stephen asked if there were any new issues or discussion items to put on
the agenda.  Lynne Green asked to discuss arrangements for the upcoming
IBIS summit at DesignCon East.


PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions.  These
notes capture some of the content and discussion.  More details are 
available in the documents uploaded to the location noted above.


IBIS ANNUAL REPORT
Stephen Peters, Intel Corporation
Stephen opened the presentations with a summary of today's meeting,
a look back at the previous year, and a look ahead at the coming years'
challenges.  Stephen noted that IBIS 3.2 is truly an international
standard, as evidenced by European and Japanese interest, and that,
despite the weak economy, the IBIS Open forum membership remained constant
at about 24 paid members.  The organization remains financially healthy.

Significant events this year included the passage of IBIS 4.0, the adoption
of multi-lingual modeling, and the introduction of the Interconnect
Modeling (ICM) specification for review by the forum. The biggest 
challenges for the coming year include enabling the future roadmap by 
passing IBIS 4.1 and adoption of the ICM Specification. In addition, 
Stephen stressed the need for an updated IBIS cookbook and providing 
AMS modeling guidance to the industry.  The IBIS Open Forum must also 
continue to work to improve model quality.  Stephen would also like to
continue to track European EMC/EMI developments and determine the need
for XML based parsers.  Finally, Stephen offered his thanks to the officers
and other members of the organization for their support and help during
the past year.


IBIS QUALITY COMMITTEE UPDATE
Kim Helliwell, Apple Computer
Kim began his presentation by noting that, as cycle times decrease and edge
rates increase, quality models are becoming more important.  On recent
accomplishments, the committee has completed review of seven of the 10
quality document sections. In addition, BUG 71 dealing with non-monotonic
error due to individual I-V table checking has been passed.  Kim noted that
this was the most common warning from the parser, and with the parser now
checking summed tables this warning will now have meaning.

Kim reviewed the IBIS quality levels, noting that for a model to be valid
at a level then it must have passed all previous levels.  Arpad Muranyi 
asked if a level 3 model must have passed both level 2a and 2b. Kim replied
that a level three model must pass both. In follow-up questioning,
Kim clarified that the spice simulation models must be correct.

Regarding future items, Kim noted that there are 3 documents left to review
(VT curves and ramps, model correlation, and possible errors). Lynne Green
will be compiling the sections into the final documentation, and the plan
is to have this effort completed for review in time for the IBIS East summit
meeting in October, 2003.  Finally, Kim mentioned that the committee is
interested in feedback on the document, even on the chapters that have 
not been completed.

For additional information on the quality committee and to be included on
the mailing list send mail to ibis-quality@freelist.org.  The IBIS quality
committee web site is available on the IBIS web page or at

  http://www.sisoft.com/ibis-quality


ICM STATUS AND UPDATE
Michael Mirmak, Intel Corp
Michael stated that the purpose of the IBIS Interconnect Modeling 
Specification (ICM specification) is to establish a human-readable
standard format for exchanging interconnect modeling data.  At a high level,
the specification uses a two part format.  The first part describes the 
model in terms of a 'section', with sections either joined in a tree 
arrangement according to implicit connections or in a nodal arrangement with
explicitly described nodes.  The second part of an ICM file supplies 
the electrical data for each section.  Electrical data is in the form of 
either RLGC matrices or S-parameters.

Michael noted that since September, 2002 over 63 issues have been formally
logged.  Most were editorial changes, but there were also some technical
limitations and clarifications added.  RLGC and S-parameter sections are
not permitted within the same model.  S-parameter data is only to be used 
with the [Nodal Path Description] keyword. 

Michael noted that the draft 1.0 specification was officially introduced at 
the May 30, 2003 meeting and a parser is in development.  Michael asked for
example models from the summit participants.

Some technical advancements have been proposed for future revisions.
One suggestion would permit mixing RLGC and S-parameter data within a 
single model description.  Requests have also been made to include support 
for frequency dependent RLGC matrices.  Enhancements and BUGS will be 
handled by a process similar to the existing BIRD process for the IBIS 
specification.  For the longer term, suggestions have been made that 
explicit links between IBIS and ICM be made in one or both specifications.
At present, tools are implicitly assumed to handle the use of ICM models as 
package data for IBIS models.  A larger issue involves Touchstone(R) 
support for mixed-mode S-parameters. At present, Touchstone(R) is 
understood to support only standard single-ended S11, S12, etc. 
S-parameters.  While the format can be used to distribute mixed-mode data 
(SDD12, SCD22, etc.), the specification includes no guidance for users or 
tools for interpreting the placement of the data points in a standard way.  
Finally, Michael mentioned that to best support and encourage ICM usage, 
a cookbook is needed.

Michael closed his presentation by noting that the quickest way to achieve
an official specification is to provide feedback on the draft and example
models for parser testing.  He thanked the past contributors and present
Connector Subcommittee members for their assistance in producing the ICM 
specification.

Stephen asked the group regarding their interest in mixed-mode S-parameters.
Steve Corey stated that TDA had similar questions regarding Touchstone(R) 
when TDA Systems built their parser software.  Steve saw a need for 
explicitly supporting mixed-mode, but had no immediate suggestion on the 
best way to do so.  Michael mentioned that the driving force behind mixed 
mode is the prevalence of differential signaling technologies, such as USB, 
SATA, LVDS and the upcoming PCI-Express.  Currently, multi-mode (more than 
two ports) descriptions, while potentially useful, have no immediate 
application and are essentially an exercise in completeness.


ELECTION OF OFFICERS FOR 2002-2003:
Stephen Peters opened the floor for nominations for each of the six
officer positions starting with Chair, Vice-Chair, Secretary, Webmaster, 
Postmaster, and Model Librarian.  No nominations from the floor were
made.  Bob Ross moved that the slate of nominees as read below be elected.
Arpad Muranyi seconded, and the following officers for 2003-2004 were 
elected unanimously.

  Michael Mirmak, Chair
  Lynne Green, Vice Chair
  Randy Wolff, Secretary
  Syed Huq, Webmaster
  John Angulo, Postmaster
  Roy Leventhal, Model Librarian


IBIS 4.1 STATUS AND UPDATE
Lynne Green, Cadence Design Systems
Lynne began her presentation by noting that IBIS 4.0 was approved in July,
2002 and a parser is expected in the third quarter of 2003.  IBIS 4.1 will
include five additional BIRDs, including the major addition of multi-lingual
modeling support.  Lynne also noted that there is one outstanding BIRD
that will probably not be included in IBIS 4.1.

The remaining BIRDS to be included in IBIS 4.1 address several different
issues.  Improved support for differential buffers is addressed through
BIRD 77.  BIRD 80 added ext_ref as a new [Pin Mapping] column, helping to
drive adoption of BIRD 78 to extend the line length limit to 120 characters.  
Finally, BIRD 81 clarifies [Series Pin Mapping] and series model usage.

The next step in IBIS specification development is presentation of
the draft version of IBIS 4.1 to the Open Forum for an approval vote.  
Once the specification is approved, a parser is written and any issues 
which arise from parser development are folded into IBIS
4.2 (which may include an EMC specification as defined by BIRD 74).  
When the IBIS 4.2 parser is stable, the specification will be presented 
to ANSI/EIA for approval through a formal letter ballot. 


BEHAVIORAL VHDL-AMS I/O BUFFER MODELS USING IBIS
Arpad Muranyi, Intel Corp. and Luca Giacotto, Université Joseph Fourier
Arpad stated that the motivation for the presentation was to develop
algorithms for simulating a basic I/O buffer model IBIS description 
using VHDL-AMS.  Source code for this effort will be made freely available 
to anyone interested. Arpad noted that his presentation was not 
intended as a tutorial on the VHDL-AMS language.

Arpad first presented a standard IBIS I/O model with four IV curves
(pullup, pulldown, clamps) and Vt tables that describe switching.
Arpad then introduced the classic equations which define the Vt and
IV curve relationship, where the IV curves scale the Vt curves through
coefficients called K factors (here, Kpu and Kpd for the pullup and
pulldown factors, respectively).  Arpad noted that Kpu and Kpd are assumed 
to be identical which may not be accurate in all cases.

Arpad then went on to show the equations as implemented in VHDL-AMS code, 
where the two equations are solved to find the value of K.  The equations 
are placed into a for loop, and K is resolved for each point on the pullup 
or pulldown curve.  Arpad noted that the K values are calculated and stored 
from the model data when the simulator is initialized, not at run time.

Arpad showed results comparing HSPICE B-element and AMS implementation 
results to data from the source transistor model.  In general, the B-element 
and AMS curves matched closely, but were not identical.

Luca then presented a slightly different version of the code with 
separate structures defining the pullup, pulldown and clamp behaviors.  
The top-level code contained only the concurrent statements of the digital 
logic and transistors.

Luca then went on to explain how to solve an existing problem first noted
when creating models for DDR memory interfaces.  These models connect
their terminations to VCC/2 when used, but the model is extracted with 
fixture voltages of VCC and GND.  The best approach to using this data
in these cases is that, while some simulators can only use two Vt tables 
at a time, different sets of Vt tables may be used at different times or 
depending on the model's initial conditions.  Luca described a four-curve
data set, with fixture voltages set to 0, 1/3*Vcc, 2/3*Vcc and Vcc.  With 
this set of waveforms, the AMS implementation overlays transistor level 
model results across the entire run time.  Luca noted that this approach 
still assumes that all Vt tables have the same R_fixture, which generally 
matches the target system impedance.

A discussion followed regarding loading where Al Davis and others noted
that lower impedance loads will cause more error than higher impedance 
loads for a given set of model data.

Arpad's and Luca's files will be uploaded to the IBIS web site.


IBIS ALGORITHMS REVISITED
Bob Ross, Teraspeed
Bob stated that his slides were part of a larger presentation given
at the IEEE SPI Conference in Siena, Italy earlier this year.  Bob noted
that, early on, IBIS tools settled on a data-processing algorithm 
involving two waveforms, but there are other algorithms possible.  These
include using multiple tables with dynamic interpolation and modeling the 
transistors themselves as was done for the Japanese IMIC specification.  
Recently radial base functions have also been considered.

Bob first explained a very simple algorithm using only ramp data and
assuming a 5 volt linear device driving into a 50 ohm resistive load.
Additional variations, including Norton and Thevenin linear transitions
plus table multipliers were addressed, with a comparison to actual 
waveforms.  Bob showed how two waveforms were required to get independent K 
values for IBIS pullup and pulldown data.

More advanced simulation techniques must handle generalized loading cases, 
rather than loads which are purely resistive.  Bob used a SPICE netlist to 
address the problem, incorporating two models in a feedback loop of an 
operational amplifier, where the amplifier itself drove the scaling or K 
table values.  The input of the amplifier, being connected to output node, 
would then converge on an appropriate solution for the load used.

Finally, Bob addressed overclocking IBIS buffers, where IBIS models are
driven in simulation over shorter periods than allowed by the length
of the Vt waveforms.  Unfortunately, no immediate solution to this
problem is currently available.  A discussion followed the presentation,
in which Al Davis, Arpad Muranyi and Bob examined additional alternatives
for addressing overclocking and buffer characterization.


AD-HOC PRESENTATION ON HOW TO MODEL THE SWITCHING INTO AN UNFINISHED 
EDGE PROBLEM (Ad Hoc)
Arpad Muranyi, Intel Corp.
In addition to his scheduled presentations, Arpad provided an ad-hoc
set of slides addressing the driver overclocking problem.  Using several
image overlays, Arpad demonstrated that overclocked buffers show a 
relatively constant delay between pulldown turning off and pullup
turning on, and vice-versa.  Arpad proposed that this delay could be
characterized and included with other IBIS data as a parameter. 


MODELING ON-DIE TERMINATIONS
Arpad Muranyi, Intel Corp.
Arpad began his presentation by noting some of the more advanced
design features now commonly available, including dynamic clamps,
staged buffers, kicker circuits and the like.  While many of these
features may be difficult to model without intimate knowledge of the
buffer design, a general rule of thumb is that any design aspect 
which is static should be represented through the IBIS clamp tables.  
Users and model makers observing this rule for terminations should 
be careful to use the appropriate rail for correct power and ground 
bounce simulations.  Most especially, double counting of these 
termination features should be avoided whenever possible.

Arpad classified the types of termination as series, parallel or 
switched parallel.  Series termination does not require any special 
analysis for inclusion in IBIS as it will naturally be included in
the IV curve shapes.  Parallel termination behaviors should be placed 
in clamp tables by sweeping the voltage on the pad from -Vcc to
2*Vcc, both using ground referencing and Vcc referencing.  By 
finding the curve which passes through the origin, one can find
the curve set most appropriate in which to include the resistor.  This
curve will be cut at Vcc, while the other will be cut at ground.  The curve
without the resistor can then be normalized or shifted to pass through
the IV origin.  Both curves can then be extrapolated to 2*Vcc.

Switch parallel terminations are commonly implemented by leaving either
the pullup or pulldown active when the device receives.  In this case,
normal I/O IV curves may be created and the appropriate pullup or 
pulldown curve may be copied to a [Submodel] and renamed to be a
dynamic, non-driving clamp.  Example IBIS text for this implementation
was provided.

Finally, Arpad addressed the case where both pullup and pulldown 
terminations are present in a design.  The model maker in this case cannot
be sure how to determine the value of each termination separately when 
only the Thevinen equivalent can be observed.   Lynne Green and
Bob Ross suggested that analysis of the slopes can be used to
help determine where non-linear resistive termination data can be
included.


OTHER DISCUSSIONS AND AD HOC PRESENTATIONS 
Stephen reminded participants that, if they intend to attend DesignCon 
East, they should register as soon as possible. 

Lynne Green gave a brief report on her observations from the DAC floor.  
She noted that a greater number of I/O companies have heard of
IBIS than in previous years, with an increased interest in membership.  
I/O companies and organizations expressed general interest in AMS 
technologies for mixed electrical and mechanical simulations, but not 
necessarily for modeling I/O buffers.  Buffer modeling using AMS 
is likely to become more prevalent within the next two to three years.  

Lynne also mentioned that several tools displayed on the DAC floor 
included support of SPICE, AMS and IBIS together.  Arpad noted that he 
would like to see more AMS implementations with greater model development 
and debugging capabilities.

CONCLUDING ITEMS
Stephen Peters thanked the presenters for the great and informative 
presentations.  After reminding the participants regarding the next 
teleconference meeting, Stephen closed the IBIS Summit Meeting.


NEXT MEETING(S):
The next Open Forum meeting will be the IBIS Summit at DesignCon East
on Monday, June 23, 2003.  Teleconference bridge details will be
distributed separately.

The Open Forum will also hold a meeting on Friday, June 27, 2003 from
8:00 AM to 10:00 AM Pacific time.  A vote on BIRD 74.4 is planned.

============================================================================

                                      NOTES

IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046
            michael.mirmak@intel.com
            Senior Analog Engineer, Intel Corporation
            M/S FM6-45
            1900 Prairie City Rd.
            Folsom, CA  95630

VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 451-1871
            lgreen@cadence.com
            Senior Modeling Engineer, Cadence Design Systems
            320 120th Ave NE, Suite B-103, Bellevue, WA 98005-3016

SECRETARY:  Randy Wolff (208) 363-1764, Fax: (208) 368-3475
            rrwolff@micron.com
            Simulation Engineer, Micron Technology, Inc.
            8000 S. Federal Way
            Mail Stop: 1-711
            Boise, ID 83707-0006
        
LIBRARIAN:  Roy Leventhal (847) 590-9398
            roy.leventhal@ieee.org
            Consultant, Leventhal Design and Communications
            1924 North Burke Drive
            Arlington Heights, Illinois 60004

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
            John_angulo@mentor.com
            Development Engineer, Mentor Graphics
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052


This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  majordomo@eda.org
      In the body, for the IBIS Open Forum Reflector:
      subscribe ibis <your e-mail address>

      In the body, for the IBIS Users' Group Reflector:
      subscribe ibis-users <your e-mail address>

      Help and other commands:
      help

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
      bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
      /pub/ibis/bugs/s2iplt/bugsplt.txt respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.

============================================================================
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------------------------------

Date: Tue, 10 Jun 2003 09:52:36 -0400
From: "Allen Chao" <achao@synopsys.com>
Subject: [IBIS-Users] [IBIS] for a question of s2ibis2, thanks in advance!!

Hi,
First of all, any help will be greatly appreciated. I am a coop student here
and I am in charge of the conversion from Hspice to IBIS model.
I am confused about how to construct [pin mapping] and [pin] in a command
file .s2i. (I am using North Carolina State University's s2ibis2 utility for
automatic Spice model to IBIS Version 2.1 model conversion)
Our device has some switches (by indicating high or low) to control the
transfer speed. I am trying to model the output by grounding or vcc few
inputs. I've tried a lot of cases. Can anyone show me how to ground or vcc
an input?
THANKS IN ADVANCE!!!

Allen Chao

I also include the error log and what I put in the .s2i file in the bottom.
- -------------------------------------------------------------------------
- -Below is the error log from the pct8.out file (any information on this is
good too. ^^)

 vouts2i tx_pd 0 dc 0
 h$dps2i vdd33t_tx 0 dc 5.5

 **error**:  voltage source not found on above line

 vgclh
h\i vss33t@.temp 27
 **error**  above line attempts to redefine h$dps2i


 **error**:  voltage source not found on above line

 .options ingold=2
 .dc vouts2i 5 10 0.1
 .print dc i(vouts2i)
 .end
 >error   ***difficulty in reading input

- -------------------------------------------------------------------------
Here is what I put in the .s2i file:

[pin mapping]
1   DRV_GND 	NC
2   NC 		DRV_VDD
3   DRV_GND		DRV_VDD
4   DRV_GND		DRV_VDD
|5   NC           NC
|6	NC		DRV_VDD
|7   DRV_GND	NC
8     NC		NC
9     NC		NC
10    NC		NC
11    NC		NC
12    NC		NC
13    NC		NC
|14   DRV_GND     NC
|15
|16
17  NC	NC
18  NC	NC
19  NC	NC
|20
|21  DRV_GND	DRV_VDD
|22  DRV_GND	DRV_VDD
|23  DRV_GND      NC
|24  DRV_GND	NC

[Pin]
1	VSS33T_TX	gnd     GND
2	VDD33T_TX	vdd	POWER
3	DP		dp	output_dp
- -> 12 9
4	DM		dm	output_dm
- -> 12 9
|5	IABSPN100U_TX	iabs100	test
|6	HS_DRIVE_ENABLEN vdd	POWER
|7	HS_DRIVE_ENABLE gnd	GND
8	TX_PD 		pd_gnd	input
9	FS_LS_OE 	ena	input
10	FS_LS_DATAN 	in_2	input
11	FS_EDGE_SEL	fs_vdd	input
12 	FS_LS_DATA 	in_1	input
13	TX_SE0 		tx_gnd	input
|14	HCSEF 		gnd	GND
|15	HS_DATAN
|16	HS_DATA
17	VDRES[2]	2_gnd	input
18	VDRES[1]	1_vdd	input
19	VDRES[0]	0_gnd	input
|20	DETECT_5V_ENN
|21	VDTX_TEST_OUT[0] vdtxto0	test
|22	VDTX_TEST_OUT[1] vdtxto1	test
|23	HS_CURRENT_SRC_EN	gnd	GND
|24	IABSPN25U_TX	iabs25	test

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------------------------------

Date: Tue, 10 Jun 2003 09:43:38 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce

John,

Sorry for the late reply.  We do use IBIS models for what we
call "Power Delivery" simulations (which is the same thing
you asked about).  However, we only use the buffer model in
IBIS format, and have a more accurate package and PDN model
in different formats.

The new ICM (IBIS Interconnect Model Specification) provides
(now) a much more accurate way to model the passive circuits,
but the new language extensions to the buffer modeling
capabilities of IBIS (BIRD75) will provide further improvements
for buffer modeling also.

As soon as tools begin to support these new features we will be
able to do very accurate power delivery simulations using IBIS
files for the passive as well as the active circuits.

Arpad Muranyi
Intel Corporation
===============================================================

- -----Original Message-----
From: John Phillippe [mailto:john.phillippe@motorola.com]
Sent: Thursday, May 08, 2003 2:27 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce


I'm curious as to how many people use IBIS models to simulate VDD Droop 
and Ground Bounce.  Is IBIS even a worthwhile format to try this with? 
Do current simulators do anything with regards to modeling the voltage 
drops across the powerbus on the chip?

- -- 
John Phillippe
SPS, 32 Bit Embedded Controller Division, IC Creation
Motorola      -  512-895-1835
Austin, TX    -  john.phillippe@motorola.com
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------------------------------

Date: Tue, 10 Jun 2003 10:09:07 -0700
From: "Zhiping Yang" <zhiping@cisco.com>
Subject: Re: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce

HI Arpad,

Can you clarify a little bit more on this? Do you have any papers or
presenations on this topic? For my understanding, it is impossible or very
difficult to model the cross-bar current in IBIS model, but the cross-bar
current is very important for power delivery system simulation. About one
year ago, I did some simulation comparasions between HSPICE model and IBIS
model in power integrity. At that time, the IBIS model behaviored very poor
for some kinds of I/O buffer. I would be very interested to be updated on
new IBIS capabilities on power delivery system simulations. Thanks.

Zhiping


Zhiping Yang. Ph.D.
Signal Integrity Engineer
CISCO SYSTEMS
170 West Tasman Dr.
San Jose, CA 95134
Phone: 408-525-5690
Fax: 408-525-5690
E-mail: zhiping@cisco.com

This Message and any attached documents contain confidential information of
CISCO Systems,  Inc. and its affiliates and may be used only by the intended
recipient(s) of this communication for the purpose set forth and in a manner
consistent with your agreement with Cisco Systems, Inc. to preserve its
confidential information.

- ----- Original Message -----
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: <ibis-users@eda.org>
Sent: Tuesday, June 10, 2003 9:43 AM
Subject: RE: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce


> John,
>
> Sorry for the late reply.  We do use IBIS models for what we
> call "Power Delivery" simulations (which is the same thing
> you asked about).  However, we only use the buffer model in
> IBIS format, and have a more accurate package and PDN model
> in different formats.
>
> The new ICM (IBIS Interconnect Model Specification) provides
> (now) a much more accurate way to model the passive circuits,
> but the new language extensions to the buffer modeling
> capabilities of IBIS (BIRD75) will provide further improvements
> for buffer modeling also.
>
> As soon as tools begin to support these new features we will be
> able to do very accurate power delivery simulations using IBIS
> files for the passive as well as the active circuits.
>
> Arpad Muranyi
> Intel Corporation
> ===============================================================
>
> -----Original Message-----
> From: John Phillippe [mailto:john.phillippe@motorola.com]
> Sent: Thursday, May 08, 2003 2:27 PM
> To: ibis-users@eda.org
> Subject: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce
>
>
> I'm curious as to how many people use IBIS models to simulate VDD Droop
> and Ground Bounce.  Is IBIS even a worthwhile format to try this with?
> Do current simulators do anything with regards to modeling the voltage
> drops across the powerbus on the chip?
>
> --
> John Phillippe
> SPS, 32 Bit Embedded Controller Division, IC Creation
> Motorola      -  512-895-1835
> Austin, TX    -  john.phillippe@motorola.com
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------------------------------

Date: Wed, 11 Jun 2003 15:39:14 +0530
From: locate_me <locate_me@15to25.com>
Subject: [IBIS-Users] MIME-Version: 1.0

- --153914115103.19543.locate_me@15to25.com
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit

hi,
  i'm trying to make IBIS model for a I/O buffer. i'm giving two cycle (two pulse) of input and enable is there from initialization.
when i compare the netlist simulation result and IBIS model simulation result. i'm getting IBIS model result (in 2nd cycle) very far from the netlist simulation result. in the very first cycle every thing fine both plots are overlapping eachother.
 now 1) shd i give enable after the input means a pulse shd be there on enable.
     2) there are two rising and falling waveforms are generated for two type of load (one to gnd and other to Vcc). and i'm not using ne thing for selecting the ramp up parameter while simulating the IBIS model. we have two parameter called ramp_rwf and ramp_fwf. default value for this 0. so shd i change it to 2.

regs 
deepak

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------------------------------

Date: Wed, 11 Jun 2003 14:39:19 +0200
From: Itzik Peleg <itzik.peleg@il.marvell.com>
Subject: Re: [IBIS-Users] MIME-Version: 1.0

Hello deepak

 1. What version of hspice are you using ?
      If you are using 2001 version try to replace it to a newer one.
 2. The parameters ramp_rwf and ramp_fwf determine the usage of the Vt
curves. If your model include the Vt curves (... it better be) then
setting the prams to 2 will give you the most accurate results.

- --
Regards

Itzik Peleg
Board Technology Group

Marvell Semiconductor Israel Ltd
Moshav Manof, D.N. Misgav 20184, ISRAEL
Email - itzik.peleg@il.marvell.com
Tel   - +972 4 9951192
Cell  - +972 54 452482
Fax   - +972 4 9999334
WWW Page: http://www.marvell.com
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------------------------------

Date: Thu, 12 Jun 2003 16:07:04 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] Differential I/O IBIS Models

Suhail,

Check out my presentation at:

http://www.eda.org/pub/ibis/summits/oct02/muranyi.pdf

particularly pages 7-8.  I hope this will help you to get
started.  Just be aware, not too many tool vendors have
implemented the series keywords yet.

Arpad
=========================================================

- -----Original Message-----
From: Suhail Zain [mailto:suhail@lightspeed.com]
Sent: Wednesday, June 04, 2003 3:27 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] Differential I/O IBIS Models




Hi:

What is the best way to generate IBIS models fro Differential I/Os? 
 When I use S2IBIS2 to generate the model
(single ended approach), the IBISCHK3 fails. Any suggestions.

Suhail Zain




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------------------------------

Date: Fri, 13 Jun 2003 11:30:26 -0400
From: "Hassan Ali" <Hassan.Ali@fidus.ca>
Subject: RE: [IBIS-Users] Differential I/O IBIS Models

Arpad, 

1. The IV curve setup on page 8 of your presentation would give rise to
several IV tables - as many as the number of Vp/Vn steps. How do you
consolidate those tables into single pullup and pulldown IV tables?

2. On the V-t curve setup of page 18, how do you obtain Idiff? 

I'd appreciate your response to the above.

Thanks.

Hassan.


Hassan Ali, Ph.D.             
Signal Integrity Specialist   -Talented, innovative designers
Fidus Systems Inc.               -Highly competitive rates
Tel: (613) 828-0063 Ext.342   -Fixed-price business model
Fax: (613) 828-3113              -State-of-the-art design tools
http://www.fidus.ca                -Customer-friendly attitude

- -----Original Message-----
From: Muranyi, Arpad [mailto:arpad.muranyi@intel.com] 
Sent: Thursday, June 12, 2003 7:07 PM
To: ibis-users@eda.org
Subject: RE: [IBIS-Users] Differential I/O IBIS Models

Suhail,

Check out my presentation at:

http://www.eda.org/pub/ibis/summits/oct02/muranyi.pdf

particularly pages 7-8.  I hope this will help you to get
started.  Just be aware, not too many tool vendors have
implemented the series keywords yet.

Arpad
=========================================================

- -----Original Message-----
From: Suhail Zain [mailto:suhail@lightspeed.com]
Sent: Wednesday, June 04, 2003 3:27 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] Differential I/O IBIS Models




Hi:

What is the best way to generate IBIS models fro Differential I/Os? 
 When I use S2IBIS2 to generate the model
(single ended approach), the IBISCHK3 fails. Any suggestions.

Suhail Zain




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------------------------------

Date: Fri, 13 Jun 2003 08:41:14 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] Differential I/O IBIS Models

Hassan,

1)  You could use the [Series MOSFET] keyword to describe that
surface.  The only limitation is that is assumes a symmetric
surface, but it allows you up to 100 IV curves.

2)  I suspect that you are talking about page 19, not 18.  Idiff
is the same as "differential current" on pg. 8, 10, 12, 14, 16.

I hope this clarifies your questions.

Arpad
================================================================

- -----Original Message-----
From: Hassan Ali [mailto:Hassan.Ali@fidus.ca]
Sent: Friday, June 13, 2003 8:30 AM
To: Muranyi, Arpad; ibis-users@eda.org
Subject: RE: [IBIS-Users] Differential I/O IBIS Models


Arpad, 

1. The IV curve setup on page 8 of your presentation would give rise to
several IV tables - as many as the number of Vp/Vn steps. How do you
consolidate those tables into single pullup and pulldown IV tables?

2. On the V-t curve setup of page 18, how do you obtain Idiff? 

I'd appreciate your response to the above.

Thanks.

Hassan.


Hassan Ali, Ph.D.             
Signal Integrity Specialist   -Talented, innovative designers
Fidus Systems Inc.               -Highly competitive rates
Tel: (613) 828-0063 Ext.342   -Fixed-price business model
Fax: (613) 828-3113              -State-of-the-art design tools
http://www.fidus.ca                -Customer-friendly attitude

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------------------------------

Date: Mon, 16 Jun 2003 10:38:24 -0700
From: "Mirmak, Michael" <michael.mirmak@intel.com>
Subject: [IBIS-Users] Agenda, IBIS Open Forum Summit at DesignCon East

- ------------------------------------------------------------------
AGENDA, IBIS SUMMIT MEETING
June 23, 2003 at DesignCon East
 
Best Western Royal Plaza Hotel and Trade Center
181 Boston Post Road West
Marlborough, Massachusetts
 
Room: Westborough 
      (check signs at site)

Teleconference: 916-356-2663
     Bridge No: 1
      Passcode: 879-9810

Those requiring toll-free access must register with 
Barry Katz (bkatz@sisoft.com) at least 24 hours in advance

All times US Eastern Daylight
- ------------------------------------------------------------------
 
9:00 AM     Refreshments & Sign In
 
9:30 AM     Introductions
            - Welcome to Summit
            - Introductions
            - Opens for New Issues and Discussion Topics
 
9:45 AM     IBIS Chair's Report
            Michael Mirmak, Intel Corporation
 
10:00 AM    IBIS Quality Committee Update
            Barry Katz, Signal Integrity Software (SiSoft)

10:30 AM    Break
 
10:45 AM    ICM Status and Update
            Michael Mirmak, Intel Corporation
 
11:15 AM    Behavioral VHDL-AMS I/O Buffer Model using IBIS
            Arpad Muranyi, Intel Corporation
 
11:45 AM    Lunch (hosted by IBIS)
            Best Western Royal Plaza Hotel
 
1:00 PM     IBIS models at 1.25 GHz and Beyond 
            Robert Haller, Signal Integrity Software (SiSoft)

1:30 PM     IBIS 4.1 Status and Update
            Lynne Green, Cadence Design Systems

2:00 PM     IBIS Algorithms Revisited
            Bob Ross, Teraspeed 

2:30 PM     Break

2:45 PM     Ad Hoc Presentation on How to Model the
            Switching into an Unfinished Edge Problem
            Arpad Muranyi, Intel Corporation

3:00 PM     Modeling On-die Terminations
            Arpad Muranyi, Intel Corporation
 
3:30 PM     On-Die Termination Comments
            Bob Ross, Teraspeed

3:45 PM     Open Discussion and Ad Hoc Topics
            All
 
4:45 PM     Concluding Items
            - Next Open Forum Meeting June 27, 2003
 
5:00 PM     End of IBIS Summit Meeting
 
- ------------------------------------------------------------------
 
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------------------------------

Date: Mon, 16 Jun 2003 11:55:39 -0700
From: "Eric Hsu" <ehsu@netlogicmicro.com>
Subject: RE: [IBIS-Users] Problem in ibs file generated by s2ibs2

This is a multi-part message in MIME format.

- ------_=_NextPart_001_01C33438.E10C0AAF
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi Mike and IBIS experts,

According to previous your suggestion to fix data jumping issue, we get =
the ibis model as follows:

Case1(#define DIODE_DROP_DEFAULT    1.0)
 -3.3000       0.000A              0.000A              0.000A
  -3.1000       0.000A              0.000A              0.000A
  -2.9000       0.000A              0.000A              0.000A
  -2.7000       0.000A              0.000A              0.000A
  -2.5000       0.000A              0.000A             -10.0000mA
  -2.3000       0.000A              0.000A             -10.0000mA
  -2.1000       0.000A              0.000A              0.000A
  -1.9000      -10.0000mA           0.000A              0.000A
  -1.7000      -10.0000mA           0.000A             -10.0000mA
  -1.5000      -10.0000mA           0.000A             -10.0000mA	=
<---(jumping point)
  -1.0000      -44.0000mA          -10.0000mA          -64.0000mA	<---
  -0.9000      -53.0000mA          -17.0000mA          -79.2000mA
  -0.8000      -67.3000mA          -23.0000mA          -87.3700mA
  -0.7000      -66.9500mA          -30.0000mA          -83.6600mA
  ...
  ...
  ...
P.S.--- no error flag by ibischk3.
Case2(#define DIODE_DROP_DEFAULT    0.7)
  -3.3000       0.000A              0.000A              0.000A
  -3.2488       0.000A              0.000A              0.000A
  -3.1976       0.000A              0.000A              0.000A
  -3.1464       0.000A              0.000A              0.000A
  -3.0952       0.000A              0.000A              0.000A
  -3.0440       0.000A              0.000A              0.000A
  -2.9928       0.000A              0.000A              0.000A
  -2.9416       0.000A              0.000A              0.000A
  -2.8904       0.000A              0.000A              0.000A
  -2.8392       0.000A              0.000A              0.000A	=
<---(jumping point)
  -0.6888      -66.5200mA          -30.7000mA          -83.0900mA	<---
  -0.6376      -64.1500mA          -33.7700mA          -80.3100mA
  -0.5864      -61.2330mA          -35.3200mA          -77.0500mA
  ...
  ...
  ...
P.S.--ERROR (line  156) - More Than 100 Voltage Points Provided For =
Pulldown/Pullup.

There are couple problems I would like to solve,
First, while modify from 1.0 to 0.7, it seems cause bigger jump from 0.5 =
to 2.1 (1.5-1.0 and 2.8-0.7), is there anything else cause this problem?
Second, by setting 0.7 as diode default, it will generate over 100 point =
in pulldown and pullup tables, and ibischk3 complain error for that. Do =
we need to update ibischk3? Or any solution we can fix it?
Third, if comparing sweep voltage point from two case, you can see case1 =
is 0.2 or 0.1V, but in case2 it always keep 0.512V. It suppose to like =
this? Or we also change other parameter, such "sweep_step_default" in =
s2idflt.h file?


Best Regards,



Eric Hsu
Interface Technologies
NetLogic Microsystems, Inc.
450 National Ave.
Mountain View, CA 94043
650-961-6676 x198
This e-mail contains NetLogic Microsystems, Inc. Confidential =
information



- -----Original Message-----
From: Mike LaBonte [mailto:milabont@cisco.com]
Sent: Wednesday, May 14, 2003 11:53 AM
To: Syed Huq; Birendra Rana
Cc: ibis-users@server.eda.org
Subject: RE: [IBIS-Users] Problem in ibs file generated by s2ibs2


The fixed s2ibis2 prints 4 digits after the decimal instead of 2. With =
only
2 digits, voltage differences less than 10mV between points make them =
appear
identical.

Also there is a parameter in s2idflt.h:

#define DIODE_DROP_DEFAULT              1.0

This is used by s2ibis2 to jump around in the SPICE data to find =
beginnings
and ends of "linear" and "non-linear" regions. On lower voltage devices =
the
1V value makes s2ibis2 jump too far and pick up wrong data or ignore =
data.
Change the value to 0.7, recompile, and s2ibis2 will work better.

Mike LaBonte

> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
> Behalf Of Syed Huq
> Sent: Wednesday, May 14, 2003 12:12 PM
> To: Birendra Rana
> Cc: ibis-users@eda.org
> Subject: Re: [IBIS-Users] Problem in ibs file generated by s2ibs2
>
>
> First of all, you are using an older version of s2ibis2. You should
> download the s2ibis2_fix.tar.Z
>
> I have seen these repetition of data points. Not sure what causes it.
> You have to delete them to clean up the file.
>
> Delete everything below 3.6V as well as one of the -0.9 entries.
>
> Syed
>
> On Wed, 2003-05-14 at 04:56, Birendra Rana wrote:
> > Hi all,
> >
> > I have generated an IBIS Model for an I/O buffer using s2ibis2 =
script.
> > Interestingly the generated ibs file has entries in the Pull down
> > table as follows :
> >
> > [Pulldown]
> > |  voltage         I(typ)           I(min)             I(max)
> > |
> >      -1.80          -42.50mA     -54.11mA         -28.61mA
> >       .
> >       .
> >       .
> >      -0.90         -36.68mA     -30.62mA        -38.74mA
> >      -0.90         -36.68mA     -30.62mA        -38.74mA  <-
> > Repetition of above data
> >      -0.80         -37.07mA     -29.68mA        -41.00mA
> >       .
> >       .
> >       .
> >       0.00             0.36uA         2.61nA            2.86uA
> >       .
> >       .
> >       .
> >       3.60            94.05mA      80.81mA           0.11A
> >       0.00             -1.80A          0.11kA          -92.95A   <-
> > ?????
> >  -137.28             -1.70A        -99.02A          -82.08A   <-
> > ?????
> >       3.60            94.05mA      80.81mA           0.11A     <-
> > Repetition of 3.60V entry data
> >
> > Similar kind of entries (like the repetition of -0.90V and 3.60V =
data
> > and extra 2 rows) are there in the Pullup table. The ".out"
> > files however look alright.
> >
> > Any reasons for these extra / repetitive entries ?
> >
> > Regards,
> >
> > Birendra
> > =
**************************Disclaimer************************************
> >
> > Information contained in this E-MAIL being proprietary to Wipro
> Limited is
> > 'privileged' and 'confidential' and intended for use only by
> the individual
> >  or entity to which it is addressed. You are notified that any
> use, copying
> > or dissemination of the information contained in the E-MAIL in
> any manner
> > whatsoever is strictly prohibited.
> >
> >
> ******************************************************************
> *********
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------------------------------

Date: Mon, 16 Jun 2003 15:35:33 -0400
From: "Mike LaBonte" <milabont@cisco.com>
Subject: RE: [IBIS-Users] Problem in ibs file generated by s2ibs2

This is a multi-part message in MIME format.

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I forgot about that part. What I did is:

1) Change SWEEP_STEP_DEFAULT from 0.1 to 0.01 in s2ibis.h

2) Take out the 3 places in setupVoltages() where sweepStep is adjusted
   in a binary fashion:

   /*   while ( ( fabs( *sweepRange_P / *sweepStep_P ) + 1 ) >
MAX_TABLE_SIZE )
            *sweepStep_P *= 2; */

3) Add sweepStep adjustment at the very end of setupVoltages():
    /*------------------------------------------------------------------
    *   (18jan2001) Adjust the sweepStep to keep the table size within
limits.
    *   The SWEEP_STEP_DEFAULT has been decreased from 0.1V to 0.01V. The
    *   binary multiplication algorithm has been replaced by a stepping
    *   algorithm that leaves the final value at some multiple of the
default.
    *   This change provides a number of VI points that is close to
    *   MAX_TABLE_SIZE.
    *------------------------------------------------------------------*/
    {
      double sweepStepInc = *sweepStep_P;

      while ( ROUND(*sweepRange_P / *sweepStep_P) >= MAX_TABLE_SIZE )
        *sweepStep_P += sweepStepInc;
    }

Mike

- -----Original Message-----
From: Eric Hsu [mailto:owner-ibis-users@eda.org]On Behalf Of Eric Hsu
Sent: Monday, June 16, 2003 2:56 PM
To: Mike LaBonte
Cc: Frank Dunlap; Ibis-Users (E-mail)
Subject: RE: [IBIS-Users] Problem in ibs file generated by s2ibs2


Hi Mike and IBIS experts,

According to previous your suggestion to fix data jumping issue, we get the
ibis model as follows:

Case1(#define DIODE_DROP_DEFAULT    1.0)
 -3.3000       0.000A              0.000A              0.000A
  -3.1000       0.000A              0.000A              0.000A
  -2.9000       0.000A              0.000A              0.000A
  -2.7000       0.000A              0.000A              0.000A
  -2.5000       0.000A              0.000A             -10.0000mA
  -2.3000       0.000A              0.000A             -10.0000mA
  -2.1000       0.000A              0.000A              0.000A
  -1.9000      -10.0000mA           0.000A              0.000A
  -1.7000      -10.0000mA           0.000A             -10.0000mA
  -1.5000      -10.0000mA           0.000A             -10.0000mA
<---(jumping point)
  -1.0000      -44.0000mA          -10.0000mA          -64.0000mA	<---
  -0.9000      -53.0000mA          -17.0000mA          -79.2000mA
  -0.8000      -67.3000mA          -23.0000mA          -87.3700mA
  -0.7000      -66.9500mA          -30.0000mA          -83.6600mA
  ...
  ...
  ...
P.S.--- no error flag by ibischk3.
Case2(#define DIODE_DROP_DEFAULT    0.7)
  -3.3000       0.000A              0.000A              0.000A
  -3.2488       0.000A              0.000A              0.000A
  -3.1976       0.000A              0.000A              0.000A
  -3.1464       0.000A              0.000A              0.000A
  -3.0952       0.000A              0.000A              0.000A
  -3.0440       0.000A              0.000A              0.000A
  -2.9928       0.000A              0.000A              0.000A
  -2.9416       0.000A              0.000A              0.000A
  -2.8904       0.000A              0.000A              0.000A
  -2.8392       0.000A              0.000A              0.000A	<---(jumping
point)
  -0.6888      -66.5200mA          -30.7000mA          -83.0900mA	<---
  -0.6376      -64.1500mA          -33.7700mA          -80.3100mA
  -0.5864      -61.2330mA          -35.3200mA          -77.0500mA
  ...
  ...
  ...
P.S.--ERROR (line  156) - More Than 100 Voltage Points Provided For
Pulldown/Pullup.

There are couple problems I would like to solve,
First, while modify from 1.0 to 0.7, it seems cause bigger jump from 0.5 to
2.1 (1.5-1.0 and 2.8-0.7), is there anything else cause this problem?
Second, by setting 0.7 as diode default, it will generate over 100 point in
pulldown and pullup tables, and ibischk3 complain error for that. Do we need
to update ibischk3? Or any solution we can fix it?
Third, if comparing sweep voltage point from two case, you can see case1 is
0.2 or 0.1V, but in case2 it always keep 0.512V. It suppose to like this? Or
we also change other parameter, such "sweep_step_default" in s2idflt.h file?


Best Regards,



Eric Hsu
Interface Technologies
NetLogic Microsystems, Inc.
450 National Ave.
Mountain View, CA 94043
650-961-6676 x198
This e-mail contains NetLogic Microsystems, Inc. Confidential information



- -----Original Message-----
From: Mike LaBonte [mailto:milabont@cisco.com]
Sent: Wednesday, May 14, 2003 11:53 AM
To: Syed Huq; Birendra Rana
Cc: ibis-users@server.eda.org
Subject: RE: [IBIS-Users] Problem in ibs file generated by s2ibs2


The fixed s2ibis2 prints 4 digits after the decimal instead of 2. With only
2 digits, voltage differences less than 10mV between points make them appear
identical.

Also there is a parameter in s2idflt.h:

#define DIODE_DROP_DEFAULT              1.0

This is used by s2ibis2 to jump around in the SPICE data to find beginnings
and ends of "linear" and "non-linear" regions. On lower voltage devices the
1V value makes s2ibis2 jump too far and pick up wrong data or ignore data.
Change the value to 0.7, recompile, and s2ibis2 will work better.

Mike LaBonte

> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
> Behalf Of Syed Huq
> Sent: Wednesday, May 14, 2003 12:12 PM
> To: Birendra Rana
> Cc: ibis-users@eda.org
> Subject: Re: [IBIS-Users] Problem in ibs file generated by s2ibs2
>
>
> First of all, you are using an older version of s2ibis2. You should
> download the s2ibis2_fix.tar.Z
>
> I have seen these repetition of data points. Not sure what causes it.
> You have to delete them to clean up the file.
>
> Delete everything below 3.6V as well as one of the -0.9 entries.
>
> Syed
>
> On Wed, 2003-05-14 at 04:56, Birendra Rana wrote:
> > Hi all,
> >
> > I have generated an IBIS Model for an I/O buffer using s2ibis2 script.
> > Interestingly the generated ibs file has entries in the Pull down
> > table as follows :
> >
> > [Pulldown]
> > |  voltage         I(typ)           I(min)             I(max)
> > |
> >      -1.80          -42.50mA     -54.11mA         -28.61mA
> >       .
> >       .
> >       .
> >      -0.90         -36.68mA     -30.62mA        -38.74mA
> >      -0.90         -36.68mA     -30.62mA        -38.74mA  <-
> > Repetition of above data
> >      -0.80         -37.07mA     -29.68mA        -41.00mA
> >       .
> >       .
> >       .
> >       0.00             0.36uA         2.61nA            2.86uA
> >       .
> >       .
> >       .
> >       3.60            94.05mA      80.81mA           0.11A
> >       0.00             -1.80A          0.11kA          -92.95A   <-
> > ?????
> >  -137.28             -1.70A        -99.02A          -82.08A   <-
> > ?????
> >       3.60            94.05mA      80.81mA           0.11A     <-
> > Repetition of 3.60V entry data
> >
> > Similar kind of entries (like the repetition of -0.90V and 3.60V data
> > and extra 2 rows) are there in the Pullup table. The ".out"
> > files however look alright.
> >
> > Any reasons for these extra / repetitive entries ?
> >
> > Regards,
> >
> > Birendra
> > **************************Disclaimer************************************
> >
> > Information contained in this E-MAIL being proprietary to Wipro
> Limited is
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> the individual
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------------------------------

Date: Tue, 17 Jun 2003 11:43:11 -0700
From: Kannan Srinivasagam <pks@cypress.com>
Subject: [IBIS-Users] Question on pullup curves at Vtable=0

This is a multi-part message in MIME format.
- --------------99A83373D6C564AE9A6FD994
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Hi,
I am generating IBIS models for a part. For an I/O buffer model, I am
getting currents in the range of 8-20mA under MIN and MAX conditions,
when
Vtable = 0 for my PULL-UP curves. My TYP condition works fine, and I get
0A
currents for Vtable = 0.

I believe the standard is to have currents lesser than 1mA when Vtable =
0
under ALL conditions. Is there a way I can offset these currents, and
get
them to be less than a milliamp for Vtable = 0?

Thanks,
- -Kannan
.

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- --------------99A83373D6C564AE9A6FD994--

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------------------------------

Date: Thu, 19 Jun 2003 16:23:56 -0700
From: "Mirmak, Michael" <michael.mirmak@intel.com>
Subject: [IBIS-Users] Agenda, IBIS Open Forum Teleconference 6/27

		     IBIS Open Forum Meeting Agenda
			      for 6/27/03

           Bridge Number    Reservation #    Passcode
           1-916-356-2663       1            132-1085 
            (International Dial-In: 1-617-801-9781)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into
the meeting, ask for the IBIS Open Forum hosted by Stephen Peters and
give
the Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Mirmak

     - Intros of New IBIS Participants, Meeting Quorum       Mirmak
     - Call for Patents                                      Mirmak
     - Membership Update and Treasurers Report               Mirmak
     - Review of Previous Meeting's Minutes (and ARs)        Mirmak
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal,
All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation)
Perrin/Peters
     - JEDEC Committee Report                                Green

     DAC Summit Report                                       Peters

     DesignCon Summit Report                                 Katz/Mirmak

     IBIS Version 4.0 Parser Funding and Status
Mirmak/Peters

     IBIS Version 4.1 Discussion                             Peters/Ross

     IBIS Quality Committee Report                           Katz

     IBIS Model Review Committee                             Green

     New Administrative Issues                               All

8:45 Technical Discussion

     IBIS Futures Committee Report
Peters/Green

     IBIS ICM Specification Review                           Mirmak, All

     BIRD74.4 - EMI Parameters                               de Burgh
     - Call for vote 

     IBISCHK3 Status                                         Ross/Angulo
     - BUG73 Fix

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Mirmak

9:55 Sign Off
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------------------------------

Date: Thu, 19 Jun 2003 16:43:06 -0700
From: "Eric Hsu" <ehsu@netlogicmicro.com>
Subject: [IBIS-Users] Vinh and Vinl definition

This is a multi-part message in MIME format.

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Hi IBIS experts,

When reading HSTL spec. of JEDEC, it define Vinh(dc) and Vinl(dc) as =
Vref+/-100mV,  Vinh(ac) and Vinl(ac) as Vref+/-200mV. For ibis model, =
which one it suppose to be taken?

Best Regards,

Eric Hsu
Interface Technologies
NetLogic Microsystems, Inc.
450 National Ave.
Mountain View, CA 94043
650-961-6676 x198
This e-mail contains NetLogic Microsystems, Inc. Confidential =
information



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------------------------------

Date: Thu, 19 Jun 2003 16:58:34 -0700
From: "Beal, Weston" <weston_beal@mentorg.com>
Subject: [IBIS-Users] RE: Vinh and Vinl definition

Eric,

If you intend to use the IBIS model for timing simulation then use the (ac) levels.  If you are going to do noise measurements then you use the (dc) levels.  For the general case I would include two sets of Vinl and Vinh with comments defining when to use each set.

In IBIS 4.0 you can specify all 4 levels directly in the [Receiver Thresholds] block, but I don't know of any simulation checker that recognizes those parameters, yet.

Regards,
Weston


>  -----Original Message-----
> From: 	Eric Hsu [mailto:ehsu@netlogicmicro.com] 
> Sent:	Thursday, June 19, 2003 4:43 PM
> To:	Ibis-Users (E-mail)
> Cc:	Frank Dunlap
> Subject:	Vinh and Vinl definition
> 
> Hi IBIS experts,
> 
> When reading HSTL spec. of JEDEC, it define Vinh(dc) and Vinl(dc) as Vref+/-100mV,  Vinh(ac) and Vinl(ac) as Vref+/-200mV. For ibis model, which one it suppose to be taken?
> 
> Best Regards,
> 
> Eric Hsu
> Interface Technologies
> NetLogic Microsystems, Inc.
> 450 National Ave.
> Mountain View, CA 94043
> 650-961-6676 x198
> This e-mail contains NetLogic Microsystems, Inc. Confidential information
> 
> 
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------------------------------

Date: Thu, 19 Jun 2003 19:28:17 -0500
From: "Rick Kingen" <Rick.Kingen@motorola.com>
Subject: [IBIS-Users] IBIS VMEAS and VREF Question.

This is a multi-part message in MIME format.

- ------=_NextPart_000_009D_01C33698.EF953D90
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

I am getting the following warning when I run my model thru the parser:

WARNING - Model 'I_O2': MIN VI curves cannot drive through Vmeas=3D1.5V
          given load Rref=3D50 Ohms to Vref=3D0V

Can anyone enlighten me as to the significance of this warning?  Will =
the simulator in general have a problem?  The WInIBIS data looks good.

Thanks in advance.

Rick Kingen

_______________________________________________
This email communication along with any attachments
is classified as:
=20
[ X]  General business information
[ ]  Motorola internal use only
[ ]  Motorola confidential proprietary
=20

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	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2800.1106" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>I am getting the following warning when =
I run my=20
model thru the parser:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>WARNING - Model 'I_O2': MIN VI curves =
cannot drive=20
through =
Vmeas=3D1.5V<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
given load Rref=3D50 Ohms to Vref=3D0V<BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Can anyone enlighten me as to the =
significance of=20
this warning?&nbsp; Will the simulator in general have a problem?&nbsp; =
The=20
WInIBIS data looks good.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Thanks in advance.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Rick Kingen</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>&nbsp;</DIV></FONT>
<DIV><FONT face=3DArial=20
size=3D2>_______________________________________________<BR>This email=20
communication along with any attachments<BR>is classified =
as:<BR>&nbsp;<BR>[=20
X]&nbsp; General business information<BR>[ ]&nbsp; Motorola internal use =

only<BR>[ ]&nbsp; Motorola confidential=20
proprietary<BR>&nbsp;<BR></FONT></DIV></BODY></HTML>

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------------------------------

Date: Thu, 19 Jun 2003 18:41:54 -0700
From: "Jeremy Plunkett" <jeremy@serverworks.com>
Subject: RE: [IBIS-Users] RE: Vinh and Vinl definition

Hi Weston,
actually the HSTL and SSTL specifications both indicate that timing is
measured at the VREF crossing (see note 1 under table 2.2-c in the HSTL
spec).  In system simulations you may want to allow for noise on VREF by
measuring timing at the DC levels or a custom set of levels based on the
maximum expected VREF noise at the IO ring of the receiver. Measuring timing
at the AC levels would create an unnecessarily large guardband.

The purpose of the AC levels is to qualify whether an input signal has
overdriven the comparator enough to ensure that the transition is received
with accurate timing (ie acceptable propagation delay through the input
buffer).

In system simulations I measure at all 5 thresholds, which sometimes
requires adding "dummy" input buffers with no capacitance or IV curves to
capture the extra thresholds.

regards,
Jeremy




- -----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of Beal, Weston
Sent: Thursday, June 19, 2003 4:59 PM
To: 'Eric Hsu'; Ibis-Users (E-mail)
Cc: Frank Dunlap
Subject: [IBIS-Users] RE: Vinh and Vinl definition


Eric,

If you intend to use the IBIS model for timing simulation then use the (ac)
levels.  If you are going to do noise measurements then you use the (dc)
levels.  For the general case I would include two sets of Vinl and Vinh with
comments defining when to use each set.

In IBIS 4.0 you can specify all 4 levels directly in the [Receiver
Thresholds] block, but I don't know of any simulation checker that
recognizes those parameters, yet.

Regards,
Weston


>  -----Original Message-----
> From: 	Eric Hsu [mailto:ehsu@netlogicmicro.com]
> Sent:	Thursday, June 19, 2003 4:43 PM
> To:	Ibis-Users (E-mail)
> Cc:	Frank Dunlap
> Subject:	Vinh and Vinl definition
>
> Hi IBIS experts,
>
> When reading HSTL spec. of JEDEC, it define Vinh(dc) and Vinl(dc) as
Vref+/-100mV,  Vinh(ac) and Vinl(ac) as Vref+/-200mV. For ibis model, which
one it suppose to be taken?
>
> Best Regards,
>
> Eric Hsu
> Interface Technologies
> NetLogic Microsystems, Inc.
> 450 National Ave.
> Mountain View, CA 94043
> 650-961-6676 x198
> This e-mail contains NetLogic Microsystems, Inc. Confidential information
>
>
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------------------------------

Date: Fri, 20 Jun 2003 10:26:39 +0200
From: "Henrik G. Madsen" <hgm@vitesse.com>
Subject: RE: [IBIS-Users] RE: Vinh and Vinl definition

Hi,

There is actually a third option.

For single ended HSTL inputs, the HSTL standard specifies 0.75 V (Vref) as reference point for input waveform timing. Likewise VDDQ/2 for output timing.

Regards,
/Henrik

- -----Original Message-----
From: Beal, Weston [mailto:weston_beal@mentorg.com]
Sent: 20. juni 2003 01:59
To: 'Eric Hsu'; Ibis-Users (E-mail)
Cc: Frank Dunlap
Subject: [IBIS-Users] RE: Vinh and Vinl definition


Eric,

If you intend to use the IBIS model for timing simulation then use the (ac) levels.  If you are going to do noise measurements then you use the (dc) levels.  For the general case I would include two sets of Vinl and Vinh with comments defining when to use each set.

In IBIS 4.0 you can specify all 4 levels directly in the [Receiver Thresholds] block, but I don't know of any simulation checker that recognizes those parameters, yet.

Regards,
Weston


>  -----Original Message-----
> From: 	Eric Hsu [mailto:ehsu@netlogicmicro.com] 
> Sent:	Thursday, June 19, 2003 4:43 PM
> To:	Ibis-Users (E-mail)
> Cc:	Frank Dunlap
> Subject:	Vinh and Vinl definition
> 
> Hi IBIS experts,
> 
> When reading HSTL spec. of JEDEC, it define Vinh(dc) and Vinl(dc) as Vref+/-100mV,  Vinh(ac) and Vinl(ac) as Vref+/-200mV. For ibis model, which one it suppose to be taken?
> 
> Best Regards,
> 
> Eric Hsu
> Interface Technologies
> NetLogic Microsystems, Inc.
> 450 National Ave.
> Mountain View, CA 94043
> 650-961-6676 x198
> This e-mail contains NetLogic Microsystems, Inc. Confidential information
> 
> 
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Date: Fri, 20 Jun 2003 10:24:10 -0700
From: "Flora, Matthew" <matthew_flora@mentorg.com>
Subject: RE: [IBIS-Users] IBIS VMEAS and VREF Question.

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Dear Mr. Kingen,
 
As I understand the message, the currents specified in the I-V tables
of the model are simply insufficient to drop enough voltage across a
50 ohm load resistor to reach 1.5 volts at the output of the driver.
The message is meant to point out an inconsistency in the data of the
model.
 
I believe Vmeas is used only for timing measurements (so I suppose you could risk ignoring the message if you are not interested in timing simulations).  I know at least one simulator that will refuse
to run a timing simulation when the model generates that warning.
 
Best regards,
Matthew Flora
Mentor Graphics, Corp.
 
 -----Original Message-----
From: Rick Kingen [mailto:Rick.Kingen@motorola.com]
Sent: Thursday, June 19, 2003 5:28 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] IBIS VMEAS and VREF Question.



I am getting the following warning when I run my model thru the parser:
 
WARNING - Model 'I_O2': MIN VI curves cannot drive through Vmeas=1.5V
          given load Rref=50 Ohms to Vref=0V

Can anyone enlighten me as to the significance of this warning?  Will the simulator in general have a problem?  The WInIBIS data looks good.
 
Thanks in advance.
 
Rick Kingen
 
_______________________________________________
This email communication along with any attachments
is classified as:
 
[ X]  General business information
[ ]  Motorola internal use only
[ ]  Motorola confidential proprietary
 



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<DIV><FONT face="Lucida Console" size=2><SPAN class=817205116-20062003>Dear Mr. 
Kingen,</SPAN></FONT></DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN 
class=817205116-20062003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN class=817205116-20062003>As I 
understand the message, the currents specified in the I-V 
tables</SPAN></FONT></DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN class=817205116-20062003>of the 
model are simply insufficient to drop enough voltage across 
a</SPAN></FONT></DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN class=817205116-20062003>50 ohm 
load resistor to reach 1.5 volts at the output of the 
driver.</SPAN></FONT></DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN class=817205116-20062003>The 
message is meant to point out an inconsistency in the data of 
the</SPAN></FONT></DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN 
class=817205116-20062003>model.</SPAN></FONT></DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN 
class=817205116-20062003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN class=817205116-20062003>I believe 
Vmeas is used only for timing measurements (so I suppose you could risk ignoring 
the message if you are not interested in timing simulations).&nbsp; I know at 
least one simulator that will refuse</SPAN></FONT></DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN class=817205116-20062003>to run a 
timing simulation when the model generates that warning.</SPAN></FONT></DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN 
class=817205116-20062003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Lucida Console" size=2><SPAN class=817205116-20062003>Best 
regards,</SPAN></FONT></DIV>
<DIV><FONT><SPAN class=817205116-20062003></SPAN></FONT><FONT><SPAN 
class=817205116-20062003><FONT face="Lucida Console" size=2>Matthew 
Flora<BR>Mentor Graphics, Corp.<BR></FONT></SPAN></FONT><FONT face=Tahoma><FONT 
size=2><SPAN class=817205116-20062003><FONT 
face="Lucida Console">&nbsp;</FONT></SPAN></FONT></FONT></DIV>
<DIV><FONT face=Tahoma><FONT size=2><SPAN 
class=817205116-20062003>&nbsp;</SPAN>-----Original Message-----<BR><B>From:</B> 
Rick Kingen [mailto:Rick.Kingen@motorola.com]<BR><B>Sent:</B> Thursday, June 19, 
2003 5:28 PM<BR><B>To:</B> ibis-users@eda.org<BR><B>Subject:</B> [IBIS-Users] 
IBIS VMEAS and VREF Question.<BR><BR></DIV></FONT></FONT>
<BLOCKQUOTE dir=ltr 
style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
  <DIV><FONT face=Arial size=2>I am getting the following warning when I run my 
  model thru the parser:</FONT></DIV>
  <DIV><FONT face=Arial size=2></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2>WARNING - Model 'I_O2': MIN VI curves cannot 
  drive through 
  Vmeas=1.5V<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; given 
  load Rref=50 Ohms to Vref=0V<BR></FONT></DIV>
  <DIV><FONT face=Arial size=2>Can anyone enlighten me as to the significance of 
  this warning?&nbsp; Will the simulator in general have a problem?&nbsp; The 
  WInIBIS data looks good.</FONT></DIV>
  <DIV><FONT face=Arial size=2></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2>Thanks in advance.</FONT></DIV>
  <DIV><FONT face=Arial size=2></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2>Rick Kingen</FONT></DIV>
  <DIV><FONT face=Arial size=2><FONT 
  face="Lucida Console"></FONT>&nbsp;</DIV></FONT>
  <DIV><FONT face=Arial 
  size=2>_______________________________________________<BR>This email 
  communication along with any attachments<BR>is classified as:<BR>&nbsp;<BR>[ 
  X]&nbsp; General business information<BR>[ ]&nbsp; Motorola internal use 
  only<BR>[ ]&nbsp; Motorola confidential 
proprietary<BR>&nbsp;<BR></FONT></DIV></BLOCKQUOTE></BODY></HTML>

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End of ibis-users V1 #25
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