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Subject: ibis-users V1 #27
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ibis-users           Friday, August 1 2003           Volume 01 : Number 027




----------------------------------------------------------------------

Date: Fri, 11 Jul 2003 11:57:15 -0700
From: "Mirmak, Michael" <michael.mirmak@intel.com>
Subject: [IBIS-Users] BIRD82 - Clarification of Clamp Table Use CORRECTED

An early draft of BIRD82 was accidentally posted yesterday.  The correct
version is enclosed.

- - Michael Mirmak
  Intel Corp.
  Chair, EIA/IBIS Open Forum

************************************************************************
************************************************************************
                  Buffer Issue Resolution Document  (BIRD)

BIRD ID#:       82
ISSUE TITLE:    Clarification of Clamp Table Use
REQUESTOR:      Lynne Green, Cadence, and Robert Haller, SiSoft
DATE SUBMITTED: June 27, 2003
DATE ACCEPTED BY IBIS OPEN FORUM:  Pending

************************************************************************
************************************************************************

STATEMENT OF THE ISSUE:

Double-counting of clamp currents is the result of confusion over how 
the clamp currents are summed by the tools.  Model makers are often 
unsure if clamps are always active, or whether the [Power Clamp] works 
only with the [Pullup] and the [GND Clamp] only with the [Pulldown].  
This is difficult, if not impossible, to detect with a parser.

This issue can be resolved by clarification of the text under 
|    Keywords:  [Pulldown], [Pullup], [GND Clamp], [POWER Clamp]

************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

Old text:
|         It is assumed that the simulator sums the clamp tables
|         together with the appropriate [Pullup] or [Pulldown] table
|         when a buffer is driving high or low, respectively.  From this
|         assumption and the nature of 3-statable buffers, it follows
|         that the data in the clamping table sections are handled as
|         constantly present tables and the [Pullup] and [Pulldown]
|         tables are used only when needed in the simulation.

Proposed text:
|         It is assumed that the simulator will sum both clamp tables
|         (power and ground), if they exist, to the [Pullup] table when
|         the buffer is driving high. The simulator will sum both clamp
|         tables (power and ground), if they exist, to the [Pulldown]
|         table when the buffer is driving low.  The simulator will sum
|         both clamp tables when the buffer is not driving (input or
|         3-state operation).
|         It follows that the data in the clamping table sections are
|         handled as constantly present effects, while the [Pullup] and
|         [Pulldown] tables are used only when needed in the simulation.


************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Comments from members of the Quality committee, as well as others,
indicated that some models double-count clamp currents.


************************************************************************

ANY OTHER BACKGROUND INFORMATION:

Initially, it was suggested that this be detected by the parser, but
it was decided that this was too difficult.  This led to further
discussion of why double-counting occurred, and how clarification of
the spec could help address the issue.


************************************************************************


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------------------------------

Date: Tue, 15 Jul 2003 12:23:01 -0400
From: "Lynne Green" <lgreen@cadence.com>
Subject: [IBIS-Users] RE: IBIS Question

Hello, Naftali,

In the future, please post your questions to the IBIS reflector
(ibis-users@eda.org).  You will get faster replies, and from the best
experts.

As a general rule, V-t curves are used for actual simulations, while
[Ramp] values are used for analytic algorithms.

The IBIS spec recommends that V-t tables be generated without R_dut,
L_dut, and C_dut.

Best regards,
Lynne

- -----Original Message-----
From: Naftali.Refaeli@ecitele.com [mailto:Naftali.Refaeli@ecitele.com] 
Sent: Tuesday, July 15, 2003 3:28 AM
To: Lynne Green
Subject: IBIS Question



Hello Lynne.

May I ask an IBIS V-T question?

Look at the following V-T data:
|***********************************************************************
|*************************
|
[Ramp]
| variable       typ                 min                 max
dV/dt_r          1.52/0.81n          1.45/0.83n          1.56/0.81n
dV/dt_f          1.43/0.68n          1.38/0.69n          1.46/0.71n
R_load = 50.00
|
[Rising Waveform]
R_fixture = 50.00
V_fixture = 0.000
C_fixture = 10.00pF
R_dut = 4.77m
L_dut = 6.95nH
C_dut = 8.66pF
| time           V(typ)              V(min)              V(max)
|
  0.000S         0.000V              0.000V              0.000V
1.000e-10S     -42.220uV           -42.220uV           -71.850uV
  0.200nS       -0.501mV        ...

|***********************************************************************
|*************************

The IBIS  "[Ramp] dtr"  value is ~800pSec, while [Rising Waveform] shows
about 1.2nsec Rise time. This is - of course - because of loading the
I/O by C_fixture = 10.00pF, R_dut = 4.77m, L_dut = 6.95nH, C_dut =
8.66pF

But - how the simulator use the [Rising Waveform] data ?
Does the simulator calculate "real" t_rise by using both [Ramp] and V-T
table, or it presume that V-T data is more accurate for that
calculation?

(Embedded image moved to file: pic18969.pcx)

*****************************************
Naftali Refaeli
Analog & High Speed Applications.
EDS-ECI
30 Hasivim St.
Petah-Tikva 49133  Israel
Tl.     +972-3-9266973       Fax:   +972-3-9268188
*****************************************
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------------------------------

Date: Wed, 16 Jul 2003 13:52:42 -0700
From: "Angulo, John" <john_angulo@mentorg.com>
Subject: RE: [IBIS-Users] RE: IBIS Question

The following is forwarded on behalf of Syed Huq at Cisco to work around a list administration bug:

- -----Original Message-----
Some simulators may ignore the V/T Waveform tables because all the 
subparameters were not provided and use the Ramp data instead.

You need to make sure 'what' your simulator used Ramp or V/T..

Syed

>X-MimeOLE: Produced By Microsoft Exchange V6.0.6249.0
>content-class: urn:content-classes:message
>MIME-Version: 1.0
>Subject: [IBIS-Users] RE: IBIS Question
>Date: Tue, 15 Jul 2003 12:23:01 -0400
>Thread-Topic: IBIS Question
>Thread-Index: AcNKu/D/lKDAdSc9SAWNZ5w54i/dUwAL2RIQ
>From: "Lynne Green" <lgreen@cadence.com>
>To: <Naftali.Refaeli@ecitele.com>
>Cc: <ibis-users@eda.org>
>X-Received: By mailgate.Cadence.COM as JAA22630 at Tue Jul 15 09:23:02 
2003
>Content-Transfer-Encoding: 8bit
>X-MIME-Autoconverted: from quoted-printable to 8bit by server.eda.org id 
h6FGNB6O002304
>
>Hello, Naftali,
>
>In the future, please post your questions to the IBIS reflector
>(ibis-users@eda.org).  You will get faster replies, and from the best
>experts.
>
>As a general rule, V-t curves are used for actual simulations, while
>[Ramp] values are used for analytic algorithms.
>
>The IBIS spec recommends that V-t tables be generated without R_dut,
>L_dut, and C_dut.
>
>Best regards,
>Lynne
>
>-----Original Message-----
>From: Naftali.Refaeli@ecitele.com [mailto:Naftali.Refaeli@ecitele.com] 
>Sent: Tuesday, July 15, 2003 3:28 AM
>To: Lynne Green
>Subject: IBIS Question
>
>
>
>Hello Lynne.
>
>May I ask an IBIS V-T question?
>
>Look at the following V-T data:
>|***********************************************************************
>|*************************
>|
>[Ramp]
>| variable       typ                 min                 max
>dV/dt_r          1.52/0.81n          1.45/0.83n          1.56/0.81n
>dV/dt_f          1.43/0.68n          1.38/0.69n          1.46/0.71n
>R_load = 50.00
>|
>[Rising Waveform]
>R_fixture = 50.00
>V_fixture = 0.000
>C_fixture = 10.00pF
>R_dut = 4.77m
>L_dut = 6.95nH
>C_dut = 8.66pF
>| time           V(typ)              V(min)              V(max)
>|
>  0.000S         0.000V              0.000V              0.000V
>1.000e-10S     -42.220uV           -42.220uV           -71.850uV
>  0.200nS       -0.501mV        ...
>
>|***********************************************************************
>|*************************
>
>The IBIS  "[Ramp] dtr"  value is ~800pSec, while [Rising Waveform] shows
>about 1.2nsec Rise time. This is - of course - because of loading the
>I/O by C_fixture = 10.00pF, R_dut = 4.77m, L_dut = 6.95nH, C_dut =
>8.66pF
>
>But - how the simulator use the [Rising Waveform] data ?
>Does the simulator calculate "real" t_rise by using both [Ramp] and V-T
>table, or it presume that V-T data is more accurate for that
>calculation?
>
>(Embedded image moved to file: pic18969.pcx)
>
>*****************************************
>Naftali Refaeli
>Analog & High Speed Applications.
>EDS-ECI
>30 Hasivim St.
>Petah-Tikva 49133  Israel
>Tl.     +972-3-9266973       Fax:   +972-3-9268188
>*****************************************
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------------------------------

Date: Wed, 16 Jul 2003 14:37:55 -0700
From: "Duane Mattheisen" <duane.mattheisen@onsemi.com>
Subject: Re: [IBIS-Users] RE: IBIS Question

Also some simulators may ignore the V/T Wave form tables if the "min,
Typ and max" timing delays are not in the slowest to fastest order. 
Thanks Duane M

"Angulo, John" wrote:
> 
> The following is forwarded on behalf of Syed Huq at Cisco to work around a list administration bug:
> 
> -----Original Message-----
> Some simulators may ignore the V/T Waveform tables because all the
> subparameters were not provided and use the Ramp data instead.
> 
> You need to make sure 'what' your simulator used Ramp or V/T..
> 
> Syed
> 
> >X-MimeOLE: Produced By Microsoft Exchange V6.0.6249.0
> >content-class: urn:content-classes:message
> >MIME-Version: 1.0
> >Subject: [IBIS-Users] RE: IBIS Question
> >Date: Tue, 15 Jul 2003 12:23:01 -0400
> >Thread-Topic: IBIS Question
> >Thread-Index: AcNKu/D/lKDAdSc9SAWNZ5w54i/dUwAL2RIQ
> >From: "Lynne Green" <lgreen@cadence.com>
> >To: <Naftali.Refaeli@ecitele.com>
> >Cc: <ibis-users@eda.org>
> >X-Received: By mailgate.Cadence.COM as JAA22630 at Tue Jul 15 09:23:02
> 2003
> >Content-Transfer-Encoding: 8bit
> >X-MIME-Autoconverted: from quoted-printable to 8bit by server.eda.org id
> h6FGNB6O002304
> >
> >Hello, Naftali,
> >
> >In the future, please post your questions to the IBIS reflector
> >(ibis-users@eda.org).  You will get faster replies, and from the best
> >experts.
> >
> >As a general rule, V-t curves are used for actual simulations, while
> >[Ramp] values are used for analytic algorithms.
> >
> >The IBIS spec recommends that V-t tables be generated without R_dut,
> >L_dut, and C_dut.
> >
> >Best regards,
> >Lynne
> >
> >-----Original Message-----
> >From: Naftali.Refaeli@ecitele.com [mailto:Naftali.Refaeli@ecitele.com]
> >Sent: Tuesday, July 15, 2003 3:28 AM
> >To: Lynne Green
> >Subject: IBIS Question
> >
> >
> >
> >Hello Lynne.
> >
> >May I ask an IBIS V-T question?
> >
> >Look at the following V-T data:
> >|***********************************************************************
> >|*************************
> >|
> >[Ramp]
> >| variable       typ                 min                 max
> >dV/dt_r          1.52/0.81n          1.45/0.83n          1.56/0.81n
> >dV/dt_f          1.43/0.68n          1.38/0.69n          1.46/0.71n
> >R_load = 50.00
> >|
> >[Rising Waveform]
> >R_fixture = 50.00
> >V_fixture = 0.000
> >C_fixture = 10.00pF
> >R_dut = 4.77m
> >L_dut = 6.95nH
> >C_dut = 8.66pF
> >| time           V(typ)              V(min)              V(max)
> >|
> >  0.000S         0.000V              0.000V              0.000V
> >1.000e-10S     -42.220uV           -42.220uV           -71.850uV
> >  0.200nS       -0.501mV        ...
> >
> >|***********************************************************************
> >|*************************
> >
> >The IBIS  "[Ramp] dtr"  value is ~800pSec, while [Rising Waveform] shows
> >about 1.2nsec Rise time. This is - of course - because of loading the
> >I/O by C_fixture = 10.00pF, R_dut = 4.77m, L_dut = 6.95nH, C_dut =
> >8.66pF
> >
> >But - how the simulator use the [Rising Waveform] data ?
> >Does the simulator calculate "real" t_rise by using both [Ramp] and V-T
> >table, or it presume that V-T data is more accurate for that
> >calculation?
> >
> >(Embedded image moved to file: pic18969.pcx)
> >
> >*****************************************
> >Naftali Refaeli
> >Analog & High Speed Applications.
> >EDS-ECI
> >30 Hasivim St.
> >Petah-Tikva 49133  Israel
> >Tl.     +972-3-9266973       Fax:   +972-3-9268188
> >*****************************************
> >|------------------------------------------------------------------
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------------------------------

Date: Fri, 18 Jul 2003 01:02:07 -0700 (PDT)
From: sk <wsk78@yahoo.com>
Subject: [IBIS-Users] IBIS Models & Device Speed Grade

Hi all,

Apart from doing lab measurement, are there any other
ways of generating IBIS models for each device speed
grade (slow, typical and fast)? 
I don't think Spice extraction can do this since speed
grades are only determined after fabrication. (Please
correct me if I'm wrong)

Any comments are welcome and appreciated.

Thanks

__________________________________
Do you Yahoo!?
SBC Yahoo! DSL - Now only $29.95 per month!
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------------------------------

Date: Fri, 18 Jul 2003 13:50:46 +0530
From: akhilesh.chandra@st.com
Subject: [IBIS-Users] IBIS Models & Device Speed Grade

Hello All,
           I am going to generate IBIS model of LVDS cell with terminated
resitence of 100ohm.
  Can any one of you guide how I will put information of two pad in my
models and what setup is required to make simulation. If you have some
document it help me a lot.

With Best Regards
Akhilesh

> Hi all,
> 
> Apart from doing lab measurement, are there any other
> ways of generating IBIS models for each device speed
> grade (slow, typical and fast)? 
> I don't think Spice extraction can do this since speed
> grades are only determined after fabrication. (Please
> correct me if I'm wrong)
> 
> Any comments are welcome and appreciated.
> 
> Thanks
> 
> __________________________________
> Do you Yahoo!?
> SBC Yahoo! DSL - Now only $29.95 per month!
> http://sbc.yahoo.com
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------------------------------

Date: Fri, 18 Jul 2003 13:58:16 +0530
From: akhilesh.chandra@st.com
Subject: [IBIS-Users] IBIS Model of LVDS cell

Hello All,
           I am going to generate IBIS model of LVDS cell with terminated
resitence of 100ohm.
  Can any one of you guide how I will put information of two pad in my
models and what setup is required to make simulation. If you have some
document it help me a lot.

Please discard my last mail.

With Best Regards
Akhilesh
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------------------------------

Date: Fri, 18 Jul 2003 18:45:37 +0530
From: Anshuli Goel <anshuli@ti.com>
Subject: [IBIS-Users] C-Comp

Hello Experts

I have one naive question.
While defining the C_Comp we say "C_comp defines the silicon  die
capacitance. This value should not include capacitance of
  the package.The C_comp capacitance must represent what you see when you
look into the die at the die pad. This includes the die pad, metal
connections  on the die, the driver transistor's capacitance, the  receiver
(input)capacitance, everything that is on the die."

But my understanding is that anyway the netlist is going to have driver
transistors in it in case of buffers, why do we need to account for the
capacitance for driver transistors ?? I can understand about the metal
connection and bond pad capacitance ,but I am not able to understand the
Transistors Capacitance part of it . Please clarify.

Regards
Anshuli


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------------------------------

Date: Fri, 18 Jul 2003 16:40:50 +0300
From: "hazem" <hazem@qualim.com>
Subject: RE: [IBIS-Users] C-Comp

Well, that's a good question!!
Driver output stage usually has large size transistors for driving
current capabilities. The drain-bulk capacitance of such transistors can
reach few Pico Farads in some cases. Never the less, transistor
capacitance also varies in a nonlinear way with drain/source/gate
voltage which make C-comp very critical parameter to model.
I hope this will help...
BR,
Hazem Hegazy

- -----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Anshuli Goel
Sent: Friday, July 18, 2003 4:16 PM
To: 'ibis-users@eda.org'
Subject: [IBIS-Users] C-Comp

Hello Experts

I have one naive question.
While defining the C_Comp we say "C_comp defines the silicon  die
capacitance. This value should not include capacitance of
  the package.The C_comp capacitance must represent what you see when
you
look into the die at the die pad. This includes the die pad, metal
connections  on the die, the driver transistor's capacitance, the
receiver
(input)capacitance, everything that is on the die."

But my understanding is that anyway the netlist is going to have driver
transistors in it in case of buffers, why do we need to account for the
capacitance for driver transistors ?? I can understand about the metal
connection and bond pad capacitance ,but I am not able to understand the
Transistors Capacitance part of it . Please clarify.

Regards
Anshuli


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------------------------------

Date: Fri, 18 Jul 2003 08:06:12 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] C-Comp

That is because the IV curves do not exhibit any capacitive
behavior, they are only DC.  In order to put the capacitive
effects into the IBIS model we need to add a capacitance to
the IV curves.

Arpad Muranyi
Intel Corporation
===========================================================

- -----Original Message-----
From: Anshuli Goel [mailto:anshuli@ti.com]
Sent: Friday, July 18, 2003 6:16 AM
To: 'ibis-users@eda.org'
Subject: [IBIS-Users] C-Comp


Hello Experts

I have one naive question.
While defining the C_Comp we say "C_comp defines the silicon  die
capacitance. This value should not include capacitance of
  the package.The C_comp capacitance must represent what you see when you
look into the die at the die pad. This includes the die pad, metal
connections  on the die, the driver transistor's capacitance, the  receiver
(input)capacitance, everything that is on the die."

But my understanding is that anyway the netlist is going to have driver
transistors in it in case of buffers, why do we need to account for the
capacitance for driver transistors ?? I can understand about the metal
connection and bond pad capacitance ,but I am not able to understand the
Transistors Capacitance part of it . Please clarify.

Regards
Anshuli


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------------------------------

Date: Fri, 18 Jul 2003 10:38:04 -0500
From: "Roy Leventhal" <Roy.Leventhal@ieee.org>
Subject: RE: [IBIS-Users] C-Comp

Anshuli,

Be aware that capacitive behavior is included in the V-T behavioral curves
and/or the slew rates based on them. Unsophisticated providers of simulation
software (hopefully, few remain) can thus mistakenly "double count" the
effects of Ccomp unless they adjust for its presence in the circuit.

So, why is Ccomp included? To account for the capacitive loading on the
circuit, direct or reflected wave, and it is the total capacitive loading
looking into the die pad.


Best Regards,

Roy

- -----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of Anshuli Goel
Sent: Friday, July 18, 2003 8:16 AM
To: 'ibis-users@eda.org'
Subject: [IBIS-Users] C-Comp


Hello Experts

I have one naive question.
While defining the C_Comp we say "C_comp defines the silicon  die
capacitance. This value should not include capacitance of
  the package.The C_comp capacitance must represent what you see when you
look into the die at the die pad. This includes the die pad, metal
connections  on the die, the driver transistor's capacitance, the  receiver
(input)capacitance, everything that is on the die."

But my understanding is that anyway the netlist is going to have driver
transistors in it in case of buffers, why do we need to account for the
capacitance for driver transistors ?? I can understand about the metal
connection and bond pad capacitance ,but I am not able to understand the
Transistors Capacitance part of it . Please clarify.

Regards
Anshuli


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------------------------------

Date: Fri, 18 Jul 2003 13:10:03 -0400
From: Robert Haller <rhaller@sisoft.com>
Subject: Re: [IBIS-Users] C-Comp

IBIS users,

At today's IBIS open forum call, the issue was raised concerning the 
limitations of Ccomp in the present IBIS spec. This issue is being added 
to the next ibis open forum agenda technical discussion.

I would like to solicit feedback from Model developers and users for 
proposed changes, as well as voice my own opinion.

Present syntax

|      typ     min     max
|
C_comp 3.90pF  3.10pF  4.80pF

My personal experience has shown that I/O buffer often have different 
C_comp when driving and receiving. To keep things simple, I would 
suggest that a simple extension to the C_comp would be to specify a 
C_comp driving and C_comp receiving for  Model_type = I/O

regards,
bob
- -- 
Robert J. Haller (rhaller@sisoft.com)
Principal Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 15



Roy Leventhal wrote:
> Anshuli,
> 
> Be aware that capacitive behavior is included in the V-T behavioral curves
> and/or the slew rates based on them. Unsophisticated providers of simulation
> software (hopefully, few remain) can thus mistakenly "double count" the
> effects of Ccomp unless they adjust for its presence in the circuit.
> 
> So, why is Ccomp included? To account for the capacitive loading on the
> circuit, direct or reflected wave, and it is the total capacitive loading
> looking into the die pad.
> 
> 
> Best Regards,
> 
> Roy
> 


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------------------------------

Date: Fri, 18 Jul 2003 13:30:51 -0700
From: Kim Helliwell <kimgh@apple.com>
Subject: Re: [IBIS-Users] C-Comp

I'm just curious how this would be folded in with the 4-part C_comp
(BIRD 76.1). Will we end up with 2 (or even 4) more C_comp
values? Or does just 1 value adequately characterize the
receiver?



Kim


On Friday, July 18, 2003, at 10:10  AM, Robert Haller wrote:

> IBIS users,
>
> At today's IBIS open forum call, the issue was raised concerning the 
> limitations of Ccomp in the present IBIS spec. This issue is being 
> added to the next ibis open forum agenda technical discussion.
>
> I would like to solicit feedback from Model developers and users for 
> proposed changes, as well as voice my own opinion.
>
> Present syntax
>
> |      typ     min     max
> |
> C_comp 3.90pF  3.10pF  4.80pF
>
> My personal experience has shown that I/O buffer often have different 
> C_comp when driving and receiving. To keep things simple, I would 
> suggest that a simple extension to the C_comp would be to specify a 
> C_comp driving and C_comp receiving for  Model_type = I/O
>
> regards,
> bob
> -- 
> Robert J. Haller (rhaller@sisoft.com)
> Principal Consultant
> Signal Integrity Software Inc.
> 6 Clock Tower Place, Suite 250
> Maynard, MA 01754
> Phone: (978) 461-0449, ext 15
>
>
>
> Roy Leventhal wrote:
>> Anshuli,
>> Be aware that capacitive behavior is included in the V-T behavioral 
>> curves
>> and/or the slew rates based on them. Unsophisticated providers of 
>> simulation
>> software (hopefully, few remain) can thus mistakenly "double count" 
>> the
>> effects of Ccomp unless they adjust for its presence in the circuit.
>> So, why is Ccomp included? To account for the capacitive loading on 
>> the
>> circuit, direct or reflected wave, and it is the total capacitive 
>> loading
>> looking into the die pad.
>> Best Regards,
>> Roy
>
>
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>
Kim Helliwell
Apple Computer
kimgh@apple.com
408 974 9936

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------------------------------

Date: Sat, 19 Jul 2003 16:22:52 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] Diff Pin Question

Andis,

I don't remember seeing a response to your posting, so here is mine.
(Sorry for the delay).

You can use a negative number for the delay to describe that the
second pin (inverting output) is switching earlier than the first
pin (non-inverting output).  If the delay value is positive, the
inverting output is switching later by that amount.

Arpad Muranyi
Intel Corporation
==================================================================

- -----Original Message-----
From: Lauzums, Andris [mailto:ALAUZUMS@intersil.com] 
Sent: Thursday, June 26, 2003 10:49 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Diff Pin Question


	
Hello-

I had a question about the [Diff_Pin] parameter in the IBIS
specification.  In reference to t_delay, (min, typ, and max), where my
non-inverting ouput is output A, and my inverting output is B, I am
unclear about the following:

Does a positive (as opposed to negative) value in the t_delay column
mean that A occurs after B, or that B occurs after A?  I have read the
IBIS specification for this parameter, and it states that "(t-delay
contains) launch delays of the non-inverting pins relative to the
inverting pins.  The values can be of either polarity".  It does not
seem to specify which way is positive, and which way is negative.  This
is the source of my confusion.

Thank you for the help-

Andris Lauzums
Intersil Corporation
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------------------------------

Date: Mon, 21 Jul 2003 14:49:29 +0530
From: Anshuli Goel <anshuli@ti.com>
Subject: Re: [IBIS-Users] C-Comp

Arpad

As far as I understand the C_comp value is not taken into account for IV curve
calculation , it is only added in the calculation in VT curve , so while
calculating VT curve we already have capacitance , why do we need to put
C_Comp ??

Anshuli
"Muranyi, Arpad" wrote:

> That is because the IV curves do not exhibit any capacitive
> behavior, they are only DC.  In order to put the capacitive
> effects into the IBIS model we need to add a capacitance to
> the IV curves.
>
> Arpad Muranyi
> Intel Corporation
> ===========================================================
>
> -----Original Message-----
> From: Anshuli Goel [mailto:anshuli@ti.com]
> Sent: Friday, July 18, 2003 6:16 AM
> To: 'ibis-users@eda.org'
> Subject: [IBIS-Users] C-Comp
>
> Hello Experts
>
> I have one naive question.
> While defining the C_Comp we say "C_comp defines the silicon  die
> capacitance. This value should not include capacitance of
>   the package.The C_comp capacitance must represent what you see when you
> look into the die at the die pad. This includes the die pad, metal
> connections  on the die, the driver transistor's capacitance, the  receiver
> (input)capacitance, everything that is on the die."
>
> But my understanding is that anyway the netlist is going to have driver
> transistors in it in case of buffers, why do we need to account for the
> capacitance for driver transistors ?? I can understand about the metal
> connection and bond pad capacitance ,but I am not able to understand the
> Transistors Capacitance part of it . Please clarify.
>
> Regards
> Anshuli
>
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------------------------------

Date: Mon, 21 Jul 2003 15:10:25 +0530
From: "Birendra Rana" <birendra.rana@wipro.com>
Subject: RE: [IBIS-Users] C-Comp

Hi Anshuli,

The C_comp parameter is a bit confusing at first but I hope this
explanation will set it right :

The C_comp parameter tells the simulator what capacitance it should
expect when looking "into" the model. The tables in the IBIS model
wouldn't have that Info. To get the feel of the C_comp parameter try
simulating a I/O buffer IBIS model with a transmission line with a
termination resistor and a capacitive load. Take the IBIS model with
C_comp = 0 pF and other case with C_comp = some value. You will see the
difference in the waveforms as reflected output signal will encounter
this 'capacitance' of the buffer in the second case.

Hope this clears.

Birendra

- -----Original Message-----
From: Anshuli Goel [mailto:anshuli@ti.com] 
Sent: Monday, 21 July 2003 2:49 PM
To: Muranyi, Arpad; 'ibis-users@eda.org'
Subject: Re: [IBIS-Users] C-Comp


Arpad

As far as I understand the C_comp value is not taken into account for IV
curve calculation , it is only added in the calculation in VT curve , so
while calculating VT curve we already have capacitance , why do we need
to put C_Comp ??

Anshuli
"Muranyi, Arpad" wrote:

> That is because the IV curves do not exhibit any capacitive behavior, 
> they are only DC.  In order to put the capacitive effects into the 
> IBIS model we need to add a capacitance to the IV curves.
>
> Arpad Muranyi
> Intel Corporation 
> ===========================================================
>
> -----Original Message-----
> From: Anshuli Goel [mailto:anshuli@ti.com]
> Sent: Friday, July 18, 2003 6:16 AM
> To: 'ibis-users@eda.org'
> Subject: [IBIS-Users] C-Comp
>
> Hello Experts
>
> I have one naive question.
> While defining the C_Comp we say "C_comp defines the silicon  die 
> capacitance. This value should not include capacitance of
>   the package.The C_comp capacitance must represent what you see when 
> you look into the die at the die pad. This includes the die pad, metal

> connections  on the die, the driver transistor's capacitance, the  
> receiver (input)capacitance, everything that is on the die."
>
> But my understanding is that anyway the netlist is going to have 
> driver transistors in it in case of buffers, why do we need to account

> for the capacitance for driver transistors ?? I can understand about 
> the metal connection and bond pad capacitance ,but I am not able to 
> understand the Transistors Capacitance part of it . Please clarify.
>
> Regards
> Anshuli
>
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------------------------------

Date: Mon, 21 Jul 2003 02:40:39 -0700 (PDT)
From: hazem@qualim.com
Subject: Re: [IBIS-Users] C-Comp

Anshuli,
The v-t tables contain the c_comp behavior but at
certain loading conditions (50 Ohm to GND/VDD). We need
to tell the simulator the c_comp value in order to
update the internal differential equations with the
term c *di/dt at different loading conditions.
You can try this by setting C_comp to zero and try to
get the 50 Ohm to GND/VDD from the IBIS simulator. You
will get exactly the correct wave form versus SPICE.
Another trial is to set C_comp to zero and try to
simulate the buffer at 100 Ohm to VDD for example and
compare it with spice. You will get bad correlation
even with this simple load. On the other hand, if you
used the correct C_comp value you will get excellent
correlation even with very harsh loading conditions.
I also recommend to read this presentation as in the
first pages it demonstrate the importance of C_comp in
time response domain:

http://www.eda.org/pub/ibis/summits/jun02/hegazy.pdf

BR,


On Mon, 21 Jul 2003 14:49:29 +0530, Anshuli Goel wrote:

> 
> Arpad
> 
> As far as I understand the C_comp value is not taken
> into account for IV curve
> calculation , it is only added in the calculation in
VT
> curve , so while
> calculating VT curve we already have capacitance , why
> do we need to put
> C_Comp ??
> 
> Anshuli
> "Muranyi, Arpad" wrote:
> 
> > That is because the IV curves do not exhibit any
> capacitive
> > behavior, they are only DC.  In order to put the
> capacitive
> > effects into the IBIS model we need to add a
> capacitance to
> > the IV curves.
> >
> > Arpad Muranyi
> > Intel Corporation
> >
>
===========================================================
> >
> > -----Original Message-----
> > From: Anshuli Goel [mailto:anshuli@ti.com]
> > Sent: Friday, July 18, 2003 6:16 AM
> > To: 'ibis-users@eda.org'
> > Subject: [IBIS-Users] C-Comp
> >
> > Hello Experts
> >
> > I have one naive question.
> > While defining the C_Comp we say "C_comp defines the
> silicon  die
> > capacitance. This value should not include
> capacitance of
> >   the package.The C_comp capacitance must represent
> what you see when you
> > look into the die at the die pad. This includes the
> die pad, metal
> > connections  on the die, the driver transistor's
> capacitance, the  receiver
> > (input)capacitance, everything that is on the die."
> >
> > But my understanding is that anyway the netlist is
> going to have driver
> > transistors in it in case of buffers, why do we need
> to account for the
> > capacitance for driver transistors ?? I can
> understand about the metal
> > connection and bond pad capacitance ,but I am not
> able to understand the
> > Transistors Capacitance part of it . Please clarify.
> >
> > Regards
> > Anshuli
> >
> >
>
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Hazem Hegazy 
Tel: +20(2)4043350 
Mobile: +20(10) 6052154 
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------------------------------

Date: Mon, 21 Jul 2003 13:05:28 +0200
From: erik.van.der.ven@philips.com
Subject: RE: [IBIS-Users] Diff Pin Question

This is a multipart message in MIME format.
- --=_alternative 003D22B1C1256D6A_=
Content-Type: text/plain; charset="us-ascii"

The delay time is not implemented in Hyperlynx. Does anyone know if this 
feature is implemented in other IBIS simulators? Does anyone have an idea 
to what extend the more "advanced" keywords are implemented well by 
simulators (otherwise it is useless to make dedicated IBIS models).

With kind regards,

Ir. Erik van der Ven
Room DB1032
Business Line Networking Infrastructure
Philips Semiconductors BV
Gerstweg 2
6534 AE Nijmegen
The Netherlands
Phone: +31-24-3534334









"Muranyi, Arpad" <arpad.muranyi@intel.com>
Sent by: 
owner-ibis-users@eda.org
07/20/03 01:22 AM

 
        To:     <ibis-users@eda.org>
        cc:     (bcc: Erik van der Ven/NYM/SC/PHILIPS)
        Subject:        RE: [IBIS-Users] Diff Pin Question
        Classification: 



Andis,

I don't remember seeing a response to your posting, so here is mine.
(Sorry for the delay).

You can use a negative number for the delay to describe that the
second pin (inverting output) is switching earlier than the first
pin (non-inverting output).  If the delay value is positive, the
inverting output is switching later by that amount.

Arpad Muranyi
Intel Corporation
==================================================================

- -----Original Message-----
From: Lauzums, Andris [mailto:ALAUZUMS@intersil.com] 
Sent: Thursday, June 26, 2003 10:49 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Diff Pin Question


 
Hello-

I had a question about the [Diff_Pin] parameter in the IBIS
specification.  In reference to t_delay, (min, typ, and max), where my
non-inverting ouput is output A, and my inverting output is B, I am
unclear about the following:

Does a positive (as opposed to negative) value in the t_delay column
mean that A occurs after B, or that B occurs after A?  I have read the
IBIS specification for this parameter, and it states that "(t-delay
contains) launch delays of the non-inverting pins relative to the
inverting pins.  The values can be of either polarity".  It does not
seem to specify which way is positive, and which way is negative.  This
is the source of my confusion.

Thank you for the help-

Andris Lauzums
Intersil Corporation
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- --=_alternative 003D22B1C1256D6A_=
Content-Type: text/html; charset="us-ascii"


<br><font size=2 face="sans-serif">The delay time is not implemented in Hyperlynx. Does anyone know if this feature is implemented in other IBIS simulators? Does anyone have an idea to what extend the more &quot;advanced&quot; keywords are implemented well by simulators (otherwise it is useless to make dedicated IBIS models).</font>
<br>
<br><font size=2 face="sans-serif">With kind regards,</font>
<br><font size=2 face="sans-serif"><br>
Ir. Erik van der Ven<br>
Room DB1032<br>
Business Line Networking Infrastructure<br>
Philips Semiconductors BV<br>
Gerstweg 2<br>
6534 AE Nijmegen<br>
The Netherlands<br>
Phone: +31-24-3534334</font>
<br>
<br>
<br>
<table width=100%>
<tr valign=top>
<td>
<td>
<br>
<br>
<br>
<br>
<br><font size=1 face="sans-serif"><b>&quot;Muranyi, Arpad&quot; &lt;arpad.muranyi@intel.com&gt;</b></font>
<p><font size=1 face="sans-serif">Sent by: </font>
<br><font size=1 face="sans-serif">owner-ibis-users@eda.org</font>
<p><font size=1 face="sans-serif">07/20/03 01:22 AM</font>
<br>
<td><font size=1 face="Arial">&nbsp; &nbsp; &nbsp; &nbsp; </font>
<br><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; To: &nbsp; &nbsp; &nbsp; &nbsp;&lt;ibis-users@eda.org&gt;</font>
<br><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; cc: &nbsp; &nbsp; &nbsp; &nbsp;(bcc: Erik van der Ven/NYM/SC/PHILIPS)</font>
<br><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; Subject: &nbsp; &nbsp; &nbsp; &nbsp;RE: [IBIS-Users] Diff Pin Question</font>
<p><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; Classification: &nbsp; &nbsp; &nbsp; &nbsp;</font>
<br></table>
<br>
<br>
<br><font size=2 face="Courier New">Andis,<br>
<br>
I don't remember seeing a response to your posting, so here is mine.<br>
(Sorry for the delay).<br>
<br>
You can use a negative number for the delay to describe that the<br>
second pin (inverting output) is switching earlier than the first<br>
pin (non-inverting output). &nbsp;If the delay value is positive, the<br>
inverting output is switching later by that amount.<br>
<br>
Arpad Muranyi<br>
Intel Corporation<br>
==================================================================<br>
<br>
- -----Original Message-----<br>
From: Lauzums, Andris [mailto:ALAUZUMS@intersil.com] <br>
Sent: Thursday, June 26, 2003 10:49 AM<br>
To: ibis-users@eda.org<br>
Subject: [IBIS-Users] Diff Pin Question<br>
<br>
<br>
 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <br>
Hello-<br>
<br>
I had a question about the [Diff_Pin] parameter in the IBIS<br>
specification. &nbsp;In reference to t_delay, (min, typ, and max), where my<br>
non-inverting ouput is output A, and my inverting output is B, I am<br>
unclear about the following:<br>
<br>
Does a positive (as opposed to negative) value in the t_delay column<br>
mean that A occurs after B, or that B occurs after A? &nbsp;I have read the<br>
IBIS specification for this parameter, and it states that &quot;(t-delay<br>
contains) launch delays of the non-inverting pins relative to the<br>
inverting pins. &nbsp;The values can be of either polarity&quot;. &nbsp;It does not<br>
seem to specify which way is positive, and which way is negative. &nbsp;This<br>
is the source of my confusion.<br>
<br>
Thank you for the help-<br>
<br>
Andris Lauzums<br>
Intersil Corporation<br>
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------------------------------

Date: Mon, 21 Jul 2003 15:52:07 -0400
From: "Ingraham, Andrew" <a.ingraham@ieee.org>
Subject: Re: [IBIS-Users] IBIS Models & Device Speed Grade

> Apart from doing lab measurement, are there any other
> ways of generating IBIS models for each device speed
> grade (slow, typical and fast)?


> I don't think Spice extraction can do this since speed
> grades are only determined after fabrication. (Please
> correct me if I'm wrong)

That depends.  I have used SPICE models created well before fabrication,
that represented weak, typ, and strong process corners.

One could also argue that even Typical SPICE models are inaccurate (and
therefore unavailable) before fabrication.  All are extrapolations based on
expectations, and all can be expected to change over time.  A good fab house
should have some idea of what their process variations will be, based on
past history.

I have also seen suggestions to take the typical curves (or typical SPICE
model) and scale them by some percentage to get the weak/strong corners.
No, it isn't very scientific.  But scaling a well developed process ought to
be reasonably predictable so that such extrapolations tend to work much of
the time.  Still, exceptions happen.

Regards,
Andy



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------------------------------

Date: Mon, 21 Jul 2003 14:08:14 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] C-Comp

Anshuli,

The Vt curves include the effect of C_comp, but it needs to be
compensated out if there is an extra capacitance in the IBIS model
to account for C_comp.  However, the C_comp capacitor must be
there so that when you look into the buffer you would see that
capacitance.  The fact that the Vt curve has the effect of
C_comp does not mean that looking into the buffer you see that
capacitance, it only means that the curve is slower than it would
be without the capacitive effects.

In short, the C_comp is there to make the capacitive effects visible
to the rest of the circuit, but the compensation inside the buffer
is done to avoid double counting for it in the shape of the waveforms.

Arpad
======================================================================

- -----Original Message-----
From: Anshuli Goel [mailto:anshuli@ti.com]
Sent: Monday, July 21, 2003 2:19 AM
To: Muranyi, Arpad; 'ibis-users@eda.org'
Subject: Re: [IBIS-Users] C-Comp


Arpad

As far as I understand the C_comp value is not taken into account for IV curve
calculation , it is only added in the calculation in VT curve , so while
calculating VT curve we already have capacitance , why do we need to put
C_Comp ??

Anshuli
"Muranyi, Arpad" wrote:

> That is because the IV curves do not exhibit any capacitive
> behavior, they are only DC.  In order to put the capacitive
> effects into the IBIS model we need to add a capacitance to
> the IV curves.
>
> Arpad Muranyi
> Intel Corporation
> ===========================================================
>
> -----Original Message-----
> From: Anshuli Goel [mailto:anshuli@ti.com]
> Sent: Friday, July 18, 2003 6:16 AM
> To: 'ibis-users@eda.org'
> Subject: [IBIS-Users] C-Comp
>
> Hello Experts
>
> I have one naive question.
> While defining the C_Comp we say "C_comp defines the silicon  die
> capacitance. This value should not include capacitance of
>   the package.The C_comp capacitance must represent what you see when you
> look into the die at the die pad. This includes the die pad, metal
> connections  on the die, the driver transistor's capacitance, the  receiver
> (input)capacitance, everything that is on the die."
>
> But my understanding is that anyway the netlist is going to have driver
> transistors in it in case of buffers, why do we need to account for the
> capacitance for driver transistors ?? I can understand about the metal
> connection and bond pad capacitance ,but I am not able to understand the
> Transistors Capacitance part of it . Please clarify.
>
> Regards
> Anshuli
>
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Tue, 22 Jul 2003 17:24:27 -0400
From: "Lynne Green" <lgreen@cadence.com>
Subject: [IBIS-Users] SPICE to IBIS Methodology webinar

The webinar on SPICE to IBIS Methodology, presented last week by Lynne
Green, Cadence, with help from Arpad Muranyi, has generated many
positive comments, along with many requests for file information.  The
SPICE to IBIS demo files that Arpad mentioned from his IBIS training
class are downloadable from
http://www.eda.org/pub/ibis/training/IBIS_class_JEDEC.zip.

If you missed the live webinar, you can register to view the archived
webinar at
http://www.cadencepcb.com/webinar/SpiceToIbis/frmSpiceToIbis.asp.

We are in the process of preparing for a second SPICE to IBIS webinar
with Lynne and Arpad, focusing on differential buffers.   If you are a
registered member of the Signal Integrity community at specctraquest.com
you will receive notification of upcoming webinars.  Register at
http://www.specctraquest.com.

All webinars are open to everyone, and are offered at no charge.

Sincerely,
Lynne Green
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------------------------------

Date: Wed, 23 Jul 2003 16:14:32 -0600
From: rrwolff@micron.com
Subject: [IBIS-Users] [IBIS] Open forum minutes (07/18/03)

DATE: 7/23/03

SUBJECT: July 18, 2003 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2003 PARTICIPANTS LIST:
Ansoft Corporation             (Eric Bracken)
Apple Computer                 Kim Helliwell
Applied Simulation Technology  Fred Balistreri
Cadence Design Systems         Lynne Green*, Lance Wang
Cisco Systems                  Syed Huq*, Michael LaBonte,
                               Val Mandruson, Hung Pham,
                               Todd Westerhoff
Fairchild Semiconductor        (Graham Connolly)
Hitachi ULSI Systems           Kazuyoshi Shoji
Intel Corporation              Stephen Peters*, Michael Mirmak*,
                               Arpad Muranyi*, Eric Magnusson
LSI Logic                      Frank Gasparik*
Matsushita (Panasonic)         Atsuji Ito
Mentor Graphics                [Bob Ross], Ian Dodd*, Guy de Burgh*,
                               John Angulo*, Mike Donnelly, Weston Beal 
Micron Technology              Randy Wolff*
Molex Incorporated             Gus Panella
Motorola                       (Rick Kingen)
National Semiconductor         [Milt Schwartz], [Tim Coyle]
NEC Electric Corporation       (Itsuki Yamada)
Philips Semiconductor          (D.C. Sessions), Stephanie Goedecke
Siemens (& Automotive) AG      Eckhard Lenski, Michael Kindij, 
                               Burkhard Muller, Katja Koller, 
                               Andre Goerisch, Manfred Maurer, 
                               Bernard Unger, Amir Motamedi, 
                               Hartmut Ibowski, Gerald Bannert
Signal Integrity Software      Bob Haller*, Barry Katz, Doug Burns
Sigrity                        [Raj Raghuram]
Synopsys                       Warren Wong, Edmund Cheng
Texas Instruments              Thomas Fisher
Teraspeed                      Scott McMorrow, Tom Dagostino,
                               Kevin Simpson, Bob Ross*
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Zuken (& Incases)              Michael Schaeder, Ralf Bruening

OTHER PARTICIPANTS IN 2003:
Agilent Technologies           Herbert Lage
Brocade                        Frank Yuan, Yongrue Yu
Conexant                       Gary Felker
EADS CCR                       Alix de la Villeguerin
EFM                            Ekkehard Miersch
EMC Corporation                Brian Arsenault, John Fernandez,
                               Simba Julian
Fraunhofer IZM                 Ege Engin
Fujitsu                        Tadashi Arai
GEIA                           (Chris Denham)
Huawei Technologies            (Jiang Xiang Zhong)
Independent                    Kelly Green, Luca Giacotto
Infineon Tech AG               Christian Sporrer
Marvell Semiconductor          Itzik Peleg
NetLogic Microsystems          Eric Hsu
North East Systems Associates  Edward Sayre 
Plexus                         Joseph Socha
Politechnico de Torino         Igor Stievano
Qlogic                         Larry Barnes
Sintecs BV                     Hans Klos, Bob te Nijenhuis
SiQual                         (Rob Hinz)
Sun Microsystems               Tim Coyle
Via Technologies               (Weber Chuang)
Xilinx                         Susan Wu


In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses. 
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are 
as follows:

       Date           Bridge Number    Reservation #    Passcode
  August 8, 2003      1-916-356-2663        1           583-0451

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas 
out 7 days before each Open Forum, and meeting minutes out within 7 days 
after.  When you call into the meeting, ask for the IBIS Open Forum hosted 
by Michael Mirmak and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
No new introductions.


CALL FOR PATENTS
Michael Mirmak called for any patents or pending patents related to the 
IBIS Version 4.0 standard. No companies declared a patent.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Michael Mirmak reported that the current membership still stands at 25 paid 
members.  The "Voting members and 2003 participants list" which appears 
at the top of the minutes has been updated to reflect the 2003 membership.


REVIEW OF MINUTES AND AR'S
Michael Mirmak mentioned that the June 23, 2003 summit minutes and
the June 27, 2003 meeting minutes needed changes to their participants
lists to reflect the current year's voting members.  The changes were
approved by acclamation.  Bob Ross added that the appropriate changes 
have already been made to the documents available on the web.


MISCELLANY/ANNOUNCEMENTS
No new announcements.


PRESS AND WEB PAGE UPDATES
Syed Huq reported that he has completed an initial review of the IBIS
roster to reflect the current membership list.  The response level
has not been high.  Bob Ross suggested that individual reminders be
sent to unresponsive companies, based on known good addresses.  In 
addition, Syed accepted an AR to replace the eigroup.org Futures
Committee link with a direct link to the IBIS 4.1 specification.
Syed also noted that an update to the Events page is in progress.


NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross reported that Roy Leventhal provided an updated model
library to EIA on June 29 for the eigroup.org website. 


OPENS FOR NEW ISSUES
No new issues.


INTERNATIONAL/EXTERNAL PROGRESS
- - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation)
  No report.
- - JEDEC Activity Report. 
  Nothing to report.

 
DATE/PCB EAST SUMMIT DISCUSSION
Michael Mirmak reviewed the current plans for DATE/PCB EAST.  An IBIS 
Summit is tentatively scheduled for Tuesday, October 21, but specific 
locations and times have not yet been determined.  Bob Ross suggested that
a call for papers be issued in mid-August.  He noted that the 
attendance at this event has usually been good.


DESIGNCON SUMMIT DISCUSSION
Bob Ross observed that arrangements for DesignCon 2004 should be almost
identical to those in previous years.  Michael Mirmak and Stephen
Peters noted that the DesignCon planners had already contacted them
regarding co-sponsorship and other issues.  Guy deBurgh mentioned that 
he has reserved time away from work for DesignCon and is willing to 
transport and set up the IBIS booth at the event.  Michael thanked him
for his efforts.  Syed and Michael have accepted an AR to obtain the
latest contact information for DesignCon to post on the IBIS web site.


IBIS VERSION 4.0 PARSER FUNDING AND STATUS
Michael Mirmak reported that the Open Forum has received a commitment 
from an additional company to purchase an IBISCHK4 parser license.  
This brings the total number of contributing organizations to nine, the 
original target.  Invoicing will be completed through the GEIA.  Stephen 
Peters stated that the GEIA had received payment from all other parser 
purchasers.  Bob Ross noted that payment for the parser should be issued 
to the developer by the end of the year or earlier, if possible.

Bob Ross noted that a beta version of IBISCHK4 had been compiled and
is available for download at:

http://www.vhdl.org/pub/ibis/ibischk4_beta


IBIS VERSION 4.1 DISCUSSION
Bob Ross reminded the Open Forum that a text version of IBIS
version 4.1 is available on the web.  Both the text and a PDF version
are available at:

  http://www.vhdl.org/pub/ibis/wip/

Few comments have been received on 4.1, though parser author Atul
Agarwal has addressed several key issues.  Lynne Green and Bob Ross
have been collecting feedback for future discussion.  Stephen Peters
suggested that formal readings of 4.1 begin during Open Forum meetings,
to review each BIRD change individually.  After three readings, the
specification can be presented to the Open Forum for an approval vote.
The Open Forum consensus was to address detailed technical issues in
a separate committee with recommendations presented to the Open
Forum for individual review and approval. 

Michael accepted an AR to establish a technical committee for 4.1 review.
In addition, Stephen proposed specifically discussing the relationship
between BIRD75, the [Ramp] keyword, and the C_comp subparameter in the
next Open Forum meeting.


IBIS QUALITY COMMITTEE
Robert Haller reported that the Quality Committee met on July 15, with
eight attendees.  The Committee continues to meet every two weeks and 
holds good discussions.  The next meeting is scheduled for July 29.


IBIS MODEL REVIEW COMMITTEE
Lynne Green reported that models have been sent to the Committee from 
Analog Devices in Ireland.  These have been distributed to the 
Committee members.  Lynne noted that EDA tool vendors are welcome to 
join the Committee.


NEW ADMINISTRATIVE ISSUES
No new issues.


S2IBIS3
Bob Ross noted that a "first step" revision of S2IBIS3 is available
from students at North Carolina State University (NCSU), specifically
Ambrish Varna.  This version is written in Java and does not support
conversion of all keywords (for example, support for [Series Current] and
MOSFET-related I-V tables is still in the planning stage).  Syed Huq
mentioned that he had installed Java and was actively validating the S2IBIS3
software. Syed also inquired about the Open Forum's policy toward
development of software which generates IBIS models.  Bob Ross stated that
the Open Forum does not provide funds for development which 
competes with products produced by Open Forum members.  Free, open
source software may be linked through the IBIS web site.  Michael Mirmak
accepted an AR to obtain a link to the S2IBIS3 software for posting to the
IBIS web site.


BIRD82 - Clarification of Clamp Table Use
Lynne Green and Robert Haller introduced BIRD82, which changes language
in the specification to clarify how clamp effects are to be combined
with pullup and pulldown data without double-counting.  At present, 
there is no way to address double-counting issues with parser
checks alone.  Bob Ross raised several concerns regarding the syntax
and format of the BIRD plus the suggestion that the specification should
avoid making specific algorithmic recommendations.  Lynne Green and
Robert Haller will revise and resubmit the BIRD.


BIRD74.4 - EMI Parameters
Guy de Burgh reported that he had received additional comments on the 
syntax of BIRD 74.4 from Bob Ross and others.  Guy will reissue
the BIRD as 74.5 when all suggestions and editorial changes have been
received and included. 


IBISCHK4 & BUG TRACKING STATUS
Thanks to efforts by Guy deBurgh, Lynne Green and Bob Ross, a beta version 
of the IBISCHK4 parser, compiled for several operating systems, can be 
found at:

http://www.vhdl.org/pub/ibis/ibischk4_beta

Test cases will be provided to the Quality committee for their review.
Bob Ross reviewed the procedure for approval of the IBISCHK4 parser.
The beta code will be provided to all licensees for their review.  All
BUG reports, including the analysis of the developer, will be closed 
through review in the Open Forum.  John Angulo noted that checking
of BUGs 68 and 78 have yet to be completed.  In addition, there were
minor differences noted between the developer's reference output and
the actual output of the software.  


IBIS ICM SPECIFICATION REVIEW
Michael Mirmak reported that a single message was received as feedback 
on the IBIS Interconnect Specification (ICM), in response to the recent
electronic call for review.  The issue raised was substantially similar 
to comments made at the recent IBIS Summit.  At this point, formal
readings will be scheduled in the Open Forum to move the ICM toward
an approval vote.


NEXT MEETINGS:
A brief discussion was held on whether to hold a meeting on August 29, 
before a major US holiday.  Lynne Green suggested that, with the high number
of documents now being analyzed, the meeting should be moved to August 22.  
This issue will be closed at the August 8 meeting.

The next teleconference meeting is scheduled for August 8, 2003 from 8:00
AM to 10:00 AM Pacific Daylight Time.  

============================================================================
                               NOTES

IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046
            michael.mirmak@intel.com
            Senior Analog Engineer, Intel Corporation
            M/S FM6-45
            1900 Prairie City Rd.
            Folsom, CA  95630

VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 451-1871
            lgreen@cadence.com
            Senior Modeling Engineer, Cadence Design Systems
            320 120th Ave NE, Suite B-103, Bellevue, WA 98005-3016

SECRETARY:  Randy Wolff (208) 363-1764, Fax: (208) 368-3475
            rrwolff@micron.com
            Simulation Engineer, Micron Technology, Inc.
            8000 S. Federal Way
            Mail Stop: 1-711
            Boise, ID 83707-0006
        
LIBRARIAN:  Roy Leventhal (847) 590-9398
            roy.leventhal@ieee.org
            Consultant, Leventhal Design and Communications
            1924 North Burke Drive
            Arlington Heights, Illinois 60004

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
            John_angulo@mentor.com
            Development Engineer, Mentor Graphics
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052


This meeting was conducted in accordance with the EIA Legal Guides and EIA 
Manual of Organization and Procedure.

The following e-mail addresses are used:

  majordomo@eda.org
      In the body, for the IBIS Open Forum Reflector:
      subscribe ibis <your e-mail address>

      In the body, for the IBIS Users' Group Reflector:
      subscribe ibis-users <your e-mail address>

      Help and other commands:
      help

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
      bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
      /pub/ibis/bugs/s2iplt/bugsplt.txt respectively.

Information on IBIS technical contents, IBIS participants, and actual IBIS 
models are available on the IBIS Home page found by selecting the Electronic 
Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.
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------------------------------

Date: Wed, 23 Jul 2003 18:01:59 -0700
From: "Angulo, John" <john_angulo@mentorg.com>
Subject: [IBIS-Users] In V/T curves why does 50 points in .ibs Vs 100 in spice output

The following is posted on behalf of Jose Corona at Artisan Components.  Please send all private replies to jcorona@artisan.com only.

- -----Original Message-----

Hello,

Does anyone know why in the .ibs file generated by s2ibis2 the V/T curves
only report 50 points, whereas in the spice output files there are 100 
points?

Here is a sample of the spice output and the .ibs output:

SPICE(typ corner):

Index    time              v(opad)

- --------------------------------------------------------------------------------

0        0.0000000e+00     4.3253099e-01

1        5.0000000e-11     4.3253113e-01

2        1.0000000e-10     4.3252559e-01

3        1.5000000e-10     4.3252751e-01

4        2.0000000e-10     4.3253553e-01

5        2.5000000e-10     4.3253529e-01

6        3.0000000e-10     4.3253389e-01

7        3.5000000e-10     4.3253236e-01

8        4.0000000e-10     4.3253074e-01

9        4.5000000e-10     4.3252927e-01

10       5.0000000e-10     4.3253518e-01

11       5.5000000e-10     4.3256145e-01

12       6.0000000e-10     4.3260427e-01

13       6.5000000e-10     4.3261196e-01

14       7.0000000e-10     4.3256039e-01

15       7.5000000e-10     4.3247953e-01

16       8.0000000e-10     4.3242192e-01

17       8.5000000e-10     4.3246200e-01

18       9.0000000e-10     4.3256133e-01

19       9.5000000e-10     4.3278955e-01

20       1.0000000e-09     4.3323946e-01


IBIS:

[Rising Waveform]

R_fixture = 60.0000

V_fixture = 0.9000

| time           V(typ)              V(min)              V(max)

|

  0.000S          0.4325V             0.4109V             0.4434V

1.000e-10S        0.4325V             0.4109V             0.4433V

   0.2000nS       0.4325V             0.4109V             0.4434V

   0.3000nS       0.4325V             0.4109V             0.4434V

   0.4000nS       0.4325V             0.4109V             0.4435V

   0.5000nS       0.4325V             0.4109V             0.4433V

   0.6000nS       0.4326V             0.4109V             0.4451V

   0.7000nS       0.4326V             0.4109V             0.4476V

   0.8000nS       0.4324V             0.4109V             0.6000V

   0.9000nS       0.4325V             0.4109V             1.3244V

   1.0000nS       0.4330V             0.4109V             1.5174V



I'll appreciate any input on this issue,
Thanks,

- -Jose


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------------------------------

Date: Thu, 24 Jul 2003 09:50:16 -0400
From: "Lovette, Whynn" <Whynn.Lovette@usa.xerox.com>
Subject: [IBIS-Users] s2ibis questions

 
Where is the best place to find detailed information on using the s2ibis
tool? 
I am able to produce an IBIS model of an I/O buffer I'm working with and the
typical results look very close to the spice results but the max and min
cases are not that different from the typical.
Looking at the spice file that s2ibis generates it appears to be testing
over the expected temp, voltage and process ranges.
When I run IBISCHK it tells me that all the curves are nonmonotonic.
Looking for help.
Thanks
Whynn Lovette
Xerox Corp.

This e-mail message, including any attachments, is for the sole use of the
intended recipient(s) and may contain confidential information.  Any
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are not the intended recipient(s) please contact the sender by reply e-mail
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------------------------------

Date: 24 Jul 2003 08:59:31 -0700
From: Syed Huq <shuq@cisco.com>
Subject: Re: [IBIS-Users] s2ibis questions

Look under:
http://www.eda.org/pub/ibis/s2ibis/s2ibis2_v1.1/

When you un'tar, you will get various sub-dir. Look at /doc etc

Syed

On Thu, 2003-07-24 at 06:50, Lovette, Whynn wrote:
>  
> Where is the best place to find detailed information on using the s2ibis
> tool? 
> I am able to produce an IBIS model of an I/O buffer I'm working with and the
> typical results look very close to the spice results but the max and min
> cases are not that different from the typical.
> Looking at the spice file that s2ibis generates it appears to be testing
> over the expected temp, voltage and process ranges.
> When I run IBISCHK it tells me that all the curves are nonmonotonic.
> Looking for help.
> Thanks
> Whynn Lovette
> Xerox Corp.
> 
> This e-mail message, including any attachments, is for the sole use of the
> intended recipient(s) and may contain confidential information.  Any
> unauthorized review, use, disclosure or distribution is prohibited.  If you
> are not the intended recipient(s) please contact the sender by reply e-mail
> and destroy all copies of the original message. Finally, the recipient
> should check that this email is authentic and examine it for the presence of
> viruses. Xerox does perform virus checks but cannot accept liability for any
> damage caused by any virus transmitted by this email. Thank you.
> 
> 
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------------------------------

Date: Thu, 24 Jul 2003 21:37:07 -0400
From: "Ambrish Varma" <akvarma@ncsu.edu>
Subject: RE: [IBIS-Users] In V/T curves why does 50 points in .ibs Vs 100 in spice output

Hi Jose,
You see this is because in s2ibis2, the default VT table length is
hard-coded to 50. This is set in the s2idflt.h in the /src folder and
was done so the table does not become too large and show redundant data
(as you can see). 

If you want to change the size of the table, you need to open the
abovementioned file, change the 'WAVE_POINTS_DEFAULT' parameter to 101
and then recompile the source files.
Hope this helps.
- -Ambrish Varma

Ambrish K Varma
akvarma@ncsu.edu
ph(919)513-2015
fax(919)515-2285

- -----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Angulo, John
Sent: Wednesday, July 23, 2003 9:02 PM
To: 'ibis-users@eda.org'
Subject: [IBIS-Users] In V/T curves why does 50 points in .ibs Vs 100 in
spice output

The following is posted on behalf of Jose Corona at Artisan Components.
Please send all private replies to jcorona@artisan.com only.

- -----Original Message-----

Hello,

Does anyone know why in the .ibs file generated by s2ibis2 the V/T
curves
only report 50 points, whereas in the spice output files there are 100 
points?

Here is a sample of the spice output and the .ibs output:

SPICE(typ corner):

Index    time              v(opad)

- ------------------------------------------------------------------------
- --------

0        0.0000000e+00     4.3253099e-01

1        5.0000000e-11     4.3253113e-01

2        1.0000000e-10     4.3252559e-01

3        1.5000000e-10     4.3252751e-01

4        2.0000000e-10     4.3253553e-01

5        2.5000000e-10     4.3253529e-01

6        3.0000000e-10     4.3253389e-01

7        3.5000000e-10     4.3253236e-01

8        4.0000000e-10     4.3253074e-01

9        4.5000000e-10     4.3252927e-01

10       5.0000000e-10     4.3253518e-01

11       5.5000000e-10     4.3256145e-01

12       6.0000000e-10     4.3260427e-01

13       6.5000000e-10     4.3261196e-01

14       7.0000000e-10     4.3256039e-01

15       7.5000000e-10     4.3247953e-01

16       8.0000000e-10     4.3242192e-01

17       8.5000000e-10     4.3246200e-01

18       9.0000000e-10     4.3256133e-01

19       9.5000000e-10     4.3278955e-01

20       1.0000000e-09     4.3323946e-01


IBIS:

[Rising Waveform]

R_fixture = 60.0000

V_fixture = 0.9000

| time           V(typ)              V(min)              V(max)

|

  0.000S          0.4325V             0.4109V             0.4434V

1.000e-10S        0.4325V             0.4109V             0.4433V

   0.2000nS       0.4325V             0.4109V             0.4434V

   0.3000nS       0.4325V             0.4109V             0.4434V

   0.4000nS       0.4325V             0.4109V             0.4435V

   0.5000nS       0.4325V             0.4109V             0.4433V

   0.6000nS       0.4326V             0.4109V             0.4451V

   0.7000nS       0.4326V             0.4109V             0.4476V

   0.8000nS       0.4324V             0.4109V             0.6000V

   0.9000nS       0.4325V             0.4109V             1.3244V

   1.0000nS       0.4330V             0.4109V             1.5174V



I'll appreciate any input on this issue,
Thanks,

- -Jose


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------------------------------

Date: Fri, 25 Jul 2003 11:21:18 -0700
From: Bob Ross <bob@teraspeed.com>
Subject: [IBIS-Users] BIRD74.5 EMI Parameters

To All:

Guy de Burgh has sumitted BIRD74.5 for review.

Bob

To the IBIS Committee.

BIRD 74 has been updated. Briefly the changes are:

1) Syntax changes have been made to conform to the IBIS specification.
   The technical content has not been affected.


Guy de Burgh
Mentor Graphics


******************************************************************************
******************************************************************************

BIRD ID#:        74.5
ISSUE TITLE:     EMI Parameters
REQUESTER:       Guy de Burgh, Mentor Graphics
DATE SUBMITTED:  3/19/02, 5/31/02/9/16/02, 4/30/03, 5/21/03. 7/18/03
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************
******************************************************************************

STATEMENT OF THE ISSUE:

Additional parameters required for EMI analysis.
All these parameters are optional.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The following changes are proposed:

******************************************************************************

Changes and additions to the IBIS Specification are shown by the |* lines.
Examples are shown as they would be seen in a specification.

|=============================================================================
|=============================================================================
|
|                                 Section 10
|
|                        E M I   P A R A M E T E R S
|
|=============================================================================
|
| There are two sections here: one for a [Component] and one for a [Model].
|
|=============================================================================
|=============================================================================
|
| This section describes the structure of the EMI parameters under a
| top-level [Component] keyword. It is used to describe the EMI parameters
| associated with a [Component]. The parameters must be surrounded by
| the [Begin EMI Component] and [End EMI Component] keywords.
|
| The following set of keywords are defined:
|
|   [Begin EMI Component]
|   [End EMI Component]
|   [Pin EMI]
|   [Pin Domain EMI]
|
| The following set of sub-parameters are defined:
|
|   Domain
|   Cpd
|   C_Heatsink_gnd
|   C_Heatsink_float
|
|=============================================================================
|
|     Keyword:  [Begin EMI Component]
|    Required:  No
| Description:  Marks the beginning of the Component EMI parameters.
|  Sub-Params:  Domain, Cpd, C_Heatsink_gnd, C_Heatsink_float
|
|               Domain indicates whether the component is a digital, analog
|               or part digital part analog. Analog circuits are more
|               susceptible to low-level noise. Analog circuits operate at
|               very low signal levels (mV or uV) and can contain high gain
|               amplifiers. In contrast, digital circuits operate at
|               relatively large signal levels (compared to analog 
circuits).
|
|               The syntax for Domain is:
|                  Domain   Domain_value
|
|               Where Domain_value is an enumerated argument, and is one of:
|                  Digital, Analog, Digital_analog
|
|               If not entered the default is Digital.
|
|               Cpd is the power dissipation capacitance parameter.
|               Cpd (Power Dissipation Capacitance) is the internal 
parasitic
|               capacitance (e.g., gate-to-source and gate-to-drain
|               capacitance) plus the equivalent capacitance associated with
|               the through currents when both transistors (n-channel and
|               p-channel) are momentarily conducting.
|
|               It is typically for CMOS devices, and helps provide a more
|               accurate estimation of the power bus current, and therefore
|               the noise voltage on the power bus. Knowing the high 
frequency
|               noise on the power bus (due to switching of digital 
circuits)
|               the radiation can be calculated.
|
|               Sometimes Iccd (Dynamic power supply current) is found in
|               databooks. It is normally given for FACT families. Iccd is
|               specified in units of mA/MHz.
|
|               Cpd can be calculated from Iccd by the equation
|                  Cpd (nF) = Iccd (mA/MHz) / Vcc (V).
|
|               The syntax for Cpd is:
|                  Cpd = capacitance_value
|
|               The units of capacitance_value are Farads.
|
|               If not entered the default is 0.0F.
|
|               C_Heatsink_Float and C_Heatsink_Gnd define the heatsink
|               capacitance and connection conditions.
|               C_Heatsink_Float indicates that the heatsink is floating,
|               and C_Heatsink_Gnd indicates that the heatsink is grounded.
|
|               Internal currents inside a (high speed) IC can be closely
|               coupled onto a heatsink. As the heatsink is physically much
|               larger than the IC silicon chip and bond wires it is a more
|               efficient radiator. Knowing the capacitance of the heatsink
|               the radiated electric field can be estimated.
|
|               Only one of these sub-parameters can be defined. It is not
|               legal to define both. It is legal to omit both. In this case
|               it means that a heatsink is not present.
|
|               The keyword takes one argument: the heatsink capacitance
|
|               The syntax for Heatsink_cap is:
|                  C_Heatsink_float = capacitance_value
|                  C_Heatsink_gnd   = capacitance_value
|
|               The units for capacitance_value are Farads.
|
|               If this sub-parameter is not entered the default is that the
|               component does not have a heatsink.
|
|=============================================================================
|
|     Keyword:  [End EMI Component]
|    Required:  No
| Description:  Marks the end of the Component EMI parameters.
|
|=============================================================================
|
|  Example:
|
[Begin EMI Component]
Domain           Digital
Cpd            = 6.4pF
C_Heatsink_gnd = 3.4pF
[End EMI Component]
|
|=============================================================================
|
|     Keyword:  [Pin EMI]
|    Required:  No
| Description:  Specifies the EMI parameters for a Pin.
|  Sub-Params:  domain_name, clock_div
| Usage Rules:  Each line must contain three columns.
|               The first column must contain the pin name. This pin name
|               must match a pin name in the [Pin] keyword. (The pin name
|               is the first column in the [Pin] record.)
|
|               The second column is the domain name. This specifies the 
clock
|               domain for that pin. This is used by [Pin Domain EMI].
|               The field can be left blank, or set to NA, if unused.
|
|               The default for domain_name is that the percentage of power
|               used is 100%.
|
|               The third column is the clock division. This is the ratio
|               of the frequency at this pin to the reference pin. The
|               reference pin is always set to "1.0". The ratio is a 
floating
|               point number. The choice of the reference in does not matter
|               as this information is pin to pin ratios. It is 
suggested that
|               the pin with the dominant frequency is chosen as the 
reference.
|               The field can be left blank, or set to NA, if unused.
|
|               The default for clock_div is 1.0
|
|               Column length limits are:
|                  pin_name      5 characters max
|                  domain_name  20 characters max
|                  clock_div     5 characters max
|
|               It is not a requirement to specify every pin. An undefined
|               pin will default to 100% power usage for Domain_name,
|               and 1.0 for clock_div.
|
|============================================================================
|
|     Keyword:  [Pin Domain EMI]
|    Required:  No
| Description:  Specifies the percentage of power used in each clock domain.
|  Sub-Params:  percentage
| Usage Rules:  Each line must contain two columns.
|               The first column must contain the domain_name. This name 
must
|               match a domain name in the [Pin EMI] keyword. (The domain
|               name is the second column in that record.)
|
|               The percentage represents a user definable percentage of the
|               power used by that domain. It is an integer in the range
|               0 < percentage =< 100
|
|               Column length limits are:
|                  domain_name  20 characters max
|                  percentage    5 characters max
|
|=============================================================================
|
|  Example:
|
[Begin EMI Component]
Domain          Digital
Cpd           = 6.4pF
|
[Pin EMI]   domain_name    clock_div
 4          MEM            0.5
 5          MEM            0.5
14          CPU            1.0
15          RIOG           0.5
|
[Pin Domain EMI]   percentage
 CPU               40
 MEM               30
 RIOG              30
|
[End EMI Component]
|
|=============================================================================
|=============================================================================
|
| This section describes the structure of the EMI parameters under a
| top-level [Model] keyword. It is used to describe the EMI parameters
| associated with a [Model]. The parameters must be surrounded by
| the [Begin EMI Model] and [End EMI Model] keywords.
|
| The following set of keywords are defined:
|
|   [Begin EMI Model]
|   [End EMI Model]
|
| The following set of sub-parameters are defined:
|
|   Model_emi_type
|   Model_Domain
|
|=============================================================================
|
|     Keyword:  [Begin EMI Model]
|    Required:  No
| Description:  Marks the beginning of the Model EMI parameters.
|  Sub-Params:  Model_emi_type, Domain
|
|               Model_emi_type indicates whether the model (for this 
pin) is a
|               ferrite or not.
|
|               The syntax for Model_emi_type is:
|                  Model_emi_type   Model_emi_type_value
|
|               Where Model_emi_type_value is an enumerated argument, and is
|               one of:
|                  Ferrite, Not_a_ferrite
|
|               If not entered (the default) the model is Not_a_ferrite.
|
|               Model_Domain indicates whether the model is digital or 
analog.
|               This is only used if the [Component EMI] Domain is set to
|               Digital_analog. If the [Component EMI] Domain is set to
|               anything else Model_Domain is ignored.
|
|               The syntax for Domain is:
|                  Model_Domain   Domain_value
|
|               Where Domain_value is one of:
|                  Digital, Analog
|
|               If not entered the default is to use the [Component EMI]
|               Domain setting and it's default.
|
|=============================================================================
|
|     Keyword:  [End EMI Model]
|    Required:  No
| Description:  Marks the end of the Model EMI parameters.
|
|=============================================================================
|
|-----------------------------------------------------------------------------
|
[Begin EMI Model]
Domain          Analog
Model_emi_type  Ferrite
[End EMI Model]
|
******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

EMI is becoming increasingly important in PCB design.
EMI simulation is not an exact science. The problem is too complicated
for today's computers. However being able to identify which signals
radiate more than others (relatively), and showing where the energy
flows in a system does help in identifying potential EMI problems.
No longer requiring absolute accuracy, but requiring relative accuracy,
makes the analysis considerably easier, and possible. The parameters
specified here are chosen for that purpose, and have been specifically
chosen as they are readily available in data books in order to make it
easier to create models.

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

Presentations on this topic were given at the IBIS Summit Meeting
at DAC on June 21, 2001, and at DesignCon on January 28, 2002.

******************************************************************************

- -- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
2926 SE Yamhill St.                Device Modeling Division
Portland, OR 97214                 13610 SW Harness Lane
503-239-5536                       Beaverton, OR 97008
http://www.teraspeed.com           503-430-1065
bob@teraspeed.com                  503-246-8048 Direct



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------------------------------

Date: Mon, 28 Jul 2003 09:02:32 +0530
From: KMuthulakshmi@scmmicro.co.in
Subject: [IBIS-Users] IBIS model Error

This is a multipart message in MIME format.
- --=_alternative 001375A765256D71_=
Content-Type: text/plain; charset="us-ascii"

Hi All,

I need IBIS expert's advice on the following.

I get the following warning when checking the IBIS model. 

Warning - Model bp_usb_hs: The [Rising Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture]=0V
      has TYP column DC endpoints of  0.00V and  0.38v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.14V and  1.06V),
      a difference of 99.99% and 64.28%, respectively.

Warning - Model bp_usb_hs: The [Falling Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture]=0V
      has TYP column DC endpoints of  0.00V and  0.38v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.14V and  1.06V),
      a difference of 99.99% and 64.28%, respectively.

Warning - Model bp_usb_hs: The [Rising Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture_min]=0V
      has MIN column DC endpoints of  0.00V and  0.37v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.09V and  0.93V),
      a difference of 99.99% and 60.23%, respectively.

Warning - Model bp_usb_hs: The [Falling Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture_min]=0V
      has MIN column DC endpoints of  0.00V and  0.37v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.09V and  0.93V),
      a difference of 99.99% and 60.23%, respectively.

Warning - Model bp_usb_hs: The [Rising Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture_max]=0V
      has MAX column DC endpoints of  0.00V and  0.39v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.77V and  1.83V),
      a difference of 100.00% and 78.72%, respectively.

Warning - Model bp_usb_hs: The [Falling Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture_max]=0V
      has MAX column DC endpoints of  0.00V and  0.38v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.77V and  1.83V),
      a difference of 100.00% and 79.26%, respectively.

Please tell me the impact of this warning in simulation. I use XTK for the 
simulation. Eventhough the rise and fall VT curve values range from 0V to 
0.38V in the IBIS model, I get 1.04V to 1.14V wave form. How is this 
related with this. I am using Cypress "CY7C65640" hub controller's IBIS 
model.

Awaiting your earliest reply.

Note: One IBIS parser gives the above warnings and another parser gives 
them as Errors.
        I do not know whether files can be attached with this mail. If it 
is OK, I can send  the IBIS model.

thanks & regards
K.Muthu Lakshmi (KML)

SCM Microsystems (India) Pvt. Ltd.
email: KMuthulakshmi@scmmicro.co.in
Web: www.scmmicro.com

- --=_alternative 001375A765256D71_=
Content-Type: text/html; charset="us-ascii"


<br><font size=2 face="sans-serif">Hi All,</font>
<br>
<br><font size=2 face="sans-serif">I need IBIS expert's advice on the following.</font>
<br>
<br><font size=2 face="sans-serif">I get the following warning when checking the IBIS model. </font>
<br>
<br><font size=2 color=blue face="sans-serif">Warning - Model bp_usb_hs: The [Rising Waveform] </font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; with [R_fixture]=45 Ohms and [V_fixture]=0V</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; has TYP column DC endpoints of &nbsp;0.00V and &nbsp;0.38v, but</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; an equivalent load applied to the model's I-V tables yields</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; different voltages ( 1.14V and &nbsp;1.06V),</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; a difference of 99.99% and 64.28%, respectively.</font>
<br>
<br><font size=2 color=blue face="sans-serif">Warning - Model bp_usb_hs: The [Falling Waveform] </font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; with [R_fixture]=45 Ohms and [V_fixture]=0V</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; has TYP column DC endpoints of &nbsp;0.00V and &nbsp;0.38v, but</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; an equivalent load applied to the model's I-V tables yields</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; different voltages ( 1.14V and &nbsp;1.06V),</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; a difference of 99.99% and 64.28%, respectively.</font>
<br>
<br><font size=2 color=blue face="sans-serif">Warning - Model bp_usb_hs: The [Rising Waveform] </font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; with [R_fixture]=45 Ohms and [V_fixture_min]=0V</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; has MIN column DC endpoints of &nbsp;0.00V and &nbsp;0.37v, but</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; an equivalent load applied to the model's I-V tables yields</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; different voltages ( 1.09V and &nbsp;0.93V),</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; a difference of 99.99% and 60.23%, respectively.</font>
<br>
<br><font size=2 color=blue face="sans-serif">Warning - Model bp_usb_hs: The [Falling Waveform] </font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; with [R_fixture]=45 Ohms and [V_fixture_min]=0V</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; has MIN column DC endpoints of &nbsp;0.00V and &nbsp;0.37v, but</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; an equivalent load applied to the model's I-V tables yields</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; different voltages ( 1.09V and &nbsp;0.93V),</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; a difference of 99.99% and 60.23%, respectively.</font>
<br>
<br><font size=2 color=blue face="sans-serif">Warning - Model bp_usb_hs: The [Rising Waveform] </font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; with [R_fixture]=45 Ohms and [V_fixture_max]=0V</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; has MAX column DC endpoints of &nbsp;0.00V and &nbsp;0.39v, but</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; an equivalent load applied to the model's I-V tables yields</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; different voltages ( 1.77V and &nbsp;1.83V),</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; a difference of 100.00% and 78.72%, respectively.</font>
<br>
<br><font size=2 color=blue face="sans-serif">Warning - Model bp_usb_hs: The [Falling Waveform] </font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; with [R_fixture]=45 Ohms and [V_fixture_max]=0V</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; has MAX column DC endpoints of &nbsp;0.00V and &nbsp;0.38v, but</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; an equivalent load applied to the model's I-V tables yields</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; different voltages ( 1.77V and &nbsp;1.83V),</font>
<br><font size=2 color=blue face="sans-serif">&nbsp; &nbsp; &nbsp; a difference of 100.00% and 79.26%, respectively.</font>
<br>
<br><font size=2 face="sans-serif">Please tell me the impact of this warning in simulation. I use XTK for the simulation. Eventhough the rise and fall VT curve values range from 0V to 0.38V in the IBIS model, I get 1.04V to 1.14V wave form. How is this related with this. I am using Cypress &quot;CY7C65640&quot; hub controller's IBIS model.</font>
<br>
<br><font size=2 face="sans-serif">Awaiting your earliest reply.</font>
<br>
<br><font size=2 face="sans-serif">Note: One IBIS parser gives the above warnings and another parser gives them as Errors.</font>
<br><font size=2 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; I do not know whether files can be attached with this mail. If it is OK, I can send &nbsp;the IBIS model.</font>
<br>
<br><font size=2 face="sans-serif">thanks &amp; regards<br>
K.Muthu Lakshmi (KML)<br>
<br>
SCM Microsystems (India) Pvt. Ltd.<br>
email: KMuthulakshmi@scmmicro.co.in<br>
Web: www.scmmicro.com</font>
<br>
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------------------------------

Date: Mon, 28 Jul 2003 10:09:33 +0200
From: erik.van.der.ven@philips.com
Subject: Re: [IBIS-Users] IBIS model Error

This is a multipart message in MIME format.
- --=_alternative 002D0844C1256D71_=
Content-Type: text/plain; charset="us-ascii"

Hello Muthu Lakshmi,

I think there is something wrong with your IBIS model. The DC end points 
calculated from the I-V tables should match the V-T end points (logic 
levels). If the error is within 2% you should get a warning, otherwise an 
error. The difference you mention is very big.

The DC end points are calculated from the I-V tables (therefore you don't 
see the end points of the V-T table). The I-V tables are derived by 
sweeping a voltage at the output and measuring the resulting current. By 
applying a certain load the voltages from the logic high and low level are 
calculated from the pull-up and pull-down curve (and of course they should 
be near the waveform end point voltages). The V-T data is used to describe 
the transition between the logic levels calculated from the I-V data.

I would suggest that you contact Cypress to ask if this model is OK.


With kind regards,


Ir. Erik van der Ven
Room DB1032
Business Line Networking Infrastructure
Philips Semiconductors BV
Gerstweg 2
6534 AE Nijmegen
The Netherlands
Phone: +31-24-3534334









KMuthulakshmi@scmmicro.co.in
Sent by: 
owner-ibis-users@eda.org
07/28/03 05:32 AM

 
        To:     ibis-users@eda.org
        cc:     (bcc: Erik van der Ven/NYM/SC/PHILIPS)
        Subject:        [IBIS-Users] IBIS model Error
        Classification: 




Hi All, 

I need IBIS expert's advice on the following. 

I get the following warning when checking the IBIS model. 

Warning - Model bp_usb_hs: The [Rising Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture]=0V 
      has TYP column DC endpoints of  0.00V and  0.38v, but 
      an equivalent load applied to the model's I-V tables yields 
      different voltages ( 1.14V and  1.06V), 
      a difference of 99.99% and 64.28%, respectively. 

Warning - Model bp_usb_hs: The [Falling Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture]=0V 
      has TYP column DC endpoints of  0.00V and  0.38v, but 
      an equivalent load applied to the model's I-V tables yields 
      different voltages ( 1.14V and  1.06V), 
      a difference of 99.99% and 64.28%, respectively. 

Warning - Model bp_usb_hs: The [Rising Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture_min]=0V 
      has MIN column DC endpoints of  0.00V and  0.37v, but 
      an equivalent load applied to the model's I-V tables yields 
      different voltages ( 1.09V and  0.93V), 
      a difference of 99.99% and 60.23%, respectively. 

Warning - Model bp_usb_hs: The [Falling Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture_min]=0V 
      has MIN column DC endpoints of  0.00V and  0.37v, but 
      an equivalent load applied to the model's I-V tables yields 
      different voltages ( 1.09V and  0.93V), 
      a difference of 99.99% and 60.23%, respectively. 

Warning - Model bp_usb_hs: The [Rising Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture_max]=0V 
      has MAX column DC endpoints of  0.00V and  0.39v, but 
      an equivalent load applied to the model's I-V tables yields 
      different voltages ( 1.77V and  1.83V), 
      a difference of 100.00% and 78.72%, respectively. 

Warning - Model bp_usb_hs: The [Falling Waveform] 
      with [R_fixture]=45 Ohms and [V_fixture_max]=0V 
      has MAX column DC endpoints of  0.00V and  0.38v, but 
      an equivalent load applied to the model's I-V tables yields 
      different voltages ( 1.77V and  1.83V), 
      a difference of 100.00% and 79.26%, respectively. 

Please tell me the impact of this warning in simulation. I use XTK for the 
simulation. Eventhough the rise and fall VT curve values range from 0V to 
0.38V in the IBIS model, I get 1.04V to 1.14V wave form. How is this 
related with this. I am using Cypress "CY7C65640" hub controller's IBIS 
model. 

Awaiting your earliest reply. 

Note: One IBIS parser gives the above warnings and another parser gives 
them as Errors. 
        I do not know whether files can be attached with this mail. If it 
is OK, I can send  the IBIS model. 

thanks & regards
K.Muthu Lakshmi (KML)

SCM Microsystems (India) Pvt. Ltd.
email: KMuthulakshmi@scmmicro.co.in
Web: www.scmmicro.com 


- --=_alternative 002D0844C1256D71_=
Content-Type: text/html; charset="us-ascii"


<br><font size=2 face="sans-serif">Hello Muthu Lakshmi,</font>
<br>
<br><font size=2 face="sans-serif">I think there is something wrong with your IBIS model. The DC end points calculated from the I-V tables should match the V-T end points (logic levels). If the error is within 2% you should get a warning, otherwise an error. The difference you mention is very big.</font>
<br>
<br><font size=2 face="sans-serif">The DC end points are calculated from the I-V tables (therefore you don't see the end points of the V-T table). The I-V tables are derived by sweeping a voltage at the output and measuring the resulting current. By applying a certain load the voltages from the logic high and low level are calculated from the pull-up and pull-down curve (and of course they should be near the waveform end point voltages). The V-T data is used to describe the transition between the logic levels calculated from the I-V data.</font>
<br>
<br><font size=2 face="sans-serif">I would suggest that you contact Cypress to ask if this model is OK.</font>
<br>
<br>
<br><font size=2 face="sans-serif">With kind regards,</font>
<br>
<br><font size=2 face="sans-serif"><br>
Ir. Erik van der Ven<br>
Room DB1032<br>
Business Line Networking Infrastructure<br>
Philips Semiconductors BV<br>
Gerstweg 2<br>
6534 AE Nijmegen<br>
The Netherlands<br>
Phone: +31-24-3534334</font>
<br>
<br>
<br>
<table width=100%>
<tr valign=top>
<td>
<td>
<br>
<br>
<br>
<br>
<br><font size=1 face="sans-serif"><b>KMuthulakshmi@scmmicro.co.in</b></font>
<p><font size=1 face="sans-serif">Sent by: </font>
<br><font size=1 face="sans-serif">owner-ibis-users@eda.org</font>
<p><font size=1 face="sans-serif">07/28/03 05:32 AM</font>
<br>
<td><font size=1 face="Arial">&nbsp; &nbsp; &nbsp; &nbsp; </font>
<br><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; To: &nbsp; &nbsp; &nbsp; &nbsp;ibis-users@eda.org</font>
<br><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; cc: &nbsp; &nbsp; &nbsp; &nbsp;(bcc: Erik van der Ven/NYM/SC/PHILIPS)</font>
<br><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; Subject: &nbsp; &nbsp; &nbsp; &nbsp;[IBIS-Users] IBIS model Error</font>
<p><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; Classification: &nbsp; &nbsp; &nbsp; &nbsp;</font>
<br></table>
<br>
<br>
<br><font size=2 face="sans-serif"><br>
Hi All,</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 face="sans-serif"><br>
I need IBIS expert's advice on the following.</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 face="sans-serif"><br>
I get the following warning when checking the IBIS model. </font><font size=3 face="Times New Roman"><br>
</font><font size=2 color=blue face="sans-serif"><br>
Warning - Model bp_usb_hs: The [Rising Waveform] <br>
 &nbsp; &nbsp; &nbsp;with [R_fixture]=45 Ohms and [V_fixture]=0V</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;has TYP column DC endpoints of &nbsp;0.00V and &nbsp;0.38v, but</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;an equivalent load applied to the model's I-V tables yields</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;different voltages ( 1.14V and &nbsp;1.06V),</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;a difference of 99.99% and 64.28%, respectively.</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 color=blue face="sans-serif"><br>
Warning - Model bp_usb_hs: The [Falling Waveform] <br>
 &nbsp; &nbsp; &nbsp;with [R_fixture]=45 Ohms and [V_fixture]=0V</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;has TYP column DC endpoints of &nbsp;0.00V and &nbsp;0.38v, but</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;an equivalent load applied to the model's I-V tables yields</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;different voltages ( 1.14V and &nbsp;1.06V),</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;a difference of 99.99% and 64.28%, respectively.</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 color=blue face="sans-serif"><br>
Warning - Model bp_usb_hs: The [Rising Waveform] <br>
 &nbsp; &nbsp; &nbsp;with [R_fixture]=45 Ohms and [V_fixture_min]=0V</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;has MIN column DC endpoints of &nbsp;0.00V and &nbsp;0.37v, but</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;an equivalent load applied to the model's I-V tables yields</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;different voltages ( 1.09V and &nbsp;0.93V),</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;a difference of 99.99% and 60.23%, respectively.</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 color=blue face="sans-serif"><br>
Warning - Model bp_usb_hs: The [Falling Waveform] <br>
 &nbsp; &nbsp; &nbsp;with [R_fixture]=45 Ohms and [V_fixture_min]=0V</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;has MIN column DC endpoints of &nbsp;0.00V and &nbsp;0.37v, but</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;an equivalent load applied to the model's I-V tables yields</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;different voltages ( 1.09V and &nbsp;0.93V),</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;a difference of 99.99% and 60.23%, respectively.</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 color=blue face="sans-serif"><br>
Warning - Model bp_usb_hs: The [Rising Waveform] <br>
 &nbsp; &nbsp; &nbsp;with [R_fixture]=45 Ohms and [V_fixture_max]=0V</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;has MAX column DC endpoints of &nbsp;0.00V and &nbsp;0.39v, but</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;an equivalent load applied to the model's I-V tables yields</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;different voltages ( 1.77V and &nbsp;1.83V),</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;a difference of 100.00% and 78.72%, respectively.</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 color=blue face="sans-serif"><br>
Warning - Model bp_usb_hs: The [Falling Waveform] <br>
 &nbsp; &nbsp; &nbsp;with [R_fixture]=45 Ohms and [V_fixture_max]=0V</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;has MAX column DC endpoints of &nbsp;0.00V and &nbsp;0.38v, but</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;an equivalent load applied to the model's I-V tables yields</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;different voltages ( 1.77V and &nbsp;1.83V),</font><font size=3 face="Times New Roman"> </font><font size=2 color=blue face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp;a difference of 100.00% and 79.26%, respectively.</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 face="sans-serif"><br>
Please tell me the impact of this warning in simulation. I use XTK for the simulation. Eventhough the rise and fall VT curve values range from 0V to 0.38V in the IBIS model, I get 1.04V to 1.14V wave form. How is this related with this. I am using Cypress &quot;CY7C65640&quot; hub controller's IBIS model.</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 face="sans-serif"><br>
Awaiting your earliest reply.</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 face="sans-serif"><br>
Note: One IBIS parser gives the above warnings and another parser gives them as Errors.</font><font size=3 face="Times New Roman"> </font><font size=2 face="sans-serif"><br>
 &nbsp; &nbsp; &nbsp; &nbsp;I do not know whether files can be attached with this mail. If it is OK, I can send &nbsp;the IBIS model.</font><font size=3 face="Times New Roman"> </font>
<br><font size=2 face="sans-serif"><br>
thanks &amp; regards<br>
K.Muthu Lakshmi (KML)<br>
<br>
SCM Microsystems (India) Pvt. Ltd.<br>
email: KMuthulakshmi@scmmicro.co.in<br>
Web: www.scmmicro.com</font><font size=3 face="Times New Roman"> </font>
<br>
<br>
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------------------------------

Date: Thu, 31 Jul 2003 11:09:42 +0200
From: "Henrik G. Madsen" <hgm@vitesse.com>
Subject: [IBIS-Users] How to set the Power Clamp Reference

Hi

I hope that I can get some feedback on this.

I have the below simplified output driver with a pullup and pulldown transistor and some clamp diodes.

VDD  = 3.3 V
VDD2 = 2.5 V
VSS  = 0 V

                 VDD         VDD2
                 _____       ________
                      |     |
                      |    / \
                     -     ---
                 ___|       |
                    |      / \
                     -     ---
                      |     |
                      |-----|
                      |     |
                     -
                 ___|       |
                    |      / \
                     -     ---
                      |     |
                      |     |
                 -----------------  VSS

When generating the I-V curves for the IBIS model, the POWER CLAMP and GND CLAMP curves should include the parasitic current running in respectively the Pullup and Pulldown transistor, when they are off as I understand it.

What would be the best solution for controlling the Power Clamp voltage during IBIS model generation?

1) Just using the [Voltage Range] = 3.3V 3.0V 3.6V along with a controlled supply, which control the VDD2. (VDD2 scales with VDD)
E_VDD2 VDD2 VSS PWL(1) VDD VSS 0,0 2.84,2.84 2.86,2.3 3.0,2.3 3.6,2.7

or
2)
Using the 
[Pullup reference]       = 3.3V 3.0V 3.6V
[Pulldown reference]     = 0.0V 0.0V 0.0V
[Power Clamp Reference]  = 2.5V 2.3V 2.7V
[GND Clamp Reference]    = 0.0V 0.0V 0.0V


I prefer #1 since it ensures that the power and ground clamp voltages are scalled from -3.3V to 6.6V

Any comments?

Regards
/Henrik


_____________________________________
Henrik G Madsen
HW Engineer, M.Sc.E.E 
Vitesse Semiconductor Corporation A/S
Ethernet Products Division
Hoerkaer 16,  DK-2730 Herlev, DENMARK
Direct: +45 4485 5920
Phone: +45 4485 5900, Fax: +45 4485 5901
mail: hgm@vitesse.com
web: http://www.vitesse.com
_____________________________________


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------------------------------

Date: Thu, 31 Jul 2003 08:38:24 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] How to set the Power Clamp Reference

Henrik,

It seems that your two options end up being the same, since your
VDD values will be 3.3, 3.0 and 3.6 for generating the typ., min.,
and max. IV curves, for which the PWL table yields 2.3, 2.5 and
2.7, respectively.  That unusual relationship at VDD = 0 .. 2.86
is not going to happen when the VDD range is 3.0 .. 3.6.

Also, in IBIS you can't use equations or relational tables for
expressing one voltage as a function of another one, so you can
only do your second option as far as the IBIS syntax goes.

Arpad Muranyi
Intel Corporation
================================================================

- -----Original Message-----
From: Henrik G. Madsen [mailto:hgm@vitesse.com]
Sent: Thursday, July 31, 2003 2:10 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] How to set the Power Clamp Reference


Hi

I hope that I can get some feedback on this.

I have the below simplified output driver with a pullup and pulldown transistor and some clamp diodes.

VDD  = 3.3 V
VDD2 = 2.5 V
VSS  = 0 V

                 VDD         VDD2
                 _____       ________
                      |     |
                      |    / \
                     -     ---
                 ___|       |
                    |      / \
                     -     ---
                      |     |
                      |-----|
                      |     |
                     -
                 ___|       |
                    |      / \
                     -     ---
                      |     |
                      |     |
                 -----------------  VSS

When generating the I-V curves for the IBIS model, the POWER CLAMP and GND CLAMP curves should include the parasitic current running in respectively the Pullup and Pulldown transistor, when they are off as I understand it.

What would be the best solution for controlling the Power Clamp voltage during IBIS model generation?

1) Just using the [Voltage Range] = 3.3V 3.0V 3.6V along with a controlled supply, which control the VDD2. (VDD2 scales with VDD)
E_VDD2 VDD2 VSS PWL(1) VDD VSS 0,0 2.84,2.84 2.86,2.3 3.0,2.3 3.6,2.7

or
2)
Using the 
[Pullup reference]       = 3.3V 3.0V 3.6V
[Pulldown reference]     = 0.0V 0.0V 0.0V
[Power Clamp Reference]  = 2.5V 2.3V 2.7V
[GND Clamp Reference]    = 0.0V 0.0V 0.0V


I prefer #1 since it ensures that the power and ground clamp voltages are scalled from -3.3V to 6.6V

Any comments?

Regards
/Henrik


_____________________________________
Henrik G Madsen
HW Engineer, M.Sc.E.E 
Vitesse Semiconductor Corporation A/S
Ethernet Products Division
Hoerkaer 16,  DK-2730 Herlev, DENMARK
Direct: +45 4485 5920
Phone: +45 4485 5900, Fax: +45 4485 5901
mail: hgm@vitesse.com
web: http://www.vitesse.com
_____________________________________


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------------------------------

Date: Thu, 31 Jul 2003 15:51:57 -0400
From: Timothy Coyle <timothy.coyle@sun.com>
Subject: [IBIS-Users] Comments on IBIS Spec Version 4.1

Hi,
The following are some comments/feedback I have on IBIS version 4.1. My comments are not necessarily on the new
additions to version 4.1, but some things that could be changed/modified in previous versions.

- - Page 17, under keyword diff pin, it states that if it is a differential input than vdiff overrides and supercedes need for Vinh and
Vinl parameters. But on page 22 it states that for any Input model type if Vinh and Vinl are not defined the parser gives a warning. When people
create a differential buffer, most are not concerned with the single-ended signal. I have seen a lot of people define the Vinh and Vinl as the
differential thresholds (say +/- 100mv for LVDS) because they think these will be applied to the differential signal. I think some more clarification
is needed here when someone is using an Input as a differential input. 

- - page 24, under keyword model, the Cref and Rref subparamter paragraph.(last paragraph) I have always taken issue with the way this is worded.
I do not think propogation delay should be used - some people will confuse this with the time it takes from the input to the output, which is not
correct for IBIS. I think we should say in order for simulators to calculate flight time correctly, a timing load is need to determine the time
it takes the output buffer to reach Vmeas. Some people refer to this as time to Vmeas. 


- - pg 53, under keyword Rising/Falling waveform, last paragraph stating that V/T curve assumes die capacitance included. Then it goes on 
to say that this can lead to numerical errors with C_comp in simulators. I am under the impression that for an output buffer model that the
simulator will compensate for the die capacitance being in the V/T curves. Maybe this needs more clarification?


Regards,
Tim
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------------------------------

Date: 31 Jul 2003 13:23:25 -0700
From: Syed Huq <shuq@cisco.com>
Subject: Re: [IBIS-Users] Mid Year Roster Cleanup - Pls respond

Hello,

Thanks to many of you for your quick responses. Your requested changes
to the roster has been updated. Let me know if there are other changes.

For those of you who have not had a chance to respond, pls do so asap to
avoid deletion of your entry from the IBIS roster.

Thanks,
Syed

On Fri, 2003-06-27 at 16:55, Syed Huq wrote:
> Hello,
> 
> Pls take a moment to review your roster entry on the IBIS page:
> 
> http://www.vhdl.org/pub/ibis/roster/roster.html
> 
> If certain information needs to be updated, pls provide the changes to
> me. We want your information to be current for the IBIS community.
> 
> If no changes are needed, still respond back to me and confirm.
> 
> Failure to provide a response may result in the removal of your entries
> from the roster so your quick response will be highly appreciated.
> 
> Regards,
> Syed
> Cisco Systems, Inc
> Webmaster
> 
> 
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------------------------------

Date: Thu, 31 Jul 2003 13:32:12 -0700
From: "Mirmak, Michael" <michael.mirmak@intel.com>
Subject: [IBIS-Users] Agenda, IBIS Open Forum Teleconference 8/8

		     IBIS Open Forum Meeting Agenda
			       for 8/08/03

           Bridge Number    Reservation #   Passcode
           1-916-356-2663       1           583-0451
            (International Dial-In: 1-617-801-9781)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into
the meeting, ask for the IBIS Open Forum hosted by Michael Mirmak and 
give the Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                       Mirmak

     - Intros of New IBIS Participants, Meeting Quorum     Mirmak
     - Call for Patents (IBIS 4.0, 4.1, ICM)               Mirmak
     - Membership Update and Treasurers Report             Mirmak
     - Review of Previous Meeting's Minutes (and ARs)      Mirmak
         July 18 Open Forum Minutes
     - Miscellany/Announcements                            All
     - Press & Web Page Updates                            Huq, All
     - New Models Available, Library Update                Leventhal
     - Opens for New Issues                                All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS 
       and EMC Simulation)                                 Perrin/Peters
     - JEDEC Committee Report                              Green

     PCB East Summit Planning                              Mirmak

     IBIS Version 4.0 Parser Status                        Mirmak/Peters

     IBIS Quality Committee Report                         Katz

     IBIS Model Review Committee                           Green

     S2IBIS3 Status                                        Ross

     New Administrative Issues                             All

8:45 Technical Discussion

     BIRD74.5 - EMI Parameters                             de Burgh
     - Call for vote

     IBIS Version 4.1 Discussion                           All
     - C_comp required for multi-lingual extensions?     
     - [Ramp] required for multi-lingual extensions?

     ICM Specification Reading and Discussion              Mirmak, All
     - Call for vote on Sept. 12

     IBISCHK4 Status                                       Ross/Angulo
     - BUG68 and BUG78
     - Test Suite?

     Driver Schedule Clarification                         Muranyi
     - Subparameters ignored in scheduled models?

     New Technical Issues                                  All

9:50 Wrap Up and Next Meetings Plans                       Mirmak

9:55 Sign Off
  
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------------------------------

Date: Fri, 1 Aug 2003 14:13:11 -0700
From: "Abril, Giovanni" <giovanni.abril@ngc.com>
Subject: [IBIS-Users] C_comp value in IBIS model

This is a multi-part message in MIME format.

- ------_=_NextPart_001_01C35871.B6D28312
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	charset="iso-8859-1"
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Hello IBIS gurus,

I've created an IBIS model using a spice netlist from the vendor, and =
I'm wondering what to do with C_comp.  My rising and falling waveforms =
include the effect of C_comp, but what should I put in the IBIS model?  =
I have a spec sheet that says min C_comp is 2.8pF, max is 10pF.  =
Currently I have 5.0pF for typ, 2.8pF min and 10pF max.=20

Thanks,

Giovanni

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<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
6.0.6472.0">
<TITLE>C_comp value in IBIS model</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->

<P><FONT SIZE=3D2 FACE=3D"Arial">Hello IBIS gurus,</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">I've created an IBIS model using a =
spice netlist from the vendor, and I'm wondering what to do with =
C_comp.&nbsp; My rising and falling waveforms include the effect of =
C_comp, but what should I put in the IBIS model?&nbsp; I have a spec =
sheet that says min C_comp is 2.8pF, max is 10pF.&nbsp; Currently I have =
5.0pF for typ, 2.8pF min and 10pF max. </FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Thanks,</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Giovanni</FONT>
</P>

</BODY>
</HTML>
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------------------------------

Date: Fri, 1 Aug 2003 14:44:50 -0700
From: Kim Helliwell <kimgh@apple.com>
Subject: Re: [IBIS-Users] C_comp value in IBIS model

- --Apple-Mail-6--137288472
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain;
	charset=ISO-8859-1;
	format=flowed

If the waveforms already include the effects of C_comp, putting
the C_comp value in the IBIS model will double-count the effect
of C_comp, which is probably not what you want.

I feel certain that the right thing to do is re-run the spice sims
with C_comp removed from the simulations, and put the correct
typ/min/max values of C_comp directly in the IBIS model

If I were your customer trying to use this model, I'd be really unhappy
to find that C_comp was (silently) being double counted. And I'd
be suspicious of your model if C_comp were 0 with no explanation.

At the very least, if you don't want to re-run things, you should set
C_comp to 0 but put in a comment that the reason it's zero is that
the effects of C_comp are included in the rising/falling waveforms.

But this is definitely a distant second-best, in my opinion.

Kim

On Friday, August 1, 2003, at 02:13  PM, Abril, Giovanni wrote:

> Hello IBIS gurus,
>
> I've created an IBIS model using a spice netlist from the vendor, and=20=

> I'm wondering what to do with C_comp.=A0 My rising and falling =
waveforms=20
> include the effect of C_comp, but what should I put in the IBIS=20
> model?=A0 I have a spec sheet that says min C_comp is 2.8pF, max is=20
> 10pF.=A0 Currently I have 5.0pF for typ, 2.8pF min and 10pF max.
>
> Thanks,
>
> Giovanni
>
>
Kim Helliwell
Apple Computer
kimgh@apple.com
408 974 9936


- --Apple-Mail-6--137288472
Content-Transfer-Encoding: quoted-printable
Content-Type: text/enriched;
	charset=ISO-8859-1

If the waveforms already include the effects of C_comp, putting

the C_comp value in the IBIS model will double-count the effect

of C_comp, which is probably not what you want.


I feel certain that the right thing to do is re-run the spice sims

with C_comp removed from the simulations, and put the correct

typ/min/max values of C_comp directly in the IBIS model


If I were your customer trying to use this model, I'd be really unhappy

to find that C_comp was (silently) being double counted. And I'd

be suspicious of your model if C_comp were 0 with no explanation.


At the very least, if you don't want to re-run things, you should set

C_comp to 0 but put in a comment that the reason it's zero is that

the effects of C_comp are included in the rising/falling waveforms.


But this is definitely a distant second-best, in my opinion.


Kim


On Friday, August 1, 2003, at 02:13  PM, Abril, Giovanni wrote:


<excerpt><fontfamily><param>Arial</param><smaller>Hello IBIS =
gurus,</smaller></fontfamily>


<fontfamily><param>Arial</param><smaller>I've created an IBIS model
using a spice netlist from the vendor, and I'm wondering what to do
with C_comp.=A0 My rising and falling waveforms include the effect of
C_comp, but what should I put in the IBIS model?=A0 I have a spec sheet
that says min C_comp is 2.8pF, max is 10pF.=A0 Currently I have 5.0pF
for typ, 2.8pF min and 10pF max.</smaller></fontfamily>


<fontfamily><param>Arial</param><smaller>Thanks,</smaller></fontfamily>


<fontfamily><param>Arial</param><smaller>Giovanni</smaller></fontfamily>



</excerpt>Kim Helliwell

Apple Computer

kimgh@apple.com

408 974 9936



- --Apple-Mail-6--137288472--

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------------------------------

Date: Fri, 1 Aug 2003 15:05:09 -0700
From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject: RE: [IBIS-Users] C_comp value in IBIS model

This is a multi-part message in MIME format.

- ------_=_NextPart_001_01C35878.F93465FB
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	charset="iso-8859-1"
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Kim,
=20
I hate to argue with you, but your response is quite wrong.
=20
It is not possible, or the least very hard to remove the effects
of die capacitance from a SPICE model.  So the waveforms that
were generated from a SPICE simulation will always include the
effects of C_comp.  Also, putting such a waveform and a C_comp
value into an IBIS model will not double count C_comp.  This
is actually how IBIS simulators expect to get the data, because
they are the ones who do the compensation to avoid double counting.
=20
So Giovanni did exactly the right thing.
=20
The only thing he needs to watch out for is that if he does a
SPICE vs. IBIS correlation, he should have the value for C_comp
in the IBIS model that was measured on the SPICE model, and not
the data sheet number, because the two may not be the same value.
For correlation work.  However, if the IBIS model needs to be
according to the data book, using the data book values is the right
thing to do.  (Remember, the SPICE model may not have all the
layout related extra capacitances in the circuit, which is the
case most often when someone has a pre layout model).
=20
Arpad Muranyi
Intel Corporation
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
=20
- -----Original Message-----
From: Kim Helliwell [mailto:kimgh@apple.com]
Sent: Friday, August 01, 2003 2:45 PM
To: Abril, Giovanni
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] C_comp value in IBIS model


If the waveforms already include the effects of C_comp, putting=20
the C_comp value in the IBIS model will double-count the effect=20
of C_comp, which is probably not what you want.=20

I feel certain that the right thing to do is re-run the spice sims=20
with C_comp removed from the simulations, and put the correct=20
typ/min/max values of C_comp directly in the IBIS model=20

If I were your customer trying to use this model, I'd be really unhappy=20
to find that C_comp was (silently) being double counted. And I'd=20
be suspicious of your model if C_comp were 0 with no explanation.=20

At the very least, if you don't want to re-run things, you should set=20
C_comp to 0 but put in a comment that the reason it's zero is that=20
the effects of C_comp are included in the rising/falling waveforms.=20

But this is definitely a distant second-best, in my opinion.=20

Kim=20

On Friday, August 1, 2003, at 02:13 PM, Abril, Giovanni wrote:=20


Hello IBIS gurus,=20

I've created an IBIS model using a spice netlist from the vendor, and =
I'm wondering what to do with C_comp.  My rising and falling waveforms =
include the effect of C_comp, but what should I put in the IBIS model?  =
I have a spec sheet that says min C_comp is 2.8pF, max is 10pF.  =
Currently I have 5.0pF for typ, 2.8pF min and 10pF max.=20

Thanks,=20

Giovanni=20



Kim Helliwell=20
Apple Computer=20
kimgh@apple.com=20
408 974 9936=20


- ------_=_NextPart_001_01C35878.F93465FB
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	charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<TITLE></TITLE>

<META content=3D"MSHTML 6.00.2716.2200" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D406305921-01082003>Kim,</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>I hate to=20
argue with you, but your response is quite wrong.</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>It is not=20
possible, or the least very hard to remove the =
effects</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>of die=20
capacitance from a SPICE model.&nbsp; So the waveforms =
that</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>were=20
generated from a SPICE simulation will always include =
the</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>effects of=20
C_comp.&nbsp; Also, putting such a waveform and a =
C_comp</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>value into=20
an IBIS model will not double count C_comp.&nbsp; =
This</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>is actually=20
how IBIS simulators expect to get the data, because</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>they are the=20
ones who do the compensation to avoid double =
counting.</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>So Giovanni=20
did exactly the right thing.</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>The only=20
thing he needs to watch out for is that if he does a</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>SPICE vs.=20
IBIS correlation, he should have the value for =
C_comp</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>in the IBIS=20
model that was measured on the SPICE model, and not</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>the data=20
sheet number, because the two may not be the same =
value.</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>For=20
correlation work.&nbsp; However, if the IBIS model needs to=20
be</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>according to=20
the data book, using the data book values is the =
right</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>thing to=20
do.&nbsp; (Remember, the SPICE model may not have all =
the</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>layout=20
related extra capacitances in the circuit, which is =
the</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>case most=20
often when someone has a pre layout model).</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>Arpad=20
Muranyi</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>Intel=20
Corporation</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D406305921-01082003>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<=
/SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Kim Helliwell=20
[mailto:kimgh@apple.com]<BR><B>Sent:</B> Friday, August 01, 2003 2:45=20
PM<BR><B>To:</B> Abril, Giovanni<BR><B>Cc:</B>=20
ibis-users@eda.org<BR><B>Subject:</B> Re: [IBIS-Users] C_comp value in =
IBIS=20
model<BR><BR></FONT></DIV><!-- Converted from text/enriched format -->
<DIV>If the waveforms already include the effects of C_comp, putting =
</DIV>
<DIV>the C_comp value in the IBIS model will double-count the effect =
</DIV>
<DIV>of C_comp, which is probably not what you want. </DIV><BR>
<DIV>I feel certain that the right thing to do is re-run the spice sims =
</DIV>
<DIV>with C_comp removed from the simulations, and put the correct =
</DIV>
<DIV>typ/min/max values of C_comp directly in the IBIS model </DIV><BR>
<DIV>If I were your customer trying to use this model, I'd be really =
unhappy=20
</DIV>
<DIV>to find that C_comp was (silently) being double counted. And I'd =
</DIV>
<DIV>be suspicious of your model if C_comp were 0 with no explanation.=20
</DIV><BR>
<DIV>At the very least, if you don't want to re-run things, you should =
set=20
</DIV>
<DIV>C_comp to 0 but put in a comment that the reason it's zero is that =
</DIV>
<DIV>the effects of C_comp are included in the rising/falling waveforms. =

</DIV><BR>
<DIV>But this is definitely a distant second-best, in my opinion. =
</DIV><BR>
<DIV>Kim </DIV><BR>
<DIV>On Friday, August 1, 2003, at 02:13 PM, Abril, Giovanni wrote: =
</DIV><BR>
<BLOCKQUOTE>
  <DIV><FONT face=3DArial><SMALL>Hello IBIS gurus,</SMALL></FONT> =
</DIV><BR>
  <DIV><FONT face=3DArial><SMALL>I've created an IBIS model using a =
spice netlist=20
  from the vendor, and I'm wondering what to do with C_comp.&nbsp; My =
rising and=20
  falling waveforms include the effect of C_comp, but what should I put =
in the=20
  IBIS model?&nbsp; I have a spec sheet that says min C_comp is 2.8pF, =
max is=20
  10pF.&nbsp; Currently I have 5.0pF for typ, 2.8pF min and 10pF=20
  max.</SMALL></FONT> </DIV><BR>
  <DIV><FONT face=3DArial><SMALL>Thanks,</SMALL></FONT> </DIV><BR>
  <DIV><FONT face=3DArial><SMALL>Giovanni</SMALL></FONT> =
</DIV><BR><BR></BLOCKQUOTE>
<DIV>Kim Helliwell </DIV>
<DIV>Apple Computer </DIV>
<DIV>kimgh@apple.com </DIV>
<DIV>408 974 9936 </DIV><BR></BODY></HTML>

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------------------------------

Date: Fri, 1 Aug 2003 15:02:22 -0700
From: "Jeremy Plunkett" <jeremy@serverworks.com>
Subject: RE: [IBIS-Users] C_comp value in IBIS model

This is a multi-part message in MIME format.

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Kim,
actually a simulator which implements IBIS correctly will "cancel out" the
effects of C_comp on the output waveform.  However the C_comp will be
present as part of the input loading that the buffer presents to the bus.

In practice there is probably a limit to how far you can tweak C_comp away
from the real value for most simulators.  When I tried it in Hspice,
changing C_comp from the "correct" value to 0pF results in minimal changes
to the output waveform, but changing C_comp to 100x the correct value does
cause noticeable changes (but not what you might expect).

It's generally not possible to remove C_comp from the simulations when the
model is generated, since in most cases a large portion of C_comp is due to
the output transistors, and if you take those out of the netlist you won't
have much luck getting the IBIS data.

Jeremy
  -----Original Message-----
  From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf
Of Kim Helliwell
  Sent: Friday, August 01, 2003 2:45 PM
  To: Abril, Giovanni
  Cc: ibis-users@eda.org
  Subject: Re: [IBIS-Users] C_comp value in IBIS model


  If the waveforms already include the effects of C_comp, putting
  the C_comp value in the IBIS model will double-count the effect
  of C_comp, which is probably not what you want.

  I feel certain that the right thing to do is re-run the spice sims
  with C_comp removed from the simulations, and put the correct
  typ/min/max values of C_comp directly in the IBIS model

  If I were your customer trying to use this model, I'd be really unhappy
  to find that C_comp was (silently) being double counted. And I'd
  be suspicious of your model if C_comp were 0 with no explanation.

  At the very least, if you don't want to re-run things, you should set
  C_comp to 0 but put in a comment that the reason it's zero is that
  the effects of C_comp are included in the rising/falling waveforms.

  But this is definitely a distant second-best, in my opinion.

  Kim

  On Friday, August 1, 2003, at 02:13 PM, Abril, Giovanni wrote:


    Hello IBIS gurus,

    I've created an IBIS model using a spice netlist from the vendor, and
I'm wondering what to do with C_comp.  My rising and falling waveforms
include the effect of C_comp, but what should I put in the IBIS model?  I
have a spec sheet that says min C_comp is 2.8pF, max is 10pF.  Currently I
have 5.0pF for typ, 2.8pF min and 10pF max.

    Thanks,

    Giovanni



  Kim Helliwell
  Apple Computer
  kimgh@apple.com
  408 974 9936



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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3315.2870" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D687325321-01082003>Kim,</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D687325321-01082003>actually a simulator which implements IBIS =
correctly=20
will "cancel out" the effects of C_comp on the output waveform.&nbsp; =
However=20
the C_comp will be present as part of the input loading that the buffer =
presents=20
to the bus.</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D687325321-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D687325321-01082003>In=20
practice there is probably a limit to how far you can tweak C_comp away =
from the=20
real value for most simulators.&nbsp; When I tried it in Hspice, =
changing C_comp=20
from the "correct" value to 0pF results in minimal changes to the output =

waveform, but changing C_comp to 100x the correct value does cause =
noticeable=20
changes (but not what you might expect).</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D687325321-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D687325321-01082003>It's=20
generally not possible to remove C_comp from the simulations when the =
model is=20
generated, since in most cases a large portion of C_comp is due to the =
output=20
transistors, and if you take those out of the netlist you won't have =
much luck=20
getting the IBIS data.</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D687325321-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D687325321-01082003>Jeremy</SPAN></FONT></DIV>
<BLOCKQUOTE>
  <DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> =
owner-ibis-users@eda.org=20
  [mailto:owner-ibis-users@eda.org]<B>On Behalf Of </B>Kim=20
  Helliwell<BR><B>Sent:</B> Friday, August 01, 2003 2:45 =
PM<BR><B>To:</B> Abril,=20
  Giovanni<BR><B>Cc:</B> ibis-users@eda.org<BR><B>Subject:</B> Re: =
[IBIS-Users]=20
  C_comp value in IBIS model<BR><BR></DIV></FONT>If the waveforms =
already=20
  include the effects of C_comp, putting<BR>the C_comp value in the IBIS =
model=20
  will double-count the effect<BR>of C_comp, which is probably not what =
you=20
  want.<BR><BR>I feel certain that the right thing to do is re-run the =
spice=20
  sims<BR>with C_comp removed from the simulations, and put the=20
  correct<BR>typ/min/max values of C_comp directly in the IBIS =
model<BR><BR>If I=20
  were your customer trying to use this model, I'd be really =
unhappy<BR>to find=20
  that C_comp was (silently) being double counted. And I'd<BR>be =
suspicious of=20
  your model if C_comp were 0 with no explanation.<BR><BR>At the very =
least, if=20
  you don't want to re-run things, you should set<BR>C_comp to 0 but put =
in a=20
  comment that the reason it's zero is that<BR>the effects of C_comp are =

  included in the rising/falling waveforms.<BR><BR>But this is =
definitely a=20
  distant second-best, in my opinion.<BR><BR>Kim<BR><BR>On Friday, =
August 1,=20
  2003, at 02:13 PM, Abril, Giovanni wrote:<BR><BR>
  <BLOCKQUOTE><?fontfamily><?param Arial><?smaller>Hello IBIS =
gurus,<?/smaller><?/fontfamily><BR><BR><?fontfamily><?param =
Arial><?smaller>I've=20
    created an IBIS model using a spice netlist from the vendor, and I'm =

    wondering what to do with C_comp.&nbsp; My rising and falling =
waveforms=20
    include the effect of C_comp, but what should I put in the IBIS =
model?&nbsp;=20
    I have a spec sheet that says min C_comp is 2.8pF, max is =
10pF.&nbsp;=20
    Currently I have 5.0pF for typ, 2.8pF min and 10pF =
max.<?/smaller><?/fontfamily><BR><BR><?fontfamily><?param =
Arial><?smaller>Thanks,<?/smaller><?/fontfamily><BR><BR><?fontfamily><?pa=
ram =
Arial><?smaller>Giovanni<?/smaller><?/fontfamily><BR><BR><BR></BLOCKQUOTE=
>Kim=20
  Helliwell<BR>Apple Computer<BR>kimgh@apple.com<BR>408 974=20
9936<BR><BR></BLOCKQUOTE></BODY></HTML>

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------------------------------

Date: Fri, 1 Aug 2003 15:16:15 -0700 
From: "Beal, Weston" <weston_beal@mentorg.com>
Subject: RE: [IBIS-Users] C_comp value in IBIS model

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The effect of C_comp is only double counted if you are using a substandard simulator.  All the major simulators that I know of expect C_comp to be specified with the same (static approximation) value as what is included in the waveforms.  Somewhere in the simulator this is reconciled.  Usually it is done is such a way that the capacitive effect is calculated out of the waveforms and then the lumped capacitor is present at the pin during the transient simulation..
 
As Arpad noted, the capacitive effect is usually impossible to remove from the SPICE models used to derive IBIS data.  It is part of the transistor models.  Arpad and others have proposed methods of finding the best static value of the die capacitance to use for C_comp and this value needs to be there.  If you put the value of 0 for C_comp then the simulator will try to back out the capacitance and put no capacitance at the pin.  At first this seems OK because the waveforms still have all the capacitive effect.  The problem appears when a reflected signal hits this pin or if this pin is hi-Z.  There would be no capacitive loading and you would then have invalid simulations.
 
C_comp is your friend.  Embrace it.  ( and enhance it )
 
Regards,
Weston
 

- -----Original Message-----
From: Kim Helliwell [mailto:kimgh@apple.com]
Sent: Friday, August 01, 2003 2:45 PM
To: Abril, Giovanni
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] C_comp value in IBIS model



If the waveforms already include the effects of C_comp, putting 

the C_comp value in the IBIS model will double-count the effect 

of C_comp, which is probably not what you want. 


I feel certain that the right thing to do is re-run the spice sims 

with C_comp removed from the simulations, and put the correct 

typ/min/max values of C_comp directly in the IBIS model 


If I were your customer trying to use this model, I'd be really unhappy 

to find that C_comp was (silently) being double counted. And I'd 

be suspicious of your model if C_comp were 0 with no explanation. 


At the very least, if you don't want to re-run things, you should set 

C_comp to 0 but put in a comment that the reason it's zero is that 

the effects of C_comp are included in the rising/falling waveforms. 


But this is definitely a distant second-best, in my opinion. 


Kim 


On Friday, August 1, 2003, at 02:13 PM, Abril, Giovanni wrote: 


Hello IBIS gurus, 


I've created an IBIS model using a spice netlist from the vendor, and I'm wondering what to do with C_comp.  My rising and falling waveforms include the effect of C_comp, but what should I put in the IBIS model?  I have a spec sheet that says min C_comp is 2.8pF, max is 10pF.  Currently I have 5.0pF for typ, 2.8pF min and 10pF max. 


Thanks, 


Giovanni 



Kim Helliwell 

Apple Computer 

kimgh@apple.com 

408 974 9936 



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<DIV><SPAN class=495500522-01082003><FONT face=Arial color=#0000ff size=2>The 
effect of C_comp is only double counted if you are using a substandard 
simulator.&nbsp; All the major simulators that I know of expect C_comp to be 
specified with the same (static approximation) value as what is included in the 
waveforms.&nbsp; Somewhere in the simulator this is reconciled.&nbsp; Usually it 
is done is such a way that the capacitive effect is calculated out of the 
waveforms and then the lumped capacitor is present at the pin during the 
transient simulation..</FONT></SPAN></DIV>
<DIV><SPAN class=495500522-01082003><FONT face=Arial color=#0000ff 
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=495500522-01082003><FONT face=Arial color=#0000ff size=2>As 
Arpad noted, the capacitive effect is usually impossible to remove from the 
SPICE models used to derive IBIS data.&nbsp; It is part of the transistor 
models.&nbsp; Arpad and others have proposed methods of finding the best static 
value of the die capacitance to use for C_comp and this value needs to be 
there.&nbsp; If you put the value of 0 for C_comp then the simulator will try to 
back out the capacitance and put no capacitance at the pin.&nbsp; At first this 
seems OK because the waveforms still have all the capacitive effect.&nbsp; The 
problem appears when a reflected signal hits this pin or if this pin is 
hi-Z.&nbsp; There would be no capacitive loading and you would then have invalid 
simulations.</FONT></SPAN></DIV>
<DIV><SPAN class=495500522-01082003><FONT face=Arial color=#0000ff 
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=495500522-01082003><FONT face=Arial color=#0000ff size=2>C_comp 
is your friend.&nbsp; Embrace it.&nbsp; ( and enhance it )</FONT></SPAN></DIV>
<DIV><SPAN class=495500522-01082003><FONT face=Arial color=#0000ff 
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=495500522-01082003><FONT face=Arial color=#0000ff 
size=2>Regards,</FONT></SPAN></DIV>
<DIV><SPAN class=495500522-01082003><FONT face=Arial color=#0000ff 
size=2>Weston</FONT></SPAN></DIV>
<DIV><SPAN class=495500522-01082003></SPAN>&nbsp;</DIV>
<BLOCKQUOTE>
  <DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Kim Helliwell 
  [mailto:kimgh@apple.com]<BR><B>Sent:</B> Friday, August 01, 2003 2:45 
  PM<BR><B>To:</B> Abril, Giovanni<BR><B>Cc:</B> 
  ibis-users@eda.org<BR><B>Subject:</B> Re: [IBIS-Users] C_comp value in IBIS 
  model<BR><BR></FONT></DIV>
  <P>If the waveforms already include the effects of C_comp, putting </P>
  <P>the C_comp value in the IBIS model will double-count the effect </P>
  <P>of C_comp, which is probably not what you want. </P><BR>
  <P>I feel certain that the right thing to do is re-run the spice sims </P>
  <P>with C_comp removed from the simulations, and put the correct </P>
  <P>typ/min/max values of C_comp directly in the IBIS model </P><BR>
  <P>If I were your customer trying to use this model, I'd be really unhappy 
</P>
  <P>to find that C_comp was (silently) being double counted. And I'd </P>
  <P>be suspicious of your model if C_comp were 0 with no explanation. </P><BR>
  <P>At the very least, if you don't want to re-run things, you should set </P>
  <P>C_comp to 0 but put in a comment that the reason it's zero is that </P>
  <P>the effects of C_comp are included in the rising/falling waveforms. 
</P><BR>
  <P>But this is definitely a distant second-best, in my opinion. </P><BR>
  <P>Kim </P><BR>
  <P>On Friday, August 1, 2003, at 02:13 PM, Abril, Giovanni wrote: </P><BR>
  <P><FONT face=Arial size=2>Hello IBIS gurus,</FONT> </P><BR>
  <P><FONT face=Arial size=2>I've created an IBIS model using a spice netlist 
  from the vendor, and I'm wondering what to do with C_comp.&nbsp; My rising and 
  falling waveforms include the effect of C_comp, but what should I put in the 
  IBIS model?&nbsp; I have a spec sheet that says min C_comp is 2.8pF, max is 
  10pF.&nbsp; Currently I have 5.0pF for typ, 2.8pF min and 10pF max.</FONT> 
  </P><BR>
  <P><FONT face=Arial size=2>Thanks,</FONT> </P><BR>
  <P><FONT face=Arial size=2>Giovanni</FONT> </P><BR><BR>
  <P>Kim Helliwell </P>
  <P>Apple Computer </P>
  <P>kimgh@apple.com </P>
  <P>408 974 9936 </P><BR></BLOCKQUOTE></BODY></HTML>

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------------------------------

Date: Fri, 1 Aug 2003 15:15:54 -0700
From: "Abril, Giovanni" <giovanni.abril@ngc.com>
Subject: RE: [IBIS-Users] C_comp value in IBIS model

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Hi Arpad,
=20
You are right, the tool, IS from Mentor Graphics says it does not double =
count C_comp, instead they create "Internal Waveforms" based on the =
C_comp found in the model.  I suppose the problem is that, the SPICE =
netlist may have had a C_comp of say, 3pF, but my max value is 10pF, I =
think IS assumes the model was created with 10pF.  I guess I should =
contact them and ask them.
=20
Thanks,
Giovanni

- -----Original Message-----
From: Muranyi, Arpad [mailto:arpad.muranyi@intel.com]
Sent: Friday, August 01, 2003 3:05 PM
To: ibis-users@eda.org
Subject: RE: [IBIS-Users] C_comp value in IBIS model


Kim,
=20
I hate to argue with you, but your response is quite wrong.
=20
It is not possible, or the least very hard to remove the effects
of die capacitance from a SPICE model.  So the waveforms that
were generated from a SPICE simulation will always include the
effects of C_comp.  Also, putting such a waveform and a C_comp
value into an IBIS model will not double count C_comp.  This
is actually how IBIS simulators expect to get the data, because
they are the ones who do the compensation to avoid double counting.
=20
So Giovanni did exactly the right thing.
=20
The only thing he needs to watch out for is that if he does a
SPICE vs. IBIS correlation, he should have the value for C_comp
in the IBIS model that was measured on the SPICE model, and not
the data sheet number, because the two may not be the same value.
For correlation work.  However, if the IBIS model needs to be
according to the data book, using the data book values is the right
thing to do.  (Remember, the SPICE model may not have all the
layout related extra capacitances in the circuit, which is the
case most often when someone has a pre layout model).
=20
Arpad Muranyi
Intel Corporation
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
=20
- -----Original Message-----
From: Kim Helliwell [mailto:kimgh@apple.com]
Sent: Friday, August 01, 2003 2:45 PM
To: Abril, Giovanni
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] C_comp value in IBIS model


If the waveforms already include the effects of C_comp, putting=20
the C_comp value in the IBIS model will double-count the effect=20
of C_comp, which is probably not what you want.=20

I feel certain that the right thing to do is re-run the spice sims=20
with C_comp removed from the simulations, and put the correct=20
typ/min/max values of C_comp directly in the IBIS model=20

If I were your customer trying to use this model, I'd be really unhappy=20
to find that C_comp was (silently) being double counted. And I'd=20
be suspicious of your model if C_comp were 0 with no explanation.=20

At the very least, if you don't want to re-run things, you should set=20
C_comp to 0 but put in a comment that the reason it's zero is that=20
the effects of C_comp are included in the rising/falling waveforms.=20

But this is definitely a distant second-best, in my opinion.=20

Kim=20

On Friday, August 1, 2003, at 02:13 PM, Abril, Giovanni wrote:=20


Hello IBIS gurus,=20

I've created an IBIS model using a spice netlist from the vendor, and =
I'm wondering what to do with C_comp.  My rising and falling waveforms =
include the effect of C_comp, but what should I put in the IBIS model?  =
I have a spec sheet that says min C_comp is 2.8pF, max is 10pF.  =
Currently I have 5.0pF for typ, 2.8pF min and 10pF max.=20

Thanks,=20

Giovanni=20



Kim Helliwell=20
Apple Computer=20
kimgh@apple.com=20
408 974 9936=20



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<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D289430822-01082003>Hi=20
Arpad,</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D289430822-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D289430822-01082003>You=20
are right, the tool, IS from Mentor Graphics says it does not double =
count=20
C_comp, instead they create "Internal Waveforms" based on the C_comp =
found in=20
the model.&nbsp; I suppose the problem is that, the SPICE netlist may =
have had a=20
C_comp of say, 3pF, but my max value is 10pF, I think IS assumes the =
model was=20
created with 10pF.&nbsp; I guess I should contact them and ask=20
them.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D289430822-01082003></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D289430822-01082003>Thanks,</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D289430822-01082003>Giovanni</SPAN></FONT></DIV>
<BLOCKQUOTE>
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> Muranyi, Arpad=20
  [mailto:arpad.muranyi@intel.com]<BR><B>Sent:</B> Friday, August 01, =
2003 3:05=20
  PM<BR><B>To:</B> ibis-users@eda.org<BR><B>Subject:</B> RE: =
[IBIS-Users] C_comp=20
  value in IBIS model<BR><BR></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
  class=3D406305921-01082003>Kim,</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
  class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>I hate to=20
  argue with you, but your response is quite wrong.</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
  class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>It is not=20
  possible, or the least very hard to remove the =
effects</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>of die=20
  capacitance from a SPICE model.&nbsp; So the waveforms=20
that</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>were=20
  generated from a SPICE simulation will always include =
the</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>effects of=20
  C_comp.&nbsp; Also, putting such a waveform and a =
C_comp</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>value into=20
  an IBIS model will not double count C_comp.&nbsp; =
This</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>is=20
  actually how IBIS simulators expect to get the data,=20
  because</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>they are=20
  the ones who do the compensation to avoid double =
counting.</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
  class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>So=20
  Giovanni did exactly the right thing.</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
  class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>The only=20
  thing he needs to watch out for is that if he does =
a</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>SPICE vs.=20
  IBIS correlation, he should have the value for =
C_comp</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>in the=20
  IBIS model that was measured on the SPICE model, and =
not</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>the data=20
  sheet number, because the two may not be the same =
value.</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>For=20
  correlation work.&nbsp; However, if the IBIS model needs to=20
  be</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>according=20
  to the data book, using the data book values is the =
right</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>thing to=20
  do.&nbsp; (Remember, the SPICE model may not have all =
the</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>layout=20
  related extra capacitances in the circuit, which is =
the</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>case most=20
  often when someone has a pre layout model).</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
  class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>Arpad=20
  Muranyi</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D406305921-01082003>Intel=20
  Corporation</SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
  =
class=3D406305921-01082003>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<=
/SPAN></FONT></DIV>
  <DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
  class=3D406305921-01082003></SPAN></FONT>&nbsp;</DIV>
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> Kim Helliwell=20
  [mailto:kimgh@apple.com]<BR><B>Sent:</B> Friday, August 01, 2003 2:45=20
  PM<BR><B>To:</B> Abril, Giovanni<BR><B>Cc:</B>=20
  ibis-users@eda.org<BR><B>Subject:</B> Re: [IBIS-Users] C_comp value in =
IBIS=20
  model<BR><BR></FONT></DIV><!-- Converted from text/enriched format -->
  <DIV>If the waveforms already include the effects of C_comp, putting =
</DIV>
  <DIV>the C_comp value in the IBIS model will double-count the effect =
</DIV>
  <DIV>of C_comp, which is probably not what you want. </DIV><BR>
  <DIV>I feel certain that the right thing to do is re-run the spice =
sims </DIV>
  <DIV>with C_comp removed from the simulations, and put the correct =
</DIV>
  <DIV>typ/min/max values of C_comp directly in the IBIS model =
</DIV><BR>
  <DIV>If I were your customer trying to use this model, I'd be really =
unhappy=20
  </DIV>
  <DIV>to find that C_comp was (silently) being double counted. And I'd =
</DIV>
  <DIV>be suspicious of your model if C_comp were 0 with no explanation. =

  </DIV><BR>
  <DIV>At the very least, if you don't want to re-run things, you should =
set=20
  </DIV>
  <DIV>C_comp to 0 but put in a comment that the reason it's zero is =
that </DIV>
  <DIV>the effects of C_comp are included in the rising/falling =
waveforms.=20
  </DIV><BR>
  <DIV>But this is definitely a distant second-best, in my opinion. =
</DIV><BR>
  <DIV>Kim </DIV><BR>
  <DIV>On Friday, August 1, 2003, at 02:13 PM, Abril, Giovanni wrote: =
</DIV><BR>
  <BLOCKQUOTE>
    <DIV><FONT face=3DArial><SMALL>Hello IBIS gurus,</SMALL></FONT> =
</DIV><BR>
    <DIV><FONT face=3DArial><SMALL>I've created an IBIS model using a =
spice=20
    netlist from the vendor, and I'm wondering what to do with =
C_comp.&nbsp; My=20
    rising and falling waveforms include the effect of C_comp, but what =
should I=20
    put in the IBIS model?&nbsp; I have a spec sheet that says min =
C_comp is=20
    2.8pF, max is 10pF.&nbsp; Currently I have 5.0pF for typ, 2.8pF min =
and 10pF=20
    max.</SMALL></FONT> </DIV><BR>
    <DIV><FONT face=3DArial><SMALL>Thanks,</SMALL></FONT> </DIV><BR>
    <DIV><FONT face=3DArial><SMALL>Giovanni</SMALL></FONT>=20
  </DIV><BR><BR></BLOCKQUOTE>
  <DIV>Kim Helliwell </DIV>
  <DIV>Apple Computer </DIV>
  <DIV>kimgh@apple.com </DIV>
  <DIV>408 974 9936 </DIV><BR></BLOCKQUOTE></BODY></HTML>

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