From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #48 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Thursday, December 30 2004 Volume 01 : Number 048 ---------------------------------------------------------------------- Date: Tue, 14 Dec 2004 08:36:27 -0800 From: Bob Ross Subject: [IBIS-Users] IBIS Summit Meeitng at DesignCon - Second Annoucement To All: This message from Syed Huq is being resent because of possible IBIS reflector problems: - -------------- DesignCon is offering 20% off all conferences packages through Dec15, 2004: http://www.designcon.com/registration/index.html If you register for the Exhibits before December 15th, registration is free. After Dec. 15th, the cost will be $75. So if you are unsure whether you will attend, we recommend registering before Dec 15th. - ----------------------------------------------------------------------- IBIS SUMMIT SECOND CALL FOR PARTICIPATION & PRESENTATIONS - ----------------------------------------------------------------------- I B I S S U M M I T M E E T I N G Time/Date: Monday January 31st, 2005 8:00 AM to 5 PM Location: Santa Clara Convention Center Santa Clara, CA Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: DesignCon If your company would be interested in sponsoring this event, please contact Syed Huq . Benefits to sponsors include formal recognition at the meeting and acknowledgement in the Calls for Papers and meeting minutes. Your financial support strengthens the organization by allowing IBIS to focus resources on industry activities rather than raising money, and you will receive generous thanks for your support. DesignCon Conference January 31- February 3rd, 2005 Santa Clara Convention Center Santa Clara, CA Exhibit registration is Free if you register before December 15, 2004. Come and visit IBIS Booth . See http://www.designcon.com/ for more information. Conference Catalog: http://www.eda.org/pub/ibis/summits/jan05/DC05_Catalog.pdf BACKGROUND DesignCon is the premier annual Silicon Valley event for the electronic design automation (EDA) and semiconductor industry. Topics of current interest to the EIA IBIS Open Forum are addressed at DesignCon. This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. Any pending formal decisions (votes) will be announced at least two weeks prior to the meeting. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Send to: Syed Huq CALL FOR PRESENTATIONS We are seeking presentations from individuals who have experiences of interest to the IBIS modeling community. In the past, these have included demonstrations of modeling techniques, explanations of behavioral algorithms and descriptions of difficulties encountered in specific applications. Of particular interest are topics related to model correlation, modeling building experiences and comparisons to other modeling methods. Presentations may be addressed to any and all levels of IBIS experience, from beginning to advanced. Format of Presentation: LCD Projection with Windows laptop. Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat. Electronic presentations should be made available by January 21, 2005 for uploading and copying to the presentation laptop. Presentors are responsible for bringing 50 copies if not received by January 21. If you plan a presentation, please supply Title: Presenter: E-mail address: Company: Telephone: Estimated Time: Send this to: Syed Huq AGENDA The agenda includes presentations, discussions, breaks, and a luncheon (which will be provided). This will be developed as presentation proposals are received. Please pre-register with Syed Huq(shuq@cisco.com) by January 15, 2005 to reserve a free lunch spot. LIST OF NEARBY HOTELS See for travel directions, hotels and other information. - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 503-750-6481 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 13 Dec 2004 10:06:15 -0800 From: Syed Huq Subject: [IBIS-Users] IBIS Summit At DesignCon2005 - Second Call for Paper DesignCon is offering 20% off all conferences packages through Dec15, 2004: http://www.designcon.com/registration/index.html If you register for the Exhibits before December 15th, registration is free. After Dec. 15th, the cost will be $75. So if you are unsure whether you will attend, we recommend registering before Dec 15th. - ----------------------------------------------------------------------- IBIS SUMMIT SECOND CALL FOR PARTICIPATION & PRESENTATIONS - ----------------------------------------------------------------------- I B I S S U M M I T M E E T I N G Time/Date: Monday January 31st, 2005 8:00 AM to 5 PM Location: Santa Clara Convention Center Santa Clara, CA Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: DesignCon If your company would be interested in sponsoring this event, please contact Syed Huq . Benefits to sponsors include formal recognition at the meeting and acknowledgement in the Calls for Papers and meeting minutes. Your financial support strengthens the organization by allowing IBIS to focus resources on industry activities rather than raising money, and you will receive generous thanks for your support. DesignCon Conference January 31- February 3rd, 2005 Santa Clara Convention Center Santa Clara, CA Exhibit registration is Free if you register before December 15, 2004. Come and visit IBIS Booth . See http://www.designcon.com/ for more information. Conference Catalog: http://www.eda.org/pub/ibis/summits/jan05/DC05_Catalog.pdf BACKGROUND DesignCon is the premier annual Silicon Valley event for the electronic design automation (EDA) and semiconductor industry. Topics of current interest to the EIA IBIS Open Forum are addressed at DesignCon. This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. Any pending formal decisions (votes) will be announced at least two weeks prior to the meeting. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Send to: Syed Huq CALL FOR PRESENTATIONS We are seeking presentations from individuals who have experiences of interest to the IBIS modeling community. In the past, these have included demonstrations of modeling techniques, explanations of behavioral algorithms and descriptions of difficulties encountered in specific applications. Of particular interest are topics related to model correlation, modeling building experiences and comparisons to other modeling methods. Presentations may be addressed to any and all levels of IBIS experience, from beginning to advanced. Format of Presentation: LCD Projection with Windows laptop. Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat. Electronic presentations should be made available by January 21, 2005 for uploading and copying to the presentation laptop. Presentors are responsible for bringing 50 copies if not received by January 21. If you plan a presentation, please supply Title: Presenter: E-mail address: Company: Telephone: Estimated Time: Send this to: Syed Huq AGENDA The agenda includes presentations, discussions, breaks, and a luncheon (which will be provided). This will be developed as presentation proposals are received. Please pre-register with Syed Huq(shuq@cisco.com) by January 15, 2005 to reserve a free lunch spot. LIST OF NEARBY HOTELS See for travel directions, hotels and other information. - ----------------------------------------------------------------- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 13 Dec 2004 13:29:21 -0800 From: Syed Huq Subject: [IBIS-Users] Re: IBIS Summit At DesignCon2005 - Second Call for Paper - --=-GbQVD2wSrgIt2OwxsA2Z Content-Type: text/plain Content-Transfer-Encoding: 7bit RESENDING - Syed - --=-GbQVD2wSrgIt2OwxsA2Z Content-Disposition: inline Content-Description: Forwarded message - IBIS Summit At DesignCon2005 - Second Call for Paper Content-Type: message/rfc822 Subject: IBIS Summit At DesignCon2005 - Second Call for Paper From: Syed Huq To: ibis@eda.org, ibis-users@eda.org Content-Type: text/plain Organization: Cisco Systems, Inc Message-Id: <1102961175.578.18.camel@asipd01-lnx.cisco.com> Mime-Version: 1.0 X-Mailer: Ximian Evolution 1.4.5 Date: Mon, 13 Dec 2004 10:06:15 -0800 Content-Transfer-Encoding: 7bit DesignCon is offering 20% off all conferences packages through Dec15, 2004: http://www.designcon.com/registration/index.html If you register for the Exhibits before December 15th, registration is free. After Dec. 15th, the cost will be $75. So if you are unsure whether you will attend, we recommend registering before Dec 15th. - ----------------------------------------------------------------------- IBIS SUMMIT SECOND CALL FOR PARTICIPATION & PRESENTATIONS - ----------------------------------------------------------------------- I B I S S U M M I T M E E T I N G Time/Date: Monday January 31st, 2005 8:00 AM to 5 PM Location: Santa Clara Convention Center Santa Clara, CA Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: DesignCon If your company would be interested in sponsoring this event, please contact Syed Huq . Benefits to sponsors include formal recognition at the meeting and acknowledgement in the Calls for Papers and meeting minutes. Your financial support strengthens the organization by allowing IBIS to focus resources on industry activities rather than raising money, and you will receive generous thanks for your support. DesignCon Conference January 31- February 3rd, 2005 Santa Clara Convention Center Santa Clara, CA Exhibit registration is Free if you register before December 15, 2004. Come and visit IBIS Booth . See http://www.designcon.com/ for more information. Conference Catalog: http://www.eda.org/pub/ibis/summits/jan05/DC05_Catalog.pdf BACKGROUND DesignCon is the premier annual Silicon Valley event for the electronic design automation (EDA) and semiconductor industry. Topics of current interest to the EIA IBIS Open Forum are addressed at DesignCon. This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. Any pending formal decisions (votes) will be announced at least two weeks prior to the meeting. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Send to: Syed Huq CALL FOR PRESENTATIONS We are seeking presentations from individuals who have experiences of interest to the IBIS modeling community. In the past, these have included demonstrations of modeling techniques, explanations of behavioral algorithms and descriptions of difficulties encountered in specific applications. Of particular interest are topics related to model correlation, modeling building experiences and comparisons to other modeling methods. Presentations may be addressed to any and all levels of IBIS experience, from beginning to advanced. Format of Presentation: LCD Projection with Windows laptop. Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat. Electronic presentations should be made available by January 21, 2005 for uploading and copying to the presentation laptop. Presentors are responsible for bringing 50 copies if not received by January 21. If you plan a presentation, please supply Title: Presenter: E-mail address: Company: Telephone: Estimated Time: Send this to: Syed Huq AGENDA The agenda includes presentations, discussions, breaks, and a luncheon (which will be provided). This will be developed as presentation proposals are received. Please pre-register with Syed Huq(shuq@cisco.com) by January 15, 2005 to reserve a free lunch spot. LIST OF NEARBY HOTELS See for travel directions, hotels and other information. - ----------------------------------------------------------------- - --=-GbQVD2wSrgIt2OwxsA2Z-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 14 Dec 2004 11:05:36 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] way to extract rising and falling waveform in differential cells Akhilesh A ramp based model simulation will start its transition immediately, there is no time delay built into the model. A SPICE simulation will include the delay of the buffer and other effects you are seeing in the SPICE output. If you want the two to match you need to include the full waveform models in the IBIS model. These waveforms need to be extracted preserving the time delay of the buffer. Using the SPICE to IBIS tools available on the IBIS web page should give you the results you want. If you need assistance in using this we can help. Tom Dagostino Teraspeed Consulting Group LLC 503-430-1065 tom@teraspeed.com www.teraspeed.com - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf Of Akhilesh CHANDRA Sent: Tuesday, December 14, 2004 5:48 AM To: ibis-users@eda.org Cc: Akhilesh CHANDRA Subject: [IBIS-Users] way to extract rising and falling waveform in differential cells Hello Friends, I am devloping IBIS model of a differential cell having swing 300mv. when I run simulation at 300mhz then I find out there is a transition shift between IBIS and spice result. In my model I give just ramp database dv/dt for transition. In my view this problem may be resolve if I give complete rising and falling waveform in my models. Is anyone know how we can extract rising and falling waveform for a cell that have differential swing or any other way to reduce this shift. My results are attached with the mail. regards Akhilesh |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 14 Dec 2004 20:12:28 -0500 From: "Dr. Edward P. Sayre" Subject: [IBIS-Users] NESA move complete and back in business Folks: NESA has completed our move to new quarters and more efficient quarters! New physical address, same phone, fax and email addresses. All data is in the signature block below. Happy Holidays to all our colleagues and friends in the IBIS organization. Sincerely, ed sayre & the NESA staff +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ | NORTH EAST SYSTEMS ASSOCIATES, INC. | | ------------------------------------- | | "High Performance Engineering & Design" | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ | Dr. Ed Sayre e-mail: esayre@nesa.com| | NESA, Inc. http://www.nesa.com/ | | 235 Littleton Road, Ste 2 Tel +1.978.392-8787 | | Westford, MA 01886 Fax +1.978.392-8686 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 15 Dec 2004 09:56:23 -0500 From: "Zanella, Fabrizio" Subject: [IBIS-Users] Hspice ibischk4 tool This is a multi-part message in MIME format. - ------_=_NextPart_001_01C4E2B6.3E68360C Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable The latest version of Synopsys Hspice, version 2004.09, uses the ibischk4 tool, version 4.0.1. In a simulation I ran yesterday, Hspice reported errors running the v4.0.1 ibischk4 with the rising and falling waveforms when using an IBIS model as a driver.=20 Here's a sample of the errors: ERROR - Model osoc2_od: The [Rising Waveform]=20 with [R_fixture]=3D60 Ohms and [V_fixture]=3D3.3V has TYP column DC endpoints of 2.02V and 3.30v, but an equivalent load applied to the model's I-V tables yields different voltages ( 2.02V and 2.02V), a difference of inf% and inf%, respectively. ERROR - Model osoc2_od: The [Falling Waveform]=20 with [R_fixture]=3D60 Ohms and [V_fixture]=3D3.3V has TYP column DC endpoints of 2.02V and 3.30v, but an equivalent load applied to the model's I-V tables yields different voltages ( 2.02V and 2.02V), a difference of inf% and inf%, respectively. =20 An engineer at the device manufacturer said there are no errors when he uses the ibischk4 v4.0.2 tool. Can someone explain what the differences are between versions 4.0.1 and 4.0.2 of the ibischk4 tool and does anyone know whether Synopsys will be moving to the latest ibischk4 tool in the Hspice simulator? Thanks and regards, =20 Fabrizio Zanella Signal Integrity Enterasys Networks Andover, MA Phone: 978-684-1340 fzanella@enterasys.com =20 - ------_=_NextPart_001_01C4E2B6.3E68360C Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

The latest version of Synopsys Hspice, version = 2004.09, uses the ibischk4 tool, version 4.0.1.   In a simulation I ran = yesterday, Hspice reported errors running the v4.0.1 ibischk4 with the rising and = falling waveforms when using an IBIS model as a driver. =

Here’s a sample of the = errors:

ERROR - Model osoc2_od: The [Rising Waveform] =

      with = [R_fixture]=3D60 Ohms and [V_fixture]=3D3.3V

      has TYP column = DC endpoints of  2.02V and  3.30v, = but

      an equivalent = load applied to the model's I-V tables yields

      different = voltages ( 2.02V and  2.02V),

      a difference of   inf% and   inf%, = respectively.

ERROR - Model osoc2_od: The [Falling = Waveform]

      with = [R_fixture]=3D60 Ohms and [V_fixture]=3D3.3V

      has TYP column = DC endpoints of  2.02V and  3.30v, = but

      an equivalent = load applied to the model's I-V tables yields

      different = voltages ( 2.02V and  2.02V),

      a difference of   inf% and   inf%, = respectively.

 

An engineer at the device manufacturer said there are = no errors when he uses the ibischk4 v4.0.2 tool.  Can someone explain = what the differences are between versions 4.0.1 and 4.0.2 of the ibischk4 = tool and does anyone know whether Synopsys will be moving to the latest ibischk4 tool = in the Hspice simulator?

Thanks and regards,

 

Fabrizio Zanella

Signal = Integrity

Enterasys = Networks

Andover, MA

Phone:  = 978-684-1340

fzanella@enterasys.com<= /font>

 

- ------_=_NextPart_001_01C4E2B6.3E68360C-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 15 Dec 2004 08:37:56 -0700 From: rrwolff@micron.com Subject: [IBIS-Users] [IBIS] Open forum minutes (12/10/04) This is a multi-part message in MIME format. - ------_=_NextPart_001_01C4E2BC.0C438C6D Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable - ------_=_NextPart_001_01C4E2BC.0C438C6D Content-Type: text/plain; name="m121004.txt" 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|------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 15 Dec 2004 21:42:20 +0530 From: Akhilesh CHANDRA Subject: Re: [IBIS-Users] way to extract rising and falling waveform in differential cells Hello Tom, Is spice to IBIS tool calculate the waveform data for differential cell also, means cell have just a swing of 300mv, because till date I am not able to see IBIS model of a differential cell that have limted swing with waveform information. With Best regards Akhilesh Tom Dagostino wrote: >Akhilesh > >A ramp based model simulation will start its transition immediately, there >is no time delay built into the model. A SPICE simulation will include the >delay of the buffer and other effects you are seeing in the SPICE output. >If you want the two to match you need to include the full waveform models in >the IBIS model. These waveforms need to be extracted preserving the time >delay of the buffer. Using the SPICE to IBIS tools available on the IBIS >web page should give you the results you want. > >If you need assistance in using this we can help. > >Tom Dagostino >Teraspeed Consulting Group LLC >503-430-1065 >tom@teraspeed.com >www.teraspeed.com > >-----Original Message----- >From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On >Behalf Of Akhilesh CHANDRA >Sent: Tuesday, December 14, 2004 5:48 AM >To: ibis-users@eda.org >Cc: Akhilesh CHANDRA >Subject: [IBIS-Users] way to extract rising and falling waveform in >differential cells > > >Hello Friends, > > I am devloping IBIS model of a differential cell having swing 300mv. >when I run simulation at 300mhz then I find out there is a transition >shift between IBIS and spice result. In my model I give just ramp >database dv/dt for transition. In my view this problem may be resolve if >I give complete rising and falling waveform in my models. > Is anyone know how we can extract rising and falling waveform for a >cell that have differential swing or any other way to reduce this shift. > > My results are attached with the mail. > >regards >Akhilesh > > > > > > |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 15 Dec 2004 09:34:16 -0800 From: Bob Ross Subject: Re: [IBIS-Users] Hspice ibischk4 tool Fabrizio: The difference between ibischk4 Version 4.0.1 and ibischk4 Version 4.0.1 is BUG82. BUG82 was serious enough to justify a special release of ibischk4. http://eda.org/pub/ibis/bugs/ibischk/index.html A text list of what verion a bug fix has been implemented exists in the bugdir.txt file link at the end of this link. Bob Zanella, Fabrizio wrote: > The latest version of Synopsys Hspice, version 2004.09, uses the > ibischk4 tool, version 4.0.1. In a simulation I ran yesterday, Hspice > reported errors running the v4.0.1 ibischk4 with the rising and falling > waveforms when using an IBIS model as a driver. > > Here’s a sample of the errors: > > ERROR - Model osoc2_od: The [Rising Waveform] > > with [R_fixture]=60 Ohms and [V_fixture]=3.3V > > has TYP column DC endpoints of 2.02V and 3.30v, but > > an equivalent load applied to the model's I-V tables yields > > different voltages ( 2.02V and 2.02V), > > a difference of inf% and inf%, respectively. > > ERROR - Model osoc2_od: The [Falling Waveform] > > with [R_fixture]=60 Ohms and [V_fixture]=3.3V > > has TYP column DC endpoints of 2.02V and 3.30v, but > > an equivalent load applied to the model's I-V tables yields > > different voltages ( 2.02V and 2.02V), > > a difference of inf% and inf%, respectively. > > > > An engineer at the device manufacturer said there are no errors when he > uses the ibischk4 v4.0.2 tool. Can someone explain what the differences > are between versions 4.0.1 and 4.0.2 of the ibischk4 tool and does > anyone know whether Synopsys will be moving to the latest ibischk4 tool > in the Hspice simulator? > > Thanks and regards, > > > > Fabrizio Zanella > > Signal Integrity > > Enterasys Networks > > Andover, MA > > Phone: 978-684-1340 > > fzanella@enterasys.com > > > - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 503-750-6481 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 16 Dec 2004 14:09:44 +0100 From: Ralf Bruening Subject: [IBIS-Users] European IBIS Summit At DATe 2005 -First Call for Paper/Call for Participation To All: We have been holding successful European IBIS Summit Meetings for the past seven years. Next year we are again holding a meeting along with DATe 05 on Friday, March 11, 2005. The purpose is to promote communication among users and developers of IBIS models in Europe. The meeting is free and open to everyone. However, you will have to register for the exhibition at DATe (to get access to the meeting room). Refreshments are planned. Below is some information on the IBIS Summit and some related events. You are invited to register and also to submit presentation proposals. Ralf Bruening Product Manager High Speed Design ZUKEN EMC Technology Center - ----------------------------------------------------------------------------------- E U R O P E A N I B I S S U M M I T M E E T I N G F I R S T C A L L F O R P A R T I C I P A T I O N Time/Date: 9:00 AM - 2:00 PM, Friday, March 11, 2004 Location: Meeting room @ ICM Messe Munich (Munich ICM Congress Center) Munich, Germany (where DATE 2005 is being held). Free DATE 2005 exhibition registration for room entry, see URL below. Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas Sponsors: Zuken, Mentor Graphics, Cadence Design Systems/Flowcad, Siemens. If your company would be interested in sponsoring this event, please contact or Ralf Bruening or Eckard Lenski from Siemens AG Benefits to sponsors include formal recognition at the meeting and mention in the Calls for Papers and meeting minutes. Your financial support strengthens the organization by allowing IBIS to focus resources on industry activities rather than raising money, and you will receive generous thanks for your support. DATE 2005 Conference: March 07-11, 2005. The IBIS meeting is scheduled the day after the DATE 2005 exhibition ends. Location: ICM International Congress Center, Munich, Germany DATE URL: http://www.date-conference.com Background: DATE (Design, Automation, and Test in Europe) is the only European event dedicated to electronic system design and test. Topics of current interest to the EIA IBIS Open Forum are addressed at DATE. This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. Any pending formal decisions (votes) will be announced at least two weeks prior to the meeting. Topics and presentations may include (list is open for further contributions): - Submitted Presentations on IBIS Topics (See below) - Information about the most recent IBIS Developments - Less formal Ad Hoc Presentations and Discussions - IBIS and Modelling Questions and Answers The meeting is free and open to everyone. However, you will have to register for the exhibition at DATe (to get access to the meeting room). Refreshments are planned. Below is some information on the IBIS Summit and some related events. You are invited to register and also to submit presentation proposals. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the European IBIS Summit meeting. If you plan to participate, please register with the information below (deadline, Febrary 25th, 2005): Name: E-mail address: Company: Telephone: Send to: Ralf Bruening (ralf.bruening@zuken.de) CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. Some suggested subjects of interest are: - IBIS Model Development Experiences - Company IBIS Standards and Requirements - Generating and Validating IBIS Models - Future IBIS Requirements - Modelling of dedicated technology issues (i.e. connectors, very high speed interfaces) - EMC/EMI IBIS Issues - Experiences using IBIS in the PCB Design process Format of Presentation: LCD or Overhead Projections Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat PDF. Electronic presentations should be made available by February the 25th, 2005. Otherwise the presentor will be expected to provide 30 copies for distribution. If you plan a presentation, please supply Title: Presenter: E-mail address: Company: Telephone: Estimate Time: Send this to both: Ralf Bruening (ralf.bruening@zuken.de) AGENDA The agenda includes presentations, discussions, breaks, and a luncheon (which will be provided). This will be developed as presentation proposals are received. LIST OF NEARBY HOTELS See for travel directions, hotels and other information. Looking forward to meeting you at DATe 2005 in Munich Ralf Bruening _____________________________________________ Ralf Bruening Product Manager High Speed Design/Partner & Solution Business Zuken EMC Technology Center Vattmannstr.3 33100 Paderborn Germany Tel: ++49 (0) 5251 150 600 (direct -621) Fax: ++49 (0) 5251 150 700 Cellular: +49 170 4228512 (alternative: +49 172 9070675) Email: ralf.bruening@zuken.de Web: www.zuken.com _____________________________________________ This message is for the designated recipient only and may contain privileged, proprietary, or otherwise private information. If you have received it in error, please notify the sender immediately and delete the original. Any other use of the email by you is prohibited. |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 16 Dec 2004 16:32:53 -0800 From: "Mirmak, Michael" Subject: [IBIS-Users] BIRD94: Clarifications on [Diff Pin] Parameters This is a multi-part message in MIME format. - ------_=_NextPart_001_01C4E3CF.F2C24381 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable The enclosed BIRD, Clarifications on [Diff Pin] Parameters, is distributed on behalf of Arpad Muranyi of Intel Corporation. It will be discussed at the January 7, 2005 IBIS Open Forum teleconference. - - Michael Mirmak Intel Corp. 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format=flowed Content-Transfer-Encoding: 7bit Hello Fred, I want to know how we can simlate rising and falling waveform database for a cell that have swing between 0.51v to 1.27V. The supply use are 0V to2.5V. During the extraction I put resistence to 1.76 and 0.51V insted of 2.5V to 0V(in typ case). Again my models are good at lower frequency(15MHZ) but become worst at high frequency(622Mhz). Is any one give ibis models of such type of cells with rising and falling database. Is any extra precaution is required to make model for a cell that is working till 1GHZ. If anyone can send me such type of models it help me. Regards Akhilesh Fred Balistreri wrote: >Are you asking about the test circuit or a software program that does this? > >Best Regards, >Fred >----- Original Message ----- >From: "Akhilesh CHANDRA" >To: >Cc: "Akhilesh CHANDRA" >Sent: Tuesday, December 14, 2004 5:47 AM >Subject: [IBIS-Users] way to extract rising and falling waveform in >differential cells > > > > >>Hello Friends, >> >> I am devloping IBIS model of a differential cell having swing 300mv. >>when I run simulation at 300mhz then I find out there is a transition >>shift between IBIS and spice result. In my model I give just ramp >>database dv/dt for transition. In my view this problem may be resolve if >>I give complete rising and falling waveform in my models. >> Is anyone know how we can extract rising and falling waveform for a >>cell that have differential swing or any other way to reduce this shift. >> >> My results are attached with the mail. >> >>regards >>Akhilesh >> >> >> >> >> > > >---------------------------------------------------------------------------- >---- > > > > > > > > - --------------000205080407090801000002 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Hello Fred,

  I want to know how we can simlate rising and falling waveform database for a cell that have swing between 0.51v to 1.27V. The supply use are 0V to2.5V. During  the extraction I put resistence to 1.76 and 0.51V insted of 2.5V to 0V(in typ case). Again my models are good at lower frequency(15MHZ) but become worst at high frequency(622Mhz).

  Is any one give ibis models of such type of cells with rising and falling database. Is any extra precaution is required to make model for a cell that is working till 1GHZ.
 If anyone can send me such type of models it help me.
Regards
Akhilesh
Fred Balistreri wrote:
Are you asking about the test circuit or a software program that does this?

Best Regards,
Fred
- ----- Original Message ----- 
From: "Akhilesh CHANDRA" <akhilesh.chandra@st.com>
To: <ibis-users@eda.org>
Cc: "Akhilesh CHANDRA" <akhilesh.chandra@st.com>
Sent: Tuesday, December 14, 2004 5:47 AM
Subject: [IBIS-Users] way to extract rising and falling waveform in
differential cells


  
Hello Friends,

   I am devloping IBIS model of a differential cell having swing 300mv.
when I run simulation at 300mhz then I find out there is a transition
shift between IBIS and spice result. In my model I give just ramp
database dv/dt for transition. In my view this problem may be resolve if
I give complete rising and falling waveform in my models.
  Is anyone know how we can extract rising and falling waveform for a
cell that have differential swing or any other way to reduce this shift.

  My results are attached with the mail.

regards
Akhilesh



    


- ----------------------------------------------------------------------------
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- --------------000205080407090801000002-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sun, 19 Dec 2004 09:21:44 -0500 From: "Andrew Ingraham" Subject: Re: [IBIS-Users] way to extract rising and falling waveform in differential cells This is a multi-part message in MIME format. - ------=_NextPart_000_0105_01C4E5AC.284BAC00 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Akhilesh, In the example you gave earlier, the simulation was at 250 MHz (2 ns = high and 2 ns low) and the waveform had just about reached the other = state when it was being switched again. Attempting to simulate this = much faster (622 MHz or 1 GHz), with IBIS, is probably doomed to failure = because of IBIS's limitations. This is sometimes known as = "over-clocking" the IBIS model, because the model hasn't reached the = other state yet when it is being clocked again in the other direction. = Some simulators handle this situation very poorly, so you could see very = poor IBIS vs. SPICE correlation at such faster frequencies. Regards, Andy - ------=_NextPart_000_0105_01C4E5AC.284BAC00 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Akhilesh,
 
In the example you gave earlier, the simulation was = at 250 MHz=20 (2 ns high and 2 ns low) and the waveform had just = about reached the=20 other state when it was being switched again.  Attempting to = simulate this=20 much faster (622 MHz or 1 GHz), with IBIS, is probably doomed to failure = because=20 of IBIS's limitations.  This is sometimes = known as=20 "over-clocking" the IBIS model, because the model hasn't reached = the=20 other state yet when it is being clocked again in the other=20 direction.  Some simulators handle this situation very poorly, so=20 you could see very poor IBIS vs. SPICE correlation at such=20 faster frequencies.
 
Regards,
Andy
 
 
- ------=_NextPart_000_0105_01C4E5AC.284BAC00-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sun, 19 Dec 2004 21:09:35 +0530 From: Akhilesh CHANDRA Subject: Re: [IBIS-Users] way to extract rising and falling waveform in differential cells - --------------010001010102090301000302 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Hello Andy, That means we can't make IBIS model that work at 1ghz. I think we can make IBIS models at such high frequency. Now I put both rising and falling database in my model and it is parsed by golden parser without any problem but still result are not good at 622Mhz. Is this also problem from simulator. I am using eldo (AMS CADENCE)for validation. Regards Akhilesh Andrew Ingraham wrote: > Akhilesh, > > In the example you gave earlier, the simulation was at 250 MHz (2 ns > high and 2 ns low) and the waveform had just about reached the other > state when it was being switched again. Attempting to simulate this > much faster (622 MHz or 1 GHz), with IBIS, is probably doomed to > failure because of IBIS's limitations. This is sometimes known as > "over-clocking" the IBIS model, because the model hasn't reached the > other state yet when it is being clocked again in the other > direction. Some simulators handle this situation very poorly, so > you could see very poor IBIS vs. SPICE correlation at such > faster frequencies. > > Regards, > Andy > > - --------------010001010102090301000302 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Hello Andy,

 That means we can't make IBIS model that work at 1ghz. I think we can make IBIS models at such high frequency. Now I put both rising and falling database in my model and it is parsed by golden parser without any problem but still result are not good at 622Mhz.
  Is this also problem from simulator. I am using eldo (AMS CADENCE)for validation.

Regards
Akhilesh

Andrew Ingraham wrote:
Akhilesh,
 
In the example you gave earlier, the simulation was at 250 MHz (2 ns high and 2 ns low) and the waveform had just about reached the other state when it was being switched again.  Attempting to simulate this much faster (622 MHz or 1 GHz), with IBIS, is probably doomed to failure because of IBIS's limitations.  This is sometimes known as "over-clocking" the IBIS model, because the model hasn't reached the other state yet when it is being clocked again in the other direction.  Some simulators handle this situation very poorly, so you could see very poor IBIS vs. SPICE correlation at such faster frequencies.
 
Regards,
Andy
 
 

- --------------010001010102090301000302-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sun, 19 Dec 2004 12:11:34 -0800 From: "lgreen" Subject: RE: [IBIS-Users] way to extract rising and falling waveform in differential cells This is a multi-part message in MIME format. - ------=_NextPart_000_0038_01C4E5C3.E4EC95B0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hello, Akilesh, One might build a separate model for each frequency. However, as Andy points out, a model built at one frequency will NOT correlate well between SI simulators and SPICE. Overclcoked models are handled differently by different SI simulators, so the quality of comparison would depend on the simulator. The parser makes few checks on table data. So models can pass the parser even when the data is "bad" or incomplete. You might want to use the IBIS Quality Checklist, which contains additional checks (some of them manual).http://www.sisoft.com/ibis-quality/ Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com _____ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Akhilesh CHANDRA Sent: Sunday, December 19, 2004 7:40 AM To: Andrew Ingraham Cc: ibis-users@eda.org; Akhilesh CHANDRA Subject: Re: [IBIS-Users] way to extract rising and falling waveform in differential cells Hello Andy, That means we can't make IBIS model that work at 1ghz. I think we can make IBIS models at such high frequency. Now I put both rising and falling database in my model and it is parsed by golden parser without any problem but still result are not good at 622Mhz. Is this also problem from simulator. I am using eldo (AMS CADENCE)for validation. Regards Akhilesh Andrew Ingraham wrote: Akhilesh, In the example you gave earlier, the simulation was at 250 MHz (2 ns high and 2 ns low) and the waveform had just about reached the other state when it was being switched again. Attempting to simulate this much faster (622 MHz or 1 GHz), with IBIS, is probably doomed to failure because of IBIS's limitations. This is sometimes known as "over-clocking" the IBIS model, because the model hasn't reached the other state yet when it is being clocked again in the other direction. Some simulators handle this situation very poorly, so you could see very poor IBIS vs. SPICE correlation at such faster frequencies. Regards, Andy - ------=_NextPart_000_0038_01C4E5C3.E4EC95B0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hello, = Akilesh,

 

One might build a separate model = for each frequency.  However, as Andy points out, a model built at one = frequency will NOT correlate well between SI simulators and SPICE.  = Overclcoked models are handled differently by different SI simulators, so the = quality of comparison would depend on the simulator.

 

The parser makes few checks on = table data.  So models can pass the parser even when the data is “bad” or incomplete.  You might want to use the IBIS Quality Checklist, = which contains additional checks (some of them = manual).http://www.sisoft.com/ibis-quality/

 

Best = regards,

Lynne

 

 

"IBIS training when you need it, where you need = it."

 

Dr. Lynne Green

Green Streak Programs

http://www.greenstreakprograms.com

425-788-0412

lgreen22@mindspring.com

 

 


From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Akhilesh CHANDRA
Sent: Sunday, December = 19, 2004 7:40 AM
To: Andrew Ingraham
Cc: ibis-users@eda.org; = Akhilesh CHANDRA
Subject: Re: [IBIS-Users] = way to extract rising and falling waveform in differential = cells

 

Hello Andy,

 That means we can't make IBIS model that work at 1ghz. I think we = can make IBIS models at such high frequency. Now I put both rising and = falling database in my model and it is parsed by golden parser without any = problem but still result are not good at 622Mhz.
  Is this also problem from simulator. I am using eldo (AMS = CADENCE)for validation.

Regards
Akhilesh

Andrew Ingraham wrote:

Akhilesh,

 

In the example you gave earlier, the = simulation was at 250 MHz (2 ns high and 2 ns low) and the waveform had just about reached the other state when it was being switched = again.  Attempting to simulate this much faster (622 MHz or 1 GHz), with IBIS, = is probably doomed to failure because of IBIS's limitations.  This is sometimes known as "over-clocking" the IBIS model, because the model hasn't reached the other state yet when it is being = clocked again in the other direction.  Some simulators handle this = situation very poorly, so you could see very poor IBIS vs. SPICE correlation = at such faster frequencies.

 

Regards,

Andy

 

 

 

- ------=_NextPart_000_0038_01C4E5C3.E4EC95B0-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sun, 19 Dec 2004 13:34:23 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] way to extract rising and falling waveform in differential cells This is a multi-part message in MIME format. - ------=_NextPart_000_0089_01C4E5CF.73AA2D20 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Are you terminating both sides of the differential driver when you extract the VT waveforms? Many times differential buffers will not operate properly if they do not have the proper termination on both outputs. Tom Dagostino Teraspeed Consulting Group LLC 503-430-1065 tom@teraspeed.com www.teraspeed.com -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf Of Akhilesh CHANDRA Sent: Sunday, December 19, 2004 7:40 AM To: Andrew Ingraham Cc: ibis-users@eda.org; Akhilesh CHANDRA Subject: Re: [IBIS-Users] way to extract rising and falling waveform in differential cells Hello Andy, That means we can't make IBIS model that work at 1ghz. I think we can make IBIS models at such high frequency. Now I put both rising and falling database in my model and it is parsed by golden parser without any problem but still result are not good at 622Mhz. Is this also problem from simulator. I am using eldo (AMS CADENCE)for validation. Regards Akhilesh Andrew Ingraham wrote: Akhilesh, In the example you gave earlier, the simulation was at 250 MHz (2 ns high and 2 ns low) and the waveform had just about reached the other state when it was being switched again. Attempting to simulate this much faster (622 MHz or 1 GHz), with IBIS, is probably doomed to failure because of IBIS's limitations. This is sometimes known as "over-clocking" the IBIS model, because the model hasn't reached the other state yet when it is being clocked again in the other direction. Some simulators handle this situation very poorly, so you could see very poor IBIS vs. SPICE correlation at such faster frequencies. Regards, Andy - ------=_NextPart_000_0089_01C4E5CF.73AA2D20 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Are=20 you terminating both sides of the differential driver when you extract = the VT=20 waveforms?  Many times differential buffers will not operate = properly if=20 they do not have the proper termination on both = outputs.
 

Tom Dagostino
Teraspeed Consulting Group=20 LLC
503-430-1065
tom@teraspeed.com
www.teraspeed.com =

-----Original Message-----
From: = owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org]On Behalf Of Akhilesh=20 CHANDRA
Sent: Sunday, December 19, 2004 7:40 = AM
To: Andrew=20 Ingraham
Cc: ibis-users@eda.org; Akhilesh = CHANDRA
Subject:=20 Re: [IBIS-Users] way to extract rising and falling waveform in = differential=20 cells

Hello Andy,

 That means we can't = make=20 IBIS model that work at 1ghz. I think we can make IBIS models at such = high=20 frequency. Now I put both rising and falling database in my model and = it is=20 parsed by golden parser without any problem but still result are not = good at=20 622Mhz.
  Is this also problem from simulator. I am using eldo = (AMS=20 CADENCE)for validation.

Regards
Akhilesh

Andrew = Ingraham=20 wrote:
Akhilesh,
 
In the example you gave earlier, the simulation = was at 250=20 MHz (2 ns high and 2 ns low) and the waveform had just=20 about reached the other state when it was being switched = again. =20 Attempting to simulate this much faster (622 MHz or 1 GHz), with = IBIS, is=20 probably doomed to failure because of IBIS's limitations.  = This is sometimes known as "over-clocking" the IBIS model, = because=20 the model hasn't reached the other state yet when it is = being=20 clocked again in the other direction.  Some simulators handle = this=20 situation very poorly, so you could see very poor IBIS vs. = SPICE=20 correlation at such faster frequencies.
 
Regards,
Andy
 
 

- ------=_NextPart_000_0089_01C4E5CF.73AA2D20-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 21 Dec 2004 13:47:47 +0800 From: slwu Subject: Re: [IBIS-Users] Hspice ibischk4 tool Hi All, Does anybody know whether BUG82 is also fixed in ibischk4 Version 4.1.0beta ? Thanks slwu Bob Ross wrote: > Fabrizio: > > The difference between ibischk4 Version 4.0.1 and ibischk4 Version 4.0.1 > is BUG82. BUG82 was serious enough to justify a special release of > ibischk4. > > http://eda.org/pub/ibis/bugs/ibischk/index.html > > A text list of what verion a bug fix has been implemented exists > in the bugdir.txt file link at the end of this link. > > Bob > > Zanella, Fabrizio wrote: > > > The latest version of Synopsys Hspice, version 2004.09, uses the > > ibischk4 tool, version 4.0.1. In a simulation I ran yesterday, Hspice > > reported errors running the v4.0.1 ibischk4 with the rising and falling > > waveforms when using an IBIS model as a driver. > > > > Here?s a sample of the errors: > > > > ERROR - Model osoc2_od: The [Rising Waveform] > > > > with [R_fixture]=60 Ohms and [V_fixture]=3.3V > > > > has TYP column DC endpoints of 2.02V and 3.30v, but > > > > an equivalent load applied to the model's I-V tables yields > > > > different voltages ( 2.02V and 2.02V), > > > > a difference of inf% and inf%, respectively. > > > > ERROR - Model osoc2_od: The [Falling Waveform] > > > > with [R_fixture]=60 Ohms and [V_fixture]=3.3V > > > > has TYP column DC endpoints of 2.02V and 3.30v, but > > > > an equivalent load applied to the model's I-V tables yields > > > > different voltages ( 2.02V and 2.02V), > > > > a difference of inf% and inf%, respectively. > > > > > > > > An engineer at the device manufacturer said there are no errors when he > > uses the ibischk4 v4.0.2 tool. Can someone explain what the differences > > are between versions 4.0.1 and 4.0.2 of the ibischk4 tool and does > > anyone know whether Synopsys will be moving to the latest ibischk4 tool > > in the Hspice simulator? > > > > Thanks and regards, > > > > > > > > Fabrizio Zanella > > > > Signal Integrity > > > > Enterasys Networks > > > > Andover, MA > > > > Phone: 978-684-1340 > > > > fzanella@enterasys.com > > > > > > > > -- > Bob Ross > Teraspeed Consulting Group LLC Teraspeed Labs > 121 North River Drive 13610 SW Harness Lane > Narragansett, RI 02882 Beaverton, OR 97008 > 503-750-6481 503-430-1065 > http://www.teraspeed.com 503-246-8048 Direct > bob@teraspeed.com > > |------------------------------------------------------------------ > |For help or to subscribe/unsubscribe, email majordomo@eda.org > |with just the appropriate command message(s) in the body: > | > | help > | subscribe ibis > | subscribe ibis-users > | unsubscribe ibis > | unsubscribe ibis-users > | > |or email a written request to ibis-request@eda.org. > | > |IBIS reflector archives exist under: > | > | http://www.eda.org/pub/ibis/email_archive/ Recent > | http://www.eda.org/pub/ibis/users_archive/ Recent > | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 20 Dec 2004 21:52:34 -0800 From: Bob Ross Subject: Re: [IBIS-Users] Hspice ibischk4 tool Hello Shulong: Yes BUG82 should be fixed since Ver 4.0.2 served as the baseline for Versio 4.1X developement underway. Bob slwu wrote: > Hi All, > > Does anybody know whether BUG82 is also fixed in ibischk4 Version 4.1.0beta > ? > > Thanks > slwu > > Bob Ross wrote: > > >>Fabrizio: >> >>The difference between ibischk4 Version 4.0.1 and ibischk4 Version 4.0.1 >>is BUG82. BUG82 was serious enough to justify a special release of >>ibischk4. >> >> http://eda.org/pub/ibis/bugs/ibischk/index.html >> >>A text list of what verion a bug fix has been implemented exists >>in the bugdir.txt file link at the end of this link. >> >>Bob >> >>Zanella, Fabrizio wrote: >> >> >>>The latest version of Synopsys Hspice, version 2004.09, uses the >>>ibischk4 tool, version 4.0.1. In a simulation I ran yesterday, Hspice >>>reported errors running the v4.0.1 ibischk4 with the rising and falling >>>waveforms when using an IBIS model as a driver. >>> >>>Here?s a sample of the errors: >>> >>>ERROR - Model osoc2_od: The [Rising Waveform] >>> >>> with [R_fixture]=60 Ohms and [V_fixture]=3.3V >>> >>> has TYP column DC endpoints of 2.02V and 3.30v, but >>> >>> an equivalent load applied to the model's I-V tables yields >>> >>> different voltages ( 2.02V and 2.02V), >>> >>> a difference of inf% and inf%, respectively. >>> >>>ERROR - Model osoc2_od: The [Falling Waveform] >>> >>> with [R_fixture]=60 Ohms and [V_fixture]=3.3V >>> >>> has TYP column DC endpoints of 2.02V and 3.30v, but >>> >>> an equivalent load applied to the model's I-V tables yields >>> >>> different voltages ( 2.02V and 2.02V), >>> >>> a difference of inf% and inf%, respectively. >>> >>> >>> >>>An engineer at the device manufacturer said there are no errors when he >>>uses the ibischk4 v4.0.2 tool. Can someone explain what the differences >>>are between versions 4.0.1 and 4.0.2 of the ibischk4 tool and does >>>anyone know whether Synopsys will be moving to the latest ibischk4 tool >>>in the Hspice simulator? >>> >>>Thanks and regards, >>> >>> >>> >>>Fabrizio Zanella >>> >>>Signal Integrity >>> >>>Enterasys Networks >>> >>>Andover, MA >>> >>>Phone: 978-684-1340 >>> >>>fzanella@enterasys.com - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 503-750-6481 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 24 Dec 2004 18:53:12 -0800 From: Bob Ross Subject: [IBIS-Users] IIRD8.2 - Distinct Model_pinmap and Model_nodemap Names This is a multi-part message in MIME format. - --------------050704000901020401070700 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit To All: IIRD8.2 containng some editorial revisions is attached to be considered at the next IBIS Meeting. Bob - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 503-750-6481 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com - --------------050704000901020401070700 Content-Type: text/plain; name="iird8.2.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="iird8.2.txt" ICM Issue Resolution Document (IIRD) IIRD ID#: 8.2 ISSUE TITLE: Distinct Model_pinmap and Model_nodemap Names REQUESTOR: Bob Ross, Teraspeed Consulting Group DATE SUBMITTED: September 22, 2004 DATE REVISED: November 21, 2004, December 24, 2004 DATE ACCEPTED BY IBIS OPEN FORUM: PENDING **************************************************************************** **************************************************************************** STATEMENT OF THE ISSUE: Model_pinmap and Model_nodemap names under [Tree Path Description] and [Nodal Path Description] need to be distinct to allow interfacing with IBIS or other types of connections. If the names are reused, then a method is needed for EDA tools to identify the specific name for connections. **************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: Statements are added that the Model_pinmap and Model_nodemap names must either be distinct or else differentiated by a new subparameter "Side" under [Tree Path Description] and [Nodal Path Description]. Change instruction lines are identified by |** Changes are identified by |*, |***, |**** lines. Some unchanged portions are omitted. |** MODIFY THE TREE DIAGRAM IN THE PORTION BELOW |--/--[Begin ICM Family] | (see Chapter 7) | | |--[Manufacturer] | | |--[ICM Family Description] | | |--[ICM Model List] | | | |--/--[Begin ICM Model] | | | | ICM_model_type | | | | SGR | | | | Ref_impedance | | | |--[ICM Model Description] | | | |--[Tree Path Description] | | | | Model_pinmap |** Add this line | | | | Side |** End of addition | | | | Fork, Endfork | | | | Section | | | |--[Nodal Path Description] | | | | Model_nodemap |** Add this line | | | | Side |** End of addition | | | | N_section | | | |--[ICM Swath Parameters] | (optional, for swaths) | | | | Left_edge | | | | Right_edge | | | | Top_edge | | | | Bottom_edge | | | |--[ICM Swath Pin Numbers] | (optional, for swaths) | | \--[End ICM Model] | | | |--[ICM Pin Map] | Pins to Physical | | Pin_order | | Num_of_columns | | Num_of_rows | | Pin_list | |--[ICM Node Map] | Nodes to Physical | \--[End ICM Family] | |** MAKE CHANGES TO THE [Tree Path Description] KEYWORD SHOWN BELOW: ============================================================================= Keyword: [Tree Path Description] Required: Yes, if [Nodal Path Description] does not exist |** Delete this line Sub-params: Model_pinmap, Section, Fork, Endfork |** Add this line Sub-params: Model_pinmap, Side, Section, Fork, Endfork |** End of addition Used By: [Begin ICM Model] Uses: [ICM Pin Map] Description: This keyword describes the connection path between the pin or pins on one side of the interconnect and the corresponding set of pins on the other side. This pin to pin interconnect is divided into one or more "sections", where each section consists of RLGC data. Sections are generally cascaded in series, but the Fork and Endfork subparameters allow sections to branch off the main interconnect path as a stub or tee. Usage Rules: A [Tree Path Description] is used when all of the sections in a given interconnect have one-to-one mapping. In other words, each pin is electrically connected to at least one other pin of the interconnect through a conductor. Topologies where physical crossing of one conductor over or under another occurs shall not be described using [Tree Path Description]. |** Several paragraphs are omitted ..... The [Tree Path Description] keyword line is followed by at least one Model_pinmap and one Section subparameters which describe the pin-to-conductor mapping, and the topology of the interconnect. The electrical properties of an interconnect section are described in the matrices under the [Begin ICM Section] keyword which are referenced by the Section subparameter(s), discussed below. Branches or "T" connections are indicated by the "Fork" and "Endfork" subparameters. Tree path descriptions are terminated with a Model_pinmap subparameter. These subparameters are described in detail below. Model_pinmap A path description begins with the required subparameter Model_pinmap. This subparameter is followed by the name of a "pin map" which names the pins on that end of the interconnect. A second Model_pinmap is used at the end of the path description to reference the pin map used for the other end of the interconnect. The Model_pinmap subparameter can also be used to reference a pin map for the pins at the end of any Fork. Note that the pin map name given as an argument to a Model_pinmap subparameter must match the name of a pin map defined by a subsequent [ICM Pin Map] keyword. The argument to the Model_pinmap subparameter and the sub- parameter itself are separated by whitespace. There can be as many Model_pinmap subparameters as required, but each must be on a single line. |* Delete this paragraph: In general, an interconnect will have a single pin map that is referenced at the beginning and end of a path description. |** Replace with this paragraph: |**** One or more Model_pinmap lines can exist, but each pin map |**** name must be unique and reference a different [ICM Pin Map] |**** description even if the content is dentical. Alternatively, |**** the same Model_pinmap may be used, but the subparameter Side |**** described below must follow next. |** End of replacement paragrapth |** Add new sub-section Side |**** If a Model_pinmap pin map name is repeated within a [Tree Path Description] keyword, the Side subparameter is required and positioned as the next line under the Model_pinmap |**** subparameter. The Side subparameter is followed a unique side |**** name to allow tools to identify which of the identical pin maps |**** to make the connection. The Side subparameter is required for all Model_pinmap lines with identical pin map names. The Side subparameter is optional when the pin map name is unique. |** End of sub-section addition |** MODIFY THE EXAMPLE AS SHOWN BELOW - ----------------------------------------------------------------------------- "ICM Model" Examples - ----------------------------------------------------------------------------- Example 1: A simple single line model with one section SectA Port1 >--------< Port2 [Begin ICM Model] MyModelExample1 ICM_model_type SLM_general SGR 3:1 Ref_impedance=50 [Tree Path Description] Model_pinmap Example1_pinmap |** Add these lines Side A | The Model_pinmap name is reused, so Side and a unique | side name is required |** End of addition Section Mult=1 Diagonal_matrix1 Model_pinmap Example1_pinmap |** Add these lines Side B | The Model_pinmap name is reused, so Side and a unique | side name is required |** End of addition . . . [End ICM Model] |** Remainder of the Example is omitted ... |** MAKE CHANGES TO THE [Nodal Path Description] KEYWORD SHOWN BELOW: ============================================================================= Keyword: [Nodal Path Description] Required: Yes, if [Tree Path Description] does not exist |** Delete this line Sub-params: N_section, Model_nodemap |** Add this line Sub-params: N_section, Model_nodemap, Side |** End of addition Used By: [Begin ICM Model] Uses: [ICM Node Map] Description: This keyword marks the beginning of a nodal path description. It contains the information on how two or more nodes are connected. The nodal description style allows for any arbitrary topologies to be described. Nodes define the connection points where the conductors of two or more sections are joined together, or where the path is interfaced to the outside world. Please note that single connections (dangling ends) at nodes are also permitted. Thus nodes can represent any connection points, including pins (on either side of connectors, packages, or sockets), pads and bumps of a die (where the connections to the package or printed circuit board are made), or the ends of either side of interconnect sections of printed circuit boards. An interconnect path may have one or more sections where each section is described by RLGC or S-parameter matrices. Multiple sections within a path description may be connected in any arbitrary manner by using the usual node naming techniques. Please note that the swath features cannot be used with this keyword. Also note that the use of both RLGC and S-parameter matrix data for sections within the same [Nodal Path Description] is prohibited. Usage Rules: The [Nodal Path Description] keyword may appear multiple times in the file, however it may appear only once between each pair of [Begin ICM Model]/[End ICM Model] keywords. |** Several paragraphs are omitted ..... Model_nodemap The required subparameter Model_nodemap is used to reference the [ICM Node Map] keyword which provides a mapping between the actual data book pin (or signal) names and the node names used in the path description. A path description must have at least one occurrence of the required subparameter Model_nodemap, but can have as many Model_nodemap subparameters as needed to adequately describe the interconnect. The number of Model_nodemap subparameters used in a path description would be typically the same as the number of ends or sides in a connector or interconnect. Each Model_nodemap subparameter must be on a single line. The Model_nodemap subparameter is followed by one argument, which the name of a node map. The argument must match the name of a node map defined by a subsequent [ICM Node Map] keyword. The argument and the subparameter must be separated by at least one white space. |** Add this paragraph: |**** One or more Model_nodemap lines can exist, but each node map |**** name must be unique and reference a different [ICM Node Map] |**** description even if the content is identical. Alternatively, |**** the same Model_nodemap may be used, but the subparameter Side |**** described below must follow next. |** End of added paragraph |** Add new sub-section Side |**** If a Model_nodemap pin map name is repeated within a [Nodal Path Description] keyword, the Side subparameter is |**** required and positioned as the next line under the |**** Model_nodemap subparameter. The Side subparameter is followed |**** by a unique side name to allow tools to identify which of the |**** identical node maps to make the connection. The Side subparameter is required for all Model_nodemap lines with identical node map names. The Side subparameter is |**** optional when the node map name is unique. |** End of sub-section addition **************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Originally it was assumed that if the pinout at each end of an interconnect such as a connector had the same pin numbers, then the same [ICM Pin Map] table could be used as referenced by the Model_pinmap. However, this leads to ambiguous begin-end conditions for straight through paths and possible ambiguity for splitter topologies possible in both the Tree Path Description] and [Nodal Path Description] when a specific end needs to be connected externally. So unique Model_pinmap and Model_nodemap names are explicitly specified to assist in the correct connection. This prepares ICM for a possible IBIS BIRD to connect IBIS with ICM using the multi-lingual format. The language is not changed regarding possible single Model_pinmap and Model_nodemap lines. And Unmated model will have a single Model_*map line. IIRD8.1: A new subparameter "Side" is introduced so that the same Model_pinmap name can be used several times without requiring coping an entire [ICM Pin Map] table. It is also introduced for Model_nodemap for the same reason. This option was chosen among the following: (1) Do nothing - NO syntax change, compatible with 1.0 wasteful for large connectors (2) Devise an extension convention Example1_A, EXample1_B ... Example1/A. Extension may conflict with an actual naming convention. (3) Introduce Optional subparameter or second column OR single SPACE Example1 Side A or Example1 A However, calling routine must work with/without extension. (4) Perhaps introduce in the [ICM Pin Map] and [ICM Node Map] a) multiple names b) Another_name xxxxx subparameter syntax Option (3) with a distinct subparameter Side is chosen as as the method that is consistent with the rest of the specification. IIRD8.2 Some editorial changes per Arpad Muranyi's comments are made and noted by |**** lines **************************************************************************** ANY OTHER BACKGROUND INFORMATION: IIRD8 assumes that IIRD6 will be rejected. The golden parser must be corrected to accept only one Model_*map or else test that the arguments of several are unique. IIRD8 was discussed at the October 29, 2004 IBIS meeting and the Novemeber 4, 2004 IBIS Futures Meeting. The action item was to investigate a better method of differentiating the terminals by some name, extension or name and subparameter to avoid the need to provide large, identical pin tables. **************************************************************************** - --------------050704000901020401070700-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 24 Dec 2004 22:58:48 -0800 From: "Mirmak, Michael" Subject: [IBIS-Users] BIRD95: Power Integrity Analysis Using IBIS This is a multi-part message in MIME format. - ------_=_NextPart_001_01C4EA4F.34D0DCBA Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable The enclosed BIRD, Power Integrity Analysis Using IBIS, is submitted on behalf of Syed Huq, Vinu Arumugham and Zhiping Yang of Cisco Systems. It will be discussed at the January 7, 2005 IBIS Open Forum teleconference. - - Michael Mirmak Intel Corp. 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http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 28 Dec 2004 10:30:42 -0800 From: Syed Huq Subject: Re: [IBIS-Users] BIRD95: Power Integrity Analysis Using IBIS Hi Matsui-san, Thanks for your questions/comments on BIRD95. We are including our responses below. Pls feel free to let us know if you have more questions. Regards, Syed-- IBIS Vice-Chair & Webmaster Cisco Systems, Inc On Sun, 2004-12-26 at 09:00, Mirmak, Michael wrote: > Comments from Matsui-san on BIRD95. > > - MM > > ______________________________________________________________________ > From: matsui [mailto:matsui@apsimtech.com] > > My comments and thoughts on SSO and EMI models are below. > > 1. If I_bypass is described as a current source, it may not be > right. > Series current source always feed the same current to out side. > I think the I_bypass and C_p+b may be in parallel. Or voltage > source > is OK. All current source models must have admittance or > device models > in parallel. The current waveforms will be varied by loads and > admittance/ > impedance of switching transistors. The admittance/impedance > consists > of linear power rails and nonlinear transistors. I remember > Arpad has > presented nonlinear model of C_comp. Cisco:(1) I_bypass is not a current source. I_bypass simply represents current that flows through the bypass components. > 2. There are two types of core models. One is shown in the bird. > The other (I think this is more popular) type of core logic is > not connected > to I/O buffer. I/O core logic may be connected to lower > voltage sources > with no I/O. Cisco:(2) We have internally discussed that I/O and core voltages can be different and the pre-driver can be supplied with either. > 3. SSO needs time domain model. EMI needs frequency domain model > and time > domain model. The frequency domain model means linearized > model and it > is an approximation. Current sources should be described in > real and imaginary > parts at various frequencies. The parallel admittance, if it > is a macro model, may > be approximated as real and imaginary parts at various > frequencies. > Time domain model of cores is more preferable for SSO and EMI, > because > switching transistors have strong non linearity. Current > source model is a kind of > linear approximation. Current waveforms are results. Constant > external voltage > sources are switched by nonlinear transistors. Only current > sources can't describe > load effects. They need nonlinear admittance / impedance. > Transistor or behavioral > model may describe these effects. Cisco:(3 and 6) Again BIRD95 has no current sources. BIRD95 based simulations will have more accurate EMI results than pre-BIRD95 simulations. However, BIRD95 is not specifically directed towards EMI simulations. EMI simulations are best addressed with the ICEM model. > 4. How to simplify the models of power rails on a chip and a > package is another > serious issue. Even for a package, number of die pads and > balls for power/ground > I/O. ICM and SPICE may be OK, but too complex model with too > many terminals are > not good for simulation. > 5. All the core logic is connected to common power rails with some > different DC levels > and the power/ground rails are connected to number of die pads > and package balls. > A figure of Bird 95 seems to consist of one I/O and one core > logic. I think the starting > point may be more realistic structures of an LSI chip. Cisco:(4 and 5) Common Spice package models are scaled down to a slice of the package with a handful of drivers. It should be possible to scale the model down to a single buffer. > 6. I think there is a big difference between SSO and EMI models. A > simple EMI simulation > does not need individual power I/O pin models. But accurate EMI > simulation may not > accept this model. > > Best Regards, > Norio Matsui > > |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 29 Dec 2004 17:51:24 +0800 From: =?big5?B?QW5kcmV3X0NoaWVuXCjCsrFSpndcKQ==?= Subject: [IBIS-Users] Basic questions about IBIS Hi, experts, I am a hand-held device hardward engineer who just study IBIS simulation for serveral months. I have some basic questions: 1. Is it possible to simulate setup/hold time using IBIS model? I know that we can obtain the delay difference between "test load" and "trace", but I don't know whether it is possible to ask chip vendors to provide the "gate delay + test load" of each signal. 2. What item is the main purpose of signal integrity simulation works? Overshoot, ringback, transition time, or crosstalk? 3. Is measurement-based IBIS model more accurate that SPICE simulation-based IBIS model? One of our chip vendor said it, and we do obtain more accurate results from measurement-based IBIS model. However, they said that it takes 3-4 months to generate a measurement-based IBIS model, so they are not willing to generate the IBIS model of the other I/O buffers on the same device for us. Is it possible to generate an accurate enough IBIS model in a short time? 4. When we want to generate a measurement-based IBIS model How can we select the max, min, typ buffer strength chip? 5. In IBIS, the "max" curves are measured / simulated under the condition "maximum buffer strength + lowest temperature + largest voltage" and the "min" curves are measured / simulated under the condition "minimum buffer strength + highest temperature + smallest voltage". I think it is not sufficient to simulate the ringback: as I know the ringing caused by maximum buffer strength is much larger the minimum buffer strength, but "smallest voltage - VIH" is smaller than "largest voltage - VIH", we cannot make sure whether the ringback margin is sufficient even if the simulation results of min and max passed. (Because the smallest ringback margin should be under the condition "maximum buffer strength + lowest temperature + smallest voltage") 6. Chip vendors usually set the largest and smallest voltage according to their maximum tolerance (for example 20%), however, the voltage error rate of our regulator is usually not so large. So the worst cases in IBIS model are not the same with the worst cases in our PCBA. Furthermore, sometimes the typical voltage we use is not the same with the original. I would like to know whether there is a method to generate the IBIS model we need. Any help will be apreciated, Thanks in Advance. Best regards Andrew CONFIDENTIALITY NOTE : The information in this e-mail is confidential and privileged; it is intended for use solely by the individual or entity named as the recipient hereof. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient is strictly prohibited and may violate applicable laws. If you have received this e-mail in error, please delete the original message and notify us by return email or collect call immediately. Thank you. High Tech Computer Corporation |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 29 Dec 2004 11:07:57 -0500 From: "Andrew Ingraham" Subject: [IBIS-Users] Re: Basic questions about IBIS > I know that we can obtain the delay difference between "test load" and > "trace", but I don't know whether it is possible to ask chip vendors to > provide the "gate delay + test load" of each signal. For chip outputs, gate delays should always be specified with the test load. That's the purpose of the test load. Check the data sheet; it should say somewhere that output delays are specified with the load. > 2. What item is the main purpose of signal integrity simulation works? > Overshoot, ringback, transition time, or crosstalk? Yes! To all, and more. :-) I would not try to say which one of these is most important, because it depends on the situation. > 3. Is measurement-based IBIS model more accurate that SPICE > simulation-based IBIS model? That depends. Obviously, a measurement-based model can accurately represent (one sample of a) real device. The SPICE model might or might not bear much similarity to reality. If not, then clearly the measurement-based model can be better. It depends on the care that went into making the SPICE model, whether they bothered to correlate it with measurements, etc. The IBIS model should have min and max characteristics, but they might not have sample parts of both extremes. Thus, some extrapolation (based on best guesses) may be required. Of course the same is true of SPICE models too. Measurement-based models tend to have some "noise" that may need to be smoothed out. A lot of fine noise in the tables can lead to odd behavior in the simulator. Many SPICE models are created from expectations of what the chip vendor thinks he ought to get from his new process, and the targets can be wrong. Plus, oftentimes there are difficulties extracting SPICE models from certain structures (particularly in the I/O area), and it is easy to get a lousy SPICE model; one that's totally missing the clamp devices, or has the wrong drive strength, or whatever. Depending on the frequencies of interest, it can take a lot of skill to correctly measure and model the characteristics of the device. This is one area where a SPICE-derived model may have the advantage (assuming, of course, that the SPICE model was good at those frequencies). > One of our chip vendor said it, and we do obtain more accurate results > from measurement-based IBIS model. However, they said that it takes 3-4 > months to generate a measurement-based IBIS model, so they are not willing > to generate the IBIS model of the other I/O buffers on the same device for > us. > Is it possible to generate an accurate enough IBIS model in a short > time? Yes. The 3-4 months includes the time to schedule the work, assign personnel and equipment, get up to speed, some padding in case something goes wrong and they need to start over, write up reports, etc. They probably don't have someone sitting around with nothing to do who can start on your devices today. Hence the extra time. > 4. When we want to generate a measurement-based IBIS model How can we > select the max, min, typ buffer strength chip? You can adjust the supply voltages and perhaps the temperature when making these measurements, but there's nothing YOU can do to represent a best-case or worst-case chip from the fab. The IC manufacturer can do this, but it's not cheap. Either you get samples that are certified by the vendor to represent the likely extremes of the fab process, or you take samples, hope that they are typical, and margin the curves by some amount. Regards, Andy |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 30 Dec 2004 15:17:27 +0800 From: "Andrew_Chien\(???\)" Subject: [IBIS-Users] RE: [IBIS] Re: Basic questions about IBIS Dear Mr. Ingraham, Thanks so much for your kindly answer. You really give me an elaboration about me questions. About 1, I should ask our chip vendor to fill out the "TBD" values in their specification. About 3, A. So, chips are usually not made according to SPICE file; On the contrary, SPICE files are extracted from chip and guess. Thus, SPICE-derived IBIS model and encrypted SPICE model are not as accurate as measurement-based IBIS model. (except some situation) B. So, the extremes of SPICE-derived model are only expectations. And only if chip vendor spend a lot of money and a lot of time to screen the extreme chips from manufacture process and then use a long time to measure it, we cannot get a accurate IBIS model. I am afraid that the schedule of IBIS model is too slow to let us prevent SI problems in advance... C. If everything is optimized, how long will it usually take to generate a IBIS3.2 model of one I/O buffer? About 4, A. I would like to know whether the influence from fab process is smaller than the influence from temperature and voltage or not. i.e. if chip vendors didn't spend their resource to select the typical and extreme chips, how much will the simulation result be influenced? B. For most IBIS model, the typical temperature is room temperature, however, for some chips (ex: CPU), the temperature is much higher than room temperature. Is it reasonable to ask chip vendors to change the typical temperature. Could you also give some comments to the rest two questions if it is conveniet for you? Thank you in advance. Best regards Andrew Chien - -----Original Message----- From: owner-ibis@eda.org [mailto:owner-ibis@eda.org]On Behalf Of Andrew Ingraham Sent: Thursday, December 30, 2004 12:08 AM To: ibis@eda.org; ibis-users@eda.org Subject: [IBIS] Re: Basic questions about IBIS > I know that we can obtain the delay difference between "test load" and > "trace", but I don't know whether it is possible to ask chip vendors to > provide the "gate delay + test load" of each signal. For chip outputs, gate delays should always be specified with the test load. That's the purpose of the test load. Check the data sheet; it should say somewhere that output delays are specified with the load. > 2. What item is the main purpose of signal integrity simulation works? > Overshoot, ringback, transition time, or crosstalk? Yes! To all, and more. :-) I would not try to say which one of these is most important, because it depends on the situation. > 3. Is measurement-based IBIS model more accurate that SPICE > simulation-based IBIS model? That depends. Obviously, a measurement-based model can accurately represent (one sample of a) real device. The SPICE model might or might not bear much similarity to reality. If not, then clearly the measurement-based model can be better. It depends on the care that went into making the SPICE model, whether they bothered to correlate it with measurements, etc. The IBIS model should have min and max characteristics, but they might not have sample parts of both extremes. Thus, some extrapolation (based on best guesses) may be required. Of course the same is true of SPICE models too. Measurement-based models tend to have some "noise" that may need to be smoothed out. A lot of fine noise in the tables can lead to odd behavior in the simulator. Many SPICE models are created from expectations of what the chip vendor thinks he ought to get from his new process, and the targets can be wrong. Plus, oftentimes there are difficulties extracting SPICE models from certain structures (particularly in the I/O area), and it is easy to get a lousy SPICE model; one that's totally missing the clamp devices, or has the wrong drive strength, or whatever. Depending on the frequencies of interest, it can take a lot of skill to correctly measure and model the characteristics of the device. This is one area where a SPICE-derived model may have the advantage (assuming, of course, that the SPICE model was good at those frequencies). > One of our chip vendor said it, and we do obtain more accurate results > from measurement-based IBIS model. However, they said that it takes 3-4 > months to generate a measurement-based IBIS model, so they are not willing > to generate the IBIS model of the other I/O buffers on the same device for > us. > Is it possible to generate an accurate enough IBIS model in a short > time? Yes. The 3-4 months includes the time to schedule the work, assign personnel and equipment, get up to speed, some padding in case something goes wrong and they need to start over, write up reports, etc. They probably don't have someone sitting around with nothing to do who can start on your devices today. Hence the extra time. > 4. When we want to generate a measurement-based IBIS model How can we > select the max, min, typ buffer strength chip? You can adjust the supply voltages and perhaps the temperature when making these measurements, but there's nothing YOU can do to represent a best-case or worst-case chip from the fab. The IC manufacturer can do this, but it's not cheap. Either you get samples that are certified by the vendor to represent the likely extremes of the fab process, or you take samples, hope that they are typical, and margin the curves by some amount. Regards, Andy CONFIDENTIALITY NOTE : The information in this e-mail is confidential and privileged; it is intended for use solely by the individual or entity named as the recipient hereof. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient is strictly prohibited and may violate applicable laws. If you have received this e-mail in error, please delete the original message and notify us by return email or collect call immediately. Thank you. High Tech Computer Corporation |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 30 Dec 2004 13:20:55 -0800 From: Syed Huq Subject: [Fwd: RE: [IBIS] Re: [IBIS-Users] BIRD95: Power Integrity Analysis Using IBIS] Mike, Our responses below to your questions. Happy Holidays, Syed - -- IBIS Vice-Chair & Webmaster Cisco Systems, Inc On Wed, 2004-12-29 at 08:33, Mike LaBonte wrote: > BIRD95 reminds us of the difficulties associated with the current profile > issue, but hopefully this time we can work it through to a conclusion. My > comments: > > 1) Norio Matsui may have raised the most important issue, the fact that > there may not be exactly one bypass capacitor and one pre-driver section > associated with one buffer, all sharing current from one supply. In fact > this case seems quite unlikely. Scaling the total bypass capacitance, > pre-driver current and output current for an arbitrary slice of a component > down to one of it's buffers should a model that is likely not very accurate > for any single buffer, or for any collection of buffers unless the > collection happens to be equal to those in the slice. And a single current > profile still doesn't solve the correct apportionment of current to paths > from distinct power supply voltages. > Cisco: BIRD95 only addresses the case where the pre-driver and buffer share the same power rail. If a bypass capacitor is shared, it has to be scaled. Pre-driver and output current need no scaling because they will be obtained from Spice simulation of a single buffer. Since only one power rail is modeled, a single current profile is sufficient. Our proposal is mainly for the last stage of I/O power supply which we called VDDQ. The IvsT table is only associated with VDDQ at this time. For the VDDQ net within one I/O buffer, We didn't see the need to seperate the currents go through the different bypass capactiors or different pre-drive circuit. One lumped current should be good enough. This brings up the point of how even a regular IBIS buffer model is to be derived. Should the IBIS model be derived from Spice that includes a bypass network or a perfect supply? If a pre-driver is connected to core Vdd, it needs to be integrated into the ICEM core current profile model. > 2) Accepting for the moment that we are attempting to represent multiple > current paths with a single table here, why not specify ground current > instead of power current? Isn't it more likely that all of these currents > flow through a single ground plane than through a single power plane? > Cisco: The reasons why we only provide the current from VDDQ not GND are: #1. VDDQ noise is what we care for SSO simulation. #2.There could be other power supplies with the I/O buffer, so the GND current is the combination (in a certain degree) of the all power supplies current. It is impossible to seperate the I_VDDQ from the total current when there is only one IvsT table is provided. > 3) Although the IBIS specification limits itself with regard to explaining > how a simulator might use the data, I feel that some effort might be > warranted here to advance the cause of consistency among simulators. For > starters, should we have some words of wisdom explaining that the current > out of the pad can be determined, and represents the difference between the > current into the power supply (if there is only one) and out through ground > (if there is only one). Digging deeper, how will the simulator decide how > much of the current passing through ground is "crowbarred" through the > pullup and pulldown, versus passing through the other current path formed by > the bypass capacitors and pre-drivers? This has a bearing on the turn-on/off > rates chosen for the pullup/pulldown. Mainly I would like to see some > discussion of this from simulator people, to validate that the simulation > outcome is deterministic. Even if there has been discussion already within > the IBIS committee, it would be good to make a record in the IBIS > specification for future implementers. > Cisco: For a majority of the cases, we think the simulator does not have to know how much of the current is crowbar and how much is pre-driver. If this becomes important it may have to be handled in a future enhancement over BIRD95. > 4) I think the text should clarify that positive values represent current > flowing into the buffer. > Cisco: Agreed. > 5) Although it may seem obvious, maybe the specification should clarify that > in the case of open_XXX models, where current is supplied by the test > fixture, that current is not to be accounted for in the [Series Composite > Current]. > Cisco: We should be able to do this. > 6) What would the [Series Composite Current] profile look like for a > differential output buffer? Presumably these must be taken as a pair, and > the total current for the pair ideally remains nearly static. Should we > require the measurements to be taken this way, or should we allow model > makers to provide separate P and N models with different current profiles? > Cisco: If IBIS always models differential buffers as two single-ended ones, the power modeling will do the same. If IBIS can handle true differential buffer, we could add IvsT table for that case later. SSN impact with Diff buffers may not be as significant compared to single-ended buffers. > 7) The proposed [Series Composite Current] keyword associates itself with a > preceding [XXX Waveform] keyword, and is thus position dependent. Some > existing IBIS keywords are position dependent. For example, [Ramp] is part > of a second level of hierarchy under [Model]. But I think [Series Composite > Current] would be a third level of hierarchy, being under [XXX Waveform], > which is under [Model]. Is this OK, or would it be better to simply add 3 > more columns to the [XXX Waveform] tables? > Cisco: We would prefer not to add 3 more colums to the [XXX Waveform] but we are open to suggestions. This is more of a format/keyword placement issue. > 8) Can the [Series Composite Current] keyword follow only some [XXX > Waveform] tables and not others? > Cisco: Yes. In the case of Open_Drain, some of the tables will no longer be present. > 9) The text describes [Series Composite Current] as current flowing through > R_VDD, but the circuit diagram calls it R_VDDQ. > Cisco: We will fix this. > 10) More nit picking: I had to modify the ASCII circuit diagram to make it > line up right. > Cisco: Is this because of the width settings on your Email client. We can fix any format issues. |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #48 ************************