From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #51 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Thursday, February 10 2005 Volume 01 : Number 051 ---------------------------------------------------------------------- Date: Tue, 18 Jan 2005 08:40:22 +0100 From: Ralf Bruening Subject: [IBIS-Users] European IBIS Summit At DATe 2005 - Second Call for Papers/Call for Participation To All: We have been holding successful European IBIS Summit Meetings for the past seven years. Next year we are again holding a meeting along with DATe 05 on Friday, March 11, 2005. The purpose is to promote communication among users and developers of IBIS models in Europe. The meeting is free and open to everyone. However, you will have to register for the exhibition at DATe (to get access to the meeting room). Refreshments are planned. Below is some information on the IBIS Summit and some related events. You are invited to register and also to submit presentation proposals. Ralf Bruening Product Manager High Speed Design ZUKEN EMC Technology Center - ----------------------------------------------------------------------------------- E U R O P E A N I B I S S U M M I T M E E T I N G S E C O N D C A L L F O R P A R T I C I P A T I O N Time/Date: 9:00 AM - 2:00 PM, Friday, March 11, 2004 Location: Meeting Room @ ICM Messe Munich (Munich ICM Congress Center) Munich, Germany (where DATE 2005 is being held). Free DATE 2005 exhibition registration for room entry, see URL below. Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas Sponsors: Zuken, Mentor Graphics, Cadence Design Systems/Flowcad, Siemens. If your company would be interested in sponsoring this event, please contact Ralf Bruening or Eckard Lenski from Siemens AG Benefits to sponsors include formal recognition at the meeting and mention in the Calls for Papers and meeting minutes. Your financial support strengthens the organization by allowing IBIS to focus resources on industry activities rather than raising money, and you will receive generous thanks for your support. DATE 2005 Conference: March 07-11, 2005. The IBIS meeting is scheduled the day after the DATE 2005 exhibition ends. Location: ICM International Congress Center, Munich, Germany DATE URL: http://www.date-conference.com Background: DATE (Design, Automation, and Test in Europe) is the only European event dedicated to electronic system design and test. Topics of current interest to the EIA IBIS Open Forum are addressed at DATE. This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. Any pending formal decisions (votes) will be announced at least two weeks prior to the meeting. Topics and presentations may include (list is open for further contributions): - Submitted Presentations on IBIS Topics (See below) - Information about the most recent IBIS Developments - Less formal Ad Hoc Presentations and Discussions - IBIS and Modelling Questions and Answers The meeting is free and open to everyone. However, you will have to register for the exhibition at DATe (to get access to the meeting room). Refreshments are planned. Below is some information on the IBIS Summit and some related events. You are invited to register and also to submit presentation proposals. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the European IBIS Summit meeting. If you plan to participate, please register with the information below (deadline, Febrary 25th, 2005): Name: E-mail address: Company: Telephone: Send to: Ralf Bruening (ralf.bruening@zuken.de) CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. Some suggested subjects of interest are: - IBIS Model Development Experiences - Company IBIS Standards and Requirements - Generating and Validating IBIS Models - Future IBIS Requirements - Modelling of dedicated technology issues (i.e. connectors, very high speed interfaces) - EMC/EMI IBIS Issues - Experiences using IBIS in the PCB Design process Format of Presentation: LCD or Overhead Projections Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat PDF. Electronic presentations should be made available by February the 25th, 2005. Otherwise the presentor will be expected to provide 30 copies for distribution. If you plan a presentation, please supply Title: Presenter: E-mail address: Company: Telephone: Estimate Time: Send this to both: Ralf Bruening (ralf.bruening@zuken.de) AGENDA The agenda includes presentations, discussions, breaks, and a luncheon (which will be provided). This will be developed as presentation proposals are received. LIST OF NEARBY HOTELS See for travel directions, hotels and other information. Looking forward to meeting you at DATe 2005 in Munich Ralf Bruening _____________________________________________ Ralf Bruening Product Manager High Speed Design/Partner & Solution Business Zuken EMC Technology Center Vattmannstr.3 33100 Paderborn Germany Tel: ++49 (0) 5251 150 600 (direct -621) Fax: ++49 (0) 5251 150 700 Cellular: +49 170 4228512 (alternative: +49 172 9070675) Email: ralf.bruening@zuken.de Web: www.zuken.com _____________________________________________ This message is for the designated recipient only and may contain privileged, proprietary, or otherwise private information. If you have received it in error, please notify the sender immediately and delete the original. Any other use of the email by you is prohibited. |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 18 Jan 2005 16:28:45 -0700 From: rrwolff@micron.com Subject: [IBIS-Users] [IBIS] Open forum minutes (01/07/05) This is a multi-part message in MIME format. - ------_=_NextPart_001_01C4FDB5.74081090 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable - ------_=_NextPart_001_01C4FDB5.74081090 Content-Type: text/plain; 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email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 20 Jan 2005 19:06:55 -0800 From: "Arnab Hazarika" Subject: [IBIS-Users] query regarding ramp functions This is a multi-part message in MIME format. - ------=_NextPart_000_0073_01C4FF23.354F8A80 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi all , I have doubt regarding the ramp down and ramp up functions. While creating the .s2i i have set the simulation time to be 2.5ns. The pulse signal thereby generated by s2ibis in rdn.spi is PULSE(2.5 0 0 2.5e-11 2.5e-11 5e-09 1.01e-08) .TRAN 2.5e-11 2.5e-09 However if i carry ahead with pulse and transient statement then for = the other ramp functions then in the final ibis file i get Ramp] | variable typ min = max dV/dt_r 0.61/0.13n 8.892e-21/-0.58n 0.82/89.36p Now dT must be greater than 0 in a Ramp specification and thereby = winibis flags off an error. So I needed to know how i go about this problem. Looking forward for your comments. Thanking you. warm regards arnab hazarika - ------=_NextPart_000_0073_01C4FF23.354F8A80 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Hi all ,
I have doubt regarding the ramp down = and ramp up=20 functions.
 
 While creating the .s2i i = have set the=20 simulation time to be 2.5ns.
 
 The pulse signal thereby = generated by=20 s2ibis in rdn.spi is
    PULSE(2.5 0 0 = 2.5e-11 2.5e-11=20 5e-09 1.01e-08)
    .TRAN 2.5e-11 =20 2.5e-09
 However if i carry ahead with = pulse and=20 transient statement then for the other ramp functions then in the = final=20 ibis file i get
    Ramp]
|=20 variable      =20  typ          &nbs= p;            = ;      =20 min           &nbs= p;    =20 max
dV/dt_r         =20 0.61/0.13n         =20 8.892e-21/-0.58n    0.82/89.36p
 Now dT must be greater than 0 in = a Ramp=20 specification and thereby winibis flags off an error.
 
 So I needed to know how i go = about this=20 problem.
 
 Looking forward for your=20 comments.
 Thanking you.
 
warm regards
arnab hazarika
 
- ------=_NextPart_000_0073_01C4FF23.354F8A80-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 20 Jan 2005 09:42:29 -0800 From: "Tom Dagostino" Subject: [IBIS-Users] RE: [IBIS] query regarding ramp functions This is a multi-part message in MIME format. - ------=_NextPart_000_00E5_01C4FED4.5BB532A0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Have you looked at the output waveforms to see if the have completed transitions? Tom Dagostino Teraspeed Consulting Group LLC 503-430-1065 tom@teraspeed.com www.teraspeed.com -----Original Message----- From: owner-ibis@eda.org [mailto:owner-ibis@eda.org]On Behalf Of Arnab Hazarika Sent: Thursday, January 20, 2005 7:07 PM To: ibis@eda.org Cc: ibis-users@eda.org Subject: [IBIS] query regarding ramp functions Hi all , I have doubt regarding the ramp down and ramp up functions. While creating the .s2i i have set the simulation time to be 2.5ns. The pulse signal thereby generated by s2ibis in rdn.spi is PULSE(2.5 0 0 2.5e-11 2.5e-11 5e-09 1.01e-08) .TRAN 2.5e-11 2.5e-09 However if i carry ahead with pulse and transient statement then for the other ramp functions then in the final ibis file i get Ramp] | variable typ min max dV/dt_r 0.61/0.13n 8.892e-21/-0.58n 0.82/89.36p Now dT must be greater than 0 in a Ramp specification and thereby winibis flags off an error. So I needed to know how i go about this problem. Looking forward for your comments. Thanking you. warm regards arnab hazarika - ------=_NextPart_000_00E5_01C4FED4.5BB532A0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Have=20 you looked at the output waveforms to see if the have completed=20 transitions?
 

Tom Dagostino
Teraspeed Consulting Group=20 LLC
503-430-1065
tom@teraspeed.com
www.teraspeed.com =

-----Original Message-----
From: owner-ibis@eda.org = [mailto:owner-ibis@eda.org]On Behalf Of Arnab = Hazarika
Sent:=20 Thursday, January 20, 2005 7:07 PM
To: = ibis@eda.org
Cc:=20 ibis-users@eda.org
Subject: [IBIS] query regarding ramp=20 functions

Hi all ,
I have doubt regarding the ramp down = and ramp up=20 functions.
 
 While creating the .s2i i = have set the=20 simulation time to be 2.5ns.
 
 The pulse signal thereby = generated by=20 s2ibis in rdn.spi is
    PULSE(2.5 0 0 = 2.5e-11 2.5e-11=20 5e-09 1.01e-08)
    .TRAN = 2.5e-11 =20 2.5e-09
 However if i carry ahead with = pulse and=20 transient statement then for the other ramp functions then in the = final=20 ibis file i get
    Ramp]
|=20 variable      =20 =  typ          &nbs= p;            = ;      =20 = min           &nbs= p;    =20 max
dV/dt_r         =20 0.61/0.13n         =20 8.892e-21/-0.58n    0.82/89.36p
 Now dT must be greater than 0 = in a Ramp=20 specification and thereby winibis flags off an error.
 
 So I needed to know how i go = about this=20 problem.
 
 Looking forward for your=20 comments.
 Thanking you.
 
warm regards
arnab hazarika
 
- ------=_NextPart_000_00E5_01C4FED4.5BB532A0-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 21 Jan 2005 09:52:01 +0530 From: "Vivek Kumar Sundriyal" Subject: [IBIS-Users] Re: [IBIS] query regarding ramp functions Hi Arnab , One way to get about this problem is to cross check the Tr, Tf for that particular IO buffer. You can also increse the simulation time. Here 2.5ns is very less. Try increasing it to about 10ns and check the results. If this does not work, try with the [Tr] and [Tf]. Thanks , Vivek "Arnab Hazarika" cc: ibis-users@eda.org Sent by: Subject: [IBIS] query regarding ramp functions owner-ibis@eda.or g 01/21/05 08:36 AM Hi all , I have doubt regarding the ramp down and ramp up functions. While creating the .s2i i have set the simulation time to be 2.5ns. The pulse signal thereby generated by s2ibis in rdn.spi is PULSE(2.5 0 0 2.5e-11 2.5e-11 5e-09 1.01e-08) .TRAN 2.5e-11 2.5e-09 However if i carry ahead with pulse and transient statement then for the other ramp functions then in the final ibis file i get Ramp] | variable typ min max dV/dt_r 0.61/0.13n 8.892e-21/-0.58n 0.82/89.36p Now dT must be greater than 0 in a Ramp specification and thereby winibis flags off an error. So I needed to know how i go about this problem. Looking forward for your comments. Thanking you. warm regards arnab hazarika |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 21 Jan 2005 17:15:37 -0800 From: "Mirmak, Michael" Subject: [IBIS-Users] Agenda, IBIS Open Forum Teleconference for January 28, 2005 IBIS Open Forum Meeting Agenda for January 28, 2005 Telephone Number Bridge Passcode 1-916-356-2663 4 066-5906 All meetings are 8:00 AM to 9:55 AM US Pacific Time. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international numbers, please contact Michael Mirmak. 8:00 Check-In, Intros, Announcements Mirmak - Intros of New IBIS Participants, Meeting Quorum Mirmak - Call for Patents (IBIS 4.0/4.1, ICM) Mirmak - Membership Update and Treasurer's Report Mirmak - Review of Previous Meeting's Minutes (and ARs) Mirmak January 7, 2005 Open Forum Minutes - Press & Web Page Updates Huq - New Models Available, Library Update Wang - Announcements, Opens for New Issues All 8:15 Administrative and Project Discussions Mailing List Administration Ross International/External Progress - IEEE & Accellera Liaison Mirmak - Other activities All Summit Status - DesignCon 2005 Mirmak - DATE 2005 - Japan IBIS Event - Other Events ANSI Balloting Status Wolff - IBIS 3.2, 4.x and ICM 1.x S2IBIS3 Status Varma/Ross IBIS 4.1 Parser Status Ross ICM Specification and Parser Status Green/Mirmak Quality Committee Report Haller Model Review Committee Report Green Futures Subcommittee Report Mirmak Cookbook Subcommittee Report Mirmak New Administrative Issues All 8:45 Technical Discussion BIRD92.1: Multiple Terminator and Series Elements Mirmak under [Model] - Call for Vote BIRD94: Clarifications on [Diff Pin] Parameters Muranyi BIRD95: Power Integrity Analysis Using IBIS Huq BIRD96: [Model Spec] and [Receiver Thresholds] Wolff Ordering IIRD2.3: Frequency Dependent RLGC Matrices Mirmak - Call for Vote IIRD8.3: Distinct Model_pinmap and Model_nodemap Ross Names - Call for Vote IBISCHK4 BUG Status Angulo/Mirmak ICMCHK1 BUG Status Green/Mirmak New Technical Issues All 9:50 Wrap Up and Next Meeting Plans Mirmak - January 31, 2005 IBIS Summit at DesignCon - February 18, 2005 IBIS Open Forum Teleconference 9:55 Sign Off |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 21 Jan 2005 18:09:58 -0800 From: "Mirmak, Michael" Subject: [IBIS-Users] DesignCon Conference Catalog As the IBIS Open Forum is holding a Summit at DesignCon 2005 and we fully support all DesignCon activities, we forwarding the attached signup information provided by the DesignCon organizers. Those planning on attending the IBIS Summit at DesignCon should visit the IBIS Summit registration link and sign up - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum The International Engineering Consortium (IEC) together with the IBIS Open Forum invites you to register for DesignCon 2005 , taking place January 31 February 3, 2005, at the Santa Clara Convention Center, Santa Clara, Calif. This annual conference and technology exhibition is designed exclusively for the electronic-design and semiconductor communities and is ideally positioned as the first major conference of the year for our industry. You can view the DesignCon conference catalog in its entirety on the event web site. Highlights of this premier event include: Technology Exhibition: Featuring leading organizations presenting EDA tools, test and measurement equipment, PCBs and related technologies, semiconductor components and IP, interconnect technologies, and more. Don't miss three new elements to the technology exhibition! * The PCB Technology Pavilion provides a showcase for companies demonstrating products that meet the sophisticated needs of printed-circuit board designers. * The Semiconductor Technology Pavilion features companies demonstrating integrated-circuit products and related technologies. * The TecPreviewVillage presents demonstrations of an array of products, services and solutions linked to associated conference papers. Complimentary Programming: Take advantage of a series of free educational opportunities, including the following: * Keynote Addresses delivered by Michael Fister, President and Chief Executive Officer, Cadence Design Systems; Aart de Geus, Chairman and Chief Executive Officer, Synopsys; and, Wally Rhines, Chief Executive Officer and Chairman of the Board of Directors, Mentor Graphics. * Plenary Panel discussing the topical issue of Design Verification: From Specifications to Closure. * Eight exciting conference panels debating relevant issues facing our industry today. Conference Programming: 100+ technical sessions including 40-minute paper presentations and half-day TecForum tutorials providing you with solutions to your most challenging issues. In addition, the IEC Executive Forum @ DesignCon offers a unique educational experience by way of five lively panels comprised of industry leaders sharing their insights, perspectives, predictions and visions in a dynamic and exciting discussion. IBIS Open Forum Summit: Co-located at DesignCon, this annual event, held on January 31 from 8:30 am 5:00 pm, allows you to network with your peers while learning about new versions of the IBIS specification and much more! To review the DesignCon conference schedule, download the DesignCon 2005 conference catalog or visit the on-line schedule . A variety of attractive conference packages are available to meet your professional and personal schedule and needs. We look forward to seeing you in Santa Clara! Best regards, John R. Janowiak Executive Director International Engineering Consortium |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 24 Jan 2005 10:46:23 +0200 From: "Itzik Peleg" Subject: RE: [IBIS-Users] BIRD 95 Comments. Hello Syed Sorry for my late replay. I am still missing something. What are the conditions to capture the current? Capturing the current under some loading conditions can be different from other loading conditions. How the captured current is processed in order to yield the correct buffer loading on the power rail? Please elaborate. Itzik - -----Original Message----- From: Syed Huq [mailto:shuq@cisco.com] Sent: Sunday, January 09, 2005 12:01 AM To: Peleg Itzik Cc: IBIS Users Subject: Re: [IBIS-Users] BIRD 95 Comments. Hi Peleg, Thanks for your comments on the 7th teleconf. Some responses in-line - Syed On Sat, 2005-01-08 at 13:37, Peleg Itzik wrote: > And back to BIRD 95: > > The current is measured with the resistance and inductance of the power > supply rail of the pad. While the rising and falling v(t) table are > measured with ideal supply. > Isn't it better to measure the current on an ideal supply so the current > is correlated to the voltage response that was capture in the rising or > falling wave form. > Please elaborate why the current is measured with the inductance and > resistance. The L_xxx and R_xxx in the diagram are on-die parasitics. These are part of the encrypted SPICE you may have. We wanted to show that these components are present in your netlist as you make your measurements. These user is *not* placing any specific L_xxx or R_xxx to make these measurements. We do want time coreelated V/T and I/T. Ideal supply maynot give you the kind of SSN you wish to simulate. Regards, Syed - -- IBIS Vice-Chair & Webmaster Cisco Systems, Inc |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 24 Jan 2005 18:23:30 +0200 From: Itzik Peleg Subject: [IBIS-Users] Question about [Add submodel] keyword. This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. - ------_=_NextPart_001_01C50231.0A90E596 Content-Type: text/plain Hello All As far as I understand the IBIS spec, when [Add Submodel] keyword is used the I(v) curves that are describe in the submodel are Added to the model corresponding I(v) curve. - -- Regards Itzik Peleg Board Technology Group Marvell Semiconductor Israel Ltd 6 Ha'mada St. Industrial Area P.O.Box 692 Yokneam 20692 ISRAEL Email - itzik.peleg@il.marvell.com Tel - +972 4 9091192 Cell - +972 54 4452482 Fax - +972 4 9091501 WWW Page: http://www.marvell.com ======================================================================== This message may contain confidential, proprietary or legally privileged information. The information is intended only for the use of the individual or entity named above. If the reader of this message is not the intended recipient, you are hereby notified that any dissemination, distribution or copying of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by telephone, or by e-mail and delete the message from your computer. Thank you! ======================================================================== - ------_=_NextPart_001_01C50231.0A90E596 Content-Type: text/html Content-Transfer-Encoding: quoted-printable

Hello All

 

As far as I understand the IBIS spec, when [Add = Submodel] keyword is used the I(v) curves that are describe in the submodel are = Added to the model corresponding = I(v) curve.

 

--
Regards
 
Itzik =
Peleg
Board =
Technology Group
 
Marvell =
Semiconductor Israel Ltd
6 Ha'mada =
St. Industrial =
Area
P.O.Box 692 =
Yokneam  20692<=
/st1:PostalCode>  ISRAEL
Email - = itzik.peleg@il.marvell.com
Tel   - +972 4  =
9091192
Cell  - +972 54 =
4452482
Fax   - +972 4  =
9091501
WWW =
Page: http://www.marvell.com
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D
This =
message may contain confidential, proprietary or legally =
privileged
information. The information is intended =
only for the use of the
individual or entity named above. If the =
reader of this message is not
the =
intended recipient, you are hereby notified that any =
dissemination,
distribution or copying of this =
communication is strictly =
prohibited.
If you =
have received this communication in error, please notify =
us
immediately by telephone, or by e-mail and =
delete the message from
your =
computer.
 
Thank =
you!
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D

 

- ------_=_NextPart_001_01C50231.0A90E596-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 24 Jan 2005 09:25:31 -0800 From: Syed Huq Subject: RE: [IBIS-Users] BIRD 95 Comments. The loading condition will be similar to the R_fixture value used for V/T curves. We also have recommended loading mentioned in BIRD95. One such condition is 'no-load' as well. BIRD95 allows maximum of 100 IvsT curves. Each can be under specific user defined load as well. - - Syed - -- IBIS Vice-Chair & Webmaster Cisco Systems, Inc On Mon, 2005-01-24 at 00:46, Itzik Peleg wrote: > Hello Syed > > Sorry for my late replay. > > I am still missing something. What are the conditions to capture the > current? Capturing the current under some loading conditions can be > different from other loading conditions. How the captured current is > processed in order to yield the correct buffer loading on the power rail? > Please elaborate. > > Itzik > > -----Original Message----- > From: Syed Huq [mailto:shuq@cisco.com] > Sent: Sunday, January 09, 2005 12:01 AM > To: Peleg Itzik > Cc: IBIS Users > Subject: Re: [IBIS-Users] BIRD 95 Comments. > > Hi Peleg, > > Thanks for your comments on the 7th teleconf. Some responses in-line - > Syed > > > On Sat, 2005-01-08 at 13:37, Peleg Itzik wrote: > > > And back to BIRD 95: > > > > The current is measured with the resistance and inductance of the power > > supply rail of the pad. While the rising and falling v(t) table are > > measured with ideal supply. > > Isn't it better to measure the current on an ideal supply so the current > > is correlated to the voltage response that was capture in the rising or > > falling wave form. > > Please elaborate why the current is measured with the inductance and > > resistance. > > The L_xxx and R_xxx in the diagram are on-die parasitics. These are part > of the encrypted SPICE you may have. We wanted to show that these > components are present in your netlist as you make your measurements. > > These user is *not* placing any specific L_xxx or R_xxx to make these > measurements. > > We do want time coreelated V/T and I/T. Ideal supply maynot give you the > kind of SSN you wish to simulate. > > Regards, > Syed |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 25 Jan 2005 14:44:09 +0000 From: "lee yang" Subject: RE: [IBIS-Users] IV Curves Thanks Lynne, i appreciate it very much! >From: "lgreen" >To: "'lee yang'" , >CC: >Subject: RE: [IBIS-Users] IV Curves >Date: Wed, 12 Jan 2005 21:30:05 -0800 > >Lee- > >Consider Randy's case 1, except switching from Vcc to 0V: >The reflected voltage (Vr) would be forward voltage (Vf)*RC = -Vcc*1 = -Vcc >The load voltage (Vload) is Vf+Vr = -Vcc+(0) = -Vcc > >You might consider checking out some of the excellent transmission line >textbooks. The books by Dr. Johnson and by Eric Bogatin are also good. > >- Lynne > >-----Original Message----- >From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf >Of lee yang >Sent: Wednesday, January 12, 2005 4:02 PM >To: rrwolff@micron.com >Cc: ibis-users@eda.org >Subject: RE: [IBIS-Users] IV Curves > >Hi Randy Wolff, >Thanks a lot for your detail and useful explaination, i appreciate it very >much. Now, i have a much better idea about the reflection. >I have a further question: >In case 3 below, although the reflected voltage is -vcc, the total voltage >in driver site is 0V. Do you have any example that shows the voltage at >driver site is at -vcc? (which is cover by IBIS voltage range.) >Many thanks. > >Appreciated, >Lee > > > > > >|------------------------------------------------------------------ >|For help or to subscribe/unsubscribe, email majordomo@eda.org >|with just the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or email a written request to ibis-request@eda.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda.org/pub/ibis/email_archive/ Recent >| http://www.eda.org/pub/ibis/users_archive/ Recent >| http://www.eda.org/pub/ibis/email/ E-mail since 1993 _________________________________________________________________ Find answers fast with MSN Search BETA. Find answers fast with MSN Search BETA. New look and improved results. Give it a try! |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 25 Jan 2005 12:39:32 -0800 From: Syed Huq Subject: [IBIS-Users] DesignCon 2005 IBIS Summit - Agenda - ------------------------------------------------------------------ AGENDA, IBIS SUMMIT MEETING January 31, 2005 Santa Clara Convention Center Santa Clara, California Room: Magnolia Room, Westin Hotel (check signs at site) - ------------------------------------------------------------------ 8:00 AM Refreshments & Sign In 8:30 AM Introductions - Welcome to Summit - Introductions - IBIS Booth 940 - Opens for Issues, Discussion Topics 8:45 AM IBIS Chair's Report and Roadmap Michael Mirmak, Intel Corporation 9:00 AM IBIS Quality Committee Report Kim Helliwell, Silicon Bandwidth, Inc. 9:30 AM An Initial Case Study for BIRD95 - Enhancing IBIS for SSO Power Integrity Simulation Sam Chitwood, Raymond Chen, Jiayuan Fang Sigrity Inc. 10:00 AM BREAK 10:15 AM BIRD95 and Power Integrity Validation using HSPICE Syed Huq, , Vinu Arumugham, Dr.Zhiping Yang Cisco Systems, Inc 10:45 AM BIRD95 Technical Discussion - All Syed Huq, Vinu Arumugham, and Dr.Zhiping Yang Cisco Systems, Inc 12:00 PM LUNCH - (Hosted by DesignCon) Pre-registration required 1:00 PM IBIS Power/Ground Modeling of LSI Core Logic with High Pin Count Package for EMI and PI Norio Matsui, Applied Simulation Technology Hiroshi Wabuka, NEC 1:30 PM Modeling Pre/De-emphasis Buffers with [Driver Schedule] Arpad Muranyi, Intel Corporation 2:00 PM Modeling Complex IOs with IBIS 4.1 Donald Telian, Cadence Design Systems 2:30 PM Stacked Package Modeling with IBIS Version 4.1 Tom Dagostino and Bob Ross, Teraspeed Consulting Group 3:00 PM BREAK 3:15 PM Practical Issues in Enabling a Corporate IBIS Library Todd Westerhoff, Cisco Systems, Inc 3:45 PM A Preview of the IBIS 4.0 Cookbook Michael Mirmak, Intel Corporation 4:15 PM Searching the WWW for Spice and IBIS Kellee Crisafulli, CelsioniX, Inc. 4:45 PM Opens/Discussion 4:55 PM Concluding Items - Next Open Forum Meeting, February 18 2005 - DATE 2005, March 11, 2005, Paris, France 5:00 PM End of IBIS Summit Meeting - ------------------------------------------------------------------ REGISTRATION INFORMATION People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Send to: Syed Huq(shuq@cisco.com) Lunch registration is separate. To register for lunch, you must be registered for DesignCon (information at ). - ------------------------------------------------------------------ Sponsors: DesignCon, Cisco Systems and Cadence Design Systems DesignCon: January 31-February 3, 2005 Santa Clara Convention Center Santa Clara, California See for more information. LIST OF NEARBY HOTELS See for travel directions, hotels and other information. |------------------------------------------------------------------ |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 27 Jan 2005 15:20:48 -0700 From: "Johnson Jr, Robert H. (FL51)" Subject: [IBIS-Users] IBIS LVDS Receiver 100 ohm termination modeling Is this the standard approach for modeling an LVDS receiver with a 100 ohm termination? [Series Pin Mapping] pin_2 model_name function_table_group | A B rterm_100 [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max | A B 100mV 0 0 0 | ************************************************************************ | 100ohm differential resistor |************************************************************************ | [Model] rterm_100 Model_type Series | | (typ) (min) (max) | C_comp 0.1000pF 0.1000pF 0.1000pF [Temperature Range] 25.0000 100.0000 0.000 [Voltage Range] 2.5000V 2.3750V 2.6250V [R Series] 105 125 80 thanks, Bob |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 27 Jan 2005 14:30:41 -0800 From: "Beal, Weston" Subject: RE: [IBIS-Users] IBIS LVDS Receiver 100 ohm termination modeling Yes, if your simulator supports this syntax. - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Johnson Jr, Robert H. (FL51) Sent: Thursday, January 27, 2005 2:21 PM To: ibis-users@eda.org Subject: [IBIS-Users] IBIS LVDS Receiver 100 ohm termination modeling Is this the standard approach for modeling an LVDS receiver with a 100 ohm termination? [Series Pin Mapping] pin_2 model_name function_table_group | A B rterm_100 [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max | A B 100mV 0 0 0 | ************************************************************************ | 100ohm differential resistor |*********************************************************************** |* | [Model] rterm_100 Model_type Series | | (typ) (min) (max) | C_comp 0.1000pF 0.1000pF 0.1000pF [Temperature Range] 25.0000 100.0000 0.000 [Voltage Range] 2.5000V 2.3750V 2.6250V [R Series] 105 125 80 thanks, Bob |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org with just |the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 27 Jan 2005 14:42:37 -0800 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] IBIS LVDS Receiver 100 ohm termination modeling Bob, Thank you for your interest in IBIS! What you propose certainly looks feasible. In addition to the syntax you show, you might also consider adding single-ended buffer models for each of the A and B pins, if these demonstrate diode clamping behaviors, single-ended internal terminations and/or other features not captured by just the series resistive element between the pins. The IBIS specification permits single-ended buffers to be used in conjunction with series elements. Also note that, if the resistance of your receiver termination is non-linear but is time-invariant, you might instead use [Series Current] or [Series MOSFET] in place of [R Series]. - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Johnson Jr, Robert H. (FL51) Sent: Thursday, January 27, 2005 2:21 PM To: ibis-users@eda.org Subject: [IBIS-Users] IBIS LVDS Receiver 100 ohm termination modeling Is this the standard approach for modeling an LVDS receiver with a 100 ohm termination? [Series Pin Mapping] pin_2 model_name function_table_group | A B rterm_100 [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max | A B 100mV 0 0 0 | ************************************************************************ | 100ohm differential resistor |*********************************************************************** * | [Model] rterm_100 Model_type Series | | (typ) (min) (max) | C_comp 0.1000pF 0.1000pF 0.1000pF [Temperature Range] 25.0000 100.0000 0.000 [Voltage Range] 2.5000V 2.3750V 2.6250V [R Series] 105 125 80 thanks, Bob |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sun, 30 Jan 2005 10:19:03 -0800 From: "Mirmak, Michael" Subject: [IBIS-Users] BIRD95.1 - Power Integrity Analysis using IBIS This is a multi-part message in MIME format. - ------_=_NextPart_001_01C506F8.3A7A4A25 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable The enclosed revised BIRD, Power Integrity Analysis using IBIS, is submitted on behalf of Syed Huq, Vinu Arumugham and Zhiping Yang of Cisco Systems, Inc. It will be discussed at the February 18th IBIS Open Forum teleconference and also at the DesignCon 2005 IBIS Summit on January 31 (printed copies will be available at the summit). - - Michael Mirmak Intel Corp. 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Jan 2005 05:34:54 +0000 From: "lee yang" Subject: [IBIS-Users] VHDL-AMS Model Hi, Recently I heard about another behavioral model call VHDL-AMS, can anyone please give some background about it? Since we already have IBIS model, what is the reason we need to use VHDL-AMS model instead? What is the pros and cons compared to IBIS model? Thanks and appreciate if someone can shed some light. - -Lee Yang _________________________________________________________________ Find love online with MSN Personals. http://match.msn.com.my/match/mt.cfm?pg=channel |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 31 Jan 2005 08:40:14 -0800 From: "lgreen" Subject: RE: [IBIS-Users] VHDL-AMS Model Hello, Lee, An excellent question. VHDL-AMS (and Verilog-AMS) are standards. They support mixed-signal modeling. One can express a functional block, such as a MUX or I/O buffer, as a digital, analog, or mixed-signal block. Analog blocks can be expressed as equations, including if/then controls, which has both advantages over table-based models (such as taking into account independent variations with Vcc and Temperature). Starting with IBIS 4.1, VHDL-AMS, Verilog-AMS, and SPICE 3f5 models are allowed as model formats for IBIS, under the [Model] keyword. All of these can be used as behavioral or structural descriptions of a block, such as an I/O buffer or a MUX. Please see the IBIS 4.1 specification for details. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of lee yang Sent: Sunday, January 30, 2005 9:35 PM To: ibis-users@eda.org Subject: [IBIS-Users] VHDL-AMS Model Hi, Recently I heard about another behavioral model call VHDL-AMS, can anyone please give some background about it? Since we already have IBIS model, what is the reason we need to use VHDL-AMS model instead? What is the pros and cons compared to IBIS model? Thanks and appreciate if someone can shed some light. - -Lee Yang |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 01 Feb 2005 13:41:23 +0000 From: "lee yang" Subject: RE: [IBIS-Users] VHDL-AMS Model Hello Lynne, Thanks a lot for your prompt responce and the useful information. Do you have a link or document showing how to model the VHDL-AMS model? Btw, what tools support the simulation of VHDL-AMS model? Are HyperLynx and Hspice able to simulate this model? Thanks again for your excellent support so far. - - Lee >From: "lgreen" >To: "'lee yang'" , >Subject: RE: [IBIS-Users] VHDL-AMS Model >Date: Mon, 31 Jan 2005 08:40:14 -0800 > >Hello, Lee, > >An excellent question. > >VHDL-AMS (and Verilog-AMS) are standards. They support mixed-signal >modeling. One can express a functional block, such as a MUX or I/O buffer, >as a digital, analog, or mixed-signal block. Analog blocks can be >expressed >as equations, including if/then controls, which has both advantages over >table-based models (such as taking into account independent variations with >Vcc and Temperature). > >Starting with IBIS 4.1, VHDL-AMS, Verilog-AMS, and SPICE 3f5 models are >allowed as model formats for IBIS, under the [Model] keyword. All of these >can be used as behavioral or structural descriptions of a block, such as an >I/O buffer or a MUX. Please see the IBIS 4.1 specification for details. > >Best regards, >Lynne > >"IBIS training when you need it, where you need it." > >Dr. Lynne Green >Green Streak Programs >http://www.greenstreakprograms.com >425-788-0412 >lgreen22@mindspring.com > > >-----Original Message----- >From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf >Of lee yang >Sent: Sunday, January 30, 2005 9:35 PM >To: ibis-users@eda.org >Subject: [IBIS-Users] VHDL-AMS Model > >Hi, > >Recently I heard about another behavioral model call VHDL-AMS, can anyone >please give some background about it? >Since we already have IBIS model, what is the reason we need to use >VHDL-AMS > >model instead? What is the pros and cons compared to IBIS model? >Thanks and appreciate if someone can shed some light. > >-Lee Yang > > > >|------------------------------------------------------------------ >|For help or to subscribe/unsubscribe, email majordomo@eda.org >|with just the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or email a written request to ibis-request@eda.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda.org/pub/ibis/email_archive/ Recent >| http://www.eda.org/pub/ibis/users_archive/ Recent >| http://www.eda.org/pub/ibis/email/ E-mail since 1993 _________________________________________________________________ Get your mobile ringtones, operator logos and picture messages from MSN Mobile http://msn.smsfactory.no/ |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 1 Feb 2005 08:47:18 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] VHDL-AMS Model Lee, There are a few presentations on this subject: http://www.eda.org/pub/ibis/summits/jun03b/muranyi1.pdf http://www.eda.org/pub/ibis/summits/feb04a/muranyi2.pdf Regarding tool support, HSPICE doesn't support the VHDL-AMS language, but there are many other tools which do. Do a little research on the web, and you will find out who has what. Arpad ======================================================= - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of lee yang Sent: Tuesday, February 01, 2005 5:41 AM To: lgreen22@mindspring.com; ibis-users@eda.org Subject: RE: [IBIS-Users] VHDL-AMS Model Hello Lynne, Thanks a lot for your prompt responce and the useful information. Do you have a link or document showing how to model the VHDL-AMS model? Btw, what tools support the simulation of VHDL-AMS model? Are HyperLynx and Hspice able to simulate this model? Thanks again for your excellent support so far. - - Lee |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 1 Feb 2005 08:49:41 -0800 From: "lgreen" Subject: RE: [IBIS-Users] VHDL-AMS Model Hello, Lee, There are a number of simulators that can handle *-AMS with IBIS and SPICE. HyperLynx does this using Mentor's "Eldo" simulator. Perhaps others on this list can comment on HSPICE, SPECCTRAQuest, and other tools. Links to the standards organizations: http://www.vhdl.org/analog/ (IEEE 1076.1 Working Group) http://www.eda.org/verilog-ams/ (Accellera Verilog Analog Mixed-Signal Group) Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com - -----Original Message----- From: lee yang [mailto:changly_80@hotmail.com] Sent: Tuesday, February 01, 2005 5:41 AM To: lgreen22@mindspring.com; ibis-users@eda.org Subject: RE: [IBIS-Users] VHDL-AMS Model Hello Lynne, Thanks a lot for your prompt responce and the useful information. Do you have a link or document showing how to model the VHDL-AMS model? Btw, what tools support the simulation of VHDL-AMS model? Are HyperLynx and Hspice able to simulate this model? Thanks again for your excellent support so far. - - Lee >From: "lgreen" >To: "'lee yang'" , >Subject: RE: [IBIS-Users] VHDL-AMS Model >Date: Mon, 31 Jan 2005 08:40:14 -0800 > >Hello, Lee, > >An excellent question. > >VHDL-AMS (and Verilog-AMS) are standards. They support mixed-signal >modeling. One can express a functional block, such as a MUX or I/O buffer, >as a digital, analog, or mixed-signal block. Analog blocks can be >expressed >as equations, including if/then controls, which has both advantages over >table-based models (such as taking into account independent variations with >Vcc and Temperature). > >Starting with IBIS 4.1, VHDL-AMS, Verilog-AMS, and SPICE 3f5 models are >allowed as model formats for IBIS, under the [Model] keyword. All of these >can be used as behavioral or structural descriptions of a block, such as an >I/O buffer or a MUX. Please see the IBIS 4.1 specification for details. > >Best regards, >Lynne > >"IBIS training when you need it, where you need it." > >Dr. Lynne Green >Green Streak Programs >http://www.greenstreakprograms.com >425-788-0412 >lgreen22@mindspring.com > > >-----Original Message----- >From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf >Of lee yang >Sent: Sunday, January 30, 2005 9:35 PM >To: ibis-users@eda.org >Subject: [IBIS-Users] VHDL-AMS Model > >Hi, > >Recently I heard about another behavioral model call VHDL-AMS, can anyone >please give some background about it? >Since we already have IBIS model, what is the reason we need to use >VHDL-AMS > >model instead? What is the pros and cons compared to IBIS model? >Thanks and appreciate if someone can shed some light. > >-Lee Yang > |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 1 Feb 2005 09:21:24 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] VHDL-AMS Model Lee, The biggest difference between (legacy) IBIS and VHDL-AMS models is flexibility. First, the IBIS v4.1 specification allows you to use VHDL-AMS, Verilog-AMS models as external models, that's why I refer to the older IBIS capabilities as legacy IBIS. So the biggest problem with legacy IBIS was that the algorithms were all predefined, and the IBIS file would just give you data for those algorithms. Every time there was a change in the behavior of the buffers we wanted to model we had to come up with a new keyword and this took a prohibitively long time. VHDL-AMS and Verilog-AMS are more like programming languages. You can write equations almost any whichever way you want. Therefore basically sky is the limit as far as modeling is concerned. This is a wonderful thing, because all those limitations that existed in legacy IBIS models can be done away without possibly having to change anything in the spec any more. On the other hand, this may make it somewhat more difficult for the model maker, because they will have to learn the language, and they will also need to learn how to translate a certain behavior they observe into the form of equations. This may not necessarily have to be a big concern, though, because I believe that there will be many models written in these languages which will be used as templates, so that by providing parameters for them they could be used for many devices as long as they belong to the same general family. I hope this helps you to understand what these languages can do. Thanks, Arpad ================================================================= - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of lee yang Sent: Sunday, January 30, 2005 9:35 PM To: ibis-users@eda.org Subject: [IBIS-Users] VHDL-AMS Model Hi, Recently I heard about another behavioral model call VHDL-AMS, can anyone please give some background about it? Since we already have IBIS model, what is the reason we need to use VHDL-AMS model instead? What is the pros and cons compared to IBIS model? Thanks and appreciate if someone can shed some light. - -Lee Yang |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 1 Feb 2005 09:27:03 -0800 From: "Beal, Weston" Subject: RE: [IBIS-Users] VHDL-AMS Model For clarification, Eldo is a SPICE simulator so it doesn't include the VHDL-AMS simulator. The integration of Eldo and the VHDL-AMS simulator (with some others) is called ADMS. At this time HyperLynx LineSim and BoardSim can use SPICE models and run either Eldo or HSPICE (if you have HSPICE licensed from Synopsys). In the future HyperLynx will run ADMS behind the scenes also. About two years ago ICX got the power to run ADMS under the covers so it can simulate with IBIS, SPICE, VHDL-AMS, and S-parameters at the same time. As far as I know, this is the first tool anywhere that can automatically create the netlist from a PCB and run a simulation with any or all of the above mentioned models and verify the results against SI and delay constraints. I hope this isn't considered too product oriented for this list. I just wanted to make sure that we're talking about the correct features in this discussion. - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of lgreen Sent: Tuesday, February 01, 2005 8:50 AM To: 'lee yang'; ibis-users@eda.org Subject: RE: [IBIS-Users] VHDL-AMS Model Hello, Lee, There are a number of simulators that can handle *-AMS with IBIS and SPICE. HyperLynx does this using Mentor's "Eldo" simulator. Perhaps others on this list can comment on HSPICE, SPECCTRAQuest, and other tools. Links to the standards organizations: http://www.vhdl.org/analog/ (IEEE 1076.1 Working Group) http://www.eda.org/verilog-ams/ (Accellera Verilog Analog Mixed-Signal Group) Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com - -----Original Message----- From: lee yang [mailto:changly_80@hotmail.com] Sent: Tuesday, February 01, 2005 5:41 AM To: lgreen22@mindspring.com; ibis-users@eda.org Subject: RE: [IBIS-Users] VHDL-AMS Model Hello Lynne, Thanks a lot for your prompt responce and the useful information. Do you have a link or document showing how to model the VHDL-AMS model? Btw, what tools support the simulation of VHDL-AMS model? Are HyperLynx and Hspice able to simulate this model? Thanks again for your excellent support so far. - - Lee >From: "lgreen" >To: "'lee yang'" , >Subject: RE: [IBIS-Users] VHDL-AMS Model >Date: Mon, 31 Jan 2005 08:40:14 -0800 > >Hello, Lee, > >An excellent question. > >VHDL-AMS (and Verilog-AMS) are standards. They support mixed-signal >modeling. One can express a functional block, such as a MUX or I/O >buffer, as a digital, analog, or mixed-signal block. Analog blocks can >be expressed as equations, including if/then controls, which has both >advantages over table-based models (such as taking into account >independent variations with Vcc and Temperature). > >Starting with IBIS 4.1, VHDL-AMS, Verilog-AMS, and SPICE 3f5 models are >allowed as model formats for IBIS, under the [Model] keyword. All of >these can be used as behavioral or structural descriptions of a block, >such as an I/O buffer or a MUX. Please see the IBIS 4.1 specification for details. > >Best regards, >Lynne > >"IBIS training when you need it, where you need it." > >Dr. Lynne Green >Green Streak Programs >http://www.greenstreakprograms.com >425-788-0412 >lgreen22@mindspring.com > > >-----Original Message----- >From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On >Behalf Of lee yang >Sent: Sunday, January 30, 2005 9:35 PM >To: ibis-users@eda.org >Subject: [IBIS-Users] VHDL-AMS Model > >Hi, > >Recently I heard about another behavioral model call VHDL-AMS, can >anyone please give some background about it? >Since we already have IBIS model, what is the reason we need to use >VHDL-AMS > >model instead? What is the pros and cons compared to IBIS model? >Thanks and appreciate if someone can shed some light. > >-Lee Yang > |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org with just |the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 2 Feb 2005 02:19:24 -0500 From: "Pratt, Gary" Subject: RE: [IBIS-Users] VHDL-AMS Model Hi Lee, You responded directly, but I thought your question would be of interest to the greater group ... Your question of ease and accuracy can be answered on several levels. For instance, assuming you could develop a traditional IBIS 3.x model for a high-speed source-synchronous serial I/O (note 1), it will take an enormous amount of time to create a model for each permutation of configuration. For instance, assume your driver has 4 different voltage levels, 4 different pre-emphasis levels, 2 different terminations, and 3 different process corners; you have 96 different IBIS models to create. A VHDL-AMS model would be much easier to develop, and much easier for your model users to manage the configurations. (Note 1: I've heard strong arguments both ways on this issue. Since I don't have any first-hand experience, I won't comment either way. ) On the other hand, there is currently no spice-to-vhdlams tool like there is spice-to-ibis. So, it is currently up to the model creator to make the appropriate SPICE simulations of the transistor-level design, make the appropriate measurements, and build those measurements into a VHDL-AMS model. In that respect, using spice-to-ibis for a simple IBIS model would be much easier. Though, hopefully, as the popularity of AMS grows, spice-to-AMS tools will become available. As for accuracy, because VHDL-AMS allows more degrees of modeling freedom, my feeling is that it can be more accurate than IBIS. However, on well-behaved drivers which fits the IBIS model template well, there may be no difference in accuracy. On the other hand, since I have no idea how to model a receiver containing internal equalization in traditional IBIS, for me, a VHDL-AMS model would be infinitely more accurate in this application. Likewise, for attempting to use IBIS for power integrity purposes, etc. In summary, I would say if your model will fit the traditional IBIS 3.x mold, use traditional IBIS. If not, consider VHDL-AMS. You should also be aware that in addition to AMS languages, IBIS 4.1 allows for modeling with Berkeley SPICE primitives. This can be an easier alternative for someone knowledgeable in SPICE doing some simple modeling. SPICE versus AMS is somewhat analogous to Unix scripting versus C programming. Like UNIX scripting, SPICE provides some basic building blocks that are easy to assemble and run. But also like UNIX, scripting will run slower, and if your scripting requires more complexity than is provided in the basic UNIX commands, it can be difficult or impossible to accomplish your task without someone creating another UNIX command for you (most likely, in C). In the case of SPICE, you would need to convince your SPICE tool vendor of the need for the additional building block, then wait for them to implement and release the new feature (then hope that all SPICE vendors follow suit so your model will be relatively universal). In the case of AMS, if you need some additional functionality, you just add it to your model. Since the AMS language is self contained, anything you add to the model will be immediately available to anyone using a simulator which supports the IBIS 4.1 VHDL-AMS standard. Speaking of support, I believe Mentor Graphics is currently the only EDA vendor who currently supports an AMS language in an SI tool. But, I also understand that the other two major EDA vendors have working VHDL-AMS simulators in-house. So, hopefully they will all be porting these to their SI tools in the future. I hope that helps, Gary - -----Original Message----- From: lee yang [mailto:changly_80@hotmail.com] Sent: Tuesday, February 01, 2005 7:46 AM To: Pratt, Gary Subject: RE: [IBIS-Users] VHDL-AMS Model Hi Gary, Appreciate the information you provided. Does it mean that VHLS-AMS model is much easier to be produced compared to IBIS model? Do we need to run the Hspice simulation in order to generate the VHDL-AMS model like what is being done to generate IBIS model? What is the accuracy of the model compared to IBIS model? Thanks a lot and hope to hear from you soon! - -Lee >From: "Pratt, Gary" >To: "lee yang" , >Subject: RE: [IBIS-Users] VHDL-AMS Model >Date: Mon, 31 Jan 2005 12:18:49 -0500 > >Hello Lee, > >A simple answer to your question is VHDL-AMS provides a high level of >flexibility. So for instance, instead of waiting for functionality to >be added to the IBIS standard and then waiting for SI tool vendors to >implement the function; VHDL-AMS provides you the ability to implement >the function immediately. To date, the flexibility of VHDL-AMS has >provided significant benefit in simplifying modeling of highly >configurable devices such as PCI Express drivers and difficult to model >receivers containing internal equalization. I suspect VHDL-AMS could >also be applied to implementing the functionality required for modeling >power integrity. > >Gary > > > >-----Original Message----- >From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On >Behalf Of lee yang >Sent: Sunday, January 30, 2005 11:35 PM >To: ibis-users@eda.org >Subject: [IBIS-Users] VHDL-AMS Model > >Hi, > >Recently I heard about another behavioral model call VHDL-AMS, can >anyone please give some background about it? >Since we already have IBIS model, what is the reason we need to use >VHDL-AMS model instead? What is the pros and cons compared to IBIS >model? >Thanks and appreciate if someone can shed some light. > >-Lee Yang > >_________________________________________________________________ >Find love online with MSN Personals. >http://match.msn.com.my/match/mt.cfm?pg=channel > >|------------------------------------------------------------------ >|For help or to subscribe/unsubscribe, email majordomo@eda.org with >|just > >|the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or email a written request to ibis-request@eda.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda.org/pub/ibis/email_archive/ Recent >| http://www.eda.org/pub/ibis/users_archive/ Recent >| http://www.eda.org/pub/ibis/email/ E-mail since 1993 _________________________________________________________________ Find just what you are after with the more precise, more powerful new MSN Search. http://search.msn.com.my/ Try it now. |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 03 Feb 2005 13:39:15 +0000 From: "lee yang" Subject: RE: [IBIS-Users] VHDL-AMS Model Hello all, Thanks a lot for the information. It is very informative and helpful. Much appreciated with the responces. - -Lee >From: "Muranyi, Arpad" >To: >Subject: RE: [IBIS-Users] VHDL-AMS Model >Date: Tue, 1 Feb 2005 09:21:24 -0800 > >Lee, > >The biggest difference between (legacy) IBIS and VHDL-AMS models >is flexibility. First, the IBIS v4.1 specification allows you to >use VHDL-AMS, Verilog-AMS models as external models, that's why >I refer to the older IBIS capabilities as legacy IBIS. > >So the biggest problem with legacy IBIS was that the algorithms >were all predefined, and the IBIS file would just give you data >for those algorithms. Every time there was a change in the behavior >of the buffers we wanted to model we had to come up with a new >keyword and this took a prohibitively long time. > >VHDL-AMS and Verilog-AMS are more like programming languages. >You can write equations almost any whichever way you want. >Therefore basically sky is the limit as far as modeling is >concerned. > >This is a wonderful thing, because all those limitations that >existed in legacy IBIS models can be done away without possibly >having to change anything in the spec any more. On the other hand, >this may make it somewhat more difficult for the model maker, >because they will have to learn the language, and they will also >need to learn how to translate a certain behavior they observe >into the form of equations. This may not necessarily have to be >a big concern, though, because I believe that there will be many >models written in these languages which will be used as templates, >so that by providing parameters for them they could be used for >many devices as long as they belong to the same general family. > >I hope this helps you to understand what these languages can do. > >Thanks, > >Arpad >================================================================= > > > >-----Original Message----- >From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf >Of lee yang >Sent: Sunday, January 30, 2005 9:35 PM >To: ibis-users@eda.org >Subject: [IBIS-Users] VHDL-AMS Model > >Hi, > >Recently I heard about another behavioral model call VHDL-AMS, can anyone >please give some background about it? >Since we already have IBIS model, what is the reason we need to use >VHDL-AMS >model instead? What is the pros and cons compared to IBIS model? >Thanks and appreciate if someone can shed some light. > >-Lee Yang > >|------------------------------------------------------------------ >|For help or to subscribe/unsubscribe, email majordomo@eda.org >|with just the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or email a written request to ibis-request@eda.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda.org/pub/ibis/email_archive/ Recent >| http://www.eda.org/pub/ibis/users_archive/ Recent >| http://www.eda.org/pub/ibis/email/ E-mail since 1993 _________________________________________________________________ Get an advanced look at the new version of MSN Messenger. http://messenger.msn.com.my/Beta/Default.aspx |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 10 Feb 2005 13:05:10 -0800 From: "Arnab Hazarika" Subject: Re: [IBIS-Users] Query on Pullup/Pulldown Hi all, Its mentioned that the pullup current we see in the model is the difference of the 2 currents one generated in dut1.spi and other generated in put1.spi.But when i open the corresponding .out files the difference doesnt seem to be the same as against the pullup data. Also i have problem regarding the warninfg that flags of due to the Monotonicity in the V/I curves. thanks®ards arnab hazarika - ----- Original Message ----- From: "Ambrish Varma" To: "'Vivek Kumar Sundriyal'" ; Sent: Friday, January 14, 2005 8:49 AM Subject: RE: [IBIS-Users] Query on Pullup/Pulldown > Hello Vivek, > put1.spi is the setup file for the entire driver whereas dut1.spi is the > file with the driver disabled (to get the clamp current). > > The pullup current you see in the model is the difference of the 2 currents > to give the performance of only the driver. > > We then take only a few points from the linear part of the curve and a > majority of points from the 'interesting' part of the curve. > > That's a 100 feet view of how things are done in s2ibis2. > > Hope that helps, > Ambrish. > > > Ambrish K Varma > akvarma@ncsu.edu > North Carolina State University > ph(919)513-2015, fax(919)515-2285 > > -----Original Message----- > From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf > Of Vivek Kumar Sundriyal > Sent: Friday, January 14, 2005 7:12 AM > To: ibis-users@eda.org; owner-ibis-users@eda.org > Subject: [IBIS-Users] Query on Pullup/Pulldown > > Hi , > > Working on s2ibis2, i find put1.spi and dut1.spi for the generation of > the > pullup data. > > Can anyone explain why do we need two sets of files for the pull up > data ? > > How does s2ibis2 extrapolate/interpolate these values into the final > .ibs > file ? > > Thanks, > > Vivek > > > > > > > > > |------------------------------------------------------------------ > |For help or to subscribe/unsubscribe, email majordomo@eda.org > |with just the appropriate command message(s) in the body: > | > | help > | subscribe ibis > | subscribe ibis-users > | unsubscribe ibis > | unsubscribe ibis-users > | > |or email a written request to ibis-request@eda.org. > | > |IBIS reflector archives exist under: > | > | http://www.eda.org/pub/ibis/email_archive/ Recent > | http://www.eda.org/pub/ibis/users_archive/ Recent > | http://www.eda.org/pub/ibis/email/ E-mail since 1993 > > > |------------------------------------------------------------------ > |For help or to subscribe/unsubscribe, email majordomo@eda.org > |with just the appropriate command message(s) in the body: > | > | help > | subscribe ibis > | subscribe ibis-users > | unsubscribe ibis > | unsubscribe ibis-users > | > |or email a written request to ibis-request@eda.org. > | > |IBIS reflector archives exist under: > | > | http://www.eda.org/pub/ibis/email_archive/ Recent > | http://www.eda.org/pub/ibis/users_archive/ Recent > | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 10 Feb 2005 08:57:06 -0700 From: rrwolff@micron.com Subject: [IBIS-Users] [IBIS] Open forum minutes (01/28/05) This is a multi-part message in MIME format. - ------_=_NextPart_001_01C50F89.2B71C59C Content-Type: multipart/alternative; boundary="----_=_NextPart_002_01C50F89.2B71C59C" - ------_=_NextPart_002_01C50F89.2B71C59C Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable <>=20 - ------_=_NextPart_002_01C50F89.2B71C59C Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [IBIS] Open forum minutes (01/28/05)

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