From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #56 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Thursday, April 14 2005 Volume 01 : Number 056 ---------------------------------------------------------------------- Date: Fri, 25 Mar 2005 09:14:44 -0800 From: Syed Huq Subject: [IBIS-Users] Agenda, IBIS Open Forum Teleconference for April 1st 2005 IBIS Open Forum Meeting Agenda for April 1, 2005 Telephone Number Bridge Passcode 1-916-356-2663 1 350-5998 All meetings are 8:00 AM to 9:55 AM US Pacific Time. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international numbers, please contact Michael Mirmak. 8:00 Check-In, Intros, Announcements Huq - Intros of New IBIS Participants, Meeting Quorum Huq - Call for Patents (IBIS, ICM) Huq - Membership Update and Treasurer's Report Huq - Review of Previous Meeting's Minutes (and ARs) Huq March 11, 2005 Open Forum Minutes March 11, 2005 European IBIS Summit Minutes - Press & Web Page Updates Huq - New Models Available, Library Update Wang - Meeting Procedure through May Huq - Announcements, Opens for New Issues All 8:15 Administrative and Project Discussions Mailing List Administration Ross International/External Progress All Summit Status All - DATE Feedback - Japan IBIS Event Feedback - DAC 2005 - Other Events EIA/ANSI Balloting Status Wolff - IBIS 3.2, 4.x and ICM 1.x S2IBIS3 Status Varma/Ross IBIS 4.1 Parser Status Ross ICM Specification and Parser Status Green/Huq - Second 1.1 "Reading" and Call for Comment - Parser License fee Ross/Huq Quality Committee Report Haller Model Review Committee Report Green Futures Subcommittee Report Huq Cookbook Subcommittee Report Huq New Administrative Issues All 8:45 Technical Discussion BIRD94.1: Clarifications on [Diff Pin] Parameters Muranyi BIRD95.3: Power Integrity Analysis using IBIS Huq BIRD97: Gate Modulation Effect Muranyi IBISCHK4 BUG Status All - Ver 4.1.0 bug - BUG87 - Reentry of BUG82 Ross ICMCHK1 BUG Status All New Technical Issues All 9:50 Wrap Up and Next Meeting Plans Huq - April 22, 2005 IBIS Open Forum Teleconference 9:55 Sign Off |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 28 Mar 2005 15:35:31 -0600 From: "RODRIGUEZ_LECONA_RAMIRO" Subject: [IBIS-Users] V-t tables generation Hi all, When I generate the V-t tables for an output IBIS model I have to apply a transition in its input. If the datasheet specify an output rise/fall time range between, for example, 0.1ns min and 1.0 ns max, What is the rise/fall time I have to apply to the input transition? How do the IBIS simulators implement the rising/falling waveforms when the IBIS model was generated with a rise/fall time smaller than the the rise/fall time used to switch the buffer? Regards, Ramiro |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 28 Mar 2005 14:12:08 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] V-t tables generation Ramiro, Theoretically it shouldn't matter. The reason is because the I/O buffer model should have enough pre-drivers before the output stage so that the input to the first pre-driver should not effect the output of the final stage. For this reason I would recommend that you should apply the fastest edge possible, because the Vt curves must be time correlated, and due to the input threshold voltage variations between rising and falling edge inputs, the faster the stimulus is, the better your time correlation will be. Arpad Muranyi Intel Corporation - ---------------------------------------------------------- - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of RODRIGUEZ_LECONA_RAMIRO Sent: Monday, March 28, 2005 1:36 PM To: ibis-info@eda.org; ibis-users@eda.org Subject: [IBIS-Users] V-t tables generation Hi all, When I generate the V-t tables for an output IBIS model I have to apply a transition in its input. If the datasheet specify an output rise/fall time range between, for example, 0.1ns min and 1.0 ns max, What is the rise/fall time I have to apply to the input transition? How do the IBIS simulators implement the rising/falling waveforms when the IBIS model was generated with a rise/fall time smaller than the the rise/fall time used to switch the buffer? Regards, Ramiro |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 29 Mar 2005 22:16:56 +0200 From: Koller Katja Subject: [IBIS-Users] AW: [IBIS] Comments on BIRD97 This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. - ------_=_NextPart_001_01C5349C.41329F0A Content-Type: text/plain Hello All! I hoped for reactions on my last email regarding BIRD97 and the u_th. Since I didn't see any responses I would like to clarify two aspects: A) u_th At the first glance, it seems that the u_th is a sensitive parameter, that vendors don't want to reveal. But if you take the formula for long channel: u_th = u_th0 + gamma*[(2*phi_F + U_SB)**0.5 - (2*phi_F)**0.5] were u_th0, gamma, phi_F und U_SB are unknown parameters which describe the process you can see that it is not possible to derive them from the known u_th. B) Comparison of real and calculated I_inst concrete example: vcc=3.3V, I_pd(3.3V) = 50mA, u_th=1.5V real I_inst(U_inst): U_inst/V |I_inst/mA (I_real) - --------------- 3.0 | 42 | 2.7 | 33 | 2.0 | 14 | 1.5 | 0 | 1.0 | 0 | with Pc calculated I_inst(U_inst) at different U_extract: U_inst/V | I_inst/mA (I_pc) U_extract/V |3.0 |2.7 |2.0 |1.5 |1.0 | Pc |0.92|0.81|0.46|0.00|0.00| - -------------------------------------- 3.0 | 42 | 37 | 21 | 0 | 0 | 2.7 | 38 | 33 | 19 | 0 | 0 | 2.0 | 28 | 25 | 14 | 0 | 0 | 1.5 | 21 | 19 | 11 | 0 | 0 | 1.0 | 14 | 13 | 7 | 0 | 0 | deviation of the calculated I_inst(U_inst) to the real current: U_inst/V | (1 - I_pc/I_real)*100 | U_extract/V | 3.0 | 2.7 | 2.0 | 1.5 | 1.0 | - ------------------------------------------- 3.0 | 0% | +12%| +50%|+100%|+100%| 2.7 |-15% | 0%| +42%|+100%|+100%| 2.0 |-100%| -6%| 0%|+100%|+100%| 1.5 | >> | >> | >> | 0%| 0%| 1.0 | >> | >> | >> | 0%| 0%| >> = infinite 1) All percent-values with a negativ sign (-) represent cases were the simulation will show fewer errors than in real. ==> hidden errors 2) All percent-values with a positiv sign (+) represent cases were the simulation will show more errors than in real. ==> useless design effort 3) The table shows, that you get huge current deviations if calculated with the Power_coeff. 4) The formula is not applicable in the region below the value of u_th (infinite or +100%). Katja - ------_=_NextPart_001_01C5349C.41329F0A Content-Type: text/html Content-Transfer-Encoding: quoted-printable AW: [IBIS] Comments on BIRD97

Hello All!

I hoped for reactions on my last = email regarding BIRD97 and the u_th. Since I didn't see any responses I = would like to clarify two aspects:

A) u_th
At the first glance, it seems = that the u_th is a sensitive parameter, that vendors don't want to = reveal.  But if you take the formula for long channel:

u_th =3D u_th0 + gamma*[(2*phi_F = + U_SB)**0.5 - (2*phi_F)**0.5]
were u_th0, gamma, phi_F und = U_SB are unknown parameters which describe the process you can see that = it is not possible to derive them from the known u_th.

B) Comparison of real and = calculated I_inst
concrete example: vcc=3D3.3V, = I_pd(3.3V) =3D 50mA, u_th=3D1.5V

real = I_inst(U_inst):
U_inst/V |I_inst/mA = (I_real)
---------------
3.0      | 42 |
2.7      | 33 |
2.0      | 14 |
1.5      |  0 |
1.0      |  0 |

with Pc calculated = I_inst(U_inst) at different U_extract:
U_inst/V    = |       I_inst/mA (I_pc)
U_extract/V |3.0 |2.7 |2.0 |1.5 = |1.0 |
Pc          = |0.92|0.81|0.46|0.00|0.00|
--------------------------------------
3.0         | 42 | 37 | 21 = |  0 |  0 |
2.7         | 38 | 33 | 19 = |  0 |  0 |
2.0         | 28 | 25 | 14 = |  0 |  0 |
1.5         | 21 | 19 | 11 = |  0 |  0 |
1.0         | 14 | 13 = |  7 |  0 |  0 |

deviation of the calculated = I_inst(U_inst) to the real current:
U_inst/V    = |    (1 - I_pc/I_real)*100    |
U_extract/V | 3.0 | 2.7 | 2.0 | = 1.5 | 1.0 |
-------------------------------------------
3.0         |  0% | = +12%| +50%|+100%|+100%|
2.7         |-15% = |   0%| +42%|+100%|+100%|
2.0         |-100%|  = - -6%|   0%|+100%|+100%|
1.5         |  = >> |  >> |  >> |   = 0%|   0%|
1.0         |  = >> |  >> |  >> |   = 0%|   0%|  >> =3D infinite

1) All percent-values with a = negativ sign (-) represent cases were the simulation will show fewer = errors than in real. =3D=3D> hidden errors

2) All percent-values with a = positiv sign (+) represent cases were the simulation will show more = errors than in real. =3D=3D> useless design effort

3) The table shows, that you get = huge current deviations if calculated with the Power_coeff.
4) The formula is not = applicable in the region below the value of u_th (infinite or = +100%).

Katja


- ------_=_NextPart_001_01C5349C.41329F0A-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 29 Mar 2005 17:30:09 -0800 From: Syed Huq Subject: [IBIS-Users] BIRD95.3: Power Integrity Analysis using IBIS - --=-++QbEr+TuKWQeqhY5vng Content-Type: text/plain Content-Transfer-Encoding: 7bit Attached is BIRD95.3 with changes based on comments including those captured at the March 11, 2005 IBIS Meeting. The changes and justifications are discussed in the ANALYSIS PATH/DATA section. They include (1) changing the subparameters in BIRD95.2 to keywords for the effective impedance per buffer, (2) not supporting *_ECL models at this time, and (3) adding detail to the text based on some of the questions raised. BIRD95.3 will be discussed at the April 1st, 2005 IBIS Open Forum teleconference. Syed Huq Cisco Systems, Inc Acting Chair, EIA IBIS Open Forum - --=-++QbEr+TuKWQeqhY5vng Content-Disposition: attachment; filename=BIRD95.3.txt Content-Type: text/plain; name=BIRD95.3.txt; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit ****************************************************************************** ****************************************************************************** BIRD ID#: 95.3 ISSUE TITLE: Power Integrity Analysis using IBIS REQUESTER: Syed Huq, Vinu Arumugham and Zhiping Yang, Cisco Systems, Inc.; Bob Ross, Teraspeed Consulting Group DATE SUBMITTED: December 13, 2004 DATE REVISED: January 28, 2005, March 8, 2005, March 29, 2005 DATE ACCEPTED BY IBIS OPEN FORUM: PENDING ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: Power Integrity Analysis which includes Current switching profile of the Core as well as Simultaneous Switching Noise (SSN) of the Input/Output (I/O) stages of a buffer needs to be analyzed through IBIS. This BIRD proposes a modeling scheme to solve this. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: Power Integrity Analysis from a modeling perspective has been split into multiple tasks. Current into the power and ground rails are needed to give a more accurate analysis for ground and power bounce associated with simultaneous switching noise. Solving the Simultaneous Switching Noise (SSN) will be achieved through the use of I-T tables and [Z Equiv] keywords as part of this proposal. Five keywords and some other modifications are introduced: *** The [R Equiv], [L Equiv], [C Equiv] and [G Equiv] keywords are entered above the [Ramp] keyword in the document: |============================================================================== | Keywords: [R Equiv], [L Equiv], [C Equiv], [G Equiv] | Required: No | Description: Describes the impedance between the [Pullup Reference] and | [Pulldown Reference] in terms of a resistance, inductance, | capacitance in series and a parallel conductance. | Usage Rules: These keywords are positioned with the other keywords under the | [Model] keyword. | | For each of these keywords, the three columns hold the | typical, minimum, and maximum values. The three | entries must be placed on a single line and must be separated | by at least one white space. All three columns are required | under these subparameters. However, data is only required in | the typical column. If minimum and/or maximum values are not | available, the reserved word "NA" must be used, indicating that | the typical column entry will be used. | | These keywords are optional, but if any are missing, it takes | on a default value of zero. Thus [C Equiv], if missing, opens | the series path, and if [R Equiv] is missing, the resistance is | assumed zero. If [G Equiv] is missing, it is not included in | the model | | The keyword connections are defined with respect to reference | diagram in parallel to an I/O pin on the die on a per buffer | basis. The Power Pin is | the [Pullup Reference] and the Ground Pin is the [Pulldown | [Reference]. | | | | __________________________________ Power Pin | | [Pullup Reference] | ___________________|_______________________ | | | | | | ___________|______________ | | | ____|____ | | | | | | | | | | | | |[R Equiv]| | | Die | | | |_________| | | | | | ____|____ ____|____ ____|____ | | | | | | | | I/O | | | | |[L Equiv]| |[G Equiv]| | die |-------------- | | |_________| |_________| |_________| | | | ____|____ | | | | | | | | | | | | |[C Equiv]| | | | | | |_________| | | | | | |___________|______________| | | | | | | |___________________|_______________________| | | | |________________________________ Ground Pin | [Pulldown Reference] | | | These Keywords might not be effective for *_ECL technologies | because the [Pullup Reference] and [Pulldown Reference] are | connected to the same rail (which also can be Ground), and the | the most negative rail might not be specified. | | These keywords might not have any effect for the Model_type | settings of Input, Input_diff, Terminator, Series, and | Series_switch. These settings do not have a driver mode of | operation. | | Other Notes: The [R Equiv], [L Equiv], [C Equiv] and [G Equiv] keywords may | be used with, but do not require the [Composite Current] keyword | described later. Also, an example of a more detailed internal | network for these equivalent impedances is presented under the | [Composite Current] keyword. |------------------------------------------------------------------------------ | variable Typ Min Max | [R Equiv] 2.0m NA NA [L Equiv] 0.2n .3n .1n | Follow Process, Temperature [C Equiv] 2.0p 1.0p 1.3p | Voltage conditions with no [G Equiv] 2.0u NA NA | Ordering of values assumed | |============================================================================== *** The following keyword is positioned under the [Rising Waveform]/[Falling Waveform] keyword: Note, BIRD95.3 changes include substantial rewrite because of the conversion of the R_zvddq, L_zvddq, C_zvddq and G_zvddq subparameters into keywords. The BIRD95.2 text is retained at the end of BIRD95.3 for comparison since the rewritten text below does show the changes. |============================================================================== | Keywords: [Composite Current] | Required: No | Description: Describes the shape of the rising and falling edge | current waveforms from the power supply measured through | the power pin terminal. | Usage Rules: The [Composite Current] keyword is positioned under the | [Rising Waveform] (for rising waveform currents) and | [Falling Waveform] (for falling waveform currents. The keywords | are followed by | a table of current versus time rows (I-T) that | describe the shape of a current waveform. These I-T tables | inherit the fixture test load of the [Rising Waveform] | or [Falling Waveform] R/L/C/V_fixture and R/L/C_dut | subparameters. | | The [Composite Current] keyword is optional. It can be omitted, | or it can be positioned under a few, but not all of the rising | and falling waveform tables. | | The table itself | consists of one column of time points, then | three columns of current points in the standard typ, min, and | max format. The four entries must be placed on a single line and | must be separated by at least one white space. All four | columns are required. However, data is only required in the | typical column. If minimum or maximum data is not available, | use the reserved word "NA". The first value in the time column | need not be '0'. Time values must increase as one parses down | the table. The waveform table can contain a maximum of 1000 | data points. | | The I-T table data must be time-correlated with the V-T data | above. That is, the currents documented in the I-T table | correspond to the voltages in the V-T table at the identical | time points and for the given *_fixture load. | | The following diagram illustrates a typical configurating which | a [Rising Waveform] or [Falling Waveform is extracted. The | DUT die is modified to include the Power Pin and Ground Pin. | | | Power Pin | {Composite Current] | | | | | | PACKAGE | TEST FIXTURE | ____|____ | | | DUT | L_dut R_dut | L_fixture R_fixture | | die |---@@@@@--/\/\/\--o-----|--@@@@---o---/\/\/\--- V_fixture | |_________| | | | | | | | | | | | | | | | C_dut === | === C_fixture | | | | | | |_______________________|_____|_________|___ | Ground Pin | GND | | | The [Composite Current] direction is shown with respect to the | Power Pin. The new keywords are shown added to the DUT die. | These subparameters do not effect the [Rising Waveform] and | [Falling Waveform] table extractions, but give added equivalent | circuit detail for more accurate power pin current calculations. | | The [Composite Current] Keyword might not be effective for *_ECL | technologies | because the [Pullup Reference] and [Pulldown Reference] are | connected to the same rail (which also can be Ground}, and the | the most negative rail might not be specified. | | Other Notes: The internal networks for the DUT die 'Black Box' are shown | below to illustrate the effects that the equivalent circuit | are intended to describe. The Power Pin terminal is ahown as | VDDQ, and the Ground Pin terminal is shown as GND. | | | Black Box [Composite Current] | VDDQ | | o | __________________________________________________________________________| |__ || | | | || | | | || v | | || -------- -------- | | || | | | | | | || ____________________________________________|L_VDDQ|_|R_VDDQ|__| | || | | | | | | | | | | || | | | | | -------- -------- | || ----- | | | | | || | E | | / | | | || | S | ---------------- \ P_| --- PowerClamp | || | R | | Pre-Driver | / || / \ | || ----- | Circuit | \ ||_ --- | || | | powered by | | | | | || | | VDDQ | | | | | I_sig | || ----- ---------------- | | | | -------> | || | E | | o-----o--|----o---------------------------o || | S | | | | | | | Sig || | | L | | | | / | | | | || I_byp| ----- I_pre| |I_term| \ N_| v --- GNDClamp | || | | | | | / || I_cb / \ | || v | v | v \ ||_ --- | || ----- | | | | ------ ------- | || ----- C_p+b | | | | | | | | || |___________________|_________|_____|_______|___|L_GND|_|R_GND|__ | || | | | | | | || ------ ------- | | || | | || | | ||____________________________________________________________________________|__| | | | o | GND | | | Other elements in a more detailed typical (per buffer) model are: | | I_byp - Bypass current | I_pre - Pre-Driver current | I_cb - Crow-bar current | I_term - Termination current (optional) | L_VDDQ - On-die inductance of I/O Power | R_VDDQ - On-die resistance of I/O Power | L_GND - On-die inductance of Ground | R_GND - On-die resistance of Ground | C_p+b - Bypass + Parasitic Capacitance | ESR - Equivalent Series Resistance for on-die Decap | ESL - Equivalent Series Inductance for on-die Decap | | | The keywords [R Equiv], [L Equiv], [C Equiv] and [G Equiv] presented | earlier document an equivalent impedance of the internal Power pin | to Ground pin for each buffer as extracted at the terminals. The | [C Series], [Lc Series], [Rc Series] and [R Series] keywords along | with [Series Pin Mapping] could also be used to provide an equivalent | total impedance (versus a per buffer impedance) across the rails. In | the future, the ICM format might provide more accurate detail. | | The [C Equiv] value expressed on a per buffer basis captures the | effective bypass and parasitic for the internal structure of each | buffer. The extracted equivalent circuit would also capture the | C_comp* contribution attached to the rails. If the values are of | the same magnitude, then the C_comp* rail to rail contribution | should be subtracted from the the [C Equiv] values as a first order | adjustment. | | The Power Pin terminal in most cases is the [Pullup Reference], | or the default [Voltage Range] value. The [Pulldown Reference] is | usually the GND connection. | | If [POWER Clamp Reference] or [GND Clamp Reference] are different | than the [Pullup Reference] or [Pulldown Reference] voltages, | the model may not account for all of the currents. However, the | simulation of current transients should still be reasonable. | | The [Composite Current] can still be defined for Model_types without } the [Pullup] keywords (such as Open_drain) because the [Pullup | Reference] or [Voltage Range] are still required. Pre-driver and | other internal paths still exist. | | In most cases six [Composite Current] tables are recommended | for accurate modeling. The first four tables correspond to the | recommended fixture conditions for [Rising Waveform] and [Falling | Waveform] tables (normally 50 ohm loads to Vdd and GND). Two | additional waveforms for no load conditions (such as with an R_fixure | of 1.0 Megaohm) are useful. However, some EDA tools may use only | the first four waveforms. So these additional open load waveform | I-T tables should be in [Rising Waveform] and [Falling Waveform] | tables positioned after the other V-T tables to maintain the best | output response accuracy. These extra two tables do not apply | for any of the Open-drain and Open-source technologies. | | When the [Model] is configured differentially with the [Diff Pin] | keyword, the individual I-T currents for each [Model] is used as | an approximation. This summation may not be as accurate as the | the actual measured currents under actual operation. | | The [Composite Current] table can be derived from currents measured | at the GND node that have been transformed by combining with the | current at the output pin. | | The [Pin Mapping] keyword is used to document how buffers with | common voltage rails are connected. The effective impedances for | each buffer between the [Pullup Reference] and [Pulldown Reference] | are then combined to form the total effective impedance between | the voltage rails. | | The [Composite Current] keyword is not designed to accurately | document the effects of controlled switching buffers such as | those defined with [Submodel] or [Driver Schedule] keywords. | The additional currents for the specific controlled switching | fixture loads would be documented by the [Composite Curent] | values, but these additions might not describe the currents | for arbitrary load conditions because of control interactions. |------------------------------------------------------------------------------ | [Rising Waveform] R_fixture = 50.0 V_fixture = 0.0 | ... | ... | Rising Waveform table | ... [Composite Current] | | Time I(typ) I(min) I(max) 0 4.243E-05 NA NA 4.00E-11 4.244E-05 NA NA 8.00E-11 4.242E-05 NA NA 1.20E-10 4.265E-05 NA NA 1.60E-10 3.610E-05 NA NA 2.00E-10 3.903E-03 NA NA .. .. .. 3.80E-09 2.012E-02 NA NA 3.84E-09 2.012E-02 NA NA 3.88E-09 2.012E-02 NA NA 3.92E-09 2.012E-02 NA NA 3.96E-09 2.012E-02 NA NA 4.00E-09 2.012E-02 NA NA | [Falling Waveform] R_fixture = 50.0 V_fixture = 1.8 | ... | ... | Falling Waveform table | ... [Composite Current] | | Time I(typ) I(min) I(max) 0 4.302E-05 NA NA 4.00E-11 4.299E-05 NA NA 8.00E-11 4.304E-05 NA NA 1.20E-10 4.287E-05 NA NA 1.60E-10 4.782E-05 NA NA 2.00E-10 1.459E-04 NA NA .. .. .. 3.80E-09 4.933E-05 NA NA 3.84E-09 5.211E-05 NA NA 3.88E-09 5.490E-05 NA NA 3.92E-09 5.441E-05 NA NA 3.96E-09 4.842E-05 NA NA 4.00E-09 4.244E-05 NA NA | | ... etc. | |============================================================================== *** The following entries are made to the Tree diagram in Section 3a under the [Model] keywords as noted by the |*** lines: | | |-- [Lc Series] | | |-- [Rc Series] | | |-- [Series Current] | | |-- [Series MOSFET] Vds |*** Add these keywords | | |-- [R Equiv] | | |-- [L Equiv] | | |-- [C Equiv] | | |-- [G Equiv] |*** End of addition | | |-- [Ramp] dV/dt_r, dV/dt_f, | | |-- [Rising Waveform] R_fixture, V_fixture, | | | V_fixture_min, V_fixture_max, | | | C_fixture, L_fixture, R_dut, L_dut, | | | C_dut |*** Add this keywords | | | ----------------- | | | | | | | |-- [Composite Current] | | | |*** End of addition | | |-- [Falling Waveform] R_fixture, V_fixture, | | | V_fixture_min, V_fixture_max, | | | C_fixture, L_fixture, R_dut, L_dut, | | | C_dut |*** Add this keywords | | | ----------------- | | | | | | | |-- [Composite Current] | | | |*** End of addition | | |-- [Test Data] Test_data_type *, Driver_model, | | | Driver_model_inv, Test_load | | | ----------- *** The following change is made in Section 2, item 8) to add mho as a base unit as denoted in the |*** line: | 8) Valid scaling factors are: | T = tera k = kilo n = nano | G = giga m = milli p = pico | M = mega u = micro f = femto | When no scaling factors are specified, the appropriate base units are |*** assumed. (These are volts, amperes, ohms, mhos, farads, henries, and | seconds.) The parser looks at only one alphabetic character after a | numerical entry, therefore it is enough to use only the prefixes to | scale the parameters. However, for clarity, it is allowed to use full | abbreviations for the units, (e.g., pF, nH, mA, mOhm). In addition, | scientific notation IS allowed (e.g., 1.2345e-12). ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Power Integrity Analysis has become a significat part of Signal Integrity Simulations and Analysis. Core voltages are going down with process enhancement and, I/O speeds are increasing, it is critical that high-speed applications solve Power Integrity issues on the die, package and PCBs combined. System failures can be traced to poor Power Integrity Designs. During the DesignCon2004 Power Integrity Panel, these issues were discussed. It was suggested to explore a solution through the IBIS commitee and hence this BIRD proposal. Several discussions were conducted(3/12/04,5/14/04,6/8/04,7/16/04,8/24/04) with the IBIS Futures Meetings. BIRD95.3: Based on comments and intent of BIRD95.2, the following changes were made: Subparameters for R_zvddq, L_zvddq, C_zvddq, and G_zvddq were changed to four keywords under [Model]: [R Equiv], [L Equiv], [C Equiv] and [G Equiv]. for the following reasons: (1) avoid repeating the same values for each occurance of [Composite Current] because there was never the intention to support different values, (2) to allow for typ-min-max values under the extraction conditions. The name change in keywords was made to conform better to the illustrative diagram components (ESR, ESL, etc) and to emphasize that these are overall equivalent values. A consequence of this syntactical change is that these keywords can be used whether or not [Composite Current] is defined. This is good because gate modulation control sometimes is sufficient in some devices. Several syntactical choices exist: (1) uses the [Series Pin Mapping] keyword and the already defined Series models, (2) write as subparameters under model similar to C_comp, (3) capture the group under new keyword (such as [Zvddq]) under [Model], but use a subparameter format under this like [Package] and R_pin, etc. (4) define as independent keywords such as [R Equiv], etc. like the [Rgnd], [Rpower] terimnator elements, (5) do nothing and rely on some future connection to hook up ICM with IBIS. Choice (1) has syntactical might not be available on a per buffer basis. Also, this requires a complete [Series Pin Mapping] pinout of all such connections along with the [Pin Mapping] keyword. Using the (2) subparameter method directly under [Model] is a syntactical departure from what we have traditionally done. Even some [Model Spec] subparameters are grouped under a keyword for grouping purpose. (Putting these additional impedances under [Model Spec] was also rejected because the describe electrical content, not specification information or specification test setups.) Positioning the subparameters under a keyword (such as [Zvvdq]) for grouping purposes is the preferred alternative and was almost used for BIRD95.3. While it has grouping advantages for content location purposes, and while it may follow the syntax similar to [Package] and its R_pin, L_pin, and C_pin subparameters, all electrical content under the [Model] keyword are described by keywords such as those for I-V tables, and terminators (e.g., [Rac], [Cac], [Rpower], [Rgnd]) or [TTpower], [TTgnd]. The choice for using the keyword format follows from these cases. The C_comp* subparameters remain the only exception. The other detail concerns more resolution on ECL/PECL support. The problem is that the negative reference supply is not required. The options are to simply list this as an unsupported exception at this time, or to add more requirements and conditions. The choice is changed to specify that it is not supported and leave its support to other BIRDs if there is a compelling industrial need. Some other changes per the discussion at the March 11, 2005 meeting: 1) _typ, _min, _max for the sub-params - Itzik Peleg Added with the four new keywords. 2) C_comp for Power and GND and it's relation to this BIRD - Arpad Muranyi Added by stating that C_comp* is assumed separate from [C Equiv]. 3) C_p+b, Is this Total or per I/O - John Angulo Stated per I/O 4) On-die cap for power rail, is this included or not - Michael Mirmak Assumed separate, if it exists and modeled by [C Series] 5) Make a statement that says, this is for a single buffer and not a complete component - John Angulo Assumed per single buffer by statements and positioning under [Model] 6) Z_VDDDQ subparams and placement under Model_type - Bob Ross/John Angulo Added statement that the new keywords might not be used for Input, Terminator, Series, Series Switch, Input_diff model_type. The positioning of [Composite Current] under the [Rising Waveform] and [Falling Waveform] keywords already constrain that it is used only where the waveform tables are used. The tree diagram and addition of mho as a base unit is added for completeness. Some Editorial changes and corrections are made. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: Other Power Integrity Related BIRDs are planned, but there may be future issues regarding exactly what is adopted to be discussed separately. Other than the already proposed BIRD97, BIRD95.3 has sufficient content for a complete solution at a lower level without these planned BIRDs: Linkage to a Core model will be achieved by BIRDXX (TBD). Linkage to an ICM model will be achieved by BIRDYY (TBD). Linkage to a Gate Modulation model will be achieved by BIRD97. This proposal is based on various past work done by many IBIS contributors and they are listed in no particular order. Links to ICEM are also listed: DesignCon2004 PDN Simulation panel proceedings material and slides: http://home.att.net/~istvan.novak/papers.html BIRD42.3: Modeling Current Waveforms C. Kumar, Bob Ross IBIS and ICEM interaction: B. Ross, Microelectronic Journal November 16, 2003 ICEM: - ---- EMC for Component, Integrated circuits Electrical Model(ICEM) 93/XX/CDC, Project number 62014-3 Cookbook for Integrated Circuit model ICEM, Project number 62014-3 IBIS Summits: - ------------- EMC model for prediction of parasitic emission, E. Sicard, March 2001 Electromagnetic Compatibility simulation of Printed Circuit Board, M. Christian, March 2001 ICEM - Proposal IEC62014-3, J.C.Perrin, March 2001 Advances of the ICEM model for Emission of Integrated Circuit, S. Calvet, January 2001 Adding On-Chip Capacitance in IBIS Format for SSO Simulation, R. Chen, January 2004 Simultaneous Switching Noise(SSN)Modeling, B. Unger January 2000 Crossbar-current out of CMOS-IBIS-Models, K. Koller & G .Bannert, March 2002 IC-Emit Comparing Simulated/Measured IC Emission Spectrum, E. Sicard & A. Soubeyran Februayr 2004 REVISION HISTORY CHANGES: Replace following BIRD95.1 lines: |*Power Integrity Analysis from a modeling perspective has been split into |*two tasks. |*1)Solving the Simultaneous Switching Noise (SSN) on the I/O level using current |* and future IBIS syntax. This will be achieved through IvsT tables. |*2)Solving the Core Current Switching profile using the ICEM (Integrated circuits |* Electrical Model specification, Project number 62014-3). This will be achieved |* by a call statement within IBIS calling an ICEM model. Using v4.1 IBIS syntax. replace: Current into the power and ground rails are needed to give a more accurate analysis for ground and power bounce associated with simultaneous switching noise. replace: | Keywords: [Series Composite Current] with: replace: | Description: Describes the shape of the rising and falling edge | current waveforms from the power supply measured through | R_VDD(see diagram). This includes Pre-driver, Crow-bar current, | on-die I_bypass and I_term(see diagram). replace: | Usage Rules: The [Series Composite Current] keyword is positioned under the replace: | | | -------- -------- (**) | | | | |<--- | _____________________________________________|L_VDDQ|_|R_VDDQ|__VDDQ | | | | | | | | | | | | | | | | -------- -------- | ----- | | | | | | E | | / | | | | S | ---------------- \ P_| --- PowerClamp | | R | | Pre-Driver | / || / \ | ----- | Circuit | \ ||__ --- | | | powered by | | | | | | | VDDQ | | | | | I_sig | ----- ---------------- | | | | -------> | | E | | o-----o--|----o---------- | | S | | | | | | | | | L | | | | / | | | |I_bypass| ----- I_pre| |I_term| \ N_| v --- GNDClamp | | | | | | / || I_cb / \ | v | v | v \ ||_ --- | ----- | | | | ------ ------- | ----- C_p+b | | | | | | | | | |___________________|_________|_____|_______|___|L_GND|_|R_GND|__GND | | | | | | ------ ------- | | I_bypass - Bypass current | I_pre - Pre-Driver current | I_cb - Crow-bar current | I_term - Termination current (optional) | L_VDDQ - On-die inductance of I/O Power | R_VDDQ - On-die resistance of I/O Power | L_GND - On-die inductance of Ground | R_GND - On-die resistance of Ground | C_p+b - Bypass + Parasitic Capacitance | ESR - Equivalent Series Resistance for on-die Decap | ESL - Equivalent Series Inductance for on-die Decap | | (**) - Current measure point The original BIRD95.2 [Composite Current] writeup is captured here for historical reference. |============================================================================== | Keywords: [Composite Current] | Required: No | Description: Describes the shape of the rising and falling edge | current waveforms from the power supply measured through | the power pin terminal illustrated more fully in the Usage | Rules. | Sub-params: R_zvddq, R L_zvddq, C_zvddq_typ, G_zvddq | Usage Rules: The [Composite Current] keyword is positioned under the | [Rising Waveform] (for rising waveform currents) and | [Falling Waveform] (for falling waveform currents. The keywords | are followed by optional on-die parasitic die subparameters and | then a table of current versus time rows (I-T) that | describe the shape of a current waveform. These I-T tables | inherit the fixture test load of the [Rising Waveform] | or [Falling Waveform] R/L/C/V_fixture and R/L/C_dut | subparameters. | | The [Composite Current] keyword is optional. It can be omitted, | or it can be positioned under a few, but not all of the rising | and falling waveform tables. | | The listed subparemeters, R_zvddq, L_zvddq, C_zvddq, and G_zvddq, | describe the impedance path between the power pin terminal and | ground (see Other Notes below). The first three subparameters | describe a series path of resistance, inductance and capacitance. | The forth subparameter describe a separate path in parallel to | the series path and also between the power pin terminal and | ground. | | These subparameters are optional, but if any are missing, they | take on a default value of zero. Thus C_zvddq, if missing, opens | the series path, and if R_zvddq is missing, the resistance is | assumed zero. If G_zvddq is missing, it is not included in the | model | | The I-T table follows these subparameters. The table itself | consists of one column of time points, then | three columns of current points in the standard typ, min, and | max format. The four entries must be placed on a single line and | must be separated by at least one white space. All four | columns are required. However, data is only required in the | typical column. If minimum or maximum data is not available, | use the reserved word "NA". The first value in the time column | need not be '0'. Time values must increase as one parses down | the table. The waveform table can contain a maximum of 1000 | data points. | | The following diagramss illustrate a typical configurating which | a [Rising Waveform] or [Falling Waveform is extracted. The | DUT die is modified to include the Power Pin and Ground Pin. | | | Power Pin | | | | | | | PACKAGE | TEST FIXTURE | ____|____ | | | DUT | L_dut R_dut | L_fixture R_fixture | | die |---@@@@@--/\/\/\--o-----|--@@@@---o---/\/\/\--- V_fixture | |_________| | | | | | | | | | | | | | | | C_dut === | === C_fixture | | | | | | |_______________________|_____|_________|___ | Ground Pin | GND | | | The [Composite Current] direction is shown with respect to the | Power Pin and the new subparameters are added to the DUT die. | These subparameters do not effect the [Rising Waveform and | [Falling Waveform] table extractions, but give added equivalant | circuit detail for more accurate power pin current calculations. | | ! [Composite Current] | <------ | __________________________________ Rower Pin | | | ___________________|_______________________ | | | | | | ___________|______________ | | | ____|____ | | | | | | | | | DUT | | | | R_zvddq | | | die | | | |_________| | | | | | ____|____ ____|____ ____|____ | | | | | | | | I/O | | | | | L_zvddq | | G_zvddq | | die |-------------- To L_dut | | |_________| |_________| |_________| | | | ____|____ | | | | | | | | | | | | | C_zvddq | | | | | | |_________| | | | | | |___________|______________| | | | | | | |___________________|_______________________| | | | |________________________________ Ground Pin | | | | Other Notes: The internal networks for the DUT die 'Black Box' are shown | below to illustrate the effects that the equivalent circuit | are intended to describe. The Power Pin terminal is ahown as | VDDQ, and the Ground Pin terminal is shown as GND. | | | VDDQ | Black Box (**) o | ___________________________________________________________________________||__ || || | || || | || v| | || -------- -------- | | || | | | | | | || ____________________________________________|L_VDDQ|_|R_VDDQ|__| | || | | | | | | | | | | || | | | | | -------- -------- | || ----- | | | | | || | E | | / | | | || | S | ---------------- \ P_| --- PowerClamp | || | R | | Pre-Driver | / || / \ | || ----- | Circuit | \ ||_ --- | || | | powered by | | | | | || | | VDDQ | | | | | I_sig | || ----- ---------------- | | | | -------> | || | E | | o-----o--|----o---------------------------o || | S | | | | | | | Sig || | | L | | | | / | | | | || I_byp| ----- I_pre| |I_term| \ N_| v --- GNDClamp | || | | | | | / || I_cb / \ | || v | v | v \ ||_ --- | || ----- | | | | ------ ------- | || ----- C_p+b | | | | | | | | || |___________________|_________|_____|_______|___|L_GND|_|R_GND|__ | || | | | | | | || ------ ------- | | || | | || | | ||____________________________________________________________________________|__| | | | o | GND | | (**) I-T - current through VDDQ terminal. | | Other elements typically in a more detailed model are | | I_byp - Bypass current | I_pre - Pre-Driver current | I_cb - Crow-bar current | I_term - Termination current (optional) | L_VDDQ - On-die inductance of I/O Power | R_VDDQ - On-die resistance of I/O Power | L_GND - On-die inductance of Ground | R_GND - On-die resistance of Ground | C_p+b - Bypass + Parasitic Capacitance | ESR - Equivalent Series Resistance for on-die Decap | ESL - Equivalent Series Inductance for on-die Decap | | | The subparameters R_zvddq, L_zvddq, C_zvddq and G_zvddq represent | and effective impedance of the internal Power pin to Ground pin | elements, as extracted from the terminals. In the future, the ICM | format might proivde more accurate detail, if needed. | NOTE: The Power Pin terminal in most cases is the [Pullup Reference], | or the default [Voltage Range] value. This [Pullup Reference] can | also be GND, as in some *_ECL technologies, and the Ground Pin is the | more negative reference. In such cases, the [GND Clamp Reference] | value should be defined. | | If [POWER Clamp Reference] or [GND Clamp Reference] are different | than the [Pullup Reference] or [Pulldown Reference] voltages, | the model may not account for all of the currents. However, the | simulatiion should still closely approximate the current transients. | | The [Composite Current] can still be defined for Model_types with } out the [Pullup] keywords (such as Open_drain) because the [Pullup | Reference] or [Voltage Range] are still required. Pre-driver and | other internal paths still exist. | | NOTE: In most cases six [Composite Current] tables are recommended | for accurate modeling. The first four tables correspond to the | recommended fixture conditions for [Rising Waveform] and [Falling | Waveform] tables (normally 50 ohm loads to Vdd and GND). Two | additional waveforms for no load conditions (such as with an R_fixure | of 1.0 megaohm are useful. However, some EDA tools may use only | the first four waveforms. So these additional open load waveform | I-T tables should be in [Rising Waveform] and [Falling Waveform] | tables positioned after the other V-T tables to maintain the best | output response accuracy. These extra two tables do not apply | for any of the Open-drain and Open-source technologies or for | ECL technologies. | | When the [Model] is configured differentially with the [Diff Pin] | keyword, the individual I-T currents for each [Model] is used as | an approximation. This summation may not be as accurate as the | the actual measured currents under actual operation. | | The [Composite Current] table can be derived from currents measured | at the GND node that have been transformed by combining with the | current at the output pin. | | The [Pin Mapping] keyword is used to docuemnt the voltage rails | of several buffers are combined. This combination includes the | effective impedances describe for each buffer | | The [Composite Current] keyword is not designed to accurately | document the effects of controlled switching buffers such as | those defined with [Submodel] or [Driver Schedule] keywords. |------------------------------------------------------------------------------ | [Rising Waveform] R_fixture = 50.0 V_fixture = 0.0 | ... | ... | Rising Waveform table | ... [Composite Current] R_zvddq = 2.0m L_zvddq = 0.2n C_zvddq = 2.0p G_zvddq = 2.0u | | Time I(typ) I(min) I(max) 0 4.243E-05 NA NA 4.00E-11 4.244E-05 NA NA 8.00E-11 4.242E-05 NA NA 1.20E-10 4.265E-05 NA NA 1.60E-10 3.610E-05 NA NA 2.00E-10 3.903E-03 NA NA .. .. .. 3.80E-09 2.012E-02 NA NA 3.84E-09 2.012E-02 NA NA 3.88E-09 2.012E-02 NA NA 3.92E-09 2.012E-02 NA NA 3.96E-09 2.012E-02 NA NA 4.00E-09 2.012E-02 NA NA | [Falling Waveform] R_fixture = 50.0 V_fixture = 1.8 | ... | ... | Falling Waveform table | ... [Composite Current] R_zvddq = 2.0m L_zvddq= 0.2n C_zvddq = 2.0p G_zvddq = 2.0u | | Time I(typ) I(min) I(max) 0 4.302E-05 NA NA 4.00E-11 4.299E-05 NA NA 8.00E-11 4.304E-05 NA NA 1.20E-10 4.287E-05 NA NA 1.60E-10 4.782E-05 NA NA 2.00E-10 1.459E-04 NA NA .. .. .. 3.80E-09 4.933E-05 NA NA 3.84E-09 5.211E-05 NA NA 3.88E-09 5.490E-05 NA NA 3.92E-09 5.441E-05 NA NA 3.96E-09 4.842E-05 NA NA 4.00E-09 4.244E-05 NA NA | | ... etc. | |------------------------------------------------------------------------------ - --=-++QbEr+TuKWQeqhY5vng-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 30 Mar 2005 15:41:54 +0530 From: Subject: [IBIS-Users] How to include Differential and Non-differential Models in the same file Hi, I have an input Buffer and I need to devolope IBIS model for this.It is having 2 modes in MODE_1 it acts as a analog differential input Buffer (A and AZ are differential inputs and Y as output). MODE_2 it acts as non-differential input Buffer (A is the only input since AZ must be floating and Y is the output). If I generate models for these how do I include these in a single component? Why because MODE_1 having Pin structure A and AZ along with [Diffpin] and MODE_2 having Pin structure only A and not [DiffPin]. And [DiffPin] key word will be having influence on Non-differential Model i.e MODE_2. Thanks Regards kiran Confidentiality Notice The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain confidential or privileged information. If you are not the intended recipient, please notify the sender at Wipro or Mailadmin@wipro.com immediately and destroy all copies of this message and any attachments. |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 1 Apr 2005 16:50:13 +0200 From: Subject: [IBIS-Users] ODT topics Hi, recently I have took responsibility for IBIS models in Memory Products of Infineon and soon I have realised that it is very tricky. There were generated some ODT IBIS models (for DDR2 with thevenin impedance, not possible to separate Pull-up and Pull -down impedance) with s2ibis2 as Inputs with Power and Ground Clamps curves. Everything was OK until first customer were complaining that during his simulations our ODT behave other than comparing to Samsung and Micron ODT's. After some 5-6 hours of frustrating analysis we have discovered that the "only" problem is that neither the clamp curves are cut where they reach zero nor they are extrapolated horizontally to 2*Vcc. As soon as we done that (cutting at zero current and extrapolating to 2*Vcc) everything was OK. By the way, Mr. Muranyi has nicely explained this procedure in his paper "Modeling on-die terminations in IBIS (without double counting)". The problem that we have experienced is obviously because of double counting of some data. My question would be: what are simulators (e.g. HSPICE) really doing with IBIS models (specially with Input models), how are data treated, what is the algorithm of calculation (if designer was aware of this algorithm double counting could be perhaps avoided)? Is it possible to get this things written in electronic form or anywhere on Internet? By the way, on IBIS summit Meeting in Munich in March (DATE 2005) somebody mentioned something about some Cookbook for ODT's. Is there any estimation when will this Cookbook appear? Many thanks in advance for any help or advice, Radovan Vuletic Infineon Technologies AG MP PD PDE Room 03.911 Balanstraße 73 D-81541 München Phone: +49 (0)89 234 20108 Fax: +49 (0)89 234 27705 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@infineon.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 01 Apr 2005 11:36:50 -0600 From: "RODRIGUEZ_LECONA_RAMIRO" Subject: [IBIS-Users] xtal inputs Hi all, Is there any special requirement for xtal inputs from IBIS point of view? Or simply I have to specify the xtal inputs like a differential pins and include the clamps curves? Thanks. Ramiro |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 1 Apr 2005 11:48:03 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] ODT topics Radovan, To answer your question: "My question would be: what are simulators (e.g. HSPICE) really doing with IBIS models (specially with Input models), how are data treated, what is the algorithm of calculation (if designer was aware of this algorithm double counting could be perhaps avoided)? Is it possible to get this things written in electronic form or anywhere on Internet?" The clamp I-V tables are always present in the simulation, and the pullup and pulldown I-V tables are switched on/off as the buffer is driving high/low. The end result is that the currents of the pullup or pulldown I-V tables are added together with the clamps. "By the way, on IBIS summit Meeting in Munich in March (DATE 2005) somebody mentioned something about some Cookbook for ODT's. Is there any estimation when will this Cookbook appear?" I believe the plan is that the Cookbook will be released May/June time frame this summer. Arpad - ----------------------------------------------------------------- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 1 Apr 2005 22:51:06 -0500 From: "Andrew Ingraham" Subject: Re: [IBIS-Users] ODT topics > "My question would be: what are simulators (e.g. HSPICE) really doing with > IBIS models ... > The clamp I-V tables are always present in the simulation, and > the pullup and pulldown I-V tables are switched on/off as the > buffer is driving high/low. The end result is that the currents > of the pullup or pulldown I-V tables are added together with > the clamps. Well actually, ... Sorry to nit-pick, but in HSPICE the clamps are not necessarily always there. The end-user who puts an IBIS model in his simulation needs to make sure to include ALL the optional element nodes. If he leaves the optional nodes out, HSPICE has this nasty feature (it is really intended as a feature, not a bug) that the clamp I-V tables are omitted. Once those nodes are included in the netlist, then Arpad's statement above is correct. Regards, Andy |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sat, 02 Apr 2005 15:59:05 +0530 From: Akhilesh CHANDRA Subject: [IBIS-Users] How we can model preemphasis and deemphasis Hello, In my one buffer preemphasis and deemphasis is present . Can any one model this in IBIS . if any one have any doc regarding this then please give me I am not able to understand how we model this. Regards Akhilesh |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sat, 2 Apr 2005 08:34:19 -0500 From: "Andrew Ingraham" Subject: Re: [IBIS-Users] ODT topics Hmmm, my mail doesn't seem to be reaching eda.org. Here is try # 3: > "My question would be: what are simulators (e.g. HSPICE) really doing with > IBIS models ... > The clamp I-V tables are always present in the simulation, and > the pullup and pulldown I-V tables are switched on/off as the > buffer is driving high/low. The end result is that the currents > of the pullup or pulldown I-V tables are added together with > the clamps. Well actually, ... Sorry to nit-pick, but in HSPICE the clamps are not necessarily always there. The end-user who puts an IBIS model in his simulation needs to make sure to include ALL the optional element nodes. If he leaves the optional nodes out, HSPICE has this nasty feature (it is really intended as a feature, not a bug) that the clamp I-V tables are omitted. Once those nodes are included in the netlist, then Arpad's statement above is correct. Regards, Andy |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 4 Apr 2005 10:54:55 +0530 From: "Vivek Kumar Sundriyal" Subject: [IBIS-Users] Latest IBIS Version Hi , I want to use the latest version of the spice-to-IBIS converter. On the website (http://www.eigroup.org/ibis/tools.htm ) I notice that the IBIS Golden parser supports IBIS Version 4.0, but the latest Spice-to-IBIS converter is s2ibis3 which supports v3.2. My questions are : Which is the latest version of IBIS ? Is it 3.2 or 4.0 ? Which is the latest spice-to-IBIS converter ? Thanks , Vivek |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 4 Apr 2005 11:47:50 -0400 From: "Todd Westerhoff \(twesterh\)" Subject: RE: [IBIS-Users] ODT topics Radovan, I don't remember that I've seen many replies from vendors in response to your original question. So ... I offer these words of advice. Many models end clamp curves at 0V, because they assume clamp current will be zero at that point. As you have already pointed out, input termination doesn't work that way, so the current at 0V is non-zero. Because 0V in the clamp curves corresponds to the supply voltage, and positive voltage extends out beyond the supply - a clamp curve that ends at 0V will have to extrapolate inside of the device's actual operating region. If the current ans slope at 0V are zero, the extrapolation is trivial. That's not the case for input termination, and we've found that different simulators use different techniques for extrapolating data off end of the curve. Some tools extarpolate using the slope at the endpoint; others simply extend the last value of the curve out flat (i.e. slope = 0). I've never seen a thorough listing of which tool does what - our knowledge is based on empirical observation. My recommendation - define your clamp curves completely - from -2*VDDQ to VDDQ - so the simulator never needs to extrapolate the values. Todd. Todd Westerhoff High Speed Design Group Manager Cisco Systems 1414 Massachusetts Ave - Boxboro, MA - 01719 email:twesterh@cisco.com ph: 978-936-2149 ============================================ "Always do right. This will gratify some people and astonish the rest." - - Mark Twain - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Radovan.Vuletic@infineon.com Sent: Friday, April 01, 2005 9:50 AM To: ibis-users@eda.org Subject: [IBIS-Users] ODT topics Hi, recently I have took responsibility for IBIS models in Memory Products of Infineon and soon I have realised that it is very tricky. There were generated some ODT IBIS models (for DDR2 with thevenin impedance, not possible to separate Pull-up and Pull -down impedance) with s2ibis2 as Inputs with Power and Ground Clamps curves. Everything was OK until first customer were complaining that during his simulations our ODT behave other than comparing to Samsung and Micron ODT's. After some 5-6 hours of frustrating analysis we have discovered that the "only" problem is that neither the clamp curves are cut where they reach zero nor they are extrapolated horizontally to 2*Vcc. As soon as we done that (cutting at zero current and extrapolating to 2*Vcc) everything was OK. By the way, Mr. Muranyi has nicely explained this procedure in his paper "Modeling on-die terminations in IBIS (without double counting)". The problem that we have experienced is obviously because of double counting of some data. My question would be: what are simulators (e.g. HSPICE) really doing with IBIS models (specially with Input models), how are data treated, what is the algorithm of calculation (if designer was aware of this algorithm double counting could be perhaps avoided)? Is it possible to get this things written in electronic form or anywhere on Internet? By the way, on IBIS summit Meeting in Munich in March (DATE 2005) somebody mentioned something about some Cookbook for ODT's. Is there any estimation when will this Cookbook appear? Many thanks in advance for any help or advice, Radovan Vuletic Infineon Technologies AG MP PD PDE Room 03.911 Balanstraße 73 D-81541 München Phone: +49 (0)89 234 20108 Fax: +49 (0)89 234 27705 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@infineon.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org with just |the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 4 Apr 2005 09:45:50 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] Latest IBIS Version Vivek, The latest version of IBIS is v4.1, and the v4.1 parser (IBIS checker) has also been released not too long ago. True, the latest IBIS converter, s2ibis3 supports IBIS 3.2, but you can do a lot by hand to give you a 4.1 model. Arpad - ---------------------------------------------------------- - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Vivek Kumar Sundriyal Sent: Sunday, April 03, 2005 10:25 PM To: ibis-users@eda.org; owner-ibis-users@eda.org Subject: [IBIS-Users] Latest IBIS Version Hi , I want to use the latest version of the spice-to-IBIS converter. On the website (http://www.eigroup.org/ibis/tools.htm ) I notice that the IBIS Golden parser supports IBIS Version 4.0, but the latest Spice-to-IBIS converter is s2ibis3 which supports v3.2. My questions are : Which is the latest version of IBIS ? Is it 3.2 or 4.0 ? Which is the latest spice-to-IBIS converter ? Thanks , Vivek |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 4 Apr 2005 09:51:09 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] ODT topics Andy, (I got two of these messages). You are making a good point, but the way I understood this story was that if you didn't define those optional clamp reference nodes, the current was automatically coming out of the pullup and pulldown reference nodes, just as if the clamp reference would have been shorted to them. Now, in the earlier version of HSPICE there was a bug in this, but I thought that was fixed a long time ago, though I didn't check it lately. I got too used to defining all nodes every time I use it... Arpad ======================================================== - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andrew Ingraham Sent: Saturday, April 02, 2005 5:34 AM To: ibis-users@eda.org Subject: Re: [IBIS-Users] ODT topics Hmmm, my mail doesn't seem to be reaching eda.org. Here is try # 3: > "My question would be: what are simulators (e.g. HSPICE) really doing with > IBIS models ... > The clamp I-V tables are always present in the simulation, and > the pullup and pulldown I-V tables are switched on/off as the > buffer is driving high/low. The end result is that the currents > of the pullup or pulldown I-V tables are added together with > the clamps. Well actually, ... Sorry to nit-pick, but in HSPICE the clamps are not necessarily always there. The end-user who puts an IBIS model in his simulation needs to make sure to include ALL the optional element nodes. If he leaves the optional nodes out, HSPICE has this nasty feature (it is really intended as a feature, not a bug) that the clamp I-V tables are omitted. Once those nodes are included in the netlist, then Arpad's statement above is correct. Regards, Andy |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 4 Apr 2005 09:55:18 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] How we can model preemphasis and deemphasis Akhilesh, Look at two of my latest presentations on this subject. http://www.eda.org/pub/ibis/summits/jan05/muranyi.pdf http://www.eda.org/pub/ibis/summits/mar05/muranyi.pdf I hope you will find useful information in these presentations. There are some others as well if you keep digging... Arpad ======================================================= - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Akhilesh CHANDRA Sent: Saturday, April 02, 2005 2:29 AM To: Akhilesh CHANDRA; ibis-info@eda.org; ibis-users@eda.org Subject: [IBIS-Users] How we can model preemphasis and deemphasis Hello, In my one buffer preemphasis and deemphasis is present . Can any one model this in IBIS . if any one have any doc regarding this then please give me I am not able to understand how we model this. Regards Akhilesh |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Apr 2005 18:59:31 -0400 From: "Ambrish Varma" Subject: [IBIS-Users] delay problem This is a multi-part message in MIME format. - ------=_NextPart_000_0093_01C53A11.9A14B2F0 Content-Type: multipart/alternative; boundary="----=_NextPart_001_0094_01C53A11.9A14B2F0" - ------=_NextPart_001_0094_01C53A11.9A14B2F0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hello, I know this problem has been asked several times and answered several times as well. So my apologies in advance. Attached is a comparison of hspice and ibis circuits. I want to know a) Why there is a delay at the falling edge. b) Where delay information is stored in an IBIS model, if at all. c) Does it matter to have a delay? The periods seem to match up. The IBIS model is created from hspice netlist. Thanks for any feedback, Regards, Ambrish. Ambrish K Varma akvarma@ncsu.edu North Carolina State University ph(919)513-2015, fax(919)515-2285 - ------=_NextPart_001_0094_01C53A11.9A14B2F0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hello,

I know this problem has been asked several times and answered several times as well.

So my apologies in = advance.

 

Attached is a comparison of hspice and ibis circuits. = I want to know

a)       = Why there is a delay at the falling edge.

b)       = Where delay information is stored in an IBIS model, if at = all.

c)       = Does it matter to have a delay? The periods seem to match = up.

The IBIS model is created from hspice = netlist.

 

Thanks for any feedback,

Regards,

Ambrish.

 

Ambrish K = Varma

akvarma@ncsu.edu<= /span>

North = Carolina State University

ph(919)513-2015, fax(919)515-2285

 

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attaching the replies I got for the same question a while ago. Looks like you have a similar issue.=20 Hope this helps. Prabhu/~ ___snip_________________________________________________________________ _____=20 =20 -----Original Message----- From: Bob Ross [mailto:bob@teraspeed.com ] Sent: Tuesday, March 16, 2004 1:27 AM To: Mohan, Prabhu Cc: Ibis-Users (E-mail) Subject: Re: [IBIS-Users] IBIS-SPICE correlation Hello Prabhu: Several people provided some useful observations. It is difficult to give specific advice without having all the data (IBIS file, test circuit, simulator used). However, I suggest checking if "over-clocking" exists per Arpad Muranyi's response and presentation link below by doing these tests: (1) Run the simulation with even a slower cycle time such as an 80 ns period to see if the second cycle rising edge "snaps" into overlaying correlation. (2) Or possibly modify the IBIS file itself and truncate the [Falling Waveform] data to 20 ns or less. The test condition appears to be a lightly loaded buffer (3.3 V swing) but the internal tables may be based on R_fixture values of 50 ohms. One of the falling edge tables may be longer than 20 ns. The EDA tool should check for transition completion in case the model waveform tables are documented over a conservatively long time duration. Either the completion condition is not satisfied or such a test may not exist. The EDA tool may be assuming an "over-clocking" condition and cause a "snap" to next edge transition and lose the edge delay. Bob Ross Teraspeed Consulting Group --------- Arpad Muranyi's response: Your waveform tables seem to be longer than the pulse width of your simulation stimulus. Please see my the first part of my presentation for explanation: http://www.eda.org/pub/ibis/summits/jun03b/muranyi2.pdf =20 The clue is that the first edge is correct, but from the second edge onward you have a shift. I hope this helps, Arpad ___snip_________________________________________________________________ _____=20 =20 ________________________________ From: Ambrish Varma [mailto:akvarma@ncsu.edu]=20 Sent: Tuesday, April 05, 2005 4:00 PM To: ibis-users@eda.org Cc: ibis@eda.org Subject: [IBIS-Users] delay problem Hello, I know this problem has been asked several times and answered several times as well. So my apologies in advance. =20 Attached is a comparison of hspice and ibis circuits. I want to know=20 a) Why there is a delay at the falling edge. b) Where delay information is stored in an IBIS model, if at all. c) Does it matter to have a delay? The periods seem to match up. The IBIS model is created from hspice netlist. =20 Thanks for any feedback, Regards,=20 Ambrish. =20 Ambrish K Varma akvarma@ncsu.edu North Carolina State University ph(919)513-2015, fax(919)515-2285 =20 - ------_=_NextPart_001_01C53A34.DAA090AF Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable RE: [IBIS-Users] delay problem

Hi = Ambarish

I am = attaching the replies I got for the same question a while = ago.
Looks like = you have a similar issue.
Hope this = helps.
Prabhu/~



___snip_____________________________________________________________= _________
 

    -----Original Message-----

    From: Bob = Ross [mailto:bob@teraspeed.com <mailto:bob@teraspeed.com> ]
    Sent: = Tuesday, March 16, 2004 1:27 AM
    To: Mohan, = Prabhu
    Cc: = Ibis-Users (E-mail)
    Subject: = Re: [IBIS-Users] IBIS-SPICE correlation

    Hello = Prabhu:

    Several = people provided some useful observations. It is difficult
    to give = specific advice without having all the data (IBIS file,
    test = circuit, simulator used).
    However, I = suggest checking if "over-clocking" exists per = Arpad
    Muranyi's = response and presentation link below by doing these
    tests:

    (1) Run the = simulation with even a slower cycle time such as an
    80 ns = period to see if the second cycle rising edge "snaps" = into
    overlaying = correlation.
    (2) Or = possibly modify the IBIS file itself and truncate
    the = [Falling Waveform] data to 20 ns or less.
    The test = condition appears to be a lightly loaded buffer (3.3 V
    swing) but = the internal tables may be based on R_fixture values
    of 50 ohms. = One of the falling edge tables may be longer than 20 ns.
    The EDA = tool should check for transition completion in case the
    model = waveform tables are documented over a conservatively long
    time = duration. Either the completion condition is not satisfied
    or such a = test may not exist. The EDA tool may be assuming an
    "over-clocking" condition and cause a "snap" to = next edge
    transition = and lose the edge delay.

    Bob = Ross
    Teraspeed = Consulting Group

    ---------

    Arpad = Muranyi's response:

    Your = waveform tables seem to be longer than the pulse
    width of = your simulation stimulus. Please see my the
    first part = of my presentation for explanation:
    http://www.eda.org/pub/ibis/summits/jun03b/muranyi2.pdf = <http://www.eda.org/pub/ibis/summits/jun03b/muranyi2.pdf> =

    The clue is = that the first edge is correct, but from
    the second = edge onward you have a shift.
    I hope this = helps,

    Arpad

___snip_____________________________________________________________= _________
 

________________________________

From: = Ambrish Varma [mailto:akvarma@ncsu.edu]
Sent: = Tuesday, April 05, 2005 4:00 PM
To: = ibis-users@eda.org
Cc: = ibis@eda.org
Subject: = [IBIS-Users] delay problem



Hello,

I know this = problem has been asked several times and answered several times as = well.

So my = apologies in advance.

 

Attached is = a comparison of hspice and ibis circuits. I want to know

a)       Why there is a delay at the = falling edge.

b)       Where delay information is = stored in an IBIS model, if at all.

c)       Does it matter to have a = delay? The periods seem to match up.

The IBIS = model is created from hspice netlist.

 

Thanks for = any feedback,

Regards, =

Ambrish.

 

Ambrish K = Varma

akvarma@ncsu.edu

North = Carolina State University

ph(919)513-2015, fax(919)515-2285

 

- ------_=_NextPart_001_01C53A34.DAA090AF-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 06 Apr 2005 17:30:55 +0800 From: slwu Subject: [IBIS-Users] [Question] about a true differential buffer in a [Component] This is a multi-part message in MIME format. - --------------B70AF4F693CE83A7E474A4D2 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Experts, In IBIS4.1 specification, a true differential buffer has two polarity-inverted ports, i.e. 'A_signal_pos' and 'A_signal_neg'... and my question is whether we also need two pins in [Component] to map these two ports for only one true differential buffer? Thanks Shulong - --------------B70AF4F693CE83A7E474A4D2 Content-Type: text/x-vcard; charset=us-ascii; name="Shulong.Wu.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for slwu Content-Disposition: attachment; filename="Shulong.Wu.vcf" begin:vcard n:Wu;Shawn x-mozilla-html:TRUE org:Synopsys Inc. HSPICE Team adr:;;;;;; version:2.1 email;internet:slwu@synopsys.com title:Signal Integrity Engineer x-mozilla-cpt:;-30400 fn:Shawn end:vcard - --------------B70AF4F693CE83A7E474A4D2-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 6 Apr 2005 10:30:03 -0700 From: "lgreen" Subject: RE: [IBIS-Users] delay problem This is a multi-part message in MIME format. - ------=_NextPart_000_0000_01C53A93.98A4AE20 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hi, Ambrish, a) IBIS simulators trigger with a signal having a finite slope, and buffer toggles at some voltage on that slope, so a small time offset is not unusual. I would be more concerned about why the two waveform shapes are different, esp. at the top and bottom of the transitions. b) The timing information is in the V-t tables. These include the buffer's internal delay, as well as timing differences between rising and falling transitions (relative to the buffer's "signal" toggle. c) All delay effects internal to the buffer are important. Later, system timing can adjust simulated delays relative to the data sheet using the standard load (Vmeas, etc.). This relies on V-t tables being correct. Please feel free to send a sample model to the IBIS Model Review Committee. We want to support your efforts on s2ibis3. Best regards, Lynne _____ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Ambrish Varma Sent: Tuesday, April 05, 2005 4:00 PM To: ibis-users@eda.org Cc: ibis@eda.org Subject: [IBIS-Users] delay problem Hello, I know this problem has been asked several times and answered several times as well. So my apologies in advance. Attached is a comparison of hspice and ibis circuits. I want to know a) Why there is a delay at the falling edge. b) Where delay information is stored in an IBIS model, if at all. c) Does it matter to have a delay? The periods seem to match up. The IBIS model is created from hspice netlist. Thanks for any feedback, Regards, Ambrish. Ambrish K Varma akvarma@ncsu.edu North Carolina State University ph(919)513-2015, fax(919)515-2285 - ------=_NextPart_000_0000_01C53A93.98A4AE20 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi, Ambrish,

 =

a)       = IBIS simulators trigger with a signal having a finite slope, = and buffer toggles at some voltage on that slope, so a small time offset is = not unusual.  I would be more concerned about why the two waveform = shapes are different, esp. at the top and bottom of the = transitions.

b)       = The timing information is in the V-t tables.  These = include the buffer’s internal delay, as well as timing differences between = rising and falling transitions (relative to the buffer’s = “signal” toggle.

c)       = All delay effects internal to the buffer are important. = Later, system timing can adjust simulated delays relative to the data sheet using the standard load (Vmeas, etc.).  This relies on V-t tables being = correct.

 

Please feel free to send a sample = model to the IBIS Model Review Committee.  We want to support your efforts = on s2ibis3.

 

Best = regards,

Lynne

 

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Ambrish Varma
Sent: Tuesday, April 05, = 2005 4:00 PM
To: = ibis-users@eda.org
Cc: ibis@eda.org
Subject: [IBIS-Users] = delay problem

 

Hello,

I know this problem has = been asked several times and answered several times as = well.

So my apologies in = advance.

 

Attached is a comparison of = hspice and ibis circuits. I want to know

a)       = Why there is a delay at the falling edge.

b)       = Where delay information is stored in an IBIS model, if at all.

c)       = Does it matter to have a delay? The periods seem to match = up.

The IBIS model is created = from hspice netlist.

 

Thanks for any = feedback,

Regards, =

Ambrish.

 

Ambrish K Varma

akvarma@ncsu.edu

North Carolina State University

ph(919)513-2015, fax(919)515-2285

 

- ------=_NextPart_000_0000_01C53A93.98A4AE20-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 6 Apr 2005 15:49:10 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] [Question] about a true differential buffer in a [Component] Shulong, I will start with a quote from the IBIS specification from the [External Model] section: | The [Diff Pin] keyword is still required within the same | [Component] definition when [External Model] describes a true | differential buffer. The models referenced by each pin listed | under [Diff Pin] MUST be the same. This means that you must have two pins on the [Pin] list calling the SAME model name, and these two pins must be associated as a differential pair using the [Diff Pin] keyword. What may be confusing about this is that we have are instantiating a [Model] in which we have a true differential [External Model] that has two I/O terminals. The name of this single [Model] is mentioned twice on the [Pin] list, but regardless of that, it is instantiated only once, because it contains a true differential model having two I/O terminals. (If the [Model] contained a normal single ended model, it would be instantiated once for each pin, a total of two times). I hope this gave an answer to your question. Arpad - ------------------------------------------------------------------- - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of slwu Sent: Wednesday, April 06, 2005 2:31 AM To: ibis@eda.org; ibis-users@eda.org Subject: [IBIS-Users] [Question] about a true differential buffer in a [Component] Hi Experts, In IBIS4.1 specification, a true differential buffer has two polarity-inverted ports, i.e. 'A_signal_pos' and 'A_signal_neg'... and my question is whether we also need two pins in [Component] to map these two ports for only one true differential buffer? Thanks Shulong |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Apr 2005 20:39:17 +0530 From: Akhilesh CHANDRA Subject: [IBIS-Users] logic0 and logic1 problem in IBIS models Hello , I am working on one of my differential cells. When I validate my IBIS models from two different simulator then I got two different logic 0 and logic1 values. To find out it's problem of simulator or my models I must know what are the logic0 and logic1 according to the models. Can any one have any idea how we can extract logic0 and logic1 from the model files. I am highly blocked due to this issue. Your help is deeply appreciated. Regards Akhilesh |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Apr 2005 08:50:32 -0700 From: Syed Huq Subject: [IBIS-Users] New IBISCHK411 Executable available for download The ibischk4 Version 4.1.1 parser executables are now uploaded. The free executables are available for various OS platforms: http://www.eda.org/pub/ibis/ibischk4/ It contains the BUG87 fix (reinsertion of the BUG82 fix left out of Version 4.1.0). Thanks to Doran David for originally discovering the problem. Regards, Syed - -- Cisco Systems, Inc Acting Chair - EIA IBIS Forum |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Apr 2005 09:51:19 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] logic0 and logic1 problem in IBIS models Akhilesh The logic 1 and logic 0 states depend on the load attached to the buffer. If the load is an open circuit then the logic 0 will be the voltage in the pulldown table where the current is zero. The 1 will be the voltage in the pullup table where the current is zero. You can construct load lines and apply those to the IV tables to predict the output voltage for any load. Regards, Tom Dagostino Teraspeed Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 http://www.teraspeed.com tom@teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 Teraspeed is the registered service mark of Teraspeed Consulting Group LLC - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf Of Akhilesh CHANDRA Sent: Monday, April 11, 2005 8:09 AM To: ibis-users@eda.org Cc: Akhilesh CHANDRA Subject: [IBIS-Users] logic0 and logic1 problem in IBIS models Hello , I am working on one of my differential cells. When I validate my IBIS models from two different simulator then I got two different logic 0 and logic1 values. To find out it's problem of simulator or my models I must know what are the logic0 and logic1 according to the models. Can any one have any idea how we can extract logic0 and logic1 from the model files. I am highly blocked due to this issue. Your help is deeply appreciated. Regards Akhilesh |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Apr 2005 22:34:34 +0530 From: Akhilesh CHANDRA Subject: Re: [IBIS-Users] logic0 and logic1 problem in IBIS models Hello Tom, Yes, I agree with you but I find out most of the simulator not follow this rule for differential cells and fails to give correct logic labels. Is any other way by which it calculate for differential cells. Regards Akhilesh Tom Dagostino wrote: >Akhilesh > >The logic 1 and logic 0 states depend on the load attached to the buffer. >If the load is an open circuit then the logic 0 will be the voltage in the >pulldown table where the current is zero. The 1 will be the voltage in the >pullup table where the current is zero. You can construct load lines and >apply those to the IV tables to predict the output voltage for any load. > >Regards, > >Tom Dagostino >Teraspeed Labs >13610 SW Harness Lane >Beaverton, OR 97008 >503-430-1065 >http://www.teraspeed.com >tom@teraspeed.com > >Teraspeed Consulting Group LLC >121 North River Drive >Narragansett, RI 02882 >401-284-1827 > >Teraspeed is the registered service mark of >Teraspeed Consulting Group LLC > >-----Original Message----- >From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On >Behalf Of Akhilesh CHANDRA >Sent: Monday, April 11, 2005 8:09 AM >To: ibis-users@eda.org >Cc: Akhilesh CHANDRA >Subject: [IBIS-Users] logic0 and logic1 problem in IBIS models > > > >Hello , > > I am working on one of my differential cells. When I validate my IBIS >models from two different simulator then I got two different logic 0 and >logic1 values. To find out it's problem of simulator or my models I must >know what are the logic0 and logic1 according to the models. Can any one >have any idea how we can extract logic0 and logic1 from the model files. > > I am highly blocked due to this issue. Your help is deeply appreciated. > >Regards >Akhilesh > >|------------------------------------------------------------------ >|For help or to subscribe/unsubscribe, email majordomo@eda.org >|with just the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or email a written request to ibis-request@eda.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda.org/pub/ibis/email_archive/ Recent >| http://www.eda.org/pub/ibis/users_archive/ Recent >| http://www.eda.org/pub/ibis/email/ E-mail since 1993 > >|------------------------------------------------------------------ >|For help or to subscribe/unsubscribe, email majordomo@eda.org >|with just the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or email a written request to ibis-request@eda.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda.org/pub/ibis/email_archive/ Recent >| http://www.eda.org/pub/ibis/users_archive/ Recent >| http://www.eda.org/pub/ibis/email/ E-mail since 1993 > > |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Apr 2005 10:31:53 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] logic0 and logic1 problem in IBIS models The same principle applies to differential buffers as to single ended. A load line constructed between the two IV curves should predict the output high and low levels. In this case the magnitudes of the currents will be the same but the polarity will be reversed. The pullup will have -X mA and the pulldown will have +X mA. The out put voltages will be the voltage at (-)X mA. Tom Dagostino Teraspeed Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 http://www.teraspeed.com tom@teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 Teraspeed is the registered service mark of Teraspeed Consulting Group LLC - -----Original Message----- From: Akhilesh CHANDRA [mailto:akhilesh.chandra@st.com] Sent: Monday, April 11, 2005 10:05 AM To: tom@teraspeed.com Cc: ibis-users@eda.org; Akhilesh CHANDRA Subject: Re: [IBIS-Users] logic0 and logic1 problem in IBIS models Hello Tom, Yes, I agree with you but I find out most of the simulator not follow this rule for differential cells and fails to give correct logic labels. Is any other way by which it calculate for differential cells. Regards Akhilesh Tom Dagostino wrote: >Akhilesh > >The logic 1 and logic 0 states depend on the load attached to the buffer. >If the load is an open circuit then the logic 0 will be the voltage in the >pulldown table where the current is zero. The 1 will be the voltage in the >pullup table where the current is zero. You can construct load lines and >apply those to the IV tables to predict the output voltage for any load. > >Regards, > >Tom Dagostino >Teraspeed Labs >13610 SW Harness Lane >Beaverton, OR 97008 >503-430-1065 >http://www.teraspeed.com >tom@teraspeed.com > >Teraspeed Consulting Group LLC >121 North River Drive >Narragansett, RI 02882 >401-284-1827 > >Teraspeed is the registered service mark of >Teraspeed Consulting Group LLC > >-----Original Message----- >From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On >Behalf Of Akhilesh CHANDRA >Sent: Monday, April 11, 2005 8:09 AM >To: ibis-users@eda.org >Cc: Akhilesh CHANDRA >Subject: [IBIS-Users] logic0 and logic1 problem in IBIS models > > > >Hello , > > I am working on one of my differential cells. When I validate my IBIS >models from two different simulator then I got two different logic 0 and >logic1 values. To find out it's problem of simulator or my models I must >know what are the logic0 and logic1 according to the models. Can any one >have any idea how we can extract logic0 and logic1 from the model files. > > I am highly blocked due to this issue. Your help is deeply appreciated. > >Regards >Akhilesh > >|------------------------------------------------------------------ >|For help or to subscribe/unsubscribe, email majordomo@eda.org >|with just the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or email a written request to ibis-request@eda.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda.org/pub/ibis/email_archive/ Recent >| http://www.eda.org/pub/ibis/users_archive/ Recent >| http://www.eda.org/pub/ibis/email/ E-mail since 1993 > >|------------------------------------------------------------------ >|For help or to subscribe/unsubscribe, email majordomo@eda.org >|with just the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or email a written request to ibis-request@eda.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda.org/pub/ibis/email_archive/ Recent >| http://www.eda.org/pub/ibis/users_archive/ Recent >| http://www.eda.org/pub/ibis/email/ E-mail since 1993 > > |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Apr 2005 11:20:48 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] logic0 and logic1 problem in IBIS models What Tom is writing is correct, but he forgot to mention the clamp tables. The currents in the clamps tables must always be added to the calculation Tom described to find the high and low levels. Arpad ==================================================== - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Tom Dagostino Sent: Monday, April 11, 2005 9:51 AM To: Akhilesh CHANDRA; ibis-users@eda.org Subject: RE: [IBIS-Users] logic0 and logic1 problem in IBIS models Akhilesh The logic 1 and logic 0 states depend on the load attached to the buffer. If the load is an open circuit then the logic 0 will be the voltage in the pulldown table where the current is zero. The 1 will be the voltage in the pullup table where the current is zero. You can construct load lines and apply those to the IV tables to predict the output voltage for any load. Regards, Tom Dagostino Teraspeed Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 http://www.teraspeed.com tom@teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 Teraspeed is the registered service mark of Teraspeed Consulting Group LLC |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 12 Apr 2005 12:25:28 -0600 From: rrwolff@micron.com Subject: [IBIS-Users] [IBIS] Open forum minutes (04/01/05) This is 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2005 14:10:13 -0400 From: "Muck, Phil" Subject: [IBIS-Users] .top file extension This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. - ------_=_NextPart_000_01C5411D.340A3B70 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C5411D.340A3B70" - ------_=_NextPart_001_01C5411D.340A3B70 Content-Type: text/plain; charset="iso-8859-1" Done anyone know of board simulation with a .top file extension. Regards Phillip Muck Staff Engineer DATARAM Corp. (609)799-0071 ext 2323 (609)897-7035 Fax pmuck@dataram.com <> - ------_=_NextPart_001_01C5411D.340A3B70 Content-Type: text/html; charset="iso-8859-1" .top file extension

Done anyone know of board simulation with a .top file extension.

Regards
Phillip Muck
Staff Engineer
DATARAM Corp.
(609)799-0071 ext 2323
(609)897-7035 Fax
pmuck@dataram.com
<<Muck, Phil.vcf>>

- ------_=_NextPart_001_01C5411D.340A3B70-- - ------_=_NextPart_000_01C5411D.340A3B70 Content-Type: application/octet-stream; name="Muck, Phil.vcf" Content-Disposition: attachment; filename="Muck, Phil.vcf" BEGIN:VCARD VERSION:2.1 N:Muck;Phil FN:Muck, Phil ORG:Dataram Corporation;Engineering NOTE:Engineering TEL;WORK;VOICE:609-799-0071 x2323 ADR;WORK:;Princeton;PO Box 7528;Princeton;NJ;08543-7528;US LABEL;WORK;ENCODING=QUOTED-PRINTABLE:Princeton=0D=0APO Box 7528=0D=0APrinceton, NJ 08543-7528=0D=0AUS EMAIL;PREF;INTERNET:PMuck@dataram.com REV:20040525T180429Z END:VCARD - ------_=_NextPart_000_01C5411D.340A3B70-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 14 Apr 2005 13:43:53 -0500 From: Subject: RE: [IBIS-Users] .top file extension This is a multi-part message in MIME format. - ------_=_NextPart_001_01C54121.E82EF192 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cadence has a simulation tool, SigXplorer also known as Allegro PCB SI 610 that uses the .top file extension for its input file. Aubrey Sparkman=20 Enterprise Engineering Signal Integrity Team=20 Dell, Inc.=20 Aubrey_Sparkman@Dell.com=20 (512) 723-3592=20 =20 _____ =20 From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Muck, Phil Sent: Thursday, April 14, 2005 1:10 PM To: 'ibis-users@eda.org' Subject: [IBIS-Users] .top file extension Done anyone know of board simulation with a .top file extension.=20 Regards=20 Phillip Muck=20 Staff Engineer=20 DATARAM Corp.=20 (609)799-0071 ext 2323=20 (609)897-7035 Fax=20 pmuck@dataram.com=20 <>=20 - ------_=_NextPart_001_01C54121.E82EF192 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable .top file extension
Cadence has a simulation tool, = SigXplorer also=20 known as Allegro PCB SI 610 that uses the .top file extension for its = input=20 file.

Aubrey = Sparkman=20
Enterprise=20 Engineering Signal Integrity Team
Dell, Inc.
Aubrey_Sparkman@Dell.com =
(512) = 723-3592

 

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Muck, = Phil
Sent:=20 Thursday, April 14, 2005 1:10 PM
To:=20 'ibis-users@eda.org'
Subject: [IBIS-Users] .top file=20 extension

Done anyone know of board simulation with = a .top file=20 extension.

Regards
Phillip Muck
Staff=20 Engineer
DATARAM = Corp.=20
(609)799-0071 ext 2323 =
(609)897-7035 Fax
pmuck@dataram.com
<<Muck, Phil.vcf>>

- ------_=_NextPart_001_01C54121.E82EF192-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #56 ************************