IBIS Summit First Call for Papers - DesignCon East (IEC) Sep 19th = 2005

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Andy = Joe
Sent:=20 Wednesday, July 27, 2005 4:18 AM
To:=20 ibis-users@eda.org
Subject: [IBIS-Users] IBIS=20 Question

Hi,

I have a question = regarding the=20 [Package] keyword in an IBIS file. As far as I am concerned, the RLC = values in=20 this section applied to all the I/O pins, my question is if these RLC = values=20 also applied to power and ground pins as well? If they are not applied = to power=20 and ground pins, how can we address the effects of different packages to = the=20 power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin for = every=20 single pin are not available, only package min, typ and max RLC are = available)

Thanks.

-Andy

St= art your=20 day with Yahoo! - make it your home page - ------_=_NextPart_001_01C592C1.33849FDD-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 27 Jul 2005 17:59:25 -0700 (PDT) From: Andy Joe Subject: RE: [IBIS-Users] IBIS Question - --0-1839443901-1122512365=:39569 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Thanks Arpad... Can Mentor and Cadence tool vendors give comment about this if the tools applied the package RLC value to the power and ground pins as well? If not, may I know how the tools handle the effect caused by package parasitic i.e. IR drop? Thanks. - -Andy "Muranyi, Arpad" wrote: Andy, The problem is that the IBIS spec doesn't spell out that the package parameters are also to be applied to power and GND pins. In my opinion they should be used for those too, but it doesn't mean that all tool vendors do it. Arpad =========================================================== - --------------------------------- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe Sent: Wednesday, July 27, 2005 4:18 AM To: ibis-users@eda.org Subject: [IBIS-Users] IBIS Question Hi, I have a question regarding the [Package] keyword in an IBIS file. As far as I am concerned, the RLC values in this section applied to all the I/O pins, my question is if these RLC values also applied to power and ground pins as well? If they are not applied to power and ground pins, how can we address the effects of different packages to the power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin for every single pin are not available, only package min, typ and max RLC are available) Thanks. - -Andy - --------------------------------- Start your day with Yahoo! - make it your home page - --------------------------------- Start your day with Yahoo! - make it your home page - --0-1839443901-1122512365=:39569 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit

Thanks Arpad...

Can Mentor and Cadence tool vendors give comment about this if the tools applied the package RLC value to the power and ground pins as well? If not, may I know how the tools handle the effect caused by package parasitic i.e. IR drop?

Thanks.

-Andy

"Muranyi, Arpad" <arpad.muranyi@intel.com> wrote:

Andy,

The problem is that the IBIS spec doesn't spell out that

the package parameters are also to be applied to power

and GND pins. In my opinion they should be used for those

too, but it doesn't mean that all tool vendors do it.

Arpad

===========================================================

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe
Sent: Wednesday, July 27, 2005 4:18 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] IBIS Question

Hi,

I have a question regarding the [Package] keyword in an IBIS file. As far as I am concerned, the RLC values in this section applied to all the I/O pins, my question is if these RLC values also applied to power and ground pins as well? If they are not applied to power and ground pins, how can we address the effects of different packages to the power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin for every single pin are not available, only package min, typ and max RLC are available)

Thanks.

-Andy

Start your day with Yahoo! - make it your home page

Start your day with Yahoo! - make it your home page - --0-1839443901-1122512365=:39569-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 28 Jul 2005 11:10:37 +0530 From: Subject: RE: [IBIS-Users] IBIS Question Hi vivek, Thanks for the earliest response. 1) I cheked with IBISCHK4 it did not report even warning for this [Rgnd] of 52kohm ,and for another model also [Rgnd] is used as 600Kohm same is case. But our problem is we sent the model to our customer and they are using ICX I don't know which version but it is reporting "Bad Numerical Value". Is this problem with [Rgnd] key word or with "ohm" which I used after 52K. 2)If I make version 4.0 it will not show the all Non-monotonic warnings but ICX does not support 4.0 Version because of this constraint I had give ibis model with 3.2 to my customer. 3)for [Model Selector] is supported by the ICX, if so which versions will allow this feature. Best Regards Kiran Kumar - -----Original Message----- From: Vivek Kumar Sundriyal [mailto:Vivek.Kumar.Sundriyal@nsc.com] Sent: Thursday, July 28, 2005 10:41 AM To: Seshadri KiranKumar (WT01 - EMBEDDED & PRODUCT ENGINEERING SOLUTIONS) Subject: RE: [IBIS-Users] IBIS Question Hi Kiran , For 1) If the R-pkg values are more than 50KOhm, IBISCheck gives a warning ( only if the IBIS version is 4.0) that the range of R-pkg is 0 to 50K. I dont know if the same case exists with [Rgnd]. You can probably give it a try. For 2) To cross-check on the non-monotonic warning, make your IBIS Version to 4.0 and then try ibschk4 again. What is important is the summation of the Pullup and Powerclamp and the pulldown and gndclamp. This summation should be monotonic. If your IBIS version is made 4.0,IBISCHK4 checks for this summation. And if the summation is monotonic, you wont get warning errors. For sure for the error 3. Cheers , Vivek seshadri.kirankuma r@wipro.com To: ibis-users@eda.org, owner-ibis-users@eda.org, si-list-request@freelists.org, Sent by: si-list@freelists.org owner-ibis-users@e cc: da.org Subject: RE: [IBIS-Users] IBIS Question 07/27/05 08:19 PM Hi , I have some problem with IBIS model that I had delivered to my customer. I have attached REPORT file listing all Errors that ICX tool parsed. There you can find 3 kinds of warnings as follows: 1) ;;Error : at line 3991 in file txt05668.ibs : Bad numerical value 52Kohm found. This is because in this component few of models using [Rgnd] key word as follows [Rgnd] 52kohm NA NA i am feeling this Error is because of "ohm" . If I am correct why it is not showing atleast warning in IBISCHK4 case. 2) ;;Error : at line 4438 in file txt05668.ibs : Messages for model BT0005_MODE0: ;; ;; Error: The sum of the typical clamp curves is not monotonic at voltage 1.78. ;; ;; Error: The sum of the maximum clamp curves is not monotonic at voltage 1.87. IBISCHK4 lists as a Non-monotonicity warnings where as ICX listing them as Errors. It would help me lot if you mention how to silence these warnings. 3) ;;Warning : at line 5316 in file txt05668.ibs : Pin model BT0005_MODE0 referred to by the selector BT0005_MODE does not exist in this file. Ignoring this selection. This I have mentioned Model selector key word option as follows [Model Selector] BT0005_MODE BT0005_MODE0 Buffer oprating at 1.8V BT0005_MODE1 Buffer oprating at 2.75V BT0005_MODE2 Buffer oprating at 3.3V As far IBIS since it is proper definition it is not listing where as it is not recognizing by ICX tool Kindly help me by providing proper solution for above problems. Thanks in advance for your valuable support. Best Regards Kiran Kumar Confidentiality Notice The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain confidential or privileged information. If you are not the intended recipient, please notify the sender at Wipro or Mailadmin@wipro.com immediately and destroy all copies of this message and any attachments. (See attached file: txt05668.report.txt) Confidentiality Notice The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain confidential or privileged information. If you are not the intended recipient, please notify the sender at Wipro or Mailadmin@wipro.com immediately and destroy all copies of this message and any attachments. |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 28 Jul 2005 09:12:14 -0700 From: "Beal, Weston" Subject: RE: [IBIS-Users] IBIS Question This is a multi-part message in MIME format. - ------_=_NextPart_001_01C5938F.1EA8BF82 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Andy, =20 You should assume that all IBIS simulations use ideal voltage sources at the power and ground nodes of the IBIS model unless proven otherwise. That's the way ICX used to do it, and I believe others did as well. With the advent of BIRD75, ICX now supports the inclusion of a SPICE or VHDL-AMS circuit for a more complete model of the package including connections from the power and ground nodes of the IBIS model to the PCB. =20 Regards, Weston =20 ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe Sent: Wednesday, July 27, 2005 5:59 PM To: Muranyi, Arpad; ibis-users@eda.org Subject: RE: [IBIS-Users] IBIS Question Thanks Arpad... Can Mentor and Cadence tool vendors give comment about this if the tools applied the package RLC value to the power and ground pins as well? If not, may I know how the tools handle the effect caused by package parasitic i.e. IR drop? Thanks. - -Andy "Muranyi, Arpad" wrote: Andy, =20 The problem is that the IBIS spec doesn't spell out that the package parameters are also to be applied to power and GND pins. In my opinion they should be used for those too, but it doesn't mean that all tool vendors do it. =20 Arpad = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe Sent: Wednesday, July 27, 2005 4:18 AM To: ibis-users@eda.org Subject: [IBIS-Users] IBIS Question =09 =09 Hi, =20 I have a question regarding the [Package] keyword in an IBIS file. As far as I am concerned, the RLC values in this section applied to all the I/O pins, my question is if these RLC values also applied to power and ground pins as well? If they are not applied to power and ground pins, how can we address the effects of different packages to the power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin for every single pin are not available, only package min, typ and max RLC are available) Thanks. =20 -Andy =09 ________________________________ Start your day with Yahoo! - make it your home page =20 ________________________________ Start your day with Yahoo! - make it your home page =20 - ------_=_NextPart_001_01C5938F.1EA8BF82 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Andy,

You should assume that all IBIS simulations use = ideal=20 voltage sources at the power and ground nodes of the IBIS model unless = proven=20 otherwise. That's the way ICX used to do it, and I believe others did as = well.=20 With the advent of BIRD75, ICX now supports the inclusion of a SPICE or = VHDL-AMS=20 circuit for a more complete model of the package including connections = from the=20 power and ground nodes of the IBIS model to the PCB.

Regards,

Weston

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Andy = Joe
Sent:=20 Wednesday, July 27, 2005 5:59 PM
To: Muranyi, Arpad;=20 ibis-users@eda.org
Subject: RE: [IBIS-Users] IBIS=20 Question

Thanks Arpad...

Can Mentor and Cadence tool vendors give comment about this if the = tools=20 applied the package RLC value to the power and ground pins as well? If = not, may=20 I know how the tools handle the effect caused by package parasitic i.e. = IR=20 drop?

Thanks.

-Andy

"Muranyi, Arpad" = <arpad.muranyi@intel.com>=20 wrote:

Andy,

The problem is that the IBIS spec doesn't = spell out=20 that

the package parameters are also to be = applied to=20 power

and GND pins. In my opinion they = should be used=20 for those

too, but it doesn't mean = that all tool=20 vendors do it.

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Andy = Joe
Sent:=20 Wednesday, July 27, 2005 4:18 AM
To:=20 ibis-users@eda.org
Subject: [IBIS-Users] IBIS=20 Question

Hi,

I have a question = regarding the=20 [Package] keyword in an IBIS file. As far as I am concerned, the RLC = values in=20 this section applied to all the I/O pins, my question is if these RLC = values=20 also applied to power and ground pins as well? If they are not applied = to=20 power and ground pins, how can we address the effects of different = packages to=20 the power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin = for=20 every single pin are not available, only package min, typ and max = RLC are=20 available)

Thanks.

-Andy

St= art=20 your day with Yahoo! - make it your home page

St= art your=20 day with Yahoo! - make it your home page - ------_=_NextPart_001_01C5938F.1EA8BF82-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 28 Jul 2005 09:35:59 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] IBIS Question This is a multi-part message in MIME format. - ------_=_NextPart_001_01C59392.70087554 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Andy, =20 Sorry for the "canned" answer but such tool specific questions are best if directed to the vendor... To be honest, I don't know these details about these tools, and I don't want to give you misleading answers. Plus, the answers may not be a simple yes or no either. =20 Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ________________________________ From: Andy Joe [mailto:andy_joe123@yahoo.com]=20 Sent: Wednesday, July 27, 2005 5:59 PM To: Muranyi, Arpad; ibis-users@eda.org Subject: RE: [IBIS-Users] IBIS Question Thanks Arpad... Can Mentor and Cadence tool vendors give comment about this if the tools = applied the package RLC value to the power and ground pins as well? If = not, may I know how the tools handle the effect caused by package = parasitic i.e. IR drop? Thanks. - -Andy "Muranyi, Arpad" wrote: Andy, =20 The problem is that the IBIS spec doesn't spell out that the package parameters are also to be applied to power and GND pins. In my opinion they should be used for those too, but it doesn't mean that all tool vendors do it. =20 Arpad = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On = Behalf Of Andy Joe Sent: Wednesday, July 27, 2005 4:18 AM To: ibis-users@eda.org Subject: [IBIS-Users] IBIS Question =09 =09 Hi, =20 I have a question regarding the [Package] keyword in an IBIS file. As = far as I am concerned, the RLC values in this section applied to all the = I/O pins, my question is if these RLC values also applied to power and = ground pins as well? If they are not applied to power and ground pins, = how can we address the effects of different packages to the power and = ground pins in an IBIS model? (If R_pin, L_pin and C_pin for every = single pin are not available, only package min, typ and max RLC are = available) Thanks. =20 -Andy =09 ________________________________ Start your day with Yahoo! - make it your home page = =20 ________________________________ Start your day with Yahoo! - make it your home page = =20 - ------_=_NextPart_001_01C59392.70087554 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Andy,

Sorry for the "canned" answer but such tool = specific=20 questions

are best if directed to the vendor... = To be=20 honest, I don't know

these details about these tools, and I don't = want to=20 give you

misleading answers. Plus, the answers = may not be=20 a simple yes or

no either.

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=

From: Andy Joe = [mailto:andy_joe123@yahoo.com]=20
Sent: Wednesday, July 27, 2005 5:59 PM
To: Muranyi, = Arpad;=20 ibis-users@eda.org
Subject: RE: [IBIS-Users] IBIS=20 Question

Thanks Arpad...

Thanks.

-Andy

"Muranyi, Arpad" = <arpad.muranyi@intel.com>=20 wrote:

Andy,

The problem is that the IBIS spec doesn't = spell out=20 that

the package parameters are also to be = applied to=20 power

and GND pins. In my opinion they = should be used=20 for those

too, but it doesn't mean = that all tool=20 vendors do it.

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Andy = Joe
Sent:=20 Wednesday, July 27, 2005 4:18 AM
To:=20 ibis-users@eda.org
Subject: [IBIS-Users] IBIS=20 Question

Hi,

I have a question = regarding the=20 [Package] keyword in an IBIS file. As far as I am concerned, the RLC = values in=20 this section applied to all the I/O pins, my question is if these RLC = values=20 also applied to power and ground pins as well? If they are not applied = to=20 power and ground pins, how can we address the effects of different = packages to=20 the power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin = for=20 every single pin are not available, only package min, typ and max = RLC are=20 available)

Thanks.

-Andy

St= art=20 your day with Yahoo! - make it your home page

St= art your=20 day with Yahoo! - make it your home page - ------_=_NextPart_001_01C59392.70087554-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 28 Jul 2005 12:56:01 -0400 From: "Lance Wang" Subject: RE: [IBIS-Users] IBIS Question This is a multi-part message in MIME format. - ------_=_NextPart_001_01C59395.3CBF35C9 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable Andy, Try to take Arpad out your web. :-) Just for your information, Cadence tool (PCB SI) does include RLC for power/gnd pins in the network if their specified in the IBIS model. =20 Please be free to send a private email to me for specific Cadence tool questions. =20 Best regards, Lance Wang=20 Cadence Design Systems, Inc.=20 978-262-6685=20 ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe Sent: Wednesday, July 27, 2005 8:59 PM To: Muranyi, Arpad; ibis-users@eda.org Subject: RE: [IBIS-Users] IBIS Question =20 Thanks Arpad... Can Mentor and Cadence tool vendors give comment about this if the tools applied the package RLC value to the power and ground pins as well? If not, may I know how the tools handle the effect caused by package parasitic i.e. IR drop? Thanks. - -Andy "Muranyi, Arpad" wrote: Andy, =20 The problem is that the IBIS spec doesn't spell out that the package parameters are also to be applied to power and GND pins. In my opinion they should be used for those too, but it doesn't mean that all tool vendors do it. =20 Arpad = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D =20 =09 ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe Sent: Wednesday, July 27, 2005 4:18 AM To: ibis-users@eda.org Subject: [IBIS-Users] IBIS Question Hi, =20 I have a question regarding the [Package] keyword in an IBIS file. As far as I am concerned, the RLC values in this section applied to all the I/O pins, my question is if these RLC values also applied to power and ground pins as well? If they are not applied to power and ground pins, how can we address the effects of different packages to the power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin for every single pin are not available, only package min, typ and max RLC are available) Thanks. =20 -Andy =09 ________________________________ Start your day with Yahoo! - make it your home page =20 ________________________________ Start your day with Yahoo! - make it your home page =20 - ------_=_NextPart_001_01C59395.3CBF35C9 Content-Type: text/html; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable

Andy,

Try to take Arpad out your web. = J

Just for your information, Cadence = tool (PCB SI) does include RLC for power/gnd pins in the network if their = specified in the IBIS model.

Please be free to send a private = email to me for specific Cadence tool questions.

Best = regards,

Lance Wang
Cadence Design Systems, = Inc.
978-262-6685

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe
Sent: Wednesday, July 27, = 2005 8:59 PM
To: Muranyi, Arpad; ibis-users@eda.org
Subject: RE: [IBIS-Users] = IBIS Question

Thanks Arpad...

Can Mentor and Cadence tool vendors give comment about this if the tools applied = the package RLC value to the power and ground pins as well? If not, may I = know how the tools handle the effect caused by package parasitic i.e. IR = drop?

Thanks.

-Andy

"Muranyi, Arpad" <arpad.muranyi@intel.com> = wrote:

Andy,

The problem is that = the IBIS spec doesn't spell out that

the package = parameters are also to be applied to power

and GND pins. = In my opinion they should be used for those

too, but it doesn't = mean that all tool vendors do it.

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe
Sent: Wednesday, July 27, = 2005 4:18 AM
To: = ibis-users@eda.org
Subject: [IBIS-Users] = IBIS Question

Hi,=

I have a question regarding = the [Package] keyword in an IBIS file. As far as I am concerned, the RLC = values in this section applied to all the I/O pins, my question is if these RLC = values also applied to power and ground pins as well? If they are not applied = to power and ground pins, how can we address the effects of different packages to = the power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin for = every single pin are not available, only package min, typ and max RLC are available)

Thanks.

-Andy

Sta= rt your day with Yahoo! - make it your home page =

Sta= rt your day with Yahoo! - make it your home page =

- ------_=_NextPart_001_01C59395.3CBF35C9-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 28 Jul 2005 16:44:11 -0700 From: "Syed Huq \(shuq\)" Subject: [IBIS-Users] IBIS Summit First Call for Papers - DesignCon East (IEC) Sep 19th 2005 This is a multi-part message in MIME format. - ------_=_NextPart_001_01C593CE.65E45A68 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable - ----------------------------------------------------------------------- IBIS SUMMIT at DesignCon East (IEC) FIRST CALL FOR PARTICIPATION & PRESENTATIONS - ----------------------------------------------------------------------- I B I S S U M M I T M E E T I N G Time/Date: Monday September 19, 2005 8:00 AM to 5 PM Location: DCU Center Worcester, Massachusetts Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: DesignCon East (IEC) Cadence, Mentor Graphics, Intel, SiSoft If your company would be interested in sponsoring this event, please contact Syed Huq . Benefits to sponsors include formal recognition at the meeting and acknowledgement in the Calls for Papers and meeting minutes. Your financial support strengthens the organization by allowing IBIS to focus resources on industry activities rather than raising money, and you will receive generous thanks for your support. DesignCon East Conference September 19 - 21, 2005 DCU Center Worcester, Massachusetts =20 For more information, see Catalog: = BACKGROUND DesignCon East (IEC)is the premier annual event for electronic design engineers working at the chip, board, and system levels in the Eastern Region of the United States. Topics of current interest to the EIA IBIS Open Forum are addressed at DesignCon East. This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. Any pending formal decisions (votes) will be announced at least two weeks prior to the meeting. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Send to: Beth MacKenzie CALL FOR PRESENTATIONS We are seeking presentations from individuals who have experiences of interest to the IBIS modeling community. In the past, these have included demonstrations of modeling techniques, explanations of behavioral algorithms and descriptions of difficulties encountered in specific applications. Of particular interest are topics related to model correlation, modeling building experiences and comparisons to other modeling methods. Presentations may be addressed to any and all levels of IBIS experience, from beginning to advanced. Format of Presentation: LCD Projection with Windows laptop. Time: 15-30 Minutes Electronic Archival: We request electronic versions so that the presentations can be archived and also made available to non-attendees. Formats used in the past have been text, Power Point, Word, Postscript, and Acrobat. Electronic presentations should be made available by September 12, 2005 for uploading and copying to the presentation laptop. If you plan a presentation, please supply Title: Presenter: E-mail address: Company: Telephone: Estimated Time: Send this to: Syed Huq AGENDA The agenda includes presentations, discussions, breaks, and a = luncheon. This will be developed as presentation proposals are received. The following individuals have signed up to present at the summit (presentation titles are tentative). LIST OF NEARBY HOTELS See for = travel directions, hotels and other information. - ----------------------------------------------------------------- - ------_=_NextPart_001_01C593CE.65E45A68 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable IBIS Summit First Call for Papers - DesignCon East (IEC) Sep 19th = 2005

----------------------------------------------------------------= - -------
            &= nbsp; IBIS SUMMIT at DesignCon East (IEC)
            &= nbsp;        FIRST CALL FOR
            &= nbsp; PARTICIPATION & PRESENTATIONS
- -----------------------------------------------------------------------

            &= nbsp; I B I S   S U M M I T   M E E T I N G

Time/Date: Monday September 19, 2005 8:00 AM to 5 PM

Location:   DCU Center
            = Worcester, Massachusetts

Content:    Presentations and Discussions

Purpose:    Solicit and Exchange IBIS Model Related = Information
            and = Ideas.

Sponsors:   DesignCon East (IEC)
            = Cadence, Mentor Graphics, Intel, SiSoft

            If = your company would be interested in sponsoring this
            = event, please contact Syed Huq
            = <shuq@cisco.com>.
            = Benefits to sponsors include formal recognition at the
            = meeting and acknowledgement in the Calls for Papers and
            = meeting minutes.

            Your = financial support strengthens the organization by
            = allowing IBIS to focus resources on industry activities
            = rather than raising money, and you will receive generous
            = thanks for your support.

DesignCon East Conference
            = September 19 - 21, 2005
            DCU = Center
            = Worcester, Massachusetts

            For = more information, see
            = <http:/= /www.iec.org/events/2005/designcon_east/index.html/>
            = Catalog:
            = <http://www.iec.org/events/2005/designcon_east/pdf/dceast05_catalog= .pdf>

BACKGROUND

DesignCon East (IEC)is the premier annual event for electronic = design
engineers working at the chip, board, and system levels in the = Eastern
Region of the United States. Topics of current interest to = the EIA
IBIS Open Forum are addressed at DesignCon East.

This meeting will be conducted as a formal IBIS Summit = Meeting.
Presentations are expected to be available and archived in an
electronic format, and minutes of the meeting will be issued. = Any
pending formal decisions (votes) will be announced at least two = weeks
prior to the meeting.

CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool = development,
and digital circuit design are invited to participate in the = Summit
meeting. If you plan to participate, please register with = the
information below:

   Name:
   E-mail address:
   Company:
   Telephone:

Send to:
    Beth MacKenzie <bmakenzie@sisoft.com>

CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have = experiences of
interest to the IBIS modeling community. In the past, these = have
included demonstrations of modeling techniques, explanations = of
behavioral algorithms and descriptions of difficulties = encountered in
specific applications. Of particular interest are topics = related to
model correlation, modeling building experiences and comparisons = to
other modeling methods. Presentations may be addressed to = any and
all levels of IBIS experience, from beginning to advanced.

Format of Presentation: LCD Projection with Windows = laptop.

Time: 15-30 Minutes

Electronic Archival: We request electronic versions so that = the
presentations can be archived and also made available to
non-attendees. Formats used in the past have been text, = Power Point,
Word, Postscript, and Acrobat. Electronic presentations = should be
made available by September 12, 2005 for uploading and copying to = the
presentation laptop.

If you plan a presentation, please supply

   Title:
   Presenter:
   E-mail address:
   Company:
   Telephone:

   Estimated Time:

Send this to:

Syed Huq <shuq@cisco.com>

AGENDA

The agenda includes presentations, discussions, breaks, and a = luncheon.
This will be developed as presentation proposals are = received.

The following individuals have signed up to present at the = summit
(presentation titles are tentative).

LIST OF NEARBY HOTELS

See <http:/= /www.iec.org/events/2005/designcon_east/index.html/> for = travel
directions, hotels and other information.
- -----------------------------------------------------------------

- ------_=_NextPart_001_01C593CE.65E45A68-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 28 Jul 2005 20:55:20 -0700 From: "Sam Chitwood" Subject: RE: [IBIS-Users] IBIS Question This is a multi-part message in MIME format. - ------=_NextPart_000_003F_01C593B6.AAA83B10 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hi Andy, You have to be careful trying to model to model the PDS in this way. While the lumped, low frequency loop inductance approximation of the signal nets with respect to their reference can be reasonably captured, the same cannot always be said for power and ground pins. Trying to model these structures with a partial inductance approach can be tricky, as the mutuals must be included for the partials to be meaningful. Also, depending on your current transients and frequencies of interest, a linear PDS model simply may not be appropriate. If you want to move beyond the ideal power supply regime, care must be taken to model the PDS appropriately. You'll want to include the frequency dependent coupling between the signals and the PDS as well, in order to fully characterize the SSO effects on your system. Please let me know if you have any questions on this. Thanks! Sam _____ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe Sent: Wednesday, July 27, 2005 4:18 AM To: ibis-users@eda.org Subject: [IBIS-Users] IBIS Question Hi, I have a question regarding the [Package] keyword in an IBIS file. As far as I am concerned, the RLC values in this section applied to all the I/O pins, my question is if these RLC values also applied to power and ground pins as well? If they are not applied to power and ground pins, how can we address the effects of different packages to the power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin for every single pin are not available, only package min, typ and max RLC are available) Thanks. - -Andy _____ Start your day with Yahoo! - make it your home page - ------=_NextPart_000_003F_01C593B6.AAA83B10 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi = Andy,

You have to be careful trying to = model to model the PDS in this way. While the lumped, low frequency loop inductance approximation of the signal nets with respect to their = reference can be reasonably captured, the same cannot always be said for power and = ground pins. Trying to model these structures with a partial inductance = approach can be tricky, as the mutuals must be included for the partials to be meaningful. Also, depending on your current transients and = frequencies of interest, a linear PDS model simply may not be = appropriate.

If you want to move beyond the = ideal power supply regime, care must be taken to model the PDS appropriately. = You’ll want to include the frequency dependent coupling between the signals and = the PDS as well, in order to fully characterize the SSO effects on your = system.

Please let me know if you have any questions on this. Thanks!

Sam

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe
Sent: Wednesday, July 27, = 2005 4:18 AM
To: = ibis-users@eda.org
Subject: [IBIS-Users] = IBIS Question

Hi,

I have a question regarding the [Package] keyword in = an IBIS file. As far as I am concerned, the RLC values in this section applied = to all the I/O pins, my question is if these RLC values also applied to power = and ground pins as well? If they are not applied to power and ground pins, = how can we address the effects of different packages to the power and ground = pins in an IBIS model? (If R_pin, L_pin and C_pin for every single pin are not = available, only package min, typ and max RLC are = available)

Thanks.

-Andy

Sta= rt your day with Yahoo! - make it your home page =

- ------=_NextPart_000_003F_01C593B6.AAA83B10-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 29 Jul 2005 18:02:47 -0700 From: Abdulrahman Rafiq Subject: RE: [IBIS-Users] IBIS Question This is a multi-part message in MIME format. - ------=_NextPart_000_003E_01C59467.BAA84760 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Arpad, I would tend to agree with you, as pkg parasitic should also be included for POWER and GND pins. Couldn't this be included as a requirement in the IBIS Spec? - -Abbey Abdulrahman Rafiq arafiq@ucsbalum.net _____ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Muranyi, Arpad Sent: Wednesday, July 27, 2005 8:38 AM To: ibis-users@eda.org Subject: RE: [IBIS-Users] IBIS Question Andy, The problem is that the IBIS spec doesn't spell out that the package parameters are also to be applied to power and GND pins. In my opinion they should be used for those too, but it doesn't mean that all tool vendors do it. Arpad =========================================================== _____ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe Sent: Wednesday, July 27, 2005 4:18 AM To: ibis-users@eda.org Subject: [IBIS-Users] IBIS Question Hi, I have a question regarding the [Package] keyword in an IBIS file. As far as I am concerned, the RLC values in this section applied to all the I/O pins, my question is if these RLC values also applied to power and ground pins as well? If they are not applied to power and ground pins, how can we address the effects of different packages to the power and ground pins in an IBIS model? (If R_pin, L_pin and C_pin for every single pin are not available, only package min, typ and max RLC are available) Thanks. - -Andy _____ Start your day with Yahoo! - make it your home page - ------=_NextPart_000_003E_01C59467.BAA84760 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Arpad, =

I would tend to agree with you, as = pkg parasitic should also be included for POWER and GND pins. Couldn’t this be = included as a requirement in the IBIS Spec?

-Abbey =

Abdulrahman = Rafiq

arafiq@ucsbalum.net

From: = owner-ibis-users@eda.org = [mailto:owner-ibis-users@eda.org] On Behalf Of Muranyi, Arpad
Sent: Wednesday, July 27, = 2005 8:38 AM
To: ibis-users@eda.org
Subject: RE: [IBIS-Users] = IBIS Question

Andy,

The problem is that the IBIS spec doesn't = spell out that

the package parameters are also to be applied = to power

and GND pins. In my opinion they should = be used for those

too, but it doesn't mean that all tool = vendors do it.

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

From: owner-ibis-users@eda.org = [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe
Sent: Wednesday, July 27, = 2005 4:18 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] = IBIS Question

Hi,

Thanks.

-Andy

Sta= rt your day with Yahoo! - make it your home page =

- ------=_NextPart_000_003E_01C59467.BAA84760-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sat, 30 Jul 2005 20:05:44 -0700 From: "Mirmak, Michael" Subject: [IBIS-Users] Agenda, IBIS Open Forum teleconference for August 5, 2005 IBIS Open Forum Meeting Agenda for August 5, 2005 Telephone Number Bridge Passcode 1-916-356-2663 2 493-6726 All meetings are 8:00 AM to 9:55 AM US Pacific Time. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international numbers, please contact Michael Mirmak. 8:00 Check-In, Intros, Announcements Mirmak - Intros of New IBIS Participants, Meeting Quorum Mirmak - Call for Patents Mirmak - Membership Update and Treasurer's Report Mirmak - Review of Previous Meeting's Minutes (and ARs) Mirmak July 15, 2005 Open Forum Minutes - Web Page Updates Huq - Mailing List Administration Ross - Library Update Wang - Announcements, Opens for New Issues All 8:15 Project Discussions and Subcommittee Reports International/External Progress - IEC TC47 Ross - Other activities All EIA, ANSI Approval Activities Wolff Summit Status All - DesignCon East - Asian IBIS Summit - Other Events Subcommittee Reports - Quality Haller - Model Review Green - Futures Mirmak - Cookbook Mirmak New Issues All 8:45 Technical Discussion BIRD99.1: AMS Language Versions Muranyi - Call for vote BIRD95.6: Power Integrity Analysis using IBIS Huq et al - Call for vote BIRD94.2: Clarifications on [Diff Pin] Parameters Muranyi BIRD97.2: Gate Modulation Effect Muranyi BIRD98: Gate Modulation Effect (table format) Muranyi IBISCHK4 BUG Status Angulo/Mirmak ICMCHK1 BUG Status Green/Mirmak New Technical Issues All 9:50 Wrap Up and Next Meeting Plans Mirmak - August 26, 2005 IBIS Open Forum 9:55 Sign Off |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 01 Aug 2005 09:50:23 -0700 From: Bob Ross Subject: [IBIS-Users] Asian IBIS Summit First Announcement To All: The IBIS Open Forum is holding an Asian IBIS Summit Meeting in Shenzhen, China, a major technology center near Hong Kong. This is an early initial announcement for longer term planning. Several companies listed below are cp-sponsoring this large event to be held at the luxurious Crowne Plaza Hotel. We are planning for about 200 attendees including several IBIS experts from the US. We encourage Asian technical contributions. We expect a full agenda of relevant material. Bob Ross Teraspeed Consulting Group Lance Wang Cadence Design Systems - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT FIRST CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- http://www.eda.org/pub/ibis/summits/dec05/ASIAN_IBIS_SUMMIT_CHINESE.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T M E E T I N G Time/Date: Tuesday December 6, 2005, 8:00 AM to 5:30 PM Meeting starts at 9:00 AM Location: Crowne Plaza Hotel Shenzhen 9026 Shennan Rd, OCT Shenzhen, 518053 CHINA Tel: 86-755-26936888 Fax: 86-755-26936999 E-mail: cpsz@cpsz.com http://www.ichotelsgroup.com/h/d/cp/1/en/hd/SZXNS Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Sponsors: Cadence Design Systems, Huawei Technologies, Mentor Graphics Corporation, Signal Integrity Software (SiSoft) Sigrity, Zuken and possibly others not yet confirmed. Contact us for details regarding sponsorship. Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room BACKGROUND Shenzhen, next to Hong Kong, is a special economic zone in the Peoples Republic of China with many high technology companies and many development and sales offices of foreign companies. Many sites of interest are near the conference hotel. Like the European IBIS Summit, our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translation as needed in a manner to be determined. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Comments: (Such as assistance for the travel requirements at the end) Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Lance Wang, Cadence Design Systems lwang@cadence.com SIGNUP DEADLINE: November 25, 2005 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to Asian-based presentations. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Copies: Available at the meeting for all attendees Presentation Deadline: October 30, 2005 to produce hard copies for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in a Chinese and translation to be arranged. Asian-based submissions are encouraged. AGENDA 8:15 - 9:00 Sign in, casual conversation, vendor tables 9:00 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 17:30 Presentations 17:30 - 18:30 Casual conversations, vendor tables The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Two major IBIS Committee Presentations from IBIS officers - most likely, Michael Mirmak, Intel Corporation and another selected person Several presentations on IBIS applications or modeling issues are expected from co-sponsor companies or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. A link to the conference hotel, Crown Plaza Hotel Shenzhen, is: http://www.ichotelsgroup.com/h/d/cp/1/en/hd/SZXNS Comply with your travel rules, such as indicated in the link below to China and Shenzhen. Work with your travel agent. Notify us as a sign-up comment if you need assistance. Visas, if needed, should fall in the visit/business category: http://www.travelchinaguide.com/embassy/visa.htm - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 1 Aug 2005 10:04:05 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] IBIS Question This is a multi-part message in MIME format. - ------_=_NextPart_001_01C596BB.0671BCA5 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Abbey, =20 The IBIS specification is generally trying to not require things as much as possible. For example, note that none of the I-V tables are ***required***, even though it would make sense to say that a pulldown and pullup I-V table is required for driver buffers. =20 Similarly, the capability is there for describing the package parasitics for supply pins. Whether model makers choose to provide it or simulation vendors choose to use it is really not supposed to be a concern of the specification. =20 Arpad - ------------------------------------------------------------- ________________________________ From: Abdulrahman Rafiq [mailto:arafiq786@gmail.com]=20 Sent: Friday, July 29, 2005 6:03 PM To: Muranyi, Arpad; ibis-users@eda.org Subject: RE: [IBIS-Users] IBIS Question Arpad,=20 =20 I would tend to agree with you, as pkg parasitic should also be included = for POWER and GND pins. Couldn't this be included as a requirement in = the IBIS Spec? =20 - -Abbey=20 =20 Abdulrahman Rafiq arafiq@ucsbalum.net=20 ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On = Behalf Of Muranyi, Arpad Sent: Wednesday, July 27, 2005 8:38 AM To: ibis-users@eda.org Subject: RE: [IBIS-Users] IBIS Question =20 Andy, =20 The problem is that the IBIS spec doesn't spell out that the package parameters are also to be applied to power and GND pins. In my opinion they should be used for those too, but it doesn't mean that all tool vendors do it. =20 Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D =20 ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On = Behalf Of Andy Joe Sent: Wednesday, July 27, 2005 4:18 AM To: ibis-users@eda.org Subject: [IBIS-Users] IBIS Question Hi, =20 I have a question regarding the [Package] keyword in an IBIS file. As = far as I am concerned, the RLC values in this section applied to all the = I/O pins, my question is if these RLC values also applied to power and = ground pins as well? If they are not applied to power and ground pins, = how can we address the effects of different packages to the power and = ground pins in an IBIS model? (If R_pin, L_pin and C_pin for every = single pin are not available, only package min, typ and max RLC are = available) Thanks. =20 - -Andy ________________________________ Start your day with Yahoo! - make it your home page = =20 - ------_=_NextPart_001_01C596BB.0671BCA5 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Abbey,

The IBIS specification is generally trying to = not=20 require

things as much as possible. For = example, note=20 that none

of the I-V tables are ***required***, even = though it=20 would

make sense to say that a pulldown and pullup = I-V table=20 is

required for driver = buffers.

Similarly, the capability is there for = describing the=20 package

parasitics for supply pins. Whether = model makers=20 choose to

provide it or simulation vendors choose to = use it=20 is=20 really

not supposed to be a concern of the=20 specification.

Arpad

----------------------------------------------= - ---------------

From: Abdulrahman Rafiq=20 [mailto:arafiq786@gmail.com]
Sent: Friday, July 29, 2005 6:03 = PM
To: Muranyi, Arpad; ibis-users@eda.org
Subject: = RE:=20 [IBIS-Users] IBIS Question

Arpad,=20

I would tend = to agree=20 with you, as pkg parasitic should also be included for POWER and GND = pins.=20 Couldn=92t this be included as a requirement in the IBIS=20 Spec?

-Abbey=20

Abdulrahman=20 Rafiq

arafiq@ucsbalum.net=20

From:=20 owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Muranyi, = Arpad
Sent: Wednesday, July 27, 2005 = 8:38=20 AM
To: = ibis-users@eda.org
Subject: RE: [IBIS-Users] IBIS=20 Question

Andy,

The problem is = that the IBIS=20 spec doesn't spell out that

the package = parameters are=20 also to be applied to power

and GND = pins. In my=20 opinion they should be used for those

too, but it = doesn't mean=20 that all tool vendors do it.

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

From:=20 owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Andy Joe
Sent: Wednesday, July 27, 2005 = 4:18=20 AM
To: = ibis-users@eda.org
Subject: [IBIS-Users] IBIS=20 Question

Hi,

Thanks.

-Andy

Sta= rt your day=20 with Yahoo! - make it your home page=20

- ------_=_NextPart_001_01C596BB.0671BCA5-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 2 Aug 2005 11:42:34 -0700 From: "Abril, Giovanni \(Space Technology\)" Subject: [IBIS-Users] IBIS EBD files Hello IBIS gurus, I'm trying to determine how to specify an RC path in EBD format that looks like this: J1----------------------C2---------------------------Tline------------------Rpullup | \-------R2---------------/ | C1 | | J2------- (GND) I'm not sure how to describe the Path for the parallel C2, R2. Here's what I've got: Pin J1 Fork L=0 C=2p / (this is C1 cap) Pin J2 End Fork L=0 C=4p / (this is C2 cap) L=58 L=? R=? C=? / (this would be my tline) Node U21.1 (call to my pullup model) How do I connect R2 in parallel with C2? Another fork staement? Thanks, Giovanni |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 2 Aug 2005 12:34:22 -0700 From: "Flora, Matthew" Subject: RE: [IBIS-Users] IBIS EBD files Dear Giovanni, If I remember the spec correctly: - - All capacitors in a path description are "parallel" (i.e. one side of the capacitor is connected to the path and the other side is implicitly connected to ground). I believe the only way to get a capacitor to be in series with the path is to make use of an IBIS model of a series capacitor. - - The EBD format doesn't support loops in a path. Each branch (fork) in a path is expected to end at a pin (either one of the EBD's external connector pins or at the pin of a 'Node') or to simply end. If you want a loop in the path, then again, you must use an IBIS mode of a series element. Best regards, Matthew Flora > -----Original Message----- > From: owner-ibis-users@eda.org > [mailto:owner-ibis-users@eda.org] On Behalf Of Abril, > Giovanni (Space Technology) > Sent: Tuesday, August 02, 2005 11:43 AM > To: ibis-users@eda.org > Subject: [IBIS-Users] IBIS EBD files > > Hello IBIS gurus, > > I'm trying to determine how to specify an RC path in EBD > format that looks like this: > > J1----------------------C2---------------------------Tline---- > --------------Rpullup > | \-------R2---------------/ > | > C1 > | > | > J2------- (GND) > > > I'm not sure how to describe the Path for the parallel C2, R2. > Here's what I've got: > Pin J1 > Fork > L=0 C=2p / (this is C1 cap) > Pin J2 > End Fork > L=0 C=4p / (this is C2 cap) > > L=58 L=? R=? C=? / (this would be my tline) > Node U21.1 (call to my pullup model) > > How do I connect R2 in parallel with C2? Another fork staement? > > Thanks, > Giovanni > > > |------------------------------------------------------------------ > |For help or to subscribe/unsubscribe, email majordomo@eda.org > |with just the appropriate command message(s) in the body: > | > | help > | subscribe ibis > | subscribe ibis-users > | unsubscribe ibis > | unsubscribe ibis-users > | > |or email a written request to ibis-request@eda.org. > | > |IBIS reflector archives exist under: > | > | http://www.eda.org/pub/ibis/email_archive/ Recent > | http://www.eda.org/pub/ibis/users_archive/ Recent > | http://www.eda.org/pub/ibis/email/ E-mail since 1993 > |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 04 Aug 2005 00:52:07 +0000 From: "lau yy" Subject: [IBIS-Users] RISING n FALLING

Dear ALL,

Recently, I building a model and I face aproblem. For my I/O pin, my rising and falling data show as below

[Rising Waveform]
R_fixture = 50.0000
V_fixture = 3.0000
V_fixture_min = 2.7000
V_fixture_max = 3.6000
| time           V(typ)              V(min)              V(max)
|
0.000S          1.8460V             2.0370V             1.7920V
   2.0000nS       2.1155V             2.1130V             2.2380V
   4.0000nS       2.7760V             2.4780V             3.3855V
   6.0000nS       2.9727V             2.6540V             3.5830V
   8.0000nS       2.9970V             2.6930V             3.5985V
10.0000nS       2.9990V             2.6975V             3.5995V
12.0000nS       2.9990V             2.6990V             3.6000V
14.0000nS       3.0000V             2.6990V             3.6000V

Q1 : It looks like not starting from around 0V. And same as Falling, it wont fall lower than 1.8V. Is that means my model wrong or the input/output voltage range for the product is small?

Q2: My pullup and pulldown data is started from 0A. But it pass the ibischk3.

[Pulldown]
| voltage     I(typ)              I(min)              I(max)
|
-3.0000       0.000A              0.000A              0.000A
-2.8000       0.000A              0.000A              0.000A
-2.6000       0.000A              0.000A              0.000A

Thanks

rdgs

yylau

|------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 3 Aug 2005 18:36:48 -0700 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] RISING n FALLING This is a multi-part message in MIME format. - ------_=_NextPart_001_01C59894.FB51ACAE Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable YY, =20 Thank you for your message. =20 =20 To respond to your first question, why do you expect to a rising waveform table using a Vcc-terminated load to start at 0 V? For a typical push-pull buffer structure, a [Rising Waveform] into a load to Vcc (assuming your Vcc =3D 3.0 V) characterizes the *pulldown turning off.* The [Rising Waveform] table in this case should end at the termination voltage (which yours does) and start at a voltage determined by the voltage divider between the Ron of your buffer's pulldown and the R_fixture load.=20 =20 If you want a [Rising Waveform] which starts at 0 V, look at or generate a [Rising Waveform] table which uses a ground-terminated load. Such a table would characterize the *pullup turning on.* =20 Your second question is much harder to answer without additional data. Are the [Pulldown] and [Pullup] tables *entirely* zero? If so, did you enable your buffer's outputs to drive when you collected the data? If not, do your [POWER Clamp] and [GND Clamp] tables include valid data? Were the clamps included in your circuit when you collected the [Pulldown] and [Pullup] data? Did you perform any clamp subtraction on your [Pullup] and [Pulldown] data before including it in your IBIS file? I would advise checking your circuit simulation setup to ensure that it makes sense for the data you are trying to collect. =20 - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of lau yy Sent: Wednesday, August 03, 2005 5:52 PM To: ibis-users@eda.org Subject: [IBIS-Users] RISING n FALLING Dear ALL, =20 Recently, I building a model and I face aproblem. For my I/O pin, my rising and falling data show as below =20 [Rising Waveform] R_fixture =3D 50.0000 V_fixture =3D 3.0000 V_fixture_min =3D 2.7000 V_fixture_max =3D 3.6000 | time V(typ) V(min) V(max) | 0.000S 1.8460V 2.0370V 1.7920V 2.0000nS 2.1155V 2.1130V 2.2380V 4.0000nS 2.7760V 2.4780V 3.3855V 6.0000nS 2.9727V 2.6540V 3.5830V 8.0000nS 2.9970V 2.6930V 3.5985V 10.0000nS 2.9990V 2.6975V 3.5995V 12.0000nS 2.9990V 2.6990V 3.6000V 14.0000nS 3.0000V 2.6990V 3.6000V =20 Q1 : It looks like not starting from around 0V. And same as Falling, it wont fall lower than 1.8V. Is that means my model wrong or the input/output voltage range for the product is small?=20 =20 Q2: My pullup and pulldown data is started from 0A. But it pass the ibischk3. =20 [Pulldown] | voltage I(typ) I(min) I(max) | -3.0000 0.000A 0.000A 0.000A -2.8000 0.000A 0.000A 0.000A -2.6000 0.000A 0.000A 0.000A =20 Thanks =20 =20 rdgs yylau |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993=20 - ------_=_NextPart_001_01C59894.FB51ACAE Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

YY,

Thank you for your message. =

To respond to your first question, why do you = expect=20 to a rising waveform table using a Vcc-terminated load to = start=20 at 0 V? For a typical push-pull buffer structure, a [Rising = Waveform] into=20 a load to Vcc (assuming your Vcc =3D 3.0 V) characterizes the *pulldown = turning=20 off.* The [Rising Waveform] table in this case should end at = the=20 termination voltage (which yours does) and start at a voltage = determined by=20 the voltage divider between the Ron of your buffer's pulldown and = the=20 R_fixture load.

If you want a [Rising Waveform] which starts at = 0 V, look=20 at or generate a [Rising Waveform] table which uses a=20 ground-terminated load. Such a table would characterize = the=20 *pullup turning on.*

Your second question is much harder to answer = without=20 additional data. Are the [Pulldown] and [Pullup] tables *entirely* = zero? If so, did you enable your buffer's outputs to drive when = you=20 collected the data? If not, do your [POWER Clamp] and [GND Clamp] = tables=20 include valid data? Were the clamps included in your circuit when = you=20 collected the [Pulldown] and [Pullup] data? Did you perform any = clamp=20 subtraction on your [Pullup] and [Pulldown] data before including it in = your=20 IBIS file? I would advise checking your circuit simulation = setup to=20 ensure that it makes sense for the data you are trying to=20 collect.

- Michael Mirmak

Intel Corp.

Chair, EIA IBIS Open = Forum

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of lau = yy
Sent:=20 Wednesday, August 03, 2005 5:52 PM
To:=20 ibis-users@eda.org
Subject: [IBIS-Users] RISING n=20 FALLING

Dear ALL,

Recently, I building a model and I face aproblem. For = my I/O pin,=20 my rising and falling data show as below

[Rising Waveform]
R_fixture =3D 50.0000
V_fixture = =3D=20 3.0000
V_fixture_min =3D 2.7000
V_fixture_max =3D 3.6000
|=20 time          =20 V(typ)           &= nbsp; =20 V(min)           &= nbsp; =20 V(max)
|
=20 0.000S         =20 1.8460V           = =20 2.0370V           = =20 1.7920V
   2.0000nS      =20 2.1155V           = =20 2.1130V           = =20 2.2380V
   4.0000nS      =20 2.7760V           = =20 2.4780V           = =20 3.3855V
   6.0000nS      =20 2.9727V           = =20 2.6540V           = =20 3.5830V
   8.0000nS      =20 2.9970V           = =20 2.6930V           = =20 3.5985V
10.0000nS      =20 2.9990V           = =20 2.6975V           = =20 3.5995V
12.0000nS      =20 2.9990V           = =20 2.6990V           = =20 3.6000V
14.0000nS      =20 3.0000V           = =20 2.6990V           = =20 3.6000V

Q1 : It looks like not starting from around 0V. And = same as=20 Falling, it wont fall lower than 1.8V. Is that means my model wrong = or the=20 input/output voltage range for the product is small?

Q2: My pullup and pulldown data is started from 0A. = But it=20 pass the ibischk3.

[Pulldown]
| voltage    =20 I(typ)           &= nbsp; =20 I(min)           &= nbsp; =20 I(max)
|
-3.0000      =20 0.000A           &= nbsp; =20 0.000A           &= nbsp; =20 0.000A
-2.8000      =20 0.000A           &= nbsp; =20 0.000A           &= nbsp; =20 0.000A
-2.6000      =20 0.000A           &= nbsp; =20 0.000A           &= nbsp; =20 0.000A

Thanks

rdgs

yylau