From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #78 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Wednesday, February 8 2006 Volume 01 : Number 078 ---------------------------------------------------------------------- Date: Tue, 7 Feb 2006 09:45:59 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] RE: [IBIS] To capture the delay variation with change in IO voltage This is a multi-part message in MIME format. - ------_=_NextPart_001_01C62C0E.5B37BE8B Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Venu, =20 The IBIS model will only partially for the Vcc variations. Here is how: =20 If you lower the supply voltage, the origin of the pullup IV curve will go down to that lower voltage. So the pullup will pull up to a lower voltage. =20 However, in real transistor circuits, this lower supply voltage would also reduce the IV curve size, because the Vgs voltage is smaller than at the normal supply voltage. This effect is usually called the "gate modulation effect" and is not reproduced by IBIS simulators to my knowledge. We are working on BIRD98 to describe this effect for IBIS models. =20 http://www.vhdl.org/pub/ibis/birds/bird98.txt =20 There may be two reasons for being interested in supply voltage variations. =20 1) Static DC characteristics of the buffer, i.e. how much will its strength change if we change the supply voltage. If you need this, you can generate several IV curves at different supply voltages and make a [Model] for each set. You can then use the [Model Selector] keyword to allow the tool to select the one you want to simulate with. =20 2) Dynamic noise simulations, i.e. you want to find out how the buffer will "degrade" its switching performance when there is noise in the supply voltage during its switching. This is a more difficult task, and IBIS is not doing too well on it. We have BIRD95 and BIRD98 as Lynne mentioned it already to solve this deficiency in the IBIS world. However, as usual, if you write your own models in the *-AMS languages, you can describe these behaviors to your heart's content without having to wait for BIRD95 and BIRD98. =20 I hope this will shed some light on your questions. =20 Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =20 =20 ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On = Behalf Of Lynne D. Green Sent: Tuesday, February 07, 2006 8:07 AM To: 'Ummalaneni, Venu Babu (Venu)'; ibis-users@eda.org; ibis@eda.org Cc: 'Kotikalapudi, Shiva Kumar (Shiva)' Subject: [IBIS-Users] RE: [IBIS] To capture the delay variation with = change in IO voltage=20 Hello, Venu, =20 Problems modeling delay changes with supply changes is a known "feature" = of IBIS. =20 The IBIS Open Forum is actively working on this. BIRDs 95.6, 97.2, and = 98 are part of the solution. BIRD 95.6 was recently approved. =20 User input is important in addressing timing issues. You would be = welcome to attend the IBIS Open Forum and IBIS Futures meetings. For = more info on these meetings (agenda, teleconference passcodes) please = contact the IBIS chair, Michael Mirmak (michael.mirmak@intel.com). =20 Best regards, Lynne ________________________________ From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of = Ummalaneni, Venu Babu (Venu) Sent: Tuesday, February 07, 2006 2:57 AM To: ibis-users@eda.org; ibis@eda.org Cc: Kotikalapudi, Shiva Kumar (Shiva) Subject: [IBIS] To capture the delay variation with change in IO = voltage=20 =09 =09 Hi Gurus, I have generated an IBIS model using rated IO voltage(1.5V) and = simulated it at the same IO voltage(1.5V); the matching between=20 hspice vs IBIS is very good (1st waveform in attached *.pdf). When I = simulated the same IBIS model with reduced IO voltage (1.1v),=20 the matching is poor (2nd waveform) between IBIS and hspice models. = IBIS model is not able to capture the delay variation with supply = voltage variation. Next, I have re-generated the IBIS model with reduced IO voltage(1.1V) = and the simulation at this voltage(1.1V) gives good matching=20 (3rd waveform) between IBIS and hspice models. Means IBIS model can not be used to see the variation in delay with the = ripples on IO voltage? Is it known limitation? Are there any techniques/methods exist to build an IBIS model, which = can be used to simulate at an IO voltage lesser/greater than the voltage at which it is build? Here, I am attaching a PDF of the waveforms I observed. Could some one help me in clarifying the above queries? Thanks in advance. Best Regards, Venu <>=20 - ------_=_NextPart_001_01C62C0E.5B37BE8B Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To capture the delay variation with change in IO = voltage
Venu,
 
The IBIS model will only partially for the = Vcc=20 variations.
Here is how:
 
If you lower the supply voltage, the origin = of the=20 pullup
IV curve will go down to that lower = voltage.  So=20 the pullup
will pull up to a lower = voltage.
 
However, in real transistor circuits, this = lower=20 supply
voltage would also reduce the IV curve size, = because=20 the
Vgs voltage is smaller than at the normal = supply=20 voltage.
This effect is usually called the "gate = modulation=20 effect"
and is not reproduced by IBIS simulators = to my=20 knowledge.
We are working on BIRD98 to describe this = effect for=20 IBIS
models.
 
http://www.vhdl.or= g/pub/ibis/birds/bird98.txt
 
There may be two reasons for being interested = in=20 supply
voltage variations.
 
1)  Static DC characteristics of the = buffer, i.e.=20 how
much will its strength change if we change = the=20 supply
voltage.  If you need this, you can = generate=20 several IV
curves at different supply voltages and make = a=20 [Model]
for each set.  You can then use the = [Model=20 Selector]
keyword to allow the tool to select the one = you=20 want
to simulate with.
 
2)  Dynamic noise simulations, i.e. you = want to=20 find
out how the buffer will "degrade" its = switching=20 performance
when there is noise in the supply voltage = during=20 its
switching.  This is a more difficult = task, and=20 IBIS is
not doing too well on it.  We have = BIRD95 and=20 BIRD98 as
Lynne mentioned it already to solve = this=20 deficiency in
the IBIS world.  However, as usual, if = you write=20 your
own models in the *-AMS languages, you can = describe=20 these
behaviors to your heart's content without = having to=20 wait
for BIRD95 and BIRD98.
 
I hope this will shed some light on your=20 questions.
 
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
 
 

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Lynne D.=20 Green
Sent: Tuesday, February 07, 2006 8:07 AM
To:=20 'Ummalaneni, Venu Babu (Venu)'; ibis-users@eda.org; = ibis@eda.org
Cc:=20 'Kotikalapudi, Shiva Kumar (Shiva)'
Subject: [IBIS-Users] RE: = [IBIS]=20 To capture the delay variation with change in IO voltage =

Hello, Venu,
 
Problems modeling delay changes = with supply=20 changes is a known "feature" of IBIS.
 
The IBIS Open Forum is actively working on = this. =20 BIRDs 95.6, 97.2, and 98 are part of the solution.  BIRD 95.6 was = recently=20 approved.
 
User input is important in addressing timing = issues. =20 You would be welcome to attend the IBIS Open Forum and IBIS Futures=20 meetings.  For more info on these meetings (agenda, teleconference=20 passcodes) please contact the IBIS chair, Michael Mirmak (michael.mirmak@intel.com).
 
Best regards,
Lynne

From: owner-ibis@eda.org=20 [mailto:owner-ibis@eda.org] On Behalf Of Ummalaneni, Venu Babu=20 (Venu)
Sent: Tuesday, February 07, 2006 2:57 = AM
To:=20 ibis-users@eda.org; ibis@eda.org
Cc: Kotikalapudi, Shiva = Kumar=20 (Shiva)
Subject: [IBIS] To capture the delay variation with = change=20 in IO voltage

Hi=20 Gurus,

I=20 have generated an IBIS model using rated IO = voltage(1.5V) = and simulated it at the same=20 IO voltage(1.5V);=20 the matching between

hspice vs=20 IBIS is very good (1st waveform in = attached=20 *.pdf). When I=20 simulated the same = IBIS model with=20 reduced IO = voltage (1.1v),

the=20 matching is poor (2nd waveform) between IBIS and = hspice models. IBIS model = is not able to=20 capture = the delay=20 variation with supply voltage variation.

Next, I have re-generated the IBIS = model with=20 reduced IO = voltage(1.1V)=20 and the = simulation at this voltage(1.1V) gives good = matching =

(3rd = waveform)=20 between IBIS and hspice models.

Means IBIS model can not be = used to=20 see=20 the variation in=20 delay with the ripples on IO voltage? = Is it known = limitation?

Are there any = techniques/methods exist = to build an IBIS model,=20 which can be used to simulate at=20 an IO

voltage=20 lesser/greater than the voltage = at which it is = build?

Here, I=20 am attaching a PDF of the waveforms I=20 observed.

Could=20 some one = help me in clarifying the above queries?

Thanks in=20 advance.

Best=20 Regards,

Venu

<<ibis_hspice_delay.pdf>>

- ------_=_NextPart_001_01C62C0E.5B37BE8B-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 7 Feb 2006 10:15:49 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] Capacitance and transition time Sorry for the late reply, but things were a bit hectic. However, this is an important question and I would like to reply to it. Unfortunately I need to disagree with the previous replies. I have seen several cases when IBIS models do not perform well with capacitive loads. Especially when the capacitive load comes as a series DC blocking (decoupling) capacitance placed in the path of the signal. Searching for the reasons, I realized that this may be inherent in the basic 2-equations 2-unknowns algorithm (most) tools may be using(?). (I don't know for fact what the algorithms of various tools are, so I can't answer that question). This algorithm uses Kirchoff's and Ohm's law to convert the V-t curves into k-t curves which are ultimately used to scale the static I-V curves in the model. The problem with this is that the equations of reactive loads (C and L) include dV/dt and dI/dt, which is missing from this algorithm all together. Now, if the circuit is such that the dI/dt and dV/dt components are small with respect to the Ohm's law relations, you will see relatively accurate results. However, if the reactive elements dominate the voltage and current relationships, chances are that your simulation results will not be very accurate. Interestingly, T-line loads do not fall into the category of reactive loads, they look very much like resistive loads, so we do not need to be worried about those. I will have a short presentation on this in the upcoming IBIS Summit meeting, which will be uploaded to the IBIS web site shortly. This will be more like a problem statement only, but I hope that this will put things in perspective. Arpad - ---------------------------------------------------------- - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Hazem Mahmoud Hegazy Sent: Tuesday, January 31, 2006 1:25 AM To: IBIS-USERS Subject: Re: [IBIS-Users] Capacitance and transition time I agree with Tom that IBIS will produce very good resluts on different capacitive loads. In some cases, usually LVDS drivers(due to their high sensitivity to even resistive load), we might face a problem but not very likely. BR, Hazem On Mon, 30 Jan 2006 22:50:21 -0500 "Andrew Ingraham" wrote: >In normal usage, the actual load (i.e., traces and other >devices) connected >to an output device creates a rather complex, frequency >dependent load. >It's highly unlikely that the output device was >characterized with that kind >of load. > >While there may not be a guarantee, one should expect >that an IBIS model >would produce reasonably good results with such complex >loads as well as >simple R/C loads (with not unreasonable values), even >though they weren't >use to generate the VT curves. > >Anyway, most VT curves are established with resistive >loads (zero >capacitance), which "never" happens in practice. The VT >curves may be used >only to "calibrate" the simulator's representation of the >ouput device, not >to generate actual waveforms. > >Regards, >Andy > > >> A coworker wants to simulate what affect connecting >> different capacitors to the output pin of a device >> would have on its transtion time. He doesn't have >> access to spice models and he asked me if he could use >> IBIS models. I told him that since the models are >> characterized under a given load, changing that load >> in simulation may not give him very accurate results. >> Was I correct, or will the simulator use the values of >> the IV curves and test fixture to accurately skew the >> rise and fall times specified in the VT curves? > >|------------------------------------------------------------------ >|For help or to subscribe/unsubscribe, email >majordomo@eda.org >|with just the appropriate command message(s) in the >body: >| >| help >| subscribe ibis different> >| subscribe ibis-users different> >| unsubscribe ibis different> >| unsubscribe ibis-users different> >| >|or email a written request to ibis-request@eda.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda.org/pub/ibis/email_archive/ Recent >| http://www.eda.org/pub/ibis/users_archive/ Recent >| http://www.eda.org/pub/ibis/email/ E-mail >since 1993 Hazem Hegazy$IBIS modeling manager$Quality ___________________________________________________________________________ Your email is totally virus secure by MenaNet AntiVirus. Tired of spam? Get advanced, send spam emails to MenaNet.AntiSpam@menanet.net to be protected by MenaNet AntiSpam. http://www.menanet.net |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 8 Feb 2006 08:30:57 -0800 From: "Abdulrahman Rafiq" Subject: [IBIS-Users] Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models This is a multi-part message in MIME format. - ------=_NextPart_000_002E_01C62C89.FC5246B0 Content-Type: multipart/alternative; boundary="----=_NextPart_001_002F_01C62C89.FC5246B0" - ------=_NextPart_001_002F_01C62C89.FC5246B0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Published by EDACafe.com on 2/7/06, text of article below. http://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews &articleid=241206 Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models WILSONVILLE, Ore.-(BUSINESS WIRE)-Feb. 7, 2006- Mentor Graphics Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the release of the ICX(R) and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation I/O controller hub. This kit is the first to utilize Intel's new IBIS 4.1 and IEEE 1076.1 standard VHDL-AMS ( http://www.eigroup.org/ibis/) models. These analog/mixed-signal (AMS) models have been developed by Intel for the I/O controller hub portion of their next generation chipset, codenamed "Broadwater." These AMS signal integrity (SI) models also provide significant speed and accuracy benefits over traditional SPICE and IBIS modeling techniques. And being wrapped in IBIS syntax, these new models are as easy to import and use as traditional IBIS models. "Mentor Graphics is pleased to support these new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president and general manager, Systems Design Division, Mentor Graphics. "We are committed to open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and believe that they provide the flexibility and standardization required to cover modeling requirements now and into the future." Traditional IBIS constructs cannot accurately model today's advanced I/O buffers. As a result, many designers and engineers of PCBs performing SI analysis are forced to use complex transistor-level SPICE models. These models run slowly, often suffer convergence problems, and are typically distributed in a proprietary format. On the other hand, the IBIS 4.1 AMS models offer the benefit of superior performance and improved accuracy, with no convergence issues, in an IEEE standard format. "Intel is pleased to support the new IBIS 4.1 standard for signal integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, application engineering director of Intel's Business Client Group. "We are confident our customers will find the increased speed, accuracy, and flexibility of the IBIS 4.1 AMS models to be a significant benefit in their high-speed PCB design process." The Mentor ICX and ICX Pro kits for Intel's next generation I/O controller hub includes a complete IBIS model for the I/O controller hub, including AMS models for the PCI Express, Serial ATA and USB2 interfaces, as well as IBIS-formatted S-parameter models for the package pins and connectors, and traditional IBIS models for the other lower-speed interfaces. The ICX kit also includes a custom menu for configuring device and test conditions, and a complete reference design layout for Intel's next generation chipset imported into the tool ready for SI analysis. The next generation I/O controller hub high-speed receiver models also include a novel application of AMS which measures and plots eye-opening values in real-time while the simulation is in progress. The ICX and ICX Pro design kits is are available through Mentor and its local sales force. Customers can contact Mentor Graphics Corporation at designkit_info@mentor.com for more information. The Intel IBIS models and reference designs are available through Intel. Customers can contact their local Intel sales office for more information. About ICX and ICX Pro Mentor Graphics' ICX solution combines the electrical and physical aspects of a design, providing an integrated design and verification environment for signal integrity and timing analysis during layout. This environment uses true electrical rules to drive the placement and routing, as well as verification, of high-speed boards, ensuring electrically-correct designs the first time. ICX Pro Explorer provides a schematic-based what-if signal integrity environment, with extensive capabilities for pre-layout simulation, including sweeps. Both solutions are built using the ICX simulation technology. Through its support of IBIS 4.1, this simulation environment provides the ability to mix and match models of various formats (IBIS, SPICE, AMS). This gives designers and engineers the ultimate flexibility in terms of model support. About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 4000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/. Mentor Graphics and ICX are registered trademarks and ICX Pro is a trademark of Mentor Graphics Corporation. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. All other company or product names are the registered trademarks or trademarks of their respective owners. _____ Contact: Mentor Graphics Debra Layton, 720-494-1043 Email Contact Suzanne Graham, 503-685-7789 Email Contact Click here for Internet Business Systems Copyright 1994 - 2006, Internet Business Systems, Inc. 1-888-44-WEB-44 --- Contact us, or visit our other sites: AECCafe DCCCafe TechJobsCafe GISCafe MCADCafe NanoTechCafe PCBCafe Privacy Policy - --- Abdulrahman Rafiq (Hardware/IO Interconnect Modeling Engineer) ASIPD/SIPD/ISBU/DSSTG/Cisco Systems, Inc Phone : +1-408-527-5540 Fax : +1-408-526-6603 Pager : +1-888-646-7881 Email : arafiq@cisco.com Epage : arafiq@epage.cisco.com GrpURL : http://wwwin-sipd.cisco.cm RefURL : http://www.eigroup.org/ibis/ - ------=_NextPart_001_002F_01C62C89.FC5246B0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Published by EDACafe.com on 2/7/06, text of article=20 below. 
http://www10.edacafe.com/nbc/articles/vi= ew_article.php?section=3DCorpNews&articleid=3D241206
 
Mentor Graphics Announces Support for = Intel's IBIS=20 4.1 AMS Signal Integrity Models


WILSONVILLE, Ore.—(BUSINESS = WIRE)—Feb. 7,=20 2006— Mentor Graphics Corporation (Nasdaq:MENT), the market and technology leader in = printed=20 circuit board (PCB) design solutions, today announced the release of the = ICX(R)=20 and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation = I/O=20 controller hub. This kit is the first to utilize Intel's new IBIS 4.1 = and IEEE=20 1076.1 standard VHDL-AMS (<= FONT=20 color=3D#0033cc>http://www.eigroup.org/ibis/) models. These=20 analog/mixed-signal (AMS) models have been developed by Intel for the = I/O=20 controller hub portion of their next generation chipset, codenamed = "Broadwater."=20 These AMS signal integrity (SI) models also provide significant speed = and=20 accuracy benefits over traditional SPICE and IBIS modeling techniques. = And being=20 wrapped in IBIS syntax, these new models are as easy to import and use = as=20 traditional IBIS models.

"Mentor Graphics is pleased to support = these=20 new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president = and=20 general manager, Systems Design Division, Mentor Graphics. "We are = committed to=20 open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and = believe=20 that they provide the flexibility and standardization required to cover = modeling=20 requirements now and into the future."

Traditional IBIS = constructs=20 cannot accurately model today's advanced I/O buffers. As a result, many=20 designers and engineers of PCBs performing SI analysis are forced to use = complex=20 transistor-level SPICE models. These models run slowly, often suffer = convergence=20 problems, and are typically distributed in a proprietary format. On the = other=20 hand, the IBIS 4.1 AMS models offer the benefit of superior performance = and=20 improved accuracy, with no convergence issues, in an IEEE standard = format.=20

"Intel is pleased to support the new IBIS 4.1 standard for = signal=20 integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, = application engineering director of Intel's Business Client Group. "We = are=20 confident our customers will find the increased speed, accuracy, and = flexibility=20 of the IBIS 4.1 AMS models to be a significant benefit in their = high-speed PCB=20 design process."

The Mentor ICX and ICX Pro kits for Intel's = next=20 generation I/O controller hub includes a complete IBIS model for the I/O = controller hub, including AMS models for the PCI Express, Serial ATA and = USB2=20 interfaces, as well as IBIS-formatted S-parameter models for the package = pins=20 and connectors, and traditional IBIS models for the other lower-speed=20 interfaces. The ICX kit also includes a custom menu for configuring = device and=20 test conditions, and a complete reference design layout for Intel's next = generation chipset imported into the tool ready for SI analysis. The = next=20 generation I/O controller hub high-speed receiver models also include a = novel=20 application of AMS which measures and plots eye-opening values in = real-time=20 while the simulation is in progress.

The ICX and ICX Pro design = kits is=20 are available through Mentor and its local sales force. Customers can = contact=20 Mentor Graphics Corporation at designkit_info@mentor.com for more = information.=20 The Intel IBIS models and reference designs are available through Intel. = Customers can contact their local Intel sales office for more = information.=20

About ICX and ICX Pro

Mentor Graphics' ICX solution = combines the=20 electrical and physical aspects of a design, providing an integrated = design and=20 verification environment for signal integrity and timing analysis during = layout.=20 This environment uses true electrical rules to drive the placement and = routing,=20 as well as verification, of high-speed boards, ensuring = electrically-correct=20 designs the first time. ICX Pro Explorer provides a schematic-based = what-if=20 signal integrity environment, with extensive capabilities for pre-layout = simulation, including sweeps. Both solutions are built using the ICX = simulation=20 technology. Through its support of IBIS 4.1, this simulation environment = provides the ability to mix and match models of various formats (IBIS, = SPICE,=20 AMS). This gives designers and engineers the ultimate flexibility in = terms of=20 model support.

About Mentor Graphics

Mentor Graphics = Corporation=20 (Nasdaq:MENT) is a world leader in electronic = hardware and=20 software design solutions, providing products, consulting services and=20 award-winning support for the world's most successful electronics and=20 semiconductor companies. Established in 1981, the company reported = revenues over=20 the last 12 months of about $700 million and employs approximately 4000 = people=20 worldwide. Corporate headquarters are located at 8005 S.W. Boeckman = Road,=20 Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located = at 1001=20 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: = http://www.mentor.com/.

Mentor = Graphics and ICX=20 are registered trademarks and ICX Pro is a trademark of Mentor Graphics=20 Corporation. Intel is a trademark or registered trademark of Intel = Corporation=20 or its subsidiaries in the United States and other countries. All other = company=20 or product names are the registered trademarks or trademarks of their = respective=20 owners.


Contact: 
Mentor Graphics
Debra Layton, 720-494-1043
=
Email Contact
Suzanne Graham, 503-685-7789
Email =
Contact
 
 Copyright 1994 - 2006, Internet Business Systems, =
Inc.
1-888-44-WEB-44 --- Contact us, or visit our other sites:
AECCafe  DCCCafe  TechJobsCafe  GISCafe  MCADCafe  NanoTechCafe  PCBCafe   
 Privacy =
Policy
 
---
Abdulrahman Rafiq =
(Hardware/IO Interconnect = Modeling=20 Engineer)
ASIPD/SIPD/ISBU/DSSTG/Cisco Systems,=20 Inc
Phone  :=20 +1-408-527-5540
Fax      :=20 +1-408-526-6603
Pager   :=20 +1-888-646-7881
Email    : = arafiq@cisco.com
Epage   : arafiq@epage.cisco.com =
GrpURL : http://wwwin-sipd.cisco.cm =
RefURL  : http://www.eigroup.org/ibis/
 
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------=_NextPart_000_002E_01C62C89.FC5246B0-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 8 Feb 2006 09:39:50 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] RE: [IBIS] To capture the delay variation with change in IO voltage This is a multi-part message in MIME format. - ------_=_NextPart_001_01C62CD6.A9EB7F0B Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Venu, =20 I just remembered something that I forgot to mention in my previous reply. =20 This is not an IBIS parameter, but HSPICE does have something in the B-element which tries to imitate the gate modulation effect. Look at the last two items on this list: =20 =20 B_IO nd_pu nd_pd nd_out nd_in nd_en V_out_of_in [nd_pc nd_gc] + file=3D'file_name' model=3D'model_name' + [typ=3D{typ|min|max|fast|slow}] [power=3D{on|off}] + [buffer=3D{3|input_output}] + [xv_pu=3Dstate_pu] [xv_pd=3Dstate_pd] + [interpol=3D{1|2}] + [ramp_fwf=3D{2|1|0}] [ramp_rwf=3D{2|1|0}] + [fwf_tune=3Dfwf_tune_value] [rwf_tune=3Drwf_tune_value] + [nowarn] + [c_com_pu=3Dc_com_pu_value] + [c_com_pd=3Dc_com_pd_value] + [c_com_pc=3Dc_com_pc_value] + [c_com_gc=3Dc_com_gc_value] + [pu_scal=3Dpu_scal_value] + [pd_scal=3Dpd_scal_value] + [pc_scal=3Dpc_scal_value] + [gc_scal=3Dgc_scal_value] + [rwf_scal=3Drwf_scal_value] + [fwf_scal=3Dfwf_scal_value] + [spu_scal=3Dspu_scal_value] + [spd_scal=3Dspd_scal_value] =20 =20 They are scaling coefficients which scale the IV curves based on the change in the supply voltage. They are not documented too well in the HSPICE manuals, but as far as I remember they will do the following: =20 If you have a value of 1, the IV curve will be scaled by the same percentage as the supply deviates from the value given by the IBIS model. For example, a 5V buffer getting 4.5 volts means a 10% change down, so the IV curve will be reduced by 10%. If you give 0.5 for these parameters, the same 10% change in the supply will result in 5% change in the IV curve. A zero will result in no change in the IV curves, a 2 will result a 20% change, and so on... As far as I remember, negative values will also work reversing the relationship (lower supplies will increase the IV curves). =20 I hope this helps. =20 Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 ________________________________ From: Ummalaneni, Venu Babu (Venu) [mailto:venubabu@agere.com]=20 Sent: Wednesday, February 08, 2006 1:51 AM To: Muranyi, Arpad Cc: Kotikalapudi, Shiva Kumar (Shiva); Patel, Nirav (Nirav) Subject: RE: [IBIS-Users] RE: [IBIS] To capture the delay variation with = change in IO voltage=20 Arpad, =20 It is good to know that IBIS forum is actively working on these = features. Thank you very much for the very detailed response and pointers. =20 Best Regards, Venu =20 =20 - -----Original Message----- From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of = Muranyi, Arpad Sent: Tuesday, February 07, 2006 11:16 PM To: ibis-users@eda.org; ibis@eda.org Subject: RE: [IBIS-Users] RE: [IBIS] To capture the delay variation with = change in IO voltage=20 =20 Venu, =20 The IBIS model will only partially for the Vcc variations. Here is how: =20 If you lower the supply voltage, the origin of the pullup IV curve will go down to that lower voltage. So the pullup will pull up to a lower voltage. =20 However, in real transistor circuits, this lower supply voltage would also reduce the IV curve size, because the Vgs voltage is smaller than at the normal supply voltage. This effect is usually called the "gate modulation effect" and is not reproduced by IBIS simulators to my knowledge. We are working on BIRD98 to describe this effect for IBIS models. =20 http://www.vhdl.org/pub/ibis/birds/bird98.txt =20 There may be two reasons for being interested in supply voltage variations. =20 1) Static DC characteristics of the buffer, i.e. how much will its strength change if we change the supply voltage. If you need this, you can generate several IV curves at different supply voltages and make a [Model] for each set. You can then use the [Model Selector] keyword to allow the tool to select the one you want to simulate with. =20 2) Dynamic noise simulations, i.e. you want to find out how the buffer will "degrade" its switching performance when there is noise in the supply voltage during its switching. This is a more difficult task, and IBIS is not doing too well on it. We have BIRD95 and BIRD98 as Lynne mentioned it already to solve this deficiency in the IBIS world. However, as usual, if you write your own models in the *-AMS languages, you can describe these behaviors to your heart's content without having to wait for BIRD95 and BIRD98. =20 I hope this will shed some light on your questions. =20 Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D - ------_=_NextPart_001_01C62CD6.A9EB7F0B Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To capture the delay variation with change in IO = voltage
Venu,
 
I just remembered something that I forgot to = mention
in my previous reply.
 
This is not an IBIS parameter, but HSPICE does have=20 something
in the B-element which tries to imitate the gate=20 modulation
effect.  Look at the last two items on this=20 list:
 
 
B_IO nd_pu nd_pd nd_out nd_in nd_en V_out_of_in [nd_pc = nd_gc]
+=20 file=3D'file_name' model=3D'model_name'
+ = [typ=3D{typ|min|max|fast|slow}]=20 [power=3D{on|off}]
+ [buffer=3D{3|input_output}]
+ = [xv_pu=3Dstate_pu]=20 [xv_pd=3Dstate_pd]
+ [interpol=3D{1|2}]
+ [ramp_fwf=3D{2|1|0}]=20 [ramp_rwf=3D{2|1|0}]
+ [fwf_tune=3Dfwf_tune_value] = [rwf_tune=3Drwf_tune_value]
+=20 [nowarn]
+ [c_com_pu=3Dc_com_pu_value]
+ = [c_com_pd=3Dc_com_pd_value]
+=20 [c_com_pc=3Dc_com_pc_value]
+ [c_com_gc=3Dc_com_gc_value]
+=20 [pu_scal=3Dpu_scal_value]
+ [pd_scal=3Dpd_scal_value]
+=20 [pc_scal=3Dpc_scal_value]
+ [gc_scal=3Dgc_scal_value]
+=20 [rwf_scal=3Drwf_scal_value]
+ [fwf_scal=3Dfwf_scal_value]
+=20 [spu_scal=3Dspu_scal_value]
+ = [spd_scal=3Dspd_scal_value]
 
 
They are scaling coefficients which scale the IV curves=20 based
on the change in the supply voltage.  They are not=20 documented
too well in the HSPICE manuals, but as far as I remember=20 they
will do the following:
 
If you have a value of 1, the IV curve will be scaled by=20 the
same percentage as the supply deviates from the value=20 given
by the IBIS model.  For example, a 5V buffer getting 4.5=20 volts
means a 10% change down, so the IV curve will be reduced by=20 10%.
If you give 0.5 for these parameters, the same 10% change in=20 the
supply will result in 5% change in the IV curve.  A zero=20 will
result in no change in the IV curves, a 2 will result a=20 20%
change, and so on...  As far as I remember, = negative=20 values will
also work reversing the relationship (lower supplies will=20 increase
the IV curves).
 
I hope this=20 helps.
 
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

 
From: Ummalaneni, Venu Babu (Venu)=20 [mailto:venubabu@agere.com]
Sent: Wednesday, February 08, = 2006 1:51=20 AM
To: Muranyi, Arpad
Cc: Kotikalapudi, Shiva Kumar = (Shiva);=20 Patel, Nirav (Nirav)
Subject: RE: [IBIS-Users] RE: [IBIS] To = capture=20 the delay variation with change in IO voltage

Arpad,

 

It = is good to=20 know that IBIS forum is actively working on these = features.

Thank you very=20 much for the very detailed response and pointers.

 

Best=20 Regards,

Venu

 

 

-----Original=20 Message-----
From:=20 owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Muranyi, = Arpad
Sent: Tuesday, = February 07,=20 2006 11:16=20 PM
To: ibis-users@eda.org;=20 ibis@eda.org
Subject: = RE:=20 [IBIS-Users] RE: [IBIS] To capture the delay variation with change in IO = voltage=20

 

Venu,

 

The = IBIS model=20 will only partially for the Vcc variations.

Here is=20 how:

 

If = you lower=20 the supply voltage, the origin of the pullup

IV = curve will=20 go down to that lower voltage.  So the pullup

will pull up to=20 a lower voltage.

 

However, in=20 real transistor circuits, this lower supply

voltage would=20 also reduce the IV curve size, because the

Vgs = voltage is=20 smaller than at the normal supply voltage.

This effect is=20 usually called the "gate modulation effect"

and = is not=20 reproduced by IBIS simulators to my knowledge.

We = are working=20 on BIRD98 to describe this effect for IBIS

models.

 

http://www.vhdl.or= g/pub/ibis/birds/bird98.txt

 

There may be=20 two reasons for being interested in supply

voltage=20 variations.

 

1)  Static=20 DC characteristics of the buffer, i.e. how

much will its=20 strength change if we change the supply

voltage. =20 If you need this, you can generate several IV

curves at=20 different supply voltages and make a [Model]

for = each=20 set.  You can then use the [Model Selector]

keyword to=20 allow the tool to select the one you want

to = simulate=20 with.

 

2) =20 Dynamic noise simulations, i.e. you want to find

out = how the=20 buffer will "degrade" its switching performance

when there is=20 noise in the supply voltage during its

switching.  = This is a=20 more difficult task, and IBIS is

not = doing too=20 well on it.  We have BIRD95 and BIRD98 as

Lynne mentioned=20 it already to solve this deficiency in

the = IBIS=20 world.  However, as usual, if you write your

own = models in=20 the *-AMS languages, you can describe these

behaviors to=20 your heart's content without having to wait

for = BIRD95 and=20 BIRD98.

 

I = hope this=20 will shed some light on your questions.

 

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D

- ------_=_NextPart_001_01C62CD6.A9EB7F0B-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 8 Feb 2006 08:22:17 -0800 From: "Abdulrahman Rafiq" Subject: [IBIS-Users] Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models This is a multi-part message in MIME format. - ------=_NextPart_000_001C_01C62C88.C65E21B0 Content-Type: multipart/alternative; boundary="----=_NextPart_001_001D_01C62C88.C65E21B0" - ------=_NextPart_001_001D_01C62C88.C65E21B0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Published by EDACafe.com on 2/7/06, text of article below. http://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews &articleid=241206 Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models WILSONVILLE, Ore.-(BUSINESS WIRE)-Feb. 7, 2006- Mentor Graphics Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the release of the ICX(R) and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation I/O controller hub. This kit is the first to utilize Intel's new IBIS 4.1 and IEEE 1076.1 standard VHDL-AMS ( http://www.eigroup.org/ibis/) models. These analog/mixed-signal (AMS) models have been developed by Intel for the I/O controller hub portion of their next generation chipset, codenamed "Broadwater." These AMS signal integrity (SI) models also provide significant speed and accuracy benefits over traditional SPICE and IBIS modeling techniques. And being wrapped in IBIS syntax, these new models are as easy to import and use as traditional IBIS models. "Mentor Graphics is pleased to support these new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president and general manager, Systems Design Division, Mentor Graphics. "We are committed to open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and believe that they provide the flexibility and standardization required to cover modeling requirements now and into the future." Traditional IBIS constructs cannot accurately model today's advanced I/O buffers. As a result, many designers and engineers of PCBs performing SI analysis are forced to use complex transistor-level SPICE models. These models run slowly, often suffer convergence problems, and are typically distributed in a proprietary format. On the other hand, the IBIS 4.1 AMS models offer the benefit of superior performance and improved accuracy, with no convergence issues, in an IEEE standard format. "Intel is pleased to support the new IBIS 4.1 standard for signal integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, application engineering director of Intel's Business Client Group. "We are confident our customers will find the increased speed, accuracy, and flexibility of the IBIS 4.1 AMS models to be a significant benefit in their high-speed PCB design process." The Mentor ICX and ICX Pro kits for Intel's next generation I/O controller hub includes a complete IBIS model for the I/O controller hub, including AMS models for the PCI Express, Serial ATA and USB2 interfaces, as well as IBIS-formatted S-parameter models for the package pins and connectors, and traditional IBIS models for the other lower-speed interfaces. The ICX kit also includes a custom menu for configuring device and test conditions, and a complete reference design layout for Intel's next generation chipset imported into the tool ready for SI analysis. The next generation I/O controller hub high-speed receiver models also include a novel application of AMS which measures and plots eye-opening values in real-time while the simulation is in progress. The ICX and ICX Pro design kits is are available through Mentor and its local sales force. Customers can contact Mentor Graphics Corporation at designkit_info@mentor.com for more information. The Intel IBIS models and reference designs are available through Intel. Customers can contact their local Intel sales office for more information. About ICX and ICX Pro Mentor Graphics' ICX solution combines the electrical and physical aspects of a design, providing an integrated design and verification environment for signal integrity and timing analysis during layout. This environment uses true electrical rules to drive the placement and routing, as well as verification, of high-speed boards, ensuring electrically-correct designs the first time. ICX Pro Explorer provides a schematic-based what-if signal integrity environment, with extensive capabilities for pre-layout simulation, including sweeps. Both solutions are built using the ICX simulation technology. Through its support of IBIS 4.1, this simulation environment provides the ability to mix and match models of various formats (IBIS, SPICE, AMS). This gives designers and engineers the ultimate flexibility in terms of model support. About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 4000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/. Mentor Graphics and ICX are registered trademarks and ICX Pro is a trademark of Mentor Graphics Corporation. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. All other company or product names are the registered trademarks or trademarks of their respective owners. _____ Contact: Mentor Graphics Debra Layton, 720-494-1043 Email Contact Suzanne Graham, 503-685-7789 Email Contact Click here for Internet Business Systems Copyright 1994 - 2006, Internet Business Systems, Inc. 1-888-44-WEB-44 --- Contact us, or visit our other sites: AECCafe DCCCafe TechJobsCafe GISCafe MCADCafe NanoTechCafe PCBCafe Privacy Policy - --- Abdulrahman Rafiq (Hardware/IO Interconnect Modeling Engineer) ASIPD/SIPD/ISBU/DSSTG/Cisco Systems, Inc Phone : +1-408-527-5540 Fax : +1-408-526-6603 Pager : +1-888-646-7881 Email : arafiq@cisco.com Epage : arafiq@epage.cisco.com GrpURL : http://wwwin-sipd.cisco.cm RefURL : http://www.eigroup.org/ibis/ - ------=_NextPart_001_001D_01C62C88.C65E21B0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Published by EDACafe.com on 2/7/06, text of article=20 below. 
http://www10.edacafe.com/nbc/articles/vi= ew_article.php?section=3DCorpNews&articleid=3D241206
 
Mentor Graphics Announces Support for = Intel's IBIS=20 4.1 AMS Signal Integrity Models


WILSONVILLE, Ore.—(BUSINESS = WIRE)—Feb. 7,=20 2006— Mentor Graphics Corporation (Nasdaq:MENT), the market and technology leader in = printed=20 circuit board (PCB) design solutions, today announced the release of the = ICX(R)=20 and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation = I/O=20 controller hub. This kit is the first to utilize Intel's new IBIS 4.1 = and IEEE=20 1076.1 standard VHDL-AMS (<= FONT=20 color=3D#0033cc>http://www.eigroup.org/ibis/) models. These=20 analog/mixed-signal (AMS) models have been developed by Intel for the = I/O=20 controller hub portion of their next generation chipset, codenamed = "Broadwater."=20 These AMS signal integrity (SI) models also provide significant speed = and=20 accuracy benefits over traditional SPICE and IBIS modeling techniques. = And being=20 wrapped in IBIS syntax, these new models are as easy to import and use = as=20 traditional IBIS models.

"Mentor Graphics is pleased to support = these=20 new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president = and=20 general manager, Systems Design Division, Mentor Graphics. "We are = committed to=20 open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and = believe=20 that they provide the flexibility and standardization required to cover = modeling=20 requirements now and into the future."

Traditional IBIS = constructs=20 cannot accurately model today's advanced I/O buffers. As a result, many=20 designers and engineers of PCBs performing SI analysis are forced to use = complex=20 transistor-level SPICE models. These models run slowly, often suffer = convergence=20 problems, and are typically distributed in a proprietary format. On the = other=20 hand, the IBIS 4.1 AMS models offer the benefit of superior performance = and=20 improved accuracy, with no convergence issues, in an IEEE standard = format.=20

"Intel is pleased to support the new IBIS 4.1 standard for = signal=20 integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, = application engineering director of Intel's Business Client Group. "We = are=20 confident our customers will find the increased speed, accuracy, and = flexibility=20 of the IBIS 4.1 AMS models to be a significant benefit in their = high-speed PCB=20 design process."

The Mentor ICX and ICX Pro kits for Intel's = next=20 generation I/O controller hub includes a complete IBIS model for the I/O = controller hub, including AMS models for the PCI Express, Serial ATA and = USB2=20 interfaces, as well as IBIS-formatted S-parameter models for the package = pins=20 and connectors, and traditional IBIS models for the other lower-speed=20 interfaces. The ICX kit also includes a custom menu for configuring = device and=20 test conditions, and a complete reference design layout for Intel's next = generation chipset imported into the tool ready for SI analysis. The = next=20 generation I/O controller hub high-speed receiver models also include a = novel=20 application of AMS which measures and plots eye-opening values in = real-time=20 while the simulation is in progress.

The ICX and ICX Pro design = kits is=20 are available through Mentor and its local sales force. Customers can = contact=20 Mentor Graphics Corporation at designkit_info@mentor.com for more = information.=20 The Intel IBIS models and reference designs are available through Intel. = Customers can contact their local Intel sales office for more = information.=20

About ICX and ICX Pro

Mentor Graphics' ICX solution = combines the=20 electrical and physical aspects of a design, providing an integrated = design and=20 verification environment for signal integrity and timing analysis during = layout.=20 This environment uses true electrical rules to drive the placement and = routing,=20 as well as verification, of high-speed boards, ensuring = electrically-correct=20 designs the first time. ICX Pro Explorer provides a schematic-based = what-if=20 signal integrity environment, with extensive capabilities for pre-layout = simulation, including sweeps. Both solutions are built using the ICX = simulation=20 technology. Through its support of IBIS 4.1, this simulation environment = provides the ability to mix and match models of various formats (IBIS, = SPICE,=20 AMS). This gives designers and engineers the ultimate flexibility in = terms of=20 model support.

About Mentor Graphics

Mentor Graphics = Corporation=20 (Nasdaq:MENT) is a world leader in electronic = hardware and=20 software design solutions, providing products, consulting services and=20 award-winning support for the world's most successful electronics and=20 semiconductor companies. Established in 1981, the company reported = revenues over=20 the last 12 months of about $700 million and employs approximately 4000 = people=20 worldwide. Corporate headquarters are located at 8005 S.W. Boeckman = Road,=20 Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located = at 1001=20 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: = http://www.mentor.com/.

Mentor = Graphics and ICX=20 are registered trademarks and ICX Pro is a trademark of Mentor Graphics=20 Corporation. Intel is a trademark or registered trademark of Intel = Corporation=20 or its subsidiaries in the United States and other countries. All other = company=20 or product names are the registered trademarks or trademarks of their = respective=20 owners.


Contact: 
Mentor Graphics
Debra Layton, 720-494-1043
=
Email Contact
Suzanne Graham, 503-685-7789
Email =
Contact
 
 Copyright 1994 - 2006, Internet Business Systems, =
Inc.
1-888-44-WEB-44 --- Contact us, or visit our other sites:
AECCafe  DCCCafe  TechJobsCafe  GISCafe  MCADCafe  NanoTechCafe  PCBCafe   
 Privacy =
Policy
 
---
Abdulrahman Rafiq =
(Hardware/IO Interconnect = Modeling=20 Engineer)
ASIPD/SIPD/ISBU/DSSTG/Cisco Systems,=20 Inc
Phone  :=20 +1-408-527-5540
Fax      :=20 +1-408-526-6603
Pager   :=20 +1-888-646-7881
Email    : = arafiq@cisco.com
Epage   : arafiq@epage.cisco.com =
GrpURL : http://wwwin-sipd.cisco.cm =
RefURL  : http://www.eigroup.org/ibis/
 
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------=_NextPart_000_001C_01C62C88.C65E21B0-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 8 Feb 2006 08:35:30 -0800 From: "Abdulrahman Rafiq" Subject: [IBIS-Users] Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models This is a multi-part message in MIME format. - ------=_NextPart_000_003A_01C62C8A.9E6B02C0 Content-Type: multipart/alternative; boundary="----=_NextPart_001_003B_01C62C8A.9E6B02C0" - ------=_NextPart_001_003B_01C62C8A.9E6B02C0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Published by EDACafe.com on 2/7/06, text of article below. http://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews &articleid=241206 Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models WILSONVILLE, Ore.-(BUSINESS WIRE)-Feb. 7, 2006- Mentor Graphics Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the release of the ICX(R) and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation I/O controller hub. This kit is the first to utilize Intel's new IBIS 4.1 and IEEE 1076.1 standard VHDL-AMS ( http://www.eigroup.org/ibis/) models. These analog/mixed-signal (AMS) models have been developed by Intel for the I/O controller hub portion of their next generation chipset, codenamed "Broadwater." These AMS signal integrity (SI) models also provide significant speed and accuracy benefits over traditional SPICE and IBIS modeling techniques. And being wrapped in IBIS syntax, these new models are as easy to import and use as traditional IBIS models. "Mentor Graphics is pleased to support these new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president and general manager, Systems Design Division, Mentor Graphics. "We are committed to open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and believe that they provide the flexibility and standardization required to cover modeling requirements now and into the future." Traditional IBIS constructs cannot accurately model today's advanced I/O buffers. As a result, many designers and engineers of PCBs performing SI analysis are forced to use complex transistor-level SPICE models. These models run slowly, often suffer convergence problems, and are typically distributed in a proprietary format. On the other hand, the IBIS 4.1 AMS models offer the benefit of superior performance and improved accuracy, with no convergence issues, in an IEEE standard format. "Intel is pleased to support the new IBIS 4.1 standard for signal integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, application engineering director of Intel's Business Client Group. "We are confident our customers will find the increased speed, accuracy, and flexibility of the IBIS 4.1 AMS models to be a significant benefit in their high-speed PCB design process." The Mentor ICX and ICX Pro kits for Intel's next generation I/O controller hub includes a complete IBIS model for the I/O controller hub, including AMS models for the PCI Express, Serial ATA and USB2 interfaces, as well as IBIS-formatted S-parameter models for the package pins and connectors, and traditional IBIS models for the other lower-speed interfaces. The ICX kit also includes a custom menu for configuring device and test conditions, and a complete reference design layout for Intel's next generation chipset imported into the tool ready for SI analysis. The next generation I/O controller hub high-speed receiver models also include a novel application of AMS which measures and plots eye-opening values in real-time while the simulation is in progress. The ICX and ICX Pro design kits is are available through Mentor and its local sales force. Customers can contact Mentor Graphics Corporation at designkit_info@mentor.com for more information. The Intel IBIS models and reference designs are available through Intel. Customers can contact their local Intel sales office for more information. About ICX and ICX Pro Mentor Graphics' ICX solution combines the electrical and physical aspects of a design, providing an integrated design and verification environment for signal integrity and timing analysis during layout. This environment uses true electrical rules to drive the placement and routing, as well as verification, of high-speed boards, ensuring electrically-correct designs the first time. ICX Pro Explorer provides a schematic-based what-if signal integrity environment, with extensive capabilities for pre-layout simulation, including sweeps. Both solutions are built using the ICX simulation technology. Through its support of IBIS 4.1, this simulation environment provides the ability to mix and match models of various formats (IBIS, SPICE, AMS). This gives designers and engineers the ultimate flexibility in terms of model support. About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 4000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/. Mentor Graphics and ICX are registered trademarks and ICX Pro is a trademark of Mentor Graphics Corporation. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. All other company or product names are the registered trademarks or trademarks of their respective owners. _____ Contact: Mentor Graphics Debra Layton, 720-494-1043 Email Contact Suzanne Graham, 503-685-7789 Email Contact Click here for Internet Business Systems Copyright 1994 - 2006, Internet Business Systems, Inc. 1-888-44-WEB-44 --- Contact us, or visit our other sites: AECCafe DCCCafe TechJobsCafe GISCafe MCADCafe NanoTechCafe PCBCafe Privacy Policy - --- Abdulrahman Rafiq (Hardware/IO Interconnect Modeling Engineer) ASIPD/SIPD/ISBU/DSSTG/Cisco Systems, Inc Phone : +1-408-527-5540 Fax : +1-408-526-6603 Pager : +1-888-646-7881 Email : arafiq@cisco.com Epage : arafiq@epage.cisco.com GrpURL : http://wwwin-sipd.cisco.cm RefURL : http://www.eigroup.org/ibis/ - ------=_NextPart_001_003B_01C62C8A.9E6B02C0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Published by EDACafe.com on 2/7/06, text of article=20 below. 
http://www10.edacafe.com/nbc/articles/vi= ew_article.php?section=3DCorpNews&articleid=3D241206
 
Mentor Graphics Announces Support for = Intel's IBIS=20 4.1 AMS Signal Integrity Models


WILSONVILLE, Ore.—(BUSINESS = WIRE)—Feb. 7,=20 2006— Mentor Graphics Corporation (Nasdaq:MENT), the market and technology leader in = printed=20 circuit board (PCB) design solutions, today announced the release of the = ICX(R)=20 and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation = I/O=20 controller hub. This kit is the first to utilize Intel's new IBIS 4.1 = and IEEE=20 1076.1 standard VHDL-AMS (<= FONT=20 color=3D#0033cc>http://www.eigroup.org/ibis/) models. These=20 analog/mixed-signal (AMS) models have been developed by Intel for the = I/O=20 controller hub portion of their next generation chipset, codenamed = "Broadwater."=20 These AMS signal integrity (SI) models also provide significant speed = and=20 accuracy benefits over traditional SPICE and IBIS modeling techniques. = And being=20 wrapped in IBIS syntax, these new models are as easy to import and use = as=20 traditional IBIS models.

"Mentor Graphics is pleased to support = these=20 new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president = and=20 general manager, Systems Design Division, Mentor Graphics. "We are = committed to=20 open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and = believe=20 that they provide the flexibility and standardization required to cover = modeling=20 requirements now and into the future."

Traditional IBIS = constructs=20 cannot accurately model today's advanced I/O buffers. As a result, many=20 designers and engineers of PCBs performing SI analysis are forced to use = complex=20 transistor-level SPICE models. These models run slowly, often suffer = convergence=20 problems, and are typically distributed in a proprietary format. On the = other=20 hand, the IBIS 4.1 AMS models offer the benefit of superior performance = and=20 improved accuracy, with no convergence issues, in an IEEE standard = format.=20

"Intel is pleased to support the new IBIS 4.1 standard for = signal=20 integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, = application engineering director of Intel's Business Client Group. "We = are=20 confident our customers will find the increased speed, accuracy, and = flexibility=20 of the IBIS 4.1 AMS models to be a significant benefit in their = high-speed PCB=20 design process."

The Mentor ICX and ICX Pro kits for Intel's = next=20 generation I/O controller hub includes a complete IBIS model for the I/O = controller hub, including AMS models for the PCI Express, Serial ATA and = USB2=20 interfaces, as well as IBIS-formatted S-parameter models for the package = pins=20 and connectors, and traditional IBIS models for the other lower-speed=20 interfaces. The ICX kit also includes a custom menu for configuring = device and=20 test conditions, and a complete reference design layout for Intel's next = generation chipset imported into the tool ready for SI analysis. The = next=20 generation I/O controller hub high-speed receiver models also include a = novel=20 application of AMS which measures and plots eye-opening values in = real-time=20 while the simulation is in progress.

The ICX and ICX Pro design = kits is=20 are available through Mentor and its local sales force. Customers can = contact=20 Mentor Graphics Corporation at designkit_info@mentor.com for more = information.=20 The Intel IBIS models and reference designs are available through Intel. = Customers can contact their local Intel sales office for more = information.=20

About ICX and ICX Pro

Mentor Graphics' ICX solution = combines the=20 electrical and physical aspects of a design, providing an integrated = design and=20 verification environment for signal integrity and timing analysis during = layout.=20 This environment uses true electrical rules to drive the placement and = routing,=20 as well as verification, of high-speed boards, ensuring = electrically-correct=20 designs the first time. ICX Pro Explorer provides a schematic-based = what-if=20 signal integrity environment, with extensive capabilities for pre-layout = simulation, including sweeps. Both solutions are built using the ICX = simulation=20 technology. Through its support of IBIS 4.1, this simulation environment = provides the ability to mix and match models of various formats (IBIS, = SPICE,=20 AMS). This gives designers and engineers the ultimate flexibility in = terms of=20 model support.

About Mentor Graphics

Mentor Graphics = Corporation=20 (Nasdaq:MENT) is a world leader in electronic = hardware and=20 software design solutions, providing products, consulting services and=20 award-winning support for the world's most successful electronics and=20 semiconductor companies. Established in 1981, the company reported = revenues over=20 the last 12 months of about $700 million and employs approximately 4000 = people=20 worldwide. Corporate headquarters are located at 8005 S.W. Boeckman = Road,=20 Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located = at 1001=20 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: = http://www.mentor.com/.

Mentor = Graphics and ICX=20 are registered trademarks and ICX Pro is a trademark of Mentor Graphics=20 Corporation. Intel is a trademark or registered trademark of Intel = Corporation=20 or its subsidiaries in the United States and other countries. All other = company=20 or product names are the registered trademarks or trademarks of their = respective=20 owners.


Contact: 
Mentor Graphics
Debra Layton, 720-494-1043
=
Email Contact
Suzanne Graham, 503-685-7789
Email =
Contact
 
 Copyright 1994 - 2006, Internet Business Systems, =
Inc.
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 Privacy =
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---
Abdulrahman Rafiq =
(Hardware/IO Interconnect = Modeling=20 Engineer)
ASIPD/SIPD/ISBU/DSSTG/Cisco Systems,=20 Inc
Phone  :=20 +1-408-527-5540
Fax      :=20 +1-408-526-6603
Pager   :=20 +1-888-646-7881
Email    : = arafiq@cisco.com
Epage   : arafiq@epage.cisco.com =
GrpURL : http://wwwin-sipd.cisco.cm =
RefURL  : http://www.eigroup.org/ibis/
 
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------=_NextPart_000_003A_01C62C8A.9E6B02C0-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 8 Feb 2006 08:37:46 -0800 From: "Abdulrahman Rafiq" Subject: [IBIS-Users] Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models This is a multi-part message in MIME format. - ------=_NextPart_000_0040_01C62C8A.EF86DDA0 Content-Type: multipart/alternative; boundary="----=_NextPart_001_0041_01C62C8A.EF86DDA0" - ------=_NextPart_001_0041_01C62C8A.EF86DDA0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Published by EDACafe.com on 2/7/06, text of article below. http://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews &articleid=241206 Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models WILSONVILLE, Ore.-(BUSINESS WIRE)-Feb. 7, 2006- Mentor Graphics Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the release of the ICX(R) and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation I/O controller hub. This kit is the first to utilize Intel's new IBIS 4.1 and IEEE 1076.1 standard VHDL-AMS ( http://www.eigroup.org/ibis/) models. These analog/mixed-signal (AMS) models have been developed by Intel for the I/O controller hub portion of their next generation chipset, codenamed "Broadwater." These AMS signal integrity (SI) models also provide significant speed and accuracy benefits over traditional SPICE and IBIS modeling techniques. And being wrapped in IBIS syntax, these new models are as easy to import and use as traditional IBIS models. "Mentor Graphics is pleased to support these new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president and general manager, Systems Design Division, Mentor Graphics. "We are committed to open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and believe that they provide the flexibility and standardization required to cover modeling requirements now and into the future." Traditional IBIS constructs cannot accurately model today's advanced I/O buffers. As a result, many designers and engineers of PCBs performing SI analysis are forced to use complex transistor-level SPICE models. These models run slowly, often suffer convergence problems, and are typically distributed in a proprietary format. On the other hand, the IBIS 4.1 AMS models offer the benefit of superior performance and improved accuracy, with no convergence issues, in an IEEE standard format. "Intel is pleased to support the new IBIS 4.1 standard for signal integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, application engineering director of Intel's Business Client Group. "We are confident our customers will find the increased speed, accuracy, and flexibility of the IBIS 4.1 AMS models to be a significant benefit in their high-speed PCB design process." The Mentor ICX and ICX Pro kits for Intel's next generation I/O controller hub includes a complete IBIS model for the I/O controller hub, including AMS models for the PCI Express, Serial ATA and USB2 interfaces, as well as IBIS-formatted S-parameter models for the package pins and connectors, and traditional IBIS models for the other lower-speed interfaces. The ICX kit also includes a custom menu for configuring device and test conditions, and a complete reference design layout for Intel's next generation chipset imported into the tool ready for SI analysis. The next generation I/O controller hub high-speed receiver models also include a novel application of AMS which measures and plots eye-opening values in real-time while the simulation is in progress. The ICX and ICX Pro design kits is are available through Mentor and its local sales force. Customers can contact Mentor Graphics Corporation at designkit_info@mentor.com for more information. The Intel IBIS models and reference designs are available through Intel. Customers can contact their local Intel sales office for more information. About ICX and ICX Pro Mentor Graphics' ICX solution combines the electrical and physical aspects of a design, providing an integrated design and verification environment for signal integrity and timing analysis during layout. This environment uses true electrical rules to drive the placement and routing, as well as verification, of high-speed boards, ensuring electrically-correct designs the first time. ICX Pro Explorer provides a schematic-based what-if signal integrity environment, with extensive capabilities for pre-layout simulation, including sweeps. Both solutions are built using the ICX simulation technology. Through its support of IBIS 4.1, this simulation environment provides the ability to mix and match models of various formats (IBIS, SPICE, AMS). This gives designers and engineers the ultimate flexibility in terms of model support. About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 4000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/. Mentor Graphics and ICX are registered trademarks and ICX Pro is a trademark of Mentor Graphics Corporation. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. All other company or product names are the registered trademarks or trademarks of their respective owners. _____ Contact: Mentor Graphics Debra Layton, 720-494-1043 Email Contact Suzanne Graham, 503-685-7789 Email Contact Click here for Internet Business Systems Copyright 1994 - 2006, Internet Business Systems, Inc. 1-888-44-WEB-44 --- Contact us, or visit our other sites: AECCafe DCCCafe TechJobsCafe GISCafe MCADCafe NanoTechCafe PCBCafe Privacy Policy - --- Abdulrahman Rafiq (Hardware/IO Interconnect Modeling Engineer) ASIPD/SIPD/ISBU/DSSTG/Cisco Systems, Inc Phone : +1-408-527-5540 Fax : +1-408-526-6603 Pager : +1-888-646-7881 Email : arafiq@cisco.com Epage : arafiq@epage.cisco.com GrpURL : http://wwwin-sipd.cisco.cm RefURL : http://www.eigroup.org/ibis/ - ------=_NextPart_001_0041_01C62C8A.EF86DDA0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Published by EDACafe.com on 2/7/06, text of article=20 below. 
http://www10.edacafe.com/nbc/articles/vi= ew_article.php?section=3DCorpNews&articleid=3D241206
 
Mentor Graphics Announces Support for = Intel's IBIS=20 4.1 AMS Signal Integrity Models


WILSONVILLE, Ore.—(BUSINESS = WIRE)—Feb. 7,=20 2006— Mentor Graphics Corporation (Nasdaq:MENT), the market and technology leader in = printed=20 circuit board (PCB) design solutions, today announced the release of the = ICX(R)=20 and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation = I/O=20 controller hub. This kit is the first to utilize Intel's new IBIS 4.1 = and IEEE=20 1076.1 standard VHDL-AMS (<= FONT=20 color=3D#0033cc>http://www.eigroup.org/ibis/) models. These=20 analog/mixed-signal (AMS) models have been developed by Intel for the = I/O=20 controller hub portion of their next generation chipset, codenamed = "Broadwater."=20 These AMS signal integrity (SI) models also provide significant speed = and=20 accuracy benefits over traditional SPICE and IBIS modeling techniques. = And being=20 wrapped in IBIS syntax, these new models are as easy to import and use = as=20 traditional IBIS models.

"Mentor Graphics is pleased to support = these=20 new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president = and=20 general manager, Systems Design Division, Mentor Graphics. "We are = committed to=20 open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and = believe=20 that they provide the flexibility and standardization required to cover = modeling=20 requirements now and into the future."

Traditional IBIS = constructs=20 cannot accurately model today's advanced I/O buffers. As a result, many=20 designers and engineers of PCBs performing SI analysis are forced to use = complex=20 transistor-level SPICE models. These models run slowly, often suffer = convergence=20 problems, and are typically distributed in a proprietary format. On the = other=20 hand, the IBIS 4.1 AMS models offer the benefit of superior performance = and=20 improved accuracy, with no convergence issues, in an IEEE standard = format.=20

"Intel is pleased to support the new IBIS 4.1 standard for = signal=20 integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, = application engineering director of Intel's Business Client Group. "We = are=20 confident our customers will find the increased speed, accuracy, and = flexibility=20 of the IBIS 4.1 AMS models to be a significant benefit in their = high-speed PCB=20 design process."

The Mentor ICX and ICX Pro kits for Intel's = next=20 generation I/O controller hub includes a complete IBIS model for the I/O = controller hub, including AMS models for the PCI Express, Serial ATA and = USB2=20 interfaces, as well as IBIS-formatted S-parameter models for the package = pins=20 and connectors, and traditional IBIS models for the other lower-speed=20 interfaces. The ICX kit also includes a custom menu for configuring = device and=20 test conditions, and a complete reference design layout for Intel's next = generation chipset imported into the tool ready for SI analysis. The = next=20 generation I/O controller hub high-speed receiver models also include a = novel=20 application of AMS which measures and plots eye-opening values in = real-time=20 while the simulation is in progress.

The ICX and ICX Pro design = kits is=20 are available through Mentor and its local sales force. Customers can = contact=20 Mentor Graphics Corporation at designkit_info@mentor.com for more = information.=20 The Intel IBIS models and reference designs are available through Intel. = Customers can contact their local Intel sales office for more = information.=20

About ICX and ICX Pro

Mentor Graphics' ICX solution = combines the=20 electrical and physical aspects of a design, providing an integrated = design and=20 verification environment for signal integrity and timing analysis during = layout.=20 This environment uses true electrical rules to drive the placement and = routing,=20 as well as verification, of high-speed boards, ensuring = electrically-correct=20 designs the first time. ICX Pro Explorer provides a schematic-based = what-if=20 signal integrity environment, with extensive capabilities for pre-layout = simulation, including sweeps. Both solutions are built using the ICX = simulation=20 technology. Through its support of IBIS 4.1, this simulation environment = provides the ability to mix and match models of various formats (IBIS, = SPICE,=20 AMS). This gives designers and engineers the ultimate flexibility in = terms of=20 model support.

About Mentor Graphics

Mentor Graphics = Corporation=20 (Nasdaq:MENT) is a world leader in electronic = hardware and=20 software design solutions, providing products, consulting services and=20 award-winning support for the world's most successful electronics and=20 semiconductor companies. Established in 1981, the company reported = revenues over=20 the last 12 months of about $700 million and employs approximately 4000 = people=20 worldwide. Corporate headquarters are located at 8005 S.W. Boeckman = Road,=20 Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located = at 1001=20 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: = http://www.mentor.com/.

Mentor = Graphics and ICX=20 are registered trademarks and ICX Pro is a trademark of Mentor Graphics=20 Corporation. Intel is a trademark or registered trademark of Intel = Corporation=20 or its subsidiaries in the United States and other countries. All other = company=20 or product names are the registered trademarks or trademarks of their = respective=20 owners.


Contact: 
Mentor Graphics
Debra Layton, 720-494-1043
=
Email Contact
Suzanne Graham, 503-685-7789
Email =
Contact
 
 Copyright 1994 - 2006, Internet Business Systems, =
Inc.
1-888-44-WEB-44 --- Contact us, or visit our other sites:
AECCafe  DCCCafe  TechJobsCafe  GISCafe  MCADCafe  NanoTechCafe  PCBCafe   
 Privacy =
Policy
 
---
Abdulrahman Rafiq =
(Hardware/IO Interconnect = Modeling=20 Engineer)
ASIPD/SIPD/ISBU/DSSTG/Cisco Systems,=20 Inc
Phone  :=20 +1-408-527-5540
Fax      :=20 +1-408-526-6603
Pager   :=20 +1-888-646-7881
Email    : = arafiq@cisco.com
Epage   : arafiq@epage.cisco.com =
GrpURL : http://wwwin-sipd.cisco.cm =
RefURL  : http://www.eigroup.org/ibis/
 
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------=_NextPart_000_0040_01C62C8A.EF86DDA0-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 8 Feb 2006 08:29:02 -0800 From: "Abdulrahman Rafiq" Subject: [IBIS-Users] Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models This is a multi-part message in MIME format. - ------=_NextPart_000_0028_01C62C89.B739FB90 Content-Type: multipart/alternative; boundary="----=_NextPart_001_0029_01C62C89.B739FB90" - ------=_NextPart_001_0029_01C62C89.B739FB90 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Published by EDACafe.com on 2/7/06, text of article below. http://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews &articleid=241206 Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models WILSONVILLE, Ore.-(BUSINESS WIRE)-Feb. 7, 2006- Mentor Graphics Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the release of the ICX(R) and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation I/O controller hub. This kit is the first to utilize Intel's new IBIS 4.1 and IEEE 1076.1 standard VHDL-AMS ( http://www.eigroup.org/ibis/) models. These analog/mixed-signal (AMS) models have been developed by Intel for the I/O controller hub portion of their next generation chipset, codenamed "Broadwater." These AMS signal integrity (SI) models also provide significant speed and accuracy benefits over traditional SPICE and IBIS modeling techniques. And being wrapped in IBIS syntax, these new models are as easy to import and use as traditional IBIS models. "Mentor Graphics is pleased to support these new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president and general manager, Systems Design Division, Mentor Graphics. "We are committed to open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and believe that they provide the flexibility and standardization required to cover modeling requirements now and into the future." Traditional IBIS constructs cannot accurately model today's advanced I/O buffers. As a result, many designers and engineers of PCBs performing SI analysis are forced to use complex transistor-level SPICE models. These models run slowly, often suffer convergence problems, and are typically distributed in a proprietary format. On the other hand, the IBIS 4.1 AMS models offer the benefit of superior performance and improved accuracy, with no convergence issues, in an IEEE standard format. "Intel is pleased to support the new IBIS 4.1 standard for signal integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, application engineering director of Intel's Business Client Group. "We are confident our customers will find the increased speed, accuracy, and flexibility of the IBIS 4.1 AMS models to be a significant benefit in their high-speed PCB design process." The Mentor ICX and ICX Pro kits for Intel's next generation I/O controller hub includes a complete IBIS model for the I/O controller hub, including AMS models for the PCI Express, Serial ATA and USB2 interfaces, as well as IBIS-formatted S-parameter models for the package pins and connectors, and traditional IBIS models for the other lower-speed interfaces. The ICX kit also includes a custom menu for configuring device and test conditions, and a complete reference design layout for Intel's next generation chipset imported into the tool ready for SI analysis. The next generation I/O controller hub high-speed receiver models also include a novel application of AMS which measures and plots eye-opening values in real-time while the simulation is in progress. The ICX and ICX Pro design kits is are available through Mentor and its local sales force. Customers can contact Mentor Graphics Corporation at designkit_info@mentor.com for more information. The Intel IBIS models and reference designs are available through Intel. Customers can contact their local Intel sales office for more information. About ICX and ICX Pro Mentor Graphics' ICX solution combines the electrical and physical aspects of a design, providing an integrated design and verification environment for signal integrity and timing analysis during layout. This environment uses true electrical rules to drive the placement and routing, as well as verification, of high-speed boards, ensuring electrically-correct designs the first time. ICX Pro Explorer provides a schematic-based what-if signal integrity environment, with extensive capabilities for pre-layout simulation, including sweeps. Both solutions are built using the ICX simulation technology. Through its support of IBIS 4.1, this simulation environment provides the ability to mix and match models of various formats (IBIS, SPICE, AMS). This gives designers and engineers the ultimate flexibility in terms of model support. About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 4000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/. Mentor Graphics and ICX are registered trademarks and ICX Pro is a trademark of Mentor Graphics Corporation. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. All other company or product names are the registered trademarks or trademarks of their respective owners. _____ Contact: Mentor Graphics Debra Layton, 720-494-1043 Email Contact Suzanne Graham, 503-685-7789 Email Contact Click here for Internet Business Systems Copyright 1994 - 2006, Internet Business Systems, Inc. 1-888-44-WEB-44 --- Contact us, or visit our other sites: AECCafe DCCCafe TechJobsCafe GISCafe MCADCafe NanoTechCafe PCBCafe Privacy Policy - --- Abdulrahman Rafiq (Hardware/IO Interconnect Modeling Engineer) ASIPD/SIPD/ISBU/DSSTG/Cisco Systems, Inc Phone : +1-408-527-5540 Fax : +1-408-526-6603 Pager : +1-888-646-7881 Email : arafiq@cisco.com Epage : arafiq@epage.cisco.com GrpURL : http://wwwin-sipd.cisco.cm RefURL : http://www.eigroup.org/ibis/ - ------=_NextPart_001_0029_01C62C89.B739FB90 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Published by EDACafe.com on 2/7/06, text of article=20 below. 
http://www10.edacafe.com/nbc/articles/vi= ew_article.php?section=3DCorpNews&articleid=3D241206
 
Mentor Graphics Announces Support for = Intel's IBIS=20 4.1 AMS Signal Integrity Models


WILSONVILLE, Ore.—(BUSINESS = WIRE)—Feb. 7,=20 2006— Mentor Graphics Corporation (Nasdaq:MENT), the market and technology leader in = printed=20 circuit board (PCB) design solutions, today announced the release of the = ICX(R)=20 and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation = I/O=20 controller hub. This kit is the first to utilize Intel's new IBIS 4.1 = and IEEE=20 1076.1 standard VHDL-AMS (<= FONT=20 color=3D#0033cc>http://www.eigroup.org/ibis/) models. These=20 analog/mixed-signal (AMS) models have been developed by Intel for the = I/O=20 controller hub portion of their next generation chipset, codenamed = "Broadwater."=20 These AMS signal integrity (SI) models also provide significant speed = and=20 accuracy benefits over traditional SPICE and IBIS modeling techniques. = And being=20 wrapped in IBIS syntax, these new models are as easy to import and use = as=20 traditional IBIS models.

"Mentor Graphics is pleased to support = these=20 new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president = and=20 general manager, Systems Design Division, Mentor Graphics. "We are = committed to=20 open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and = believe=20 that they provide the flexibility and standardization required to cover = modeling=20 requirements now and into the future."

Traditional IBIS = constructs=20 cannot accurately model today's advanced I/O buffers. As a result, many=20 designers and engineers of PCBs performing SI analysis are forced to use = complex=20 transistor-level SPICE models. These models run slowly, often suffer = convergence=20 problems, and are typically distributed in a proprietary format. On the = other=20 hand, the IBIS 4.1 AMS models offer the benefit of superior performance = and=20 improved accuracy, with no convergence issues, in an IEEE standard = format.=20

"Intel is pleased to support the new IBIS 4.1 standard for = signal=20 integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, = application engineering director of Intel's Business Client Group. "We = are=20 confident our customers will find the increased speed, accuracy, and = flexibility=20 of the IBIS 4.1 AMS models to be a significant benefit in their = high-speed PCB=20 design process."

The Mentor ICX and ICX Pro kits for Intel's = next=20 generation I/O controller hub includes a complete IBIS model for the I/O = controller hub, including AMS models for the PCI Express, Serial ATA and = USB2=20 interfaces, as well as IBIS-formatted S-parameter models for the package = pins=20 and connectors, and traditional IBIS models for the other lower-speed=20 interfaces. The ICX kit also includes a custom menu for configuring = device and=20 test conditions, and a complete reference design layout for Intel's next = generation chipset imported into the tool ready for SI analysis. The = next=20 generation I/O controller hub high-speed receiver models also include a = novel=20 application of AMS which measures and plots eye-opening values in = real-time=20 while the simulation is in progress.

The ICX and ICX Pro design = kits is=20 are available through Mentor and its local sales force. Customers can = contact=20 Mentor Graphics Corporation at designkit_info@mentor.com for more = information.=20 The Intel IBIS models and reference designs are available through Intel. = Customers can contact their local Intel sales office for more = information.=20

About ICX and ICX Pro

Mentor Graphics' ICX solution = combines the=20 electrical and physical aspects of a design, providing an integrated = design and=20 verification environment for signal integrity and timing analysis during = layout.=20 This environment uses true electrical rules to drive the placement and = routing,=20 as well as verification, of high-speed boards, ensuring = electrically-correct=20 designs the first time. ICX Pro Explorer provides a schematic-based = what-if=20 signal integrity environment, with extensive capabilities for pre-layout = simulation, including sweeps. Both solutions are built using the ICX = simulation=20 technology. Through its support of IBIS 4.1, this simulation environment = provides the ability to mix and match models of various formats (IBIS, = SPICE,=20 AMS). This gives designers and engineers the ultimate flexibility in = terms of=20 model support.

About Mentor Graphics

Mentor Graphics = Corporation=20 (Nasdaq:MENT) is a world leader in electronic = hardware and=20 software design solutions, providing products, consulting services and=20 award-winning support for the world's most successful electronics and=20 semiconductor companies. Established in 1981, the company reported = revenues over=20 the last 12 months of about $700 million and employs approximately 4000 = people=20 worldwide. Corporate headquarters are located at 8005 S.W. Boeckman = Road,=20 Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located = at 1001=20 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: = http://www.mentor.com/.

Mentor = Graphics and ICX=20 are registered trademarks and ICX Pro is a trademark of Mentor Graphics=20 Corporation. Intel is a trademark or registered trademark of Intel = Corporation=20 or its subsidiaries in the United States and other countries. All other = company=20 or product names are the registered trademarks or trademarks of their = respective=20 owners.


Contact: 
Mentor Graphics
Debra Layton, 720-494-1043
=
Email Contact
Suzanne Graham, 503-685-7789
Email =
Contact
 
 Copyright 1994 - 2006, Internet Business Systems, =
Inc.
1-888-44-WEB-44 --- Contact us, or visit our other sites:
AECCafe  DCCCafe  TechJobsCafe  GISCafe  MCADCafe  NanoTechCafe  PCBCafe   
 Privacy =
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---
Abdulrahman Rafiq =
(Hardware/IO Interconnect = Modeling=20 Engineer)
ASIPD/SIPD/ISBU/DSSTG/Cisco Systems,=20 Inc
Phone  :=20 +1-408-527-5540
Fax      :=20 +1-408-526-6603
Pager   :=20 +1-888-646-7881
Email    : = arafiq@cisco.com
Epage   : arafiq@epage.cisco.com =
GrpURL : http://wwwin-sipd.cisco.cm =
RefURL  : http://www.eigroup.org/ibis/
 
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------=_NextPart_000_0028_01C62C89.B739FB90-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 8 Feb 2006 08:33:14 -0800 From: "Abdulrahman Rafiq" Subject: [IBIS-Users] Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models This is a multi-part message in MIME format. - ------=_NextPart_000_0034_01C62C8A.4D5D58B0 Content-Type: multipart/alternative; boundary="----=_NextPart_001_0035_01C62C8A.4D5D58B0" - ------=_NextPart_001_0035_01C62C8A.4D5D58B0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Published by EDACafe.com on 2/7/06, text of article below. http://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews &articleid=241206 Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models WILSONVILLE, Ore.-(BUSINESS WIRE)-Feb. 7, 2006- Mentor Graphics Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the release of the ICX(R) and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation I/O controller hub. This kit is the first to utilize Intel's new IBIS 4.1 and IEEE 1076.1 standard VHDL-AMS ( http://www.eigroup.org/ibis/) models. These analog/mixed-signal (AMS) models have been developed by Intel for the I/O controller hub portion of their next generation chipset, codenamed "Broadwater." These AMS signal integrity (SI) models also provide significant speed and accuracy benefits over traditional SPICE and IBIS modeling techniques. And being wrapped in IBIS syntax, these new models are as easy to import and use as traditional IBIS models. "Mentor Graphics is pleased to support these new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president and general manager, Systems Design Division, Mentor Graphics. "We are committed to open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and believe that they provide the flexibility and standardization required to cover modeling requirements now and into the future." Traditional IBIS constructs cannot accurately model today's advanced I/O buffers. As a result, many designers and engineers of PCBs performing SI analysis are forced to use complex transistor-level SPICE models. These models run slowly, often suffer convergence problems, and are typically distributed in a proprietary format. On the other hand, the IBIS 4.1 AMS models offer the benefit of superior performance and improved accuracy, with no convergence issues, in an IEEE standard format. "Intel is pleased to support the new IBIS 4.1 standard for signal integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, application engineering director of Intel's Business Client Group. "We are confident our customers will find the increased speed, accuracy, and flexibility of the IBIS 4.1 AMS models to be a significant benefit in their high-speed PCB design process." The Mentor ICX and ICX Pro kits for Intel's next generation I/O controller hub includes a complete IBIS model for the I/O controller hub, including AMS models for the PCI Express, Serial ATA and USB2 interfaces, as well as IBIS-formatted S-parameter models for the package pins and connectors, and traditional IBIS models for the other lower-speed interfaces. The ICX kit also includes a custom menu for configuring device and test conditions, and a complete reference design layout for Intel's next generation chipset imported into the tool ready for SI analysis. The next generation I/O controller hub high-speed receiver models also include a novel application of AMS which measures and plots eye-opening values in real-time while the simulation is in progress. The ICX and ICX Pro design kits is are available through Mentor and its local sales force. Customers can contact Mentor Graphics Corporation at designkit_info@mentor.com for more information. The Intel IBIS models and reference designs are available through Intel. Customers can contact their local Intel sales office for more information. About ICX and ICX Pro Mentor Graphics' ICX solution combines the electrical and physical aspects of a design, providing an integrated design and verification environment for signal integrity and timing analysis during layout. This environment uses true electrical rules to drive the placement and routing, as well as verification, of high-speed boards, ensuring electrically-correct designs the first time. ICX Pro Explorer provides a schematic-based what-if signal integrity environment, with extensive capabilities for pre-layout simulation, including sweeps. Both solutions are built using the ICX simulation technology. Through its support of IBIS 4.1, this simulation environment provides the ability to mix and match models of various formats (IBIS, SPICE, AMS). This gives designers and engineers the ultimate flexibility in terms of model support. About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 4000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/. Mentor Graphics and ICX are registered trademarks and ICX Pro is a trademark of Mentor Graphics Corporation. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. All other company or product names are the registered trademarks or trademarks of their respective owners. _____ Contact: Mentor Graphics Debra Layton, 720-494-1043 Email Contact Suzanne Graham, 503-685-7789 Email Contact Click here for Internet Business Systems Copyright 1994 - 2006, Internet Business Systems, Inc. 1-888-44-WEB-44 --- Contact us, or visit our other sites: AECCafe DCCCafe TechJobsCafe GISCafe MCADCafe NanoTechCafe PCBCafe Privacy Policy - --- Abdulrahman Rafiq (Hardware/IO Interconnect Modeling Engineer) ASIPD/SIPD/ISBU/DSSTG/Cisco Systems, Inc Phone : +1-408-527-5540 Fax : +1-408-526-6603 Pager : +1-888-646-7881 Email : arafiq@cisco.com Epage : arafiq@epage.cisco.com GrpURL : http://wwwin-sipd.cisco.cm RefURL : http://www.eigroup.org/ibis/ - ------=_NextPart_001_0035_01C62C8A.4D5D58B0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Published by EDACafe.com on 2/7/06, text of article=20 below. 
http://www10.edacafe.com/nbc/articles/vi= ew_article.php?section=3DCorpNews&articleid=3D241206
 
Mentor Graphics Announces Support for = Intel's IBIS=20 4.1 AMS Signal Integrity Models


WILSONVILLE, Ore.—(BUSINESS = WIRE)—Feb. 7,=20 2006— Mentor Graphics Corporation (Nasdaq:MENT), the market and technology leader in = printed=20 circuit board (PCB) design solutions, today announced the release of the = ICX(R)=20 and ICX Pro(TM) Signal Integrity Design Kits for Intel's next generation = I/O=20 controller hub. This kit is the first to utilize Intel's new IBIS 4.1 = and IEEE=20 1076.1 standard VHDL-AMS (<= FONT=20 color=3D#0033cc>http://www.eigroup.org/ibis/) models. These=20 analog/mixed-signal (AMS) models have been developed by Intel for the = I/O=20 controller hub portion of their next generation chipset, codenamed = "Broadwater."=20 These AMS signal integrity (SI) models also provide significant speed = and=20 accuracy benefits over traditional SPICE and IBIS modeling techniques. = And being=20 wrapped in IBIS syntax, these new models are as easy to import and use = as=20 traditional IBIS models.

"Mentor Graphics is pleased to support = these=20 new IBIS 4.1 AMS models from Intel," said Henry Potts, vice president = and=20 general manager, Systems Design Division, Mentor Graphics. "We are = committed to=20 open industry standards, such as IBIS 4.1 and IEEE 1076.1 VHDL-AMS, and = believe=20 that they provide the flexibility and standardization required to cover = modeling=20 requirements now and into the future."

Traditional IBIS = constructs=20 cannot accurately model today's advanced I/O buffers. As a result, many=20 designers and engineers of PCBs performing SI analysis are forced to use = complex=20 transistor-level SPICE models. These models run slowly, often suffer = convergence=20 problems, and are typically distributed in a proprietary format. On the = other=20 hand, the IBIS 4.1 AMS models offer the benefit of superior performance = and=20 improved accuracy, with no convergence issues, in an IEEE standard = format.=20

"Intel is pleased to support the new IBIS 4.1 standard for = signal=20 integrity modeling by providing IBIS 4.1 AMS models," stated Greg Crain, = application engineering director of Intel's Business Client Group. "We = are=20 confident our customers will find the increased speed, accuracy, and = flexibility=20 of the IBIS 4.1 AMS models to be a significant benefit in their = high-speed PCB=20 design process."

The Mentor ICX and ICX Pro kits for Intel's = next=20 generation I/O controller hub includes a complete IBIS model for the I/O = controller hub, including AMS models for the PCI Express, Serial ATA and = USB2=20 interfaces, as well as IBIS-formatted S-parameter models for the package = pins=20 and connectors, and traditional IBIS models for the other lower-speed=20 interfaces. The ICX kit also includes a custom menu for configuring = device and=20 test conditions, and a complete reference design layout for Intel's next = generation chipset imported into the tool ready for SI analysis. The = next=20 generation I/O controller hub high-speed receiver models also include a = novel=20 application of AMS which measures and plots eye-opening values in = real-time=20 while the simulation is in progress.

The ICX and ICX Pro design = kits is=20 are available through Mentor and its local sales force. Customers can = contact=20 Mentor Graphics Corporation at designkit_info@mentor.com for more = information.=20 The Intel IBIS models and reference designs are available through Intel. = Customers can contact their local Intel sales office for more = information.=20

About ICX and ICX Pro

Mentor Graphics' ICX solution = combines the=20 electrical and physical aspects of a design, providing an integrated = design and=20 verification environment for signal integrity and timing analysis during = layout.=20 This environment uses true electrical rules to drive the placement and = routing,=20 as well as verification, of high-speed boards, ensuring = electrically-correct=20 designs the first time. ICX Pro Explorer provides a schematic-based = what-if=20 signal integrity environment, with extensive capabilities for pre-layout = simulation, including sweeps. Both solutions are built using the ICX = simulation=20 technology. Through its support of IBIS 4.1, this simulation environment = provides the ability to mix and match models of various formats (IBIS, = SPICE,=20 AMS). This gives designers and engineers the ultimate flexibility in = terms of=20 model support.

About Mentor Graphics

Mentor Graphics = Corporation=20 (Nasdaq:MENT) is a world leader in electronic = hardware and=20 software design solutions, providing products, consulting services and=20 award-winning support for the world's most successful electronics and=20 semiconductor companies. Established in 1981, the company reported = revenues over=20 the last 12 months of about $700 million and employs approximately 4000 = people=20 worldwide. Corporate headquarters are located at 8005 S.W. Boeckman = Road,=20 Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located = at 1001=20 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: = http://www.mentor.com/.

Mentor = Graphics and ICX=20 are registered trademarks and ICX Pro is a trademark of Mentor Graphics=20 Corporation. Intel is a trademark or registered trademark of Intel = Corporation=20 or its subsidiaries in the United States and other countries. All other = company=20 or product names are the registered trademarks or trademarks of their = respective=20 owners.


Contact: 
Mentor Graphics
Debra Layton, 720-494-1043
=
Email Contact
Suzanne Graham, 503-685-7789
Email =
Contact
 
 Copyright 1994 - 2006, Internet Business Systems, =
Inc.
1-888-44-WEB-44 --- Contact us, or visit our other sites:
AECCafe  DCCCafe  TechJobsCafe  GISCafe  MCADCafe  NanoTechCafe  PCBCafe   
 Privacy =
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---
Abdulrahman Rafiq =
(Hardware/IO Interconnect = Modeling=20 Engineer)
ASIPD/SIPD/ISBU/DSSTG/Cisco Systems,=20 Inc
Phone  :=20 +1-408-527-5540
Fax      :=20 +1-408-526-6603
Pager   :=20 +1-888-646-7881
Email    : = arafiq@cisco.com
Epage   : arafiq@epage.cisco.com =
GrpURL : http://wwwin-sipd.cisco.cm =
RefURL  : http://www.eigroup.org/ibis/
 
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