From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #81 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Thursday, April 6 2006 Volume 01 : Number 081 ---------------------------------------------------------------------- Date: Tue, 21 Mar 2006 22:34:57 -0800 (PST) From: Abrar Ahmed Subject: [IBIS-Users] Question on Oscillator - --0-399418280-1143009297=:40760 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi Mr.Bob, Is it possible to model an "Oscillator" into an IBIS file. If yes, then could you please direct me to a good place where i could find helpful stuff. Thanks in advance, Abrar - --------------------------------- Yahoo! Mail Bring photos to life! New PhotoMail makes sharing a breeze. - --0-399418280-1143009297=:40760 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit
Hi Mr.Bob,
 
Is it possible to model an "Oscillator" into an IBIS file. If yes, then could you please direct me to a good place where i could find helpful stuff.
 
Thanks in advance,
Abrar
 

Yahoo! Mail
Bring photos to life! New PhotoMail makes sharing a breeze. - --0-399418280-1143009297=:40760-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 23 Mar 2006 17:15:26 +0100 From: Subject: [IBIS-Users] How to replace RLC package Hi experts, once again (almost) the same question, but now other way around ... Recently I am getting lot of pressure to figure out how (in which format) to generate reasonable package model for IBIS models of our components. Possible solutions: ============== 1.) [Sparse Matrix] - contra: tools that generate [Sparse Matrix] models can't generate models for multidrop networks (i.e. one pin one the input, more than one pads on output), sloppy support from simulation tools 2.) ICM - contra: no available tool for automated extraction (and nobody wants to do it manually :-(((() 3.) Simple RLC parameters - contra: no information about cross-coupling RLC elements (coupling capacitances, mutual inductances, etc.) Workaround: use HSpice model of package, but how to "connect" it with IBIS model? IBIS 4.1 provides new keywords [External Circuit], [End External Circuit], [External Model], [End External Model] [Node Declarations], [End Node Declarations], [Circuit Call] and [End Circuit Call] to support multi-lingual models - nice! Main question: Is there a possibility to replace package description in [Pin] section of [Component] with some [External Circuit] or [External Model] or [Node Declarations]? So what I want to do is to replace: [Pin] signal_name model_name R_pin L_pin C_pin | A1 VDD POWER 210m 4.07nH 0.27pF A2 NF NF_INPUT 168m 2.70nH 0.19pF . . . T8 VSS GND 127m 1.45nH 0.23pF T9 VSSQ GND 151m 2.18nH 0.13pF With a call to HSpice netlist [Circuit Call] Pointer to HSpice model of package [End Circuit Call] Or [External Circuit] Pointer to HSpice model of package [End External Circuit] Allows IBIS 4.1 something like that - is IBIS 4.1 planed for something like that at all? When I take a look (please see below) on a Figure 1 provided in IBIS specs, I am not sure that it is possible. | The placement of these keywords within the hierarchy of IBIS is shown in the | following diagram: | | | |-- [Component] | | | ... | | |-- [Node Declarations] | | |-- [End Node Declarations] | | | ... | | | ... | | |-- [Circuit Call] | | |-- [End Circuit Call] | | | ... | | ... | |-- [Model] | | | ... | | |-- [External Model] | | |-- [End External Model] | | | ... | | ... | |-- [External Circuit] | |-- [End External Circuit] | | ... Has anybody some idea about it? Many thanks for every answer! Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletiæ Infineon Technologies AG MP PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@infineon.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 23 Mar 2006 09:24:22 -0800 From: "Beal, Weston" Subject: RE: [IBIS-Users] How to replace RLC package Radovan, This is precisely one of the objectives of the [external circuit] block in IBIS 4 so you surely can do what you propose in IBIS. The second step is to find an EDA vendor who supports the syntax that want to use. The [Circuit Call] and [External Circuit] blocks are used together. [External Circuit] references a SPICE circuit file for the definition of the circuit and then [Circuit Call] instantiates and connects that circuit one or more times in the IBIS component. One thing to be careful of is that you don't make the SPICE circuit include too many pins. The simulator will most likely have to simulate all the PCB nets connected to one [circuit call] and this could quickly grow to an unmanageable simulation. When you find your EDA vendor that supports this syntax, you should contact the technical marketing engineer or application engineer or customer support engineer for help in creating your first IBIS component. This first one can be confusing, but after you get the concept firm in your mind it's pretty easy, like learning logarithms. Regards, Weston The content of this message is my personal opinion only and although I am an employee of Intel, the statements I make here in no way represent Intel's position on the issue, nor am I authorized to speak on behalf of Intel on this matter. - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Radovan.Vuletic@infineon.com Sent: Thursday, March 23, 2006 8:15 AM To: ibis-users@eda.org Subject: [IBIS-Users] How to replace RLC package Hi experts, once again (almost) the same question, but now other way around ... Recently I am getting lot of pressure to figure out how (in which format) to generate reasonable package model for IBIS models of our components. Possible solutions: ============== 1.) [Sparse Matrix] - contra: tools that generate [Sparse Matrix] models can't generate models for multidrop networks (i.e. one pin one the input, more than one pads on output), sloppy support from simulation tools 2.) ICM - contra: no available tool for automated extraction (and nobody wants to do it manually :-(((() 3.) Simple RLC parameters - contra: no information about cross-coupling RLC elements (coupling capacitances, mutual inductances, etc.) Workaround: use HSpice model of package, but how to "connect" it with IBIS model? IBIS 4.1 provides new keywords [External Circuit], [End External Circuit], [External Model], [End External Model] [Node Declarations], [End Node Declarations], [Circuit Call] and [End Circuit Call] to support multi-lingual models - nice! Main question: Is there a possibility to replace package description in [Pin] section of [Component] with some [External Circuit] or [External Model] or [Node Declarations]? So what I want to do is to replace: [Pin] signal_name model_name R_pin L_pin C_pin | A1 VDD POWER 210m 4.07nH 0.27pF A2 NF NF_INPUT 168m 2.70nH 0.19pF . . . T8 VSS GND 127m 1.45nH 0.23pF T9 VSSQ GND 151m 2.18nH 0.13pF With a call to HSpice netlist [Circuit Call] Pointer to HSpice model of package [End Circuit Call] Or [External Circuit] Pointer to HSpice model of package [End External Circuit] Allows IBIS 4.1 something like that - is IBIS 4.1 planed for something like that at all? When I take a look (please see below) on a Figure 1 provided in IBIS specs, I am not sure that it is possible. | The placement of these keywords within the hierarchy of IBIS is shown in the | following diagram: | | | |-- [Component] | | | ... | | |-- [Node Declarations] | | |-- [End Node Declarations] | | | ... | | | ... | | |-- [Circuit Call] | | |-- [End Circuit Call] | | | ... | | ... | |-- [Model] | | | ... | | |-- [External Model] | | |-- [End External Model] | | | ... | | ... | |-- [External Circuit] | |-- [End External Circuit] | | ... Has anybody some idea about it? Many thanks for every answer! Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletiæ Infineon Technologies AG MP PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@infineon.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 23 Mar 2006 12:14:05 -0800 From: "Lynne D. Green" Subject: RE: [IBIS-Users] How to replace RLC package Hello, Radovan, One could look into ICM Nodal or Path models. ICM s-parameters can be built from the RLC values, or any of the EDA extraction tools that can generate Touchstone files. These solutions are supported by most IBIS EDA tools. As an alternative, some EDA tools (HSPICE, Mentor, and Cadence come to mind) allow SPICE (RLC, Tline) subcircuits (netlists, models) to be used with IBIS buffer models. This does limit the choice of tools, since external SPICE subcircuits are not supported by all IBIS EDA tools. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Radovan.Vuletic@infineon.com Sent: Thursday, March 23, 2006 8:15 AM To: ibis-users@eda.org Subject: [IBIS-Users] How to replace RLC package Hi experts, once again (almost) the same question, but now other way around ... Recently I am getting lot of pressure to figure out how (in which format) to generate reasonable package model for IBIS models of our components. Possible solutions: ============== 1.) [Sparse Matrix] - contra: tools that generate [Sparse Matrix] models can't generate models for multidrop networks (i.e. one pin one the input, more than one pads on output), sloppy support from simulation tools 2.) ICM - contra: no available tool for automated extraction (and nobody wants to do it manually :-(((() 3.) Simple RLC parameters - contra: no information about cross-coupling RLC elements (coupling capacitances, mutual inductances, etc.) Workaround: use HSpice model of package, but how to "connect" it with IBIS model? IBIS 4.1 provides new keywords [External Circuit], [End External Circuit], [External Model], [End External Model] [Node Declarations], [End Node Declarations], [Circuit Call] and [End Circuit Call] to support multi-lingual models - nice! Main question: Is there a possibility to replace package description in [Pin] section of [Component] with some [External Circuit] or [External Model] or [Node Declarations]? So what I want to do is to replace: [Pin] signal_name model_name R_pin L_pin C_pin | A1 VDD POWER 210m 4.07nH 0.27pF A2 NF NF_INPUT 168m 2.70nH 0.19pF . . . T8 VSS GND 127m 1.45nH 0.23pF T9 VSSQ GND 151m 2.18nH 0.13pF With a call to HSpice netlist [Circuit Call] Pointer to HSpice model of package [End Circuit Call] Or [External Circuit] Pointer to HSpice model of package [End External Circuit] Allows IBIS 4.1 something like that - is IBIS 4.1 planed for something like that at all? When I take a look (please see below) on a Figure 1 provided in IBIS specs, I am not sure that it is possible. | The placement of these keywords within the hierarchy of IBIS is shown | in the following diagram: | | | |-- [Component] | | | ... | | |-- [Node Declarations] | | |-- [End Node Declarations] | | | ... | | | ... | | |-- [Circuit Call] | | |-- [End Circuit Call] | | | ... | | ... | |-- [Model] | | | ... | | |-- [External Model] | | |-- [End External Model] | | | ... | | ... | |-- [External Circuit] | |-- [End External Circuit] | | ... Has anybody some idea about it? Many thanks for every answer! Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletiæ Infineon Technologies AG MP PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@infineon.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 23 Mar 2006 13:53:41 -0800 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] How to replace RLC package Radovan, Thank you for your questions on IBIS. Both you and Weston have highlighted approaches that are available under IBIS 4.1. I would like to add a few details, to illustrate some of the concerns about packages under IBIS and how improvements now in planning will address your concerns. 1) You are correct that the approaches under IBIS may not address all possibilities. A simple description of the options is: a) [Pin] - each pin may have a lumped RLC circuit; does not cover corner cases, distributed t-lines or coupling b) [Package] - the entire component may have lumped RLC package circuit descriptions; covers corners, but not distributed t-lines or coupling c) [Package Model] - through .pkg, pins have distributed frequency-independent t-lines as packages, but without coupling. The same keyword can also support .pkg files with matrix data for coupling; however these matrices are frequency-independent and permit only one matrix for the entire path from pad to pin. All of the above formats assume a 1-to-1 mapping between die pads and package pins. ICM supports frequency-dependent RLGC tables along with S-parameter data, and is not limited to any particular endpoint-to-endpoint mapping scheme. You can see more information on the history of IBIS package solutions, along with ICM as a new option, at: http://www.eda.org/ibis/summits/oct03/mirmak2.pdf 2) At this point, ICM represents the best option for long-term support of complex package structures in a behavioral, standard way. Today, connections between ICM and IBIS files are left to individual tools to support. The IBIS Futures Task Group is working weekly on an update to directly link the two specifications, anticipated for IBIS 5.0. I should note that IBIS 4.1's multilingual extensions (in this case, [Circuit Call] and [External Circuit]) were intended for use with Berkeley SPICE. Proprietary SPICE variants are not supported by the parser or the specification. 3) Note that, while the [Package] keyword is required under IBIS 4.1, the data can consist of zeroes. In many cases, model authors who use [Package Model] and/or .pkg data do just that, as [Pin] and [Package] data is overridden when [Package Model] is present. Also, note that the package information listed in the [Pin] keyword is optional as well; it does not have to be listed at all. As Weston noted, your proposal for removing the package data under [Pin] and replacing it with [Circuit Call]/[External Circuit] is perfectly valid. If you were to "zero out" the [Package] keyword, you could include all package details in such a set of External Circuits, modeled in Berkeley SPICE or the AMS languages. Please consult your EDA tool vendor(s) for information on how IBIS 4.1 is supported within their products. The IBIS community recognizes that today's package options under IBIS may not be appropriate for all applications. IBIS 4.1 and ICM are specifically targeted, along with the IBIS 4.2 and IBIS 5.0 drafts in progress, to enable package interconnect solutions for today's needs and for the future. I hope this helps! - - Michael Mirmak Intel Corporation Chair, EIA IBIS Open Forum - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Radovan.Vuletic@infineon.com Sent: Thursday, March 23, 2006 8:15 AM To: ibis-users@eda.org Subject: [IBIS-Users] How to replace RLC package Hi experts, once again (almost) the same question, but now other way around ... Recently I am getting lot of pressure to figure out how (in which format) to generate reasonable package model for IBIS models of our components. Possible solutions: ============== 1.) [Sparse Matrix] - contra: tools that generate [Sparse Matrix] models can't generate models for multidrop networks (i.e. one pin one the input, more than one pads on output), sloppy support from simulation tools 2.) ICM - contra: no available tool for automated extraction (and nobody wants to do it manually :-(((() 3.) Simple RLC parameters - contra: no information about cross-coupling RLC elements (coupling capacitances, mutual inductances, etc.) Workaround: use HSpice model of package, but how to "connect" it with IBIS model? IBIS 4.1 provides new keywords [External Circuit], [End External Circuit], [External Model], [End External Model] [Node Declarations], [End Node Declarations], [Circuit Call] and [End Circuit Call] to support multi-lingual models - nice! Main question: Is there a possibility to replace package description in [Pin] section of [Component] with some [External Circuit] or [External Model] or [Node Declarations]? So what I want to do is to replace: [Pin] signal_name model_name R_pin L_pin C_pin | A1 VDD POWER 210m 4.07nH 0.27pF A2 NF NF_INPUT 168m 2.70nH 0.19pF . . . T8 VSS GND 127m 1.45nH 0.23pF T9 VSSQ GND 151m 2.18nH 0.13pF With a call to HSpice netlist [Circuit Call] Pointer to HSpice model of package [End Circuit Call] Or [External Circuit] Pointer to HSpice model of package [End External Circuit] Allows IBIS 4.1 something like that - is IBIS 4.1 planed for something like that at all? When I take a look (please see below) on a Figure 1 provided in IBIS specs, I am not sure that it is possible. | The placement of these keywords within the hierarchy of IBIS is shown in the | following diagram: | | | |-- [Component] | | | ... | | |-- [Node Declarations] | | |-- [End Node Declarations] | | | ... | | | ... | | |-- [Circuit Call] | | |-- [End Circuit Call] | | | ... | | ... | |-- [Model] | | | ... | | |-- [External Model] | | |-- [End External Model] | | | ... | | ... | |-- [External Circuit] | |-- [End External Circuit] | | ... Has anybody some idea about it? Many thanks for every answer! Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletiæ Infineon Technologies AG MP PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@infineon.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 24 Mar 2006 15:35:22 +0100 From: Subject: RE: [IBIS-Users] How to replace RLC package This is a multi-part message in MIME format. - ------_=_NextPart_001_01C64F50.2E9F6122 Content-Type: text/plain; charset="ISO-8859-2" Content-Transfer-Encoding: quoted-printable Many thanks to Weston, Lynn and Michael who have answered on my = question. Unfortunately, since in IBIS specs 4.1 there is no example for that what = I need (of course, it is not possible to cover everything) I have = created a small (very simplified) component IBIS model where I have = replaced (at least that is what I think) lumped RLC in [Pin] section = with external HSpice circuit that contains RLC couplings. Could you please take a look on it (below) and verify that I am thinking = correctly (especial for the section where is a call external circuit). = To keep it short as possible I have deleted [Pulldown], [Pullup], = [GND_Clamp], [Power_Clamp], [Ramp], [Rising Waveform] and [Falling = Waveform] - you can find the whole IBIS file (test.ibs) in the = attachment, as well as HSpice model of package (test_package.net). Btw. = I have checked the IBIS model spelling checker IBISCHK4 V4.1.1 and there = are no warnings or errors - but still, I am not sure that I have done = everything properly ... Somehow I have a feeling that I am missing a = point. Unfortunately, I can't test it with simulator, because I have = first to find one that supports IBIS 4.1. - once agin, many thanks for = any answer. [IBIS ver] 4.1 [File name] test.ibs [File Rev] 1.0 [Date] Friday, 24 March 2006=20 [Source] Simulation of a silicon level SPICE model=20 [Notes] Test model for checking IBIS 4.1 Multi-lingual Model Extensions [Disclaimer] Just a test [Copyright] (C) Copyright 2006 by Unknown=20 | |************************************************************************= | Component XYZ |************************************************************************= | [Component] XXX [Manufacturer] Unknown | [Package] | typ min max R_pkg 2.0E-01Ohm 1.0E-01Ohm 3.0E-01Ohm =20 L_pkg 2.0E-09H 1.0E-09H 3.0E-09H =20 C_pkg 2.0E-13F 1.0E-13F 3.0E-13F =20 | [Pin] signal_name model_name R_pin L_pin = C_pin | A1 VDDQ_A1 POWER 1.0E-01 1.0E-09 1.0E-13 A2 DQ Data_IO 2.0E-01 2.0E-09 = 2.0E-13 A3 VSSQ_A3 GND 3.0E-01 3.0E-09 3.0E-13 [Circuit Call] TEST_PACKAGE Port_map vddq_pad_a1 A1 Port_map dq_pad_a2 A2 Port_map vssq_pad_a3 A3 Port_map vddq_ball_a1 A1 Port_map dq_ball_a2 A2 Port_map vssq_ball_a3 A3=20 Port_map pkg_ref_gnd A3 [End Circuit Call] | |************************************************************************= | Model Data_IO |************************************************************************= | [Model] Data_IO Model_type I/O Polarity Non-Inverting Enable Active-High [Pulldown] [Pullup] [GND_clamp] [POWER_clamp] [Ramp] [Rising Waveform] [Rising Waveform] [Falling Waveform] [Falling Waveform] | | End [Component] XYZ | [External Circuit] TEST_PACKAGE Language SPICE Corner Typ test_package.net package_test Ports vddq_ball_a1 dq_ball_a2 vssq_ball_a3 vddq_pad_a1 dq_pad_a2 = vssq_pad_a3 pkg_ref_gnd [End External Circuit] [End] Regards, Radovan - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On = Behalf Of Vuletic Radovan (MP PD PDE) Sent: Thursday, March 23, 2006 5:15 PM To: ibis-users@eda.org Subject: [IBIS-Users] How to replace RLC package Hi experts, once again (almost) the same question, but now other way around ... Recently I am getting lot of pressure to figure out how (in which = format) to generate reasonable package model for IBIS models of our = components. Possible solutions: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 1.) [Sparse Matrix] - contra: tools that generate [Sparse Matrix] models = can't generate models for multidrop networks (i.e. one pin one the = input, more than one pads on output), sloppy support from simulation = tools 2.) ICM - contra: no available tool for automated extraction (and nobody = wants to do it manually :-(((() 3.) Simple RLC parameters - contra: no information about cross-coupling = RLC elements (coupling capacitances, mutual inductances, etc.) Workaround: use HSpice model of package, but how to "connect" it with = IBIS model? IBIS 4.1 provides new keywords [External Circuit], [End External = Circuit], [External Model], [End External Model] [Node Declarations], = [End Node Declarations], [Circuit Call] and [End Circuit Call] to = support multi-lingual models - nice!=20 Main question: Is there a possibility to replace package description in [Pin] section = of [Component] with some [External Circuit] or [External Model] or [Node = Declarations]? So what I want to do is to replace: [Pin] signal_name model_name R_pin L_pin C_pin | A1 VDD POWER 210m 4.07nH 0.27pF A2 NF NF_INPUT 168m 2.70nH 0.19pF . . . T8 VSS GND 127m 1.45nH 0.23pF T9 VSSQ GND 151m 2.18nH 0.13pF With a call to HSpice netlist [Circuit Call] Pointer to HSpice model of package [End Circuit Call] Or=20 [External Circuit] Pointer to HSpice model of package [End External Circuit] Allows IBIS 4.1 something like that - is IBIS 4.1 planed for something = like that at all? When I take a look (please see below) on a Figure 1 provided in IBIS = specs, I am not sure that it is possible. | The placement of these keywords within the hierarchy of IBIS is shown=20 | in the following diagram: | | | |-- [Component] | | | ... | | |-- [Node Declarations] | | |-- [End Node Declarations] | | | ... | | | ... | | |-- [Circuit Call] | | |-- [End Circuit Call] | | | ... | | ... | |-- [Model] | | | ... | | |-- [External Model] | | |-- [End External Model] | | | ... | | ... | |-- [External Circuit] | |-- [End External Circuit] | | ... Has anybody some idea about it? Many thanks for every answer! Best regards / Mit freundlichen Gr=FC=DFen / S po=B9tovanjem Radovan = Vuleti=E6 Infineon Technologies AG MP PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305=20 E-mail: radovan.vuletic@infineon.com |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org with just = |the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent =20 | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 - ------_=_NextPart_001_01C64F50.2E9F6122 Content-Type: application/octet-stream; name="test_package.net" Content-Transfer-Encoding: base64 Content-Description: test_package.net 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|IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 24 Mar 2006 16:00:15 +0100 From: "Koller, Katja" Subject: AW: [IBIS-Users] How to replace RLC package Hello Radovan, as far as I have looked at the keyword External Model and packages I found the possibility to use Series Elements. But unfortunately they are not yet supported by our simulation tool... As for your Circuit Call I think you attached a package to the pins for vcc and gnd, but not on the pin with the IO. Well, yes it is attached, but in parallel and not as series. With circuit call I can think at the moment only to include the spice-package into the hspice-model. Regards, Katja > -----Ursprüngliche Nachricht----- > Von: owner-ibis-users@eda.org > [mailto:owner-ibis-users@eda.org] Im Auftrag von > Radovan.Vuletic@infineon.com > Gesendet: Freitag, 24. März 2006 15:35 > An: ibis-users@eda.org > Betreff: RE: [IBIS-Users] How to replace RLC package > > Many thanks to Weston, Lynn and Michael who have answered on > my question. > > Unfortunately, since in IBIS specs 4.1 there is no example > for that what I need (of course, it is not possible to cover > everything) I have created a small (very simplified) > component IBIS model where I have replaced (at least that is > what I think) lumped RLC in [Pin] section with external > HSpice circuit that contains RLC couplings. > Could you please take a look on it (below) and verify that I > am thinking correctly (especial for the section where is a > call external circuit). To keep it short as possible I have > deleted [Pulldown], [Pullup], [GND_Clamp], [Power_Clamp], > [Ramp], [Rising Waveform] and [Falling Waveform] - you can > find the whole IBIS file (test.ibs) in the attachment, as > well as HSpice model of package (test_package.net). Btw. I > have checked the IBIS model spelling checker IBISCHK4 V4.1.1 > and there are no warnings or errors - but still, I am not > sure that I have done everything properly ... Somehow I have > a feeling that I am missing a point. Unfortunately, I can't > test it with simulator, because I have first to find one that > supports IBIS 4.1. - once agin, many thanks for any answer. > > [IBIS ver] 4.1 > [File name] test.ibs > [File Rev] 1.0 > [Date] Friday, 24 March 2006 > [Source] Simulation of a silicon level SPICE model > [Notes] Test model for checking IBIS 4.1 Multi-lingual > Model Extensions > [Disclaimer] Just a test > [Copyright] (C) Copyright 2006 by Unknown > | > |************************************************************* > *********** > | Component XYZ > |************************************************************* > *********** > | > [Component] XXX > [Manufacturer] Unknown > | > [Package] > | typ min max > R_pkg 2.0E-01Ohm 1.0E-01Ohm 3.0E-01Ohm > L_pkg 2.0E-09H 1.0E-09H 3.0E-09H > C_pkg 2.0E-13F 1.0E-13F 3.0E-13F > | > [Pin] signal_name model_name R_pin L_pin > C_pin > | > A1 VDDQ_A1 POWER 1.0E-01 1.0E-09 1.0E-13 > A2 DQ Data_IO 2.0E-01 > 2.0E-09 2.0E-13 > A3 VSSQ_A3 GND 3.0E-01 3.0E-09 > 3.0E-13 > [Circuit Call] TEST_PACKAGE > Port_map vddq_pad_a1 A1 > Port_map dq_pad_a2 A2 > Port_map vssq_pad_a3 A3 > Port_map vddq_ball_a1 A1 > Port_map dq_ball_a2 A2 > Port_map vssq_ball_a3 A3 > Port_map pkg_ref_gnd A3 > [End Circuit Call] > | > |************************************************************* > *********** > | Model Data_IO > |************************************************************* > *********** > | > [Model] Data_IO > Model_type I/O > Polarity Non-Inverting > Enable Active-High > [Pulldown] > [Pullup] > [GND_clamp] > [POWER_clamp] > [Ramp] > [Rising Waveform] > [Rising Waveform] > [Falling Waveform] > [Falling Waveform] > | > | End [Component] XYZ > | > [External Circuit] TEST_PACKAGE > Language SPICE > Corner Typ test_package.net package_test > Ports vddq_ball_a1 dq_ball_a2 vssq_ball_a3 vddq_pad_a1 > dq_pad_a2 vssq_pad_a3 pkg_ref_gnd > [End External Circuit] > [End] > > Regards, > Radovan > > -----Original Message----- > From: owner-ibis-users@eda.org > [mailto:owner-ibis-users@eda.org] On Behalf Of Vuletic > Radovan (MP PD PDE) > Sent: Thursday, March 23, 2006 5:15 PM > To: ibis-users@eda.org > Subject: [IBIS-Users] How to replace RLC package > > Hi experts, > > once again (almost) the same question, but now other way around ... > > Recently I am getting lot of pressure to figure out how (in > which format) to generate reasonable package model for IBIS > models of our components. > > Possible solutions: > ============== > 1.) [Sparse Matrix] - contra: tools that generate [Sparse > Matrix] models can't generate models for multidrop networks > (i.e. one pin one the input, more than one pads on output), > sloppy support from simulation tools > 2.) ICM - contra: no available tool for automated extraction > (and nobody wants to do it manually :-(((() > 3.) Simple RLC parameters - contra: no information about > cross-coupling RLC elements (coupling capacitances, mutual > inductances, etc.) > > Workaround: use HSpice model of package, but how to "connect" > it with IBIS model? > > IBIS 4.1 provides new keywords [External Circuit], [End > External Circuit], [External Model], [End External Model] > [Node Declarations], [End Node Declarations], [Circuit Call] > and [End Circuit Call] to support multi-lingual models - nice! > Main question: > Is there a possibility to replace package description in > [Pin] section of [Component] with some [External Circuit] or > [External Model] or [Node Declarations]? > So what I want to do is to replace: > [Pin] signal_name model_name R_pin L_pin C_pin > | > A1 VDD POWER 210m 4.07nH 0.27pF > A2 NF NF_INPUT 168m 2.70nH 0.19pF > . > . > . > T8 VSS GND 127m 1.45nH 0.23pF > T9 VSSQ GND 151m 2.18nH 0.13pF > > With a call to HSpice netlist > > [Circuit Call] > Pointer to HSpice model of package > [End Circuit Call] > > Or > > [External Circuit] > Pointer to HSpice model of package > [End External Circuit] > > Allows IBIS 4.1 something like that - is IBIS 4.1 planed for > something like that at all? > > When I take a look (please see below) on a Figure 1 provided > in IBIS specs, I am not sure that it is possible. > > | The placement of these keywords within the hierarchy of > IBIS is shown > | in the following diagram: > | > | > | |-- [Component] > | | | ... > | | |-- [Node Declarations] > | | |-- [End Node Declarations] > | | | ... > | | | ... > | | |-- [Circuit Call] > | | |-- [End Circuit Call] > | | | ... > | | ... > | |-- [Model] > | | | ... > | | |-- [External Model] > | | |-- [End External Model] > | | | ... > | | ... > | |-- [External Circuit] > | |-- [End External Circuit] > | | ... > > Has anybody some idea about it? > > Many thanks for every answer! > > Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletiæ > > Infineon Technologies AG > MP PD PDE > MUC/10.2.236 AP 3 > Am Campeon 1-12 > D-85579 Neuebiberg > > Phone: +49 (0)89 234 20108 > Fax (PC): +49 (0)89 234 955 5305 > > E-mail: radovan.vuletic@infineon.com > > |------------------------------------------------------------------ > |For help or to subscribe/unsubscribe, email > majordomo@eda.org with just > |the appropriate command message(s) in the body: > | > | help > | subscribe ibis > | subscribe ibis-users > | unsubscribe ibis > | unsubscribe ibis-users > | > |or email a written request to ibis-request@eda.org. > | > |IBIS reflector archives exist under: > | > | http://www.eda.org/pub/ibis/email_archive/ Recent > | http://www.eda.org/pub/ibis/users_archive/ Recent > | http://www.eda.org/pub/ibis/email/ E-mail since 1993 > |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 24 Mar 2006 09:22:14 -0800 From: "Mirmak, Michael" Subject: [IBIS-Users] Agenda, IBIS Open Forum teleconference for March 31, 2006 IBIS Open Forum Meeting Agenda for March 31, 2006 Telephone Number Bridge Passcode 1-916-356-2663 4 546-0115 All meetings are 8:00 AM to 9:55 AM US Pacific Time. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international numbers, please contact Michael Mirmak. 8:00 Check-In, Intros, Announcements Mirmak - Intros of New IBIS Participants, Meeting Quorum Mirmak - Call for Patents Mirmak - Membership Status and Treasurer's Report Mirmak - Review of Previous Meeting's Minutes (and ARs) Mirmak March 10, 2006 Summit Minutes - Web Page Updates Huq - Mailing List Administration Ross * IBIS vs. IBIS Users? - Model Library Update Wang - Announcements, Opens for New Issues All 8:15 Project Discussions and Subcommittee Reports International/External Progress All EIA, ANSI Approval Activities Wolff Summit Status All - DATE Summit Review - Summits in Asia Task Group Reports - Quality LaBonte - Model Review Green - Futures Mirmak - Cookbook Mirmak - Macromodeling Library Muranyi New Issues All 8:45 Technical Discussion IBIS 4.2 Draft Mirmak - Second "Reading" and Call for Comment BIRD97.2: Gate Modulation Effect Muranyi BIRD98: Gate Modulation Effect (table format) Muranyi IBISCHK4 BUG Status All ICMCHK1 BUG Status All New Technical Issues All 9:50 Wrap Up and Next Meeting Plans Mirmak - March 31, 2006 IBIS Open Forum Teleconference 9:55 Sign Off |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 24 Mar 2006 11:01:13 -0700 From: rrwolff@micron.com Subject: [IBIS-Users] [IBIS] Open forum Summit minutes (03/10/06) This is a multi-part message in MIME format. - ------_=_NextPart_001_01C64F6C.F0883CB0 Content-Type: multipart/alternative; boundary="----_=_NextPart_002_01C64F6C.F0883CB0" - ------_=_NextPart_002_01C64F6C.F0883CB0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Attached are the minutes of the Friday, March 10, 2006 IBIS Open Forum DATE Summit. Randy Wolff IBIS Open Forum Secretary <>=20 - ------_=_NextPart_002_01C64F6C.F0883CB0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [IBIS] Open forum Summit minutes (03/10/06)

Attached are the minutes of the = Friday, March 10, 2006 IBIS Open Forum DATE Summit.

Randy Wolff
IBIS Open Forum Secretary

= <<m031006s.txt>>

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http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 27 Mar 2006 14:09:50 -0500 From: "Ambrish Varma" Subject: [IBIS-Users] S2IBIS3 Ver 1.1 Released This is a multi-part message in MIME format. - ------=_NextPart_000_0218_01C651A8.23F5E170 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hello, A new bug fix release of S2IBIS3 is available at http://www.ece.ncsu.edu/erl/ibis/s2ibis3/s2ibis3.htm . The main fixes are: 1) Changes done to make 100 points in the VI tables (the number of points has been made a function of the sweep step). 2) Remove use of tab characters while printing the ibis file. 3) Change VinL to Vinl and VinH to Vinh. 4) Change: SWEEP_STEP_DEFAULT to 0.01. 5) Change: MAX_FILENAME_BASE_LENGTH value to 20 if you plan to use IBIS spec 3.2 6) Change: WAVE_POINTS_DEFAULT =100; (initially this was assigned to 51). 7) Corrected min and max [Ramp] calculation (The simulations for Ramp vary voltage and temperature across min, typ, and max, but all three use typ process libraries.) 8) Corrected the I/O_open_drain keyword. Used to show I_O_open_drain in the generated IBIS file. 9) Fixed pulse generation for ELDO for transient runs (corrected the narrow pulses for the transient runs) Thanks to Mike LaBonte (Cisco) and Jayasree Nayar (Cypress) for making a lot of valuable bug fixes themselves. Also thanks to Dave Lawson (BAE) and Ken Knowles (BAE) for helping in do some crucial testing for the latest release. A lot of valuable suggestions were also made by Charles Sun (IDT), Paul Tuinenga (Mentor), Christophe Robichon (Atmel) and Eric Hsu (Interface Technologies) to name a few. The setup procedure for this latest release remains the same. I have also made a new S2IBIS3 FAQ page that has a lot of questions that I have answered over the months of supporting s2ibis3. Many of these questions are related to setting up s2ibis3 - and I generally receive the same ones over and over again - hence the idea of an FAQ. The FAQ page can be viewed at http://www.ece.ncsu.edu/erl/ibis/faq/S2IBIS3_FAQ.htm Regards, Ambrish. - --Ambrish Varma North Carolina State University ph(919)513-2015, fax(919)515-2285 - ------=_NextPart_000_0218_01C651A8.23F5E170 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hello,

A new bug fix release of S2IBIS3 is available at http://www.= ece.ncsu.edu/erl/ibis/s2ibis3/s2ibis3.htm .

The main fixes are:

 

1) Changes done to make 100 points in the VI tables = (the number of points has been made a function of the sweep = step).

2) Remove use of tab characters while printing the = ibis file.

3) Change VinL to Vinl and VinH to = Vinh.

4) Change: SWEEP_STEP_DEFAULT to = 0.01.

5) Change: MAX_FILENAME_BASE_LENGTH value to 20 if = you plan to use IBIS spec 3.2

6) Change: WAVE_POINTS_DEFAULT  = =3D100;   (initially this was assigned to 51).

7) Corrected min and max [Ramp] calculation (The = simulations for Ramp vary voltage and temperature across min, typ, and max, but all = three use typ process libraries.)

8) Corrected the I/O_open_drain keyword. Used to show I_O_open_drain in the generated IBIS file.

9) Fixed pulse generation for ELDO for transient runs = (corrected the narrow pulses for the transient runs)

 

Thanks to Mike LaBonte (Cisco) and Jayasree Nayar = (Cypress) for = making a lot of valuable bug fixes themselves.  Also thanks to Dave Lawson (BAE) = and Ken Knowles (BAE) for helping in do some crucial testing for the latest = release.

A lot of valuable suggestions were also made by = Charles Sun (IDT), Paul Tuinenga (Mentor), Christophe Robichon (Atmel) and Eric Hsu = (Interface Technologies) to name a few.

 

The setup procedure for this latest release remains = the same.

 

I have also made a new S2IBIS3 FAQ page that has a = lot of questions that I have answered over the months of supporting s2ibis3. Many of = these questions are related to setting up s2ibis3 – and I generally = receive the same ones over and over again – hence the idea of an = FAQ.

The FAQ page can be viewed at http://www.= ece.ncsu.edu/erl/ibis/faq/S2IBIS3_FAQ.htm

 

Regards,

Ambrish.

 

--Ambrish = Varma

North = Carolina State University

ph(919)513-2015, fax(919)515-2285

 

- ------=_NextPart_000_0218_01C651A8.23F5E170-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 28 Mar 2006 14:14:17 +0200 From: Fabio BRINA Subject: [IBIS-Users] multiplexer - --------------070903050809030101070107 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Hi to all, Can I modeling a Multiplexer in Pass-transistor technology with IBIS ? Have you any suggestions ? many thanks. Fabio - --------------070903050809030101070107 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit  
Hi to all,

Can I modeling a  Multiplexer in Pass-transistor
technology with IBIS ?
Have you any suggestions ?

many thanks.

Fabio
- --------------070903050809030101070107-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 28 Mar 2006 08:34:41 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] multiplexer This is a multi-part message in MIME format. - ------_=_NextPart_001_01C65285.837FF23B Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Fabio, =20 You may be able to make a model for that using the [Series MOSFET] keyword. =20 Arpad Muranyi Intel Corporation =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On = Behalf Of Fabio BRINA Sent: Tuesday, March 28, 2006 4:14 AM To: ibis-users@eda.org; ibis@eda.org Subject: [IBIS-Users] multiplexer =20 Hi to all, Can I modeling a Multiplexer in Pass-transistor=20 technology with IBIS ? Have you any suggestions ? many thanks. Fabio - ------_=_NextPart_001_01C65285.837FF23B Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Fabio,
 
You may be able to make a model for that = using=20 the
[Series MOSFET] keyword.
 
Arpad Muranyi
Intel Corporation
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Fabio=20 BRINA
Sent: Tuesday, March 28, 2006 4:14 AM
To:=20 ibis-users@eda.org; ibis@eda.org
Subject: [IBIS-Users]=20 multiplexer

 
Hi to=20 all,

Can I modeling a  Multiplexer in Pass-transistor=20
technology with IBIS ?
Have you any suggestions ?

many = thanks.

Fabio
- ------_=_NextPart_001_01C65285.837FF23B-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 06 Apr 2006 10:23:04 +0000 From: "lau yy" Subject: [IBIS-Users] Warning message for MISMATCH This is a multi-part message in MIME format. - ------=_NextPart_000_23c7_651_110d Content-Type: text/html; format=flowed
Hi ALL,
 
Below I attach a model for an IO pin. The model pass with warning. I show 1 of the warning message as below:
 
WARNING - Model IO: The [Falling Waveform]
      with [R_fixture]=50 Ohms and [V_fixture_max]=3.6V
      has MAX column DC endpoints of  1.98V and  3.53v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.94V and  3.39V),
      a difference of  2.36% and  3.96%, respectively.
I study the rising and falling datas, can see that the pin is already stable but is just the voltage level can fall to 0 or reach VCC. Is this a design issue or modeling issue? I belive that is the pullup and pulldown transistor not strong enough. Am I right?
 
PLease comment.
 
Thanks
 
rdgs
yylau
- ------=_NextPart_000_23c7_651_110d Content-Type: text/plain; name="io"; format=flowed Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="io" |************************************************************************ | Model IO |************************************************************************ | [Model] IO Model_type I/O Vinl = 0.4000V Vinh = 1.3000V Vmeas = 1.5000V Cref = 50.0000pF C_comp 2.0000pF 2.0000pF 2.0000pF | | [Temperature Range] 25.0000 85.0000 -40.0000 [Pullup Reference] 3.3000V 2.7000V 3.6000V [Pulldown Reference] 0.000V 0.000V 0.000V [POWER Clamp Reference] 3.3000V 2.7000V 3.6000V [GND Clamp Reference] 0.000V 0.000V 0.000V [Pulldown] | voltage I(typ) I(min) I(max) | -3.3000 0.000A 0.000A 0.000A -3.1000 0.000A 0.000A 0.000A -2.9000 0.000A 0.000A 0.000A -2.7000 0.000A 0.000A 0.000A -2.5000 0.000A 0.000A 0.000A -2.3000 0.000A 0.000A 0.000A -2.1000 0.000A 0.000A -1.0000mA -1.9000 0.000A 0.000A -1.0000mA -1.7000 0.000A 0.000A 0.000A -1.5000 -1.0000mA -1.0000mA 0.000A -1.0000 -2.0000mA -1.0000mA -2.0000mA -0.9000 -2.2000mA -2.0000mA -5.3000mA -0.8000 -5.1000mA -2.2000mA -10.6670mA -0.7000 -9.3500mA -4.4000mA -10.1710mA -0.6000 -8.8025mA -7.2900mA -9.1316mA -0.5000 -7.4200mA -6.7890mA -7.7418mA -0.4000 -5.9456mA -5.4797mA -6.2082mA -0.3000 -4.4607mA -4.1134mA -4.6579mA -0.2000 -2.9747mA -2.7422mA -3.1057mA -0.1000 -1.4876mA -1.3714mA -1.5534mA 0.0000 30.0000nA 30.0000nA 40.0000nA 0.1000 1.4868mA 1.3692mA 1.5532mA 0.2000 2.9722mA 2.7351mA 3.1046mA 0.3000 4.4558mA 4.0974mA 4.6560mA 0.4000 5.9385mA 5.4552mA 6.2055mA 0.5000 7.4184mA 6.8085mA 7.7551mA 0.6000 8.8974mA 8.1583mA 9.3027mA 0.7000 10.3776mA 9.5037mA 10.8554mA 0.8000 11.8470mA 10.8427mA 12.3981mA 0.9000 13.3266mA 12.1763mA 13.9409mA 1.0000 14.7963mA 13.5105mA 15.4838mA 1.1000 16.2662mA 14.8354mA 17.0267mA 1.2000 17.7363mA 16.1511mA 18.5700mA 1.3000 19.1970mA 17.4675mA 20.1130mA 1.4000 20.6570mA 18.7748mA 21.6560mA 1.5000 22.1180mA 20.0830mA 23.1890mA 1.6000 23.5790mA 21.3720mA 24.7330mA 1.7000 25.0400mA 22.6620mA 26.2660mA 1.8000 26.4910mA 23.9440mA 27.7990mA 1.9000 27.9430mA 25.2170mA 29.3330mA 2.0000 29.3950mA 26.4810mA 30.8670mA 2.1000 30.8470mA 27.7360mA 32.4000mA 2.2000 32.2890mA 28.9730mA 33.9340mA 2.3000 33.7320mA 30.2130mA 35.4580mA 2.4000 35.1750mA 31.4340mA 36.9920mA 2.5000 36.6080mA 32.6480mA 38.5160mA 2.6000 38.0420mA 33.8540mA 40.0400mA 2.7000 39.4760mA 35.0350mA 41.5640mA 2.8000 40.9100mA 36.2090mA 43.0890mA 2.9000 42.3350mA 37.3580mA 44.6130mA 3.0000 43.7500mA 38.4930mA 46.1380mA 3.1000 45.1750mA 39.6120mA 47.6520mA 3.2000 46.5910mA 40.6910mA 49.1670mA 3.3000 47.9970mA 41.4180mA 50.6820mA 3.4000 52.0600mA 80.9100mA 55.1200mA 3.5000 53.5300mA 0.3383A 56.7200mA 3.6000 55.0100mA 0.8398A 58.3200mA 3.7000 56.4800mA 1.4380A 59.9100mA 3.8000 57.9400mA 2.0780A 61.5000mA 3.9000 59.4400mA 2.7400A 63.1000mA 4.0000 61.8500mA 3.4150A 64.6800mA 4.1000 96.4100mA 4.0980A 66.2700mA 4.2000 0.3950A 4.7870A 67.8900mA 4.3000 0.9384A 5.4810A 69.7400mA 4.5000 2.2190A 6.8800A 0.1027A 4.7000 3.5780A 8.2870A 1.0380A 4.9000 4.9650A 9.7010A 2.3620A 5.1000 6.3680A 11.1200A 3.7430A 5.3000 7.7790A 12.5400A 5.1450A 5.5000 9.1970A 13.9600A 6.5580A 5.7000 10.6200A 15.3900A 7.9790A 5.9000 12.0400A 16.8200A 9.4040A 6.1000 13.4700A 18.2500A 10.8300A 6.6000 17.0500A 21.8300A 14.4100A | [Pullup] | voltage I(typ) I(min) I(max) | -3.3000 0.000A 0.000A 0.000A -3.1000 10.0000mA 0.000A 0.000A -2.9000 0.000A 0.000A 0.000A -2.7000 0.000A 0.000A 0.000A -2.5000 0.000A 0.000A 0.000A -2.3000 0.000A 0.000A 0.000A -2.1000 1.0000mA 0.000A 1.0000mA -1.9000 0.000A 0.000A 0.000A -1.7000 1.0000mA 0.000A 0.000A -1.5000 0.000A 1.0000mA 1.0000mA -1.0000 2.8000mA 2.0000mA 4.9000mA -0.9000 5.6000mA 2.9000mA 14.4200mA -0.8000 12.9100mA 5.5000mA 17.0130mA -0.7000 14.2850mA 10.3900mA 15.4890mA -0.6000 12.4450mA 10.6880mA 13.5240mA -0.5000 10.3920mA 8.9910mA 11.3020mA -0.4000 8.3060mA 7.1860mA 9.0480mA -0.3000 6.2270mA 5.3770mA 6.7830mA -0.2000 4.1470mA 3.5750mA 4.5180mA -0.1000 2.0680mA 1.7810mA 2.2540mA 0.0000 -7.0000uA -4.0000uA -9.0000uA 0.1000 0.4206mA -0.2005mA 0.7367mA 0.2000 -1.7180mA -2.0010mA -1.6060mA 0.3000 -3.8500mA -3.7880mA -3.9450mA 0.4000 -5.9750mA -5.5610mA -6.2800mA 0.5000 -8.0920mA -7.3190mA -8.6100mA 0.6000 -10.2000mA -9.0600mA -10.9400mA 0.7000 -12.3000mA -10.7800mA -13.2600mA 0.8000 -14.4000mA -12.4900mA -15.5800mA 0.9000 -16.4800mA -14.1700mA -17.8900mA 1.0000 -18.5600mA -15.8300mA -20.2000mA 1.1000 -20.6300mA -17.4700mA -22.5000mA 1.2000 -22.6900mA -19.0800mA -24.8000mA 1.3000 -24.7400mA -20.6700mA -27.0900mA 1.4000 -26.7800mA -22.2200mA -29.3800mA 1.5000 -28.8000mA -23.7400mA -31.6600mA 1.6000 -30.8200mA -25.2300mA -33.9400mA 1.7000 -32.8300mA -26.6800mA -36.2100mA 1.8000 -34.8200mA -28.0800mA -38.4800mA 1.9000 -36.8000mA -29.4400mA -40.7300mA 2.0000 -38.7700mA -30.7500mA -42.9900mA 2.1000 -40.7300mA -32.0000mA -45.2400mA 2.2000 -42.6700mA -33.1800mA -47.4800mA 2.3000 -44.5900mA -34.2800mA -49.7100mA 2.4000 -46.5000mA -35.3100mA -51.9400mA 2.5000 -48.3900mA -36.2400mA -54.1600mA 2.6000 -50.2700mA -37.0700mA -56.3700mA 2.7000 -52.1300mA -37.8100mA -58.5700mA 2.8000 -53.9700mA -38.4600mA -60.7700mA 2.9000 -55.7800mA -39.0400mA -62.9600mA 3.0000 -57.5800mA -39.5600mA -65.1400mA 3.1000 -59.3500mA -40.0600mA -67.3100mA 3.2000 -61.0900mA -41.1300mA -69.4800mA 3.3000 -62.8100mA -56.3900mA -71.6300mA 3.4000 -64.5000mA -0.2251A -73.7700mA 3.5000 -66.1600mA -0.6732A -75.9100mA 3.6000 -67.7900mA -1.2520A -78.0300mA 3.7000 -69.3800mA -1.8830A -80.1400mA 3.8000 -70.9300mA -2.5390A -82.2400mA 3.9000 -72.6600mA -3.2100A -84.3300mA 4.0000 -81.4600mA -3.8910A -86.4100mA 4.1000 -0.2321A -4.5790A -88.4900mA 4.2000 -0.6992A -5.2720A -90.6700mA 4.3000 -1.2980A -5.9690A -93.1800mA 4.5000 -2.6110A -7.3710A -0.2205A 4.7000 -3.9800A -8.7810A -1.3330A 4.9000 -5.3730A -10.1900A -2.6750A 5.1000 -6.7780A -11.6100A -4.0610A 5.3000 -8.1920A -13.0400A -5.4660A 5.5000 -9.6110A -14.4600A -6.8820A 5.7000 -11.0300A -15.8900A -8.3030A 5.9000 -12.4600A -17.3200A -9.7290A 6.1000 -13.8900A -18.7500A -11.1500A 6.6000 -17.4700A -22.3400A -14.7400A | [GND_clamp] | voltage I(typ) I(min) I(max) | -3.3000 -17.4700A -18.0300A -16.8900A -3.2000 -16.7500A -17.3200A -16.1700A -3.1000 -16.0300A -16.6000A -15.4500A -3.0000 -15.3200A -15.8900A -14.7400A -2.9000 -14.6000A -15.1700A -14.0200A -2.8000 -13.8800A -14.4600A -13.3000A -2.7000 -13.1700A -13.7500A -12.5800A -2.6000 -12.4600A -13.0300A -11.8700A -2.5000 -11.7400A -12.3200A -11.1500A -2.4000 -11.0300A -11.6100A -10.4400A -2.3000 -10.3200A -10.9000A -9.7280A -2.2000 -9.6100A -10.1900A -9.0140A -2.1000 -8.8990A -9.4870A -8.3010A -2.0000 -8.1900A -8.7800A -7.5900A -1.9000 -7.4820A -8.0740A -6.8790A -1.8000 -6.7760A -7.3690A -6.1710A -1.7000 -6.0720A -6.6670A -5.4640A -1.6000 -5.3700A -5.9670A -4.7590A -1.5000 -4.6710A -5.2700A -4.0580A -1.4000 -3.9770A -4.5770A -3.3610A -1.3000 -3.2880A -3.8890A -2.6700A -1.2000 -2.6060A -3.2080A -1.9880A -1.1000 -1.9370A -2.5360A -1.3230A -1.0000 -1.2880A -1.8780A -0.6930A -0.9000 -0.6826A -1.2450A -0.1726A -0.8000 -0.1937A -0.6627A -5.8730mA -0.7000 -11.5200mA -0.2033A -1.3490mA -0.6000 -0.8365mA -18.8000mA -0.7234mA -0.5000 -0.4430mA -1.1760mA -0.4752mA -0.4000 -0.3454mA -0.3323mA -0.3698mA -0.3000 -0.2623mA -0.2286mA -0.2811mA -0.2000 -0.1803mA -0.1558mA -0.1933mA -0.1000 -98.3800uA -84.6300uA -0.1056mA 0.0000 -16.5400uA -13.7300uA -17.9000uA 0.1000 65.2000uA 56.8200uA 69.7900uA 0.2000 0.1468mA 0.1269mA 0.1574mA 0.3000 0.2282mA 0.1966mA 0.2450mA 0.4000 0.3095mA 0.2658mA 0.3325mA 0.5000 0.3906mA 0.3345mA 0.4199mA 0.6000 0.4716mA 0.4027mA 0.5073mA 0.7000 0.5524mA 0.4703mA 0.5946mA 0.8000 0.6330mA 0.5373mA 0.6819mA 0.9000 0.7134mA 0.6037mA 0.7691mA 1.0000 0.7937mA 0.6695mA 0.8562mA 1.1000 0.8738mA 0.7346mA 0.9433mA 1.2000 0.9537mA 0.7989mA 1.0300mA 1.3000 1.0330mA 0.8625mA 1.1170mA 1.4000 1.1130mA 0.9252mA 1.2040mA 1.5000 1.1920mA 0.9870mA 1.2910mA 1.6000 1.2710mA 1.0480mA 1.3770mA 1.7000 1.3500mA 1.1080mA 1.4640mA 1.8000 1.4290mA 1.1660mA 1.5510mA 1.9000 1.5070mA 1.2230mA 1.6370mA 2.0000 1.5850mA 1.2790mA 1.7230mA 2.1000 1.6630mA 1.3340mA 1.8100mA 2.2000 1.7410mA 1.3870mA 1.8960mA 2.3000 1.8180mA 1.4370mA 1.9820mA 2.4000 1.8950mA 1.4860mA 2.0680mA 2.5000 1.9720mA 1.5320mA 2.1540mA 2.6000 2.0480mA 1.5760mA 2.2400mA 2.7000 2.1240mA 1.6150mA 2.3260mA 2.8000 2.2000mA 1.6510mA 2.4110mA 2.9000 2.2750mA 1.6820mA 2.4970mA 3.0000 2.3500mA 1.7070mA 2.5820mA 3.1000 2.4250mA 1.7280mA 2.6680mA 3.2000 2.4990mA 1.8190mA 2.7530mA 3.3000 2.5730mA 3.7820mA 2.8380mA | [POWER_clamp] | voltage I(typ) I(min) I(max) | -3.3000 17.0500A 17.5300A 16.5600A -3.2000 16.3300A 16.8200A 15.8400A -3.1000 15.6100A 16.1000A 15.1300A -3.0000 14.9000A 15.3900A 14.4100A -2.9000 14.1800A 14.6800A 13.6900A -2.8000 13.4700A 13.9600A 12.9700A -2.7000 12.7500A 13.2500A 12.2600A -2.6000 12.0400A 12.5400A 11.5400A -2.5000 11.3300A 11.8300A 10.8300A -2.4000 10.6100A 11.1100A 10.1100A -2.3000 9.9070A 10.4000A 9.4030A -2.2000 9.1960A 9.7000A 8.6900A -2.1000 8.4860A 8.9920A 7.9770A -2.0000 7.7780A 8.2860A 7.2660A -1.9000 7.0710A 7.5810A 6.5570A -1.8000 6.3660A 6.8780A 5.8490A -1.7000 5.6630A 6.1780A 5.1430A -1.6000 4.9630A 5.4800A 4.4400A -1.5000 4.2670A 4.7850A 3.7400A -1.4000 3.5750A 4.0960A 3.0450A -1.3000 2.8900A 3.4120A 2.3580A -1.2000 2.2150A 2.7370A 1.6820A -1.1000 1.5560A 2.0740A 1.0300A -1.0000 0.9282A 1.4320A 0.4330A -0.9000 0.3742A 0.8303A 47.1500mA -0.8000 47.4400mA 0.3199A 5.1870mA -0.7000 4.3950mA 44.5700mA 4.0310mA -0.6000 3.0550mA 3.7820mA 3.6460mA -0.5000 2.9380mA 1.8190mA 3.5180mA -0.4000 2.8640mA 1.7280mA 3.4320mA -0.3000 2.7920mA 1.7070mA 3.3470mA -0.2000 2.7200mA 1.6820mA 3.2630mA -0.1000 2.6470mA 1.6510mA 3.1780mA 0.0000 2.5730mA 1.6150mA 3.0930mA | [Ramp] | variable typ min max dV/dt_r 0.9717/2.1253n 0.7156/2.8088n 1.1145/1.8162n dV/dt_f 0.8280/2.2698n 0.6420/2.5421n 0.9276/2.2143n R_load = 50.0000 | [Rising Waveform] R_fixture = 50.0000 V_fixture = 0.000 V_fixture_min = 0.000 V_fixture_max = 0.000 | time V(typ) V(min) V(max) | 0.000S 0.4624mV 0.3981mV 0.4904mV 0.5000nS 0.4072mV 0.3356mV 0.3906mV 1.0000nS -1.2173mV 0.1929mV 10.7325mV 1.5000nS 68.9603mV -2.9597mV 0.4445V 2.0000nS 0.3909V 1.6130mV 0.9596V 2.5000nS 0.7023V 45.2550mV 1.2260V 3.0000nS 0.9027V 0.1094V 1.3970V 3.5000nS 1.1063V 0.2475V 1.5390V 4.0000nS 1.2630V 0.4012V 1.6360V 4.5000nS 1.3420V 0.5217V 1.6960V 5.0000nS 1.4413V 0.7013V 1.7557V 5.5000nS 1.4960V 0.8206V 1.7880V 6.0000nS 1.5313V 0.9097V 1.8123V 6.5000nS 1.5600V 0.9837V 1.8240V 7.0000nS 1.5740V 1.0225V 1.8320V 7.5000nS 1.5897V 1.0747V 1.8437V 8.0000nS 1.6015V 1.1115V 1.8470V 8.5000nS 1.6050V 1.1280V 1.8520V 9.0000nS 1.6090V 1.1410V 1.8535V 9.5000nS 1.6130V 1.1567V 1.8540V 10.0000nS 1.6150V 1.1660V 1.8560V 10.5000nS 1.6165V 1.1715V 1.8565V 11.0000nS 1.6180V 1.1770V 1.8565V 11.5000nS 1.6183V 1.1817V 1.8570V 12.0000nS 1.6190V 1.1850V 1.8570V 12.5000nS 1.6195V 1.1865V 1.8570V 13.0000nS 1.6200V 1.1880V 1.8580V 13.5000nS 1.6200V 1.1890V 1.8570V 14.0000nS 1.6200V 1.1900V 1.8575V 14.5000nS 1.6200V 1.1907V 1.8580V 15.0000nS 1.6200V 1.1910V 1.8580V 15.5000nS 1.6200V 1.1917V 1.8580V 16.0000nS 1.6200V 1.1920V 1.8580V 16.5000nS 1.6200V 1.1920V 1.8580V 17.0000nS 1.6200V 1.1920V 1.8580V 17.5000nS 1.6200V 1.1920V 1.8580V 18.0000nS 1.6200V 1.1920V 1.8580V 18.5000nS 1.6200V 1.1920V 1.8580V 19.0000nS 1.6200V 1.1920V 1.8580V 19.5000nS 1.6200V 1.1920V 1.8580V 20.0000nS 1.6200V 1.1923V 1.8580V 20.5000nS 1.6200V 1.1930V 1.8580V 21.0000nS 1.6200V 1.1930V 1.8580V 21.5000nS 1.6200V 1.1930V 1.8580V 22.0000nS 1.6200V 1.1930V 1.8580V 22.5000nS 1.6200V 1.1930V 1.8580V 23.0000nS 1.6200V 1.1930V 1.8580V 23.5000nS 1.6200V 1.1930V 1.8580V 24.0000nS 1.6200V 1.1930V 1.8580V 24.5000nS 1.6200V 1.1930V 1.8580V 25.0000nS 1.6200V 1.1930V 1.8580V | [Rising Waveform] R_fixture = 50.0000 V_fixture = 3.3000 V_fixture_min = 2.7000 V_fixture_max = 3.6000 | time V(typ) V(min) V(max) | 0.000S 1.8580V 1.5870V 1.9830V 0.5000nS 1.8580V 1.5870V 1.9830V 1.0000nS 1.8820V 1.5880V 2.0885V 1.5000nS 2.1933V 1.6833V 2.6067V 2.0000nS 2.5330V 1.8790V 2.9450V 2.5000nS 2.7540V 2.0155V 3.1450V 3.0000nS 2.8610V 2.1620V 3.2350V 3.5000nS 2.9760V 2.2697V 3.3260V 4.0000nS 3.0600V 2.3770V 3.4010V 4.5000nS 3.0995V 2.4435V 3.4260V 5.0000nS 3.1513V 2.5083V 3.4673V 5.5000nS 3.1780V 2.5560V 3.4860V 6.0000nS 3.1963V 2.5800V 3.4997V 6.5000nS 3.2090V 2.6050V 3.5100V 7.0000nS 3.2165V 2.6155V 3.5135V 7.5000nS 3.2237V 2.6290V 3.5203V 8.0000nS 3.2290V 2.6385V 3.5230V 8.5000nS 3.2320V 2.6420V 3.5240V 9.0000nS 3.2325V 2.6470V 3.5265V 9.5000nS 3.2347V 2.6497V 3.5270V 10.0000nS 3.2360V 2.6520V 3.5270V 10.5000nS 3.2360V 2.6535V 3.5280V 11.0000nS 3.2370V 2.6540V 3.5280V 11.5000nS 3.2370V 2.6557V 3.5283V 12.0000nS 3.2370V 2.6560V 3.5290V 12.5000nS 3.2375V 2.6560V 3.5290V 13.0000nS 3.2380V 2.6570V 3.5290V 13.5000nS 3.2380V 2.6570V 3.5290V 14.0000nS 3.2380V 2.6570V 3.5290V 14.5000nS 3.2380V 2.6570V 3.5290V 15.0000nS 3.2380V 2.6570V 3.5290V 15.5000nS 3.2380V 2.6570V 3.5290V 16.0000nS 3.2380V 2.6580V 3.5290V 16.5000nS 3.2380V 2.6570V 3.5290V 17.0000nS 3.2380V 2.6570V 3.5290V 17.5000nS 3.2380V 2.6580V 3.5290V 18.0000nS 3.2380V 2.6570V 3.5290V 18.5000nS 3.2380V 2.6577V 3.5290V 19.0000nS 3.2380V 2.6580V 3.5290V 19.5000nS 3.2380V 2.6570V 3.5290V 20.0000nS 3.2380V 2.6577V 3.5290V 20.5000nS 3.2380V 2.6580V 3.5290V 21.0000nS 3.2380V 2.6570V 3.5290V 21.5000nS 3.2380V 2.6580V 3.5290V 22.0000nS 3.2380V 2.6570V 3.5290V 22.5000nS 3.2380V 2.6570V 3.5290V 23.0000nS 3.2380V 2.6580V 3.5290V 23.5000nS 3.2380V 2.6575V 3.5290V 24.0000nS 3.2380V 2.6573V 3.5290V 24.5000nS 3.2380V 2.6580V 3.5290V 25.0000nS 3.2380V 2.6575V 3.5290V | [Falling Waveform] R_fixture = 50.0000 V_fixture = 0.000 V_fixture_min = 0.000 V_fixture_max = 0.000 | time V(typ) V(min) V(max) | 0.000S 1.6200V 1.1920V 1.8580V 0.5000nS 1.6185V 1.1910V 1.8545V 1.0000nS 1.4900V 1.1360V 1.6050V 1.5000nS 1.0797V 0.9249V 1.0721V 2.0000nS 0.7321V 0.7144V 0.7158V 2.5000nS 0.5381V 0.5319V 0.5207V 3.0000nS 0.4294V 0.4307V 0.4177V 3.5000nS 0.3112V 0.3255V 0.2968V 4.0000nS 0.2261V 0.2364V 0.2229V 4.5000nS 0.1828V 0.1879V 0.1727V 5.0000nS 0.1216V 0.1335V 0.1155V 5.5000nS 92.0100mV 92.8200mV 84.4600mV 6.0000nS 65.2300mV 74.1767mV 60.9133mV 6.5000nS 49.5700mV 51.0600mV 45.8500mV 7.0000nS 38.0050mV 42.5750mV 34.1400mV 7.5000nS 26.2467mV 30.2867mV 24.4733mV 8.0000nS 17.0900mV 20.2550mV 15.3500mV 8.5000nS 14.1200mV 17.5600mV 13.2000mV 9.0000nS 11.3200mV 12.7450mV 9.8600mV 9.5000nS 7.5360mV 9.2683mV 6.8077mV 10.0000nS 5.6380mV 6.2890mV 4.8380mV 10.5000nS 4.2080mV 5.3505mV 3.6330mV 11.0000nS 3.3595mV 4.0370mV 2.9660mV 11.5000nS 2.1517mV 2.7970mV 1.8570mV 12.0000nS 1.6870mV 1.9670mV 1.4330mV 12.5000nS 1.2345mV 1.5530mV 1.0281mV 13.0000nS 0.8994mV 1.1314mV 0.7642mV 13.5000nS 0.5948mV 0.8556mV 0.4849mV 14.0000nS 0.4960mV 0.7302mV 0.4528mV 14.5000nS 0.3453mV 0.4577mV 0.2767mV 15.0000nS 0.2475mV 0.3616mV 0.2355mV 15.5000nS 0.1931mV 0.2484mV 0.1477mV 16.0000nS 0.1229mV 0.2217mV 0.1232mV 16.5000nS 0.1167mV 0.1324mV 86.1100uV 17.0000nS 69.3567uV 0.1160mV 62.5800uV 17.5000nS 59.2600uV 58.6600uV 42.8400uV 18.0000nS 44.8200uV 65.5000uV 32.2300uV 18.5000nS 29.6433uV 43.0067uV 24.6633uV 19.0000nS 22.3300uV 32.1800uV 15.6400uV 19.5000nS 14.0950uV 31.7950uV 16.0650uV 20.0000nS 13.3367uV 15.8800uV 8.7417uV 20.5000nS 5.6030uV 17.6300uV 8.7210uV 21.0000nS 7.0420uV 8.2383uV 5.2510uV 21.5000nS 3.5185uV 9.8560uV 4.1790uV 22.0000nS 2.7440uV 4.9050uV 3.8830uV 22.5000nS 3.0777uV 3.7823uV 2.1253uV 23.0000nS 0.9945uV 4.5290uV 2.7840uV 23.5000nS 1.7770uV 1.6669uV 1.5290uV 24.0000nS 0.8292uV 2.3268uV 1.3030uV 24.5000nS 0.9398uV 1.1490uV 1.2140uV 25.0000nS 0.9700uV 0.2963uV 0.6008uV | [Falling Waveform] R_fixture = 50.0000 V_fixture = 3.3000 V_fixture_min = 2.7000 V_fixture_max = 3.6000 | time V(typ) V(min) V(max) | 0.000S 3.2380V 2.6570V 3.5290V 0.5000nS 3.2385V 2.6575V 3.5295V 1.0000nS 3.2405V 2.6590V 3.5025V 1.5000nS 3.0677V 2.6570V 3.0460V 2.0000nS 2.6910V 2.6000V 2.7140V 2.5000nS 2.4875V 2.4585V 2.5085V 3.0000nS 2.3590V 2.3230V 2.3750V 3.5000nS 2.2150V 2.1547V 2.2913V 4.0000nS 2.1260V 2.0150V 2.1970V 4.5000nS 2.0745V 1.9325V 2.1425V 5.0000nS 1.9970V 1.8293V 2.1040V 5.5000nS 1.9660V 1.7670V 2.0610V 6.0000nS 1.9340V 1.7217V 2.0430V 6.5000nS 1.9110V 1.6870V 2.0300V 7.0000nS 1.9055V 1.6680V 2.0140V 7.5000nS 1.8867V 1.6427V 2.0077V 8.0000nS 1.8795V 1.6260V 1.9965V 8.5000nS 1.8760V 1.6180V 1.9930V 9.0000nS 1.8695V 1.6115V 1.9935V 9.5000nS 1.8670V 1.6043V 1.9890V 10.0000nS 1.8650V 1.6000V 1.9860V 10.5000nS 1.8615V 1.5970V 1.9885V 11.0000nS 1.8620V 1.5945V 1.9855V 11.5000nS 1.8610V 1.5920V 1.9847V 12.0000nS 1.8590V 1.5910V 1.9850V 12.5000nS 1.8600V 1.5900V 1.9835V 13.0000nS 1.8590V 1.5890V 1.9837V 13.5000nS 1.8590V 1.5880V 1.9840V 14.0000nS 1.8595V 1.5880V 1.9825V 14.5000nS 1.8583V 1.5877V 1.9837V 15.0000nS 1.8580V 1.5870V 1.9830V 15.5000nS 1.8587V 1.5870V 1.9827V 16.0000nS 1.8580V 1.5870V 1.9830V 16.5000nS 1.8580V 1.5870V 1.9830V 17.0000nS 1.8583V 1.5870V 1.9827V 17.5000nS 1.8580V 1.5870V 1.9830V 18.0000nS 1.8580V 1.5870V 1.9830V 18.5000nS 1.8580V 1.5870V 1.9830V 19.0000nS 1.8580V 1.5870V 1.9830V 19.5000nS 1.8580V 1.5870V 1.9830V 20.0000nS 1.8580V 1.5870V 1.9830V 20.5000nS 1.8580V 1.5870V 1.9830V 21.0000nS 1.8580V 1.5870V 1.9830V 21.5000nS 1.8580V 1.5870V 1.9830V 22.0000nS 1.8580V 1.5870V 1.9830V 22.5000nS 1.8580V 1.5870V 1.9830V 23.0000nS 1.8580V 1.5870V 1.9830V 23.5000nS 1.8580V 1.5870V 1.9830V 24.0000nS 1.8580V 1.5870V 1.9830V 24.5000nS 1.8580V 1.5870V 1.9830V 25.0000nS 1.8580V 1.5870V 1.9830V | | End [Model] IO - ------=_NextPart_000_23c7_651_110d-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 6 Apr 2006 18:40:19 +0530 From: Subject: [IBIS-Users] How to include Differential and Normal IO's of same pins This is a multi-part message in MIME format. - ------_=_NextPart_001_01C6597B.75D3E0DB Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Experts, =0D I have a doubt regarding IBIS model of incorporating Differential and Non-differential Buffers in the same IBIS file =0D As an Example there are 2 pins and corresponding LVDS definition is as follows [Pin] signal_name model_name R_pin L_pin C_pin | Pin1 CLKP LVDS_1 Pin2 CLKN LVDS_2 | [Diff_pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max | Pin1 Pin2 200mV NA NA NA =0D For the same 2 above pins there exist normal(Non differential) IO's too, my doubt is that will it be possible to include both Differential and Normal IO's with any IBIS mechanism like how a {Model Selector] chooses different models for the same pin? If so please let me know on how? =0D Suppose same if I do using [Model Selector] then what will be the impact of [Diff_pin] section on this pins when I am using only Normal models, this prototype is as listed below [Pin] signal_name model_name R_pin L_pin C_pin | Pin1 CLKP MODEL_1 Pin2 CLKN MODEL_2 | [Diff_pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max | Pin1 Pin2 200mV NA NA NA | [Model Selector] MODEL_1 LVDS_1 lvds model=0D BUFFER_1 normal output buffer | [Model Selector] MODEL_2 LVDS_2 lvds model=0D BUFFER_2 normal output buffer | What my opinion is option 2 is not proper as there is still valid(uncommented) [Diff_pin] section exist for the same pins while using normal IO's mode, please correct me if my concept is wrong =0D Any Help on this is appreciable=0D =0D Thanks & Best Regards Kiran Kumar =0D =0D =0D =0D =0D =0D =0D =0D =0D The information contained in this electronic message and any attachments to= this message are intended for the exclusive use of the addressee(s) and= may contain proprietary, confidential or privileged information. If you= are not the intended recipient, you should not disseminate, distribute or= copy this e-mail. Please notify the sender immediately and destroy all= copies of this message and any attachments.=0D WARNING: Computer viruses can be transmitted via email. The recipient= should check this email and any attachments for the presence of viruses.= The company accepts no liability for any damage caused by any virus= transmitted by this email. =0D www.wipro.com - ------_=_NextPart_001_01C6597B.75D3E0DB Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi Experts,

 

          I have a doubt regarding IBIS model of incorporating Differential and= Non-differential Buffers in the same IBIS file

 

As an Example there are 2 pins and corresponding LVDS definition is as follows

[Pin]&n= bsp;    signal_name      model_name           = ;   R_pin        L_pin        = C_pin

|<= /o:p>

Pin1&nb= sp;        CLKP     =        LVDS_1<= /b>

Pin2&nb= sp;        CLKN    =         LVDS_2

|<= /o:p>

[Diff_p= in]       inv_pin        = vdiff       tdelay_typ     tdelay_min     tdelay_max

|<= /o:p>

Pin1&nb= sp;            Pin2            200mV      NA            &= nbsp; NA            &= nbsp;  NA

&n= bsp;

For  the same 2 above pins there exist normal(Non differential) IO’s too,  my doubt is that will it be possible to include both Differential and Normal IO’s with any IBIS mechanism= like how a {Model Selector] chooses different models for the same pin? If so= please let me know on how?

   

    Suppose same if I do using [Model Selector] then what will be the impact of [Diff_pin] section on this pins= when I am using only Normal models, this= prototype is as listed below

[Pin]&n= bsp;    signal_name      model_name           = ;   R_pin        L_pin        = C_pin

|<= /o:p>

Pin1&nb= sp;        CLKP     =        MODEL_1=

Pin2&nb= sp;        CLKN    =         MODEL_2<= /font>

|<= /o:p>

[Diff_p= in]       inv_pin        = vdiff       tdelay_typ     tdelay_min     tdelay_max

|<= /o:p>

Pin1&nb= sp;            Pin2            200mV      NA            &= nbsp; NA            &= nbsp;  NA

|<= /o:p>

[Model Selector]     MODEL_1

LVDS_1&= nbsp;           &nbs= p;        lvds model

BUFFER_= 1            &n= bsp;    normal output buffer

|<= /o:p>

[Model Selector]     MODEL_2

LVDS_2&= nbsp;           &nbs= p;        lvds model

BUFFER_= 2            &n= bsp;    normal output buffer

|<= /o:p>

What my opinion is option 2 is not proper as there is= still valid(uncommented) [Diff_pin]  section exist for the same pins while= using normal IO’s mode, please correct me if my concept is= wrong

 

Any Help on this is appreciable=

 

Thanks & Best Regards

Kiran Kumar

 

 

 

 

 

 

 

 

 


The information contained in this electronic message and any attachments to= this message are intended for the exclusive use of the addressee(s) and= may contain proprietary, confidential or privileged information. If you= are not the intended recipient, you should not disseminate, distribute or= copy this e-mail. Please notify the sender immediately and destroy all= copies of this message and any attachments.

WARNING: Computer viruses can be transmitted via email. The recipient= should check this email and any attachments for the presence of viruses.= The company accepts no liability for any damage caused by any virus= transmitted by this email.

www.wipro.com
- ------_=_NextPart_001_01C6597B.75D3E0DB-- |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 6 Apr 2006 09:35:06 -0600 From: rrwolff@micron.com Subject: [IBIS-Users] [IBIS] Open forum minutes (03/31/06) This is a multi-part message in MIME format. - ------_=_NextPart_001_01C6598F.ADF6E9AE Content-Type: multipart/alternative; boundary="----_=_NextPart_002_01C6598F.ADF6E9AE" - ------_=_NextPart_002_01C6598F.ADF6E9AE Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Attached are the minutes of the Friday, March 31, 2006 IBIS Open Forum teleconference. This will be the last set of minutes sent to the "ibis-users" mailing list. Please make sure you are subscribed to the "ibis" list if you want to continue receiving the meeting minutes. Randy Wolff IBIS Open Forum Secretary <>=20 - ------_=_NextPart_002_01C6598F.ADF6E9AE Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [IBIS] Open forum minutes (03/31/06)

Attached are the minutes of the = Friday, March 31, 2006 IBIS Open Forum teleconference.

This will be the last set of = minutes sent to the "ibis-users" mailing list.  Please = make sure you are subscribed to the "ibis" list if you want to = continue receiving the meeting minutes.

Randy Wolff
IBIS Open Forum Secretary
= <<m033106.txt>>

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