From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #85 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Monday, September 11 2006 Volume 01 : Number 085 ---------------------------------------------------------------------- Date: Thu, 3 Aug 2006 11:04:02 -0700 From: "Beal, Weston" Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Radovan, First, you should not expect the curves to line up in time. The IBIS data does not represent all of the output buffer. Generally, the voltage at the pin of an IBIS model will transition sooner than the voltage at the pin of a full transistor-level model. The curves should be the same if you can slide one in time to compensate for this time offset. Try delaying the stimulus to the IBIS model by 30ps. In your pictures I see that the curve shapes are still a little bit off. It's difficult to know what causes this without seeing your simulation files. Look at the IBIS rising and falling waveform tables to see if the time extents are close to the actual transition. You want as many time-points as possible describing the actual transition and not waste them in flat regions. Different simulators deal with the flat regions at the beginning and end of the transition in different ways. I hope this helps a bit. Good Luck! Regards, Weston - -----Original Message----- From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Thursday, August 03, 2006 8:38 AM To: ibis-users@server.eda-stds.org Subject: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi experts, sorry that I trigger the same topic once again, but now it keeps me busy already more than one week and I am pretty sure that the problem is not a way how I extract IBIS model, but somewhere else! Before I elaborate the problem let me notice that I get the same result if I use 2ibis2 or s2ibis3 or if I use HSpice or some company internal analog simulator for extraction of IBIS model. Let me elaborate the problem: 1. IBIS model is generated (say with s2ibis2, but irrelevant, since there is a same result with s2ibis3) 2. I take one of spice decks for extracting rising waveform generated by extraction tool (say a00DQ40.spi) - this should be spice deck for generating 1st rising waveform in typical case. This spice deck of course contains the netlist of my circuit. 3. I modify this spice deck only that I instantiate in it just generated IBIS buffer model (in step 1.) as a B-element - in other words, I just put there IBIS model - B-element and do nothing else 4. stimuli and load for netlist remains the same and I use exactly the same stimuli and load for IBIS model as well (of course, netlist, IBIS model and their stimulus and loads are separated) 5. simulate such modified spice deck with HSpice and compare the outputs: netlist vs. IBIS model Problem: What I expect to get on output is very good overlap between Hspice simulation of netlist and IBIS model, BUT what I get on output is a fact that falling or rising edges don't overlap i.e. there is some 30ps delay (Please take a look on attached snapshots "zoom1.gif" and "zoom2.gif"). Signal "dq_40_ohm" is output of netlist, signal "io_ron_040_hspice_typ". You can see a real delay and not some different slopes due to different loads. Transient analysis is done with (.TRAN 1.36e-11 1.36e-09) - i.e. simulation step (for IBIS extraction) is 13.6ps. What worries me even more is a fact that in some cases (for different stimuli frequencies) I see that rising edges are overlapping and falling are delayed and in some cases (some other frequency of stimuli) I see that falling edges are overlapping and rising are delayed, so I don't know even where should I cut ("taylor") my V-t curves when behavior seems to be so arbitrary and frequency dependant. I know, some of you would say that 20-30ps are no problem, but exactly this 20-30ps are shifting (upwards or downwards) crossing point of rising and falling edges and destroy duty cycle and data eye diagram (target is 800MHz). Problem is independent on slope of stimuli (so with 1ps slope or 100ps of slope of stimuli I see the same result) I know that we should not speak on this forum about tools and vendors and I terribly apologize that I will still mention some of them - but on the end all our models are used with some these tools and I think that it is necessary that we exchange information about our experiences with this tools as well. So the problem is analysed with different tools: - - I see above mentioned problem when simulating with HSpice (versions 2004.09, 2005.03 and 2006.03) netlist vs. IBIS model - - I see effect of above mentioned problem when simulating with ADS - using only IBIS model - rising and falling edge crossing points are shifted same as in HSpice - - with SpecctraQuest (also simulating only with IBIS model) I see the right results! So I am pretty confused, what is correct? A few different simulators, but only one is showing a right result (or at least result that I consider as a proper). What is your experience? Have you noticed something similar? Can somebody from you do the same procedure on one of your designs (compare IBIS vs. HSpice on the same way as I done)? Has somebody an idea, proposal? Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletiæ Qimonda AG QAG PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@qimonda.com <> <> - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 4 Aug 2006 11:25:40 +0900 From: "Xuefeng Chen" Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Radovan, Weston's suggestions are very good. In addition, I have two points to mention when using HSPICE 1) ".TRAN 1.36e-11 1.36e-09" does not mean exactly the time step is 13.6ps. Dynamic time step control will be used in transient analysis. You can try option DELMAX to set the maximum time step. 2) Input stimulus is dealt with by two voltage thresholds 0.2v and 0.8v which decides the starting time point of buffer's transition. So it's better to set (vhigh+vlow)/2 = 0.5 if you use PULSE voltage source as stimulus. Of course, I think the most important thing is the waveform tables as Weston mentioned. Best regards Xuefeng - -----Original Message----- From: owner-ibis-users@eda-stds.org [mailto:owner-ibis-users@eda-stds.org] On Behalf Of Beal, Weston Sent: 2006å¹´8月4æ—¥ 2:04 To: Radovan.Vuletic@qimonda.com; ibis-users@eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Radovan, First, you should not expect the curves to line up in time. The IBIS data does not represent all of the output buffer. Generally, the voltage at the pin of an IBIS model will transition sooner than the voltage at the pin of a full transistor-level model. The curves should be the same if you can slide one in time to compensate for this time offset. Try delaying the stimulus to the IBIS model by 30ps. In your pictures I see that the curve shapes are still a little bit off. It's difficult to know what causes this without seeing your simulation files. Look at the IBIS rising and falling waveform tables to see if the time extents are close to the actual transition. You want as many time-points as possible describing the actual transition and not waste them in flat regions. Different simulators deal with the flat regions at the beginning and end of the transition in different ways. I hope this helps a bit. Good Luck! Regards, Weston - -----Original Message----- From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Thursday, August 03, 2006 8:38 AM To: ibis-users@server.eda-stds.org Subject: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi experts, sorry that I trigger the same topic once again, but now it keeps me busy already more than one week and I am pretty sure that the problem is not a way how I extract IBIS model, but somewhere else! Before I elaborate the problem let me notice that I get the same result if I use 2ibis2 or s2ibis3 or if I use HSpice or some company internal analog simulator for extraction of IBIS model. Let me elaborate the problem: 1. IBIS model is generated (say with s2ibis2, but irrelevant, since there is a same result with s2ibis3) 2. I take one of spice decks for extracting rising waveform generated by extraction tool (say a00DQ40.spi) - this should be spice deck for generating 1st rising waveform in typical case. This spice deck of course contains the netlist of my circuit. 3. I modify this spice deck only that I instantiate in it just generated IBIS buffer model (in step 1.) as a B-element - in other words, I just put there IBIS model - B-element and do nothing else 4. stimuli and load for netlist remains the same and I use exactly the same stimuli and load for IBIS model as well (of course, netlist, IBIS model and their stimulus and loads are separated) 5. simulate such modified spice deck with HSpice and compare the outputs: netlist vs. IBIS model Problem: What I expect to get on output is very good overlap between Hspice simulation of netlist and IBIS model, BUT what I get on output is a fact that falling or rising edges don't overlap i.e. there is some 30ps delay (Please take a look on attached snapshots "zoom1.gif" and "zoom2.gif"). Signal "dq_40_ohm" is output of netlist, signal "io_ron_040_hspice_typ". You can see a real delay and not some different slopes due to different loads. Transient analysis is done with (.TRAN 1.36e-11 1.36e-09) - i.e. simulation step (for IBIS extraction) is 13.6ps. What worries me even more is a fact that in some cases (for different stimuli frequencies) I see that rising edges are overlapping and falling are delayed and in some cases (some other frequency of stimuli) I see that falling edges are overlapping and rising are delayed, so I don't know even where should I cut ("taylor") my V-t curves when behavior seems to be so arbitrary and frequency dependant. I know, some of you would say that 20-30ps are no problem, but exactly this 20-30ps are shifting (upwards or downwards) crossing point of rising and falling edges and destroy duty cycle and data eye diagram (target is 800MHz). Problem is independent on slope of stimuli (so with 1ps slope or 100ps of slope of stimuli I see the same result) I know that we should not speak on this forum about tools and vendors and I terribly apologize that I will still mention some of them - but on the end all our models are used with some these tools and I think that it is necessary that we exchange information about our experiences with this tools as well. So the problem is analysed with different tools: - - I see above mentioned problem when simulating with HSpice (versions 2004.09, 2005.03 and 2006.03) netlist vs. IBIS model - - I see effect of above mentioned problem when simulating with ADS - using only IBIS model - rising and falling edge crossing points are shifted same as in HSpice - - with SpecctraQuest (also simulating only with IBIS model) I see the right results! So I am pretty confused, what is correct? A few different simulators, but only one is showing a right result (or at least result that I consider as a proper). What is your experience? Have you noticed something similar? Can somebody from you do the same procedure on one of your designs (compare IBIS vs. HSpice on the same way as I done)? Has somebody an idea, proposal? Best regards / Mit freundlichen Grüßen / S poÅ¡tovanjem Radovan Vuletić Qimonda AG QAG PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@qimonda.com <> <> - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 07 Aug 2006 14:03:24 +0530 From: Vinayak Subject: [IBIS-Users] IBIS non-monotonicity issue This is a multi-part message in MIME format. - --------------060704030600050501020902 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Hi, I was trying run ibischk4 on the ibis model it gives a warning as WARNING (line 165) - POWER Clamp Voltage data is non-monotonic though i could not find any non-monotonicity in the values in the ibis model. -0.2181818 0.1062643m 46.73129u 0.2034879m -0.2 0.106231m 46.71362u 0.2034473m -0.1818182 0.1061977m 46.69595u 0.2034067m 1.963636 0.106169m 46.68056u 0.2033726m 1.945455 0.1061409m 46.66543u 0.2033392m ----> line 165 1.927273 0.1061128m 46.6503u 0.2033058m 1.909091 0.106087m 46.63619u 0.2032756m 1.890909 0.1060628m 46.62276u 0.2032475m 1.872727 0.1060386m 46.60933u 0.2032194m 1.854545 0.1060153m 46.59625u 0.2031925m 1.836364 0.1059939m 46.58398u 0.2031681m 1.818182 0.1059725m 46.57171u 0.2031437m 1.8 0.1059511m 46.55944u 0.2031194m Should i ignore this warning. Regards vinayak - --------------060704030600050501020902 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Hi,

I was trying run ibischk4 on the ibis model
it gives a warning as

WARNING (line  165) - POWER Clamp Voltage data is non-monotonic

though i could not find any non-monotonicity in the values
in the ibis model.

   -0.2181818   0.1062643m    46.73129u   0.2034879m
         -0.2    0.106231m    46.71362u   0.2034473m
   -0.1818182   0.1061977m    46.69595u   0.2034067m
     1.963636    0.106169m    46.68056u   0.2033726m
     1.945455   0.1061409m    46.66543u   0.2033392m  ----> line 165
     1.927273   0.1061128m     46.6503u   0.2033058m
     1.909091    0.106087m    46.63619u   0.2032756m
     1.890909   0.1060628m    46.62276u   0.2032475m
     1.872727   0.1060386m    46.60933u   0.2032194m
     1.854545   0.1060153m    46.59625u   0.2031925m
     1.836364   0.1059939m    46.58398u   0.2031681m
     1.818182   0.1059725m    46.57171u   0.2031437m
          1.8   0.1059511m    46.55944u   0.2031194m

Should i ignore this warning.

Regards
vinayak

 - --------------060704030600050501020902-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 7 Aug 2006 15:26:38 +0530 From: Subject: RE: [IBIS-Users] IBIS non-monotonicity issue This is a multi-part message in MIME format. - ------_=_NextPart_001_01C6BA07.C68B679F Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Vinayak, =0D I have noticed below points from the data you pasted herewith=0D =0D 1) what is the significance of generating POWER clamp table for 1.8 to 1.96 ? because this might captured in GND clamp range. 2) if the data started from -1.8 (assuming buffer operating at 1.8V) data is captured till 1.9818V (1.8 + 0.1818182) i.e actual POWER clamp data is present for 1.9818V to 3.6V=0D coming to data present between 1.8V to 1.963636V is actual Vpad of 0V to 0.1636V . =0D usually the voltage value for IV data is as follows Pu/Pd tables --------> -1.8 to 3.6V=0D GND clamp tables ---------> -1.8 to 1.8V POWER clamp tables --------> 1.8V to 3.6V =0D Coming to warning I think data is -1.8 to -0.1818182 follows one order(+vely increasing) after that=0D 1.963636 to 1.8V follows other order (+vely decreasing) =0D Hope this helps you =0D Best Regards Kiran Kumar =0D =0D ________________________________ From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Vinayak Sent: Monday, August 07, 2006 2:03 PM To: ibis@server.eda-stds.org Cc: ibis-users@server.eda-stds.org Subject: [IBIS-Users] IBIS non-monotonicity issue =0D Hi, I was trying run ibischk4 on the ibis model=0D it gives a warning as=0D WARNING (line 165) - POWER Clamp Voltage data is non-monotonic though i could not find any non-monotonicity in the values=0D in the ibis model.=0D -0.2181818 0.1062643m 46.73129u 0.2034879m -0.2 0.106231m 46.71362u 0.2034473m -0.1818182 0.1061977m 46.69595u 0.2034067m 1.963636 0.106169m 46.68056u 0.2033726m 1.945455 0.1061409m 46.66543u 0.2033392m ----> line 165 1.927273 0.1061128m 46.6503u 0.2033058m 1.909091 0.106087m 46.63619u 0.2032756m 1.890909 0.1060628m 46.62276u 0.2032475m 1.872727 0.1060386m 46.60933u 0.2032194m 1.854545 0.1060153m 46.59625u 0.2031925m 1.836364 0.1059939m 46.58398u 0.2031681m 1.818182 0.1059725m 46.57171u 0.2031437m 1.8 0.1059511m 46.55944u 0.2031194m Should i ignore this warning.=0D Regards vinayak The information contained in this electronic message and any attachments to= this message are intended for the exclusive use of the addressee(s) and= may contain proprietary, confidential or privileged information. If you= are not the intended recipient, you should not disseminate, distribute or= copy this e-mail. Please notify the sender immediately and destroy all= copies of this message and any attachments.=0D WARNING: Computer viruses can be transmitted via email. The recipient= should check this email and any attachments for the presence of viruses.= The company accepts no liability for any damage caused by any virus= transmitted by this email. =0D www.wipro.com - ------_=_NextPart_001_01C6BA07.C68B679F Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi= Vinayak,

 

      &n= bsp; I have noticed below points from the data you pasted herewith=

 

1)      = what is the significance of generating POWER clamp table for= 1.8 to 1.96 ? because this might captured in GND clamp= range.

2)      = if the data started from -1.8 (assuming buffer operating at= 1.8V)  data is captured till 1.9818V (1.8 + 0.1818182) i.e actual POWER clamp data is present for 1.9818V to 3.6V=

      &n= bsp; coming to data present between 1.8V to 1.963636V is actual Vpad of  0V= to 0.1636V .

 

usually  the voltage  value= for IV data is as follows

Pu/Pd tables ------à  -1.8 to 3.6V=

GND clamp tables= -------à -1.8 to= 1.8V

POWER clamp tables  = ------à 1.8V  to= 3.6V

 

Coming to warning I think  data= is - -1.8 to -0.1818182 follows= one order(+vely increasing) after that

1.963636 to 1.8V= follows other= order= (+vely= decreasing)

 

Hope= this helps you

 

Best= Regards

Kiran= Kumar

 

 

= From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Vinayak
Sent: Monday, August 07,= 2006 2:03 PM
To:= ibis@server.eda-stds.org
Cc:= ibis-users@server.eda-stds.org
Subject: [IBIS-Users] IBIS non-monotonicity issue

 

Hi,

I was trying run ibischk4 on the ibis model
it gives a warning as

WARNING (line  165) - POWER Clamp Voltage data is non-monotonic

though i could not find any non-monotonicity in the values
in the ibis model.

   -0.2181818   0.1062643m   = 46.73129u   0.2034879m
         -0.2    0.106231m    46.71362u   0.2034473m
   -0.1818182   0.1061977m    46.69595u   0.2034067m
     1.963636   = 0.106169m    46.68056u   0.2033726m
     1.945455   0.1061409m    46.66543u   0.2033392m  ----> line 165
     1.927273   0.1061128m     46.6503u   0.2033058m
     1.909091   = 0.106087m    46.63619u   0.2032756m
     1.890909   0.1060628m    46.62276u   0.2032475m
     1.872727   0.1060386m    46.60933u   0.2032194m
     1.854545   0.1060153m    46.59625u   0.2031925m
     1.836364   0.1059939m    46.58398u   0.2031681m
     1.818182   0.1059725m    46.57171u   0.2031437m
          1.8   0.1059511m    46.55944u   0.2031194m

Should i ignore this warning.

Regards
vinayak


The information contained in this electronic message and any attachments to= this message are intended for the exclusive use of the addressee(s) and= may contain proprietary, confidential or privileged information. If you= are not the intended recipient, you should not disseminate, distribute or= copy this e-mail. Please notify the sender immediately and destroy all= copies of this message and any attachments.

WARNING: Computer viruses can be transmitted via email. The recipient= should check this email and any attachments for the presence of viruses.= The company accepts no liability for any damage caused by any virus= transmitted by this email.

www.wipro.com
- ------_=_NextPart_001_01C6BA07.C68B679F-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 7 Aug 2006 15:29:34 +0200 From: Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi experts, many thanks Weston and Xuefeng for your answers. I have to apologies that it wasn't immediately clear in my first mail, but I would never send mail to this forum if just delaying of stimuli for 30ps would solve my problems. Problem was, as I wrote in my mail, that in some cases rising edge was showing very good overlap between transistor netlist and IBIS, but falling edges were shifted - in other cases (with some other stimuli frequencies) falling edges were overlapping but rising edges were delayed - this problem unfortunately can't be solved by simple shifting stimuli. Hint that Xuefeng gave was really good (but who really reads such boring stuff as Additional Notes in HSpice SI Guide?). So just to recapitulate for the other people who can see/have the same problem - please find bellow the excerpt out of HSpice SI Guide: "Voltage Thresholds Voltages applied to the input and enable nodes are digital signals. They should be either 0 or 1. You can specify input voltage as: V_in nd_in 0 pulse (0 3.3 0 0.5n 0.5n 4n 8n) However, IC circuit simulation currently detects only two thresholds, 20% and 80% of [0,1] swing, that is, 0.2V and 0.8V. If a buffer is non-inverting and in a LOW state, it starts the transition to a HIGH state, if V_in > 0.8V. If the buffer is in HIGH state, it will start the transition to LOW state, if V_in < 0.2V. Specifying input voltage in the range [0, 3.3V] as in the above example does not make LOW -> HIGH transitions better in any way, but can add uncertainty over the 0.5ns time interval, when the transition actually occurs." - --- end of excerpt Originaly I used PULSE with 100ps rising/falling time with sweep from 0 to 1.5V. (and 0.2V and 0.8V are pretty asymmetrical to this range) When I used PULSE stimuli with 0ps rising and falling waveform and around 10 times finer resolution for simulation (.TRAN 1.36e-11 used for IBIS model extraction and .TRAN 1ps for simulation (although Xuefeng will say that it is perhaps not properly to say, since there is dynamic step control) I saw significantly better data-eye diagram and very good overlap between rising and falling edges - Nice! However, that rises a question if 0ps rising/falling waveforms are physically justified. Q U E S T I O N : ================= Above mentioned problem is kind of missing definition in IBIS models (O.K. not in definition of IBIS, but definitely for usage of IBIS models). Shouldn't be standardized how every tool should approach simulation of IBIS models with respect to input and enable nodes? I mean 0.2V for low and 0.8V for high is very strange - I could accept 20% of Vdd and 80% of Vdd, but to define input thresholds as absolute values, totally independent on technology and supply voltage is somehow user unfriendly (however, in HSpice it is at least mentioned in some additional note). Furthermore, it seems that every tool vendor has freedom to treat/process stimuli to input and enable node as she/he will. That leads to the fact that I can have several different output waveforms although I am using same model and stimuli - but different tool!?! I am pretty sure that this topic was already discussed among the people that are using IBIS, but what was the outcome? Is there somebody who is still driving this topics? Is there intention to standardize behavior of inputs to IBIS models? Regards, Radovan - -----Original Message----- From: Xuefeng Chen [mailto:Xuefeng.Chen@synopsys.com] Sent: Friday, August 04, 2006 4:26 AM To: Beal, Weston; Vuletic Radovan (QAG PD PDE MEM); ibis-users@eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Radovan, Weston's suggestions are very good. In addition, I have two points to mention when using HSPICE 1) ".TRAN 1.36e-11 1.36e-09" does not mean exactly the time step is 13.6ps. Dynamic time step control will be used in transient analysis. You can try option DELMAX to set the maximum time step. 2) Input stimulus is dealt with by two voltage thresholds 0.2v and 0.8v which decides the starting time point of buffer's transition. So it's better to set (vhigh+vlow)/2 = 0.5 if you use PULSE voltage source as stimulus. Of course, I think the most important thing is the waveform tables as Weston mentioned. Best regards Xuefeng - -----Original Message----- From: owner-ibis-users@eda-stds.org [mailto:owner-ibis-users@eda-stds.org] On Behalf Of Beal, Weston Sent: 2006å¹´8月4æ—¥ 2:04 To: Radovan.Vuletic@qimonda.com; ibis-users@eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Radovan, First, you should not expect the curves to line up in time. The IBIS data does not represent all of the output buffer. Generally, the voltage at the pin of an IBIS model will transition sooner than the voltage at the pin of a full transistor-level model. The curves should be the same if you can slide one in time to compensate for this time offset. Try delaying the stimulus to the IBIS model by 30ps. In your pictures I see that the curve shapes are still a little bit off. It's difficult to know what causes this without seeing your simulation files. Look at the IBIS rising and falling waveform tables to see if the time extents are close to the actual transition. You want as many time-points as possible describing the actual transition and not waste them in flat regions. Different simulators deal with the flat regions at the beginning and end of the transition in different ways. I hope this helps a bit. Good Luck! Regards, Weston - -----Original Message----- From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Thursday, August 03, 2006 8:38 AM To: ibis-users@server.eda-stds.org Subject: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi experts, sorry that I trigger the same topic once again, but now it keeps me busy already more than one week and I am pretty sure that the problem is not a way how I extract IBIS model, but somewhere else! Before I elaborate the problem let me notice that I get the same result if I use 2ibis2 or s2ibis3 or if I use HSpice or some company internal analog simulator for extraction of IBIS model. Let me elaborate the problem: 1. IBIS model is generated (say with s2ibis2, but irrelevant, since there is a same result with s2ibis3) 2. I take one of spice decks for extracting rising waveform generated by extraction tool (say a00DQ40.spi) - this should be spice deck for generating 1st rising waveform in typical case. This spice deck of course contains the netlist of my circuit. 3. I modify this spice deck only that I instantiate in it just generated IBIS buffer model (in step 1.) as a B-element - in other words, I just put there IBIS model - B-element and do nothing else 4. stimuli and load for netlist remains the same and I use exactly the same stimuli and load for IBIS model as well (of course, netlist, IBIS model and their stimulus and loads are separated) 5. simulate such modified spice deck with HSpice and compare the outputs: netlist vs. IBIS model Problem: What I expect to get on output is very good overlap between Hspice simulation of netlist and IBIS model, BUT what I get on output is a fact that falling or rising edges don't overlap i.e. there is some 30ps delay (Please take a look on attached snapshots "zoom1.gif" and "zoom2.gif"). Signal "dq_40_ohm" is output of netlist, signal "io_ron_040_hspice_typ". You can see a real delay and not some different slopes due to different loads. Transient analysis is done with (.TRAN 1.36e-11 1.36e-09) - i.e. simulation step (for IBIS extraction) is 13.6ps. What worries me even more is a fact that in some cases (for different stimuli frequencies) I see that rising edges are overlapping and falling are delayed and in some cases (some other frequency of stimuli) I see that falling edges are overlapping and rising are delayed, so I don't know even where should I cut ("taylor") my V-t curves when behavior seems to be so arbitrary and frequency dependant. I know, some of you would say that 20-30ps are no problem, but exactly this 20-30ps are shifting (upwards or downwards) crossing point of rising and falling edges and destroy duty cycle and data eye diagram (target is 800MHz). Problem is independent on slope of stimuli (so with 1ps slope or 100ps of slope of stimuli I see the same result) I know that we should not speak on this forum about tools and vendors and I terribly apologize that I will still mention some of them - but on the end all our models are used with some these tools and I think that it is necessary that we exchange information about our experiences with this tools as well. So the problem is analysed with different tools: - - I see above mentioned problem when simulating with HSpice (versions 2004.09, 2005.03 and 2006.03) netlist vs. IBIS model - - I see effect of above mentioned problem when simulating with ADS - using only IBIS model - rising and falling edge crossing points are shifted same as in HSpice - - with SpecctraQuest (also simulating only with IBIS model) I see the right results! So I am pretty confused, what is correct? A few different simulators, but only one is showing a right result (or at least result that I consider as a proper). What is your experience? Have you noticed something similar? Can somebody from you do the same procedure on one of your designs (compare IBIS vs. HSpice on the same way as I done)? Has somebody an idea, proposal? Best regards / Mit freundlichen Grüßen / S poÅ¡tovanjem Radovan Vuletić Qimonda AG QAG PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@qimonda.com <> <> - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 7 Aug 2006 11:10:07 -0500 From: "Sam Chitwood" Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi Radovan, A 0ps rise time is ok for IBIS because the stimulus signal is simply a trigger for the algorithms to start the transitions; there is nothing physical associated with the stimulus node. However, this is typically not true for transistor-level models so different stimuli are required. A number of EDA tools (but probably not all) use the 0.2 V and 0.8 V trigger points (mainly so that HSPICE decks can be directly used in other tools). This was established a long time ago. The IBIS forum does not commonly discuss 'how' EDA companies should implement capabilities - read the IBIS spec. on Series MOSFET for an example. :-) A percentage of the voltage rail could have been used for the trigger points, but that might require unique stimuli for each rail (and each typ/min/max). The fixed 0.2 and 0.8 scheme allows users to create a database of trigger sub-circuits that can be used with any supply voltage. Now that you know how it works, I think you'll find it useful. I hope I've answered some of your questions. Thanks, Sam - -----Original Message----- From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Monday, August 07, 2006 8:30 AM To: Xuefeng.Chen@synopsys.com; weston.beal@intel.com; ibis-users@server.eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi experts, many thanks Weston and Xuefeng for your answers. I have to apologies that it wasn't immediately clear in my first mail, but I would never send mail to this forum if just delaying of stimuli for 30ps would solve my problems. Problem was, as I wrote in my mail, that in some cases rising edge was showing very good overlap between transistor netlist and IBIS, but falling edges were shifted - in other cases (with some other stimuli frequencies) falling edges were overlapping but rising edges were delayed - this problem unfortunately can't be solved by simple shifting stimuli. Hint that Xuefeng gave was really good (but who really reads such boring stuff as Additional Notes in HSpice SI Guide?). So just to recapitulate for the other people who can see/have the same problem - please find bellow the excerpt out of HSpice SI Guide: "Voltage Thresholds Voltages applied to the input and enable nodes are digital signals. They should be either 0 or 1. You can specify input voltage as: V_in nd_in 0 pulse (0 3.3 0 0.5n 0.5n 4n 8n) However, IC circuit simulation currently detects only two thresholds, 20% and 80% of [0,1] swing, that is, 0.2V and 0.8V. If a buffer is non-inverting and in a LOW state, it starts the transition to a HIGH state, if V_in > 0.8V. If the buffer is in HIGH state, it will start the transition to LOW state, if V_in < 0.2V. Specifying input voltage in the range [0, 3.3V] as in the above example does not make LOW -> HIGH transitions better in any way, but can add uncertainty over the 0.5ns time interval, when the transition actually occurs." - --- end of excerpt Originaly I used PULSE with 100ps rising/falling time with sweep from 0 to 1.5V. (and 0.2V and 0.8V are pretty asymmetrical to this range) When I used PULSE stimuli with 0ps rising and falling waveform and around 10 times finer resolution for simulation (.TRAN 1.36e-11 used for IBIS model extraction and .TRAN 1ps for simulation (although Xuefeng will say that it is perhaps not properly to say, since there is dynamic step control) I saw significantly better data-eye diagram and very good overlap between rising and falling edges - Nice! However, that rises a question if 0ps rising/falling waveforms are physically justified. Q U E S T I O N : ================= Above mentioned problem is kind of missing definition in IBIS models (O.K. not in definition of IBIS, but definitely for usage of IBIS models). Shouldn't be standardized how every tool should approach simulation of IBIS models with respect to input and enable nodes? I mean 0.2V for low and 0.8V for high is very strange - I could accept 20% of Vdd and 80% of Vdd, but to define input thresholds as absolute values, totally independent on technology and supply voltage is somehow user unfriendly (however, in HSpice it is at least mentioned in some additional note). Furthermore, it seems that every tool vendor has freedom to treat/process stimuli to input and enable node as she/he will. That leads to the fact that I can have several different output waveforms although I am using same model and stimuli - but different tool!?! I am pretty sure that this topic was already discussed among the people that are using IBIS, but what was the outcome? Is there somebody who is still driving this topics? Is there intention to standardize behavior of inputs to IBIS models? Regards, Radovan - -----Original Message----- From: Xuefeng Chen [mailto:Xuefeng.Chen@synopsys.com] Sent: Friday, August 04, 2006 4:26 AM To: Beal, Weston; Vuletic Radovan (QAG PD PDE MEM); ibis-users@eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Radovan, Weston's suggestions are very good. In addition, I have two points to mention when using HSPICE 1) ".TRAN 1.36e-11 1.36e-09" does not mean exactly the time step is 13.6ps. Dynamic time step control will be used in transient analysis. You can try option DELMAX to set the maximum time step. 2) Input stimulus is dealt with by two voltage thresholds 0.2v and 0.8v which decides the starting time point of buffer's transition. So it's better to set (vhigh+vlow)/2 = 0.5 if you use PULSE voltage source as stimulus. Of course, I think the most important thing is the waveform tables as Weston mentioned. Best regards Xuefeng - -----Original Message----- From: owner-ibis-users@eda-stds.org [mailto:owner-ibis-users@eda-stds.org] On Behalf Of Beal, Weston Sent: 2006?8?4? 2:04 To: Radovan.Vuletic@qimonda.com; ibis-users@eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Radovan, First, you should not expect the curves to line up in time. The IBIS data does not represent all of the output buffer. Generally, the voltage at the pin of an IBIS model will transition sooner than the voltage at the pin of a full transistor-level model. The curves should be the same if you can slide one in time to compensate for this time offset. Try delaying the stimulus to the IBIS model by 30ps. In your pictures I see that the curve shapes are still a little bit off. It's difficult to know what causes this without seeing your simulation files. Look at the IBIS rising and falling waveform tables to see if the time extents are close to the actual transition. You want as many time-points as possible describing the actual transition and not waste them in flat regions. Different simulators deal with the flat regions at the beginning and end of the transition in different ways. I hope this helps a bit. Good Luck! Regards, Weston - -----Original Message----- From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Thursday, August 03, 2006 8:38 AM To: ibis-users@server.eda-stds.org Subject: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi experts, sorry that I trigger the same topic once again, but now it keeps me busy already more than one week and I am pretty sure that the problem is not a way how I extract IBIS model, but somewhere else! Before I elaborate the problem let me notice that I get the same result if I use 2ibis2 or s2ibis3 or if I use HSpice or some company internal analog simulator for extraction of IBIS model. Let me elaborate the problem: 1. IBIS model is generated (say with s2ibis2, but irrelevant, since there is a same result with s2ibis3) 2. I take one of spice decks for extracting rising waveform generated by extraction tool (say a00DQ40.spi) - this should be spice deck for generating 1st rising waveform in typical case. This spice deck of course contains the netlist of my circuit. 3. I modify this spice deck only that I instantiate in it just generated IBIS buffer model (in step 1.) as a B-element - in other words, I just put there IBIS model - B-element and do nothing else 4. stimuli and load for netlist remains the same and I use exactly the same stimuli and load for IBIS model as well (of course, netlist, IBIS model and their stimulus and loads are separated) 5. simulate such modified spice deck with HSpice and compare the outputs: netlist vs. IBIS model Problem: What I expect to get on output is very good overlap between Hspice simulation of netlist and IBIS model, BUT what I get on output is a fact that falling or rising edges don't overlap i.e. there is some 30ps delay (Please take a look on attached snapshots "zoom1.gif" and "zoom2.gif"). Signal "dq_40_ohm" is output of netlist, signal "io_ron_040_hspice_typ". You can see a real delay and not some different slopes due to different loads. Transient analysis is done with (.TRAN 1.36e-11 1.36e-09) - i.e. simulation step (for IBIS extraction) is 13.6ps. What worries me even more is a fact that in some cases (for different stimuli frequencies) I see that rising edges are overlapping and falling are delayed and in some cases (some other frequency of stimuli) I see that falling edges are overlapping and rising are delayed, so I don't know even where should I cut ("taylor") my V-t curves when behavior seems to be so arbitrary and frequency dependant. I know, some of you would say that 20-30ps are no problem, but exactly this 20-30ps are shifting (upwards or downwards) crossing point of rising and falling edges and destroy duty cycle and data eye diagram (target is 800MHz). Problem is independent on slope of stimuli (so with 1ps slope or 100ps of slope of stimuli I see the same result) I know that we should not speak on this forum about tools and vendors and I terribly apologize that I will still mention some of them - but on the end all our models are used with some these tools and I think that it is necessary that we exchange information about our experiences with this tools as well. So the problem is analysed with different tools: - - I see above mentioned problem when simulating with HSpice (versions 2004.09, 2005.03 and 2006.03) netlist vs. IBIS model - - I see effect of above mentioned problem when simulating with ADS - using only IBIS model - rising and falling edge crossing points are shifted same as in HSpice - - with SpecctraQuest (also simulating only with IBIS model) I see the right results! So I am pretty confused, what is correct? A few different simulators, but only one is showing a right result (or at least result that I consider as a proper). What is your experience? Have you noticed something similar? Can somebody from you do the same procedure on one of your designs (compare IBIS vs. HSpice on the same way as I done)? Has somebody an idea, proposal? Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletic Qimonda AG QAG PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@qimonda.com <> <> - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 7 Aug 2006 18:12:38 +0200 From: Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi Sam, many thanks, message understood :-)) Regards, Radovan - -----Original Message----- From: Sam Chitwood [mailto:samchitwood@sigrity.com] Sent: Monday, August 07, 2006 6:10 PM To: Vuletic Radovan (QAG PD PDE MEM); ibis-users@server.eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi Radovan, A 0ps rise time is ok for IBIS because the stimulus signal is simply a trigger for the algorithms to start the transitions; there is nothing physical associated with the stimulus node. However, this is typically not true for transistor-level models so different stimuli are required. A number of EDA tools (but probably not all) use the 0.2 V and 0.8 V trigger points (mainly so that HSPICE decks can be directly used in other tools). This was established a long time ago. The IBIS forum does not commonly discuss 'how' EDA companies should implement capabilities - read the IBIS spec. on Series MOSFET for an example. :-) A percentage of the voltage rail could have been used for the trigger points, but that might require unique stimuli for each rail (and each typ/min/max). The fixed 0.2 and 0.8 scheme allows users to create a database of trigger sub-circuits that can be used with any supply voltage. Now that you know how it works, I think you'll find it useful. I hope I've answered some of your questions. Thanks, Sam - -----Original Message----- From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Monday, August 07, 2006 8:30 AM To: Xuefeng.Chen@synopsys.com; weston.beal@intel.com; ibis-users@server.eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi experts, many thanks Weston and Xuefeng for your answers. I have to apologies that it wasn't immediately clear in my first mail, but I would never send mail to this forum if just delaying of stimuli for 30ps would solve my problems. Problem was, as I wrote in my mail, that in some cases rising edge was showing very good overlap between transistor netlist and IBIS, but falling edges were shifted - in other cases (with some other stimuli frequencies) falling edges were overlapping but rising edges were delayed - this problem unfortunately can't be solved by simple shifting stimuli. Hint that Xuefeng gave was really good (but who really reads such boring stuff as Additional Notes in HSpice SI Guide?). So just to recapitulate for the other people who can see/have the same problem - please find bellow the excerpt out of HSpice SI Guide: "Voltage Thresholds Voltages applied to the input and enable nodes are digital signals. They should be either 0 or 1. You can specify input voltage as: V_in nd_in 0 pulse (0 3.3 0 0.5n 0.5n 4n 8n) However, IC circuit simulation currently detects only two thresholds, 20% and 80% of [0,1] swing, that is, 0.2V and 0.8V. If a buffer is non-inverting and in a LOW state, it starts the transition to a HIGH state, if V_in > 0.8V. If the buffer is in HIGH state, it will start the transition to LOW state, if V_in < 0.2V. Specifying input voltage in the range [0, 3.3V] as in the above example does not make LOW -> HIGH transitions better in any way, but can add uncertainty over the 0.5ns time interval, when the transition actually occurs." - --- end of excerpt Originaly I used PULSE with 100ps rising/falling time with sweep from 0 to 1.5V. (and 0.2V and 0.8V are pretty asymmetrical to this range) When I used PULSE stimuli with 0ps rising and falling waveform and around 10 times finer resolution for simulation (.TRAN 1.36e-11 used for IBIS model extraction and .TRAN 1ps for simulation (although Xuefeng will say that it is perhaps not properly to say, since there is dynamic step control) I saw significantly better data-eye diagram and very good overlap between rising and falling edges - Nice! However, that rises a question if 0ps rising/falling waveforms are physically justified. Q U E S T I O N : ================= Above mentioned problem is kind of missing definition in IBIS models (O.K. not in definition of IBIS, but definitely for usage of IBIS models). Shouldn't be standardized how every tool should approach simulation of IBIS models with respect to input and enable nodes? I mean 0.2V for low and 0.8V for high is very strange - I could accept 20% of Vdd and 80% of Vdd, but to define input thresholds as absolute values, totally independent on technology and supply voltage is somehow user unfriendly (however, in HSpice it is at least mentioned in some additional note). Furthermore, it seems that every tool vendor has freedom to treat/process stimuli to input and enable node as she/he will. That leads to the fact that I can have several different output waveforms although I am using same model and stimuli - but different tool!?! I am pretty sure that this topic was already discussed among the people that are using IBIS, but what was the outcome? Is there somebody who is still driving this topics? Is there intention to standardize behavior of inputs to IBIS models? Regards, Radovan - -----Original Message----- From: Xuefeng Chen [mailto:Xuefeng.Chen@synopsys.com] Sent: Friday, August 04, 2006 4:26 AM To: Beal, Weston; Vuletic Radovan (QAG PD PDE MEM); ibis-users@eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Radovan, Weston's suggestions are very good. In addition, I have two points to mention when using HSPICE 1) ".TRAN 1.36e-11 1.36e-09" does not mean exactly the time step is 13.6ps. Dynamic time step control will be used in transient analysis. You can try option DELMAX to set the maximum time step. 2) Input stimulus is dealt with by two voltage thresholds 0.2v and 0.8v which decides the starting time point of buffer's transition. So it's better to set (vhigh+vlow)/2 = 0.5 if you use PULSE voltage source as stimulus. Of course, I think the most important thing is the waveform tables as Weston mentioned. Best regards Xuefeng - -----Original Message----- From: owner-ibis-users@eda-stds.org [mailto:owner-ibis-users@eda-stds.org] On Behalf Of Beal, Weston Sent: 2006?8?4? 2:04 To: Radovan.Vuletic@qimonda.com; ibis-users@eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Radovan, First, you should not expect the curves to line up in time. The IBIS data does not represent all of the output buffer. Generally, the voltage at the pin of an IBIS model will transition sooner than the voltage at the pin of a full transistor-level model. The curves should be the same if you can slide one in time to compensate for this time offset. Try delaying the stimulus to the IBIS model by 30ps. In your pictures I see that the curve shapes are still a little bit off. It's difficult to know what causes this without seeing your simulation files. Look at the IBIS rising and falling waveform tables to see if the time extents are close to the actual transition. You want as many time-points as possible describing the actual transition and not waste them in flat regions. Different simulators deal with the flat regions at the beginning and end of the transition in different ways. I hope this helps a bit. Good Luck! Regards, Weston - -----Original Message----- From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Thursday, August 03, 2006 8:38 AM To: ibis-users@server.eda-stds.org Subject: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Hi experts, sorry that I trigger the same topic once again, but now it keeps me busy already more than one week and I am pretty sure that the problem is not a way how I extract IBIS model, but somewhere else! Before I elaborate the problem let me notice that I get the same result if I use 2ibis2 or s2ibis3 or if I use HSpice or some company internal analog simulator for extraction of IBIS model. Let me elaborate the problem: 1. IBIS model is generated (say with s2ibis2, but irrelevant, since there is a same result with s2ibis3) 2. I take one of spice decks for extracting rising waveform generated by extraction tool (say a00DQ40.spi) - this should be spice deck for generating 1st rising waveform in typical case. This spice deck of course contains the netlist of my circuit. 3. I modify this spice deck only that I instantiate in it just generated IBIS buffer model (in step 1.) as a B-element - in other words, I just put there IBIS model - B-element and do nothing else 4. stimuli and load for netlist remains the same and I use exactly the same stimuli and load for IBIS model as well (of course, netlist, IBIS model and their stimulus and loads are separated) 5. simulate such modified spice deck with HSpice and compare the outputs: netlist vs. IBIS model Problem: What I expect to get on output is very good overlap between Hspice simulation of netlist and IBIS model, BUT what I get on output is a fact that falling or rising edges don't overlap i.e. there is some 30ps delay (Please take a look on attached snapshots "zoom1.gif" and "zoom2.gif"). Signal "dq_40_ohm" is output of netlist, signal "io_ron_040_hspice_typ". You can see a real delay and not some different slopes due to different loads. Transient analysis is done with (.TRAN 1.36e-11 1.36e-09) - i.e. simulation step (for IBIS extraction) is 13.6ps. What worries me even more is a fact that in some cases (for different stimuli frequencies) I see that rising edges are overlapping and falling are delayed and in some cases (some other frequency of stimuli) I see that falling edges are overlapping and rising are delayed, so I don't know even where should I cut ("taylor") my V-t curves when behavior seems to be so arbitrary and frequency dependant. I know, some of you would say that 20-30ps are no problem, but exactly this 20-30ps are shifting (upwards or downwards) crossing point of rising and falling edges and destroy duty cycle and data eye diagram (target is 800MHz). Problem is independent on slope of stimuli (so with 1ps slope or 100ps of slope of stimuli I see the same result) I know that we should not speak on this forum about tools and vendors and I terribly apologize that I will still mention some of them - but on the end all our models are used with some these tools and I think that it is necessary that we exchange information about our experiences with this tools as well. So the problem is analysed with different tools: - - I see above mentioned problem when simulating with HSpice (versions 2004.09, 2005.03 and 2006.03) netlist vs. IBIS model - - I see effect of above mentioned problem when simulating with ADS - using only IBIS model - rising and falling edge crossing points are shifted same as in HSpice - - with SpecctraQuest (also simulating only with IBIS model) I see the right results! So I am pretty confused, what is correct? A few different simulators, but only one is showing a right result (or at least result that I consider as a proper). What is your experience? Have you noticed something similar? Can somebody from you do the same procedure on one of your designs (compare IBIS vs. HSpice on the same way as I done)? Has somebody an idea, proposal? Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletic Qimonda AG QAG PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305 E-mail: radovan.vuletic@qimonda.com <> <> - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 7 Aug 2006 10:24:51 -0700 From: "Lynne D. Green" Subject: RE: [IBIS-Users] IBIS non-monotonicity issue This is a multi-part message in MIME format. - ------=_NextPart_000_0007_01C6BA0B.B86BD8C0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hello, Sehshari and Vinayak, It is strongly recommended that all four I-V tables cover -Vcc to +2Vcc. Currents are normally 0A above 0V for both POWER and GND clamp tables, unless there is an on-die pullup/pulldown termination. This is because IBIS does not specify how tables are extrapolated when there is no data beyond 0V. Model makers are welcome to submit models to the IBIS Model Review Committee for review. Further information is at http://www.eigroup.org/ibis/support.htm. Best regards, Lynne Lynne Green, Chair, IBIS Model Review Committee _____ From: owner-ibis-users@eda-stds.org [mailto:owner-ibis-users@eda-stds.org] On Behalf Of seshadri.kirankumar@wipro.com Sent: Monday, August 07, 2006 2:57 AM To: vinayak@ti.com; ibis@eda-stds.org Cc: ibis-users@eda-stds.org Subject: RE: [IBIS-Users] IBIS non-monotonicity issue Hi Vinayak, I have noticed below points from the data you pasted herewith 1) what is the significance of generating POWER clamp table for 1.8 to 1.96 ? because this might captured in GND clamp range. 2) if the data started from -1.8 (assuming buffer operating at 1.8V) data is captured till 1.9818V (1.8 + 0.1818182) i.e actual POWER clamp data is present for 1.9818V to 3.6V coming to data present between 1.8V to 1.963636V is actual Vpad of 0V to 0.1636V . usually the voltage value for IV data is as follows Pu/Pd tables --------> -1.8 to 3.6V GND clamp tables ---------> -1.8 to 1.8V POWER clamp tables --------> 1.8V to 3.6V Coming to warning I think data is -1.8 to -0.1818182 follows one order(+vely increasing) after that 1.963636 to 1.8V follows other order (+vely decreasing) Hope this helps you Best Regards Kiran Kumar _____ From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Vinayak Sent: Monday, August 07, 2006 2:03 PM To: ibis@server.eda-stds.org Cc: ibis-users@server.eda-stds.org Subject: [IBIS-Users] IBIS non-monotonicity issue Hi, I was trying run ibischk4 on the ibis model it gives a warning as WARNING (line 165) - POWER Clamp Voltage data is non-monotonic though i could not find any non-monotonicity in the values in the ibis model. -0.2181818 0.1062643m 46.73129u 0.2034879m -0.2 0.106231m 46.71362u 0.2034473m -0.1818182 0.1061977m 46.69595u 0.2034067m 1.963636 0.106169m 46.68056u 0.2033726m 1.945455 0.1061409m 46.66543u 0.2033392m ----> line 165 1.927273 0.1061128m 46.6503u 0.2033058m 1.909091 0.106087m 46.63619u 0.2032756m 1.890909 0.1060628m 46.62276u 0.2032475m 1.872727 0.1060386m 46.60933u 0.2032194m 1.854545 0.1060153m 46.59625u 0.2031925m 1.836364 0.1059939m 46.58398u 0.2031681m 1.818182 0.1059725m 46.57171u 0.2031437m 1.8 0.1059511m 46.55944u 0.2031194m Should i ignore this warning. Regards vinayak The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments. WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email. www.wipro.com - ------=_NextPart_000_0007_01C6BA0B.B86BD8C0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hello, Sehshari and = Vinayak,
 
It is strongly recommended that all four I-V = tables=20 cover -Vcc to +2Vcc.  Currents are normally 0A above 0V for = both POWER=20 and GND clamp tables, unless there is an on-die pullup/pulldown=20 termination.  This is because IBIS does not specify how tables are=20 extrapolated when there is no data beyond 0V.
 
Model makers are welcome to submit models to = the IBIS Model=20 Review Committee for review.  Further information is at http://www.eigroup.org/i= bis/support.htm.
 
Best regards,
Lynne
 
Lynne Green, Chair, IBIS Model Review=20 Committee
 
 

From: = owner-ibis-users@eda-stds.org=20 [mailto:owner-ibis-users@eda-stds.org] On Behalf Of=20 seshadri.kirankumar@wipro.com
Sent: Monday, August 07, = 2006 2:57=20 AM
To: vinayak@ti.com; ibis@eda-stds.org
Cc:=20 ibis-users@eda-stds.org
Subject: RE: [IBIS-Users] IBIS=20 non-monotonicity issue

Hi=20 Vinayak,

 

       =20 I have noticed below points from the data you pasted herewith=20

 

1)      =20 what is=20 the significance of generating POWER clamp table for 1.8 to 1.96 ? = because=20 this might captured in GND clamp range.

2)      =20 if the=20 data started from -1.8 (assuming buffer operating at 1.8V)  data = is=20 captured till 1.9818V (1.8 + 0.1818182) i.e actual = POWER=20 clamp data is present for 1.9818V to 3.6V =

       =20 coming to data present between 1.8V to 1.963636V is actual Vpad = of  0V to=20 0.1636V .

 

usually =  the=20 voltage  value for IV data is as = follows

Pu/Pd = tables=20 ------à  -1.8 = to 3.6V=20

GND clamp = tables=20 -------à -1.8 to=20 1.8V

POWER clamp = tables   ------à 1.8V  = to=20 3.6V

 

Coming to = warning I=20 think  data is -1.8 to -0.1818182 follows=20 one order(+vely increasing) after that=20

1.963636 to 1.8V = follows=20 other order (+vely=20 decreasing)

 

Hope this=20 helps you

 

Best=20 Regards

Kiran=20 Kumar

 

 

From:=20 owner-ibis-users@server.eda-stds.org=20 [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of = Vinayak
Sent: Monday, August 07, 2006 = 2:03=20 PM
To:=20 ibis@server.eda-stds.org
Cc:=20 ibis-users@server.eda-stds.org
Subject: [IBIS-Users] IBIS=20 non-monotonicity issue

 

Hi,

I was = trying=20 run ibischk4 on the ibis model
it gives a warning as =

WARNING=20 (line  165) - POWER Clamp Voltage data is = non-monotonic

though i=20 could not find any non-monotonicity in the values
in the ibis = model.=20

   -0.2181818   = 0.1062643m   =20 46.73129u  =20 0.2034879m
        =20 -0.2    0.106231m    = 46.71362u  =20 0.2034473m
   -0.1818182   = 0.1061977m   =20 46.69595u   0.2034067m
    =20 1.963636    0.106169m    = 46.68056u  =20 0.2033726m
     1.945455  =20 0.1061409m    46.66543u   0.2033392m  = - ---->=20 line 165
     1.927273  =20 0.1061128m     46.6503u  =20 0.2033058m
     1.909091   =20 0.106087m    46.63619u  =20 0.2032756m
     1.890909  =20 0.1060628m    46.62276u  =20 0.2032475m
     1.872727  =20 0.1060386m    46.60933u  =20 0.2032194m
     1.854545  =20 0.1060153m    46.59625u  =20 0.2031925m
     1.836364  =20 0.1059939m    46.58398u  =20 0.2031681m
     1.818182  =20 0.1059725m    46.57171u  =20 0.2031437m
         =20 1.8   0.1059511m    46.55944u  =20 0.2031194m

Should i ignore this warning.=20

Regards
vinayak


The information = contained in=20 this electronic message and any attachments to this message are = intended=20 for the exclusive use of the addressee(s) and may contain = proprietary,=20 confidential or privileged information. If you are not the = intended=20 recipient, you should not disseminate, distribute or copy this = e-mail.=20 Please notify the sender immediately and destroy all copies of = this=20 message and any attachments.

WARNING: Computer viruses = can be=20 transmitted via email. The recipient should check this email and = any=20 attachments for the presence of viruses. The company accepts no=20 liability for any damage caused by any virus transmitted by this = = email.

www.wipro.com
- ------=_NextPart_000_0007_01C6BA0B.B86BD8C0-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 9 Aug 2006 17:46:42 -0700 From: "Mirmak, Michael" Subject: [IBIS-Users] Asian IBIS Summit (Japan) First Announcement The IBIS Open Forum is holding the first Asian IBIS Summit (Japan) Meeting in Tokyo, Japan, where several major companies have design operations and use IBIS. This is an early announcement to aid advance travel planning. JEITA (Japan Electronics and Information Technology Industries Association) is the primary event sponsor with several companies, listed below, acting as co-sponsors. The event will held at JEITA headquarters in Tokyo. Several US experts are expected to participate. We encourage technical contributions from Asia. We expect a full agenda of relevant material. Note that we are also holding a Summit in Shanghai, China on October 27. You may want to consider this in your travel plans. Michael Mirmak Intel Corporation Takeshi Watanabe NEC Electronics Corporation - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (JAPAN) FIRST CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( J A P A N ) Time/Date: Tuesday October 31, 2006, 8:30 AM to 3:00 PM Meeting starts at 9:00 AM Location: JEITA Headquarters 3rd Fl., Mitsui Sumitomo Kaijo Bldg. Annex 11, Kanda Surugadai 3-chome, Chiyoda-ku, Tokyo 101-0062 JAPAN http://www.jeita.or.jp/english/about/location/index.htm Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) EIA IBIS Open Forum Co-sponsors (in alphabetical order): Cybernet Systems (formerly KAW) Synopsys Others to be determined Cost: FREE, including refreshments and lunch Contact us for details regarding sponsorship BACKGROUND This year we holding the first open Asian IBIS Summit (Japan) meeting. Major Japanese companies operate in Tokyo and are affiliated with JEITA and IBIS. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Japanese. Presenters may optionally deliver in Japanese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summit site and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Takeshi Watanabe, NEC Electronics Corp. takeshi.watanabe@necel.com SIGNUP DEADLINE: October 20, 2006 Because of limited space, advance registration is required. CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Microsoft Powerpoint or Adobe PDF Presentation Copies: Available at the meeting for all attendees Presentation Deadline: October 20, 2006 to produce the presentation copies for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in either Japanese or English. Submissions from Asian are encouraged. AGENDA 8:30 - 9:00 Sign in Asian IBIS Summit (Japan) 9:00 - 12:00 Presentations 12:00 - 12:40 Free lunch 12:40 - 15:00 Presentations 15:00 End of Meeting The specific agenda is being developed. We expect seven or eight presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned Several presentations on IBIS applications or modeling issues are expected from co-sponsor companies or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. JEITA suggests the Tokyo Dome Hotel as convenient accommodation. JEITA headquarters is located near several train stations (click image): http://www.jeita.or.jp/english/about/location/index.htm - ----------------------------------------------------------------- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 15 Aug 2006 10:54:53 -0700 From: Bob Ross Subject: [IBIS-Users] Asian IBIS Summit (China) Second Announcement To All: The IBIS Open Forum is holding an Asian IBIS Summit Meeting in Shanghai, China, a major technology center on Friday, October 27. This is an early second announcement for longer term travel planning. Several companies listed below are co-sponsoring this large event to be held at the luxurious Radisson Hotel Shanghai New World. Like last year, We are planning for about 150 - 200 attendees including several IBIS experts from the USA. We encourage technical contributions from Asia. We expect a full agenda of relevant material. Note, we are also planning a Summit in Tokyo, Japan on October 31, announced separately. You may want to consider this in you travel plans. Bob Ross Teraspeed Consulting Group Lance Wang Cadence Design Systems - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (CHINA) SECOND CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- http://www.eda-stds.org/pub/ibis/summits/oct06a/announcement_chinese.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( C H I N A ) Time/Date: Friday October 27, 2006, 8:00 AM to 5:30 PM Meeting starts at 9:00 AM Location: Radisson Hotel Shanghai New World 88 Nanjing Road (W) Shanghai 200003 CHINA Tel: + 86-21-63599999 Fax: + 86-21-63589705 E-mail newworld@radisson-nw.com http://www.radisson.com/shanghaicn_newworld Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Primary Sponsor: Huawei Technologies Co-sponsors (in alphabetical order): Ansoft Corporation, Cadence Design Systems, Intel Corporation, Mentor Graphics Corporation, Signal Integrity Software (SiSoft), Sigrity, and Synopsys. Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND Last December we held a successful meeting in Shenzhen. This year we are moving to Shanghai another special economic zone in the Peoples Republic of China with many high technology companies and many development and sales offices of foreign companies. Many sites of interest are near the conference hotel. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register using the information below: Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Comments: (Such as assistance for the travel requirements at the end) Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Lance Wang, Cadence Design Systems lwang@cadence.com SIGNUP DEADLINE: October 20, 2006 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: September 29, 2006 to produce the presentation booklet for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in a Chinese. Submissions from Asia are encouraged. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:15 - 9:00 Sign in, casual conversation, vendor tables 9:00 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 17:30 Presentations 17:30 - 18:30 Casual conversations, vendor tables The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned. Several presentations on IBIS applications and behavioral modeling issues, including interconnects and system components, are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. A link to the Radisson Hotel Shanghai New World is: http://www.radisson.com/shanghaicn_newworld Comply with your travel rules, such as indicated in the link below to China and Shanghai. Work with your travel agent. Notify us as a sign-up comment if you need assistance. Visas, if needed, should fall in the visit/business category: http://www.travelchinaguide.com/embassy/visa.htm - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 22 Aug 2006 14:37:57 +0530 From: Ravi Kumar DS Subject: [IBIS-Users] Not recieving any mails from IBIS group. Hi , I am not able to recieve mails from the IBIS group from past two months. Please let me know. Regards, Ravi - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 29 Aug 2006 18:40:20 -0700 From: Bob Ross Subject: [IBIS-Users] Asian IBIS Summit (China) Third Announcement To All: The IBIS Open Forum is holding an Asian IBIS Summit Meeting in Shanghai, China, a major technology center on Friday, October 27. This is a third announcement for longer term travel planning. Several companies listed below are co-sponsoring this large event to be held at the luxurious Radisson Hotel Shanghai New World. Like last year, We are planning for about 150 - 200 attendees including several IBIS experts from the USA. We encourage technical contributions from Asia. We expect a full agenda of relevant material. Note, we are also planning a Summit in Tokyo, Japan on October 31, announced separately. You may want to consider this in you travel plans. Bob Ross Teraspeed Consulting Group Lance Wang Cadence Design Systems - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (CHINA) THIRD CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- http://www.eda-stds.org/pub/ibis/summits/oct06a/announcement_chinese.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( C H I N A ) Time/Date: Friday October 27, 2006, 8:00 AM to 5:30 PM Meeting starts at 9:00 AM Location: Radisson Hotel Shanghai New World 88 Nanjing Road (W) Shanghai 200003 CHINA Tel: + 86-21-63599999 Fax: + 86-21-63589705 E-mail newworld@radisson-nw.com http://www.radisson.com/shanghaicn_newworld Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Primary Sponsor: Huawei Technologies Co-sponsors (in alphabetical order): Ansoft Corporation, Cadence Design Systems, Intel Corporation, Mentor Graphics Corporation, Signal Integrity Software (SiSoft), Sigrity, and Synopsys. Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND Last December we held a successful meeting in Shenzhen. This year we are moving to Shanghai another special economic zone in the Peoples Republic of China with many high technology companies and many development and sales offices of foreign companies. Many sites of interest are near the conference hotel. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register using the information below: Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Comments: (Such as assistance for the travel requirements at the end) Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Lance Wang, Cadence Design Systems lwang@cadence.com SIGNUP DEADLINE: October 20, 2006 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: September 29, 2006 to produce the presentation booklet for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in a Chinese. Submissions from Asia are encouraged. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:15 - 9:00 Sign in, casual conversation, vendor tables 9:00 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 17:30 Presentations 17:30 - 18:30 Casual conversations, vendor tables The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned. Several presentations on IBIS applications and behavioral modeling issues, including interconnects and system components, are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. A link to the Radisson Hotel Shanghai New World is: http://www.radisson.com/shanghaicn_newworld Comply with your travel rules, such as indicated in the link below to China and Shanghai. Work with your travel agent. Notify us as a sign-up comment if you need assistance. Visas, if needed, should fall in the visit/business category: http://www.travelchinaguide.com/embassy/visa.htm - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 31 Aug 2006 23:08:52 -0700 From: "Mirmak, Michael" Subject: [IBIS-Users] Asian IBIS Summit (Japan) Announcement The IBIS Open Forum is holding the first Asian IBIS Summit (Japan) Meeting in Tokyo, Japan, where several major companies have design operations and use IBIS. This is an updated announcement to aid travel planning. JEITA (Japan Electronics and Information Technology Industries Association) is the primary event sponsor with several companies, listed below, acting as co-sponsors. The event will held at JEITA headquarters in Tokyo. Several US experts are expected to participate. We encourage technical contributions from Asia. We expect a full agenda of relevant material. Note that we are also holding a Summit in Shanghai, China on October 27. You may want to consider this in your travel plans. Michael Mirmak Intel Corporation Takeshi Watanabe NEC Electronics Corporation - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (JAPAN) CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( J A P A N ) Time/Date: Tuesday October 31, 2006, 8:30 AM to 3:00 PM Meeting starts at 9:00 AM Location: JEITA Headquarters 3rd Fl., Mitsui Sumitomo Kaijo Bldg. Annex 11, Kanda Surugadai 3-chome, Chiyoda-ku, Tokyo 101-0062 JAPAN http://www.jeita.or.jp/english/about/location/index.htm Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) EIA IBIS Open Forum Co-sponsors (in alphabetical order): ATE Service Corporation (Sigrity) Cadence Design Systems Cybernet Systems (formerly KAW) Synopsys Others to be determined Cost: FREE, including refreshments and lunch Contact us for details regarding sponsorship BACKGROUND This year we holding the first open Asian IBIS Summit (Japan) meeting. Major Japanese companies operate in Tokyo and are affiliated with JEITA and IBIS. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Japanese. Presenters may optionally deliver in Japanese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summit site and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Takeshi Watanabe, NEC Electronics Corp. takeshi.watanabe@necel.com SIGNUP DEADLINE: October 20, 2006 Because of limited space, advance registration is required. CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Microsoft Powerpoint or Adobe PDF Presentation Copies: Available at the meeting for all attendees Presentation Deadline: October 20, 2006 to produce the presentation copies for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in either Japanese or English. Submissions from Asian are encouraged. AGENDA 8:30 - 9:00 Sign in Asian IBIS Summit (Japan) 9:00 - 12:00 Presentations 12:00 - 12:40 Free lunch 12:40 - 15:00 Presentations 15:00 End of Meeting The specific agenda is being developed. We expect seven or eight presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned Several presentations on IBIS applications or modeling issues are expected from co-sponsor companies or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. JEITA suggests the Tokyo Dome Hotel as convenient accommodation. JEITA headquarters is located near several train stations (click image): http://www.jeita.or.jp/english/about/location/index.htm - ----------------------------------------------------------------- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 05 Sep 2006 12:47:57 +0530 From: "Siva Nageswara Rao Borra" Subject: [IBIS-Users] How to obtain Golden waveforms of ver 4.x? Hi Expert, I need help regarding how to obtain the Golden waveforms mentioned in the IBIS version 4.x ? And where they are useful? Thanks in Advance for your help. With best regards, Siva Borra. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 05 Sep 2006 12:49:10 +0530 From: "Siva Nageswara Rao Borra" Subject: [IBIS-Users] Is there any valid IBIS version 4.x file available for sharing? Hi Expert, Can anybody explain with an example , how a version 4.x file looks like? And how to obtain the [Test Data] and [Test Load] parameters of Version 4.x? I have encountered errors while I used ibichk4 on the example available on http://www.vhdl.org/pub/ibis/samples/ver4.1/ Any help would be appriciated, thanks in advance. Regards, Siva Borra. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 05 Sep 2006 12:49:43 +0530 From: "Siva Nageswara Rao Borra" Subject: [IBIS-Users] Re: How and where Alternate Package Models of IBIS Version 4.x gets used? Hi Expert, > Can anybody give a clarity on how the > additional/alternate package models are helpful > and also how they can be supplied? > This is regarding the [Alternate Package]/[End Alternate] Package > models, available on IBIS version 4.x. > > Thanks in advance for your support. > > With best regards, > Siva Borra. > > - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Sep 2006 08:37:23 -0700 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] Is there any valid IBIS version 4.x file available for sharing? Siva, Thanks for your question regarding IBIS. Please ensure that you are using the latest version of ibischk4, including support of 4.1 keywords and features. The latest executables can be downloaded from: http://www.eda-stds.org/ibis/ibischk4/. Note that the sample "ideal_driver.ibs" in the subdirectory you mention has improperly commented out the [Pulldown] keyword. Removing the | character from the beginning of that line will ensure that the file passes the 4.1.1 parser. We will correct the posted materials. - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao Borra Sent: Tuesday, September 05, 2006 00:19 To: ibis-users@server.eda.org Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com Subject: [IBIS-Users] Is there any valid IBIS version 4.x file available for sharing? Hi Expert, Can anybody explain with an example , how a version 4.x file looks like? And how to obtain the [Test Data] and [Test Load] parameters of Version 4.x? I have encountered errors while I used ibichk4 on the example available on http://www.vhdl.org/pub/ibis/samples/ver4.1/ Any help would be appriciated, thanks in advance. Regards, Siva Borra. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Sep 2006 08:48:41 -0700 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] Re: How and where Alternate Package Models of IBIS Version 4.x gets used? Siva, The alternate package keywords simply enable model authors to reference different package electrical descriptions for components that feature identical buffer designs. For example, a component that is available in both DIP and surface-mount packages could be represented using one IBIS file. This file would contain the buffer information in the appropriate [Model] keywords and include one set of package information under the [Package Model] keyword. Electrical data for any other available package designs could be referenced under the [Alternate Package Model] keyword. - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao Borra Sent: Tuesday, September 05, 2006 00:20 To: ibis-users@server.eda.org Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com Subject: [IBIS-Users] Re: How and where Alternate Package Models of IBIS Version 4.x gets used? Hi Expert, > Can anybody give a clarity on how the > additional/alternate package models are helpful > and also how they can be supplied? > This is regarding the [Alternate Package]/[End Alternate] Package > models, available on IBIS version 4.x. > > Thanks in advance for your support. > > With best regards, > Siva Borra. > > - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Sep 2006 09:39:41 -0700 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] How to obtain Golden waveforms of ver 4.x? Siva, The "golden waveforms" are mentioned in the context of the [Test Data] and [Test Load] keywords. These are waveforms generated using the original circuit design on which the IBIS data is based. [Test Data] can be included in an IBIS file to give recipients an idea of how well the IBIS data, particularly after interpretation by an EDA SI tool, matches the original circuit design's output for a given load condition. For example, one could verify both the usage of the [Driver Schedule] keyword in a particular tool and the data behind it by comparing it to [Test Data] generated for the same test load and environmental conditions. If the [Test Data] and tool output match, then the tool is implementing the proper combination of the [Driver Schedule] sections for that buffer design, test conditions and data pattern. - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao Borra Sent: Tuesday, September 05, 2006 00:18 To: ibis-users@server.eda.org Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com Subject: [IBIS-Users] How to obtain Golden waveforms of ver 4.x? Hi Expert, I need help regarding how to obtain the Golden waveforms mentioned in the IBIS version 4.x ? And where they are useful? Thanks in Advance for your help. With best regards, Siva Borra. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 07 Sep 2006 12:49:09 +0530 From: "Siva Nageswara Rao Borra" Subject: Re: [IBIS-Users] Is there any valid IBIS version 4.x file available for sharing? Michael, Thank you. I have a doubt regarding the external model in the example. What information one has to discolse in Verilog/VHDL AMS? Is it buffer description or interconnect description? And where do I get the information from? Is it from IO library? Is it the case that disclosing the VHDL/Verilog Description, violates the basic purpose of IBIS ( which keeps SPICE netlist Propriotory). Regards, Siva Borra Mirmak, Michael wrote: >Siva, > >Thanks for your question regarding IBIS. Please ensure that you are >using the latest version of ibischk4, including support of 4.1 keywords >and features. The latest executables can be downloaded from: > >http://www.eda-stds.org/ibis/ibischk4/. > >Note that the sample "ideal_driver.ibs" in the subdirectory you mention >has improperly commented out the [Pulldown] keyword. Removing the | >character from the beginning of that line will ensure that the file >passes the 4.1.1 parser. We will correct the posted materials. > >- Michael Mirmak > Intel Corp. > Chair, EIA IBIS Open Forum > >-----Original Message----- >From: owner-ibis-users@server.eda.org >[mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao >Borra >Sent: Tuesday, September 05, 2006 00:19 >To: ibis-users@server.eda.org >Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com >Subject: [IBIS-Users] Is there any valid IBIS version 4.x file available >for sharing? > >Hi Expert, >Can anybody explain with an example , how a version 4.x file looks >like? > And how to obtain the [Test Data] and [Test Load] parameters of >Version 4.x? >I have encountered errors while I used ibichk4 on the example available >on >http://www.vhdl.org/pub/ibis/samples/ver4.1/ >Any help would be appriciated, thanks in advance. >Regards, >Siva Borra. > > > >-------------------------------------------------------------------- >|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >|with the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or e-mail a request to ibis-request@eda-stds.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda-stds.org/pub/ibis/email_archive/ Recent >| http://www.eda-stds.org/pub/ibis/users_archive/ Recent >| http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 > >-------------------------------------------------------------------- >|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >|with the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or e-mail a request to ibis-request@eda-stds.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda-stds.org/pub/ibis/email_archive/ Recent >| http://www.eda-stds.org/pub/ibis/users_archive/ Recent >| http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 > > > > - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 07 Sep 2006 13:40:30 +0530 From: "Siva Nageswara Rao Borra" Subject: Re: [IBIS-Users] How to obtain Golden waveforms of ver 4.x? Michael, The rising and falling waveforms are drawn considering the parameters, L_dut, R_dut, C_dut, when applied the load with L_fixture, R_fixture, C_fixture. Where as the Golden waveforms are obtained at two different points with [test load] and [test data] conditions are applied. My doubt is how will we get the [test load]/[test data] parameters? Are there any default values for these? Can you tell me how can we obtain the golden waveforms from spectre for the buffer example shown in open source s2ibis3 download from http://www.ece.ncsu.edu/erl/ibis/s2ibis3/s2ibis3.htm? s2ibis3/example/ex1/buffer.ibs. Regards, Siva Borra. Mirmak, Michael wrote: >Siva, > >The "golden waveforms" are mentioned in the context of the [Test Data] >and [Test Load] keywords. These are waveforms generated using the >original circuit design on which the IBIS data is based. [Test Data] >can be included in an IBIS file to give recipients an idea of how well >the IBIS data, particularly after interpretation by an EDA SI tool, >matches the original circuit design's output for a given load condition. > > >For example, one could verify both the usage of the [Driver Schedule] >keyword in a particular tool and the data behind it by comparing it to >[Test Data] generated for the same test load and environmental >conditions. If the [Test Data] and tool output match, then the tool is >implementing the proper combination of the [Driver Schedule] sections >for that buffer design, test conditions and data pattern. > >- Michael Mirmak > Intel Corp. > Chair, EIA IBIS Open Forum > > >-----Original Message----- >From: owner-ibis-users@server.eda.org >[mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao >Borra >Sent: Tuesday, September 05, 2006 00:18 >To: ibis-users@server.eda.org >Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com >Subject: [IBIS-Users] How to obtain Golden waveforms of ver 4.x? > >Hi Expert, > I need help regarding how to obtain the Golden waveforms >mentioned in the >IBIS version 4.x ? And where they are useful? >Thanks in Advance for your help. >With best regards, >Siva Borra. > > > > >-------------------------------------------------------------------- >|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >|with the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or e-mail a request to ibis-request@eda-stds.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda-stds.org/pub/ibis/email_archive/ Recent >| http://www.eda-stds.org/pub/ibis/users_archive/ Recent >| http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 > >-------------------------------------------------------------------- >|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >|with the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or e-mail a request to ibis-request@eda-stds.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda-stds.org/pub/ibis/email_archive/ Recent >| http://www.eda-stds.org/pub/ibis/users_archive/ Recent >| http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 > > > > - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 07 Sep 2006 14:01:50 +0530 From: "Siva Nageswara Rao Borra" Subject: Re: [IBIS-Users] Re: How and where Alternate Package Models of IBIS Version 4.x gets used? This is a multi-part message in MIME format. - --------------010107000201040701090805 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Hi Michael, Thank you very much. While obtaining data for Pullup,Pulldown and waveform data, we can consider only one package, the how would be the extra package information is useful to the user? Regards, Siva Borra. Mirmak, Michael wrote: >Siva, > >The alternate package keywords simply enable model authors to reference >different package electrical descriptions for components that feature >identical buffer designs. For example, a component that is available in >both DIP and surface-mount packages could be represented using one IBIS >file. This file would contain the buffer information in the appropriate >[Model] keywords and include one set of package information under the >[Package Model] keyword. Electrical data for any other available >package designs could be referenced under the [Alternate Package Model] >keyword. > >- Michael Mirmak > Intel Corp. > Chair, EIA IBIS Open Forum > >-----Original Message----- >From: owner-ibis-users@server.eda.org >[mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao >Borra >Sent: Tuesday, September 05, 2006 00:20 >To: ibis-users@server.eda.org >Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com >Subject: [IBIS-Users] Re: How and where Alternate Package Models of IBIS >Version 4.x gets used? > >Hi Expert, > > > >> Can anybody give a clarity on how the >>additional/alternate package models are helpful >>and also how they can be supplied? >>This is regarding the [Alternate Package]/[End Alternate] Package >>models, available on IBIS version 4.x. >> >>Thanks in advance for your support. >> >>With best regards, >>Siva Borra. >> >> >> >> > > > >-------------------------------------------------------------------- >|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >|with the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or e-mail a request to ibis-request@eda-stds.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda-stds.org/pub/ibis/email_archive/ Recent >| http://www.eda-stds.org/pub/ibis/users_archive/ Recent >| http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 > >-------------------------------------------------------------------- >|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >|with the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or e-mail a request to ibis-request@eda-stds.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda-stds.org/pub/ibis/email_archive/ Recent >| http://www.eda-stds.org/pub/ibis/users_archive/ Recent >| http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 > > > > - --------------010107000201040701090805 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Michael,

                 Thank you very much.
While obtaining data for Pullup,Pulldown and waveform data,
we can consider only one package,  the how would be the  extra package information is useful to the user?

Regards,
Siva Borra.

Mirmak, Michael wrote:
Siva,

The alternate package keywords simply enable model authors to reference
different package electrical descriptions for components that feature
identical buffer designs.  For example, a component that is available in
both DIP and surface-mount packages could be represented using one IBIS
file.  This file would contain the buffer information in the appropriate
[Model] keywords and include one set of package information under the
[Package Model] keyword.  Electrical data for any other available
package designs could be referenced under the [Alternate Package Model]
keyword.

- - Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum 

- -----Original Message-----
From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao
Borra
Sent: Tuesday, September 05, 2006 00:20
To: ibis-users@server.eda.org
Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com
Subject: [IBIS-Users] Re: How and where Alternate Package Models of IBIS
Version 4.x gets used?

Hi Expert,

  
               Can anybody give a clarity on how the 
additional/alternate package models are helpful
and also how they can be supplied?
This is regarding the [Alternate Package]/[End Alternate] Package 
models, available on IBIS version 4.x.

Thanks in advance for your support.

With best regards,
Siva Borra.


    



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- --------------010107000201040701090805-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 7 Sep 2006 09:06:01 -0700 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] Re: How and where Alternate Package Models of IBIS Version 4.x gets used? This is a multi-part message in MIME format. - ------_=_NextPart_001_01C6D297.84359AE4 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Siva, =20 In your comments, you imply that you are including the package when extracting the [Model] I-V and transient waveform information for your buffers. I would hope that this is not the case. =20 =20 The IBIS structure assumes that the buffer information is extracted separately from the package. Multiple package model sets, through the [Alternate Package Model] keyword, therefore enable users of the IBIS file for the component to use one set of buffer models with multiple package designs. =20 - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum ________________________________ From: Siva Nageswara Rao Borra [mailto:siva@india.nsc.com]=20 Sent: Thursday, September 07, 2006 01:32 To: Mirmak, Michael Cc: Siva Borra; ibis-users@eda.org; deepti@india.nsc.com Subject: Re: [IBIS-Users] Re: How and where Alternate Package Models of IBIS Version 4.x gets used? Hi Michael, Thank you very much. While obtaining data for Pullup,Pulldown and waveform data, we can consider only one package, the how would be the extra package information is useful to the user? Regards, Siva Borra.=20 Mirmak, Michael wrote: Siva, =09 The alternate package keywords simply enable model authors to reference different package electrical descriptions for components that feature identical buffer designs. For example, a component that is available in both DIP and surface-mount packages could be represented using one IBIS file. This file would contain the buffer information in the appropriate [Model] keywords and include one set of package information under the [Package Model] keyword. Electrical data for any other available package designs could be referenced under the [Alternate Package Model] keyword. =09 - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum=20 =09 -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao Borra Sent: Tuesday, September 05, 2006 00:20 To: ibis-users@server.eda.org Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com Subject: [IBIS-Users] Re: How and where Alternate Package Models of IBIS Version 4.x gets used? =09 Hi Expert, =09 =20 Can anybody give a clarity on how the=20 additional/alternate package models are helpful and also how they can be supplied? This is regarding the [Alternate Package]/[End Alternate] Package=20 models, available on IBIS version 4.x. =09 Thanks in advance for your support. =09 With best regards, Siva Borra. =09 =09 =20 =09 =09 =09 =09 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 =09 =09 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 =09 =09 =20 - ------_=_NextPart_001_01C6D297.84359AE4 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Siva,
 
In your comments, you imply that you=20 are including the package when extracting the [Model] I-V and = transient=20 waveform information for your buffers.  I = would hope that=20 this is not the case. 
 
The = IBIS structure=20 assumes that the buffer information is extracted separately from the=20 package.  Multiple package model sets, through the [Alternate=20 Package Model] keyword, therefore enable users of the IBIS = file for=20 the component to use one set of buffer models with multiple package=20 designs.
 
- Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open = Forum

From: Siva Nageswara Rao Borra=20 [mailto:siva@india.nsc.com]
Sent: Thursday, September 07, = 2006=20 01:32
To: Mirmak, Michael
Cc: Siva Borra;=20 ibis-users@eda.org; deepti@india.nsc.com
Subject: Re: = [IBIS-Users] Re:=20 How and where Alternate Package Models of IBIS Version 4.x gets=20 used?

Hi=20 Michael,

         &nb= sp;      =20 Thank you very much.
While obtaining data for Pullup,Pulldown and = waveform=20 data,
we can consider only one package,  the how would be = the =20 extra package information is useful to the user?

Regards,
Siva = Borra.=20

Mirmak, Michael wrote:
Siva,

The alternate package keywords simply enable model authors to reference
different package electrical descriptions for components that feature
identical buffer designs.  For example, a component that is available in
both DIP and surface-mount packages could be represented using one IBIS
file.  This file would contain the buffer information in the appropriate
[Model] keywords and include one set of package information under the
[Package Model] keyword.  Electrical data for any other available
package designs could be referenced under the [Alternate Package Model]
keyword.

- - Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum=20

- -----Original Message-----
From: owner-ibis-users@server.e=
da.org
[mailto:owner-ibis-users@s=
erver.eda.org] On Behalf Of Siva Nageswara Rao
Borra
Sent: Tuesday, September 05, 2006 00:20
To: ibis-users@server.eda.org
Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com
Subject: [IBIS-Users] Re: How and where Alternate Package Models of IBIS
Version 4.x gets used?

Hi Expert,

  
               Can anybody =
give a clarity on how the=20
additional/alternate package models are helpful
and also how they can be supplied?
This is regarding the [Alternate Package]/[End Alternate] Package=20
models, available on IBIS version 4.x.

Thanks in advance for your support.

With best regards,
Siva Borra.


    



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pub/ibis/email/         E-mail since 1993

- ------_=_NextPart_001_01C6D297.84359AE4-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 08 Sep 2006 15:27:32 +0530 From: "Siva Nageswara Rao Borra" Subject: Re: [IBIS-Users] Re: How and where Alternate Package Models of IBIS Version 4.x gets used? This is a multi-part message in MIME format. - --------------080109040104060207050508 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Michael, Thank you for correcting me. Now it is clear. Please help me in clarification regarding the Golden waveforms and [test data] , [test load], and external models which I posted earlier. Thanks and regards, Siva Borra. Mirmak, Michael wrote: > Siva, > > In your comments, you imply that you are including the package when > extracting the [Model] I-V and transient waveform information for your > buffers. I would hope that this is not the case. > > The IBIS structure assumes that the buffer information is extracted > separately from the package. Multiple package model sets, through the > [Alternate Package Model] keyword, therefore enable users of the IBIS > file for the component to use one set of buffer models with multiple > package designs. > > - Michael Mirmak > Intel Corp. > Chair, EIA IBIS Open Forum > > ------------------------------------------------------------------------ > *From:* Siva Nageswara Rao Borra [mailto:siva@india.nsc.com] > *Sent:* Thursday, September 07, 2006 01:32 > *To:* Mirmak, Michael > *Cc:* Siva Borra; ibis-users@eda.org; deepti@india.nsc.com > *Subject:* Re: [IBIS-Users] Re: How and where Alternate Package Models > of IBIS Version 4.x gets used? > > Hi Michael, > > Thank you very much. > While obtaining data for Pullup,Pulldown and waveform data, > we can consider only one package, the how would be the extra package > information is useful to the user? > > Regards, > Siva Borra. > > Mirmak, Michael wrote: > >>Siva, >> >>The alternate package keywords simply enable model authors to reference >>different package electrical descriptions for components that feature >>identical buffer designs. For example, a component that is available in >>both DIP and surface-mount packages could be represented using one IBIS >>file. This file would contain the buffer information in the appropriate >>[Model] keywords and include one set of package information under the >>[Package Model] keyword. Electrical data for any other available >>package designs could be referenced under the [Alternate Package Model] >>keyword. >> >>- Michael Mirmak >> Intel Corp. >> Chair, EIA IBIS Open Forum >> >>-----Original Message----- >>From: owner-ibis-users@server.eda.org >>[mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao >>Borra >>Sent: Tuesday, September 05, 2006 00:20 >>To: ibis-users@server.eda.org >>Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com >>Subject: [IBIS-Users] Re: How and where Alternate Package Models of IBIS >>Version 4.x gets used? >> >>Hi Expert, >> >> >> >>> Can anybody give a clarity on how the >>>additional/alternate package models are helpful >>>and also how they can be supplied? >>>This is regarding the [Alternate Package]/[End Alternate] Package >>>models, available on IBIS version 4.x. >>> >>>Thanks in advance for your support. >>> >>>With best regards, >>>Siva Borra. >>> >>> >>> >>> >> >> >> >>-------------------------------------------------------------------- >>|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >>|with the appropriate command message(s) in the body: >>| >>| help >>| subscribe ibis >>| subscribe ibis-users >>| unsubscribe ibis >>| unsubscribe ibis-users >>| >>|or e-mail a request to ibis-request@eda-stds.org. >>| >>|IBIS reflector archives exist under: >>| >>| http://www.eda-stds.org/pub/ibis/email_archive/ Recent >>| http://www.eda-stds.org/pub/ibis/users_archive/ Recent >>| http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 >> >>-------------------------------------------------------------------- >>|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >>|with the appropriate command message(s) in the body: >>| >>| help >>| subscribe ibis >>| subscribe ibis-users >>| unsubscribe ibis >>| unsubscribe ibis-users >>| >>|or e-mail a request to ibis-request@eda-stds.org. >>| >>|IBIS reflector archives exist under: >>| >>| http://www.eda-stds.org/pub/ibis/email_archive/ Recent >>| http://www.eda-stds.org/pub/ibis/users_archive/ Recent >>| http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 >> >> >> >> > - --------------080109040104060207050508 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Michael,
            Thank you for correcting me.
Now it is clear.
Please help me in clarification regarding the  Golden waveforms and  [test  data]  ,  [test load],
and external models which I posted earlier.

Thanks and regards,
Siva Borra.

Mirmak, Michael wrote:
Siva,
 
In your comments, you imply that you are including the package when extracting the [Model] I-V and transient waveform information for your buffers.  I would hope that this is not the case. 
 
The IBIS structure assumes that the buffer information is extracted separately from the package.  Multiple package model sets, through the [Alternate Package Model] keyword, therefore enable users of the IBIS file for the component to use one set of buffer models with multiple package designs.
 
- Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum

From: Siva Nageswara Rao Borra [mailto:siva@india.nsc.com]
Sent: Thursday, September 07, 2006 01:32
To: Mirmak, Michael
Cc: Siva Borra; ibis-users@eda.org; deepti@india.nsc.com
Subject: Re: [IBIS-Users] Re: How and where Alternate Package Models of IBIS Version 4.x gets used?

Hi Michael,

                 Thank you very much.
While obtaining data for Pullup,Pulldown and waveform data,
we can consider only one package,  the how would be the  extra package information is useful to the user?

Regards,
Siva Borra.

Mirmak, Michael wrote:
Siva,

The alternate package keywords simply enable model authors to reference
different package electrical descriptions for components that feature
identical buffer designs.  For example, a component that is available in
both DIP and surface-mount packages could be represented using one IBIS
file.  This file would contain the buffer information in the appropriate
[Model] keywords and include one set of package information under the
[Package Model] keyword.  Electrical data for any other available
package designs could be referenced under the [Alternate Package Model]
keyword.

- - Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum 

- -----Original Message-----
From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Siva Nageswara Rao
Borra
Sent: Tuesday, September 05, 2006 00:20
To: ibis-users@server.eda.org
Cc: Siva Nageswara Rao Borra; deepti@india.nsc.com
Subject: [IBIS-Users] Re: How and where Alternate Package Models of IBIS
Version 4.x gets used?

Hi Expert,

  
               Can anybody give a clarity on how the 
additional/alternate package models are helpful
and also how they can be supplied?
This is regarding the [Alternate Package]/[End Alternate] Package 
models, available on IBIS version 4.x.

Thanks in advance for your support.

With best regards,
Siva Borra.


    



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- --------------080109040104060207050508-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Sep 2006 14:17:18 +0200 From: Roberto IZZI Subject: [IBIS-Users] Open drain strange behaviour Hello everybody I 'd like to have some information about a strange behaviour of Open drain buffer Ibis model. I have noticed a mismatch between Transistor level and Ibis model voltage output during a transient analysis. In fact in presence of the same input voltage wave and the same value of load resistance (for example 70 ohm), we can observe a delay between TL output and Ibis output. This delay is the same if we change the value of load resistance. What is the cause of this strange behaviour? Thanks and best regards Roberto Izzi - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Sep 2006 16:48:26 +0200 From: Roberto IZZI Subject: [IBIS-Users] Re: [IBIS] Open drain strange behaviour This is a multi-part message in MIME format. - --------------080206060808090907030200 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Hello Michael thanks for your feedback. In my Open drain Ibis model there is no extra delay portion, because I have inserted as falling and rising waveform tables the result of transistor level simulation, that I am considering for comparison. I obtain this delay both Eldo and Hspice simulation. Best regards Roberto Michael Schaeder wrote: >Hello Roberto, > >I guess there is an extra delay portion in the >[Rising/Falling Waveform]s of your IBIS model. > >Regards, Mic. > >Monday, September 11, 2006, 2:17:18 PM, you wrote: > > > >>Hello everybody >> >> I 'd like to have some information about a strange behaviour of Open >>drain buffer >> Ibis model. I have noticed a mismatch between Transistor level and >>Ibis model >> voltage output during a transient analysis. In fact in presence of the >>same input voltage >> wave and the same value of load resistance (for example 70 ohm), >> we can observe a delay between TL output and Ibis output. This delay >>is the same >> if we change the value of load resistance. What is the cause of this >>strange behaviour? >> >> Thanks and best regards >> >> Roberto Izzi >> >> >-- >Dipl. Ing. Michael Schaeder Tel: +49 5251-150-670 >Zuken - EMC Technology Center Fax: +49 5251-150-700 >Vattmannstrasse 3 E-mail: Michael.Schaeder@pad.zuken.de >D-33100 Paderborn Web: www.zuken.com >Germany PGP Key: http://mail.pad.zuken.de/~mic/msc.asc > >-------------------------------------------------------------------- >|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >|with the appropriate command message(s) in the body: >| >| help >| subscribe ibis >| subscribe ibis-users >| unsubscribe ibis >| unsubscribe ibis-users >| >|or e-mail a request to ibis-request@eda-stds.org. >| >|IBIS reflector archives exist under: >| >| http://www.eda-stds.org/pub/ibis/email_archive/ Recent >| http://www.eda-stds.org/pub/ibis/users_archive/ Recent >| http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 > > - --------------080206060808090907030200 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Hello Michael

  thanks for your feedback.
  In my Open drain Ibis model there is no extra delay portion,
  because I have inserted as falling and rising waveform tables
  the result of transistor level simulation, that I am considering
  for comparison.
  I obtain this delay both Eldo and Hspice simulation.

  Best regards

             Roberto

Michael Schaeder wrote:
Hello Roberto,

I guess there is an extra delay portion in the
[Rising/Falling Waveform]s of your IBIS model.

Regards, Mic.

Monday, September 11, 2006, 2:17:18 PM, you wrote:

  
Hello everybody

  I 'd like to have some information about a strange behaviour of Open
drain buffer
  Ibis model. I have noticed a mismatch between Transistor level and 
Ibis model
  voltage output during a transient analysis. In fact in presence of the
same input voltage
  wave and the same value of load resistance (for example 70 ohm),
  we can observe a delay between TL output and Ibis output. This delay
is the same
  if we change the value of  load resistance. What is the cause of this
strange behaviour?

  Thanks and best regards

        Roberto Izzi
    
--
Dipl. Ing. Michael Schaeder                   Tel: +49 5251-150-670
Zuken - EMC Technology Center                 Fax: +49 5251-150-700
Vattmannstrasse 3             E-mail: Michael.Schaeder@pad.zuken.de
D-33100 Paderborn                                Web: www.zuken.com
Germany              PGP Key: http://mail.pad.zuken.de/~mic/msc.asc

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|  http://www.eda-stds.org/pub/ibis/users_archive/ Recent
|  http://www.eda-stds.org/pub/ibis/email/         E-mail since 1993
- --------------080206060808090907030200-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Sep 2006 11:46:57 -0700 From: "Lynne D. Green" Subject: [IBIS-Users] RE: [IBIS] Open drain strange behaviour Hello, Roberto, One of the first questions to ask oneself is: how does the shape of the two waveforms differ? If your SI tool's waveform matches your SPICE waveform with a time offset, your are probably seeing an effect of how the buffer DATA (from chip core) is triggered. In SPICE, waveforms show Time from Time=0 (which is start of simulation). But any "step" input is actually a ramp between two simulation time steps. This ramp rate can vary between simulations, since the time step depends on the "stop time" and other .OPTIONS settings. In many SI simulators, the buffer's DATA "trigger" is a fixed ramp. The ramp slope and trigger level for the buffer DATA are different between simulators. The result is that simulators, from SPICE to SI tool1 to SI tool2, etc, will each produce a different Time offset, but the waveform shape should match (for the same R_fixture load). If your waveforms do not match, then you have a different problem. In that case, you might wish to submit your model to the IBIS Model Review Committee for feedback (http://www.eigroup.org/ibis/support.htm). Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com - -----Original Message----- From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Roberto IZZI Sent: Monday, September 11, 2006 5:17 AM To: ibis@eda-stds.org; ibis-users@eda.org Subject: [IBIS] Open drain strange behaviour Hello everybody I 'd like to have some information about a strange behaviour of Open drain buffer Ibis model. I have noticed a mismatch between Transistor level and Ibis model voltage output during a transient analysis. In fact in presence of the same input voltage wave and the same value of load resistance (for example 70 ohm), we can observe a delay between TL output and Ibis output. This delay is the same if we change the value of load resistance. What is the cause of this strange behaviour? Thanks and best regards Roberto Izzi - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Sep 2006 12:19:37 -0700 From: "Ray Anderson" Subject: [IBIS-Users] Question on IBIS Quality Spec Interpretation (section 4.4.2) This is a multi-part message in MIME format. - ------_=_NextPart_001_01C6D5D7.38E102DB Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable =20 One of our development groups is currently reviewing one of our new IBIS models for LEVEL 0 compliance prior to initial issue to customers. A question has come up regarding the interpretation of section 4.4.2 in the iq_specification.txt document (IBIS QUALITY SPECIFICATION - Revision 1.0). =20 =20 While the text of the document defines the intent very precisely, can someone please provide an interpretation of what really needs to be checked? =20 Initially the group thought it was as simple as verifying that the voltages at the endoints of the V-T table were within 2% of the endpoint voltages in the I-V tables, but after re-reading section 4.4.2 we are not convinced that is a correct interpretation. =20 =20 =20 4.4.2 {LEVEL 0} V-T table endpoints consistent with I-V tables =20 The voltage associated with the intersection of the V_fixture, R_fixture, and R_dut (if present) load line with the respective combined high/low DC I-V characteristic should be within 2% of the V-T table DC endpoints based on the V-T table DC range. =20 The combined High State DC I-V characteristic is defined as the sum of the [Power Clamp], [GND Clamp], and [Pullup] I-V tables (ground relative). Similarly, the combined Low State DC I-V characteristic is defined as the sum of the [Power Clamp], [GND clamp], and [Pulldown] I-V tables (ground relative). =20 =20 =20 - -Ray Anderson =20 Raymond Anderson Senior Signal Integrity Staff Engineer Product Technology Department Advanced Package R&D Xilinx Inc. =20 =20 - ------_=_NextPart_001_01C6D5D7.38E102DB Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

 

One of our development groups is currently reviewing = one of our new IBIS models for LEVEL 0 compliance prior to initial issue to = customers. A question has come up regarding the interpretation of section 4.4.2 in = the iq_specification.txt document (IBIS QUALITY SPECIFICATION - Revision = 1.0).

 

 

While the text of the document defines the intent = very precisely, can someone please provide an interpretation of what really = needs to be checked?

 

Initially the group thought it was as simple as = verifying that the voltages at the endoints of the V-T table were within 2% of the endpoint voltages in the I-V tables, but after re-reading section 4.4.2 = we are not convinced that is a correct = interpretation.

 

 

 

4.4.2  {LEVEL 0}  V-T table endpoints = consistent with I-V tables

 

  The voltage associated with the intersection = of the V_fixture, R_fixture,

  and R_dut (if present) load line with the = respective combined high/low

  DC I-V characteristic should be within 2% of = the V-T table DC endpoints

  based on the V-T table DC = range.

 

  The combined High State DC I-V characteristic = is defined as the sum

  of the [Power Clamp], [GND Clamp], and = [Pullup] I-V tables (ground

  relative). Similarly, the combined Low State = DC I-V characteristic is

  defined as the sum of the [Power Clamp], [GND = clamp], and [Pulldown]

  I-V tables (ground = relative).

 

 

 

-Ray Anderson

 

Raymond = Anderson

Senior Signal Integrity Staff Engineer

Product = Technology Department

Advanced = Package R&D

Xilinx = Inc.

 <= /p>

 

- ------_=_NextPart_001_01C6D5D7.38E102DB-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #85 ************************