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- ------_=_NextPart_001_01C71569.D5DA3542-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Dec 2006 09:27:52 +0800 From: "NG,MEI-YEE" Subject: [IBIS-Users] IBIS load This is a multi-part message in MIME format. - ------_=_NextPart_001_01C7180C.95C2F593 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi experts, =20 According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. =20 Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. =20 Thank you. =20 Best regards, =20 Mei Yee Ng IC Design Engineer=20 Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 =20 - ------_=_NextPart_001_01C7180C.95C2F593 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi experts,

According to the cookbook, when extracting V-T data, = it is recommended to use a load circuit of 1R + 1F into manufacturer’s suggested pullup resistor termination and voltage. However, when I use = the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns = to stabilize, but the falling waveform requires less than 10ns. This = creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). = In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within = 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model = and the simulation shows acceptable waveforms.

Kindly advice whether it is a MUST to have a 1.5K = pullup resistor V-T table.

Thank you.

Best regards,

= Mei Yee Ng

IC Design = Engineer

Illumination = and Color Management

Solid-state = Illumination Division

Avago = Technologies Malaysia

Tel no: = +604-6108515

- ------_=_NextPart_001_01C7180C.95C2F593-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Dec 2006 09:27:52 +0800 From: "NG,MEI-YEE" Subject: [IBIS-Users] IBIS load This is a multi-part message in MIME format. - ------_=_NextPart_001_01C7180C.95C2F593 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi experts, =20 According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. =20 Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. =20 Thank you. =20 Best regards, =20 Mei Yee Ng IC Design Engineer=20 Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 =20 - ------_=_NextPart_001_01C7180C.95C2F593 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi experts,

Kindly advice whether it is a MUST to have a 1.5K = pullup resistor V-T table.

Thank you.

Best regards,

= Mei Yee Ng

IC Design = Engineer

Illumination = and Color Management

Solid-state = Illumination Division

Avago = Technologies Malaysia

Tel no: = +604-6108515

- ------_=_NextPart_001_01C7180C.95C2F593-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 4 Dec 2006 19:38:09 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] IBIS load This is a multi-part message in MIME format. - ------=_NextPart_000_0154_01C717DB.C6F32A50 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I would say do the extraction with the 50 Ohm load and put the datasheet timing load into the model in the Rref, Cref, Vref section. =20 =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 5:28 PM To: ibis-users@server.eda.org; ibis-users@server.eda.org Subject: [IBIS-Users] IBIS load Hi experts, =20 According to the cookbook, when extracting V-T data, it is recommended = to use a load circuit of 1R + 1F into manufacturer's suggested pullup = resistor termination and voltage. However, when I use the suggested pullup = resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the = falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as = recommended by cookbook). The rising waveform for this is also within 10ns. I wonder = if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution = is more appropriate in this case? I have verified this model and the = simulation shows acceptable waveforms. =20 Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T = table. =20 Thank you. =20 Best regards, =20 Mei Yee Ng IC Design Engineer=20 Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 =20 - ------=_NextPart_000_0154_01C717DB.C6F32A50 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Message

I=20 would say do the extraction with the 50 Ohm load and put the datasheet = timing=20 load into the model in the Rref, Cref, Vref section.

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness = Lane
Beaverton, OR=20 97008
503-430-1065
tom@teraspeed.com
www.teraspeed.com

Te= raspeed=20 Consulting Group LLC
121 North River Drive
Narragansett, RI=20 02882
401-284-1827

-----Original Message-----
From:=20 owner-ibis-users@server.eda.org = [mailto:owner-ibis-users@server.eda.org] On=20 Behalf Of NG,MEI-YEE
Sent: Monday, December 04, 2006 = 5:28=20 PM
To: ibis-users@server.eda.org;=20 ibis-users@server.eda.org
Subject: [IBIS-Users] IBIS=20 load

Hi=20 experts,

According to the = cookbook, when=20 extracting V-T data, it is recommended to use a load circuit of 1R + = 1F into=20 manufacturer’s suggested pullup resistor termination and = voltage. However,=20 when I use the suggested pullup resistor (1.5K), the rising waveform = takes up=20 to 100ns to stabilize, but the falling waveform requires less than = 10ns. This=20 creates inaccuracy due to the resolution of the points (when I use = 100ns=20 simulation time). In the IBIS model, I also included a waveform for = 50Ohm=20 pullup resistor (as recommended by cookbook). The rising waveform for = this is=20 also within 10ns. I wonder if I can generate IBIS model with ONLY 50 = Ohm=20 pullup because the resolution is more appropriate in this case? I have = verified this model and the simulation shows acceptable=20 waveforms.

Kindly advice whether it = is a MUST=20 to have a 1.5K pullup resistor V-T table.

Thank=20 you.

Best=20 regards,

Mei=20 Yee Ng

IC = Design Engineer=20

Illumination and=20 Color Management

Solid-state=20 Illumination Division

Avago = Technologies=20 Malaysia

Tel no:=20 +604-6108515

- ------=_NextPart_000_0154_01C717DB.C6F32A50-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 4 Dec 2006 19:55:34 -0800 From: "Lynne D. Green" Subject: RE: [IBIS-Users] IBIS load Hello, Mei-Yee, The 1.5K resistor is needed for bias control for an open-source/open-sink buffer. In addition to that resistor, one needs a V-t load (the 50 ohms you refer to). The 50 ohm load is described in the IBIS Cookbook, http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf. This means your simulation will have both resistors: the 1.5K and the 50 ohms. Once you have completed your model, please feel welcome to submit your model to the IBIS Model Review Committee, http://www.eigroup.org/ibis/support.htm. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 5:28 PM To: ibis-users@eda.org; ibis-users@eda.org Subject: [IBIS-Users] IBIS load Hi experts, According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. Thank you. Best regards, Mei Yee Ng IC Design Engineer Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Dec 2006 12:08:04 +0800 From: "NG,MEI-YEE" Subject: RE: [IBIS-Users] IBIS load This is a multi-part message in MIME format. - ------_=_NextPart_001_01C71822.F6795553 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable OK, but according to the cookbook, we need to append 1R+1F waveforms for suggested pullup resistor, which in my case is 1.5K Ohm. Is it ok if I just put 1.5K ohm as Rref instead? =20 Best regards, Mei Yee SID, Avago Technologies (Malaysia) Tel no.:604-6108515 ________________________________ From: Tom Dagostino [mailto:tom@teraspeed.com]=20 Sent: Tuesday, December 05, 2006 11:38 AM To: NG,MEI-YEE; ibis-users@server.eda.org; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load =20 I would say do the extraction with the 50 Ohm load and put the datasheet timing load into the model in the Rref, Cref, Vref section. =20 =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 5:28 PM To: ibis-users@server.eda.org; ibis-users@server.eda.org Subject: [IBIS-Users] IBIS load Hi experts, =20 According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. =20 Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. =20 Thank you. =20 Best regards, =20 Mei Yee Ng IC Design Engineer=20 Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 =20 - ------_=_NextPart_001_01C71822.F6795553 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Message

OK, but according to the cookbook, = we need to append 1R+1F waveforms for suggested pullup resistor, which in my = case is 1.5K Ohm. Is it ok if I just put 1.5K ohm as Rref = instead?

Best = regards,

Mei = Yee

SID, Avago Technologies = (Malaysia)

Tel = no.:604-6108515

From: Tom = Dagostino [mailto:tom@teraspeed.com] =
Sent: Tuesday, December = 05, 2006 11:38 AM
To: NG,MEI-YEE; ibis-users@server.eda.org; ibis-users@server.eda.org
Subject: RE: [IBIS-Users] = IBIS load

I would say do the extraction with = the 50 Ohm load and put the datasheet timing load into the model in the Rref, = Cref, Vref section.

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness = Lane
Beaverton, = OR 97008
503-430-1065
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River = Drive
Narragansett, = RI 02882
401-284-1827

-----Original = Message-----
From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] = On Behalf Of NG,MEI-YEE
Sent: Monday, December = 04, 2006 5:28 PM
To: = ibis-users@server.eda.org; ibis-users@server.eda.org
Subject: [IBIS-Users] = IBIS load

Hi experts,

According to the cookbook, when extracting V-T data, = it is recommended to use a load circuit of 1R + 1F into manufacturer’s suggested pullup resistor termination and voltage. However, when I use = the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns = to stabilize, but the falling waveform requires less than 10ns. This = creates inaccuracy due to the resolution of the points (when I use 100ns = simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup = resistor (as recommended by cookbook). The rising waveform for this is also = within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because = the resolution is more appropriate in this case? I have verified this model = and the simulation shows acceptable waveforms.

Kindly advice whether it is a MUST to have a 1.5K = pullup resistor V-T table.

Thank you.

Best regards,

= Mei Yee Ng

IC Design = Engineer

Illumination = and Color Management

Solid-state = Illumination Division

Avago = Technologies Malaysia

Tel no: = +604-6108515

- ------_=_NextPart_001_01C71822.F6795553-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Dec 2006 12:13:03 +0800 From: "NG,MEI-YEE" Subject: RE: [IBIS-Users] IBIS load Hi Lynne, Thanks for the reply. As mentioned in my earlier mail, if I use the 1.5K resistor to simulate, it will use up to 100ns to stabilize. This will affect my resolution especially for fall time, since each step is only 1ns and my fall time is less than 10ns. Is it ok to just have 50 Ohm V-T table (which has rise time <10ns), since this will provide a good resolution for both the rise and fall time? Best regards, Mei Yee SID, Avago Technologies (Malaysia) Tel no.:604-6108515 - -----Original Message----- From: Lynne D. Green [mailto:lgreen22@mindspring.com] Sent: Tuesday, December 05, 2006 11:56 AM To: NG,MEI-YEE; ibis-users@eda.org Subject: RE: [IBIS-Users] IBIS load Hello, Mei-Yee, The 1.5K resistor is needed for bias control for an open-source/open-sink buffer. In addition to that resistor, one needs a V-t load (the 50 ohms you refer to). The 50 ohm load is described in the IBIS Cookbook, http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf. This means your simulation will have both resistors: the 1.5K and the 50 ohms. Once you have completed your model, please feel welcome to submit your model to the IBIS Model Review Committee, http://www.eigroup.org/ibis/support.htm. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 5:28 PM To: ibis-users@eda.org; ibis-users@eda.org Subject: [IBIS-Users] IBIS load Hi experts, According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. Thank you. Best regards, Mei Yee Ng IC Design Engineer Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 4 Dec 2006 20:16:51 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] IBIS load Lynne The 50 Ohm pullup does the trick for "biasing control" of the buffer. There is no need for the 1.5K. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Lynne D. Green Sent: Monday, December 04, 2006 7:56 PM To: 'NG,MEI-YEE'; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Hello, Mei-Yee, The 1.5K resistor is needed for bias control for an open-source/open-sink buffer. In addition to that resistor, one needs a V-t load (the 50 ohms you refer to). The 50 ohm load is described in the IBIS Cookbook, http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf. This means your simulation will have both resistors: the 1.5K and the 50 ohms. Once you have completed your model, please feel welcome to submit your model to the IBIS Model Review Committee, http://www.eigroup.org/ibis/support.htm. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 5:28 PM To: ibis-users@eda.org; ibis-users@eda.org Subject: [IBIS-Users] IBIS load Hi experts, According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. Thank you. Best regards, Mei Yee Ng IC Design Engineer Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Dec 2006 13:54:49 +0800 From: "NG,MEI-YEE" Subject: RE: [IBIS-Users] IBIS load Hi Tom, Thanks for clarifying this. One more question, what is the difference between the manufacturer's suggested pullup load resistor used in V-T values extraction and the Rref value specified? In my case, the suggested pullup is 1.5KOhm, so I only need a 50 Ohm V-T table and my Rref = 1.5Kohm? Thank you very much. Best regards, Mei Yee SID, Avago Technologies (Malaysia) Tel no.:604-6108515 - -----Original Message----- From: Tom Dagostino [mailto:tom@teraspeed.com] Sent: Tuesday, December 05, 2006 12:17 PM To: 'Lynne D. Green'; NG,MEI-YEE; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Lynne The 50 Ohm pullup does the trick for "biasing control" of the buffer. There is no need for the 1.5K. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Lynne D. Green Sent: Monday, December 04, 2006 7:56 PM To: 'NG,MEI-YEE'; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Hello, Mei-Yee, The 1.5K resistor is needed for bias control for an open-source/open-sink buffer. In addition to that resistor, one needs a V-t load (the 50 ohms you refer to). The 50 ohm load is described in the IBIS Cookbook, http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf. This means your simulation will have both resistors: the 1.5K and the 50 ohms. Once you have completed your model, please feel welcome to submit your model to the IBIS Model Review Committee, http://www.eigroup.org/ibis/support.htm. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 5:28 PM To: ibis-users@eda.org; ibis-users@eda.org Subject: [IBIS-Users] IBIS load Hi experts, According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. Thank you. Best regards, Mei Yee Ng IC Design Engineer Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Dec 2006 00:12:09 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] IBIS load The load that is seen by a driver is first of all the trace on the circuit board. Usually trace impedance is in the 40 to 65 Ohm range. Thus the IBIS model should characterize the buffer driving the load that is expected to be seen by the driver. In your case the waveforms are relatively slow, even when the buffer is terminated in 50 Ohms. I assume your 10 nsec rise and fall times were measured without any capacitance at the load. If you simulated with a C load then you will likely have simulations issues in actual circuits. If the buffer is really 10 nsec, then you will start seeing SI issues only after about 2 nsec trace lengths or about 12 inches on the board. The only parts we see these days with such slow edge speeds are RS232 typ drivers. In this case the manufacturer has characterized the prop delay of the buffer when it is driving a 1.5K load terminated to Vdd. The timing is measured at Vmeas. If there was any C associated with the timing test load it would be included along with the timing test resistor. Also, in a real application of this buffer with a 1.5K pullup there will be relatively low currents flowing and slow edges at the load but the transition at the output of the buffer will be faster. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 9:55 PM To: tom@teraspeed.com; Lynne D. Green; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Hi Tom, Thanks for clarifying this. One more question, what is the difference between the manufacturer's suggested pullup load resistor used in V-T values extraction and the Rref value specified? In my case, the suggested pullup is 1.5KOhm, so I only need a 50 Ohm V-T table and my Rref = 1.5Kohm? Thank you very much. Best regards, Mei Yee SID, Avago Technologies (Malaysia) Tel no.:604-6108515 - -----Original Message----- From: Tom Dagostino [mailto:tom@teraspeed.com] Sent: Tuesday, December 05, 2006 12:17 PM To: 'Lynne D. Green'; NG,MEI-YEE; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Lynne The 50 Ohm pullup does the trick for "biasing control" of the buffer. There is no need for the 1.5K. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Lynne D. Green Sent: Monday, December 04, 2006 7:56 PM To: 'NG,MEI-YEE'; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Hello, Mei-Yee, The 1.5K resistor is needed for bias control for an open-source/open-sink buffer. In addition to that resistor, one needs a V-t load (the 50 ohms you refer to). The 50 ohm load is described in the IBIS Cookbook, http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf. This means your simulation will have both resistors: the 1.5K and the 50 ohms. Once you have completed your model, please feel welcome to submit your model to the IBIS Model Review Committee, http://www.eigroup.org/ibis/support.htm. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 5:28 PM To: ibis-users@eda.org; ibis-users@eda.org Subject: [IBIS-Users] IBIS load Hi experts, According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. Thank you. Best regards, Mei Yee Ng IC Design Engineer Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 6 Dec 2006 07:46:57 +0800 From: "NG,MEI-YEE" Subject: RE: [IBIS-Users] IBIS load Hi all, Thank you for clarifying the difference between the R_fixture and the Rref for my buffer. I have 2 more questions regarding an open drain buffer: *According to cookbook pg 19, for open drain buffer, the recommended load circuit is 1R+1F into manufacturer's suggested pullup resistor termination and voltage. 1) Therefore, when I generate the VT tables for Rise and Fall, my resistor is always tied to the termination voltage (eg. VDD)? Does this imply that I am simulating for the case where PCB traces (load) are always tied to high? 2) The buffer is supposed to work with pullup voltage of VDD AND 1.8V. Does this mean my VT tables will have termination voltages of VDD and 1.8V? Thank you very much for the useful feedback. Best regards, Mei Yee SID, Avago Technologies (Malaysia) Tel no.:604-6108515 - -----Original Message----- From: Tom Dagostino [mailto:tom@teraspeed.com] Sent: Tuesday, December 05, 2006 4:12 PM To: NG,MEI-YEE; 'Lynne D. Green'; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load The load that is seen by a driver is first of all the trace on the circuit board. Usually trace impedance is in the 40 to 65 Ohm range. Thus the IBIS model should characterize the buffer driving the load that is expected to be seen by the driver. In your case the waveforms are relatively slow, even when the buffer is terminated in 50 Ohms. I assume your 10 nsec rise and fall times were measured without any capacitance at the load. If you simulated with a C load then you will likely have simulations issues in actual circuits. If the buffer is really 10 nsec, then you will start seeing SI issues only after about 2 nsec trace lengths or about 12 inches on the board. The only parts we see these days with such slow edge speeds are RS232 typ drivers. In this case the manufacturer has characterized the prop delay of the buffer when it is driving a 1.5K load terminated to Vdd. The timing is measured at Vmeas. If there was any C associated with the timing test load it would be included along with the timing test resistor. Also, in a real application of this buffer with a 1.5K pullup there will be relatively low currents flowing and slow edges at the load but the transition at the output of the buffer will be faster. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 9:55 PM To: tom@teraspeed.com; Lynne D. Green; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Hi Tom, Thanks for clarifying this. One more question, what is the difference between the manufacturer's suggested pullup load resistor used in V-T values extraction and the Rref value specified? In my case, the suggested pullup is 1.5KOhm, so I only need a 50 Ohm V-T table and my Rref = 1.5Kohm? Thank you very much. Best regards, Mei Yee SID, Avago Technologies (Malaysia) Tel no.:604-6108515 - -----Original Message----- From: Tom Dagostino [mailto:tom@teraspeed.com] Sent: Tuesday, December 05, 2006 12:17 PM To: 'Lynne D. Green'; NG,MEI-YEE; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Lynne The 50 Ohm pullup does the trick for "biasing control" of the buffer. There is no need for the 1.5K. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Lynne D. Green Sent: Monday, December 04, 2006 7:56 PM To: 'NG,MEI-YEE'; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Hello, Mei-Yee, The 1.5K resistor is needed for bias control for an open-source/open-sink buffer. In addition to that resistor, one needs a V-t load (the 50 ohms you refer to). The 50 ohm load is described in the IBIS Cookbook, http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf. This means your simulation will have both resistors: the 1.5K and the 50 ohms. Once you have completed your model, please feel welcome to submit your model to the IBIS Model Review Committee, http://www.eigroup.org/ibis/support.htm. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 5:28 PM To: ibis-users@eda.org; ibis-users@eda.org Subject: [IBIS-Users] IBIS load Hi experts, According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. Thank you. Best regards, Mei Yee Ng IC Design Engineer Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 5 Dec 2006 15:59:48 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] IBIS load 1. In an open drain buffer if you were to tie your "pullup" resistor to ground how much of a transition would you get? Ohms law states that the current through a resistor is proportional to the voltage across it. So, a open drain buffer who's source is tied to ground has a resistor on its drain tied to ground will in the off state have zero current and in the on state will have zero current. 2. Since the voltage swing is going to be different with different termination voltages then it would be wise to model your output at the various voltages it may operate at. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: NG,MEI-YEE [mailto:mei-yee.ng@avagotech.com] Sent: Tuesday, December 05, 2006 3:47 PM To: tom@teraspeed.com; Lynne D. Green; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Hi all, Thank you for clarifying the difference between the R_fixture and the Rref for my buffer. I have 2 more questions regarding an open drain buffer: *According to cookbook pg 19, for open drain buffer, the recommended load circuit is 1R+1F into manufacturer's suggested pullup resistor termination and voltage. 1) Therefore, when I generate the VT tables for Rise and Fall, my resistor is always tied to the termination voltage (eg. VDD)? Does this imply that I am simulating for the case where PCB traces (load) are always tied to high? 2) The buffer is supposed to work with pullup voltage of VDD AND 1.8V. Does this mean my VT tables will have termination voltages of VDD and 1.8V? Thank you very much for the useful feedback. Best regards, Mei Yee SID, Avago Technologies (Malaysia) Tel no.:604-6108515 - -----Original Message----- From: Tom Dagostino [mailto:tom@teraspeed.com] Sent: Tuesday, December 05, 2006 4:12 PM To: NG,MEI-YEE; 'Lynne D. Green'; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load The load that is seen by a driver is first of all the trace on the circuit board. Usually trace impedance is in the 40 to 65 Ohm range. Thus the IBIS model should characterize the buffer driving the load that is expected to be seen by the driver. In your case the waveforms are relatively slow, even when the buffer is terminated in 50 Ohms. I assume your 10 nsec rise and fall times were measured without any capacitance at the load. If you simulated with a C load then you will likely have simulations issues in actual circuits. If the buffer is really 10 nsec, then you will start seeing SI issues only after about 2 nsec trace lengths or about 12 inches on the board. The only parts we see these days with such slow edge speeds are RS232 typ drivers. In this case the manufacturer has characterized the prop delay of the buffer when it is driving a 1.5K load terminated to Vdd. The timing is measured at Vmeas. If there was any C associated with the timing test load it would be included along with the timing test resistor. Also, in a real application of this buffer with a 1.5K pullup there will be relatively low currents flowing and slow edges at the load but the transition at the output of the buffer will be faster. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 9:55 PM To: tom@teraspeed.com; Lynne D. Green; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Hi Tom, Thanks for clarifying this. One more question, what is the difference between the manufacturer's suggested pullup load resistor used in V-T values extraction and the Rref value specified? In my case, the suggested pullup is 1.5KOhm, so I only need a 50 Ohm V-T table and my Rref = 1.5Kohm? Thank you very much. Best regards, Mei Yee SID, Avago Technologies (Malaysia) Tel no.:604-6108515 - -----Original Message----- From: Tom Dagostino [mailto:tom@teraspeed.com] Sent: Tuesday, December 05, 2006 12:17 PM To: 'Lynne D. Green'; NG,MEI-YEE; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Lynne The 50 Ohm pullup does the trick for "biasing control" of the buffer. There is no need for the 1.5K. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Lynne D. Green Sent: Monday, December 04, 2006 7:56 PM To: 'NG,MEI-YEE'; ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS load Hello, Mei-Yee, The 1.5K resistor is needed for bias control for an open-source/open-sink buffer. In addition to that resistor, one needs a V-t load (the 50 ohms you refer to). The 50 ohm load is described in the IBIS Cookbook, http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf. This means your simulation will have both resistors: the 1.5K and the 50 ohms. Once you have completed your model, please feel welcome to submit your model to the IBIS Model Review Committee, http://www.eigroup.org/ibis/support.htm. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of NG,MEI-YEE Sent: Monday, December 04, 2006 5:28 PM To: ibis-users@eda.org; ibis-users@eda.org Subject: [IBIS-Users] IBIS load Hi experts, According to the cookbook, when extracting V-T data, it is recommended to use a load circuit of 1R + 1F into manufacturer's suggested pullup resistor termination and voltage. However, when I use the suggested pullup resistor (1.5K), the rising waveform takes up to 100ns to stabilize, but the falling waveform requires less than 10ns. This creates inaccuracy due to the resolution of the points (when I use 100ns simulation time). In the IBIS model, I also included a waveform for 50Ohm pullup resistor (as recommended by cookbook). The rising waveform for this is also within 10ns. I wonder if I can generate IBIS model with ONLY 50 Ohm pullup because the resolution is more appropriate in this case? I have verified this model and the simulation shows acceptable waveforms. Kindly advice whether it is a MUST to have a 1.5K pullup resistor V-T table. Thank you. Best regards, Mei Yee Ng IC Design Engineer Illumination and Color Management Solid-state Illumination Division Avago Technologies Malaysia Tel no: +604-6108515 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 15 Dec 2006 11:43:41 -0800 From: "Syed Huq \(shuq\)" Subject: [IBIS-Users] DesignCon 2007: Second call for papers This is a multi-part message in MIME format. - ------_=_NextPart_001_01C72081.52F93559 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable =20 To All: =20 This is the Second Announcement for the DesignCon 2007 IBIS Summit Meeting held in Santa Clara, California. =20 We are seeking Sponsors for the IBIS meeting to cover the expenses for a Free lunch and refreshments. =20 Also note that discounts are offered for all conference packages through December 15, 2006, and also January 26, 2007 for free exhibit registration. =20 Best Regards, Syed =20 - ----------------------------------------------------------------------- IBIS SUMMIT SECOND CALL FOR PARTICIPATION & PRESENTATIONS - ----------------------------------------------------------------------- =20 I B I S S U M M I T M E E T I N G =20 Time/Date: Thursday, February 1, 2007 8:00 AM to 5:00 PM =20 Location: Hyatt Regency Santa Clara (Connected to the Santa Clara Convention Center) 5101 Great America Parkway,=20 Santa Clara, California, USA Tel: +1-408-200-1234=20 =20 Content: Presentations and Discussions =20 Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. =20 Sponsors: Cisco Systems, International Engineering Consortium (DesignCon) =20 We are seeking more co-sponsors. Please contact Syed Huq . The Benefits to sponsors include recognition at the meeting and acknowledgement in the Calls for Papers and meeting minutes. =20 Your financial support strengthens the organization by allowing IBIS to focus resources on industry activities rather than raising money, and you will receive generous thanks for your support. =20 DesignCon 2007 Conference: =20 January 19 - February 1, 2007 Santa Clara Convention Center Santa Clara, CA =20 Exhibit registration is Free if you register before January 26, 2007, and conference fees are discounted if you register before December 15, 2006. =20 http://www.designcon.com/2007/ http://www.designcon.com/2007/registration/ =20 Conference Schedule: =20 http://www.designcon.com/2007/conference/schedule.html =20 IBIS Booth: Come visit the IBIS Booth to meet attendees and pick up IBIS information. =20 BACKGROUND =20 DesignCon is the premier annual Silicon Valley event for the electronic design automation (EDA) and semiconductor industry. Topics of current interest to the EIA IBIS Open Forum are addressed at DesignCon. =20 This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. Any pending formal decisions (votes) will be announced at least two weeks prior to the meeting. =20 CALL FOR PARTICIPANTS =20 People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: =20 Name: E-mail address: Company: Telephone: =20 Send to: =20 Syed Huq =20 Registration deadline is Wednesday, January 24, 2007 to receive the free lunch. =20 =20 CALL FOR PRESENTATIONS =20 We are seeking presentations from individuals who have experiences of interest to the IBIS modeling community. In the past, these have included, but not limited to: =20 Demonstrations of modeling techniques=20 Explanations of behavioral algorithms Descriptions of difficulties encountered Model correlation Modeling building experiences Comparisons to other modeling methods New technologies for modeling buffers and component New technologies for modeling packaging and interconnect Etc. =20 Presentations may be addressed to any and all levels of IBIS experience, from beginning to advanced. =20 Presentation Format: =20 A conference laptop with LCD projection. Power Point or Acrobat electronic formats are favored and will pre-loaded on the Windows-based meeting laptop prior to the meeting. =20 Time: Usually 15-30 Minutes =20 Electronic Archival: =20 Presentations will be archived under the IBIS Summits site and also must be submitted in time for uploading and copying. Final submission deadline is: =20 Wednesday, January 24, 2007 =20 Otherwise, you should bring 50 copies. =20 If you plan a presentation, please supply the following information as soon as possible: =20 Tentative Title: Presenter: E-mail address: Company: Telephone: =20 Estimated Time: =20 Send to: =20 Bob Ross =20 AGENDA =20 The agenda includes presentations, discussions, breaks, and a FREE lunch. The agenda details will be developed as proposals are received. =20 LIST OF NEARBY HOTELS =20 The Hotel and Travel Link provides a conference hotel discount, and use internet search engines other good lodging deals: =20 http://www.designcon.com/2007/conference/hotel_and_travel.html =20 - ----------------------------------------------------------------- =20 =20 =20 =20 =20 - ------_=_NextPart_001_01C72081.52F93559 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

To All:

This is the Second Announcement for the = DesignCon=20 2007 IBIS Summit
Meeting held in Santa Clara, = California.

We are seeking Sponsors for the IBIS = meeting to=20 cover the expenses
for a Free lunch and refreshments.

Also note that discounts are offered = for all=20 conference packages
through December 15, 2006, and also January 26, = 2007 for=20 free
exhibit registration.

Best Regards,
Syed

----------------------------------------------------------------= - -------
          &n= bsp;           &nb= sp;      =20 IBIS=20 SUMMIT
          &nb= sp;           &nbs= p;       SECOND CALL=20 FOR
           =          =20 PARTICIPATION &=20 PRESENTATIONS
--------------------------------------------------------= - ---------------

&nbs= p; =20 I B I S S U M M I T M E E T I N G

Time/Date: Thursday, February 1, 2007 8:00 AM to 5:00 = PM

Location:   Hyatt Regency Santa=20 Clara
          &nbs= p;  =20 (Connected to the Santa Clara Convention=20 Center)
          &n= bsp;=20 5101 Great America Parkway,=20
            = Santa=20 Clara, California,=20 USA
           = Tel:=20 +1-408-200-1234

Content: Presentations and Discussions

Purpose: Solicit and Exchange IBIS Model Related=20 Information=20 and
= =20 Ideas.

Sponsors: Cisco Systems, International Engineering = Consortium=20 (DesignCon)

            = We are=20 seeking more co-sponsors. Please contact Syed=20 Huq
           = <shuq@cisco.com>. The = Benefits to=20 sponsors=20 include
          &n= bsp;=20 recognition at the meeting and acknowledgement in the=20 Calls
          &nbs= p; for=20 Papers and meeting minutes.

            = Your=20 financial support strengthens the organization=20 by
            = allowing IBIS to focus resources on industry=20 activities
          = ; =20 rather than raising money, and you will receive=20 generous
          &= nbsp;=20 thanks for your support.

DesignCon 2007 Conference:

            = January=20 19 - February 1,=20 2007
           = ; Santa=20 Clara Convention=20 Center
          &nb= sp;=20 Santa Clara, CA

            = Exhibit=20 registration is Free if you register=20 before
          &nb= sp;=20 January 26, 2007, and conference fees are=20 discounted
          = ; =20 if you register before December 15,=20 2006.
          &nbs= p;=20
           &nb= sp; =20 http://www.designcon.com/2007/
           &n= bsp; =20 http://www.designcon= .com/2007/registration/
    =20
     Conference Schedule:

http://ww= w.designcon.com/2007/conference/schedule.html

IBIS Booth: Come visit the IBIS Booth to meet attendees and pick=20 up
= IBIS=20 information.

BACKGROUND

DesignCon is the premier annual Silicon Valley event for the=20 electronic
design automation (EDA) and semiconductor industry. = Topics=20 of current
interest to the EIA IBIS Open Forum are addressed at=20 DesignCon.

This meeting will be conducted as a formal IBIS Summit=20 Meeting.
Presentations are expected to be available and archived in = an=20 electronic
format, and minutes of the meeting will be issued. Any = pending=20 formal
decisions (votes) will be announced at least two weeks prior = to=20 the
meeting.

CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development,=20 and
digital circuit design are invited to participate in the Summit=20 meeting.
If you plan to participate, please register with the = information=20 below:

   Name:
   E-mail address:
  =20 Company:
   Telephone:

Send to:

Syed Huq <shuq@cisco.com>

Registration deadline is Wednesday, January 24, 2007 to receive = the
free=20 lunch.

CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have = experiences
of=20 interest to the IBIS modeling community. In the past, these=20 have
included, but not limited to:

   Demonstrations of modeling techniques
   = Explanations of behavioral algorithms
   Descriptions of=20 difficulties encountered
   Model = correlation
  =20 Modeling building experiences
   Comparisons to other = modeling=20 methods
   New technologies for modeling buffers and=20 component
   New technologies for modeling packaging and=20 interconnect
   Etc.

Presentations may be addressed to any and all levels of IBIS=20 experience,
from beginning to advanced.

Presentation Format:

   A conference laptop = with=20 LCD projection. Power Point or Acrobat
   electronic = formats=20 are favored and will pre-loaded on the
   Windows-based = meeting=20 laptop prior to the meeting.

Time: Usually 15-30 Minutes

Electronic Archival:

   Presentations will be archived under the IBIS Summits=20 site
   and also must be submitted in time for uploading = and=20 copying.
   Final submission deadline is:
=20
     Wednesday, January 24, 2007

Otherwise, you should bring 50 copies.

If you plan a presentation, please supply the following = information
as=20 soon as possible:

   Tentative Title:
   = Presenter:
  =20 E-mail address:
   Company:
   = Telephone:

Estimated Time:

Send to:

Bob Ross <bob@teraspeed.com>

AGENDA

The agenda includes presentations, discussions, breaks, and a=20 FREE
lunch. The agenda details will be developed as proposals=20 are
received.

LIST OF NEARBY HOTELS

The Hotel and Travel Link provides a conference hotel discount, = and
use=20 internet search engines other good lodging deals:

h= ttp://www.designcon.com/2007/conference/hotel_and_travel.html

-----------------------------------------------------------------

- ------_=_NextPart_001_01C72081.52F93559-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 20 Dec 2006 10:39:23 -0700 From: April.Hachenburg@smsc.com Subject: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref missing ... This is a multipart message in MIME format. - --=_alternative 0060FDEE0725724A_= Content-Type: text/plain; charset="US-ASCII" IBIS Users, I wondered if anyone could clarify for me the usage of Rload vs. Rref vs. Rfixture and similarly Cref vs. Cfixture. I am using s2ibis3 and discovered that the Cref parameter specified in my .s2i file does not appear in my .ibs model file. After looking at the netlists and reading the IBIS documentation, it appears Cref is not used for any simulations. What is the purpose of Cref? And why isn't it showing up in the .ibs file? Also, I read that C_comp is taken into account for the rising/falling V-T waveforms though I cannot find that paramater in any of the corresponding netlists. How is C_comp used? As for Rref vs. Rfixture, I thought I read somewhere that for best results Rref should match Rfixture. Is that true? In my model, I am using the keywords Rising/Falling Waveform. I found that if I do not specify Rload even though I am not specifying the [Ramp] keyword, then 50ohms is used in one of the transient simulations despite Rref and Rfixture being set to 500 ohms. Should I be specifying the [Ramp] keyword along with the [Rising/Falling Waveform] keywords? If so, how do they work together? - - April - --------------------------------------------------- April Hachenburg Core Technology Design Engineer SMSC - --=_alternative 0060FDEE0725724A_= Content-Type: text/html; charset="US-ASCII"
IBIS Users,
I wondered if anyone could clarify for me the usage of Rload vs. Rref vs. Rfixture and similarly Cref vs. Cfixture.

I am using s2ibis3 and discovered that the Cref parameter specified in my .s2i file does not appear in my .ibs model file. After looking at the netlists and reading the IBIS documentation, it appears Cref is not used for any simulations. What is the purpose of Cref? And why isn't it showing up in the .ibs file?

Also, I read that C_comp is taken into account for the rising/falling V-T waveforms though I cannot find that paramater in any of the corresponding netlists. How is C_comp used?

As for Rref vs. Rfixture, I thought I read somewhere that for best results Rref should match Rfixture. Is that true? In my model, I am using the keywords Rising/Falling Waveform. I found that if I do not specify Rload even though I am not specifying the [Ramp] keyword, then 50ohms is used in one of the transient simulations despite Rref and Rfixture being set to 500 ohms. Should I be specifying the [Ramp] keyword along with the [Rising/Falling Waveform] keywords? If so, how do they work together?

- April

- ---------------------------------------------------
April Hachenburg
Core Technology Design Engineer
SMSC
- --=_alternative 0060FDEE0725724A_=-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 20 Dec 2006 12:14:23 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref missing ... This is a multi-part message in MIME format. - ------=_NextPart_000_005F_01C72430.62F17550 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable April =20 R_load is the load the buffer is placed under when the ramp data is acquired. 50 Ohms is the typical value and it is usually terminated to ground for the dV/dT rise and to power for the dV/dT fall. =20 =20 R_fixture is the load the buffer is placed under when the VT waveforms = as acquired. This value is typically 50 Ohms and is terminated to ground = for both a rising and falling waveform and then terminated to power for the other set of rising and falling waveforms. C_fixture would be any capacitance associated with the R_fixture. But its not a good idea to = have any C_fixture when extracting VT waveforms. I've seen simulator give = very wrong answers when C_fixture is present. =20 Rref is the manufacturer's timing test load's resistive component. This = can be any value (within reason) and can be terminated to any reasonable = voltage Vref the manufacturer deems appropriate for the buffer technology. It = is usually terminated to the typical value the buffer would see in an = actual application. If the buffer was an ECL output then 50 Ohms to Vcc-2Volts would be the load. Most CMOS devices have just a Cref, a capacitor terminated to ground. =20 C_comp is the capacitance associated with the I/O buffer. It includes = all the capacitance from metal, active or passive devices on the silicon. = It forms the majority of the buffer's impedance reactive component. =20 R_fixture should match the load the buffer is seeing in an actual application. Most circuit boards trace impedance runs between 40 and 70 Ohms or there about. Most buffers are characterized into a 50 Ohm load which is close to the board impedance. Since the model developer cannot predict every application 50 Ohms is a good compromise for most models. There are some technologies that are better served with a non 50 Ohm = load such as RAMBUS, which is specified into 27 Ohms or very weak CMOS = drivers that cannot drive a 50 Ohm load to Vinl or Vinh. I'd caution against = using a 500 Ohm load in your model making unless there is a very good reason = to do so. =20 =20 The Ramp key word is a legacy key word that was used before the VT = waveforms were added to IBIS. It is still required to be present in the model. If R_fixture is not specified it defaults to 50 Ohm in the model. =20 =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of April.Hachenburg@smsc.com Sent: Wednesday, December 20, 2006 9:39 AM To: ibis-users@server.eda.org Cc: akvarma@ncsu.edu Subject: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref missing = ... IBIS Users,=20 I wondered if anyone could clarify for me the usage of Rload vs. Rref = vs. Rfixture and similarly Cref vs. Cfixture.=20 I am using s2ibis3 and discovered that the Cref parameter specified in = my .s2i file does not appear in my .ibs model file. After looking at the netlists and reading the IBIS documentation, it appears Cref is not used = for any simulations. What is the purpose of Cref? And why isn't it showing = up in the .ibs file?=20 Also, I read that C_comp is taken into account for the rising/falling = V-T waveforms though I cannot find that paramater in any of the = corresponding netlists. How is C_comp used?=20 As for Rref vs. Rfixture, I thought I read somewhere that for best = results Rref should match Rfixture. Is that true? In my model, I am using the keywords Rising/Falling Waveform. I found that if I do not specify = Rload even though I am not specifying the [Ramp] keyword, then 50ohms is used = in one of the transient simulations despite Rref and Rfixture being set to = 500 ohms. Should I be specifying the [Ramp] keyword along with the [Rising/Falling Waveform] keywords? If so, how do they work together?=20 - - April - --------------------------------------------------- April Hachenburg Core Technology Design Engineer SMSC=20 - ------=_NextPart_000_005F_01C72430.62F17550 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Message

April

R_load=20 is the load the buffer is placed under when the ramp data is = acquired. 50=20 Ohms is the typical value and it is usually terminated to ground for the = dV/dT=20 rise and to power for the dV/dT fall.

R_fixture is the load the buffer is placed under when the VT = waveforms as=20 acquired. This value is typically 50 Ohms and is terminated to = ground for=20 both a rising and falling waveform and then terminated to power for the = other=20 set of rising and falling waveforms. C_fixture would be any = capacitance=20 associated with the R_fixture. But its not a good idea to have any = C_fixture when extracting VT waveforms. I've seen simulator give = very=20 wrong answers when C_fixture is present.

Rref=20 is the manufacturer's timing test load's resistive component. This = can be=20 any value (within reason) and can be terminated to any reasonable = voltage=20 Vref the manufacturer deems appropriate for the buffer = technology. It=20 is usually terminated to the typical value the buffer would see in an = actual=20 application. If the buffer was an ECL output then 50 Ohms to = Vcc-2Volts=20 would be the load. Most CMOS devices have just a Cref, a capacitor = terminated to ground.

C_comp=20 is the capacitance associated with the I/O buffer. It includes all the=20 capacitance from metal, active or passive devices on the silicon. = It forms=20 the majority of the buffer's impedance reactive = component.

R_fixture should match the load the buffer is seeing in an = actual=20 application. Most circuit boards trace impedance runs between 40 = and 70=20 Ohms or there about. Most buffers are characterized into a 50 Ohm = load=20 which is close to the board impedance. Since the model developer = cannot=20 predict every application 50 Ohms is a good compromise for most = models. =20 There are some technologies that are better served with a non 50 Ohm = load such=20 as RAMBUS, which is specified into 27 Ohms or very weak CMOS drivers = that cannot=20 drive a 50 Ohm load to Vinl or Vinh. I'd caution against = using a 500=20 Ohm load in your model making unless there is a very good reason to do = so. =20

The=20 Ramp key word is a legacy key word that was used before the VT waveforms = were=20 added to IBIS. It is still required to be present in the model. If = R_fixture is not specified it defaults to 50 Ohm in the=20 model.

-----Original Message-----
From:=20 owner-ibis-users@server.eda.org = [mailto:owner-ibis-users@server.eda.org] On=20 Behalf Of April.Hachenburg@smsc.com
Sent: Wednesday, = December=20 20, 2006 9:39 AM
To: ibis-users@server.eda.org
Cc: = akvarma@ncsu.edu
Subject: [IBIS-Users] Ramp vs. = Rising/Falling=20 waveforms, Cref missing ...

IBIS Users,
I wondered if anyone could clarify for me the = usage of=20 Rload vs. Rref vs. Rfixture and similarly Cref vs. Cfixture.=20

I am using s2ibis3 and = discovered that=20 the Cref parameter specified in my .s2i file does not appear in my = .ibs model=20 file. After looking at the netlists and reading the IBIS = documentation,=20 it appears Cref is not used for any simulations. What is the = purpose of=20 Cref? And why isn't it showing up in the .ibs file? =

Also, I read that C_comp is taken into = account for the=20 rising/falling V-T waveforms though I cannot find that paramater in = any of the=20 corresponding netlists. How is C_comp used?

As for Rref vs. Rfixture, I thought I read = somewhere=20 that for best results Rref should match Rfixture. Is that true? = In my model, I am using the keywords Rising/Falling Waveform. = I=20 found that if I do not specify Rload even though I am not specifying = the=20 [Ramp] keyword, then 50ohms is used in one of the transient = simulations=20 despite Rref and Rfixture being set to 500 ohms. Should I be = specifying=20 the [Ramp] keyword along with the [Rising/Falling Waveform] keywords? = If so,=20 how do they work together?

-=20 = April

---------------------------------------------------
April= =20 Hachenburg
Core Technology Design Engineer
SMSC=20

- ------=_NextPart_000_005F_01C72430.62F17550-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 21 Dec 2006 07:25:44 +0800 From: "NG,MEI-YEE" Subject: RE: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref missing ... This is a multi-part message in MIME format. - ------_=_NextPart_001_01C7248E.2C4F244B Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Tom, =20 I find your reply very useful. Thank you for the information. There is one question regarding C_comp that I would like to ask. When I run simulation to extract V-T curves, I used an extracted RC netlist, which means it has taken into account parasitic R and C of the buffer. In that case, do I still need to specify another C_comp value? Would that mean double-calculating this C_comp? =20 Kindly advice. Thank you. =20 Best regards, Mei Yee IC Design Engineer Avago Technologies =20 ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Tom Dagostino Sent: Thursday, December 21, 2006 4:14 AM To: April.Hachenburg@smsc.com; ibis-users@server.eda.org Cc: akvarma@ncsu.edu Subject: RE: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref missing ... =20 April =20 R_load is the load the buffer is placed under when the ramp data is acquired. 50 Ohms is the typical value and it is usually terminated to ground for the dV/dT rise and to power for the dV/dT fall. =20 =20 R_fixture is the load the buffer is placed under when the VT waveforms as acquired. This value is typically 50 Ohms and is terminated to ground for both a rising and falling waveform and then terminated to power for the other set of rising and falling waveforms. C_fixture would be any capacitance associated with the R_fixture. But its not a good idea to have any C_fixture when extracting VT waveforms. I've seen simulator give very wrong answers when C_fixture is present. =20 Rref is the manufacturer's timing test load's resistive component. This can be any value (within reason) and can be terminated to any reasonable voltage Vref the manufacturer deems appropriate for the buffer technology. It is usually terminated to the typical value the buffer would see in an actual application. If the buffer was an ECL output then 50 Ohms to Vcc-2Volts would be the load. Most CMOS devices have just a Cref, a capacitor terminated to ground. =20 C_comp is the capacitance associated with the I/O buffer. It includes all the capacitance from metal, active or passive devices on the silicon. It forms the majority of the buffer's impedance reactive component. =20 R_fixture should match the load the buffer is seeing in an actual application. Most circuit boards trace impedance runs between 40 and 70 Ohms or there about. Most buffers are characterized into a 50 Ohm load which is close to the board impedance. Since the model developer cannot predict every application 50 Ohms is a good compromise for most models. There are some technologies that are better served with a non 50 Ohm load such as RAMBUS, which is specified into 27 Ohms or very weak CMOS drivers that cannot drive a 50 Ohm load to Vinl or Vinh. I'd caution against using a 500 Ohm load in your model making unless there is a very good reason to do so. =20 =20 The Ramp key word is a legacy key word that was used before the VT waveforms were added to IBIS. It is still required to be present in the model. If R_fixture is not specified it defaults to 50 Ohm in the model. =20 =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of April.Hachenburg@smsc.com Sent: Wednesday, December 20, 2006 9:39 AM To: ibis-users@server.eda.org Cc: akvarma@ncsu.edu Subject: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref missing ... =09 IBIS Users,=20 I wondered if anyone could clarify for me the usage of Rload vs. Rref vs. Rfixture and similarly Cref vs. Cfixture.=20 =09 I am using s2ibis3 and discovered that the Cref parameter specified in my .s2i file does not appear in my .ibs model file. After looking at the netlists and reading the IBIS documentation, it appears Cref is not used for any simulations. What is the purpose of Cref? And why isn't it showing up in the .ibs file?=20 =09 Also, I read that C_comp is taken into account for the rising/falling V-T waveforms though I cannot find that paramater in any of the corresponding netlists. How is C_comp used?=20 =09 As for Rref vs. Rfixture, I thought I read somewhere that for best results Rref should match Rfixture. Is that true? In my model, I am using the keywords Rising/Falling Waveform. I found that if I do not specify Rload even though I am not specifying the [Ramp] keyword, then 50ohms is used in one of the transient simulations despite Rref and Rfixture being set to 500 ohms. Should I be specifying the [Ramp] keyword along with the [Rising/Falling Waveform] keywords? If so, how do they work together?=20 =09 - April =09 --------------------------------------------------- April Hachenburg Core Technology Design Engineer SMSC=20 - ------_=_NextPart_001_01C7248E.2C4F244B Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Message

Hi = Tom,

I find your reply very useful. = Thank you for the information. There is one question regarding C_comp that I would = like to ask. When I run simulation to extract V-T curves, I used an extracted = RC netlist, which means it has taken into account parasitic R and C of the buffer. = In that case, do I still need to specify another C_comp value? Would that mean double-calculating this C_comp?

Kindly = advice.

Thank you.

Best = regards,

Mei = Yee

IC Design = Engineer

Avago = Technologies

From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] = On Behalf Of Tom Dagostino
Sent: Thursday, December = 21, 2006 4:14 AM
To: = April.Hachenburg@smsc.com; ibis-users@server.eda.org
Cc: akvarma@ncsu.edu
Subject: RE: [IBIS-Users] = Ramp vs. Rising/Falling waveforms, Cref missing ...

April

R_load is the load the buffer is = placed under when the ramp data is acquired. 50 Ohms is the typical value = and it is usually terminated to ground for the dV/dT rise and to power for the = dV/dT fall.

R_fixture is the load the buffer is = placed under when the VT waveforms as acquired. This value is typically = 50 Ohms and is terminated to ground for both a rising and falling waveform and = then terminated to power for the other set of rising and falling = waveforms. C_fixture would be any capacitance associated with the R_fixture. = But its not a good idea to have any C_fixture when extracting VT = waveforms. I've seen simulator give very wrong answers when C_fixture is = present.

Rref is the manufacturer's timing = test load's resistive component. This can be any value (within reason) = and can be terminated to any reasonable voltage Vref the manufacturer deems appropriate for the buffer technology. It is usually terminated to = the typical value the buffer would see in an actual application. If = the buffer was an ECL output then 50 Ohms to Vcc-2Volts would be the = load. Most CMOS devices have just a Cref, a capacitor terminated to = ground.

C_comp is the capacitance = associated with the I/O buffer. It includes all the capacitance from metal, active or = passive devices on the silicon. It forms the majority of the buffer's = impedance reactive component.

R_fixture should match the load the = buffer is seeing in an actual application. Most circuit boards trace = impedance runs between 40 and 70 Ohms or there about. Most buffers are = characterized into a 50 Ohm load which is close to the board impedance. Since = the model developer cannot predict every application 50 Ohms is a good compromise = for most models. There are some technologies that are better served = with a non 50 Ohm load such as RAMBUS, which is specified into 27 Ohms or very = weak CMOS drivers that cannot drive a 50 Ohm load to Vinl or Vinh. I'd caution against using a 500 Ohm load in your model making = unless there is a very good reason to do so.

The Ramp key word is a legacy key = word that was used before the VT waveforms were added to IBIS. It is = still required to be present in the model. If R_fixture is not specified it = defaults to 50 Ohm in the model.

-----Original = Message-----
From: = owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of April.Hachenburg@smsc.com
Sent: Wednesday, December = 20, 2006 9:39 AM
To: = ibis-users@server.eda.org
Cc: akvarma@ncsu.edu
Subject: [IBIS-Users] = Ramp vs. Rising/Falling waveforms, Cref missing ...

IBIS Users,
I wondered if anyone could clarify for me the usage of Rload vs. Rref = vs. Rfixture and similarly Cref vs. Cfixture.

I am using s2ibis3 and discovered that the Cref parameter specified in my = .s2i file does not appear in my .ibs model file. After looking at the = netlists and reading the IBIS documentation, it appears Cref is not used for any simulations. What is the purpose of Cref? And why isn't it = showing up in the .ibs file?

Also, I read that C_comp is taken into account for the rising/falling V-T = waveforms though I cannot find that paramater in any of the corresponding = netlists. How is C_comp used?

As for Rref vs. Rfixture, I thought I read somewhere that for best results = Rref should match Rfixture. Is that true? In my model, I am = using the keywords Rising/Falling Waveform. I found that if I do not specify = Rload even though I am not specifying the [Ramp] keyword, then 50ohms is used = in one of the transient simulations despite Rref and Rfixture being set to 500 = ohms. Should I be specifying the [Ramp] keyword along with the [Rising/Falling = Waveform] keywords? If so, how do they work together?

- April

- ---------------------------------------------------
April Hachenburg
Core Technology Design Engineer
SMSC

- ------_=_NextPart_001_01C7248E.2C4F244B-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 20 Dec 2006 16:22:11 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref missing ... This is a multi-part message in MIME format. - ------=_NextPart_000_002A_01C72453.00F41470 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Yes, you still need to have C_comp in the model. Most simulators, from = what I have heard, don't use C_comp when they are using the buffer as a = driver. But when the buffer is receiving a signal, such as a reflection, the simulator puts C_comp into the simulation.. Ask your specific simulator company for details on how they handle this situation. =20 =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 - -----Original Message----- From: NG,MEI-YEE [mailto:mei-yee.ng@avagotech.com]=20 Sent: Wednesday, December 20, 2006 3:26 PM To: tom@teraspeed.com; April.Hachenburg@smsc.com; = ibis-users@server.eda.org Cc: akvarma@ncsu.edu Subject: RE: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref = missing ... Hi Tom, =20 I find your reply very useful. Thank you for the information. There is = one question regarding C_comp that I would like to ask. When I run = simulation to extract V-T curves, I used an extracted RC netlist, which means it has = taken into account parasitic R and C of the buffer. In that case, do I still = need to specify another C_comp value? Would that mean double-calculating this C_comp? =20 Kindly advice. Thank you. =20 Best regards, Mei Yee IC Design Engineer Avago Technologies =20 _____ =20 From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Tom Dagostino Sent: Thursday, December 21, 2006 4:14 AM To: April.Hachenburg@smsc.com; ibis-users@server.eda.org Cc: akvarma@ncsu.edu Subject: RE: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref = missing ... =20 April =20 R_load is the load the buffer is placed under when the ramp data is acquired. 50 Ohms is the typical value and it is usually terminated to ground for the dV/dT rise and to power for the dV/dT fall. =20 =20 R_fixture is the load the buffer is placed under when the VT waveforms = as acquired. This value is typically 50 Ohms and is terminated to ground = for both a rising and falling waveform and then terminated to power for the other set of rising and falling waveforms. C_fixture would be any capacitance associated with the R_fixture. But its not a good idea to = have any C_fixture when extracting VT waveforms. I've seen simulator give = very wrong answers when C_fixture is present. =20 Rref is the manufacturer's timing test load's resistive component. This = can be any value (within reason) and can be terminated to any reasonable = voltage Vref the manufacturer deems appropriate for the buffer technology. It = is usually terminated to the typical value the buffer would see in an = actual application. If the buffer was an ECL output then 50 Ohms to Vcc-2Volts would be the load. Most CMOS devices have just a Cref, a capacitor terminated to ground. =20 C_comp is the capacitance associated with the I/O buffer. It includes = all the capacitance from metal, active or passive devices on the silicon. = It forms the majority of the buffer's impedance reactive component. =20 R_fixture should match the load the buffer is seeing in an actual application. Most circuit boards trace impedance runs between 40 and 70 Ohms or there about. Most buffers are characterized into a 50 Ohm load which is close to the board impedance. Since the model developer cannot predict every application 50 Ohms is a good compromise for most models. There are some technologies that are better served with a non 50 Ohm = load such as RAMBUS, which is specified into 27 Ohms or very weak CMOS = drivers that cannot drive a 50 Ohm load to Vinl or Vinh. I'd caution against = using a 500 Ohm load in your model making unless there is a very good reason = to do so. =20 =20 The Ramp key word is a legacy key word that was used before the VT = waveforms were added to IBIS. It is still required to be present in the model. If R_fixture is not specified it defaults to 50 Ohm in the model. =20 =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of April.Hachenburg@smsc.com Sent: Wednesday, December 20, 2006 9:39 AM To: ibis-users@server.eda.org Cc: akvarma@ncsu.edu Subject: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref missing = ... IBIS Users,=20 I wondered if anyone could clarify for me the usage of Rload vs. Rref = vs. Rfixture and similarly Cref vs. Cfixture.=20 I am using s2ibis3 and discovered that the Cref parameter specified in = my .s2i file does not appear in my .ibs model file. After looking at the netlists and reading the IBIS documentation, it appears Cref is not used = for any simulations. What is the purpose of Cref? And why isn't it showing = up in the .ibs file?=20 Also, I read that C_comp is taken into account for the rising/falling = V-T waveforms though I cannot find that paramater in any of the = corresponding netlists. How is C_comp used?=20 As for Rref vs. Rfixture, I thought I read somewhere that for best = results Rref should match Rfixture. Is that true? In my model, I am using the keywords Rising/Falling Waveform. I found that if I do not specify = Rload even though I am not specifying the [Ramp] keyword, then 50ohms is used = in one of the transient simulations despite Rref and Rfixture being set to = 500 ohms. Should I be specifying the [Ramp] keyword along with the [Rising/Falling Waveform] keywords? If so, how do they work together?=20 - - April - --------------------------------------------------- April Hachenburg Core Technology Design Engineer SMSC=20 - ------=_NextPart_000_002A_01C72453.00F41470 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Yes,=20 you still need to have C_comp in the model. Most simulators, from = what I=20 have heard, don't use C_comp when they are using the buffer as a = driver. =20 But when the buffer is receiving a signal, such as a reflection, the = simulator=20 puts C_comp into the simulation.. Ask your specific simulator company = for=20 details on how they handle this situation.

-----Original Message-----
From: = NG,MEI-YEE=20 [mailto:mei-yee.ng@avagotech.com]
Sent: Wednesday, December = 20,=20 2006 3:26 PM
To: tom@teraspeed.com; = April.Hachenburg@smsc.com;=20 ibis-users@server.eda.org
Cc: = akvarma@ncsu.edu
Subject:=20 RE: [IBIS-Users] Ramp vs. Rising/Falling waveforms, Cref missing=20 ...

Hi=20 Tom,

I find your = reply=20 very useful. Thank you for the information. There is one question = regarding=20 C_comp that I would like to ask. When I run simulation to extract V-T = curves,=20 I used an extracted RC netlist, which means it has taken into account=20 parasitic R and C of the buffer. In that case, do I still need to = specify=20 another C_comp value? Would that mean double-calculating this=20 C_comp?

Kindly=20 advice.

Thank=20 you.

Best=20 regards,

Mei=20 Yee

IC Design=20 Engineer

Avago=20 Technologies

From:=20 owner-ibis-users@server.eda.org = [mailto:owner-ibis-users@server.eda.org]=20 On Behalf Of Tom=20 Dagostino
Sent: = Thursday,=20 December 21, 2006 4:14 AM
To:=20 April.Hachenburg@smsc.com; ibis-users@server.eda.org
Cc: = akvarma@ncsu.edu
Subject: RE: [IBIS-Users] Ramp = vs.=20 Rising/Falling waveforms, Cref missing = ...

April

R_load is = the load=20 the buffer is placed under when the ramp data is acquired. 50 = Ohms is=20 the typical value and it is usually terminated to ground for the dV/dT = rise=20 and to power for the dV/dT fall. =

R_fixture = is the load=20 the buffer is placed under when the VT waveforms as acquired. = This value=20 is typically 50 Ohms and is terminated to ground for both a rising and = falling=20 waveform and then terminated to power for the other set of rising and = falling=20 waveforms. C_fixture would be any capacitance associated with = the=20 R_fixture. But its not a good idea to have any C_fixture when = extracting=20 VT waveforms. I've seen simulator give very wrong answers when = C_fixture=20 is present.

Rref is the = manufacturer's timing test load's resistive component. This can = be any=20 value (within reason) and can be terminated to any reasonable voltage=20 Vref the manufacturer deems appropriate for the buffer = technology. =20 It is usually terminated to the typical value the buffer would see in = an=20 actual application. If the buffer was an ECL output then 50 Ohms = to=20 Vcc-2Volts would be the load. Most CMOS devices have just a = Cref, a=20 capacitor terminated to ground.

C_comp is = the=20 capacitance associated with the I/O buffer. It includes all the = capacitance=20 from metal, active or passive devices on the silicon. It forms = the=20 majority of the buffer's impedance reactive=20 component.

R_fixture = should=20 match the load the buffer is seeing in an actual application. = Most=20 circuit boards trace impedance runs between 40 and 70 Ohms or there=20 about. Most buffers are characterized into a 50 Ohm load which = is close=20 to the board impedance. Since the model developer cannot predict = every=20 application 50 Ohms is a good compromise for most models. There = are some=20 technologies that are better served with a non 50 Ohm load such as = RAMBUS,=20 which is specified into 27 Ohms or very weak CMOS drivers that cannot = drive a=20 50 Ohm load to Vinl or Vinh. I'd caution against using a = 500 Ohm=20 load in your model making unless there is a very good reason to do = so. =20

The Ramp = key word is=20 a legacy key word that was used before the VT waveforms were added to=20 IBIS. It is still required to be present in the model. If = R_fixture is=20 not specified it defaults to 50 Ohm in the=20 model.

Tom=20 Dagostino
Teraspeed(R) Labs
13610 SW Harness = Lane
Beaverton, OR 97008
503-430-1065
tom@teraspeed.com
www.teraspeed.com
Teraspeed=20 Consulting Group LLC
121 North=20 River Drive
Narragansett, RI=20 02882
401-284-1827=20

-----Original=20 Message-----
From:=20 owner-ibis-users@server.eda.org = [mailto:owner-ibis-users@server.eda.org]=20 On Behalf Of=20 April.Hachenburg@smsc.com
Sent: Wednesday, December 20, = 2006 9:39=20 AM
To:=20 ibis-users@server.eda.org
Cc: = akvarma@ncsu.edu
Subject: [IBIS-Users] Ramp = vs.=20 Rising/Falling waveforms, Cref missing = ...

IBIS Users,
I = wondered=20 if anyone could clarify for me the usage of Rload vs. Rref vs. = Rfixture and=20 similarly Cref vs. Cfixture.

I = am using=20 s2ibis3 and discovered that the Cref parameter specified in my .s2i = file=20 does not appear in my .ibs model file. After looking at the = netlists=20 and reading the IBIS documentation, it appears Cref is not used for = any=20 simulations. What is the purpose of Cref? And why isn't = it=20 showing up in the .ibs file?

Also, I read=20 that C_comp is taken into account for the rising/falling V-T = waveforms=20 though I cannot find that paramater in any of the corresponding = netlists.=20 How is C_comp used?

As = for Rref=20 vs. Rfixture, I thought I read somewhere that for best results Rref = should=20 match Rfixture. Is that true? In my model, I am using = the=20 keywords Rising/Falling Waveform. I found that if I do not = specify=20 Rload even though I am not specifying the [Ramp] keyword, then = 50ohms is=20 used in one of the transient simulations despite Rref and Rfixture = being set=20 to 500 ohms. Should I be specifying the [Ramp] keyword along = with the=20 [Rising/Falling Waveform] keywords? If so, how do they work=20 together?

-=20 = April

---------------------------------------------------
April= =20 Hachenburg
Core Technology Design Engineer
SMSC=20 =

- ------=_NextPart_000_002A_01C72453.00F41470-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 21 Dec 2006 10:53:29 +0530 From: Sujit Kumar-r65837 Subject: [IBIS-Users] pulse/step description for v/t curves - --------------010109010703010604080304 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit hi IBIS users Can anyone help me for this? Sujit Kumar-r65837 wrote: > How to specify the pulse/step description in .s2i file for > generating v/t curves? > How do you reach upon those values? > > > -- > thanks > sujit kumar > > > > > +91-120-4396069 > +91-09910168788 > > - -- thanks sujit kumar +91-120-4396069 +91-09910168788 - --------------010109010703010604080304 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit hi IBIS users
Can anyone help me for this?

Sujit Kumar-r65837 wrote:

How to specify the pulse/step description in .s2i file for generating v/t curves?
How do you reach upon those values?

--

thanks
sujit kumar

+91-120-4396069
+91-09910168788

thanks
sujit kumar

+91-120-4396069
+91-09910168788

- --------------010109010703010604080304-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 21 Dec 2006 13:43:17 +0800 From: "NG,MEI-YEE" Subject: RE: [IBIS-Users] pulse/step description for v/t curves This is a multi-part message in MIME format. - ------_=_NextPart_001_01C724C2.EA5C8D1B Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Sujit, =20 From my limited experience with s2ibis3, I discovered that the pulse size was generated by dividing your sweep range by 100 points. If you need to make it finer, you might need to edit the .spi files manually, but keep in mind that the number of points allowed for version 3.2 is 100 only. =20 Thank you. =20 Best regards, Mei Yee SID, Avago Technologies (Malaysia) Tel no.:604-6108515 ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Sujit Kumar-r65837 Sent: Thursday, December 21, 2006 1:23 PM To: Sujit Kumar-r65837 Cc: ibis-users@server.eda.org Subject: [IBIS-Users] pulse/step description for v/t curves =20 hi IBIS users Can anyone help me for this? Sujit Kumar-r65837 wrote: How to specify the pulse/step description in .s2i file for generating v/t curves? How do you reach upon those values? - --=20 thanks sujit kumar +91-120-4396069 +91-09910168788=20 =20 =20 - --=20 thanks sujit kumar +91-120-4396069 +91-09910168788=20 =20 =20 - ------_=_NextPart_001_01C724C2.EA5C8D1B Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi = Sujit,

From my limited experience with = s2ibis3, I discovered that the pulse size was generated by dividing your sweep = range by 100 points. If you need to make it finer, you might need to edit the = .spi files manually, but keep in mind that the number of points allowed for version = 3.2 is 100 only.

Thank = you.

Best = regards,

Mei = Yee

SID, Avago Technologies = (Malaysia)

Tel = no.:604-6108515

From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] = On Behalf Of Sujit = Kumar-r65837
Sent: Thursday, December = 21, 2006 1:23 PM
To: Sujit = Kumar-r65837
Cc: = ibis-users@server.eda.org
Subject: [IBIS-Users] = pulse/step description for v/t curves

hi IBIS users
Can anyone help me for this?

Sujit Kumar-r65837 wrote:

How to specify = the pulse/step description in .s2i file for generating v/t = curves?
How do you reach upon those values?

thanks
sujit kumar

+91-120-4396069
+91-09910168788

- ------_=_NextPart_001_01C724C2.EA5C8D1B-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #91 ************************