From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #93 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Friday, January 12 2007 Volume 01 : Number 093 ---------------------------------------------------------------------- Date: Thu, 4 Jan 2007 11:43:03 +0530 From: Sudarshan Honnudike Subject: [IBIS-Users] Common Mode range for Differential cells. This is a multipart message in MIME format. - --=_alternative 0021E65B65257259_= Content-Type: text/plain; charset="US-ASCII" Hi Experts, With the new IBIS specification we can define the differential pins with the construct [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max 1 2 200mv NA NA NA With this construct we can define the minimum difference voltage Vdiff(1-2) between the two differential pins to get logic state at the differential output. At the same time another important parameter which determines the differential output is common mode range. If the differnence between the two pins(1-2) is at its correct value ( -200 > Vdiff >200 ) but if it is not in the common mode range then output is undefined. Is there any way to define the Common Mode Range for differential cells in IBIS ? Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=_alternative 0021E65B65257259_= Content-Type: text/html; charset="US-ASCII"
Hi Experts,

With the  new IBIS specification we can define the differential pins with the construct

[Diff Pin]     inv_pin     vdiff      tdelay_typ    tdelay_min     tdelay_max
  1                    2              200mv         NA           NA                       NA

With this construct we can define the minimum difference voltage Vdiff(1-2) between the two differential pins to get
logic state at the differential output. At the same time another important parameter which determines the differential
output is common mode range. If the differnence between the two pins(1-2) is at its correct value ( -200 > Vdiff >200 )
but if it is not in the common mode range then output is undefined.

Is there any way to define the Common Mode Range for differential cells in IBIS ?

Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com
--
This message has been scanned for viruses and
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believed to be clean. - --=_alternative 0021E65B65257259_=-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 9 Jan 2007 21:41:39 +0200 From: "haim as" Subject: [IBIS-Users] IBIS Model Selector question - ------=_Part_102741_33403542.1168371699499 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Hello, I'm building a full chip ibis model and looking for an option to define something: I have group of signals which share the same "model_name". That model_name allow the user to select specific model from the [Model selector] definition. Is it possible to define that if the user selects specific model for one I/O in that group, the hole group will get the same model? Thanks for your time, Haim. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_Part_102741_33403542.1168371699499 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline

Hello,


I'm building a full chip ibis model and looking for an option to define something:


I have group of signals which share the same "model_name".

That model_name allow the user to select specific model from the [Model selector] definition.

Is it possible to define that if the user selects specific model for one I/O in that group, the hole group will get the same model?

 

Thanks for your time,

Haim.


--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_Part_102741_33403542.1168371699499-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 9 Jan 2007 11:59:58 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] IBIS Model Selector question This is a multi-part message in MIME format. - ------=_NextPart_000_02EE_01C733E5.B5A7F840 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable That is how it works =20 =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of haim as Sent: Tuesday, January 09, 2007 11:42 AM To: ibis-users@server.eda.org Subject: [IBIS-Users] IBIS Model Selector question Hello,=20 I'm building a full chip ibis model and looking for an option to define something: I have group of signals which share the same "model_name".=20 That model_name allow the user to select specific model from the [Model selector] definition.=20 Is it possible to define that if the user selects specific model for one I/O in that group, the hole group will get the same model? =20 Thanks for your time, Haim. - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner, and is=20 believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_02EE_01C733E5.B5A7F840 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Message
That=20 is how it works
 
 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness=20 Lane
Beaverton, OR=20 97008
503-430-1065
tom@teraspeed.com
www.teraspeed.com

Tera= speed=20 Consulting Group LLC
121 North River Drive
Narragansett, RI=20 02882
401-284-1827

-----Original Message-----
From:=20 owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] = On=20 Behalf Of haim as
Sent: Tuesday, January 09, 2007 11:42=20 AM
To: ibis-users@server.eda.org
Subject: [IBIS-Users= ]=20 IBIS Model Selector question

Hello,


I'm building a full chip ibis model and looking for an option to d= efine=20 something:


I have group of signals which share the same "model_name".

That model_name allow the user to select specific model from the [Mode= l=20 selector] definition.

Is it possible to define that if the user selects specific model for o= ne=20 I/O in that group, the hole group will get the same model?

 

Thanks for your time,

Haim.


--
This message has been scanned for viruses and= =20
dangerous content by MailScanner, and is=20
believed to be clean.

--=20
This message has been scanned for viruses and
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believed to be clean. - ------=_NextPart_000_02EE_01C733E5.B5A7F840-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 10 Jan 2007 11:04:37 +0530 From: Sudarshan Honnudike Subject: [IBIS-Users] Information on Vref, Rref & Cref This is a multipart message in MIME format. - --=_alternative 001E619C6525725F_= Content-Type: text/plain; charset="US-ASCII" Hi , If we have a IO pad which works in the different applications depending on the load applied on it, then do we to provide V-t waveforms(more than normal 4 curves) for different applications with different load settings.? Or can we specify that loading conditions under Rref, Vref and Cref for that model. Which one is preferable. ? I tested my model with Hyperlynx SI tool and it is not identifying the Rref and Vref values that I am specifying in my model. It will only take Cref and Vmeas while doing simulations. In that case we can't specify the loading conditions under Vref, Cref and Vref but we need to give all possible V-t curve combinations for different loading conditions. Please let me know your reply. PS : I am also waiting for the reply to my previous mail regarding Common Mode Voltage Range support in IBIS . Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=_alternative 001E619C6525725F_= Content-Type: text/html; charset="US-ASCII"
Hi ,

If we have a IO pad which works in the different applications depending on the load applied
on it, then do we to  provide V-t waveforms(more than normal 4 curves) for different applications
with different load settings.?

Or can we specify that loading conditions under Rref, Vref and Cref for that model. Which one is preferable. ?

I tested my model with Hyperlynx SI tool and it is not identifying the Rref and Vref values that I am specifying
in my model. It will only take Cref and Vmeas while doing simulations. In that case we can't specify the loading
conditions under Vref, Cref and Vref but we need to give all possible V-t curve combinations for different loading conditions.

Please let me know your reply.

PS : I am also waiting for the reply to my previous mail regarding Common Mode Voltage Range support in IBIS .

Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com
--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --=_alternative 001E619C6525725F_=-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 10 Jan 2007 10:47:10 +0100 From: "Alex Hilbers" Subject: RE: [IBIS-Users] Information on Vref, Rref & Cref - ------_=_NextPart_001_01C7349C.4C4674B9 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Sudarshan, =20 Interesting question. I always wondered how a table based model (V-I, ..), such as an IBIS model, could model any form of feedback control system, as the IO pad you describe probably is. It seems that V-t waveforms, together with a simulation tool specific algorithm, must do that job. You verify this by comparing your simulation tool with actual SPICE results. This is prone to variation based on which tool you use, I donot think this 'algorithm' is standardised. To my knowledge XTK needs the curves rising/falling, for load to VCC and GND (i.e. all 4), otherwise the V-t tables are ignored. (Some vendors do provide only 1 or 2, which is useless). Interesting is what happens if you define several load conditions (Rfixture =3D 25, 50, 75 Ohms), not to mention capacitive and inductive loading. What will the simualtion tool choose, will it interpolate, I donot have the faintest idea. I guess it won't work within IBIS, which may be the reason you do not get answers.=20 =20 Maybe a good reason to provide SPICE models for this type of buffer. Either under NDA or encrypted. Level 50 HSPICE, i.e. Philips MOS Model 9, should be fine.=20 =20 Best regards, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Alex Hilbers=20 Signal Integrity Analysis and Thermal Management, ASML, EDEV department Building 7J0005, P.O. Box 324, 5500 AH Veldhoven, The Netherlands Phone: +31-(0)40-268 5587, Fax: +31-(0)40-268 5530 Email: alex.hilbers@asml.com, www.asml.com =20 =20 ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Sudarshan Honnudike Sent: Wednesday, January 10, 2007 6:35 AM To: ibis-users@eda.org Subject: [IBIS-Users] Information on Vref, Rref & Cref Hi ,=20 If we have a IO pad which works in the different applications depending on the load applied=20 on it, then do we to provide V-t waveforms(more than normal 4 curves) for different applications=20 with different load settings.?=20 Or can we specify that loading conditions under Rref, Vref and Cref for that model. Which one is preferable. ?=20 I tested my model with Hyperlynx SI tool and it is not identifying the Rref and Vref values that I am specifying=20 in my model. It will only take Cref and Vmeas while doing simulations. In that case we can't specify the loading=20 conditions under Vref, Cref and Vref but we need to give all possible V-t curve combinations for different loading conditions.=20 Please let me know your reply.=20 PS : I am also waiting for the reply to my previous mail regarding Common Mode Voltage Range support in IBIS .=20 Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India.=20=20=20=20 Ph:+91-80-40267073=20=20 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 The information contained in this communication and any attachments is conf= idential and may be privileged, and is for the sole use of the intended recipient(s)= . Any unauthorized review, use, disclosure or distribution is prohibited. If you = are not the intended recipient, please notify the sender immediately by replying to= this message and destroy all copies of this message and any attachments. ASML is= neither liable for the proper and complete transmission of the information containe= d in this communication, nor for any delay in its receipt. - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C7349C.4C4674B9 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Sudarshan,
 
Interesting question. I always wondered how=20 a table based model (V-I, ..), such as an IBIS model, could model any = form=20 of feedback control system, as the IO pad you describe probably is.=20 It seems that V-t waveforms, together with a sim= ulation=20 tool specific algorithm, must do that job. You verify this by comparing you= r=20 simulation tool with actual SPICE results. This is prone to variation based= on=20 which tool you use, I donot think this 'algorithm' is standardised. To= my=20 knowledge XTK needs the curves rising/falling, for load to VCC and GND (i.e= . all=20 4), otherwise the V-t tables are ignored. (Some vendors do provide only 1 o= r 2,=20 which is useless). Interesting is what happens if you define several load= =20 conditions (Rfixture =3D 25, 50, 75 Ohms), not to mention capacitive and in= ductive=20 loading. What will the simualtion tool choose, will it interpolate, I donot= have=20 the faintest idea. I guess it won't work within IBIS, which may be the reas= on=20 you do not get answers.
 
Maybe a good reason to provide SPICE models for = this=20 type of buffer. Either under NDA or encrypted. Level 50 HSPICE, i.e. Philip= s MOS=20 Model 9, should be fine.
 
Best regards,
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~
Alex=20 Hilbers
Signal Integrity Analysis and Thermal Management, ASML, EDEV=20 department

Building 7J0005, P.O. Box 324, 5500 AH Veldhoven, The=20 Netherlands
Phone: +31-(0)40-268 5587, Fax: +31-(0)40-268 5530
Email:= alex.hilbers@asml.com, www.asml.com

 

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Sudarshan=20 Honnudike
Sent: Wednesday, January 10, 2007 6:35 AM
To:= =20 ibis-users@eda.org
Subject: [IBIS-Users] Information on Vref, Rre= f=20 & Cref


Hi ,

If we have a IO pad which works in the different= =20 applications depending on the load applied
on it, then do we to  provide V-t waveforms(more than normal = 4=20 curves) for different applications
with=20 different load settings.?

O= r can we=20 specify that loading conditions under Rref, Vref and Cref for that model. W= hich=20 one is preferable. ?

I test= ed my=20 model with Hyperlynx SI tool and it is not identifying the Rref and Vref va= lues=20 that I am specifying
in my mode= l. It=20 will only take Cref and Vmeas while doing simulations. In that case we can'= t=20 specify the loading
conditions = under=20 Vref, Cref and Vref but we need to give all possible V-t curve combinations= for=20 different loading conditions.

Please=20 let me know your reply.

PS = : I am=20 also waiting for the reply to my previous mail regarding Common Mode Voltag= e=20 Range support in IBIS .

Bes= t=20 Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata= Tech=20 Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-402= 67073=20  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail:=20 sudarshan.honnudike@nxp.com
--
This message has been scanned = for=20 viruses and
dangerous content by MailScanner, and is
be= lieved=20 to be clean.
-- =0D The information contained in this communication and any attachments is conf= idential=0D and may be privileged, and is for the sole use of the intended recipient(s)= . Any=0D unauthorized review, use, disclosure or distribution is prohibited. If you = are not=0D the intended recipient, please notify the sender immediately by replying to= this=0D message and destroy all copies of this message and any attachments. ASML is= neither=0D liable for the proper and complete transmission of the information containe= d in this=0D communication, nor for any delay in its receipt.=0D
--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------_=_NextPart_001_01C7349C.4C4674B9-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 10 Jan 2007 03:03:27 -0800 From: "Lynne D. Green" Subject: RE: [IBIS-Users] Information on Vref, Rref & Cref I was somewhat confused about the loading question and reply. Rref and Cref are for timing checks, not for simulation. The loading for V-t tables is R_fixture. So both are needed in a model. One should not use reactive loading in a V-t table. This has been observed to "break" the algorithm as implemented by some SI tools. The underlying algorithms have been published in two papers: * The Development of Analog SPICE Behavioral Model Based on IBIS Model Ying Wang & Han Ngee Tan * Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS P. Tehrani, Y. Chen & J. Fang - - Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Alex Hilbers Sent: Wednesday, January 10, 2007 1:47 AM To: Sudarshan Honnudike; ibis-users@eda.org Subject: RE: [IBIS-Users] Information on Vref, Rref & Cref Sudarshan, Interesting question. I always wondered how a table based model (V-I, ..), such as an IBIS model, could model any form of feedback control system, as the IO pad you describe probably is. It seems that V-t waveforms, together with a simulation tool specific algorithm, must do that job. You verify this by comparing your simulation tool with actual SPICE results. This is prone to variation based on which tool you use, I donot think this 'algorithm' is standardised. To my knowledge XTK needs the curves rising/falling, for load to VCC and GND (i.e. all 4), otherwise the V-t tables are ignored. (Some vendors do provide only 1 or 2, which is useless). Interesting is what happens if you define several load conditions (Rfixture = 25, 50, 75 Ohms), not to mention capacitive and inductive loading. What will the simualtion tool choose, will it interpolate, I donot have the faintest idea. I guess it won't work within IBIS, which may be the reason you do not get answers. Maybe a good reason to provide SPICE models for this type of buffer. Either under NDA or encrypted. Level 50 HSPICE, i.e. Philips MOS Model 9, should be fine. Best regards, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Alex Hilbers Signal Integrity Analysis and Thermal Management, ASML, EDEV department Building 7J0005, P.O. Box 324, 5500 AH Veldhoven, The Netherlands Phone: +31-(0)40-268 5587, Fax: +31-(0)40-268 5530 Email: alex.hilbers@asml.com, www.asml.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Sudarshan Honnudike Sent: Wednesday, January 10, 2007 6:35 AM To: ibis-users@eda.org Subject: [IBIS-Users] Information on Vref, Rref & Cref Hi , If we have a IO pad which works in the different applications depending on the load applied on it, then do we to provide V-t waveforms(more than normal 4 curves) for different applications with different load settings.? Or can we specify that loading conditions under Rref, Vref and Cref for that model. Which one is preferable. ? I tested my model with Hyperlynx SI tool and it is not identifying the Rref and Vref values that I am specifying in my model. It will only take Cref and Vmeas while doing simulations. In that case we can't specify the loading conditions under Vref, Cref and Vref but we need to give all possible V-t curve combinations for different loading conditions. Please let me know your reply. PS : I am also waiting for the reply to my previous mail regarding Common Mode Voltage Range support in IBIS . Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com -- This message has been scanned for viruses and dangerous content by MailScanner , and is believed to be clean. -- The information contained in this communication and any attachments is confidential and may be privileged, and is for the sole use of the intended recipient(s). Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please notify the sender immediately by replying to this message and destroy all copies of this message and any attachments. ASML is neither liable for the proper and complete transmission of the information contained in this communication, nor for any delay in its receipt. -- This message has been scanned for viruses and dangerous content by MailScanner , and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 11 Jan 2007 17:08:19 +0100 From: Roberto IZZI Subject: [IBIS-Users] Ibis open drain strange behaviour This is a multi-part message in MIME format. - --------------040003030903090003060701 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Hello everybody I 'd like to have some information about a strange behaviour of Open drain buffer Ibis model. I have noticed a mismatch between Transistor level and Ibis model voltage output during a transient analysis, considering the same buffer. In fact in presence of the same input voltage wave and for a high value of load resistance(for example 20Kohm)connected to power, we can observe a delay between TL output and Ibis output. In the Ibis file, for Open drain, Rise and fall waves tables have been extracted considering the same resistance connected to Power (20Kohm). What is the cause of this strange behaviour? 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-------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 11 Jan 2007 10:14:53 -0600 From: Subject: RE: [IBIS-Users] Ibis open drain strange behaviour Is your only concern the time delay? IBIS and Spice aren't always aligned in time since IBIS doesn't contain the buffer delay. Aubrey Sparkman Enterprise Engineering Signal Integrity Team Dell, Inc. Aubrey_Sparkman@Dell.com (512) 723-3592 The Greatest Pleasure in Life is Doing what People say can't be done... - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Roberto IZZI Sent: Thursday, January 11, 2007 10:08 AM To: ibis@server.eda-stds.org; ibis-users@server.eda.org Subject: [IBIS-Users] Ibis open drain strange behaviour Hello everybody I 'd like to have some information about a strange behaviour of Open drain buffer Ibis model. I have noticed a mismatch between Transistor level and Ibis model voltage output during a transient analysis, considering the same buffer. In fact in presence of the same input voltage wave and for a high value of load resistance(for example 20Kohm)connected to power, we can observe a delay between TL output and Ibis output. In the Ibis file, for Open drain, Rise and fall waves tables have been extracted considering the same resistance connected to Power (20Kohm). What is the cause of this strange behaviour? Thanks and best regards Roberto Izzi - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 12 Jan 2007 09:31:08 +0800 From: "NG,MEI-YEE" Subject: RE: [IBIS-Users] Ibis open drain strange behaviour Hi everybody, I would like to say that I experienced the same phenomenon as Roberto, with the IBIS waveform delayed compared to the transistor level simulation. Aubrey, what do you mean by IBIS model doesn't contain buffer delay? How does that explain IBIS model being delayed in the output response? Appreciate any feedback. Thank you. Best regards, Mei Yee - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Aubrey_Sparkman@dell.com Sent: Friday, January 12, 2007 12:15 AM To: roberto.izzi@st.com; ibis@server.eda-stds.org; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Ibis open drain strange behaviour Is your only concern the time delay? IBIS and Spice aren't always aligned in time since IBIS doesn't contain the buffer delay. Aubrey Sparkman Enterprise Engineering Signal Integrity Team Dell, Inc. Aubrey_Sparkman@Dell.com (512) 723-3592 The Greatest Pleasure in Life is Doing what People say can't be done... - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Roberto IZZI Sent: Thursday, January 11, 2007 10:08 AM To: ibis@server.eda-stds.org; ibis-users@server.eda.org Subject: [IBIS-Users] Ibis open drain strange behaviour Hello everybody I 'd like to have some information about a strange behaviour of Open drain buffer Ibis model. I have noticed a mismatch between Transistor level and Ibis model voltage output during a transient analysis, considering the same buffer. In fact in presence of the same input voltage wave and for a high value of load resistance(for example 20Kohm)connected to power, we can observe a delay between TL output and Ibis output. In the Ibis file, for Open drain, Rise and fall waves tables have been extracted considering the same resistance connected to Power (20Kohm). What is the cause of this strange behaviour? Thanks and best regards Roberto Izzi - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 12 Jan 2007 09:49:55 +0200 From: "Dimitry Eisenshtat" Subject: Re: [IBIS-Users] Ibis open drain strange behaviour Hi all, Mei Yee, if you see the buffer to be modeled as box with some interface (lets speak for example about one directional buffer which has only transmitter, so the interface in simplest case will be data_from_core, enable, pad) - you of course expected from IBIS representation the same (in ideal case) behavioral as the transistor-level simulation with spice, in other words, no delay is expected between both transient responses. But it is the artificial situation, in real life you are looking from board level and you can not synchronize your simulation with signal inside the core aren't you? How you can define for example WHEN the input signal starts the transition - it dependent on unknown digital stage number the signal is walking on before the buffer data_from_core input, isn't it ? As i understand, the delay from enable to pad is meaningless, because actually you can not define absolute time in board-level scope, only the transition itself is important. Another question is - why the delay comes to be, but for example the answer may be the time windowing of V/T tables (I mean the model maker probably shifts the transients response table in order to make the time window smaller, for example). I have to say, I'm circuit designer and I has produced a lot of IBIS models, but has actually no knowledge about using of these models on board level, so I really like to know if I have a mistake. Aubrey, did you mean the same things? Regards, Dmitry NG,MEI-YEE wrote: > Hi everybody, > > I would like to say that I experienced the same phenomenon as Roberto, > with the IBIS waveform delayed compared to the transistor level > simulation. Aubrey, what do you mean by IBIS model doesn't contain > buffer delay? How does that explain IBIS model being delayed in the > output response? > > Appreciate any feedback. Thank you. > > Best regards, > Mei Yee > > -----Original Message----- > From: owner-ibis-users@server.eda.org > [mailto:owner-ibis-users@server.eda.org] On Behalf Of > Aubrey_Sparkman@dell.com > Sent: Friday, January 12, 2007 12:15 AM > To: roberto.izzi@st.com; ibis@server.eda-stds.org; > ibis-users@server.eda.org > Subject: RE: [IBIS-Users] Ibis open drain strange behaviour > > Is your only concern the time delay? IBIS and Spice aren't always > aligned in time since IBIS doesn't contain the buffer delay. > > > Aubrey Sparkman > Enterprise Engineering Signal Integrity Team > Dell, Inc. > Aubrey_Sparkman@Dell.com > (512) 723-3592 > > The Greatest Pleasure in Life is Doing what People say can't be done... > > -----Original Message----- > From: owner-ibis-users@server.eda.org > [mailto:owner-ibis-users@server.eda.org] On Behalf Of Roberto IZZI > Sent: Thursday, January 11, 2007 10:08 AM > To: ibis@server.eda-stds.org; ibis-users@server.eda.org > Subject: [IBIS-Users] Ibis open drain strange behaviour > > Hello everybody > > I 'd like to have some information about a strange behaviour of Open > drain buffer Ibis model. > I have noticed a mismatch between Transistor level and Ibis model > voltage output during a transient analysis, considering the same buffer. > In fact in presence of the same input voltage wave and for a high value > of load resistance(for example 20Kohm)connected to power, we can observe > a delay between TL output and Ibis output. > In the Ibis file, for Open drain, Rise and fall waves tables have been > extracted considering the same resistance connected to Power (20Kohm). > What is the cause of this strange behaviour? > > Thanks and best regards > > Roberto Izzi > > > > -- > This message has been scanned for viruses and dangerous content by > MailScanner, and is believed to be clean. > =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Winbond is strictly prohibited; and any information in this email irrelevant to the official business of Winbond shall be deemed as neither given nor endorsed by Winbond. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 12 Jan 2007 09:15:25 +0100 From: Roberto IZZI Subject: Re: [IBIS] Re: [IBIS-Users] Ibis open drain strange behaviour Hello everybody Thank you very much for your feedback. In my open drain ibis model, I have extracted Rise and fall wave by TX level simulation of buffer (spice) connecting a load resistance value equal to 20K between open drain pad and power. In this case I have considered the real delay between transient of input signal and output. Now if I consider the same input signal (by which I have extracted Rise and Fall tables) for ibis model and the same resistance value (20k), I should have the same behaviour between Ibis and spice buffer. Thanks and best regards. Roberto Izzi Dimitry Eisenshtat wrote: > Hi all, > Mei Yee, if you see the buffer to be modeled as box with some > interface (lets speak for example about one directional buffer which > has only transmitter, so the interface in simplest case will be > data_from_core, enable, pad) - you of course expected from IBIS > representation the same (in ideal case) behavioral as the > transistor-level simulation with spice, in other words, no delay is > expected between both transient responses. But it is the artificial > situation, in real life you are looking from board level and you can > not synchronize your simulation with signal inside the core aren't > you? How you can define for example WHEN the input signal starts the > transition - it dependent on unknown digital stage number the signal > is walking on before the buffer data_from_core input, isn't it ? As i > understand, the delay from enable to pad is meaningless, because > actually you can not define absolute time in board-level scope, only > the transition itself is important. Another question is - why the > delay comes to be, but for example the answer may be the time > windowing of V/T tables (I mean the model maker probably shifts the > transients response table in order to make the time window smaller, > for example). > > I have to say, I'm circuit designer and I has produced a lot of IBIS > models, but has actually no knowledge about using of these models on > board level, so I really like to know if I have a mistake. Aubrey, did > you mean the same things? > > Regards, > Dmitry > > NG,MEI-YEE wrote: > >> Hi everybody, >> I would like to say that I experienced the same phenomenon as Roberto, >> with the IBIS waveform delayed compared to the transistor level >> simulation. Aubrey, what do you mean by IBIS model doesn't contain >> buffer delay? How does that explain IBIS model being delayed in the >> output response? >> >> Appreciate any feedback. Thank you. >> >> Best regards, >> Mei Yee >> >> -----Original Message----- >> From: owner-ibis-users@server.eda.org >> [mailto:owner-ibis-users@server.eda.org] On Behalf Of >> Aubrey_Sparkman@dell.com >> Sent: Friday, January 12, 2007 12:15 AM >> To: roberto.izzi@st.com; ibis@server.eda-stds.org; >> ibis-users@server.eda.org >> Subject: RE: [IBIS-Users] Ibis open drain strange behaviour >> >> Is your only concern the time delay? IBIS and Spice aren't always >> aligned in time since IBIS doesn't contain the buffer delay. >> >> >> Aubrey Sparkman Enterprise Engineering Signal Integrity Team >> Dell, Inc. Aubrey_Sparkman@Dell.com (512) 723-3592 >> >> The Greatest Pleasure in Life is Doing what People say can't be done... >> >> -----Original Message----- >> From: owner-ibis-users@server.eda.org >> [mailto:owner-ibis-users@server.eda.org] On Behalf Of Roberto IZZI >> Sent: Thursday, January 11, 2007 10:08 AM >> To: ibis@server.eda-stds.org; ibis-users@server.eda.org >> Subject: [IBIS-Users] Ibis open drain strange behaviour >> >> Hello everybody >> >> I 'd like to have some information about a strange behaviour of Open >> drain buffer Ibis model. >> I have noticed a mismatch between Transistor level and Ibis model >> voltage output during a transient analysis, considering the same buffer. >> In fact in presence of the same input voltage wave and for a high value >> of load resistance(for example 20Kohm)connected to power, we can observe >> a delay between TL output and Ibis output. In the Ibis file, for Open >> drain, Rise and fall waves tables have been >> extracted considering the same resistance connected to Power (20Kohm). >> What is the cause of this strange behaviour? >> >> Thanks and best regards >> >> Roberto Izzi >> >> >> -- >> This message has been scanned for viruses and dangerous content by >> MailScanner, and is believed to be clean. >> > > > =========================================================================================== > > The privileged confidential information contained in this email is > intended for use only by the addressees as indicated by the original > sender of this email. If you are not the addressee indicated in this > email or are not responsible for delivery of the email to such a > person, please kindly reply to the sender indicating this fact and > delete all copies of it from your computer and network server > immediately. Your cooperation is highly appreciated. It is advised > that any unauthorized use of confidential information of Winbond is > strictly prohibited; and any information in this email irrelevant to > the official business of Winbond shall be deemed as neither given nor > endorsed by Winbond. > - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 12 Jan 2007 09:38:29 +0100 From: Subject: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour This is a multi-part message in MIME format. - ------_=_NextPart_001_01C73625.09EE6EF2 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable Hi Roberto, I am pretty sure that your problem is same that I have discussed on this forum in August 2006 (at least the picture that you attached in your mail looks very similar to the pictures that I attached in my question mail). So, for more information please read the attached mails. Just shortly: trick is in the applied stimuli to IBIS model - your stimuli is too slow - - please find bellow the excerpt out of HSpice SI Guide: "Voltage Thresholds Voltages applied to the input and enable nodes are digital signals. They should be either 0 or 1. You can specify input voltage as: V_in nd_in 0 pulse (0 3.3 0 0.5n 0.5n 4n 8n) However, IC circuit simulation currently detects only two thresholds, 20% and 80% of [0,1] swing, that is, 0.2V and 0.8V. If a buffer is non-inverting and in a LOW state, it starts the transition to a HIGH state, if V_in > 0.8V. If the buffer is in HIGH state, it will start the transition to LOW state, if V_in < 0.2V. Specifying input voltage in the range [0, 3.3V] as in the above example does not make LOW -> HIGH transitions better in any way, but can add uncertainty over the 0.5ns time interval, when the transition actually occurs." - --- end of excerpt So, if you apply very fast stimuli (in ideal case step function) your B-element and HSpice netlist model responses should be the same (or at least edge aligned) - of course, I agree with you, step function doesn't make much physical sense, but that is it, it is one more limitation of IBIS modeling. Regards, Radovan - -----Original Message----- From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf Of Roberto IZZI Sent: Thursday, January 11, 2007 5:08 PM To: ibis@server.eda-stds.org; ibis-users@server.eda.org Subject: [IBIS] Ibis open drain strange behaviour Hello everybody I 'd like to have some information about a strange behaviour of Open drain buffer Ibis model. I have noticed a mismatch between Transistor level and Ibis model voltage output during a transient analysis, considering the same buffer. In fact in presence of the same input voltage wave and for a high value of load resistance(for example 20Kohm)connected to power, we can observe a delay between TL output and Ibis output.=20 In the Ibis file, for Open drain, Rise and fall waves tables have been extracted considering the same resistance connected to Power (20Kohm). What is the cause of this strange behaviour? Thanks and best regards Roberto Izzi =20=20=20=20 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C73625.09EE6EF2 Content-Type: message/rfc822 Content-Transfer-Encoding: 7bit Received: from appmail2.eu.infineon.com ([172.23.30.12]) by mucse306.eu.infineon.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.1830); Mon, 7 Aug 2006 18:14:13 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Received: from mucse315.eu.infineon.com ([172.23.30.15]) by appmail2.eu.infineon.com with Microsoft SMTPSVC(6.0.3790.1830); Mon, 7 Aug 2006 18:14:13 +0200 Received: from smtp2.infineon.com ([172.28.181.199]) by mucse315.eu.infineon.com with InterScan Message Security Suite; Mon, 07 Aug 2006 18:14:12 +0200 Received: from smtp3.stanford.edu ([171.67.20.26]) by smtp2.infineon.com with ESMTP; 07 Aug 2006 18:13:57 +0200 Received: from smtp3.stanford.edu (localhost.localdomain [127.0.0.1]) by localhost (Postfix) with SMTP id 13E6D4CA83; Mon, 7 Aug 2006 09:13:57 -0700 (PDT) Received: from cis.Stanford.EDU (cis.Stanford.EDU [171.64.100.178]) by smtp3.stanford.edu (Postfix) with ESMTP id 5D3C04CAB9; Mon, 7 Aug 2006 09:13:56 -0700 (PDT) Received: from server.eda-stds.org (eda-stds.NET [171.64.101.101]) by cis.Stanford.EDU (Postfix) with ESMTP id 4BE6613E05; Mon, 7 Aug 2006 09:13:55 -0700 (PDT) Received: from server.eda-stds.org (localhost [127.0.0.1]) by server.eda-stds.org (8.12.10/8.12.0.Beta7) with ESMTP id k77GCiDu000870; Mon, 7 Aug 2006 09:12:45 -0700 (PDT) Received: (from majordom@localhost) by server.eda-stds.org (8.12.10/8.12.10/Submit) id k77GCiJ4000869; Mon, 7 Aug 2006 09:12:44 -0700 (PDT) Content-class: urn:content-classes:message Return-Path: X-MimeOLE: Produced By Microsoft Exchange V6.5 X-OriginalArrivalTime: 07 Aug 2006 16:12:39.0614 (UTC) FILETIME=[4E0125E0:01C6BA3C] X-BrightmailFiltered: true X-SBRS: None X-Brightmail-Tracker: AAAAAA== X-Virus-Scanned: ClamAV 0.88/1639/Mon Aug 7 06:34:09 2006 on server.eda-stds.org X-Authentication-Warning: server.eda-stds.org: majordom set sender to owner-ibis-users@eda-stds.org using -f X-MIME-Autoconverted: from quoted-printable to 8bit by server.eda-stds.org id k77GCgDu000866 X-Virus-Status: Clean Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Date: Mon, 7 Aug 2006 17:12:38 +0100 Message-ID: In-Reply-To: <115496700767215259@mail.sigrity.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Thread-Index: Aca3Er4XeA3MXBO9SJCOnWNLrk2bHAAEzttAABD8UQAAp+Vx8AAL98iQAAC1LAA= From: Sender: To: , Hi Sam, many thanks, message understood :-)) Regards, Radovan=20 - -----Original Message----- From: Sam Chitwood [mailto:samchitwood@sigrity.com]=20 Sent: Monday, August 07, 2006 6:10 PM To: Vuletic Radovan (QAG PD PDE MEM); ibis-users@server.eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and= Hspice B-element simulation - bug or feature? Hi Radovan, A 0ps rise time is ok for IBIS because the stimulus signal is simply a trig= ger for the algorithms to start the transitions; there is nothing physical = associated with the stimulus node. However, this is typically not true for= transistor-level models so different stimuli are required. A number of EDA tools (but probably not all) use the 0.2 V and 0.8 V trigge= r points (mainly so that HSPICE decks can be directly used in other tools). This was established a long time ago. The IBIS forum does not commonly dis= cuss 'how' EDA companies should implement capabilities - read the IBIS spec= . on Series MOSFET for an example. :-) A percentage of the voltage rail could have been used for the trigger point= s, but that might require unique stimuli for each rail (and each typ/min/ma= x). The fixed 0.2 and 0.8 scheme allows users to create a database of trig= ger sub-circuits that can be used with any supply voltage. Now that you know how it works, I think you'll find it useful. I hope I've answered some of your questions. Thanks, Sam - -----Original Message----- From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Radovan.Vuletic@= qimonda.com Sent: Monday, August 07, 2006 8:30 AM To: Xuefeng.Chen@synopsys.com; weston.beal@intel.com; ibis-users@server.eda= - -stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and= Hspice B-element simulation - bug or feature? Hi experts, many thanks Weston and Xuefeng for your answers. I have to apologies that i= t wasn't immediately clear in my first mail, but I would never send mail to= this forum if just delaying of stimuli for 30ps would solve my problems.= =20 Problem was, as I wrote in my mail, that in some cases rising edge was show= ing very good overlap between transistor netlist and IBIS, but falling edge= s were shifted - in other cases (with some other stimuli frequencies) falli= ng edges were overlapping but rising edges were delayed - this problem unfo= rtunately can't be solved by simple shifting stimuli. Hint that Xuefeng gav= e was really good (but who really reads such boring stuff as Additional Not= es in HSpice SI Guide?). So just to recapitulate for the other people who c= an see/have the same problem - please find bellow the excerpt out of HSpice= SI Guide: "Voltage Thresholds Voltages applied to the input and enable nodes are digital signals. They sh= ould be either 0 or 1. You can specify input voltage as: V_in nd_in 0 pulse (0 3.3 0 0.5n 0.5n 4n 8n) However, IC circuit simulation= currently detects only two thresholds, 20% and 80% of [0,1] swing, that is= , 0.2V and 0.8V. If a buffer is non-inverting and in a LOW state, it starts= the transition to a HIGH state, if V_in > 0.8V. If the buffer is in HIGH s= tate, it will start the transition to LOW state, if V_in < 0.2V. Specifying input voltage in the range [0, 3.3V] as in the above example does not make = LOW -> HIGH transitions better in any way, but can add uncertainty over the= 0.5ns time interval, when the transition actually occurs." - --- end of excerpt Originaly I used PULSE with 100ps rising/falling time with sweep from 0 to = 1.5V. (and 0.2V and 0.8V are pretty asymmetrical to this range) When I used= PULSE stimuli with 0ps rising and falling waveform and around 10 times fin= er resolution for simulation (.TRAN 1.36e-11 used for IBIS model extractio= n and .TRAN 1ps for simulation (although Xuefeng will say that it is perhap= s not properly to say, since there is dynamic step control) I saw significa= ntly better data-eye diagram and very good overlap between rising and falli= ng edges - Nice! However, that rises a question if 0ps rising/falling wavef= orms are physically justified. Q U E S T I O N : =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Above mentioned problem is kind of missing definition in IBIS models (O.K. not in definition of IBIS, but definitely for usage of IBIS models). Shouldn't be standardized how every tool should approach simulation of IBIS= models with respect to input and enable nodes? I mean 0.2V for low and 0.8= V for high is very strange - I could accept 20% of Vdd and 80% of Vdd, but = to define input thresholds as absolute values, totally independent on techn= ology and supply voltage is somehow user unfriendly (however, in HSpice it = is at least mentioned in some additional note). Furthermore, it seems that = every tool vendor has freedom to treat/process stimuli to input and enable = node as she/he will. That leads to the fact that I can have several differe= nt output waveforms although I am using same model and stimuli - but differ= ent tool!?! I am pretty sure that this topic was already discussed among the people tha= t are using IBIS, but what was the outcome? Is there somebody who is still driving this topics? Is there intention to s= tandardize behavior of inputs to IBIS models? Regards, Radovan - -----Original Message----- From: Xuefeng Chen [mailto:Xuefeng.Chen@synopsys.com] Sent: Friday, August 04, 2006 4:26 AM To: Beal, Weston; Vuletic Radovan (QAG PD PDE MEM); ibis-users@eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and= Hspice B-element simulation - bug or feature? Radovan, Weston's suggestions are very good. In addition, I have two points to mention when using HSPICE=20 1) ".TRAN 1.36e-11 1.36e-09" does not mean exactly the time step is 13.6ps. Dynamic time step control will be used in transient analysis. You can try o= ption DELMAX to set the maximum time step. 2) Input stimulus is dealt with by two voltage thresholds 0.2v and 0.8v whi= ch decides the starting time point of buffer's transition. So it's better t= o set (vhigh+vlow)/2 =3D 0.5 if you use PULSE voltage source as stimulus. Of course, I think the most important thing is the waveform tables as Westo= n mentioned.=20 Best regards Xuefeng - -----Original Message----- From: owner-ibis-users@eda-stds.org [mailto:owner-ibis-users@eda-stds.org] On Behalf Of Beal, Weston Sent: 2006?8?4? 2:04 To: Radovan.Vuletic@qimonda.com; ibis-users@eda-stds.org Subject: RE: [IBIS-Users] Differences between Hspice netlist simulation and= Hspice B-element simulation - bug or feature? Radovan, First, you should not expect the curves to line up in time. The IBIS data d= oes not represent all of the output buffer. Generally, the voltage at the p= in of an IBIS model will transition sooner than the voltage at the pin of a= full transistor-level model. The curves should be the same if you can slid= e one in time to compensate for this time offset. Try delaying the stimulus= to the IBIS model by 30ps. In your pictures I see that the curve shapes are still a little bit off. It's difficult to know what causes this without seeing your simulation file= s. Look at the IBIS rising and falling waveform tables to see if the time e= xtents are close to the actual transition. You want as many time-points as = possible describing the actual transition and not waste them in flat region= s. Different simulators deal with the flat regions at the beginning and end= of the transition in different ways. I hope this helps a bit. Good Luck! Regards, Weston - -----Original Message----- From: owner-ibis-users@server.eda-stds.org [mailto:owner-ibis-users@server.eda-stds.org] On Behalf Of Radovan.Vuletic@= qimonda.com Sent: Thursday, August 03, 2006 8:38 AM To: ibis-users@server.eda-stds.org Subject: [IBIS-Users] Differences between Hspice netlist simulation and Hsp= ice B-element simulation - bug or feature? Hi experts,=20 sorry that I trigger the same topic once again, but now it keeps me busy al= ready more than one week and I am pretty sure that the problem is not a way= how I extract IBIS model, but somewhere else!=20 Before I elaborate the problem let me notice that I get the same result if = I use 2ibis2 or s2ibis3 or if I use HSpice or some company internal analog = simulator for extraction of IBIS model.=20 Let me elaborate the problem:=20 1. IBIS model is generated (say with s2ibis2, but irrelevant, since there i= s a same result with s2ibis3) 2. I take one of spice decks for extracting r= ising waveform generated by extraction tool (say a00DQ40.spi) - this should= be spice deck for generating 1st rising waveform in typical case.=20 This spice deck of course contains the netlist of my circuit.=20 3. I modify this spice deck only that I instantiate in it just generated I= BIS buffer model (in step 1.) as a B-element - in other words, I just put t= here IBIS model - B-element and do nothing else 4. stimuli and load for net= list remains the same and I use exactly the same stimuli and load for IBIS = model as well (of course, netlist, IBIS model and their stimulus and loads = are separated) 5. simulate such modified spice deck with HSpice and compare= the outputs: netlist vs. IBIS model Problem: What I expect to get on output is very good overlap between Hspice simulati= on of netlist and IBIS model, BUT what I get on output is a fact that falli= ng or rising edges don't overlap i.e. there is some 30ps delay (Please take= a look on attached snapshots "zoom1.gif" and "zoom2.gif"). Signal "dq_40_ohm" is output of netlist, signal "io_ron_040_hspice_typ". Yo= u can see a real delay and not some different slopes due to different loads. Transient analysis is done with (.TRAN 1.36e-11 1.36e-09) - i.e. simulation= step (for IBIS extraction) is 13.6ps.=20 What worries me even more is a fact that in some cases (for different stimu= li frequencies) I see that rising edges are overlapping and falling are del= ayed and in some cases (some other frequency of stimuli) I see that falling= edges are overlapping and rising are delayed, so I don't know even where s= hould I cut ("taylor") my V-t curves when behavior seems to be so arbitrar= y and frequency dependant.=20 I know, some of you would say that 20-30ps are no problem, but exactly this= 20-30ps are shifting (upwards or downwards) crossing point of rising and f= alling edges and destroy duty cycle and data eye diagram (target is 800MHz)= . Problem is independent on slope of stimuli (so with 1ps slope or 100ps of= slope of stimuli I see the same result)=20 I know that we should not speak on this forum about tools and vendors and I= terribly apologize that I will still mention some of them - but on the end= all our models are used with some these tools and I think that it is neces= sary that we exchange information about our experiences with this tools as = well. So the problem is analysed with different tools: - - I see above mentioned problem when simulating with HSpice (versions 2004.= 09, 2005.03 and 2006.03) netlist vs. IBIS model - - I see effect of above mentioned problem when simulating with ADS - using = only IBIS model - rising and falling edge crossing points are shifted same= as in HSpice - - with SpecctraQuest (also simulating only with IBIS model) I see the right= results! So I am pretty confused, what is correct? A few different simulators, but o= nly one is showing a right result (or at least result that I consider as a = proper). What is your experience? Have you noticed something similar? Can somebody f= rom you do the same procedure on one of your designs (compare IBIS vs. HSpice on the same way as I done)? Has somebody an idea, proposal? Best regards / Mit freundlichen Gr=FC=DFen / S po=B9tovanjem Radovan Vuletic Qimonda AG QAG PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305=20 E-mail: radovan.vuletic@qimonda.com <> <>=20 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org=20 |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent=20 | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org=20 |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent=20=20 | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - ------_=_NextPart_001_01C73625.09EE6EF2 Content-Type: message/rfc822 Content-Transfer-Encoding: 7bit Received: from appmail2.eu.infineon.com ([172.23.30.12]) by mucse306.eu.infineon.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.1830); Thu, 3 Aug 2006 17:39:49 +0200 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----_=_NextPart_002_01C6B713.0DC65080" Received: from mucse315.eu.infineon.com ([172.23.30.15]) by appmail2.eu.infineon.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 3 Aug 2006 17:39:49 +0200 Received: from smtp2.infineon.com ([172.28.181.199]) by mucse315.eu.infineon.com with InterScan Message Security Suite; Thu, 03 Aug 2006 17:39:48 +0200 Received: from smtp3.stanford.edu ([171.67.20.26]) by smtp2.infineon.com with ESMTP; 03 Aug 2006 17:39:46 +0200 Received: from smtp3.stanford.edu (localhost.localdomain [127.0.0.1]) by localhost (Postfix) with SMTP id 045944BE09; Thu, 3 Aug 2006 08:39:44 -0700 (PDT) Received: from cis.Stanford.EDU (cis.Stanford.EDU [171.64.100.178]) by smtp3.stanford.edu (Postfix) with ESMTP id 95FC34BDF8; Thu, 3 Aug 2006 08:39:43 -0700 (PDT) Received: from server.eda-stds.org (eda-stds.COM [171.64.101.101]) by cis.Stanford.EDU (Postfix) with ESMTP id D1BDA13DF9; Thu, 3 Aug 2006 08:39:41 -0700 (PDT) Received: from server.eda-stds.org (localhost [127.0.0.1]) by server.eda-stds.org (8.12.10/8.12.0.Beta7) with ESMTP id k73FbmDu001726; Thu, 3 Aug 2006 08:37:48 -0700 (PDT) Received: (from majordom@localhost) by server.eda-stds.org (8.12.10/8.12.10/Submit) id k73FbmF6001725; Thu, 3 Aug 2006 08:37:48 -0700 (PDT) Content-class: urn:content-classes:message Return-Path: X-MimeOLE: Produced By Microsoft Exchange V6.5 X-OriginalArrivalTime: 03 Aug 2006 15:37:36.0396 (UTC) FILETIME=[BEBC8CC0:01C6B712] X-BrightmailFiltered: true X-SBRS: None X-Brightmail-Tracker: AAAAAA== X-Virus-Scanned: ClamAV 0.88/1634/Wed Aug 2 15:32:49 2006 on server.eda-stds.org X-Authentication-Warning: server.eda-stds.org: majordom set sender to owner-ibis-users@eda-stds.org using -f X-Virus-Status: Clean Subject: [IBIS-Users] Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Date: Thu, 3 Aug 2006 16:37:35 +0100 Message-ID: X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Thread-Topic: Differences between Hspice netlist simulation and Hspice B-element simulation - bug or feature? Thread-Index: Aca3Er4XeA3MXBO9SJCOnWNLrk2bHA== From: Sender: To: This is a multi-part message in MIME format. - ------_=_NextPart_002_01C6B713.0DC65080 Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Hi experts,=20 sorry that I trigger the same topic once again, but now it keeps me busy al= ready more than one week and I am pretty sure that the problem is not a way= how I extract IBIS model, but somewhere else!=20 Before I elaborate the problem let me notice that I get the same result if = I use 2ibis2 or s2ibis3 or if I use HSpice or some company internal analog = simulator for extraction of IBIS model.=20 Let me elaborate the problem:=20 1. IBIS model is generated (say with s2ibis2, but irrelevant, since there i= s a same result with s2ibis3)=20 2. I take one of spice decks for extracting rising waveform generated by ex= traction tool (say a00DQ40.spi) - this should be spice deck for generating = 1st rising waveform in typical case.=20 This spice deck of course contains the netlist of my circuit.=20 3. I modify this spice deck only that I instantiate in it just generated I= BIS buffer model (in step 1.) as a B-element - in other words, I just put t= here IBIS model - B-element and do nothing else 4. stimuli and load for netlist remains the same and I use exactly the same= stimuli and load for IBIS model as well (of course, netlist, IBIS model an= d their stimulus and loads are separated) 5. simulate such modified spice deck with HSpice and compare the outputs: n= etlist vs. IBIS model Problem: What I expect to get on output is very good overlap between Hspice simulati= on of netlist and IBIS model, BUT what I get on output is a fact that falli= ng or rising edges don't overlap i.e. there is some 30ps delay (Please take= a look on attached snapshots "zoom1.gif" and "zoom2.gif"). Signal "dq_40_o= hm" is output of netlist, signal "io_ron_040_hspice_typ". You can see a rea= l delay and not some different slopes due to different loads. Transient analysis is done with (.TRAN 1.36e-11 1.36e-09) - i.e. simulation= step (for IBIS extraction) is 13.6ps.=20 What worries me even more is a fact that in some cases (for different stimu= li frequencies) I see that rising edges are overlapping and falling are del= ayed and in some cases (some other frequency of stimuli) I see that falling= edges are overlapping and rising are delayed, so I don't know even where s= hould I cut ("taylor") my V-t curves when behavior seems to be so arbitrar= y and frequency dependant.=20 I know, some of you would say that 20-30ps are no problem, but exactly this= 20-30ps are shifting (upwards or downwards) crossing point of rising and f= alling edges and destroy duty cycle and data eye diagram (target is 800MHz)= . Problem is independent on slope of stimuli (so with 1ps slope or 100ps of= slope of stimuli I see the same result)=20 I know that we should not speak on this forum about tools and vendors and I= terribly apologize that I will still mention some of them - but on the end= all our models are used with some these tools and I think that it is neces= sary that we exchange information about our experiences with this tools as = well. So the problem is analysed with different tools: - - I see above mentioned problem when simulating with HSpice (versions 2004.= 09, 2005.03 and 2006.03) netlist vs. IBIS model - - I see effect of above mentioned problem when simulating with ADS - using = only IBIS model - rising and falling edge crossing points are shifted same= as in HSpice - - with SpecctraQuest (also simulating only with IBIS model) I see the right= results! So I am pretty confused, what is correct? A few different simulators, but o= nly one is showing a right result (or at least result that I consider as a = proper). What is your experience? Have you noticed something similar? Can somebody f= rom you do the same procedure on one of your designs (compare IBIS vs. HSpi= ce on the same way as I done)? Has somebody an idea, proposal? Best regards / Mit freundlichen Gr=FC=DFen / S po=B9tovanjem Radovan Vuleti=E6 Qimonda AG QAG PD PDE MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 234 20108 Fax (PC): +49 (0)89 234 955 5305=20 E-mail: radovan.vuletic@qimonda.com <> <>=20 - ------_=_NextPart_002_01C6B713.0DC65080 Content-Type: image/gif; name="zoom2.gif" Content-Transfer-Encoding: base64 Content-Description: zoom2.gif Content-Disposition: attachment; filename="zoom2.gif" R0lGODdh/QPRAvcAAAAAAAAA/wBVgACAAACqgAD/AAD//yQkJCZMvysAAC1b 5S3lWzv6NED/z0lJSUxMTFD/v1FR+1UAAFVVAFVVgFWqgFWq/1clO2D/r2Zm ZmiCim1tbXp0gn8AAH9/f4mg5Y8AAJKSkpmZmZ8AAKct5aoAAKpVAKpVgKqq gKqqqqqq/63Y5q8AALJNerKysre/Jrflwbflwr8AAMaM58vB2MzMzM8AANyt wtzlLd7e3t//MOPlt+UtLeWxLeW3t+bm/+eMjOe1Ke//IPP///oTQP8AAP8A //8wAP9AAP9QAP9VgP9gAP9wAP+AAP+PAP+fAP+qAP+qgP+vAP+/AP/PAP/f AP//AP///wAZvv8NyQDouAwABOcA/NADlACuAACyAADDAAHdAOMGAAAZAABH AAM4ABMAGewAJwAJcAC+AAHLACNgABcAGSAATQAAxBcAACAAAAAABGgAvgAA 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http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 12 Jan 2007 10:07:23 -0600 From: Subject: RE: [IBIS] Re: [IBIS-Users] Ibis open drain strange behaviour Dmitry, I think you said it correctly. Roberto, If the additional delay bothers you, you could remove some of the early, non-changing data points from the IBIS data. On the other hand, it's not necessary and it makes people ask questions, think, and learn..... Aubrey Sparkman Enterprise Engineering Signal Integrity Team Dell, Inc. Aubrey_Sparkman@Dell.com (512) 723-3592 The Greatest Pleasure in Life is Doing what People say can't be done... - -----Original Message----- From: Roberto IZZI [mailto:roberto.izzi@st.com] Sent: Friday, January 12, 2007 2:15 AM To: Dimitry Eisenshtat Cc: NG,MEI-YEE; ibis@server.eda-stds.org; ibis-users@server.eda.org; Sparkman, Aubrey Subject: Re: [IBIS] Re: [IBIS-Users] Ibis open drain strange behaviour Hello everybody Thank you very much for your feedback. In my open drain ibis model, I have extracted Rise and fall wave by TX level simulation of buffer (spice) connecting a load resistance value equal to 20K between open drain pad and power. In this case I have considered the real delay between transient of input signal and output. Now if I consider the same input signal (by which I have extracted Rise and Fall tables) for ibis model and the same resistance value (20k), I should have the same behaviour between Ibis and spice buffer. Thanks and best regards. Roberto Izzi Dimitry Eisenshtat wrote: > Hi all, > Mei Yee, if you see the buffer to be modeled as box with some > interface (lets speak for example about one directional buffer which > has only transmitter, so the interface in simplest case will be > data_from_core, enable, pad) - you of course expected from IBIS > representation the same (in ideal case) behavioral as the > transistor-level simulation with spice, in other words, no delay is > expected between both transient responses. But it is the artificial > situation, in real life you are looking from board level and you can > not synchronize your simulation with signal inside the core aren't > you? How you can define for example WHEN the input signal starts the > transition - it dependent on unknown digital stage number the signal > is walking on before the buffer data_from_core input, isn't it ? As i > understand, the delay from enable to pad is meaningless, because > actually you can not define absolute time in board-level scope, only > the transition itself is important. Another question is - why the > delay comes to be, but for example the answer may be the time > windowing of V/T tables (I mean the model maker probably shifts the > transients response table in order to make the time window smaller, > for example). > > I have to say, I'm circuit designer and I has produced a lot of IBIS > models, but has actually no knowledge about using of these models on > board level, so I really like to know if I have a mistake. Aubrey, did > you mean the same things? > > Regards, > Dmitry > > NG,MEI-YEE wrote: > >> Hi everybody, >> I would like to say that I experienced the same phenomenon as >> Roberto, with the IBIS waveform delayed compared to the transistor >> level simulation. Aubrey, what do you mean by IBIS model doesn't >> contain buffer delay? How does that explain IBIS model being delayed >> in the output response? >> >> Appreciate any feedback. Thank you. >> >> Best regards, >> Mei Yee >> >> -----Original Message----- >> From: owner-ibis-users@server.eda.org >> [mailto:owner-ibis-users@server.eda.org] On Behalf Of >> Aubrey_Sparkman@dell.com >> Sent: Friday, January 12, 2007 12:15 AM >> To: roberto.izzi@st.com; ibis@server.eda-stds.org; >> ibis-users@server.eda.org >> Subject: RE: [IBIS-Users] Ibis open drain strange behaviour >> >> Is your only concern the time delay? IBIS and Spice aren't always >> aligned in time since IBIS doesn't contain the buffer delay. >> >> >> Aubrey Sparkman Enterprise Engineering Signal Integrity Team Dell, >> Inc. Aubrey_Sparkman@Dell.com (512) 723-3592 >> >> The Greatest Pleasure in Life is Doing what People say can't be done... >> >> -----Original Message----- >> From: owner-ibis-users@server.eda.org >> [mailto:owner-ibis-users@server.eda.org] On Behalf Of Roberto IZZI >> Sent: Thursday, January 11, 2007 10:08 AM >> To: ibis@server.eda-stds.org; ibis-users@server.eda.org >> Subject: [IBIS-Users] Ibis open drain strange behaviour >> >> Hello everybody >> >> I 'd like to have some information about a strange behaviour of Open >> drain buffer Ibis model. >> I have noticed a mismatch between Transistor level and Ibis model >> voltage output during a transient analysis, considering the same buffer. >> In fact in presence of the same input voltage wave and for a high >> value of load resistance(for example 20Kohm)connected to power, we >> can observe a delay between TL output and Ibis output. In the Ibis >> file, for Open drain, Rise and fall waves tables have been extracted >> considering the same resistance connected to Power (20Kohm). >> What is the cause of this strange behaviour? >> >> Thanks and best regards >> >> Roberto Izzi >> >> >> -- >> This message has been scanned for viruses and dangerous content by >> MailScanner, and is believed to be clean. >> > > > ====================================================================== > ===================== > > The privileged confidential information contained in this email is > intended for use only by the addressees as indicated by the original > sender of this email. If you are not the addressee indicated in this > email or are not responsible for delivery of the email to such a > person, please kindly reply to the sender indicating this fact and > delete all copies of it from your computer and network server > immediately. Your cooperation is highly appreciated. It is advised > that any unauthorized use of confidential information of Winbond is > strictly prohibited; and any information in this email irrelevant to > the official business of Winbond shall be deemed as neither given nor > endorsed by Winbond. > - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 12 Jan 2007 13:30:50 -0500 From: "Todd Westerhoff" Subject: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Radovan, I believe the qualifications to time correlation between HSpice and IBIS are - - not necessarily, and yes, if. Time 0 is an IBIS simulation is not guaranteed to have any special significance. You'd like to think that you could simulate your transistor and IBIS model side by side into the same load and expect them to line up, but there is no part of the spec that guarantees this. The IBIS waveform and the HSpice waveform will match in rise/fall time and shape, but they are not guaranteed to align in time. Time 0 is an IBIS model is arbitrary, which is one of the reasons why "buffer delay" simulations are used to normalize the simulated interconnect delays (flight times) to the component timing specifications - this is where Vref, Rref and Cref come from. IF the person creating the IBIS model uses a particular ramp rate at the HSpice model input, and IF the model creator uses the simulated HSpice waveform in the IBIS model without trimming it, and IF the IBIS simulator uses a similar ramp rate to stimulate the IBIS model with comparable triggering thresholds, then - yes, the transistor and IBIS simulations will line up in time. In practice, this occurs pretty often - but it's important to understand why. Most IBIS extraction software takes the simulated waveform from HSpice and puts it into the IBIS model unaltered (i.e. the IBIS output waveform does not start rising at time 0, it includes the "intrinsic" delay of the output buffer). As you pointed out, the ramp rate of the input to the buffer (in both the HSpice and IBIS simulations) is usually very fast compared to the ramp rate of the output. Thus, even if the input ramp rates or triggering thresholds are somewhat mismatched, the difference gets swamped by the much slower output ramp rate (and the simulations line up, or appear to). You need a significant mismatch in the stimulus rates to see a difference. However, one gets into trouble when the intrinsic delay of the output buffer approaches the device's data rate. The output may not finish "switching" in the IBIS curve before the next data bit is triggered. This particular behavior is problematic - the IBIS spec (last I looked) had no specific recommendation on how simulators should handle "overclocking", and different simulators handle this different ways. This is a big problem for semiconductor suppliers, as their models can have different behavior in different tools. The solution? Well, the IBIS spec does not guarantee that time 0 is when the input to the output buffer switches. Time 0 in an IBIS simulation is arbitrary. So, the model creators trim the "dead time" off the front end of the rising and falling V-T curves to ensure the outputs stabilize before the end of the data unit interval, and the time correlation to HSpice is lost. There are specific restrictions on how the dead time may be trimmed, which is a longer discussion. Point is, time correlation between IBIS and HSpice is not guaranteed. It happens frequently, but only as a consequence of the model building process. Dimitry was correct to point out that time 0 in HSpice is often arbitrary in itself - if we're dealing with a component with a clock-to-output spec, then we really have no idea when the output buffer in the device gets triggered with respect to the device's external clock pin anyway. Hope that helps, or was at least coherent ... Todd. Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@sisoft.com www.sisoft.com - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 12 Jan 2007 21:53:15 -0800 From: "Syed Huq \(shuq\)" Subject: [IBIS-Users] DesignCon 2007: 4th call for papers - IBIS Summit This is a multi-part message in MIME format. - ------_=_NextPart_001_01C736D7.1F1B5B22 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable To All: =20 This is the fourth Announcement for the DesignCon 2007 IBIS Summit Meeting held in Santa Clara, California. The program is nearly full and the agenda will be issued one week before the meeting. =20 For those who have not done so, we strongly recommend that you register for the DesignCon exhibition and, if possible the conference. Helpful links are given below. =20 =20 Best Regards, Syed =20 - ----------------------------------------------------------------------- IBIS SUMMIT FOURTH CALL FOR PARTICIPATION & PRESENTATIONS - ----------------------------------------------------------------------- =20 =20 I B I S S U M M I T M E E T I N G =20 Time/Date: Thursday, February 1, 2007 8:00 AM to 5:00 PM =20 http://www.designcon.com/2007/conference/co-located_ibis.html =20 Location: Hyatt Regency Santa Clara (Connected to the Santa Clara Convention Center) 5101 Great America Parkway, Santa Clara, California, USA Tel: +1-408-200-1234 =20 Content: Presentations and Discussions =20 Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. =20 Sponsors: Cisco Systems, International Engineering Consortium (DesignCon) =20 We are seeking more co-sponsors. Please contact Syed Huq . The Benefits to sponsors include recognition at the meeting and acknowledgement in the Calls for Papers and meeting minutes. =20 Your financial support strengthens the organization by allowing IBIS to focus resources on industry activities rather than raising money, and you will receive generous thanks for your support. =20 DesignCon 2007 Conference: =20 January 29 - February 1, 2007 Santa Clara Convention Center Santa Clara, CA =20 Exhibit registration is Free if you register before January 26, 2007 =20=20=20=20=20=20=20=20=20=20=20 http://www.designcon.com/2007/ http://www.designcon.com/2007/pdfs/dc07_catalog.pdf http://www.designcon.com/2007/registration/ =20=20=20=20 Conference Schedule: =20 http://www.designcon.com/2007/conference/schedule.html =20 BACKGROUND =20 DesignCon is the premier annual Silicon Valley event for the electronic design automation (EDA) and semiconductor industry. Topics of current interest to the EIA IBIS Open Forum are addressed at DesignCon. =20 This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. Any pending formal decisions (votes) will be announced at least two weeks prior to the meeting. =20 =20 CALL FOR PARTICIPANTS =20 People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: =20 Name: E-mail address: Company: Telephone: =20 Send to: =20 Syed Huq =20 Registration deadline is Wednesday, January 24, 2007 to receive the free lunch. =20 =20 CALL FOR PRESENTATIONS =20 We are seeking presentations from individuals who have experiences of interest to the IBIS modeling community. In the past, these have included, but not limited to: =20 Demonstrations of modeling techniques Explanations of behavioral algorithms Descriptions of difficulties encountered Model correlation Modeling building experiences Comparisons to other modeling methods New technologies for modeling buffers and component New technologies for modeling packaging and interconnect Etc. =20 Presentations may be addressed to any and all levels of IBIS experience, from beginning to advanced. =20 Presentation Format: =20 A conference laptop with LCD projection. Power Point or Acrobat electronic formats are favored and will pre-loaded on the Windows-based meeting laptop prior to the meeting. =20 Time: Usually 15-30 Minutes =20 Electronic Archival: =20 Presentations will be archived under the IBIS Summits site and also must be submitted in time for uploading and copying. Final submission deadline is: =20 Wednesday, January 24, 2007 =20 Otherwise, you should bring 50 copies. =20 If you plan a presentation, please supply the following information as soon as possible: =20 Tentative Title: Presenter: E-mail address: Company: Telephone: =20 Estimated Time: =20 Send to: =20 Bob Ross =20 AGENDA =20 The agenda includes presentations, discussions, breaks, and a FREE lunch. The agenda details will be developed as proposals are received. So far we tentatively have: =20 "IBIS Roadmap Update" "IBIS Modeling of USB Buffers" "Effects of IBIS Waveform Alignment on Simulation" "VT Initial Delay Issue" "Improving IBIS Algorithms" "Quality Committee Activities" "DFE Modeling using IBISv4.2/VHDL-AMS" "Advanced Technology Modeling Committee Update" "Power Delivery Analysis with IBIS 4.2" =20 LIST OF NEARBY HOTELS =20 The Hotel and Travel Link provides a conference hotel discount, and use internet search engines other good lodging deals: =20 http://www.designcon.com/2007/conference/hotel_and_travel.html =20 - ----------------------------------------------------------------- =20 =20 =20 =20 =20 =20 =20 =20 =20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C736D7.1F1B5B22 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
To All:
 
This is the fourth= =20 Announcement for the DesignCon 2007 IBIS Summit
Meeting held in Santa Cl= ara,=20 California.  The program is nearly
full and the agenda will be issu= ed=20 one week before the meeting.
 
For those who have not done so, we stron= gly=20 recommend that you
register for the DesignCon exhibition and, if possibl= e=20 the
conference.  Helpful links are given below.
 
 
Best=20 Regards,
Syed
 
---------------------------------------------= - --------------------------
       &nb= sp;            =          =20 IBIS=20 SUMMIT
           = ;            &n= bsp;   =20 FOURTH CALL=20 FOR
           &n= bsp;        =20 PARTICIPATION &=20 PRESENTATIONS
----------------------------------------------------------= - -------------
 
 
           =   =20 I B I S   S U M M I T   M E E T I N=20 G
 
Time/Date:  Thursday, February 1, 2007 8:00 AM to 5:00= =20 PM
            http= ://www.designcon.com/2007/conference/co-located_ibis.html
 
= Location:  =20 Hyatt Regency Santa=20 Clara
           =   =20 (Connected to the Santa Clara Convention=20 Center)
          &nbs= p;=20 5101 Great America=20 Parkway,
          &nb= sp;=20 Santa Clara, California,=20 USA
            T= el:=20 +1-408-200-1234
 
Content:    Presentations and= =20 Discussions
 
Purpose:    Solicit and Exchange IB= IS=20 Model Related Information=20 and
           = =20 Ideas.
 
Sponsors:   Cisco Systems, International=20 Engineering Consortium=20 (DesignCon)
 
        &n= bsp;  =20 We are seeking more co-sponsors.  Please contact Syed=20 Huq
            &= lt;shuq@cisco.com>.  The Benefits t= o=20 sponsors=20 include
          &nbs= p;=20 recognition at the meeting and acknowledgement in the=20 Calls
           = for=20 Papers and meeting=20 minutes.
 
         = ;  =20 Your financial support strengthens the organization=20 by
           =20 allowing IBIS to focus resources on industry=20 activities
          &= nbsp;=20 rather than raising money, and you will receive=20 generous
          &nb= sp;=20 thanks for your support.
 
DesignCon 2007=20 Conference:
 
        &n= bsp;  =20 January 29 - February 1,=20 2007
            = Santa=20 Clara Convention=20 Center
           = ;=20 Santa Clara,=20 CA
 
          = ; =20 Exhibit registration is Free if you register=20 before
           = ;=20 January 26, 2007
         &= nbsp;=20
            = ; =20 http://www.designcon.com/2007/<= BR>            =  =20 http://www.des= igncon.com/2007/pdfs/dc07_catalog.pdf
     =         =20 http://www.designcon.c= om/2007/registration/
   =20
           =20 Conference=20 Schedule:
 
        &nbs= p;    =20 http://www.= designcon.com/2007/conference/schedule.html
 

BACKGROUND
 
DesignCon is the premier annual Silicon Va= lley=20 event for the electronic
design automation (EDA) and semiconductor=20 industry.  Topics of current
interest to the EIA IBIS Open Forum ar= e=20 addressed at DesignCon.
 
This meeting will be conducted as a fo= rmal=20 IBIS Summit Meeting.
Presentations are expected to be available and arch= ived=20 in an electronic
format, and minutes of the meeting will be issued. Any= =20 pending formal
decisions (votes) will be announced at least two weeks pr= ior=20 to the
meeting.
 
 
CALL FOR PARTICIPANTS
 
People involved in IBIS Model=20 development, EDA tool development, and
digital circuit design are invite= d to=20 participate in the Summit meeting.
If you plan to participate, please=20 register with the information below:
 
  =20 Name:
   E-mail address:
   Company:
 &nb= sp;=20 Telephone:
 
Send to:
 
   Syed Huq <shuq@cisco.com>
 
Registra= tion=20 deadline is Wednesday, January 24, 2007 to receive the
free=20 lunch.
 
 
CALL FOR PRESENTATIONS
 
We are se= eking=20 presentations from individuals who have experiences
of interest to the I= BIS=20 modeling community.  In the past, these have
included, but not limi= ted=20 to:
 
   Demonstrations of modeling=20 techniques
   Explanations of behavioral algorithms
 &= nbsp;=20 Descriptions of difficulties encountered
   Model=20 correlation
   Modeling building experiences
  = =20 Comparisons to other modeling methods
   New technologies for= =20 modeling buffers and component
   New technologies for modelin= g=20 packaging and interconnect
   Etc.
 
Presentations = may=20 be addressed to any and all levels of IBIS experience,
from beginning to= =20 advanced.
 
Presentation Format:
 
   A=20 conference laptop with LCD projection.  Power Point or=20 Acrobat
   electronic formats are favored and will pre-loaded = on=20 the
   Windows-based meeting laptop prior to the=20 meeting.
 
Time: Usually 15-30 Minutes
 
Electronic= =20 Archival:
 
   Presentations will be archived under th= e=20 IBIS Summits site
   and also must be submitted in time for=20 uploading and copying.
   Final submission deadline=20 is:
 
     Wednesday, January 24,=20 2007
 
   Otherwise, you should bring 50=20 copies.
 
If you plan a presentation, please supply the followin= g=20 information
as soon as possible:
 
   Tentative=20 Title:
   Presenter:
   E-mail=20 address:
   Company:
  =20 Telephone:
 
   Estimated Time:
 
Send=20 to:
 
   Bob Ross <bob@teraspeed.com>
 
AG= ENDA
 
The=20 agenda includes presentations, discussions, breaks, and a FREE
lunch.&nb= sp;=20 The agenda details will be developed as proposals are
received.  So= far=20 we tentatively have:
 
  "IBIS Roadmap Update"
  "IBIS Modeling of USB=20 Buffers"
  "Effects of IBIS Waveform Alignment on Simulation"
&n= bsp;=20 "VT Initial Delay Issue"
  "Improving IBIS Algorithms"
 =20 "Quality Committee Activities"
  "DFE Modeling using=20 IBISv4.2/VHDL-AMS"
  "Advanced Technology Modeling Committee=20 Update"
  "Power Delivery Analysis with IBIS 4.2"
 
LIST= OF=20 NEARBY HOTELS
 
The Hotel and Travel Link provides a conference = hotel=20 discount, and
use internet search engines other good lodging=20 deals:
 
   htt= p://www.designcon.com/2007/conference/hotel_and_travel.html
 -----------------------------------------------------------------
&nbs= p;
 
 
 
 
 
 
 
 

--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------_=_NextPart_001_01C736D7.1F1B5B22-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #93 ************************