From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #94 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Thursday, January 25 2007 Volume 01 : Number 094 ---------------------------------------------------------------------- Date: Sat, 13 Jan 2007 10:57:40 +0200 From: "Dimitry Eisenshtat" Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Todd, ok, we understand that time correlation between IBIS and HSpice is not guaranteed, but is it really problem? I mean, in the most often situation there is no place for such comparison at all, because you have only IBIS model, no spice netlist is available. This is the first reason for making IBIS (if simulator speed is not an issue), is it right? Lets say, I'm with semiconductor vendor side, I have the netlist of the buffer, I make the IBIS model based on spice simulations, not lab measurements, so on final step when the model is ready I like to check it vs. original spice behavioral. This is the only situation I agree the comparison is important. But in such case there is no REAL problem - I know exactly about the delay, and if it is the only difference between the IBIS & spice - I don't care. I want ask you about IBIS simulator aspect of the point we are talking about. Look, I find in "Cookbook for ver4" strongly recommendation to trim IBIS model time tables at least to half of max buffer frequency period. (http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf page 70, 5.4.2 V-T Table Windowing). Can you please prefer from simulator software side - is it really problem for the simulator if the time table window is more then such time interval? And one additional point, you wrote "There are specific restrictions on how the dead time may be trimmed, which is a longer discussion" - right now I writes perl script which will trim tables in order to leave only transition region and decrease the time window as the Cookbook recommends to do. So, can you please explain about these restrictions? Thanks, Dmitry Todd Westerhoff wrote: > Radovan, > > I believe the qualifications to time correlation between HSpice and IBIS are > - not necessarily, and yes, if. > > Time 0 is an IBIS simulation is not guaranteed to have any special > significance. You'd like to think that you could simulate your transistor > and IBIS model side by side into the same load and expect them to line up, > but there is no part of the spec that guarantees this. The IBIS waveform > and the HSpice waveform will match in rise/fall time and shape, but they are > not guaranteed to align in time. > > Time 0 is an IBIS model is arbitrary, which is one of the reasons why > "buffer delay" simulations are used to normalize the simulated interconnect > delays (flight times) to the component timing specifications - this is where > Vref, Rref and Cref come from. > > IF the person creating the IBIS model uses a particular ramp rate at the > HSpice model input, and IF the model creator uses the simulated HSpice > waveform in the IBIS model without trimming it, and IF the IBIS simulator > uses a similar ramp rate to stimulate the IBIS model with comparable > triggering thresholds, then - yes, the transistor and IBIS simulations will > line up in time. In practice, this occurs pretty often - but it's important > to understand why. > > Most IBIS extraction software takes the simulated waveform from HSpice and > puts it into the IBIS model unaltered (i.e. the IBIS output waveform does > not start rising at time 0, it includes the "intrinsic" delay of the output > buffer). As you pointed out, the ramp rate of the input to the buffer (in > both the HSpice and IBIS simulations) is usually very fast compared to the > ramp rate of the output. Thus, even if the input ramp rates or triggering > thresholds are somewhat mismatched, the difference gets swamped by the much > slower output ramp rate (and the simulations line up, or appear to). You > need a significant mismatch in the stimulus rates to see a difference. > > However, one gets into trouble when the intrinsic delay of the output buffer > approaches the device's data rate. The output may not finish "switching" in > the IBIS curve before the next data bit is triggered. This particular > behavior is problematic - the IBIS spec (last I looked) had no specific > recommendation on how simulators should handle "overclocking", and different > simulators handle this different ways. This is a big problem for > semiconductor suppliers, as their models can have different behavior in > different tools. > > The solution? Well, the IBIS spec does not guarantee that time 0 is when > the input to the output buffer switches. Time 0 in an IBIS simulation is > arbitrary. So, the model creators trim the "dead time" off the front end of > the rising and falling V-T curves to ensure the outputs stabilize before the > end of the data unit interval, and the time correlation to HSpice is lost. > There are specific restrictions on how the dead time may be trimmed, which > is a longer discussion. > > Point is, time correlation between IBIS and HSpice is not guaranteed. It > happens frequently, but only as a consequence of the model building process. > Dimitry was correct to point out that time 0 in HSpice is often arbitrary in > itself - if we're dealing with a component with a clock-to-output spec, then > we really have no idea when the output buffer in the device gets triggered > with respect to the device's external clock pin anyway. > > Hope that helps, or was at least coherent ... > > Todd. > > Todd Westerhoff > VP, Software Products > SiSoft > 6 Clock Tower Place, Suite 250 > Maynard, MA 01754 > (978) 461-0449 x24 > twesterh@sisoft.com > www.sisoft.com > > > > =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Winbond is strictly prohibited; and any information in this email irrelevant to the official business of Winbond shall be deemed as neither given nor endorsed by Winbond. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 15 Jan 2007 10:10:41 +0100 From: Subject: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Hi Tod, I believe that you have started/mentioned now 2 different topics, that according to my opinion should be separated: 1.) correlation between HSpice and IBIS models and 2.) "overclocking of IBIS models" as some prefer to call it or "frequency dependant IBIS models" (sounds very funny) as others prefer to call it. About correlation between HSpice and IBIS models: - - I absolutely agree with you that if one knows what is he/she doing comparison between HSpice and IBIS is not necessary. - - Zero time point is for IBIS not strictly defined, IBIS model creator can/should/must cut rising/falling waveforms to get "frequently independent models" But, if one still wants to compare simulation outputs of Spice netlist and unchanged IBIS model (generated out of very same Spice netlist) there will be a difference (time shift) in result that is independent on "buffer delay" due to using of stimuli by IBIS simulation tool (once again I limit my discussion only on HSpice, but I think most of the people are using HSpice) - for me one year ago this was unexpected and I believe that this was original question of Dimitry as well. Reason is, as mentioned in my previous mail, that as soon as a stimuli is applied on Spice netlist something "happens" immediately (at least in HSpice) and as soon as transistors has reached their thresholds, internal capacitances are filled out, etc. that can be seen in waveform. For IBIS output model, if you applying for example rising transition, nothing will change until stimuli on input reaches 0.8V, just than starts "buffer delay". For slow stimuli this effect is more obvious than for fast stimuli - if one applies step function (physically not justified, but still) this effect disappears. As you said about "overclocking of IBIS models" it could be discussed very, very long ... Regards, Radovan - -----Original Message----- From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf Of Todd Westerhoff Sent: Friday, January 12, 2007 7:31 PM To: ibis@server.eda-stds.org; ibis-users@server.eda.org Subject: RE: [IBIS] Ibis open drain strange behaviour Radovan, I believe the qualifications to time correlation between HSpice and IBIS are - - not necessarily, and yes, if. Time 0 is an IBIS simulation is not guaranteed to have any special significance. You'd like to think that you could simulate your transistor and IBIS model side by side into the same load and expect them to line up, but there is no part of the spec that guarantees this. The IBIS waveform and the HSpice waveform will match in rise/fall time and shape, but they are not guaranteed to align in time. Time 0 is an IBIS model is arbitrary, which is one of the reasons why "buffer delay" simulations are used to normalize the simulated interconnect delays (flight times) to the component timing specifications - this is where Vref, Rref and Cref come from. IF the person creating the IBIS model uses a particular ramp rate at the HSpice model input, and IF the model creator uses the simulated HSpice waveform in the IBIS model without trimming it, and IF the IBIS simulator uses a similar ramp rate to stimulate the IBIS model with comparable triggering thresholds, then - yes, the transistor and IBIS simulations will line up in time. In practice, this occurs pretty often - - but it's important to understand why. Most IBIS extraction software takes the simulated waveform from HSpice and puts it into the IBIS model unaltered (i.e. the IBIS output waveform does not start rising at time 0, it includes the "intrinsic" delay of the output buffer). As you pointed out, the ramp rate of the input to the buffer (in both the HSpice and IBIS simulations) is usually very fast compared to the ramp rate of the output. Thus, even if the input ramp rates or triggering thresholds are somewhat mismatched, the difference gets swamped by the much slower output ramp rate (and the simulations line up, or appear to). You need a significant mismatch in the stimulus rates to see a difference. However, one gets into trouble when the intrinsic delay of the output buffer approaches the device's data rate. The output may not finish "switching" in the IBIS curve before the next data bit is triggered. This particular behavior is problematic - the IBIS spec (last I looked) had no specific recommendation on how simulators should handle "overclocking", and different simulators handle this different ways. This is a big problem for semiconductor suppliers, as their models can have different behavior in different tools. The solution? Well, the IBIS spec does not guarantee that time 0 is when the input to the output buffer switches. Time 0 in an IBIS simulation is arbitrary. So, the model creators trim the "dead time" off the front end of the rising and falling V-T curves to ensure the outputs stabilize before the end of the data unit interval, and the time correlation to HSpice is lost. There are specific restrictions on how the dead time may be trimmed, which is a longer discussion. Point is, time correlation between IBIS and HSpice is not guaranteed. It happens frequently, but only as a consequence of the model building process. Dimitry was correct to point out that time 0 in HSpice is often arbitrary in itself - if we're dealing with a component with a clock-to-output spec, then we really have no idea when the output buffer in the device gets triggered with respect to the device's external clock pin anyway. Hope that helps, or was at least coherent ... Todd. Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@sisoft.com www.sisoft.com - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 15 Jan 2007 10:16:13 -0500 From: "Todd Westerhoff" Subject: RE: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Sorry for the delay in reply - I took the weekend off ;-) As far as non-time correlation between IBIS and transistor models goes - no, it isn't a problem at all. It's just important that people understand what a model represents and what it doesn't, so that they can draw the right conclusions from their simulations. I was just re-iterating one of my favorite points with "time 0 in an IBIS model is arbitrary". To your point, it's worth noting that time 0 in a spice model-based simulation is often arbitrary as well. A spice model represents only the output buffer at most, so if you're analyzing a device with a clock-to-out timing specification, you still need to figure out how to combine the delays measured in simulation with the timing spec for the device. I think people often ascribe too much credibility to spice models. The model you receive is a function of how the netlist and parasitics for the buffer were extracted - it's far too easy to become confused about what part of the overall device the spice model represents. As to page 70 of the IBIS cookbook - I agree with what it says. That particular page is assuming a DDR device, so that a 100 MHz clock yields 200M transfers/sec, each with a 5 ns UI. Let's suppose you have a model with a 6ns rising V-T curve for this case. The simulator will trigger the curve, begin sweeping the output, and then get retriggered at the 5ns point - - before the rising edge is complete. What should the simulator do? - - should it just jump to the start of the falling curve (if it does, you may get a discontinuity on the output that can either glitch the output or cause a convergence problem) - - should the simulator "pipeline" the waveform results, and just remember the next edge starts 1 ns later - and if the input edges keep coming faster than the curve length, how long should the simulator keep this up before it starts clipping data? ... my earlier point was that the IBIS spec has no guidance on how a simulator should handle "overclocking" and different simulators DO handle this issue different ways. That being the case, it's best to avoid the problem by complying with the strong recommendation on page 70. As far as curve trimming goes, allow me to provide a *brief* overview, although I'm sure this subject has been discussed previously. Pointers into the archive for this subject from others would be appreciated. Let's consider a push-pull output stage instead of open drain - open-drain will just be a simpler case. Each output should have the following V-T curves [Corners] x [Edge] x [Loading] [Min / Typ / Max] x [Rising / Falling] x [50 ohms GND / 50 ohms VDDQ] ... for a total of 12 sets of V-T curves. ... for each [Corner]/[Loading] combination, it is ESSENTIAL that if you trim dead time off one curve, you trim the SAME amount of dead time off the other. As an example, if you trim 1ns off the start of the [Min]/[Rising]/[50 ohms GND] curve, you MUST trim 1ns off the [Min]/[Rising]/[50 ohms VDDQ] curve. If the second curve was already rising at that point, well, you need to trim less. This is what's called "time correlation" between curves, and it must be maintained. ... good practice dictates that you coordinate your trimming across all four of the V-T waveforms for any corner. If you don't do this, you'll introduce duty cycle distortion into the simulated waveform without meaning to. I believe this is now considered to be required practice. So, if you trim 1ns off the start of the [Min]/[Rising]/[50 ohms GND] curve, you really, really should trim 1ns off the following curves: [Min]/[Rising]/[50 ohms VDDQ] [Min]/[Falling]/[50 ohms GND] [Min]/[Falling]/[50 ohms VDDQ] ... so that time correlation is maintained across all the [Min] curves. As before, if you go to trim any of the curves and find the transition was already starting, you need to trim less. I don't believe IBIS requires that you coordinate trimming across corners. Thus, you can trim different amounts from the [Min] and [Typ] curve sets. In practice, you'll find this is useful because if you try to coordinate trimming across a 3 corners, the amount you are able to trim may be sharply limited. It's important to understand, though, that if you trim different amounts from the different corners, the time correlation between the corners will be lost. Strictly speaking, that's not a problem, as time 0 in an IBIS simulation is arbitrary. HOWEVER - if users of the model simulate the [Min] and [Typ] cases and overlay the results, they will draw incorrect conclusions if they assume the curves are time-correlated. It probably goes without saying, but - you can trim any amount of dead time you want off the END of a curve once the slope is zero. Good practice says the last two points should form a line with zero slope, so that any extrapolation the simulator performs does what you expect. As in all modeling - knowing what you've got is the first step in understanding what conclusions you can draw. Arpad & others - please correct me if I've gotten any of this wrong ... Todd. Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@sisoft.com www.sisoft.com - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Dimitry Eisenshtat Sent: Saturday, January 13, 2007 3:58 AM To: Todd Westerhoff Cc: ibis@eda-stds.org; ibis-users@eda.org Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Todd, ok, we understand that time correlation between IBIS and HSpice is not guaranteed, but is it really problem? I mean, in the most often situation there is no place for such comparison at all, because you have only IBIS model, no spice netlist is available. This is the first reason for making IBIS (if simulator speed is not an issue), is it right? Lets say, I'm with semiconductor vendor side, I have the netlist of the buffer, I make the IBIS model based on spice simulations, not lab measurements, so on final step when the model is ready I like to check it vs. original spice behavioral. This is the only situation I agree the comparison is important. But in such case there is no REAL problem - I know exactly about the delay, and if it is the only difference between the IBIS & spice - I don't care. I want ask you about IBIS simulator aspect of the point we are talking about. Look, I find in "Cookbook for ver4" strongly recommendation to trim IBIS model time tables at least to half of max buffer frequency period. (http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf page 70, 5.4.2 V-T Table Windowing). Can you please prefer from simulator software side - is it really problem for the simulator if the time table window is more then such time interval? And one additional point, you wrote "There are specific restrictions on how the dead time may be trimmed, which is a longer discussion" - right now I writes perl script which will trim tables in order to leave only transition region and decrease the time window as the Cookbook recommends to do. So, can you please explain about these restrictions? Thanks, Dmitry ... (previous thread clipped) - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 15 Jan 2007 10:22:30 -0500 From: "Todd Westerhoff" Subject: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Radovan, I understand what you're saying and agree - I thought it was worth noting the caveats for the group. One more caveat - while I think all IBIS simulators use a 1V "control input" to trigger the IBIS model, I believe they differ on the input voltage that triggers the waveform. Some use 0.5V, others use anything above 0V (rising) and below 1V (falling). Changing the edge rate of the control input will change the output waveform timing, to your original point. Thanks, Todd. Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@sisoft.com www.sisoft.com - -----Original Message----- From: Radovan.Vuletic@qimonda.com [mailto:Radovan.Vuletic@qimonda.com] Sent: Monday, January 15, 2007 4:11 AM To: twesterh@sisoft.com; ibis@eda-stds.org; ibis-users@eda.org Subject: RE: [IBIS] Ibis open drain strange behaviour Hi Tod, I believe that you have started/mentioned now 2 different topics, that according to my opinion should be separated: 1.) correlation between HSpice and IBIS models and 2.) "overclocking of IBIS models" as some prefer to call it or "frequency dependant IBIS models" (sounds very funny) as others prefer to call it. About correlation between HSpice and IBIS models: - - I absolutely agree with you that if one knows what is he/she doing comparison between HSpice and IBIS is not necessary. - - Zero time point is for IBIS not strictly defined, IBIS model creator can/should/must cut rising/falling waveforms to get "frequently independent models" But, if one still wants to compare simulation outputs of Spice netlist and unchanged IBIS model (generated out of very same Spice netlist) there will be a difference (time shift) in result that is independent on "buffer delay" due to using of stimuli by IBIS simulation tool (once again I limit my discussion only on HSpice, but I think most of the people are using HSpice) - for me one year ago this was unexpected and I believe that this was original question of Dimitry as well. Reason is, as mentioned in my previous mail, that as soon as a stimuli is applied on Spice netlist something "happens" immediately (at least in HSpice) and as soon as transistors has reached their thresholds, internal capacitances are filled out, etc. that can be seen in waveform. For IBIS output model, if you applying for example rising transition, nothing will change until stimuli on input reaches 0.8V, just than starts "buffer delay". For slow stimuli this effect is more obvious than for fast stimuli - if one applies step function (physically not justified, but still) this effect disappears. As you said about "overclocking of IBIS models" it could be discussed very, very long ... Regards, Radovan - -----Original Message----- From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf Of Todd Westerhoff Sent: Friday, January 12, 2007 7:31 PM To: ibis@server.eda-stds.org; ibis-users@server.eda.org Subject: RE: [IBIS] Ibis open drain strange behaviour Radovan, I believe the qualifications to time correlation between HSpice and IBIS are - - not necessarily, and yes, if. Time 0 is an IBIS simulation is not guaranteed to have any special significance. You'd like to think that you could simulate your transistor and IBIS model side by side into the same load and expect them to line up, but there is no part of the spec that guarantees this. The IBIS waveform and the HSpice waveform will match in rise/fall time and shape, but they are not guaranteed to align in time. Time 0 is an IBIS model is arbitrary, which is one of the reasons why "buffer delay" simulations are used to normalize the simulated interconnect delays (flight times) to the component timing specifications - this is where Vref, Rref and Cref come from. IF the person creating the IBIS model uses a particular ramp rate at the HSpice model input, and IF the model creator uses the simulated HSpice waveform in the IBIS model without trimming it, and IF the IBIS simulator uses a similar ramp rate to stimulate the IBIS model with comparable triggering thresholds, then - yes, the transistor and IBIS simulations will line up in time. In practice, this occurs pretty often - - but it's important to understand why. Most IBIS extraction software takes the simulated waveform from HSpice and puts it into the IBIS model unaltered (i.e. the IBIS output waveform does not start rising at time 0, it includes the "intrinsic" delay of the output buffer). As you pointed out, the ramp rate of the input to the buffer (in both the HSpice and IBIS simulations) is usually very fast compared to the ramp rate of the output. Thus, even if the input ramp rates or triggering thresholds are somewhat mismatched, the difference gets swamped by the much slower output ramp rate (and the simulations line up, or appear to). You need a significant mismatch in the stimulus rates to see a difference. However, one gets into trouble when the intrinsic delay of the output buffer approaches the device's data rate. The output may not finish "switching" in the IBIS curve before the next data bit is triggered. This particular behavior is problematic - the IBIS spec (last I looked) had no specific recommendation on how simulators should handle "overclocking", and different simulators handle this different ways. This is a big problem for semiconductor suppliers, as their models can have different behavior in different tools. The solution? Well, the IBIS spec does not guarantee that time 0 is when the input to the output buffer switches. Time 0 in an IBIS simulation is arbitrary. So, the model creators trim the "dead time" off the front end of the rising and falling V-T curves to ensure the outputs stabilize before the end of the data unit interval, and the time correlation to HSpice is lost. There are specific restrictions on how the dead time may be trimmed, which is a longer discussion. Point is, time correlation between IBIS and HSpice is not guaranteed. It happens frequently, but only as a consequence of the model building process. Dimitry was correct to point out that time 0 in HSpice is often arbitrary in itself - if we're dealing with a component with a clock-to-output spec, then we really have no idea when the output buffer in the device gets triggered with respect to the device's external clock pin anyway. Hope that helps, or was at least coherent ... Todd. Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@sisoft.com www.sisoft.com - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 15 Jan 2007 08:23:48 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Todd, Your explanation is excellent, couldn't have done it any better. Thanks, Arpad ======================================= - -----Original Message----- From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf Of Todd Westerhoff Sent: Monday, January 15, 2007 7:16 AM To: 'Dimitry Eisenshtat' Cc: ibis@server.eda-stds.org; ibis-users@server.eda.org Subject: RE: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Sorry for the delay in reply - I took the weekend off ;-) As far as non-time correlation between IBIS and transistor models goes - no, it isn't a problem at all. It's just important that people understand what a model represents and what it doesn't, so that they can draw the right conclusions from their simulations. I was just re-iterating one of my favorite points with "time 0 in an IBIS model is arbitrary". To your point, it's worth noting that time 0 in a spice model-based simulation is often arbitrary as well. A spice model represents only the output buffer at most, so if you're analyzing a device with a clock-to-out timing specification, you still need to figure out how to combine the delays measured in simulation with the timing spec for the device. I think people often ascribe too much credibility to spice models. The model you receive is a function of how the netlist and parasitics for the buffer were extracted - it's far too easy to become confused about what part of the overall device the spice model represents. As to page 70 of the IBIS cookbook - I agree with what it says. That particular page is assuming a DDR device, so that a 100 MHz clock yields 200M transfers/sec, each with a 5 ns UI. Let's suppose you have a model with a 6ns rising V-T curve for this case. The simulator will trigger the curve, begin sweeping the output, and then get retriggered at the 5ns point - - before the rising edge is complete. What should the simulator do? - - should it just jump to the start of the falling curve (if it does, you may get a discontinuity on the output that can either glitch the output or cause a convergence problem) - - should the simulator "pipeline" the waveform results, and just remember the next edge starts 1 ns later - and if the input edges keep coming faster than the curve length, how long should the simulator keep this up before it starts clipping data? ... my earlier point was that the IBIS spec has no guidance on how a simulator should handle "overclocking" and different simulators DO handle this issue different ways. That being the case, it's best to avoid the problem by complying with the strong recommendation on page 70. As far as curve trimming goes, allow me to provide a *brief* overview, although I'm sure this subject has been discussed previously. Pointers into the archive for this subject from others would be appreciated. Let's consider a push-pull output stage instead of open drain - open-drain will just be a simpler case. Each output should have the following V-T curves [Corners] x [Edge] x [Loading] [Min / Typ / Max] x [Rising / Falling] x [50 ohms GND / 50 ohms VDDQ] ... for a total of 12 sets of V-T curves. ... for each [Corner]/[Loading] combination, it is ESSENTIAL that if you trim dead time off one curve, you trim the SAME amount of dead time off the other. As an example, if you trim 1ns off the start of the [Min]/[Rising]/[50 ohms GND] curve, you MUST trim 1ns off the [Min]/[Rising]/[50 ohms VDDQ] curve. If the second curve was already rising at that point, well, you need to trim less. This is what's called "time correlation" between curves, and it must be maintained. ... good practice dictates that you coordinate your trimming across all four of the V-T waveforms for any corner. If you don't do this, you'll introduce duty cycle distortion into the simulated waveform without meaning to. I believe this is now considered to be required practice. So, if you trim 1ns off the start of the [Min]/[Rising]/[50 ohms GND] curve, you really, really should trim 1ns off the following curves: [Min]/[Rising]/[50 ohms VDDQ] [Min]/[Falling]/[50 ohms GND] [Min]/[Falling]/[50 ohms VDDQ] ... so that time correlation is maintained across all the [Min] curves. As before, if you go to trim any of the curves and find the transition was already starting, you need to trim less. I don't believe IBIS requires that you coordinate trimming across corners. Thus, you can trim different amounts from the [Min] and [Typ] curve sets. In practice, you'll find this is useful because if you try to coordinate trimming across a 3 corners, the amount you are able to trim may be sharply limited. It's important to understand, though, that if you trim different amounts from the different corners, the time correlation between the corners will be lost. Strictly speaking, that's not a problem, as time 0 in an IBIS simulation is arbitrary. HOWEVER - if users of the model simulate the [Min] and [Typ] cases and overlay the results, they will draw incorrect conclusions if they assume the curves are time-correlated. It probably goes without saying, but - you can trim any amount of dead time you want off the END of a curve once the slope is zero. Good practice says the last two points should form a line with zero slope, so that any extrapolation the simulator performs does what you expect. As in all modeling - knowing what you've got is the first step in understanding what conclusions you can draw. Arpad & others - please correct me if I've gotten any of this wrong ... Todd. Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@sisoft.com www.sisoft.com - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Dimitry Eisenshtat Sent: Saturday, January 13, 2007 3:58 AM To: Todd Westerhoff Cc: ibis@eda-stds.org; ibis-users@eda.org Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Todd, ok, we understand that time correlation between IBIS and HSpice is not guaranteed, but is it really problem? I mean, in the most often situation there is no place for such comparison at all, because you have only IBIS model, no spice netlist is available. This is the first reason for making IBIS (if simulator speed is not an issue), is it right? Lets say, I'm with semiconductor vendor side, I have the netlist of the buffer, I make the IBIS model based on spice simulations, not lab measurements, so on final step when the model is ready I like to check it vs. original spice behavioral. This is the only situation I agree the comparison is important. But in such case there is no REAL problem - I know exactly about the delay, and if it is the only difference between the IBIS & spice - I don't care. I want ask you about IBIS simulator aspect of the point we are talking about. Look, I find in "Cookbook for ver4" strongly recommendation to trim IBIS model time tables at least to half of max buffer frequency period. (http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf page 70, 5.4.2 V-T Table Windowing). Can you please prefer from simulator software side - is it really problem for the simulator if the time table window is more then such time interval? And one additional point, you wrote "There are specific restrictions on how the dead time may be trimmed, which is a longer discussion" - right now I writes perl script which will trim tables in order to leave only transition region and decrease the time window as the Cookbook recommends to do. So, can you please explain about these restrictions? Thanks, Dmitry ... (previous thread clipped) - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 15 Jan 2007 08:38:04 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour I would like to chime in about "frequency dependence" and "over clocking". Even though over clocking is usually achieved by cranking up the frequency of the stimulus, it not the only way to achieve that. You can also get that effect by changing the duty cycle so that the short half of the cycle becomes shorter in duration than the length of the V-t table in the IBIS file. On the other hand, when I think of frequency, I usually think of it more in terms of frequency domain analysis. What does the model do with the higher harmonic components of the signals? From this perspective legacy IBIS does not have the capability to describe frequency dependent buffer behavior, because the I-V curves yield a constant impedance at all frequencies, and C_comp is also a constant for all frequencies. In real life there are all kinds of variations with respect to frequency. Having said all this, I prefer to use the term "frequency dependence" for the latter, and "over clocking" for the former topic. Arpad =========================================================== - -----Original Message----- From: Radovan.Vuletic@qimonda.com [mailto:Radovan.Vuletic@qimonda.com] Sent: Monday, January 15, 2007 4:11 AM To: twesterh@sisoft.com; ibis@eda-stds.org; ibis-users@eda.org Subject: RE: [IBIS] Ibis open drain strange behaviour Hi Tod, I believe that you have started/mentioned now 2 different topics, that according to my opinion should be separated: 1.) correlation between HSpice and IBIS models and 2.) "overclocking of IBIS models" as some prefer to call it or "frequency dependant IBIS models" (sounds very funny) as others prefer to call it. ... ... ... Regards, Radovan - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 16 Jan 2007 00:01:37 +0200 From: "Dimitry Eisenshtat" Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Hi Todd, first of all - thanks for your reply, as I said, I'm writing script for trimming V/T tables in order to satisfy Cookbook recommendation, so your explanation is really useful. Thank you :) Ok, I see from your virtual DDR example that "over clocking" should require special treatment on IBIS simulator side, and I finally decide to avoid such situations and create IBIS models with V/T tables time window up to half of minimum signal period the buffer designed for. Now some words about HOW I will do it. I think the most important point you mentioned is "time correlation" of all given corner curves. I want use simple algorithm for automatically trimming V/T curves, let me explain. Lets say we have 12 transients, exactly as in your (most common) example of push-pull buffer simulated in 3 corners with load of 50 ohm once to supply, once to ground. The steps will be: 1) Run spice simulations (with s2ibis* or manually, does not matter) with as small time step as it possible for simulation time large enough for weakest conditions (corner/load) transition to be finally completed. The idea is to begin with "ideal" time resolution for all transitions regions in our 12 curves. 2) For each curve find largest time interval (T1,T2) which satisfy voltage tolerance of delta from initial and final DC solutions, i.e. |(V(T1)-Vstart)/VDD| < Vtol, |(V(T2)-Vend)/VDD| < Vtol where Vtol tolerance chosen smaller than IBISCHK's one so the checker will not report "DC endpoints" warning on trimmed tables latter. All data points outside of this interval (T1,T2) are declared "dead zones" and have no importance. So the Vtol value actually plays as "dead zones" definition criteria and should be the parameter to be changed if needed. 3) For all curves (rising/falling/load) of given corner find the minimum T1 value, lets define it as T1_typ, T1_slow, T1_fast or T1_. 4) Calculate maximum interval dT_max = max {|T2-T1_|} for ALL curves. 5) Shift all curves for given corner left in time by T1_ value. 6) Truncate all curves at time dT_max (from new 0 time after shifting) 7) Add one points to end of each curve in order to form a line with zero slope for case of some simulators extrapolation will be needed. 8) Remember, we start from "the best" time resolution, so it is possible that we get desire time window from overclocking point of view, but number of points in final V/T tables still exceeds the maximum allowed by IBIS spec. In this case I suggest to use "greatest change algorithm" in order to decrease the number of tables points, as it described in Cookbook (pages 63-64). As the result, if I have no mistake, we will get "corner time- correlated" tables. However, across corners correlation is not guaranteed. My assumption is that the user will be interested in analyzing the buffer's (buffer itself, I mean not control logic but pullup/pulldown devices which actually drive the pad) corner-specific behavioral/differences, so I at least do not worsen the model quality, or even improve it. Anyway, in some cases there will be no possibility to satisfy "overclocking free" condition without shifting the corner's curves one to each other, in other words without trimming different amounts from different corners. Does it make sense? I like to complete realizing this algorithm in perl and try it on last DDR2 model I produced. Only IBIS simulator I have is HSpice, so the plan is to compare the behavioral of IBIS model before and after trimming. I hope the HSpice is bad enough in "over clocking" scenario, otherwise I will see no difference/improvements anyway :) Regards, Dmitry Todd Westerhoff wrote: > Sorry for the delay in reply - I took the weekend off ;-) > > As far as non-time correlation between IBIS and transistor models goes - no, > it isn't a problem at all. It's just important that people understand what > a model represents and what it doesn't, so that they can draw the right > conclusions from their simulations. I was just re-iterating one of my > favorite points with "time 0 in an IBIS model is arbitrary". > > To your point, it's worth noting that time 0 in a spice model-based > simulation is often arbitrary as well. A spice model represents only the > output buffer at most, so if you're analyzing a device with a clock-to-out > timing specification, you still need to figure out how to combine the delays > measured in simulation with the timing spec for the device. > > I think people often ascribe too much credibility to spice models. The > model you receive is a function of how the netlist and parasitics for the > buffer were extracted - it's far too easy to become confused about what part > of the overall device the spice model represents. > > As to page 70 of the IBIS cookbook - I agree with what it says. That > particular page is assuming a DDR device, so that a 100 MHz clock yields > 200M transfers/sec, each with a 5 ns UI. Let's suppose you have a model > with a 6ns rising V-T curve for this case. The simulator will trigger the > curve, begin sweeping the output, and then get retriggered at the 5ns point > - before the rising edge is complete. What should the simulator do? > > - should it just jump to the start of the falling curve (if it does, you may > get a discontinuity on the output that can either glitch the output or cause > a convergence problem) > > - should the simulator "pipeline" the waveform results, and just remember > the next edge starts 1 ns later - and if the input edges keep coming faster > than the curve length, how long should the simulator keep this up before it > starts clipping data? > > ... my earlier point was that the IBIS spec has no guidance on how a > simulator should handle "overclocking" and different simulators DO handle > this issue different ways. That being the case, it's best to avoid the > problem by complying with the strong recommendation on page 70. > > As far as curve trimming goes, allow me to provide a *brief* overview, > although I'm sure this subject has been discussed previously. Pointers into > the archive for this subject from others would be appreciated. > > Let's consider a push-pull output stage instead of open drain - open-drain > will just be a simpler case. > > Each output should have the following V-T curves > > [Corners] x [Edge] x [Loading] > > [Min / Typ / Max] x [Rising / Falling] x [50 ohms GND / 50 ohms > VDDQ] > > ... for a total of 12 sets of V-T curves. > > ... for each [Corner]/[Loading] combination, it is ESSENTIAL that if you > trim dead time off one curve, you trim the SAME amount of dead time off the > other. As an example, if you trim 1ns off the start of the > [Min]/[Rising]/[50 ohms GND] curve, you MUST trim 1ns off the > [Min]/[Rising]/[50 ohms VDDQ] curve. If the second curve was already rising > at that point, well, you need to trim less. > > This is what's called "time correlation" between curves, and it must be > maintained. > > ... good practice dictates that you coordinate your trimming across all four > of the V-T waveforms for any corner. If you don't do this, you'll introduce > duty cycle distortion into the simulated waveform without meaning to. I > believe this is now considered to be required practice. So, if you trim 1ns > off the start of the [Min]/[Rising]/[50 ohms GND] curve, you really, really > should trim 1ns off the following curves: > > [Min]/[Rising]/[50 ohms VDDQ] > [Min]/[Falling]/[50 ohms GND] > [Min]/[Falling]/[50 ohms VDDQ] > > ... so that time correlation is maintained across all the [Min] curves. As > before, if you go to trim any of the curves and find the transition was > already starting, you need to trim less. > > I don't believe IBIS requires that you coordinate trimming across corners. > Thus, you can trim different amounts from the [Min] and [Typ] curve sets. > In practice, you'll find this is useful because if you try to coordinate > trimming across a 3 corners, the amount you are able to trim may be sharply > limited. It's important to understand, though, that if you trim different > amounts from the different corners, the time correlation between the corners > will be lost. Strictly speaking, that's not a problem, as time 0 in an IBIS > simulation is arbitrary. HOWEVER - if users of the model simulate the [Min] > and [Typ] cases and overlay the results, they will draw incorrect > conclusions if they assume the curves are time-correlated. > > It probably goes without saying, but - you can trim any amount of dead time > you want off the END of a curve once the slope is zero. Good practice says > the last two points should form a line with zero slope, so that any > extrapolation the simulator performs does what you expect. > > As in all modeling - knowing what you've got is the first step in > understanding what conclusions you can draw. > > Arpad & others - please correct me if I've gotten any of this wrong ... > > Todd. > > Todd Westerhoff > VP, Software Products > SiSoft > 6 Clock Tower Place, Suite 250 > Maynard, MA 01754 > (978) 461-0449 x24 > twesterh@sisoft.com > www.sisoft.com > -----Original Message----- > From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf > Of Dimitry Eisenshtat > Sent: Saturday, January 13, 2007 3:58 AM > To: Todd Westerhoff > Cc: ibis@eda-stds.org; ibis-users@eda.org > Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour > > Todd, > ok, we understand that time correlation between IBIS and HSpice is not > guaranteed, but is it really problem? I mean, in the most often > situation there is no place for such comparison at all, because you have > only IBIS model, no spice netlist is available. This is the first reason > for making IBIS (if simulator speed is not an issue), is it right? Lets > say, I'm with semiconductor vendor side, I have the netlist of the > buffer, I make the IBIS model based on spice simulations, not lab > measurements, so on final step when the model is ready I like to check > it vs. original spice behavioral. This is the only situation I agree the > comparison is important. But in such case there is no REAL problem - I > know exactly about the delay, and if it is the only difference between > the IBIS & spice - I don't care. > > I want ask you about IBIS simulator aspect of the point we are talking > about. Look, I find in "Cookbook for ver4" strongly recommendation to > trim IBIS model time tables at least to half of max buffer frequency > period. (http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf page 70, > 5.4.2 V-T Table Windowing). Can you please prefer from simulator > software side - is it really problem for the simulator if the time table > window is more then such time interval? And one additional point, you > wrote "There are specific restrictions on how the dead time may be > trimmed, which is a longer discussion" - right now I writes perl script > which will trim tables in order to leave only transition region and > decrease the time window as the Cookbook recommends to do. So, can you > please explain about these restrictions? > > Thanks, > Dmitry > > ... (previous thread clipped) > > - -- +---------------------------------------------------------+ | Dmitry Aizenshtat Circuit Design Engineer, NSTA | | Tel : 972-9-9702-020 Fax : 972-9-9702-001 | | mailto:dimita@taux01.nsc.com | +---------------------------------------------------------+ =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Winbond is strictly prohibited; and any information in this email irrelevant to the official business of Winbond shall be deemed as neither given nor endorsed by Winbond. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 16 Jan 2007 08:59:22 -0500 From: "Todd Westerhoff" Subject: RE: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Dimitry, This is good stuff! I have a few very small comments: Step 2: I think you meant you're going to find the *smallest* T1 to T2 interval that satisfies Vtol. Alternatively, you could find the largest interval from start to T1. Step 4: Once you've made this computation, you can determine if you're going to be able to shift ALL curves by the same amount and stay within the bit time (i.e. maintain time correlation across min/typ/max), or if you need to adjust curves by corner - in which case I'd print a message to that effect, possibly as a comment in the IBIS file itself. Your conclusion about not needing time correlation across min/typ/max curves is correct - each corner simulation gets paired with its own set of timing data (slow/typ/fast) for timing analysis, so time-correlation between corners isn't required. That having been said, it's good to preserve time-correlation between corners when you can, simply because new users won't necessarily understand the nuances of how SI results get paired with static timing. I really like the way you've defined T1 and T2. I think it would be a good idea to identify all the different curves as well: 1. [Min]/[Rising]/[50 ohm GND] 2. [Min]/[Rising]/[50 ohm VDDQ] 3. [Min]/[Falling]/[50 ohm GND] 4. [Min]/[Falling]/[50 ohm VDDQ] 5. [Typ]/[Rising]/[50 ohm GND] 6. [Typ]/[Rising]/[50 ohm VDDQ] 7. [Typ]/[Falling]/[50 ohm GND] 8. [Typ]/[Falling]/[50 ohm VDDQ] 9. [Max]/[Rising]/[50 ohm GND] 10. [Max]/[Rising]/[50 ohm VDDQ] 11. [Max]/[Falling]/[50 ohm GND] 12. [Max]/[Falling]/[50 ohm VDDQ] .... or whatever other convention makes sense. That way, we could talk about T1 for Curve 4 and know exactly what we're talking about ... Todd. Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@sisoft.com www.sisoft.com - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Dimitry Eisenshtat Sent: Monday, January 15, 2007 5:02 PM To: Todd Westerhoff Cc: ibis@eda-stds.org; ibis-users@eda.org Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Hi Todd, first of all - thanks for your reply, as I said, I'm writing script for trimming V/T tables in order to satisfy Cookbook recommendation, so your explanation is really useful. Thank you :) Ok, I see from your virtual DDR example that "over clocking" should require special treatment on IBIS simulator side, and I finally decide to avoid such situations and create IBIS models with V/T tables time window up to half of minimum signal period the buffer designed for. Now some words about HOW I will do it. I think the most important point you mentioned is "time correlation" of all given corner curves. I want use simple algorithm for automatically trimming V/T curves, let me explain. Lets say we have 12 transients, exactly as in your (most common) example of push-pull buffer simulated in 3 corners with load of 50 ohm once to supply, once to ground. The steps will be: 1) Run spice simulations (with s2ibis* or manually, does not matter) with as small time step as it possible for simulation time large enough for weakest conditions (corner/load) transition to be finally completed. The idea is to begin with "ideal" time resolution for all transitions regions in our 12 curves. 2) For each curve find largest time interval (T1,T2) which satisfy voltage tolerance of delta from initial and final DC solutions, i.e. |(V(T1)-Vstart)/VDD| < Vtol, |(V(T2)-Vend)/VDD| < Vtol where Vtol tolerance chosen smaller than IBISCHK's one so the checker will not report "DC endpoints" warning on trimmed tables latter. All data points outside of this interval (T1,T2) are declared "dead zones" and have no importance. So the Vtol value actually plays as "dead zones" definition criteria and should be the parameter to be changed if needed. 3) For all curves (rising/falling/load) of given corner find the minimum T1 value, lets define it as T1_typ, T1_slow, T1_fast or T1_. 4) Calculate maximum interval dT_max = max {|T2-T1_|} for ALL curves. 5) Shift all curves for given corner left in time by T1_ value. 6) Truncate all curves at time dT_max (from new 0 time after shifting) 7) Add one points to end of each curve in order to form a line with zero slope for case of some simulators extrapolation will be needed. 8) Remember, we start from "the best" time resolution, so it is possible that we get desire time window from overclocking point of view, but number of points in final V/T tables still exceeds the maximum allowed by IBIS spec. In this case I suggest to use "greatest change algorithm" in order to decrease the number of tables points, as it described in Cookbook (pages 63-64). As the result, if I have no mistake, we will get "corner time- correlated" tables. However, across corners correlation is not guaranteed. My assumption is that the user will be interested in analyzing the buffer's (buffer itself, I mean not control logic but pullup/pulldown devices which actually drive the pad) corner-specific behavioral/differences, so I at least do not worsen the model quality, or even improve it. Anyway, in some cases there will be no possibility to satisfy "overclocking free" condition without shifting the corner's curves one to each other, in other words without trimming different amounts from different corners. Does it make sense? I like to complete realizing this algorithm in perl and try it on last DDR2 model I produced. Only IBIS simulator I have is HSpice, so the plan is to compare the behavioral of IBIS model before and after trimming. I hope the HSpice is bad enough in "over clocking" scenario, otherwise I will see no difference/improvements anyway :) Regards, Dmitry - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 16 Jan 2007 08:59:05 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Dimitry, Before you spend too much time on this script, you may want to check out the tool and HSPICE data generation templates which are carefully hidden away in this link: http://www.vhdl.org/pub/ibis/training/IBIS_class_2003.zip (See IBIS_class_Labs.zip and IC1NT9r.zip files). Arpad ======================================================= - -----Original Message----- From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf Of Dimitry Eisenshtat Sent: Monday, January 15, 2007 2:02 PM To: Todd Westerhoff Cc: ibis@server.eda-stds.org; ibis-users@server.eda.org Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Hi Todd, first of all - thanks for your reply, as I said, I'm writing script for trimming V/T tables in order to satisfy Cookbook recommendation, so your explanation is really useful. Thank you :) Ok, I see from your virtual DDR example that "over clocking" should require special treatment on IBIS simulator side, and I finally decide to avoid such situations and create IBIS models with V/T tables time window up to half of minimum signal period the buffer designed for. Now some words about HOW I will do it. I think the most important point you mentioned is "time correlation" of all given corner curves. I want use simple algorithm for automatically trimming V/T curves, let me explain. Lets say we have 12 transients, exactly as in your (most common) example of push-pull buffer simulated in 3 corners with load of 50 ohm once to supply, once to ground. The steps will be: 1) Run spice simulations (with s2ibis* or manually, does not matter) with as small time step as it possible for simulation time large enough for weakest conditions (corner/load) transition to be finally completed. The idea is to begin with "ideal" time resolution for all transitions regions in our 12 curves. 2) For each curve find largest time interval (T1,T2) which satisfy voltage tolerance of delta from initial and final DC solutions, i.e. |(V(T1)-Vstart)/VDD| < Vtol, |(V(T2)-Vend)/VDD| < Vtol where Vtol tolerance chosen smaller than IBISCHK's one so the checker will not report "DC endpoints" warning on trimmed tables latter. All data points outside of this interval (T1,T2) are declared "dead zones" and have no importance. So the Vtol value actually plays as "dead zones" definition criteria and should be the parameter to be changed if needed. 3) For all curves (rising/falling/load) of given corner find the minimum T1 value, lets define it as T1_typ, T1_slow, T1_fast or T1_. 4) Calculate maximum interval dT_max = max {|T2-T1_|} for ALL curves. 5) Shift all curves for given corner left in time by T1_ value. 6) Truncate all curves at time dT_max (from new 0 time after shifting) 7) Add one points to end of each curve in order to form a line with zero slope for case of some simulators extrapolation will be needed. 8) Remember, we start from "the best" time resolution, so it is possible that we get desire time window from overclocking point of view, but number of points in final V/T tables still exceeds the maximum allowed by IBIS spec. In this case I suggest to use "greatest change algorithm" in order to decrease the number of tables points, as it described in Cookbook (pages 63-64). As the result, if I have no mistake, we will get "corner time- correlated" tables. However, across corners correlation is not guaranteed. My assumption is that the user will be interested in analyzing the buffer's (buffer itself, I mean not control logic but pullup/pulldown devices which actually drive the pad) corner-specific behavioral/differences, so I at least do not worsen the model quality, or even improve it. Anyway, in some cases there will be no possibility to satisfy "overclocking free" condition without shifting the corner's curves one to each other, in other words without trimming different amounts from different corners. Does it make sense? I like to complete realizing this algorithm in perl and try it on last DDR2 model I produced. Only IBIS simulator I have is HSpice, so the plan is to compare the behavioral of IBIS model before and after trimming. I hope the HSpice is bad enough in "over clocking" scenario, otherwise I will see no difference/improvements anyway :) Regards, Dmitry Todd Westerhoff wrote: > Sorry for the delay in reply - I took the weekend off ;-) > > As far as non-time correlation between IBIS and transistor models goes - no, > it isn't a problem at all. It's just important that people understand what > a model represents and what it doesn't, so that they can draw the right > conclusions from their simulations. I was just re-iterating one of my > favorite points with "time 0 in an IBIS model is arbitrary". > > To your point, it's worth noting that time 0 in a spice model-based > simulation is often arbitrary as well. A spice model represents only the > output buffer at most, so if you're analyzing a device with a clock-to-out > timing specification, you still need to figure out how to combine the delays > measured in simulation with the timing spec for the device. > > I think people often ascribe too much credibility to spice models. The > model you receive is a function of how the netlist and parasitics for the > buffer were extracted - it's far too easy to become confused about what part > of the overall device the spice model represents. > > As to page 70 of the IBIS cookbook - I agree with what it says. That > particular page is assuming a DDR device, so that a 100 MHz clock yields > 200M transfers/sec, each with a 5 ns UI. Let's suppose you have a model > with a 6ns rising V-T curve for this case. The simulator will trigger the > curve, begin sweeping the output, and then get retriggered at the 5ns point > - before the rising edge is complete. What should the simulator do? > > - should it just jump to the start of the falling curve (if it does, you may > get a discontinuity on the output that can either glitch the output or cause > a convergence problem) > > - should the simulator "pipeline" the waveform results, and just remember > the next edge starts 1 ns later - and if the input edges keep coming faster > than the curve length, how long should the simulator keep this up before it > starts clipping data? > > ... my earlier point was that the IBIS spec has no guidance on how a > simulator should handle "overclocking" and different simulators DO handle > this issue different ways. That being the case, it's best to avoid the > problem by complying with the strong recommendation on page 70. > > As far as curve trimming goes, allow me to provide a *brief* overview, > although I'm sure this subject has been discussed previously. Pointers into > the archive for this subject from others would be appreciated. > > Let's consider a push-pull output stage instead of open drain - open-drain > will just be a simpler case. > > Each output should have the following V-T curves > > [Corners] x [Edge] x [Loading] > > [Min / Typ / Max] x [Rising / Falling] x [50 ohms GND / 50 ohms > VDDQ] > > ... for a total of 12 sets of V-T curves. > > ... for each [Corner]/[Loading] combination, it is ESSENTIAL that if you > trim dead time off one curve, you trim the SAME amount of dead time off the > other. As an example, if you trim 1ns off the start of the > [Min]/[Rising]/[50 ohms GND] curve, you MUST trim 1ns off the > [Min]/[Rising]/[50 ohms VDDQ] curve. If the second curve was already rising > at that point, well, you need to trim less. > > This is what's called "time correlation" between curves, and it must be > maintained. > > ... good practice dictates that you coordinate your trimming across all four > of the V-T waveforms for any corner. If you don't do this, you'll introduce > duty cycle distortion into the simulated waveform without meaning to. I > believe this is now considered to be required practice. So, if you trim 1ns > off the start of the [Min]/[Rising]/[50 ohms GND] curve, you really, really > should trim 1ns off the following curves: > > [Min]/[Rising]/[50 ohms VDDQ] > [Min]/[Falling]/[50 ohms GND] > [Min]/[Falling]/[50 ohms VDDQ] > > ... so that time correlation is maintained across all the [Min] curves. As > before, if you go to trim any of the curves and find the transition was > already starting, you need to trim less. > > I don't believe IBIS requires that you coordinate trimming across corners. > Thus, you can trim different amounts from the [Min] and [Typ] curve sets. > In practice, you'll find this is useful because if you try to coordinate > trimming across a 3 corners, the amount you are able to trim may be sharply > limited. It's important to understand, though, that if you trim different > amounts from the different corners, the time correlation between the corners > will be lost. Strictly speaking, that's not a problem, as time 0 in an IBIS > simulation is arbitrary. HOWEVER - if users of the model simulate the [Min] > and [Typ] cases and overlay the results, they will draw incorrect > conclusions if they assume the curves are time-correlated. > > It probably goes without saying, but - you can trim any amount of dead time > you want off the END of a curve once the slope is zero. Good practice says > the last two points should form a line with zero slope, so that any > extrapolation the simulator performs does what you expect. > > As in all modeling - knowing what you've got is the first step in > understanding what conclusions you can draw. > > Arpad & others - please correct me if I've gotten any of this wrong ... > > Todd. > > Todd Westerhoff > VP, Software Products > SiSoft > 6 Clock Tower Place, Suite 250 > Maynard, MA 01754 > (978) 461-0449 x24 > twesterh@sisoft.com > www.sisoft.com > -----Original Message----- > From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf > Of Dimitry Eisenshtat > Sent: Saturday, January 13, 2007 3:58 AM > To: Todd Westerhoff > Cc: ibis@eda-stds.org; ibis-users@eda.org > Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour > > Todd, > ok, we understand that time correlation between IBIS and HSpice is not > guaranteed, but is it really problem? I mean, in the most often > situation there is no place for such comparison at all, because you have > only IBIS model, no spice netlist is available. This is the first reason > for making IBIS (if simulator speed is not an issue), is it right? Lets > say, I'm with semiconductor vendor side, I have the netlist of the > buffer, I make the IBIS model based on spice simulations, not lab > measurements, so on final step when the model is ready I like to check > it vs. original spice behavioral. This is the only situation I agree the > comparison is important. But in such case there is no REAL problem - I > know exactly about the delay, and if it is the only difference between > the IBIS & spice - I don't care. > > I want ask you about IBIS simulator aspect of the point we are talking > about. Look, I find in "Cookbook for ver4" strongly recommendation to > trim IBIS model time tables at least to half of max buffer frequency > period. (http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf page 70, > 5.4.2 V-T Table Windowing). Can you please prefer from simulator > software side - is it really problem for the simulator if the time table > window is more then such time interval? And one additional point, you > wrote "There are specific restrictions on how the dead time may be > trimmed, which is a longer discussion" - right now I writes perl script > which will trim tables in order to leave only transition region and > decrease the time window as the Cookbook recommends to do. So, can you > please explain about these restrictions? > > Thanks, > Dmitry > > ... (previous thread clipped) > > - -- +---------------------------------------------------------+ | Dmitry Aizenshtat Circuit Design Engineer, NSTA | | Tel : 972-9-9702-020 Fax : 972-9-9702-001 | | mailto:dimita@taux01.nsc.com | +---------------------------------------------------------+ =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Winbond is strictly prohibited; and any information in this email irrelevant to the official business of Winbond shall be deemed as neither given nor endorsed by Winbond. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 17 Jan 2007 15:33:21 +0200 From: "Dimitry Eisenshtat" Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Arpad, thanks for the link, I'm sure the IBIS overview pdf docs contain some info which will be new for me and so it will be useful, in other words I think it is good idea to read this stuff carefully and look for important points I not familiar with yet. My working environment is under RedHat Linux, so I have nothing to do with *.msi installation files of tool which you're using. Anyway, I prefer to deal with open source software, because if I have no source, I have no possibility to fix bugs (lets say no possibility even to try), and every piece of code has its bugs, you know. Especially when we talking about IBIS, at least from my point of view, the things is still in development, and sometimes there is a real need to improve some step in model generation process. By the way, I'll really happy to know that I have a mistake and some free open source s2ibis like software which supports all problematic issues (including C_comp calculations, differential buffers modeling, overclocking and maybe more "advanced" points) does exist. Do you know about such software? s2ibis2 is more then nothing, but not enough. s2ibis3 is more or less equivalent java version of s2ibis2. regards, Dmitry Muranyi, Arpad wrote: > Dimitry, > > Before you spend too much time on this script, you may > want to check out the tool and HSPICE data generation > templates which are carefully hidden away in this link: > > http://www.vhdl.org/pub/ibis/training/IBIS_class_2003.zip > > (See IBIS_class_Labs.zip and IC1NT9r.zip files). > > Arpad > ======================================================= > > -----Original Message----- > From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf Of Dimitry Eisenshtat > Sent: Monday, January 15, 2007 2:02 PM > To: Todd Westerhoff > Cc: ibis@server.eda-stds.org; ibis-users@server.eda.org > Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour > > Hi Todd, > first of all - thanks for your reply, as I said, I'm writing script for > trimming V/T tables in order to satisfy Cookbook recommendation, so your > explanation is really useful. Thank you :) > > Ok, I see from your virtual DDR example that "over clocking" should > require special treatment on IBIS simulator side, and I finally decide > to avoid such situations and create IBIS models with V/T tables time > window up to half of minimum signal period the buffer designed for. > > Now some words about HOW I will do it. I think the most important point > you mentioned is "time correlation" of all given corner curves. I want > use simple algorithm for automatically trimming V/T curves, let me > explain. Lets say we have 12 transients, exactly as in your (most > common) example of push-pull buffer simulated in 3 corners with load of > 50 ohm once to supply, once to ground. The steps will be: > > 1) Run spice simulations (with s2ibis* or manually, does not matter) > with as small time step as it possible for simulation time large enough > for weakest conditions (corner/load) transition to be finally completed. > The idea is to begin with "ideal" time resolution for all transitions > regions in our 12 curves. > > 2) For each curve find largest time interval (T1,T2) which satisfy > voltage tolerance of delta from initial and final DC solutions, i.e. > |(V(T1)-Vstart)/VDD| < Vtol, > |(V(T2)-Vend)/VDD| < Vtol > where Vtol tolerance chosen smaller than IBISCHK's one so the checker > will not report "DC endpoints" warning on trimmed tables latter. All > data points outside of this interval (T1,T2) are declared "dead zones" > and have no importance. So the Vtol value actually plays as "dead zones" > definition criteria and should be the parameter to be changed if needed. > > 3) For all curves (rising/falling/load) of given corner find the minimum > T1 value, lets define it as T1_typ, T1_slow, T1_fast or T1_. > > 4) Calculate maximum interval dT_max = max {|T2-T1_|} for ALL > curves. > > 5) Shift all curves for given corner left in time by T1_ value. > > 6) Truncate all curves at time dT_max (from new 0 time after shifting) > > 7) Add one points to end of each curve in order to form a line with zero > slope for case of some simulators extrapolation will be needed. > > 8) Remember, we start from "the best" time resolution, so it is possible > that we get desire time window from overclocking point of view, but > number of points in final V/T tables still exceeds the maximum allowed > by IBIS spec. In this case I suggest to use "greatest change algorithm" > in order to decrease the number of tables points, as it described in > Cookbook (pages 63-64). > > As the result, if I have no mistake, we will get "corner time- > correlated" tables. However, across corners correlation is not > guaranteed. My assumption is that the user will be interested in > analyzing the buffer's (buffer itself, I mean not control logic but > pullup/pulldown devices which actually drive the pad) corner-specific > behavioral/differences, so I at least do not worsen the model quality, > or even improve it. Anyway, in some cases there will be no possibility > to satisfy "overclocking free" condition without shifting the corner's > curves one to each other, in other words without trimming different > amounts from different corners. > > Does it make sense? I like to complete realizing this algorithm in perl > and try it on last DDR2 model I produced. Only IBIS simulator I have is > HSpice, so the plan is to compare the behavioral of IBIS model before > and after trimming. I hope the HSpice is bad enough in "over clocking" > scenario, otherwise I will see no difference/improvements anyway :) > > Regards, > Dmitry > > > Todd Westerhoff wrote: > >>Sorry for the delay in reply - I took the weekend off ;-) >> >>As far as non-time correlation between IBIS and transistor models goes - no, >>it isn't a problem at all. It's just important that people understand what >>a model represents and what it doesn't, so that they can draw the right >>conclusions from their simulations. I was just re-iterating one of my >>favorite points with "time 0 in an IBIS model is arbitrary". >> >>To your point, it's worth noting that time 0 in a spice model-based >>simulation is often arbitrary as well. A spice model represents only the >>output buffer at most, so if you're analyzing a device with a clock-to-out >>timing specification, you still need to figure out how to combine the delays >>measured in simulation with the timing spec for the device. >> >>I think people often ascribe too much credibility to spice models. The >>model you receive is a function of how the netlist and parasitics for the >>buffer were extracted - it's far too easy to become confused about what part >>of the overall device the spice model represents. >> >>As to page 70 of the IBIS cookbook - I agree with what it says. That >>particular page is assuming a DDR device, so that a 100 MHz clock yields >>200M transfers/sec, each with a 5 ns UI. Let's suppose you have a model >>with a 6ns rising V-T curve for this case. The simulator will trigger the >>curve, begin sweeping the output, and then get retriggered at the 5ns point >>- before the rising edge is complete. What should the simulator do? >> >>- should it just jump to the start of the falling curve (if it does, you may >>get a discontinuity on the output that can either glitch the output or cause >>a convergence problem) >> >>- should the simulator "pipeline" the waveform results, and just remember >>the next edge starts 1 ns later - and if the input edges keep coming faster >>than the curve length, how long should the simulator keep this up before it >>starts clipping data? >> >>... my earlier point was that the IBIS spec has no guidance on how a >>simulator should handle "overclocking" and different simulators DO handle >>this issue different ways. That being the case, it's best to avoid the >>problem by complying with the strong recommendation on page 70. >> >>As far as curve trimming goes, allow me to provide a *brief* overview, >>although I'm sure this subject has been discussed previously. Pointers into >>the archive for this subject from others would be appreciated. >> >>Let's consider a push-pull output stage instead of open drain - open-drain >>will just be a simpler case. >> >>Each output should have the following V-T curves >> >> [Corners] x [Edge] x [Loading] >> >> [Min / Typ / Max] x [Rising / Falling] x [50 ohms GND / 50 ohms >>VDDQ] >> >>... for a total of 12 sets of V-T curves. >> >>... for each [Corner]/[Loading] combination, it is ESSENTIAL that if you >>trim dead time off one curve, you trim the SAME amount of dead time off the >>other. As an example, if you trim 1ns off the start of the >>[Min]/[Rising]/[50 ohms GND] curve, you MUST trim 1ns off the >>[Min]/[Rising]/[50 ohms VDDQ] curve. If the second curve was already rising >>at that point, well, you need to trim less. >> >>This is what's called "time correlation" between curves, and it must be >>maintained. >> >>... good practice dictates that you coordinate your trimming across all four >>of the V-T waveforms for any corner. If you don't do this, you'll introduce >>duty cycle distortion into the simulated waveform without meaning to. I >>believe this is now considered to be required practice. So, if you trim 1ns >>off the start of the [Min]/[Rising]/[50 ohms GND] curve, you really, really >>should trim 1ns off the following curves: >> >> [Min]/[Rising]/[50 ohms VDDQ] >> [Min]/[Falling]/[50 ohms GND] >> [Min]/[Falling]/[50 ohms VDDQ] >> >>... so that time correlation is maintained across all the [Min] curves. As >>before, if you go to trim any of the curves and find the transition was >>already starting, you need to trim less. >> >>I don't believe IBIS requires that you coordinate trimming across corners. >>Thus, you can trim different amounts from the [Min] and [Typ] curve sets. >>In practice, you'll find this is useful because if you try to coordinate >>trimming across a 3 corners, the amount you are able to trim may be sharply >>limited. It's important to understand, though, that if you trim different >>amounts from the different corners, the time correlation between the corners >>will be lost. Strictly speaking, that's not a problem, as time 0 in an IBIS >>simulation is arbitrary. HOWEVER - if users of the model simulate the [Min] >>and [Typ] cases and overlay the results, they will draw incorrect >>conclusions if they assume the curves are time-correlated. >> >>It probably goes without saying, but - you can trim any amount of dead time >>you want off the END of a curve once the slope is zero. Good practice says >>the last two points should form a line with zero slope, so that any >>extrapolation the simulator performs does what you expect. >> >>As in all modeling - knowing what you've got is the first step in >>understanding what conclusions you can draw. >> >>Arpad & others - please correct me if I've gotten any of this wrong ... >> >>Todd. >> >>Todd Westerhoff >>VP, Software Products >>SiSoft >>6 Clock Tower Place, Suite 250 >>Maynard, MA 01754 >>(978) 461-0449 x24 >>twesterh@sisoft.com >>www.sisoft.com >>-----Original Message----- >>From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf >>Of Dimitry Eisenshtat >>Sent: Saturday, January 13, 2007 3:58 AM >>To: Todd Westerhoff >>Cc: ibis@eda-stds.org; ibis-users@eda.org >>Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour >> >>Todd, >>ok, we understand that time correlation between IBIS and HSpice is not >>guaranteed, but is it really problem? I mean, in the most often >>situation there is no place for such comparison at all, because you have >>only IBIS model, no spice netlist is available. This is the first reason >>for making IBIS (if simulator speed is not an issue), is it right? Lets >>say, I'm with semiconductor vendor side, I have the netlist of the >>buffer, I make the IBIS model based on spice simulations, not lab >>measurements, so on final step when the model is ready I like to check >>it vs. original spice behavioral. This is the only situation I agree the >>comparison is important. But in such case there is no REAL problem - I >>know exactly about the delay, and if it is the only difference between >>the IBIS & spice - I don't care. >> >>I want ask you about IBIS simulator aspect of the point we are talking >>about. Look, I find in "Cookbook for ver4" strongly recommendation to >>trim IBIS model time tables at least to half of max buffer frequency >>period. (http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf page 70, >>5.4.2 V-T Table Windowing). Can you please prefer from simulator >>software side - is it really problem for the simulator if the time table >>window is more then such time interval? And one additional point, you >>wrote "There are specific restrictions on how the dead time may be >>trimmed, which is a longer discussion" - right now I writes perl script >>which will trim tables in order to leave only transition region and >>decrease the time window as the Cookbook recommends to do. So, can you >>please explain about these restrictions? >> >>Thanks, >> Dmitry >> >>... (previous thread clipped) >> >> > > > - -- +---------------------------------------------------------+ | Dmitry Aizenshtat Circuit Design Engineer, NSTA | | Tel : 972-9-9702-020 Fax : 972-9-9702-001 | | mailto:dimita@taux01.nsc.com | +---------------------------------------------------------+ =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Winbond is strictly prohibited; and any information in this email irrelevant to the official business of Winbond shall be deemed as neither given nor endorsed by Winbond. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 17 Jan 2007 15:57:21 +0200 From: "Dimitry Eisenshtat" Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Todd, thanks for your comments. You are right, in step 2 I meant smallest (T1,T2) interval, of course. I think about Vtol and Tmin/2 (half of maximum freq period) as algorithm parameters, and I think may be more then one iteration will be needed, I mean we start with some initial small Vtol (because we want to keep maximum data points possible under "over clocking free" condition), run the algorithm, check the results - and if time window after trimming is still large then Tmin/2, we increase Vtol by some amount and run it again, until we get the desired final time window. By the way, it seems the ABSOLUTE value of |V(t)-Vendpoint/Vsupply| checking is must if we want keep some overshoots or undershoots near end points, if exist in original V/T curves. About step 4, I agree, printing of such comment into *.ibs file itself is a good idea. About the name conventions, why not, the convention you offered seems good exactly as any other possible. Dmitry. Todd Westerhoff wrote: > Dimitry, > > This is good stuff! I have a few very small comments: > > Step 2: I think you meant you're going to find the *smallest* T1 to T2 > interval that satisfies Vtol. Alternatively, you could find the largest > interval from start to T1. > > Step 4: Once you've made this computation, you can determine if you're going > to be able to shift ALL curves by the same amount and stay within the bit > time (i.e. maintain time correlation across min/typ/max), or if you need to > adjust curves by corner - in which case I'd print a message to that effect, > possibly as a comment in the IBIS file itself. > > Your conclusion about not needing time correlation across min/typ/max curves > is correct - each corner simulation gets paired with its own set of timing > data (slow/typ/fast) for timing analysis, so time-correlation between > corners isn't required. That having been said, it's good to preserve > time-correlation between corners when you can, simply because new users > won't necessarily understand the nuances of how SI results get paired with > static timing. > > I really like the way you've defined T1 and T2. I think it would be a good > idea to identify all the different curves as well: > > 1. [Min]/[Rising]/[50 ohm GND] > 2. [Min]/[Rising]/[50 ohm VDDQ] > 3. [Min]/[Falling]/[50 ohm GND] > 4. [Min]/[Falling]/[50 ohm VDDQ] > 5. [Typ]/[Rising]/[50 ohm GND] > 6. [Typ]/[Rising]/[50 ohm VDDQ] > 7. [Typ]/[Falling]/[50 ohm GND] > 8. [Typ]/[Falling]/[50 ohm VDDQ] > 9. [Max]/[Rising]/[50 ohm GND] > 10. [Max]/[Rising]/[50 ohm VDDQ] > 11. [Max]/[Falling]/[50 ohm GND] > 12. [Max]/[Falling]/[50 ohm VDDQ] > > .... or whatever other convention makes sense. That way, we could talk > about T1 for Curve 4 and know exactly what we're talking about ... > > Todd. > > Todd Westerhoff > VP, Software Products > SiSoft > 6 Clock Tower Place, Suite 250 > Maynard, MA 01754 > (978) 461-0449 x24 > twesterh@sisoft.com > www.sisoft.com > > -----Original Message----- > From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf > Of Dimitry Eisenshtat > Sent: Monday, January 15, 2007 5:02 PM > To: Todd Westerhoff > Cc: ibis@eda-stds.org; ibis-users@eda.org > Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour > > Hi Todd, > first of all - thanks for your reply, as I said, I'm writing script for > trimming V/T tables in order to satisfy Cookbook recommendation, so your > explanation is really useful. Thank you :) > > Ok, I see from your virtual DDR example that "over clocking" should > require special treatment on IBIS simulator side, and I finally decide > to avoid such situations and create IBIS models with V/T tables time > window up to half of minimum signal period the buffer designed for. > > Now some words about HOW I will do it. I think the most important point > you mentioned is "time correlation" of all given corner curves. I want > use simple algorithm for automatically trimming V/T curves, let me > explain. Lets say we have 12 transients, exactly as in your (most > common) example of push-pull buffer simulated in 3 corners with load of > 50 ohm once to supply, once to ground. The steps will be: > > 1) Run spice simulations (with s2ibis* or manually, does not matter) > with as small time step as it possible for simulation time large enough > for weakest conditions (corner/load) transition to be finally completed. > The idea is to begin with "ideal" time resolution for all transitions > regions in our 12 curves. > > 2) For each curve find largest time interval (T1,T2) which satisfy > voltage tolerance of delta from initial and final DC solutions, i.e. > |(V(T1)-Vstart)/VDD| < Vtol, > |(V(T2)-Vend)/VDD| < Vtol > where Vtol tolerance chosen smaller than IBISCHK's one so the checker > will not report "DC endpoints" warning on trimmed tables latter. All > data points outside of this interval (T1,T2) are declared "dead zones" > and have no importance. So the Vtol value actually plays as "dead zones" > definition criteria and should be the parameter to be changed if needed. > > 3) For all curves (rising/falling/load) of given corner find the minimum > T1 value, lets define it as T1_typ, T1_slow, T1_fast or T1_. > > 4) Calculate maximum interval dT_max = max {|T2-T1_|} for ALL > curves. > > 5) Shift all curves for given corner left in time by T1_ value. > > 6) Truncate all curves at time dT_max (from new 0 time after shifting) > > 7) Add one points to end of each curve in order to form a line with zero > slope for case of some simulators extrapolation will be needed. > > 8) Remember, we start from "the best" time resolution, so it is possible > that we get desire time window from overclocking point of view, but > number of points in final V/T tables still exceeds the maximum allowed > by IBIS spec. In this case I suggest to use "greatest change algorithm" > in order to decrease the number of tables points, as it described in > Cookbook (pages 63-64). > > As the result, if I have no mistake, we will get "corner time- > correlated" tables. However, across corners correlation is not > guaranteed. My assumption is that the user will be interested in > analyzing the buffer's (buffer itself, I mean not control logic but > pullup/pulldown devices which actually drive the pad) corner-specific > behavioral/differences, so I at least do not worsen the model quality, > or even improve it. Anyway, in some cases there will be no possibility > to satisfy "overclocking free" condition without shifting the corner's > curves one to each other, in other words without trimming different > amounts from different corners. > > Does it make sense? I like to complete realizing this algorithm in perl > and try it on last DDR2 model I produced. Only IBIS simulator I have is > HSpice, so the plan is to compare the behavioral of IBIS model before > and after trimming. I hope the HSpice is bad enough in "over clocking" > scenario, otherwise I will see no difference/improvements anyway :) > > Regards, > Dmitry > > > > - -- +---------------------------------------------------------+ | Dmitry Aizenshtat Circuit Design Engineer, NSTA | | Tel : 972-9-9702-020 Fax : 972-9-9702-001 | | mailto:dimita@taux01.nsc.com | +---------------------------------------------------------+ =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Winbond is strictly prohibited; and any information in this email irrelevant to the official business of Winbond shall be deemed as neither given nor endorsed by Winbond. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 17 Jan 2007 08:36:24 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Sorry, can't help you with a Linux version for my tool, or open source software other than the North Carolina offerings. Arpad ======================================================== - -----Original Message----- From: Dimitry Eisenshtat [mailto:Dimitry.Eisenshtat@winbond.com] Sent: Wednesday, January 17, 2007 5:33 AM To: Muranyi, Arpad Cc: ibis@eda-stds.org; ibis-users@eda.org Subject: Re: [IBIS-Users] RE: [IBIS] Ibis open drain strange behaviour Arpad, thanks for the link, I'm sure the IBIS overview pdf docs contain some info which will be new for me and so it will be useful, in other words I think it is good idea to read this stuff carefully and look for important points I not familiar with yet. My working environment is under RedHat Linux, so I have nothing to do with *.msi installation files of tool which you're using. Anyway, I prefer to deal with open source software, because if I have no source, I have no possibility to fix bugs (lets say no possibility even to try), and every piece of code has its bugs, you know. Especially when we talking about IBIS, at least from my point of view, the things is still in development, and sometimes there is a real need to improve some step in model generation process. By the way, I'll really happy to know that I have a mistake and some free open source s2ibis like software which supports all problematic issues (including C_comp calculations, differential buffers modeling, overclocking and maybe more "advanced" points) does exist. Do you know about such software? s2ibis2 is more then nothing, but not enough. s2ibis3 is more or less equivalent java version of s2ibis2. regards, Dmitry - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 25 Jan 2007 19:28:20 +0530 From: Sujit Kumar-r65837 Subject: [IBIS-Users] ibschk- warnings This is a multi-part message in MIME format. - --------------020305060401000203010406 Content-Type: multipart/alternative; boundary="------------010803020301060406090309" - --------------010803020301060406090309 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit hi ibis experts ibschk run on an ibis generates following warnings: IBISCHK4 V4.0.2 Checking ddr.ibs for IBIS 4.0 Compatibility... WARNING (line 219) - GND Clamp Typical data is non-monotonic WARNING (line 219) - GND Clamp Minimum data is non-monotonic WARNING (line 219) - GND Clamp Maximum data is non-monotonic WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture]=0V has TYP column DC endpoints of 0.00V and 0.18v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.01V and 0.18V), a difference of 4.10% and 3.91%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform] with [R_fixture]=500 Ohms and [V_fixture]=1.8V has TYP column DC endpoints of 0.47V and 1.80v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.50V and 1.80V), a difference of 2.18% and 0.00%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform] with [R_fixture]=500 Ohms and [V_fixture_min]=0V has MIN column DC endpoints of 0.00V and 0.96v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.02V and 0.96V), a difference of 2.14% and 0.59%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture_min]=0V has MIN column DC endpoints of 0.00V and 0.12v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.01V and 0.13V), a difference of 4.58% and 4.47%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform] with [R_fixture]=500 Ohms and [V_fixture_min]=1.65V has MIN column DC endpoints of 0.64V and 1.65v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.67V and 1.65V), a difference of 2.83% and 0.00%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture_max]=0V has MAX column DC endpoints of 0.00V and 0.24v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.01V and 0.25V), a difference of 3.89% and 3.60%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform] with [R_fixture]=500 Ohms and [V_fixture_max]=1.95V has MAX column DC endpoints of 0.39V and 1.95v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.42V and 1.95V), a difference of 2.06% and 0.01%, respectively. Errors : 0 Warnings: 10 File Passed i have following queries: > what could be the possible reason for such warnings ? > as file is passing throgh ibschk, so can i neglect the above warnings ? pls suggest. .s2i and ibs file are attached for reference. - -- thanks sujit kumar +91-120-4396069 +91-09910168788 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --------------010803020301060406090309 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit hi ibis experts
ibschk run on an ibis generates following warnings:

IBISCHK4 V4.0.2

Checking ddr.ibs for IBIS 4.0 Compatibility...

WARNING (line  219) - GND Clamp Typical data is non-monotonic
WARNING (line  219) - GND Clamp Minimum data is non-monotonic
WARNING (line  219) - GND Clamp Maximum data is non-monotonic
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]
      with [R_fixture]=50 Ohms and [V_fixture]=0V
      has TYP column DC endpoints of  0.00V and  0.18v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.01V and  0.18V),
      a difference of  4.10% and  3.91%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform]
      with [R_fixture]=500 Ohms and [V_fixture]=1.8V
      has TYP column DC endpoints of  0.47V and  1.80v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.50V and  1.80V),
      a difference of  2.18% and  0.00%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]
      with [R_fixture]=500 Ohms and [V_fixture_min]=0V
      has MIN column DC endpoints of  0.00V and  0.96v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.02V and  0.96V),
      a difference of  2.14% and  0.59%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]
      with [R_fixture]=50 Ohms and [V_fixture_min]=0V
      has MIN column DC endpoints of  0.00V and  0.12v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.01V and  0.13V),
      a difference of  4.58% and  4.47%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform]
      with [R_fixture]=500 Ohms and [V_fixture_min]=1.65V
      has MIN column DC endpoints of  0.64V and  1.65v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.67V and  1.65V),
      a difference of  2.83% and  0.00%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]
      with [R_fixture]=50 Ohms and [V_fixture_max]=0V
      has MAX column DC endpoints of  0.00V and  0.24v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.01V and  0.25V),
      a difference of  3.89% and  3.60%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform]
      with [R_fixture]=500 Ohms and [V_fixture_max]=1.95V
      has MAX column DC endpoints of  0.39V and  1.95v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.42V and  1.95V),
      a difference of  2.06% and  0.01%, respectively.

Errors  : 0
Warnings: 10

File Passed

i have following queries:
>  what could be the possible reason for such warnings ?
>  as  file is passing throgh ibschk, so can i neglect the above warnings ?

pls suggest.
.s2i and ibs file are attached for reference.


--
thanks
sujit kumar




+91-120-4396069
+91-09910168788



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believed to be clean. - --------------010803020301060406090309-- - --------------020305060401000203010406 Content-Type: text/plain; name="ddr.s2i" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="ddr.s2i" [IBIS Ver] 2.1 [File rev] 1.0 [Date] Jan 16,2007 [Source] Freescale Semiconductor India Pvt Ltd. [Notes] DDR I/O IBIS model for skyeplus [Disclaimer] Property of Freescale Incorporated. Unauthorized reproduction and/or distribution is strictly prohibited. This product is protected under copyright law. Created 2006, (C) Copyright 2006, Freescale Incorporated, All Rights Reserved UNLESS THERE IS A SIGNED, WRITTEN AGREEMENT TO THE CONTRARY, MOTOROLA IS PROVIDING THE IBIS MODELS AND WITHOUT ANY WARRANTY, EXPRESSED OR IMPLIED. Freescale assumes no liability for: 1) the accuracy of the IBIS models provided to your company; 2) the proper functioning of these IBIS Models in your design or for any resulting applications; or 3) infringement of patents, copyrights or intellectual property rights resulting from your use of these IBIS models. Freescale provides IBIS Models as a service to our customers. You and your company shall not distribute, sell or give these models to anyone else without prior written permission from Motorola. Freescale reserves the right to make changes to our products or to discontinue any semiconductor product or service without notice, and advises our customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. Please be aware that your receipt and use of the IBIS information provided shall serve as acceptance of these terms and conditions. If you do not accept these terms, you should return or destroy the IBIS models and any other accompanying information immediately. [Copyright] Copyright 2005 Freescale Inc., All Rights Reserved [Spice type] mica [Iterate] |[Cleanup] |[Summarize] 10 [Temperature Range] 25.0000 0.1050k -20.0000 [Voltage Range] 1.8000V 1.6500V 1.9500V | variable typ min max [R_pkg] 2.0000m 1.0000m 4.0000m [L_pkg] 0.2000nH 0.1000nH 0.4000nH [C_pkg] 2.0000pF 1.0000pF 4.0000pF [sim time] 8ns [tr] 25ps 25ps 25ps [tf] 25ps 25ps 25ps [rload] 50 [vil] 0 0 0 [vih] 1.20 1.10 1.30 [Component] Skyeplus [Manufacturer] Freescale Inc. [Spice file] ddr.mc [Pin] pad pad pad io_pu0_pk1_ddr0_lo - -> dout enb dout dout dout dummy enb enb enb dummy ovss ovss ovss GND ovdd ovdd ovdd POWER [Model] io_pu0_pk1_ddr0_lo [Model type] I/O [Polarity] Non-inverting [Enable] active-high [C_comp] 2.0200pF 1.9900pF 2.0300pF [Vinl] 0.54 [Vinh] 1.26 [Vmeas] 0.9 [Cref] 50p [Rref] 500 [Vref] 0 [Model file] typ.mod wcs.mod bcs.mod [Rising waveform] 500 0 0 0 NA NA NA NA NA [Falling waveform] 500 1.8 1.65 1.95 NA NA NA NA NA [Rising waveform] 50 0 0 0 NA NA NA NA NA [Falling waveform] 50 1.8 1.65 1.95 NA NA NA NA NA [Model] dummy [nomodel] - --------------020305060401000203010406 Content-Type: text/plain; name="ddr.ibs" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="ddr.ibs" |************************************************************************ | IBIS file ddr.ibs created by s2ibis2 version 2_6-Beta | North Carolina State University Electronics Research Laboratory 1995 |************************************************************************ | [IBIS ver] 4.0 [File name] ddr.ibs [File Rev] 1.0 [Date] Jan 16,2007 [Source] Freescale Semiconductor India Pvt Ltd. [Notes] DDR I/O IBIS model for skyeplus [Disclaimer] Property of Freescale Incorporated. Unauthorized reproduction and/or distribution is strictly prohibited. This product is protected under copyright law. Created 2006, (C) Copyright 2006, Freescale Incorporated, All Rights Reserved UNLESS THERE IS A SIGNED, WRITTEN AGREEMENT TO THE CONTRARY, MOTOROLA IS PROVIDING THE IBIS MODELS AND WITHOUT ANY WARRANTY, EXPRESSED OR IMPLIED. Freescale assumes no liability for: 1) the accuracy of the IBIS models provided to your company; 2) the proper functioning of these IBIS Models in your design or for any resulting applications; or 3) infringement of patents, copyrights or intellectual property rights resulting from your use of these IBIS models. Freescale provides IBIS Models as a service to our customers. You and your company shall not distribute, sell or give these models to anyone else without prior written permission from Motorola. Freescale reserves the right to make changes to our products or to discontinue any semiconductor product or service without notice, and ad ... [Copyright] Copyright 2005 Freescale Inc., All Rights Reserved | |************************************************************************ | Component Skyeplus |************************************************************************ | [Component] Skyeplus [Manufacturer] Freescale Inc. [Package] | variable typ min max R_pkg 2.0000m 1.0000m 4.0000m L_pkg 0.2000nH 0.1000nH 0.4000nH C_pkg 2.0000pF 1.0000pF 4.0000pF | [Pin] signal_name model_name R_pin L_pin C_pin pad pad io_pu0_pk1_ddr0_lo | dout dout dummy | enb enb dummy ovss ovss GND ovdd ovdd POWER | |************************************************************************ | Model io_pu0_pk1_ddr0_lo |************************************************************************ | [Model] io_pu0_pk1_ddr0_lo Model_type I/O Polarity Non-Inverting Enable Active-High Vinl = 0.5400V Vinh = 1.2600V Vmeas = 0.9000V Cref = 50.0000pF Rref = 0.5000k Vref = 0.000V C_comp 2.0200pF 1.9900pF 2.0300pF | | [Temperature Range] 25.0000 0.1050k -20.0000 [Voltage Range] 1.8000V 1.6500V 1.9500V [Pulldown] | voltage I(typ) I(min) I(max) | -1.8000 -0.1770mA -0.1800mA -0.1730mA -1.7000 -0.2030mA -0.2050mA -0.1980mA -1.6000 -0.2370mA -0.2390mA -0.2320mA -1.5000 -0.2850mA -0.2840mA -0.2780mA -1.4000 -0.3560mA -0.3531mA -0.3480mA -1.3000 -0.4732mA -0.4623mA -0.4614mA -1.2000 -0.6924mA -0.6571mA -0.6772mA -1.1000 -1.1961mA -1.0615mA -1.1894mA -1.0000 -2.6045mA -1.9870mA -2.8057mA -0.9000 -4.3820mA -3.1578mA -5.2707mA -0.8000 -4.4402mA -3.2792mA -5.3849mA -0.7000 -4.2065mA -3.0582mA -5.1801mA -0.6000 -3.8765mA -2.7704mA -4.8409mA -0.5000 -3.4461mA -2.4264mA -4.3563mA -0.4000 -2.8975mA -2.0189mA -3.6962mA -0.3000 -2.2377mA -1.5471mA -2.8776mA -0.2000 -1.5199mA -1.0359mA -1.9777mA -0.1000 -0.7738mA -0.5170mA -1.0210mA 0.0000 78.9700pA 64.0400pA 0.6308nA 0.1000 0.7317mA 0.4791mA 0.9815mA 0.2000 1.3554mA 0.8893mA 1.8202mA 0.3000 1.8790mA 1.2349mA 2.5269mA 0.4000 2.3082mA 1.5195mA 3.1075mA 0.5000 2.6435mA 1.7458mA 3.5540mA 0.6000 2.8738mA 1.9139mA 3.8386mA 0.7000 3.0024mA 2.0222mA 3.9843mA 0.8000 3.0722mA 2.0840mA 4.0627mA 0.9000 3.1166mA 2.1218mA 4.1145mA 1.0000 3.1509mA 2.1499mA 4.1567mA 1.1000 3.1831mA 2.1837mA 4.1952mA 1.2000 3.3805mA 2.3028mA 4.2357mA 1.3000 3.3973mA 2.3153mA 4.4908mA 1.4000 3.4108mA 2.3252mA 4.5075mA 1.5000 3.4215mA 2.3330mA 4.5207mA 1.6000 3.4299mA 2.3390mA 4.5311mA 1.7000 3.4365mA 2.3435mA 4.5392mA 1.8000 3.4413mA 2.3469mA 4.5451mA 1.9000 3.4558mA 2.4172mA 4.5422mA 2.0000 3.4723mA 2.7978mA 4.5590mA 2.1000 3.5631mA 3.8743mA 4.5754mA 2.2000 4.2085mA 5.6944mA 4.6014mA 2.3000 5.8282mA 8.2676mA 4.8910mA 2.4000 8.4137mA 12.8883mA 6.1950mA 2.5000 11.7769mA 38.3456mA 8.7770mA 2.6000 16.6566mA 0.1291A 12.3914mA 2.7000 48.9090mA 0.2661A 16.6983mA 2.8000 0.1604A 0.4222A 24.7422mA 2.9000 0.3111A 0.5874A 92.8945mA 3.0000 0.4756A 0.7575A 0.2333A 3.1000 0.6464A 0.9309A 0.3958A 3.2000 0.8208A 1.1064A 0.5666A 3.3000 0.9975A 1.2835A 0.7414A 3.4000 1.1758A 1.4618A 0.9187A 3.5000 1.3552A 1.6410A 1.0976A 3.6000 1.5354A 1.8209A 1.2776A | [Pullup] | voltage I(typ) I(min) I(max) | -1.8000 0.1400mA 0.1400mA 0.1500mA -1.7000 0.1600mA 0.1600mA 0.1700mA -1.6000 0.1900mA 0.1800mA 0.1900mA -1.5000 0.2250mA 0.2200mA 0.2300mA -1.4000 0.2770mA 0.2630mA 0.2880mA -1.3000 0.3540mA 0.3290mA 0.3710mA -1.2000 0.4800mA 0.4310mA 0.5070mA -1.1000 0.7120mA 0.6070mA 0.7710mA -1.0000 1.2270mA 0.9450mA 1.3960mA -0.9000 2.5829mA 1.6834mA 3.2954mA -0.8000 3.6223mA 2.6192mA 4.5614mA -0.7000 3.4485mA 2.6338mA 4.2455mA -0.6000 3.1033mA 2.3724mA 3.8476mA -0.5000 2.7039mA 2.0544mA 3.3824mA -0.4000 2.2371mA 1.6892mA 2.8241mA -0.3000 1.7007mA 1.2803mA 2.1629mA -0.2000 1.1261mA 0.8427mA 1.4436mA -0.1000 0.5566mA 0.4117mA 0.7202mA 0.0000 21.2100pA -0.5832nA 2.2960pA 0.1000 -0.5359mA -0.3901mA -0.7027mA 0.2000 -1.0231mA -0.7428mA -1.3458mA 0.3000 -1.4619mA -1.0580mA -1.9298mA 0.4000 -1.8527mA -1.3360mA -2.4554mA 0.5000 -2.1957mA -1.5769mA -2.9226mA 0.6000 -2.4911mA -1.7810mA -3.3310mA 0.7000 -2.7386mA -1.9489mA -3.6787mA 0.8000 -2.9381mA -2.0817mA -3.9627mA 0.9000 -3.0914mA -2.1827mA -4.1821mA 1.0000 -3.2055mA -2.2577mA -4.3447mA 1.1000 -3.2910mA -2.3144mA -4.4655mA 1.2000 -3.3573mA -2.3589mA -4.5581mA 1.3000 -3.4109mA -2.3954mA -4.6324mA 1.4000 -3.4560mA -2.4263mA -4.6941mA 1.5000 -3.4948mA -2.4532mA -4.7469mA 1.6000 -3.5291mA -2.4771mA -4.7933mA 1.7000 -3.5600mA -2.4990mA -4.8348mA 1.8000 -3.5882mA -2.5214mA -4.8725mA 1.9000 -3.6142mA -2.5753mA -4.9071mA 2.0000 -3.6398mA -2.8763mA -4.9392mA 2.1000 -3.7005mA -3.8357mA -4.9693mA 2.2000 -4.1340mA -5.5848mA -5.0003mA 2.3000 -5.5940mA -8.0339mA -5.1200mA 2.4000 -8.2201mA -11.1521mA -5.9779mA 2.5000 -11.7287mA -17.2174mA -8.3604mA 2.6000 -15.8625mA -55.4554mA -12.0937mA 2.7000 -24.1226mA -0.1906A -16.6275mA 2.8000 -95.0284mA -0.3946A -21.8149mA 2.9000 -0.2795A -0.6270A -47.2489mA 3.0000 -0.5099A -0.8726A -0.1962A 3.1000 -0.7573A -1.1257A -0.4211A 3.2000 -1.0127A -1.3834A -0.6682A 3.3000 -1.2728A -1.6443A -0.9246A 3.4000 -1.5360A -1.9074A -1.1860A 3.5000 -1.8014A -2.1723A -1.4504A 3.6000 -2.0682A -2.4385A -1.7169A | [GND_clamp] | voltage I(typ) I(min) I(max) | -1.8000 -2.0651A -2.0375A -2.1150A -1.7000 -1.7982A -1.7734A -1.8464A -1.6000 -1.5329A -1.5113A -1.5791A -1.5000 -1.2697A -1.2519A -1.3136A -1.4000 -1.0096A -0.9963A -1.0506A -1.3000 -0.7541A -0.7464A -0.7914A -1.2000 -0.5068A -0.5063A -0.5388A -1.1000 -0.2763A -0.2851A -0.2999A -1.0000 -91.6685mA -0.1083A -0.1008A -0.9000 -20.4744mA -25.0704mA -21.9332mA -0.8000 -12.2007mA -10.7449mA -14.0755mA -0.7000 -8.0919mA -6.9494mA -9.3225mA -0.6000 -4.6057mA -4.2048mA -5.1530mA -0.5000 -1.9957mA -2.1036mA -2.0455mA -0.4000 -0.5432mA -0.7551mA -0.4720mA -0.3000 -0.1102mA -0.1696mA -0.1103mA -0.2000 -48.9810uA -42.7947uA -62.3758uA -0.1000 -23.8512uA -16.6082uA -31.4078uA 0.0000 -2.2387nA -44.4298nA -0.9771nA 0.1000 22.6437uA 14.8425uA 30.3469uA 0.2000 42.8982uA 28.0060uA 57.7964uA 0.3000 60.7755uA 39.4886uA 82.3515uA 0.4000 76.2860uA 49.3000uA 0.1040mA 0.5000 89.4264uA 57.4491uA 0.1227mA 0.6000 0.1002mA 64.0685uA 0.1385mA 0.7000 0.1091mA 69.7489uA 0.1515mA 0.8000 0.1168mA 74.8660uA 0.1623mA 0.9000 0.1228mA 79.3462uA 0.1695mA 1.0000 0.1259mA 81.5132uA 0.1714mA 1.1000 0.1238mA 71.5554uA 0.1686mA 1.2000 -48.2734uA -27.5884uA 0.1583mA 1.3000 -42.8264uA -22.8107uA -70.1492uA 1.4000 -36.2008uA -17.2176uA -62.8418uA 1.5000 -28.5460uA -10.8663uA -54.0516uA 1.6000 -19.9435uA -3.7749uA -43.9714uA 1.7000 -10.4222uA 4.1011uA -32.7480uA 1.8000 1.8114nA 14.8215uA -20.4413uA | [POWER_clamp] | voltage I(typ) I(min) I(max) | -1.8000 1.5323A 1.5491A 1.5450A -1.7000 1.3521A 1.3704A 1.3639A -1.6000 1.1727A 1.1927A 1.1834A -1.5000 0.9945A 1.0164A 1.0040A -1.4000 0.8178A 0.8418A 0.8258A -1.3000 0.6434A 0.6699A 0.6497A -1.2000 0.4726A 0.5019A 0.4766A -1.1000 0.3081A 0.3406A 0.3092A -1.0000 0.1573A 0.1920A 0.1545A -0.9000 45.6313mA 73.0995mA 41.1090mA -0.8000 13.1555mA 17.5218mA 14.6114mA -0.7000 8.2404mA 7.6041mA 9.8179mA -0.6000 4.9126mA 4.4779mA 5.8663mA -0.5000 2.3548mA 2.3165mA 2.7557mA -0.4000 0.7523mA 0.8824mA 0.8233mA -0.3000 0.1135mA 0.1833mA 0.1117mA -0.2000 25.0040uA 28.0920uA 30.5030uA -0.1000 11.1082uA 8.6012uA 14.5486uA 0.0000 1.8114nA 56.2228nA 0.1541nA | [Ramp] | variable typ min max dV/dt_r 0.1061/0.7726n 73.7335m/1.2014n 0.1451/0.5055n dV/dt_f 0.1024/0.4919n 69.7638m/0.7616n 0.1353/0.3474n R_load = 50.0000 | [Rising Waveform] R_fixture = 0.5000k V_fixture = 0.000 V_fixture_min = 0.000 V_fixture_max = 0.000 | time V(typ) V(min) V(max) | 0.000S 0.2264uV 6.1660uV 52.1239nV 81.6327pS 0.2356uV 6.1723uV 68.1925nV 0.1633nS 0.2409uV 6.1693uV 0.4050uV 0.2449nS 0.3811uV 6.1737uV -1.4457uV 0.3265nS 0.6919uV 6.1692uV 72.6202uV 0.4082nS -2.6052uV 6.1745uV -0.1587mV 0.4898nS 52.6015uV 6.0997uV -1.5344mV 0.5714nS 38.2170uV 4.4609uV -4.7046mV 0.6531nS -0.6122mV 0.9418uV -7.7094mV 0.7347nS -1.6879mV 9.1579uV 6.4584mV 0.8163nS -3.8408mV 56.3510uV 51.1710mV 0.8980nS -6.4158mV 89.7821uV 0.1231V 0.9796nS -6.7018mV 16.0007uV 0.2272V 1.0612nS -3.9565mV -0.4047mV 0.3126V 1.1429nS 8.3712mV -1.6538mV 0.4029V 1.2245nS 38.5748mV -2.5778mV 0.5337V 1.3061nS 96.4386mV -4.2892mV 0.6330V 1.3878nS 0.1439V -5.3441mV 0.8810V 1.4694nS 0.1799V -5.3236mV 0.9813V 1.5510nS 0.2473V -5.0368mV 1.1205V 1.6327nS 0.2904V -4.4097mV 1.1907V 1.7143nS 0.3743V -0.4394mV 1.2816V 1.7959nS 0.4557V 8.5692mV 1.3200V 1.8776nS 0.5381V 16.7308mV 1.3584V 1.9592nS 0.6205V 38.0715mV 1.3860V 2.0408nS 0.6763V 52.1707mV 1.4031V 2.1224nS 0.7637V 83.5237mV 1.4201V 2.2041nS 0.8889V 0.1188V 1.4333V 2.2857nS 0.9377V 0.1475V 1.4378V 2.3673nS 0.9864V 0.1761V 1.4423V 2.4490nS 1.0502V 0.1941V 1.4454V 2.5306nS 1.0781V 0.2322V 1.4467V 2.6122nS 1.1061V 0.2703V 1.4480V 2.6939nS 1.1451V 0.2997V 1.4495V 2.7755nS 1.1561V 0.3415V 1.4498V 2.8571nS 1.1672V 0.3833V 1.4501V 2.9388nS 1.1783V 0.4459V 1.4504V 3.0204nS 1.1893V 0.4832V 1.4508V 3.1020nS 1.1985V 0.5204V 1.4510V 3.1837nS 1.2017V 0.5577V 1.4511V 3.2653nS 1.2050V 0.5949V 1.4512V 3.3469nS 1.2082V 0.6188V 1.4514V 3.4286nS 1.2114V 0.6566V 1.4515V 3.5102nS 1.2123V 0.6945V 1.4516V 3.5918nS 1.2131V 0.7324V 1.4517V 3.6735nS 1.2140V 0.7825V 1.4518V 3.7551nS 1.2148V 0.8028V 1.4519V 3.8367nS 1.2155V 0.8231V 1.4520V 3.9184nS 1.2158V 0.8434V 1.4520V 4.0000nS 1.2160V 0.8637V 1.4521V 4.0816nS 1.2163V 0.8813V 1.4522V 4.1633nS 1.2165V 0.8918V 1.4522V 4.2449nS 1.2167V 0.9022V 1.4523V 4.3265nS 1.2168V 0.9127V 1.4524V 4.4082nS 1.2170V 0.9232V 1.4524V 4.4898nS 1.2171V 0.9313V 1.4525V 4.5714nS 1.2172V 0.9354V 1.4525V 4.6531nS 1.2173V 0.9395V 1.4526V 4.7347nS 1.2174V 0.9436V 1.4526V 4.8163nS 1.2174V 0.9477V 1.4527V 4.8980nS 1.2175V 0.9505V 1.4527V 4.9796nS 1.2176V 0.9520V 1.4528V 5.0612nS 1.2176V 0.9536V 1.4528V 5.1429nS 1.2177V 0.9551V 1.4528V 5.2245nS 1.2178V 0.9567V 1.4529V 5.3061nS 1.2178V 0.9576V 1.4529V 5.3878nS 1.2179V 0.9582V 1.4529V 5.4694nS 1.2180V 0.9588V 1.4530V 5.5510nS 1.2180V 0.9594V 1.4530V 5.6327nS 1.2180V 0.9603V 1.4530V 5.7143nS 1.2181V 0.9605V 1.4530V 5.7959nS 1.2181V 0.9608V 1.4531V 5.8776nS 1.2182V 0.9610V 1.4531V 5.9592nS 1.2182V 0.9612V 1.4531V 6.0408nS 1.2182V 0.9615V 1.4531V 6.1224nS 1.2183V 0.9616V 1.4531V 6.2041nS 1.2183V 0.9617V 1.4532V 6.2857nS 1.2184V 0.9618V 1.4532V 6.3673nS 1.2184V 0.9619V 1.4532V 6.4490nS 1.2184V 0.9621V 1.4532V 6.5306nS 1.2184V 0.9621V 1.4532V 6.6122nS 1.2185V 0.9622V 1.4532V 6.6939nS 1.2185V 0.9623V 1.4533V 6.7755nS 1.2185V 0.9624V 1.4533V 6.8571nS 1.2185V 0.9624V 1.4533V 6.9388nS 1.2186V 0.9625V 1.4533V 7.0204nS 1.2186V 0.9625V 1.4533V 7.1020nS 1.2186V 0.9626V 1.4533V 7.1837nS 1.2186V 0.9626V 1.4533V 7.2653nS 1.2186V 0.9627V 1.4533V 7.3469nS 1.2187V 0.9627V 1.4533V 7.4286nS 1.2187V 0.9628V 1.4534V 7.5102nS 1.2187V 0.9628V 1.4534V 7.5918nS 1.2187V 0.9629V 1.4534V 7.6735nS 1.2187V 0.9629V 1.4534V 7.7551nS 1.2188V 0.9629V 1.4534V 7.8367nS 1.2188V 0.9629V 1.4534V 7.9184nS 1.2188V 0.9630V 1.4534V 8.0000nS 1.2188V 0.9630V 1.4534V | [Rising Waveform] R_fixture = 50.0000 V_fixture = 0.000 V_fixture_min = 0.000 V_fixture_max = 0.000 | time V(typ) V(min) V(max) | 0.000S 88.1815nV 1.7818uV 32.1883nV 81.6327pS 90.0526nV 1.7856uV 34.6551nV 0.1633nS 90.8363nV 1.7816uV 0.2894uV 0.2449nS 0.1837uV 1.7844uV -1.1728uV 0.3265nS 0.2555uV 1.7799uV 54.5396uV 0.4082nS -2.8821uV 1.7862uV -0.1606mV 0.4898nS 36.9661uV 1.7329uV -1.0784mV 0.5714nS 7.8647uV 0.6047uV -2.7310mV 0.6531nS -0.5132mV -1.0856uV -2.8716mV 0.7347nS -1.3781mV 6.4038uV 8.0819mV 0.8163nS -2.4176mV 35.2581uV 31.2094mV 0.8980nS -2.1150mV 43.0850uV 55.3842mV 0.9796nS -1.2927mV -23.3545uV 79.6073mV 1.0612nS 0.5453mV -0.2874mV 98.5085mV 1.1429nS 6.8700mV -0.9134mV 0.1220V 1.2245nS 19.9144mV -1.2745mV 0.1451V 1.3061nS 37.7666mV -1.7021mV 0.1663V 1.3878nS 47.6547mV -1.4177mV 0.1892V 1.4694nS 53.2698mV -0.8363mV 0.2065V 1.5510nS 65.1844mV -0.4301mV 0.2198V 1.6327nS 72.5819mV -88.3368uV 0.2322V 1.7143nS 87.2224mV 2.0106mV 0.2359V 1.7959nS 0.1004V 6.0081mV 0.2404V 1.8776nS 0.1137V 9.7247mV 0.2408V 1.9592nS 0.1271V 16.3606mV 0.2412V 2.0408nS 0.1348V 21.8269mV 0.2417V 2.1224nS 0.1458V 27.3619mV 0.2417V 2.2041nS 0.1599V 34.1444mV 0.2417V 2.2857nS 0.1638V 37.6828mV 0.2417V 2.3673nS 0.1677V 41.2212mV 0.2417V 2.4490nS 0.1733V 44.3127mV 0.2417V 2.5306nS 0.1741V 49.3217mV 0.2417V 2.6122nS 0.1749V 54.3307mV 0.2417V 2.6939nS 0.1758V 59.3396mV 0.2417V 2.7755nS 0.1766V 63.7377mV 0.2417V 2.8571nS 0.1766V 69.8142mV 0.2417V 2.9388nS 0.1766V 75.8907mV 0.2418V 3.0204nS 0.1766V 81.9672mV 0.2418V 3.1020nS 0.1767V 85.2228mV 0.2418V 3.1837nS 0.1767V 90.6678mV 0.2418V 3.2653nS 0.1767V 96.1128mV 0.2418V 3.3469nS 0.1767V 0.1016V 0.2418V 3.4286nS 0.1767V 0.1063V 0.2418V 3.5102nS 0.1767V 0.1090V 0.2418V 3.5918nS 0.1767V 0.1116V 0.2418V 3.6735nS 0.1767V 0.1142V 0.2418V 3.7551nS 0.1767V 0.1169V 0.2418V 3.8367nS 0.1767V 0.1189V 0.2418V 3.9184nS 0.1767V 0.1197V 0.2418V 4.0000nS 0.1767V 0.1204V 0.2418V 4.0816nS 0.1767V 0.1212V 0.2418V 4.1633nS 0.1767V 0.1219V 0.2418V 4.2449nS 0.1768V 0.1224V 0.2418V 4.3265nS 0.1768V 0.1225V 0.2418V 4.4082nS 0.1768V 0.1226V 0.2418V 4.4898nS 0.1768V 0.1227V 0.2418V 4.5714nS 0.1768V 0.1228V 0.2418V 4.6531nS 0.1768V 0.1228V 0.2419V 4.7347nS 0.1768V 0.1229V 0.2419V 4.8163nS 0.1768V 0.1229V 0.2419V 4.8980nS 0.1768V 0.1229V 0.2419V 4.9796nS 0.1768V 0.1229V 0.2419V 5.0612nS 0.1768V 0.1229V 0.2419V 5.1429nS 0.1768V 0.1229V 0.2419V 5.2245nS 0.1768V 0.1229V 0.2419V 5.3061nS 0.1768V 0.1229V 0.2419V 5.3878nS 0.1768V 0.1229V 0.2419V 5.4694nS 0.1768V 0.1229V 0.2419V 5.5510nS 0.1768V 0.1229V 0.2419V 5.6327nS 0.1768V 0.1229V 0.2419V 5.7143nS 0.1768V 0.1229V 0.2419V 5.7959nS 0.1768V 0.1229V 0.2419V 5.8776nS 0.1768V 0.1229V 0.2419V 5.9592nS 0.1768V 0.1229V 0.2419V 6.0408nS 0.1768V 0.1229V 0.2419V 6.1224nS 0.1768V 0.1229V 0.2419V 6.2041nS 0.1768V 0.1229V 0.2419V 6.2857nS 0.1768V 0.1229V 0.2419V 6.3673nS 0.1768V 0.1230V 0.2419V 6.4490nS 0.1768V 0.1230V 0.2419V 6.5306nS 0.1768V 0.1230V 0.2419V 6.6122nS 0.1768V 0.1230V 0.2419V 6.6939nS 0.1768V 0.1230V 0.2419V 6.7755nS 0.1768V 0.1230V 0.2419V 6.8571nS 0.1768V 0.1230V 0.2419V 6.9388nS 0.1768V 0.1230V 0.2419V 7.0204nS 0.1768V 0.1230V 0.2419V 7.1020nS 0.1768V 0.1230V 0.2419V 7.1837nS 0.1768V 0.1230V 0.2419V 7.2653nS 0.1768V 0.1230V 0.2419V 7.3469nS 0.1768V 0.1230V 0.2419V 7.4286nS 0.1768V 0.1230V 0.2419V 7.5102nS 0.1768V 0.1230V 0.2419V 7.5918nS 0.1768V 0.1230V 0.2419V 7.6735nS 0.1768V 0.1230V 0.2419V 7.7551nS 0.1768V 0.1230V 0.2419V 7.8367nS 0.1768V 0.1230V 0.2419V 7.9184nS 0.1768V 0.1230V 0.2419V 8.0000nS 0.1768V 0.1230V 0.2419V | [Falling Waveform] R_fixture = 0.5000k V_fixture = 1.8000 V_fixture_min = 1.6500 V_fixture_max = 1.9500 | time V(typ) V(min) V(max) | 0.000S 1.8000V 1.6500V 1.9500V 81.6327pS 1.8000V 1.6500V 1.9500V 0.1633nS 1.8000V 1.6500V 1.9500V 0.2449nS 1.8000V 1.6500V 1.9500V 0.3265nS 1.8000V 1.6500V 1.9500V 0.4082nS 1.8000V 1.6500V 1.9523V 0.4898nS 1.7999V 1.6500V 1.9554V 0.5714nS 1.8005V 1.6500V 1.9585V 0.6531nS 1.8029V 1.6500V 1.9609V 0.7347nS 1.8053V 1.6499V 1.9498V 0.8163nS 1.8071V 1.6499V 1.9247V 0.8980nS 1.8086V 1.6502V 1.8636V 0.9796nS 1.8095V 1.6512V 1.7381V 1.0612nS 1.8040V 1.6525V 1.5298V 1.1429nS 1.7877V 1.6540V 1.4002V 1.2245nS 1.7516V 1.6552V 1.2672V 1.3061nS 1.7062V 1.6560V 1.1134V 1.3878nS 1.6693V 1.6568V 1.0217V 1.4694nS 1.5836V 1.6572V 0.7842V 1.5510nS 1.5189V 1.6572V 0.7036V 1.6327nS 1.4085V 1.6566V 0.6006V 1.7143nS 1.2921V 1.6563V 0.5484V 1.7959nS 1.1938V 1.6499V 0.4796V 1.8776nS 1.0602V 1.6380V 0.4564V 1.9592nS 0.9858V 1.6318V 0.4333V 2.0408nS 0.9114V 1.5969V 0.4176V 2.1224nS 0.8571V 1.5680V 0.4086V 2.2041nS 0.7874V 1.5390V 0.3996V 2.2857nS 0.6856V 1.5185V 0.3949V 2.3673nS 0.6527V 1.4696V 0.3928V 2.4490nS 0.6198V 1.4208V 0.3907V 2.5306nS 0.5869V 1.3915V 0.3895V 2.6122nS 0.5681V 1.3316V 0.3890V 2.6939nS 0.5480V 1.2716V 0.3885V 2.7755nS 0.5279V 1.2043V 0.3879V 2.8571nS 0.5106V 1.1546V 0.3877V 2.9388nS 0.5042V 1.1050V 0.3876V 3.0204nS 0.4977V 1.0554V 0.3875V 3.1020nS 0.4912V 1.0223V 0.3874V 3.1837nS 0.4867V 0.9782V 0.3872V 3.2653nS 0.4847V 0.9340V 0.3871V 3.3469nS 0.4827V 0.8746V 0.3870V 3.4286nS 0.4808V 0.8505V 0.3869V 3.5102nS 0.4797V 0.8263V 0.3868V 3.5918nS 0.4791V 0.8022V 0.3867V 3.6735nS 0.4785V 0.7780V 0.3867V 3.7551nS 0.4779V 0.7602V 0.3866V 3.8367nS 0.4771V 0.7456V 0.3865V 3.9184nS 0.4769V 0.7310V 0.3865V 4.0000nS 0.4768V 0.7164V 0.3864V 4.0816nS 0.4766V 0.7018V 0.3863V 4.1633nS 0.4764V 0.6925V 0.3863V 4.2449nS 0.4762V 0.6857V 0.3862V 4.3265nS 0.4761V 0.6789V 0.3862V 4.4082nS 0.4761V 0.6722V 0.3861V 4.4898nS 0.4760V 0.6654V 0.3861V 4.5714nS 0.4759V 0.6617V 0.3860V 4.6531nS 0.4758V 0.6588V 0.3860V 4.7347nS 0.4757V 0.6559V 0.3859V 4.8163nS 0.4756V 0.6529V 0.3859V 4.8980nS 0.4756V 0.6487V 0.3859V 4.9796nS 0.4755V 0.6477V 0.3858V 5.0612nS 0.4754V 0.6466V 0.3858V 5.1429nS 0.4754V 0.6456V 0.3858V 5.2245nS 0.4753V 0.6445V 0.3857V 5.3061nS 0.4753V 0.6431V 0.3857V 5.3878nS 0.4752V 0.6427V 0.3857V 5.4694nS 0.4752V 0.6422V 0.3856V 5.5510nS 0.4751V 0.6417V 0.3856V 5.6327nS 0.4751V 0.6412V 0.3856V 5.7143nS 0.4750V 0.6407V 0.3856V 5.7959nS 0.4750V 0.6404V 0.3855V 5.8776nS 0.4749V 0.6402V 0.3855V 5.9592nS 0.4749V 0.6398V 0.3855V 6.0408nS 0.4749V 0.6396V 0.3855V 6.1224nS 0.4748V 0.6395V 0.3855V 6.2041nS 0.4748V 0.6393V 0.3855V 6.2857nS 0.4748V 0.6391V 0.3854V 6.3673nS 0.4748V 0.6390V 0.3854V 6.4490nS 0.4747V 0.6389V 0.3854V 6.5306nS 0.4747V 0.6389V 0.3854V 6.6122nS 0.4747V 0.6388V 0.3854V 6.6939nS 0.4746V 0.6387V 0.3854V 6.7755nS 0.4746V 0.6386V 0.3853V 6.8571nS 0.4746V 0.6385V 0.3853V 6.9388nS 0.4746V 0.6384V 0.3853V 7.0204nS 0.4745V 0.6383V 0.3853V 7.1020nS 0.4745V 0.6383V 0.3853V 7.1837nS 0.4745V 0.6382V 0.3853V 7.2653nS 0.4745V 0.6382V 0.3853V 7.3469nS 0.4745V 0.6381V 0.3853V 7.4286nS 0.4745V 0.6381V 0.3853V 7.5102nS 0.4744V 0.6380V 0.3853V 7.5918nS 0.4744V 0.6380V 0.3852V 7.6735nS 0.4744V 0.6379V 0.3852V 7.7551nS 0.4744V 0.6379V 0.3852V 7.8367nS 0.4744V 0.6379V 0.3852V 7.9184nS 0.4744V 0.6378V 0.3852V 8.0000nS 0.4743V 0.6378V 0.3852V | [Falling Waveform] R_fixture = 50.0000 V_fixture = 1.8000 V_fixture_min = 1.6500 V_fixture_max = 1.9500 | time V(typ) V(min) V(max) | 0.000S 1.8000V 1.6500V 1.9500V 81.6327pS 1.8000V 1.6500V 1.9500V 0.1633nS 1.8000V 1.6500V 1.9500V 0.2449nS 1.8000V 1.6500V 1.9500V 0.3265nS 1.8000V 1.6500V 1.9500V 0.4082nS 1.8000V 1.6500V 1.9517V 0.4898nS 1.7999V 1.6500V 1.9530V 0.5714nS 1.8004V 1.6500V 1.9538V 0.6531nS 1.8018V 1.6500V 1.9528V 0.7347nS 1.8024V 1.6500V 1.9435V 0.8163nS 1.8026V 1.6500V 1.9287V 0.8980nS 1.8028V 1.6502V 1.9012V 0.9796nS 1.8020V 1.6508V 1.8591V 1.0612nS 1.7974V 1.6514V 1.8056V 1.1429nS 1.7882V 1.6517V 1.7851V 1.2245nS 1.7723V 1.6518V 1.7635V 1.3061nS 1.7589V 1.6518V 1.7505V 1.3878nS 1.7475V 1.6516V 1.7391V 1.4694nS 1.7269V 1.6513V 1.7345V 1.5510nS 1.7114V 1.6508V 1.7299V 1.6327nS 1.6918V 1.6504V 1.7267V 1.7143nS 1.6714V 1.6501V 1.7259V 1.7959nS 1.6612V 1.6464V 1.7250V 1.8776nS 1.6510V 1.6414V 1.7249V 1.9592nS 1.6458V 1.6378V 1.7248V 2.0408nS 1.6410V 1.6298V 1.7247V 2.1224nS 1.6361V 1.6258V 1.7247V 2.2041nS 1.6337V 1.6165V 1.7246V 2.2857nS 1.6326V 1.6082V 1.7246V 2.3673nS 1.6315V 1.5997V 1.7246V 2.4490nS 1.6304V 1.5911V 1.7246V 2.5306nS 1.6298V 1.5838V 1.7246V 2.6122nS 1.6297V 1.5761V 1.7246V 2.6939nS 1.6296V 1.5685V 1.7246V 2.7755nS 1.6295V 1.5575V 1.7246V 2.8571nS 1.6294V 1.5539V 1.7246V 2.9388nS 1.6294V 1.5503V 1.7246V 3.0204nS 1.6294V 1.5466V 1.7246V 3.1020nS 1.6294V 1.5417V 1.7246V 3.1837nS 1.6293V 1.5405V 1.7245V 3.2653nS 1.6293V 1.5393V 1.7245V 3.3469nS 1.6293V 1.5380V 1.7245V 3.4286nS 1.6293V 1.5368V 1.7245V 3.5102nS 1.6293V 1.5353V 1.7245V 3.5918nS 1.6293V 1.5350V 1.7245V 3.6735nS 1.6293V 1.5348V 1.7245V 3.7551nS 1.6293V 1.5345V 1.7245V 3.8367nS 1.6293V 1.5343V 1.7245V 3.9184nS 1.6293V 1.5340V 1.7245V 4.0000nS 1.6293V 1.5340V 1.7245V 4.0816nS 1.6293V 1.5339V 1.7245V 4.1633nS 1.6293V 1.5339V 1.7245V 4.2449nS 1.6293V 1.5338V 1.7245V 4.3265nS 1.6293V 1.5338V 1.7245V 4.4082nS 1.6293V 1.5338V 1.7245V 4.4898nS 1.6293V 1.5338V 1.7245V 4.5714nS 1.6293V 1.5338V 1.7245V 4.6531nS 1.6293V 1.5337V 1.7245V 4.7347nS 1.6293V 1.5337V 1.7245V 4.8163nS 1.6293V 1.5337V 1.7245V 4.8980nS 1.6293V 1.5337V 1.7245V 4.9796nS 1.6293V 1.5337V 1.7245V 5.0612nS 1.6293V 1.5337V 1.7245V 5.1429nS 1.6293V 1.5337V 1.7245V 5.2245nS 1.6293V 1.5337V 1.7245V 5.3061nS 1.6293V 1.5337V 1.7245V 5.3878nS 1.6293V 1.5337V 1.7245V 5.4694nS 1.6293V 1.5337V 1.7245V 5.5510nS 1.6293V 1.5337V 1.7245V 5.6327nS 1.6293V 1.5337V 1.7245V 5.7143nS 1.6293V 1.5337V 1.7245V 5.7959nS 1.6293V 1.5337V 1.7245V 5.8776nS 1.6293V 1.5337V 1.7245V 5.9592nS 1.6293V 1.5337V 1.7245V 6.0408nS 1.6293V 1.5337V 1.7245V 6.1224nS 1.6293V 1.5337V 1.7245V 6.2041nS 1.6293V 1.5337V 1.7245V 6.2857nS 1.6293V 1.5337V 1.7245V 6.3673nS 1.6293V 1.5337V 1.7245V 6.4490nS 1.6293V 1.5337V 1.7245V 6.5306nS 1.6293V 1.5337V 1.7245V 6.6122nS 1.6293V 1.5337V 1.7245V 6.6939nS 1.6293V 1.5337V 1.7245V 6.7755nS 1.6293V 1.5337V 1.7245V 6.8571nS 1.6293V 1.5337V 1.7245V 6.9388nS 1.6293V 1.5337V 1.7245V 7.0204nS 1.6293V 1.5337V 1.7245V 7.1020nS 1.6293V 1.5337V 1.7245V 7.1837nS 1.6293V 1.5337V 1.7245V 7.2653nS 1.6293V 1.5337V 1.7245V 7.3469nS 1.6293V 1.5337V 1.7245V 7.4286nS 1.6293V 1.5337V 1.7245V 7.5102nS 1.6293V 1.5337V 1.7245V 7.5918nS 1.6293V 1.5337V 1.7245V 7.6735nS 1.6293V 1.5337V 1.7245V 7.7551nS 1.6293V 1.5337V 1.7245V 7.8367nS 1.6293V 1.5337V 1.7245V 7.9184nS 1.6293V 1.5337V 1.7245V 8.0000nS 1.6293V 1.5337V 1.7245V | | End [Model] io_pu0_pk1_ddr0_lo | | End [Component] Skyeplus | [End] - --------------020305060401000203010406-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 25 Jan 2007 15:19:53 +0100 From: Lars Snith Subject: Re: [IBIS-Users] ibschk- warnings Hello Sujit, The non-monotonicity is usually only when noise exceeds delta, like in the following lines: 0.000S 0.2264uV 6.1660uV 52.1239nV 81.6327pS 0.2356uV 6.1723uV 68.1925nV 0.1633nS 0.2409uV 6.1693uV 0.4050uV Nothing to worry about when your voltage/current is anyway close to zero. The waveform warnings could be caused by either short simulation time and/or selection of load. You can read more about both issues here: http://www.ece.ncsu.edu/erl/ibis/faq/S2IBIS3_FAQ.htm#_A1 Best regards, Lars Snith Sujit Kumar-r65837 wrote: > hi ibis experts > ibschk run on an ibis generates following warnings: > Errors : 0 > Warnings: 10 > > File Passed* > > i have following queries: > > what could be the possible reason for such warnings ? > > as file is passing throgh ibschk, so can i neglect the above warnings ? > > pls suggest. > .s2i and ibs file are attached for reference. - -- Those who can, Do Those who can't, Simulate - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 25 Jan 2007 08:28:15 -0700 From: April.Hachenburg@smsc.com Subject: Re: [IBIS-Users] ibschk- warnings This is a multipart message in MIME format. - --=_alternative 0054FAC10725726E_= Content-Type: text/plain; charset="US-ASCII" Sujit, Your 50ohm rising and falling waveforms are not switching sufficiently. Your driver is too weak, so you may have to boost your minimum load. - - April - --------------------------------------------------- April Hachenburg Core Technology Design Engineer SMSC - Phoenix Sujit Kumar-r65837 Sent by: owner-ibis-users@server.eda.org 01/25/2007 06:58 AM To ibis-users@server.eda.org cc Subject [IBIS-Users] ibschk- warnings hi ibis experts ibschk run on an ibis generates following warnings: IBISCHK4 V4.0.2 Checking ddr.ibs for IBIS 4.0 Compatibility... WARNING (line 219) - GND Clamp Typical data is non-monotonic WARNING (line 219) - GND Clamp Minimum data is non-monotonic WARNING (line 219) - GND Clamp Maximum data is non-monotonic WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture]=0V has TYP column DC endpoints of 0.00V and 0.18v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.01V and 0.18V), a difference of 4.10% and 3.91%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform] with [R_fixture]=500 Ohms and [V_fixture]=1.8V has TYP column DC endpoints of 0.47V and 1.80v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.50V and 1.80V), a difference of 2.18% and 0.00%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform] with [R_fixture]=500 Ohms and [V_fixture_min]=0V has MIN column DC endpoints of 0.00V and 0.96v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.02V and 0.96V), a difference of 2.14% and 0.59%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture_min]=0V has MIN column DC endpoints of 0.00V and 0.12v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.01V and 0.13V), a difference of 4.58% and 4.47%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform] with [R_fixture]=500 Ohms and [V_fixture_min]=1.65V has MIN column DC endpoints of 0.64V and 1.65v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.67V and 1.65V), a difference of 2.83% and 0.00%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture_max]=0V has MAX column DC endpoints of 0.00V and 0.24v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.01V and 0.25V), a difference of 3.89% and 3.60%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform] with [R_fixture]=500 Ohms and [V_fixture_max]=1.95V has MAX column DC endpoints of 0.39V and 1.95v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.42V and 1.95V), a difference of 2.06% and 0.01%, respectively. Errors : 0 Warnings: 10 File Passed i have following queries: > what could be the possible reason for such warnings ? > as file is passing throgh ibschk, so can i neglect the above warnings ? pls suggest. .s2i and ibs file are attached for reference. - -- thanks sujit kumar +91-120-4396069 +91-09910168788 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. [IBIS Ver] 2.1 [File rev] 1.0 [Date] Jan 16,2007 [Source] Freescale Semiconductor India Pvt Ltd. [Notes] DDR I/O IBIS model for skyeplus [Disclaimer] Property of Freescale Incorporated. Unauthorized reproduction and/or distribution is strictly prohibited. This product is protected under copyright law. Created 2006, (C) Copyright 2006, Freescale Incorporated, All Rights Reserved UNLESS THERE IS A SIGNED, WRITTEN AGREEMENT TO THE CONTRARY, MOTOROLA IS PROVIDING THE IBIS MODELS AND WITHOUT ANY WARRANTY, EXPRESSED OR IMPLIED. Freescale assumes no liability for: 1) the accuracy of the IBIS models provided to your company; 2) the proper functioning of these IBIS Models in your design or for any resulting applications; or 3) infringement of patents, copyrights or intellectual property rights resulting from your use of these IBIS models. Freescale provides IBIS Models as a service to our customers. You and your company shall not distribute, sell or give these models to anyone else without prior written permission from Motorola. Freescale reserves the right to make changes to our products or to discontinue any semiconductor product or service without notice, and advises our customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. Please be aware that your receipt and use of the IBIS information provided shall serve as acceptance of these terms and conditions. If you do not accept these terms, you should return or destroy the IBIS models and any other accompanying information immediately. [Copyright] Copyright 2005 Freescale Inc., All Rights Reserved [Spice type] mica [Iterate] |[Cleanup] |[Summarize] 10 [Temperature Range] 25.0000 0.1050k -20.0000 [Voltage Range] 1.8000V 1.6500V 1.9500V | variable typ min max [R_pkg] 2.0000m 1.0000m 4.0000m [L_pkg] 0.2000nH 0.1000nH 0.4000nH [C_pkg] 2.0000pF 1.0000pF 4.0000pF [sim time] 8ns [tr] 25ps 25ps 25ps [tf] 25ps 25ps 25ps [rload] 50 [vil] 0 0 0 [vih] 1.20 1.10 1.30 [Component] Skyeplus [Manufacturer] Freescale Inc. [Spice file] ddr.mc [Pin] pad pad pad io_pu0_pk1_ddr0_lo - -> dout enb dout dout dout dummy enb enb enb dummy ovss ovss ovss GND ovdd ovdd ovdd POWER [Model] io_pu0_pk1_ddr0_lo [Model type] I/O [Polarity] Non-inverting [Enable] active-high [C_comp] 2.0200pF 1.9900pF 2.0300pF [Vinl] 0.54 [Vinh] 1.26 [Vmeas] 0.9 [Cref] 50p [Rref] 500 [Vref] 0 [Model file] typ.mod wcs.mod bcs.mod [Rising waveform] 500 0 0 0 NA NA NA NA NA [Falling waveform] 500 1.8 1.65 1.95 NA NA NA NA NA [Rising waveform] 50 0 0 0 NA NA NA NA NA [Falling waveform] 50 1.8 1.65 1.95 NA NA NA NA NA [Model] dummy [nomodel] |************************************************************************ | IBIS file ddr.ibs created by s2ibis2 version 2_6-Beta | North Carolina State University Electronics Research Laboratory 1995 |************************************************************************ | [IBIS ver] 4.0 [File name] ddr.ibs [File Rev] 1.0 [Date] Jan 16,2007 [Source] Freescale Semiconductor India Pvt Ltd. [Notes] DDR I/O IBIS model for skyeplus [Disclaimer] Property of Freescale Incorporated. Unauthorized reproduction and/or distribution is strictly prohibited. This product is protected under copyright law. Created 2006, (C) Copyright 2006, Freescale Incorporated, All Rights Reserved UNLESS THERE IS A SIGNED, WRITTEN AGREEMENT TO THE CONTRARY, MOTOROLA IS PROVIDING THE IBIS MODELS AND WITHOUT ANY WARRANTY, EXPRESSED OR IMPLIED. Freescale assumes no liability for: 1) the accuracy of the IBIS models provided to your company; 2) the proper functioning of these IBIS Models in your design or for any resulting applications; or 3) infringement of patents, copyrights or intellectual property rights resulting from your use of these IBIS models. Freescale provides IBIS Models as a service to our customers. You and your company shall not distribute, sell or give these models to anyone else without prior written permission from Motorola. Freescale reserves the right to make changes to our products or to discontinue any semiconductor product or service without notice, and ad ... [Copyright] Copyright 2005 Freescale Inc., All Rights Reserved | |************************************************************************ | Component Skyeplus |************************************************************************ | [Component] Skyeplus [Manufacturer] Freescale Inc. [Package] | variable typ min max R_pkg 2.0000m 1.0000m 4.0000m L_pkg 0.2000nH 0.1000nH 0.4000nH C_pkg 2.0000pF 1.0000pF 4.0000pF | [Pin] signal_name model_name R_pin L_pin C_pin pad pad io_pu0_pk1_ddr0_lo | dout dout dummy | enb enb dummy ovss ovss GND ovdd ovdd POWER | |************************************************************************ | Model io_pu0_pk1_ddr0_lo |************************************************************************ | [Model] io_pu0_pk1_ddr0_lo Model_type I/O Polarity Non-Inverting Enable Active-High Vinl = 0.5400V Vinh = 1.2600V Vmeas = 0.9000V Cref = 50.0000pF Rref = 0.5000k Vref = 0.000V C_comp 2.0200pF 1.9900pF 2.0300pF | | [Temperature Range] 25.0000 0.1050k -20.0000 [Voltage Range] 1.8000V 1.6500V 1.9500V [Pulldown] | voltage I(typ) I(min) I(max) | -1.8000 -0.1770mA -0.1800mA -0.1730mA -1.7000 -0.2030mA -0.2050mA -0.1980mA -1.6000 -0.2370mA -0.2390mA -0.2320mA -1.5000 -0.2850mA -0.2840mA -0.2780mA -1.4000 -0.3560mA -0.3531mA -0.3480mA -1.3000 -0.4732mA -0.4623mA -0.4614mA -1.2000 -0.6924mA -0.6571mA -0.6772mA -1.1000 -1.1961mA -1.0615mA -1.1894mA -1.0000 -2.6045mA -1.9870mA -2.8057mA -0.9000 -4.3820mA -3.1578mA -5.2707mA -0.8000 -4.4402mA -3.2792mA -5.3849mA -0.7000 -4.2065mA -3.0582mA -5.1801mA -0.6000 -3.8765mA -2.7704mA -4.8409mA -0.5000 -3.4461mA -2.4264mA -4.3563mA -0.4000 -2.8975mA -2.0189mA -3.6962mA -0.3000 -2.2377mA -1.5471mA -2.8776mA -0.2000 -1.5199mA -1.0359mA -1.9777mA -0.1000 -0.7738mA -0.5170mA -1.0210mA 0.0000 78.9700pA 64.0400pA 0.6308nA 0.1000 0.7317mA 0.4791mA 0.9815mA 0.2000 1.3554mA 0.8893mA 1.8202mA 0.3000 1.8790mA 1.2349mA 2.5269mA 0.4000 2.3082mA 1.5195mA 3.1075mA 0.5000 2.6435mA 1.7458mA 3.5540mA 0.6000 2.8738mA 1.9139mA 3.8386mA 0.7000 3.0024mA 2.0222mA 3.9843mA 0.8000 3.0722mA 2.0840mA 4.0627mA 0.9000 3.1166mA 2.1218mA 4.1145mA 1.0000 3.1509mA 2.1499mA 4.1567mA 1.1000 3.1831mA 2.1837mA 4.1952mA 1.2000 3.3805mA 2.3028mA 4.2357mA 1.3000 3.3973mA 2.3153mA 4.4908mA 1.4000 3.4108mA 2.3252mA 4.5075mA 1.5000 3.4215mA 2.3330mA 4.5207mA 1.6000 3.4299mA 2.3390mA 4.5311mA 1.7000 3.4365mA 2.3435mA 4.5392mA 1.8000 3.4413mA 2.3469mA 4.5451mA 1.9000 3.4558mA 2.4172mA 4.5422mA 2.0000 3.4723mA 2.7978mA 4.5590mA 2.1000 3.5631mA 3.8743mA 4.5754mA 2.2000 4.2085mA 5.6944mA 4.6014mA 2.3000 5.8282mA 8.2676mA 4.8910mA 2.4000 8.4137mA 12.8883mA 6.1950mA 2.5000 11.7769mA 38.3456mA 8.7770mA 2.6000 16.6566mA 0.1291A 12.3914mA 2.7000 48.9090mA 0.2661A 16.6983mA 2.8000 0.1604A 0.4222A 24.7422mA 2.9000 0.3111A 0.5874A 92.8945mA 3.0000 0.4756A 0.7575A 0.2333A 3.1000 0.6464A 0.9309A 0.3958A 3.2000 0.8208A 1.1064A 0.5666A 3.3000 0.9975A 1.2835A 0.7414A 3.4000 1.1758A 1.4618A 0.9187A 3.5000 1.3552A 1.6410A 1.0976A 3.6000 1.5354A 1.8209A 1.2776A | [Pullup] | voltage I(typ) I(min) I(max) | -1.8000 0.1400mA 0.1400mA 0.1500mA -1.7000 0.1600mA 0.1600mA 0.1700mA -1.6000 0.1900mA 0.1800mA 0.1900mA -1.5000 0.2250mA 0.2200mA 0.2300mA -1.4000 0.2770mA 0.2630mA 0.2880mA -1.3000 0.3540mA 0.3290mA 0.3710mA -1.2000 0.4800mA 0.4310mA 0.5070mA -1.1000 0.7120mA 0.6070mA 0.7710mA -1.0000 1.2270mA 0.9450mA 1.3960mA -0.9000 2.5829mA 1.6834mA 3.2954mA -0.8000 3.6223mA 2.6192mA 4.5614mA -0.7000 3.4485mA 2.6338mA 4.2455mA -0.6000 3.1033mA 2.3724mA 3.8476mA -0.5000 2.7039mA 2.0544mA 3.3824mA -0.4000 2.2371mA 1.6892mA 2.8241mA -0.3000 1.7007mA 1.2803mA 2.1629mA -0.2000 1.1261mA 0.8427mA 1.4436mA -0.1000 0.5566mA 0.4117mA 0.7202mA 0.0000 21.2100pA -0.5832nA 2.2960pA 0.1000 -0.5359mA -0.3901mA -0.7027mA 0.2000 -1.0231mA -0.7428mA -1.3458mA 0.3000 -1.4619mA -1.0580mA -1.9298mA 0.4000 -1.8527mA -1.3360mA -2.4554mA 0.5000 -2.1957mA -1.5769mA -2.9226mA 0.6000 -2.4911mA -1.7810mA -3.3310mA 0.7000 -2.7386mA -1.9489mA -3.6787mA 0.8000 -2.9381mA -2.0817mA -3.9627mA 0.9000 -3.0914mA -2.1827mA -4.1821mA 1.0000 -3.2055mA -2.2577mA -4.3447mA 1.1000 -3.2910mA -2.3144mA -4.4655mA 1.2000 -3.3573mA -2.3589mA -4.5581mA 1.3000 -3.4109mA -2.3954mA -4.6324mA 1.4000 -3.4560mA -2.4263mA -4.6941mA 1.5000 -3.4948mA -2.4532mA -4.7469mA 1.6000 -3.5291mA -2.4771mA -4.7933mA 1.7000 -3.5600mA -2.4990mA -4.8348mA 1.8000 -3.5882mA -2.5214mA -4.8725mA 1.9000 -3.6142mA -2.5753mA -4.9071mA 2.0000 -3.6398mA -2.8763mA -4.9392mA 2.1000 -3.7005mA -3.8357mA -4.9693mA 2.2000 -4.1340mA -5.5848mA -5.0003mA 2.3000 -5.5940mA -8.0339mA -5.1200mA 2.4000 -8.2201mA -11.1521mA -5.9779mA 2.5000 -11.7287mA -17.2174mA -8.3604mA 2.6000 -15.8625mA -55.4554mA -12.0937mA 2.7000 -24.1226mA -0.1906A -16.6275mA 2.8000 -95.0284mA -0.3946A -21.8149mA 2.9000 -0.2795A -0.6270A -47.2489mA 3.0000 -0.5099A -0.8726A -0.1962A 3.1000 -0.7573A -1.1257A -0.4211A 3.2000 -1.0127A -1.3834A -0.6682A 3.3000 -1.2728A -1.6443A -0.9246A 3.4000 -1.5360A -1.9074A -1.1860A 3.5000 -1.8014A -2.1723A -1.4504A 3.6000 -2.0682A -2.4385A -1.7169A | [GND_clamp] | voltage I(typ) I(min) I(max) | -1.8000 -2.0651A -2.0375A -2.1150A -1.7000 -1.7982A -1.7734A -1.8464A -1.6000 -1.5329A -1.5113A -1.5791A -1.5000 -1.2697A -1.2519A -1.3136A -1.4000 -1.0096A -0.9963A -1.0506A -1.3000 -0.7541A -0.7464A -0.7914A -1.2000 -0.5068A -0.5063A -0.5388A -1.1000 -0.2763A -0.2851A -0.2999A -1.0000 -91.6685mA -0.1083A -0.1008A -0.9000 -20.4744mA -25.0704mA -21.9332mA -0.8000 -12.2007mA -10.7449mA -14.0755mA -0.7000 -8.0919mA -6.9494mA -9.3225mA -0.6000 -4.6057mA -4.2048mA -5.1530mA -0.5000 -1.9957mA -2.1036mA -2.0455mA -0.4000 -0.5432mA -0.7551mA -0.4720mA -0.3000 -0.1102mA -0.1696mA -0.1103mA -0.2000 -48.9810uA -42.7947uA -62.3758uA -0.1000 -23.8512uA -16.6082uA -31.4078uA 0.0000 -2.2387nA -44.4298nA -0.9771nA 0.1000 22.6437uA 14.8425uA 30.3469uA 0.2000 42.8982uA 28.0060uA 57.7964uA 0.3000 60.7755uA 39.4886uA 82.3515uA 0.4000 76.2860uA 49.3000uA 0.1040mA 0.5000 89.4264uA 57.4491uA 0.1227mA 0.6000 0.1002mA 64.0685uA 0.1385mA 0.7000 0.1091mA 69.7489uA 0.1515mA 0.8000 0.1168mA 74.8660uA 0.1623mA 0.9000 0.1228mA 79.3462uA 0.1695mA 1.0000 0.1259mA 81.5132uA 0.1714mA 1.1000 0.1238mA 71.5554uA 0.1686mA 1.2000 -48.2734uA -27.5884uA 0.1583mA 1.3000 -42.8264uA -22.8107uA -70.1492uA 1.4000 -36.2008uA -17.2176uA -62.8418uA 1.5000 -28.5460uA -10.8663uA -54.0516uA 1.6000 -19.9435uA -3.7749uA -43.9714uA 1.7000 -10.4222uA 4.1011uA -32.7480uA 1.8000 1.8114nA 14.8215uA -20.4413uA | [POWER_clamp] | voltage I(typ) I(min) I(max) | -1.8000 1.5323A 1.5491A 1.5450A -1.7000 1.3521A 1.3704A 1.3639A -1.6000 1.1727A 1.1927A 1.1834A -1.5000 0.9945A 1.0164A 1.0040A -1.4000 0.8178A 0.8418A 0.8258A -1.3000 0.6434A 0.6699A 0.6497A -1.2000 0.4726A 0.5019A 0.4766A -1.1000 0.3081A 0.3406A 0.3092A -1.0000 0.1573A 0.1920A 0.1545A -0.9000 45.6313mA 73.0995mA 41.1090mA -0.8000 13.1555mA 17.5218mA 14.6114mA -0.7000 8.2404mA 7.6041mA 9.8179mA -0.6000 4.9126mA 4.4779mA 5.8663mA -0.5000 2.3548mA 2.3165mA 2.7557mA -0.4000 0.7523mA 0.8824mA 0.8233mA -0.3000 0.1135mA 0.1833mA 0.1117mA -0.2000 25.0040uA 28.0920uA 30.5030uA -0.1000 11.1082uA 8.6012uA 14.5486uA 0.0000 1.8114nA 56.2228nA 0.1541nA | [Ramp] | variable typ min max dV/dt_r 0.1061/0.7726n 73.7335m/1.2014n 0.1451/0.5055n dV/dt_f 0.1024/0.4919n 69.7638m/0.7616n 0.1353/0.3474n R_load = 50.0000 | [Rising Waveform] R_fixture = 0.5000k V_fixture = 0.000 V_fixture_min = 0.000 V_fixture_max = 0.000 | time V(typ) V(min) V(max) | 0.000S 0.2264uV 6.1660uV 52.1239nV 81.6327pS 0.2356uV 6.1723uV 68.1925nV 0.1633nS 0.2409uV 6.1693uV 0.4050uV 0.2449nS 0.3811uV 6.1737uV -1.4457uV 0.3265nS 0.6919uV 6.1692uV 72.6202uV 0.4082nS -2.6052uV 6.1745uV -0.1587mV 0.4898nS 52.6015uV 6.0997uV -1.5344mV 0.5714nS 38.2170uV 4.4609uV -4.7046mV 0.6531nS -0.6122mV 0.9418uV -7.7094mV 0.7347nS -1.6879mV 9.1579uV 6.4584mV 0.8163nS -3.8408mV 56.3510uV 51.1710mV 0.8980nS -6.4158mV 89.7821uV 0.1231V 0.9796nS -6.7018mV 16.0007uV 0.2272V 1.0612nS -3.9565mV -0.4047mV 0.3126V 1.1429nS 8.3712mV -1.6538mV 0.4029V 1.2245nS 38.5748mV -2.5778mV 0.5337V 1.3061nS 96.4386mV -4.2892mV 0.6330V 1.3878nS 0.1439V -5.3441mV 0.8810V 1.4694nS 0.1799V -5.3236mV 0.9813V 1.5510nS 0.2473V -5.0368mV 1.1205V 1.6327nS 0.2904V -4.4097mV 1.1907V 1.7143nS 0.3743V -0.4394mV 1.2816V 1.7959nS 0.4557V 8.5692mV 1.3200V 1.8776nS 0.5381V 16.7308mV 1.3584V 1.9592nS 0.6205V 38.0715mV 1.3860V 2.0408nS 0.6763V 52.1707mV 1.4031V 2.1224nS 0.7637V 83.5237mV 1.4201V 2.2041nS 0.8889V 0.1188V 1.4333V 2.2857nS 0.9377V 0.1475V 1.4378V 2.3673nS 0.9864V 0.1761V 1.4423V 2.4490nS 1.0502V 0.1941V 1.4454V 2.5306nS 1.0781V 0.2322V 1.4467V 2.6122nS 1.1061V 0.2703V 1.4480V 2.6939nS 1.1451V 0.2997V 1.4495V 2.7755nS 1.1561V 0.3415V 1.4498V 2.8571nS 1.1672V 0.3833V 1.4501V 2.9388nS 1.1783V 0.4459V 1.4504V 3.0204nS 1.1893V 0.4832V 1.4508V 3.1020nS 1.1985V 0.5204V 1.4510V 3.1837nS 1.2017V 0.5577V 1.4511V 3.2653nS 1.2050V 0.5949V 1.4512V 3.3469nS 1.2082V 0.6188V 1.4514V 3.4286nS 1.2114V 0.6566V 1.4515V 3.5102nS 1.2123V 0.6945V 1.4516V 3.5918nS 1.2131V 0.7324V 1.4517V 3.6735nS 1.2140V 0.7825V 1.4518V 3.7551nS 1.2148V 0.8028V 1.4519V 3.8367nS 1.2155V 0.8231V 1.4520V 3.9184nS 1.2158V 0.8434V 1.4520V 4.0000nS 1.2160V 0.8637V 1.4521V 4.0816nS 1.2163V 0.8813V 1.4522V 4.1633nS 1.2165V 0.8918V 1.4522V 4.2449nS 1.2167V 0.9022V 1.4523V 4.3265nS 1.2168V 0.9127V 1.4524V 4.4082nS 1.2170V 0.9232V 1.4524V 4.4898nS 1.2171V 0.9313V 1.4525V 4.5714nS 1.2172V 0.9354V 1.4525V 4.6531nS 1.2173V 0.9395V 1.4526V 4.7347nS 1.2174V 0.9436V 1.4526V 4.8163nS 1.2174V 0.9477V 1.4527V 4.8980nS 1.2175V 0.9505V 1.4527V 4.9796nS 1.2176V 0.9520V 1.4528V 5.0612nS 1.2176V 0.9536V 1.4528V 5.1429nS 1.2177V 0.9551V 1.4528V 5.2245nS 1.2178V 0.9567V 1.4529V 5.3061nS 1.2178V 0.9576V 1.4529V 5.3878nS 1.2179V 0.9582V 1.4529V 5.4694nS 1.2180V 0.9588V 1.4530V 5.5510nS 1.2180V 0.9594V 1.4530V 5.6327nS 1.2180V 0.9603V 1.4530V 5.7143nS 1.2181V 0.9605V 1.4530V 5.7959nS 1.2181V 0.9608V 1.4531V 5.8776nS 1.2182V 0.9610V 1.4531V 5.9592nS 1.2182V 0.9612V 1.4531V 6.0408nS 1.2182V 0.9615V 1.4531V 6.1224nS 1.2183V 0.9616V 1.4531V 6.2041nS 1.2183V 0.9617V 1.4532V 6.2857nS 1.2184V 0.9618V 1.4532V 6.3673nS 1.2184V 0.9619V 1.4532V 6.4490nS 1.2184V 0.9621V 1.4532V 6.5306nS 1.2184V 0.9621V 1.4532V 6.6122nS 1.2185V 0.9622V 1.4532V 6.6939nS 1.2185V 0.9623V 1.4533V 6.7755nS 1.2185V 0.9624V 1.4533V 6.8571nS 1.2185V 0.9624V 1.4533V 6.9388nS 1.2186V 0.9625V 1.4533V 7.0204nS 1.2186V 0.9625V 1.4533V 7.1020nS 1.2186V 0.9626V 1.4533V 7.1837nS 1.2186V 0.9626V 1.4533V 7.2653nS 1.2186V 0.9627V 1.4533V 7.3469nS 1.2187V 0.9627V 1.4533V 7.4286nS 1.2187V 0.9628V 1.4534V 7.5102nS 1.2187V 0.9628V 1.4534V 7.5918nS 1.2187V 0.9629V 1.4534V 7.6735nS 1.2187V 0.9629V 1.4534V 7.7551nS 1.2188V 0.9629V 1.4534V 7.8367nS 1.2188V 0.9629V 1.4534V 7.9184nS 1.2188V 0.9630V 1.4534V 8.0000nS 1.2188V 0.9630V 1.4534V | [Rising Waveform] R_fixture = 50.0000 V_fixture = 0.000 V_fixture_min = 0.000 V_fixture_max = 0.000 | time V(typ) V(min) V(max) | 0.000S 88.1815nV 1.7818uV 32.1883nV 81.6327pS 90.0526nV 1.7856uV 34.6551nV 0.1633nS 90.8363nV 1.7816uV 0.2894uV 0.2449nS 0.1837uV 1.7844uV -1.1728uV 0.3265nS 0.2555uV 1.7799uV 54.5396uV 0.4082nS -2.8821uV 1.7862uV -0.1606mV 0.4898nS 36.9661uV 1.7329uV -1.0784mV 0.5714nS 7.8647uV 0.6047uV -2.7310mV 0.6531nS -0.5132mV -1.0856uV -2.8716mV 0.7347nS -1.3781mV 6.4038uV 8.0819mV 0.8163nS -2.4176mV 35.2581uV 31.2094mV 0.8980nS -2.1150mV 43.0850uV 55.3842mV 0.9796nS -1.2927mV -23.3545uV 79.6073mV 1.0612nS 0.5453mV -0.2874mV 98.5085mV 1.1429nS 6.8700mV -0.9134mV 0.1220V 1.2245nS 19.9144mV -1.2745mV 0.1451V 1.3061nS 37.7666mV -1.7021mV 0.1663V 1.3878nS 47.6547mV -1.4177mV 0.1892V 1.4694nS 53.2698mV -0.8363mV 0.2065V 1.5510nS 65.1844mV -0.4301mV 0.2198V 1.6327nS 72.5819mV -88.3368uV 0.2322V 1.7143nS 87.2224mV 2.0106mV 0.2359V 1.7959nS 0.1004V 6.0081mV 0.2404V 1.8776nS 0.1137V 9.7247mV 0.2408V 1.9592nS 0.1271V 16.3606mV 0.2412V 2.0408nS 0.1348V 21.8269mV 0.2417V 2.1224nS 0.1458V 27.3619mV 0.2417V 2.2041nS 0.1599V 34.1444mV 0.2417V 2.2857nS 0.1638V 37.6828mV 0.2417V 2.3673nS 0.1677V 41.2212mV 0.2417V 2.4490nS 0.1733V 44.3127mV 0.2417V 2.5306nS 0.1741V 49.3217mV 0.2417V 2.6122nS 0.1749V 54.3307mV 0.2417V 2.6939nS 0.1758V 59.3396mV 0.2417V 2.7755nS 0.1766V 63.7377mV 0.2417V 2.8571nS 0.1766V 69.8142mV 0.2417V 2.9388nS 0.1766V 75.8907mV 0.2418V 3.0204nS 0.1766V 81.9672mV 0.2418V 3.1020nS 0.1767V 85.2228mV 0.2418V 3.1837nS 0.1767V 90.6678mV 0.2418V 3.2653nS 0.1767V 96.1128mV 0.2418V 3.3469nS 0.1767V 0.1016V 0.2418V 3.4286nS 0.1767V 0.1063V 0.2418V 3.5102nS 0.1767V 0.1090V 0.2418V 3.5918nS 0.1767V 0.1116V 0.2418V 3.6735nS 0.1767V 0.1142V 0.2418V 3.7551nS 0.1767V 0.1169V 0.2418V 3.8367nS 0.1767V 0.1189V 0.2418V 3.9184nS 0.1767V 0.1197V 0.2418V 4.0000nS 0.1767V 0.1204V 0.2418V 4.0816nS 0.1767V 0.1212V 0.2418V 4.1633nS 0.1767V 0.1219V 0.2418V 4.2449nS 0.1768V 0.1224V 0.2418V 4.3265nS 0.1768V 0.1225V 0.2418V 4.4082nS 0.1768V 0.1226V 0.2418V 4.4898nS 0.1768V 0.1227V 0.2418V 4.5714nS 0.1768V 0.1228V 0.2418V 4.6531nS 0.1768V 0.1228V 0.2419V 4.7347nS 0.1768V 0.1229V 0.2419V 4.8163nS 0.1768V 0.1229V 0.2419V 4.8980nS 0.1768V 0.1229V 0.2419V 4.9796nS 0.1768V 0.1229V 0.2419V 5.0612nS 0.1768V 0.1229V 0.2419V 5.1429nS 0.1768V 0.1229V 0.2419V 5.2245nS 0.1768V 0.1229V 0.2419V 5.3061nS 0.1768V 0.1229V 0.2419V 5.3878nS 0.1768V 0.1229V 0.2419V 5.4694nS 0.1768V 0.1229V 0.2419V 5.5510nS 0.1768V 0.1229V 0.2419V 5.6327nS 0.1768V 0.1229V 0.2419V 5.7143nS 0.1768V 0.1229V 0.2419V 5.7959nS 0.1768V 0.1229V 0.2419V 5.8776nS 0.1768V 0.1229V 0.2419V 5.9592nS 0.1768V 0.1229V 0.2419V 6.0408nS 0.1768V 0.1229V 0.2419V 6.1224nS 0.1768V 0.1229V 0.2419V 6.2041nS 0.1768V 0.1229V 0.2419V 6.2857nS 0.1768V 0.1229V 0.2419V 6.3673nS 0.1768V 0.1230V 0.2419V 6.4490nS 0.1768V 0.1230V 0.2419V 6.5306nS 0.1768V 0.1230V 0.2419V 6.6122nS 0.1768V 0.1230V 0.2419V 6.6939nS 0.1768V 0.1230V 0.2419V 6.7755nS 0.1768V 0.1230V 0.2419V 6.8571nS 0.1768V 0.1230V 0.2419V 6.9388nS 0.1768V 0.1230V 0.2419V 7.0204nS 0.1768V 0.1230V 0.2419V 7.1020nS 0.1768V 0.1230V 0.2419V 7.1837nS 0.1768V 0.1230V 0.2419V 7.2653nS 0.1768V 0.1230V 0.2419V 7.3469nS 0.1768V 0.1230V 0.2419V 7.4286nS 0.1768V 0.1230V 0.2419V 7.5102nS 0.1768V 0.1230V 0.2419V 7.5918nS 0.1768V 0.1230V 0.2419V 7.6735nS 0.1768V 0.1230V 0.2419V 7.7551nS 0.1768V 0.1230V 0.2419V 7.8367nS 0.1768V 0.1230V 0.2419V 7.9184nS 0.1768V 0.1230V 0.2419V 8.0000nS 0.1768V 0.1230V 0.2419V | [Falling Waveform] R_fixture = 0.5000k V_fixture = 1.8000 V_fixture_min = 1.6500 V_fixture_max = 1.9500 | time V(typ) V(min) V(max) | 0.000S 1.8000V 1.6500V 1.9500V 81.6327pS 1.8000V 1.6500V 1.9500V 0.1633nS 1.8000V 1.6500V 1.9500V 0.2449nS 1.8000V 1.6500V 1.9500V 0.3265nS 1.8000V 1.6500V 1.9500V 0.4082nS 1.8000V 1.6500V 1.9523V 0.4898nS 1.7999V 1.6500V 1.9554V 0.5714nS 1.8005V 1.6500V 1.9585V 0.6531nS 1.8029V 1.6500V 1.9609V 0.7347nS 1.8053V 1.6499V 1.9498V 0.8163nS 1.8071V 1.6499V 1.9247V 0.8980nS 1.8086V 1.6502V 1.8636V 0.9796nS 1.8095V 1.6512V 1.7381V 1.0612nS 1.8040V 1.6525V 1.5298V 1.1429nS 1.7877V 1.6540V 1.4002V 1.2245nS 1.7516V 1.6552V 1.2672V 1.3061nS 1.7062V 1.6560V 1.1134V 1.3878nS 1.6693V 1.6568V 1.0217V 1.4694nS 1.5836V 1.6572V 0.7842V 1.5510nS 1.5189V 1.6572V 0.7036V 1.6327nS 1.4085V 1.6566V 0.6006V 1.7143nS 1.2921V 1.6563V 0.5484V 1.7959nS 1.1938V 1.6499V 0.4796V 1.8776nS 1.0602V 1.6380V 0.4564V 1.9592nS 0.9858V 1.6318V 0.4333V 2.0408nS 0.9114V 1.5969V 0.4176V 2.1224nS 0.8571V 1.5680V 0.4086V 2.2041nS 0.7874V 1.5390V 0.3996V 2.2857nS 0.6856V 1.5185V 0.3949V 2.3673nS 0.6527V 1.4696V 0.3928V 2.4490nS 0.6198V 1.4208V 0.3907V 2.5306nS 0.5869V 1.3915V 0.3895V 2.6122nS 0.5681V 1.3316V 0.3890V 2.6939nS 0.5480V 1.2716V 0.3885V 2.7755nS 0.5279V 1.2043V 0.3879V 2.8571nS 0.5106V 1.1546V 0.3877V 2.9388nS 0.5042V 1.1050V 0.3876V 3.0204nS 0.4977V 1.0554V 0.3875V 3.1020nS 0.4912V 1.0223V 0.3874V 3.1837nS 0.4867V 0.9782V 0.3872V 3.2653nS 0.4847V 0.9340V 0.3871V 3.3469nS 0.4827V 0.8746V 0.3870V 3.4286nS 0.4808V 0.8505V 0.3869V 3.5102nS 0.4797V 0.8263V 0.3868V 3.5918nS 0.4791V 0.8022V 0.3867V 3.6735nS 0.4785V 0.7780V 0.3867V 3.7551nS 0.4779V 0.7602V 0.3866V 3.8367nS 0.4771V 0.7456V 0.3865V 3.9184nS 0.4769V 0.7310V 0.3865V 4.0000nS 0.4768V 0.7164V 0.3864V 4.0816nS 0.4766V 0.7018V 0.3863V 4.1633nS 0.4764V 0.6925V 0.3863V 4.2449nS 0.4762V 0.6857V 0.3862V 4.3265nS 0.4761V 0.6789V 0.3862V 4.4082nS 0.4761V 0.6722V 0.3861V 4.4898nS 0.4760V 0.6654V 0.3861V 4.5714nS 0.4759V 0.6617V 0.3860V 4.6531nS 0.4758V 0.6588V 0.3860V 4.7347nS 0.4757V 0.6559V 0.3859V 4.8163nS 0.4756V 0.6529V 0.3859V 4.8980nS 0.4756V 0.6487V 0.3859V 4.9796nS 0.4755V 0.6477V 0.3858V 5.0612nS 0.4754V 0.6466V 0.3858V 5.1429nS 0.4754V 0.6456V 0.3858V 5.2245nS 0.4753V 0.6445V 0.3857V 5.3061nS 0.4753V 0.6431V 0.3857V 5.3878nS 0.4752V 0.6427V 0.3857V 5.4694nS 0.4752V 0.6422V 0.3856V 5.5510nS 0.4751V 0.6417V 0.3856V 5.6327nS 0.4751V 0.6412V 0.3856V 5.7143nS 0.4750V 0.6407V 0.3856V 5.7959nS 0.4750V 0.6404V 0.3855V 5.8776nS 0.4749V 0.6402V 0.3855V 5.9592nS 0.4749V 0.6398V 0.3855V 6.0408nS 0.4749V 0.6396V 0.3855V 6.1224nS 0.4748V 0.6395V 0.3855V 6.2041nS 0.4748V 0.6393V 0.3855V 6.2857nS 0.4748V 0.6391V 0.3854V 6.3673nS 0.4748V 0.6390V 0.3854V 6.4490nS 0.4747V 0.6389V 0.3854V 6.5306nS 0.4747V 0.6389V 0.3854V 6.6122nS 0.4747V 0.6388V 0.3854V 6.6939nS 0.4746V 0.6387V 0.3854V 6.7755nS 0.4746V 0.6386V 0.3853V 6.8571nS 0.4746V 0.6385V 0.3853V 6.9388nS 0.4746V 0.6384V 0.3853V 7.0204nS 0.4745V 0.6383V 0.3853V 7.1020nS 0.4745V 0.6383V 0.3853V 7.1837nS 0.4745V 0.6382V 0.3853V 7.2653nS 0.4745V 0.6382V 0.3853V 7.3469nS 0.4745V 0.6381V 0.3853V 7.4286nS 0.4745V 0.6381V 0.3853V 7.5102nS 0.4744V 0.6380V 0.3853V 7.5918nS 0.4744V 0.6380V 0.3852V 7.6735nS 0.4744V 0.6379V 0.3852V 7.7551nS 0.4744V 0.6379V 0.3852V 7.8367nS 0.4744V 0.6379V 0.3852V 7.9184nS 0.4744V 0.6378V 0.3852V 8.0000nS 0.4743V 0.6378V 0.3852V | [Falling Waveform] R_fixture = 50.0000 V_fixture = 1.8000 V_fixture_min = 1.6500 V_fixture_max = 1.9500 | time V(typ) V(min) V(max) | 0.000S 1.8000V 1.6500V 1.9500V 81.6327pS 1.8000V 1.6500V 1.9500V 0.1633nS 1.8000V 1.6500V 1.9500V 0.2449nS 1.8000V 1.6500V 1.9500V 0.3265nS 1.8000V 1.6500V 1.9500V 0.4082nS 1.8000V 1.6500V 1.9517V 0.4898nS 1.7999V 1.6500V 1.9530V 0.5714nS 1.8004V 1.6500V 1.9538V 0.6531nS 1.8018V 1.6500V 1.9528V 0.7347nS 1.8024V 1.6500V 1.9435V 0.8163nS 1.8026V 1.6500V 1.9287V 0.8980nS 1.8028V 1.6502V 1.9012V 0.9796nS 1.8020V 1.6508V 1.8591V 1.0612nS 1.7974V 1.6514V 1.8056V 1.1429nS 1.7882V 1.6517V 1.7851V 1.2245nS 1.7723V 1.6518V 1.7635V 1.3061nS 1.7589V 1.6518V 1.7505V 1.3878nS 1.7475V 1.6516V 1.7391V 1.4694nS 1.7269V 1.6513V 1.7345V 1.5510nS 1.7114V 1.6508V 1.7299V 1.6327nS 1.6918V 1.6504V 1.7267V 1.7143nS 1.6714V 1.6501V 1.7259V 1.7959nS 1.6612V 1.6464V 1.7250V 1.8776nS 1.6510V 1.6414V 1.7249V 1.9592nS 1.6458V 1.6378V 1.7248V 2.0408nS 1.6410V 1.6298V 1.7247V 2.1224nS 1.6361V 1.6258V 1.7247V 2.2041nS 1.6337V 1.6165V 1.7246V 2.2857nS 1.6326V 1.6082V 1.7246V 2.3673nS 1.6315V 1.5997V 1.7246V 2.4490nS 1.6304V 1.5911V 1.7246V 2.5306nS 1.6298V 1.5838V 1.7246V 2.6122nS 1.6297V 1.5761V 1.7246V 2.6939nS 1.6296V 1.5685V 1.7246V 2.7755nS 1.6295V 1.5575V 1.7246V 2.8571nS 1.6294V 1.5539V 1.7246V 2.9388nS 1.6294V 1.5503V 1.7246V 3.0204nS 1.6294V 1.5466V 1.7246V 3.1020nS 1.6294V 1.5417V 1.7246V 3.1837nS 1.6293V 1.5405V 1.7245V 3.2653nS 1.6293V 1.5393V 1.7245V 3.3469nS 1.6293V 1.5380V 1.7245V 3.4286nS 1.6293V 1.5368V 1.7245V 3.5102nS 1.6293V 1.5353V 1.7245V 3.5918nS 1.6293V 1.5350V 1.7245V 3.6735nS 1.6293V 1.5348V 1.7245V 3.7551nS 1.6293V 1.5345V 1.7245V 3.8367nS 1.6293V 1.5343V 1.7245V 3.9184nS 1.6293V 1.5340V 1.7245V 4.0000nS 1.6293V 1.5340V 1.7245V 4.0816nS 1.6293V 1.5339V 1.7245V 4.1633nS 1.6293V 1.5339V 1.7245V 4.2449nS 1.6293V 1.5338V 1.7245V 4.3265nS 1.6293V 1.5338V 1.7245V 4.4082nS 1.6293V 1.5338V 1.7245V 4.4898nS 1.6293V 1.5338V 1.7245V 4.5714nS 1.6293V 1.5338V 1.7245V 4.6531nS 1.6293V 1.5337V 1.7245V 4.7347nS 1.6293V 1.5337V 1.7245V 4.8163nS 1.6293V 1.5337V 1.7245V 4.8980nS 1.6293V 1.5337V 1.7245V 4.9796nS 1.6293V 1.5337V 1.7245V 5.0612nS 1.6293V 1.5337V 1.7245V 5.1429nS 1.6293V 1.5337V 1.7245V 5.2245nS 1.6293V 1.5337V 1.7245V 5.3061nS 1.6293V 1.5337V 1.7245V 5.3878nS 1.6293V 1.5337V 1.7245V 5.4694nS 1.6293V 1.5337V 1.7245V 5.5510nS 1.6293V 1.5337V 1.7245V 5.6327nS 1.6293V 1.5337V 1.7245V 5.7143nS 1.6293V 1.5337V 1.7245V 5.7959nS 1.6293V 1.5337V 1.7245V 5.8776nS 1.6293V 1.5337V 1.7245V 5.9592nS 1.6293V 1.5337V 1.7245V 6.0408nS 1.6293V 1.5337V 1.7245V 6.1224nS 1.6293V 1.5337V 1.7245V 6.2041nS 1.6293V 1.5337V 1.7245V 6.2857nS 1.6293V 1.5337V 1.7245V 6.3673nS 1.6293V 1.5337V 1.7245V 6.4490nS 1.6293V 1.5337V 1.7245V 6.5306nS 1.6293V 1.5337V 1.7245V 6.6122nS 1.6293V 1.5337V 1.7245V 6.6939nS 1.6293V 1.5337V 1.7245V 6.7755nS 1.6293V 1.5337V 1.7245V 6.8571nS 1.6293V 1.5337V 1.7245V 6.9388nS 1.6293V 1.5337V 1.7245V 7.0204nS 1.6293V 1.5337V 1.7245V 7.1020nS 1.6293V 1.5337V 1.7245V 7.1837nS 1.6293V 1.5337V 1.7245V 7.2653nS 1.6293V 1.5337V 1.7245V 7.3469nS 1.6293V 1.5337V 1.7245V 7.4286nS 1.6293V 1.5337V 1.7245V 7.5102nS 1.6293V 1.5337V 1.7245V 7.5918nS 1.6293V 1.5337V 1.7245V 7.6735nS 1.6293V 1.5337V 1.7245V 7.7551nS 1.6293V 1.5337V 1.7245V 7.8367nS 1.6293V 1.5337V 1.7245V 7.9184nS 1.6293V 1.5337V 1.7245V 8.0000nS 1.6293V 1.5337V 1.7245V | | End [Model] io_pu0_pk1_ddr0_lo | | End [Component] Skyeplus | [End] - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=_alternative 0054FAC10725726E_= Content-Type: text/html; charset="US-ASCII"
Sujit,
Your 50ohm rising and falling waveforms are not switching sufficiently.  Your driver is too weak, so you may have to boost your minimum load.

- April

- ---------------------------------------------------
April Hachenburg
Core Technology Design Engineer
SMSC - Phoenix


Sujit Kumar-r65837 <sujit@freescale.com>
Sent by: owner-ibis-users@server.eda.org

01/25/2007 06:58 AM

To
ibis-users@server.eda.org
cc
Subject
[IBIS-Users] ibschk- warnings





hi ibis experts
ibschk run on an ibis generates following warnings:

IBISCHK4 V4.0.2

Checking ddr.ibs for IBIS 4.0 Compatibility...

WARNING (line  219) - GND Clamp Typical data is non-monotonic
WARNING (line  219) - GND Clamp Minimum data is non-monotonic
WARNING (line  219) - GND Clamp Maximum data is non-monotonic
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]
     with [R_fixture]=50 Ohms and [V_fixture]=0V
     has TYP column DC endpoints of  0.00V and  0.18v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 0.01V and  0.18V),
     a difference of  4.10% and  3.91%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform]
     with [R_fixture]=500 Ohms and [V_fixture]=1.8V
     has TYP column DC endpoints of  0.47V and  1.80v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 0.50V and  1.80V),
     a difference of  2.18% and  0.00%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]
     with [R_fixture]=500 Ohms and [V_fixture_min]=0V
     has MIN column DC endpoints of  0.00V and  0.96v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 0.02V and  0.96V),
     a difference of  2.14% and  0.59%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]
     with [R_fixture]=50 Ohms and [V_fixture_min]=0V
     has MIN column DC endpoints of  0.00V and  0.12v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 0.01V and  0.13V),
     a difference of  4.58% and  4.47%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform]
     with [R_fixture]=500 Ohms and [V_fixture_min]=1.65V
     has MIN column DC endpoints of  0.64V and  1.65v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 0.67V and  1.65V),
     a difference of  2.83% and  0.00%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]
     with [R_fixture]=50 Ohms and [V_fixture_max]=0V
     has MAX column DC endpoints of  0.00V and  0.24v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 0.01V and  0.25V),
     a difference of  3.89% and  3.60%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform]
     with [R_fixture]=500 Ohms and [V_fixture_max]=1.95V
     has MAX column DC endpoints of  0.39V and  1.95v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 0.42V and  1.95V),
     a difference of  2.06% and  0.01%, respectively.

Errors  : 0
Warnings: 10

File Passed

i have following queries:
>  what could be the possible reason for such warnings ?
>  as  file is passing throgh ibschk, so can i neglect the above warnings ?

pls suggest.
.s2i and ibs file are attached for reference.
--
thanks
sujit kumar




+91-120-4396069
+91-09910168788



- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. [IBIS Ver]      2.1
[File rev]      1.0

[Date]          Jan 16,2007
[Source]        Freescale Semiconductor India Pvt Ltd.
[Notes]         DDR I/O IBIS model for skyeplus
[Disclaimer]    Property of Freescale Incorporated.  Unauthorized
               reproduction and/or distribution is strictly prohibited.
               This product is protected under copyright law.
               Created  2006, (C) Copyright  2006, Freescale Incorporated,
               All Rights Reserved

               UNLESS THERE IS A SIGNED, WRITTEN AGREEMENT TO THE
               CONTRARY, MOTOROLA IS PROVIDING THE IBIS
               MODELS  AND WITHOUT ANY WARRANTY, EXPRESSED OR
               IMPLIED.  Freescale assumes no liability for:
                1) the accuracy of the IBIS models provided to your
                   company;
                2) the proper functioning of these IBIS Models in your
                   design or for any resulting applications; or
                3) infringement of patents, copyrights or intellectual
                   property rights resulting from your use of these IBIS
                   models.
               Freescale provides IBIS Models as a service to our customers.
               You and your company shall not distribute, sell or give
               these models to anyone else without prior written
               permission from Motorola.

               Freescale reserves the right to make changes to our products or
               to discontinue any semiconductor product or service
               without notice, and advises our customers to obtain the
               latest version of relevant information to verify, before
               placing orders, that the information being relied on is
               current.

               Please be aware that your receipt and use of the IBIS
               information provided shall serve as acceptance of these
               terms and conditions.  If you do not accept these terms,
               you should return or destroy the IBIS models and any
               other accompanying information immediately.
[Copyright]     Copyright 2005 Freescale Inc., All Rights Reserved

[Spice type] mica
[Iterate]
|[Cleanup]
|[Summarize] 10

[Temperature Range]        25.0000              0.1050k              -20.0000
[Voltage Range]            1.8000V              1.6500V               1.9500V


| variable           typ                 min                 max
[R_pkg]            2.0000m             1.0000m             4.0000m
[L_pkg]            0.2000nH            0.1000nH            0.4000nH
[C_pkg]            2.0000pF            1.0000pF            4.0000pF

[sim time] 8ns
[tr] 25ps 25ps 25ps
[tf] 25ps 25ps 25ps
[rload] 50
[vil] 0 0 0
[vih] 1.20 1.10 1.30

[Component]      Skyeplus
[Manufacturer]   Freescale Inc.

[Spice file]  ddr.mc

[Pin]
pad pad pad io_pu0_pk1_ddr0_lo
- -> dout enb
dout dout dout dummy
enb enb enb dummy
ovss ovss ovss GND
ovdd ovdd ovdd POWER

[Model]       io_pu0_pk1_ddr0_lo
[Model type]  I/O
[Polarity]    Non-inverting
[Enable]      active-high

[C_comp]         2.0200pF            1.9900pF            2.0300pF

[Vinl]                      0.54
[Vinh]                      1.26
[Vmeas]                     0.9
[Cref]                      50p
[Rref]                      500
[Vref]           0
[Model file]     typ.mod wcs.mod bcs.mod

[Rising waveform]  500 0 0 0 NA NA NA NA NA
[Falling waveform] 500 1.8 1.65 1.95 NA NA NA NA NA
[Rising waveform]  50 0 0 0 NA NA NA NA NA
[Falling waveform] 50 1.8 1.65 1.95 NA NA NA NA NA

[Model]    dummy
[nomodel]
|************************************************************************
| IBIS file ddr.ibs created by s2ibis2 version 2_6-Beta
| North Carolina State University Electronics Research Laboratory  1995
|************************************************************************
|
[IBIS ver]       4.0
[File name]      ddr.ibs
[File Rev]       1.0
[Date]           Jan 16,2007
[Source]         Freescale Semiconductor India Pvt Ltd.
[Notes]          DDR I/O IBIS model for skyeplus
[Disclaimer]     Property of Freescale Incorporated. Unauthorized reproduction
                and/or distribution is strictly prohibited. This product is
                protected under copyright law. Created 2006, (C) Copyright
                2006, Freescale Incorporated, All Rights Reserved UNLESS THERE
                IS A SIGNED, WRITTEN AGREEMENT TO THE CONTRARY, MOTOROLA IS
                PROVIDING THE IBIS MODELS AND WITHOUT ANY WARRANTY, EXPRESSED
                OR IMPLIED. Freescale assumes no liability for: 1) the
                accuracy of the IBIS models provided to your company; 2) the
                proper functioning of these IBIS Models in your design or for
                any resulting applications; or 3) infringement of patents,
                copyrights or intellectual property rights resulting from your
                use of these IBIS models. Freescale provides IBIS Models as a
                service to our customers. You and your company shall not
                distribute, sell or give these models to anyone else without
                prior written permission from Motorola. Freescale reserves the
                right to make changes to our products or to discontinue any
                semiconductor product or service without notice, and ad ...
[Copyright]      Copyright 2005 Freescale Inc., All Rights Reserved
|
|************************************************************************
|                          Component Skyeplus
|************************************************************************
|
[Component]      Skyeplus
[Manufacturer]   Freescale Inc.
[Package]
| variable       typ                 min                 max
R_pkg            2.0000m             1.0000m             4.0000m
L_pkg            0.2000nH            0.1000nH            0.4000nH
C_pkg            2.0000pF            1.0000pF            4.0000pF
|
[Pin]  signal_name          model_name           R_pin     L_pin     C_pin
pad    pad                  io_pu0_pk1_ddr0_lo
| dout dout                 dummy
| enb  enb                  dummy
ovss   ovss                 GND
ovdd   ovdd                 POWER
|
|************************************************************************
|                        Model io_pu0_pk1_ddr0_lo
|************************************************************************
|
[Model]          io_pu0_pk1_ddr0_lo
Model_type       I/O
Polarity         Non-Inverting
Enable           Active-High
Vinl =   0.5400V
Vinh =   1.2600V
Vmeas =   0.9000V
Cref =  50.0000pF
Rref =   0.5000k
Vref =  0.000V
C_comp           2.0200pF            1.9900pF            2.0300pF
|
|
[Temperature Range]       25.0000             0.1050k             -20.0000
[Voltage Range]           1.8000V             1.6500V             1.9500V
[Pulldown]
| voltage     I(typ)              I(min)              I(max)
|
 -1.8000       -0.1770mA           -0.1800mA           -0.1730mA
 -1.7000       -0.2030mA           -0.2050mA           -0.1980mA
 -1.6000       -0.2370mA           -0.2390mA           -0.2320mA
 -1.5000       -0.2850mA           -0.2840mA           -0.2780mA
 -1.4000       -0.3560mA           -0.3531mA           -0.3480mA
 -1.3000       -0.4732mA           -0.4623mA           -0.4614mA
 -1.2000       -0.6924mA           -0.6571mA           -0.6772mA
 -1.1000       -1.1961mA           -1.0615mA           -1.1894mA
 -1.0000       -2.6045mA           -1.9870mA           -2.8057mA
 -0.9000       -4.3820mA           -3.1578mA           -5.2707mA
 -0.8000       -4.4402mA           -3.2792mA           -5.3849mA
 -0.7000       -4.2065mA           -3.0582mA           -5.1801mA
 -0.6000       -3.8765mA           -2.7704mA           -4.8409mA
 -0.5000       -3.4461mA           -2.4264mA           -4.3563mA
 -0.4000       -2.8975mA           -2.0189mA           -3.6962mA
 -0.3000       -2.2377mA           -1.5471mA           -2.8776mA
 -0.2000       -1.5199mA           -1.0359mA           -1.9777mA
 -0.1000       -0.7738mA           -0.5170mA           -1.0210mA
  0.0000       78.9700pA           64.0400pA            0.6308nA
  0.1000        0.7317mA            0.4791mA            0.9815mA
  0.2000        1.3554mA            0.8893mA            1.8202mA
  0.3000        1.8790mA            1.2349mA            2.5269mA
  0.4000        2.3082mA            1.5195mA            3.1075mA
  0.5000        2.6435mA            1.7458mA            3.5540mA
  0.6000        2.8738mA            1.9139mA            3.8386mA
  0.7000        3.0024mA            2.0222mA            3.9843mA
  0.8000        3.0722mA            2.0840mA            4.0627mA
  0.9000        3.1166mA            2.1218mA            4.1145mA
  1.0000        3.1509mA            2.1499mA            4.1567mA
  1.1000        3.1831mA            2.1837mA            4.1952mA
  1.2000        3.3805mA            2.3028mA            4.2357mA
  1.3000        3.3973mA            2.3153mA            4.4908mA
  1.4000        3.4108mA            2.3252mA            4.5075mA
  1.5000        3.4215mA            2.3330mA            4.5207mA
  1.6000        3.4299mA            2.3390mA            4.5311mA
  1.7000        3.4365mA            2.3435mA            4.5392mA
  1.8000        3.4413mA            2.3469mA            4.5451mA
  1.9000        3.4558mA            2.4172mA            4.5422mA
  2.0000        3.4723mA            2.7978mA            4.5590mA
  2.1000        3.5631mA            3.8743mA            4.5754mA
  2.2000        4.2085mA            5.6944mA            4.6014mA
  2.3000        5.8282mA            8.2676mA            4.8910mA
  2.4000        8.4137mA           12.8883mA            6.1950mA
  2.5000       11.7769mA           38.3456mA            8.7770mA
  2.6000       16.6566mA            0.1291A            12.3914mA
  2.7000       48.9090mA            0.2661A            16.6983mA
  2.8000        0.1604A             0.4222A            24.7422mA
  2.9000        0.3111A             0.5874A            92.8945mA
  3.0000        0.4756A             0.7575A             0.2333A
  3.1000        0.6464A             0.9309A             0.3958A
  3.2000        0.8208A             1.1064A             0.5666A
  3.3000        0.9975A             1.2835A             0.7414A
  3.4000        1.1758A             1.4618A             0.9187A
  3.5000        1.3552A             1.6410A             1.0976A
  3.6000        1.5354A             1.8209A             1.2776A
|
[Pullup]
| voltage     I(typ)              I(min)              I(max)
|
 -1.8000        0.1400mA            0.1400mA            0.1500mA
 -1.7000        0.1600mA            0.1600mA            0.1700mA
 -1.6000        0.1900mA            0.1800mA            0.1900mA
 -1.5000        0.2250mA            0.2200mA            0.2300mA
 -1.4000        0.2770mA            0.2630mA            0.2880mA
 -1.3000        0.3540mA            0.3290mA            0.3710mA
 -1.2000        0.4800mA            0.4310mA            0.5070mA
 -1.1000        0.7120mA            0.6070mA            0.7710mA
 -1.0000        1.2270mA            0.9450mA            1.3960mA
 -0.9000        2.5829mA            1.6834mA            3.2954mA
 -0.8000        3.6223mA            2.6192mA            4.5614mA
 -0.7000        3.4485mA            2.6338mA            4.2455mA
 -0.6000        3.1033mA            2.3724mA            3.8476mA
 -0.5000        2.7039mA            2.0544mA            3.3824mA
 -0.4000        2.2371mA            1.6892mA            2.8241mA
 -0.3000        1.7007mA            1.2803mA            2.1629mA
 -0.2000        1.1261mA            0.8427mA            1.4436mA
 -0.1000        0.5566mA            0.4117mA            0.7202mA
  0.0000       21.2100pA           -0.5832nA            2.2960pA
  0.1000       -0.5359mA           -0.3901mA           -0.7027mA
  0.2000       -1.0231mA           -0.7428mA           -1.3458mA
  0.3000       -1.4619mA           -1.0580mA           -1.9298mA
  0.4000       -1.8527mA           -1.3360mA           -2.4554mA
  0.5000       -2.1957mA           -1.5769mA           -2.9226mA
  0.6000       -2.4911mA           -1.7810mA           -3.3310mA
  0.7000       -2.7386mA           -1.9489mA           -3.6787mA
  0.8000       -2.9381mA           -2.0817mA           -3.9627mA
  0.9000       -3.0914mA           -2.1827mA           -4.1821mA
  1.0000       -3.2055mA           -2.2577mA           -4.3447mA
  1.1000       -3.2910mA           -2.3144mA           -4.4655mA
  1.2000       -3.3573mA           -2.3589mA           -4.5581mA
  1.3000       -3.4109mA           -2.3954mA           -4.6324mA
  1.4000       -3.4560mA           -2.4263mA           -4.6941mA
  1.5000       -3.4948mA           -2.4532mA           -4.7469mA
  1.6000       -3.5291mA           -2.4771mA           -4.7933mA
  1.7000       -3.5600mA           -2.4990mA           -4.8348mA
  1.8000       -3.5882mA           -2.5214mA           -4.8725mA
  1.9000       -3.6142mA           -2.5753mA           -4.9071mA
  2.0000       -3.6398mA           -2.8763mA           -4.9392mA
  2.1000       -3.7005mA           -3.8357mA           -4.9693mA
  2.2000       -4.1340mA           -5.5848mA           -5.0003mA
  2.3000       -5.5940mA           -8.0339mA           -5.1200mA
  2.4000       -8.2201mA          -11.1521mA           -5.9779mA
  2.5000      -11.7287mA          -17.2174mA           -8.3604mA
  2.6000      -15.8625mA          -55.4554mA          -12.0937mA
  2.7000      -24.1226mA           -0.1906A           -16.6275mA
  2.8000      -95.0284mA           -0.3946A           -21.8149mA
  2.9000       -0.2795A            -0.6270A           -47.2489mA
  3.0000       -0.5099A            -0.8726A            -0.1962A
  3.1000       -0.7573A            -1.1257A            -0.4211A
  3.2000       -1.0127A            -1.3834A            -0.6682A
  3.3000       -1.2728A            -1.6443A            -0.9246A
  3.4000       -1.5360A            -1.9074A            -1.1860A
  3.5000       -1.8014A            -2.1723A            -1.4504A
  3.6000       -2.0682A            -2.4385A            -1.7169A
|
[GND_clamp]
| voltage     I(typ)              I(min)              I(max)
|
 -1.8000       -2.0651A            -2.0375A            -2.1150A
 -1.7000       -1.7982A            -1.7734A            -1.8464A
 -1.6000       -1.5329A            -1.5113A            -1.5791A
 -1.5000       -1.2697A            -1.2519A            -1.3136A
 -1.4000       -1.0096A            -0.9963A            -1.0506A
 -1.3000       -0.7541A            -0.7464A            -0.7914A
 -1.2000       -0.5068A            -0.5063A            -0.5388A
 -1.1000       -0.2763A            -0.2851A            -0.2999A
 -1.0000      -91.6685mA           -0.1083A            -0.1008A
 -0.9000      -20.4744mA          -25.0704mA          -21.9332mA
 -0.8000      -12.2007mA          -10.7449mA          -14.0755mA
 -0.7000       -8.0919mA           -6.9494mA           -9.3225mA
 -0.6000       -4.6057mA           -4.2048mA           -5.1530mA
 -0.5000       -1.9957mA           -2.1036mA           -2.0455mA
 -0.4000       -0.5432mA           -0.7551mA           -0.4720mA
 -0.3000       -0.1102mA           -0.1696mA           -0.1103mA
 -0.2000      -48.9810uA          -42.7947uA          -62.3758uA
 -0.1000      -23.8512uA          -16.6082uA          -31.4078uA
  0.0000       -2.2387nA          -44.4298nA           -0.9771nA
  0.1000       22.6437uA           14.8425uA           30.3469uA
  0.2000       42.8982uA           28.0060uA           57.7964uA
  0.3000       60.7755uA           39.4886uA           82.3515uA
  0.4000       76.2860uA           49.3000uA            0.1040mA
  0.5000       89.4264uA           57.4491uA            0.1227mA
  0.6000        0.1002mA           64.0685uA            0.1385mA
  0.7000        0.1091mA           69.7489uA            0.1515mA
  0.8000        0.1168mA           74.8660uA            0.1623mA
  0.9000        0.1228mA           79.3462uA            0.1695mA
  1.0000        0.1259mA           81.5132uA            0.1714mA
  1.1000        0.1238mA           71.5554uA            0.1686mA
  1.2000      -48.2734uA          -27.5884uA            0.1583mA
  1.3000      -42.8264uA          -22.8107uA          -70.1492uA
  1.4000      -36.2008uA          -17.2176uA          -62.8418uA
  1.5000      -28.5460uA          -10.8663uA          -54.0516uA
  1.6000      -19.9435uA           -3.7749uA          -43.9714uA
  1.7000      -10.4222uA            4.1011uA          -32.7480uA
  1.8000        1.8114nA           14.8215uA          -20.4413uA
|
[POWER_clamp]
| voltage     I(typ)              I(min)              I(max)
|
 -1.8000        1.5323A             1.5491A             1.5450A
 -1.7000        1.3521A             1.3704A             1.3639A
 -1.6000        1.1727A             1.1927A             1.1834A
 -1.5000        0.9945A             1.0164A             1.0040A
 -1.4000        0.8178A             0.8418A             0.8258A
 -1.3000        0.6434A             0.6699A             0.6497A
 -1.2000        0.4726A             0.5019A             0.4766A
 -1.1000        0.3081A             0.3406A             0.3092A
 -1.0000        0.1573A             0.1920A             0.1545A
 -0.9000       45.6313mA           73.0995mA           41.1090mA
 -0.8000       13.1555mA           17.5218mA           14.6114mA
 -0.7000        8.2404mA            7.6041mA            9.8179mA
 -0.6000        4.9126mA            4.4779mA            5.8663mA
 -0.5000        2.3548mA            2.3165mA            2.7557mA
 -0.4000        0.7523mA            0.8824mA            0.8233mA
 -0.3000        0.1135mA            0.1833mA            0.1117mA
 -0.2000       25.0040uA           28.0920uA           30.5030uA
 -0.1000       11.1082uA            8.6012uA           14.5486uA
  0.0000        1.8114nA           56.2228nA            0.1541nA
|
[Ramp]
| variable       typ                 min                 max
dV/dt_r          0.1061/0.7726n      73.7335m/1.2014n    0.1451/0.5055n
dV/dt_f          0.1024/0.4919n      69.7638m/0.7616n    0.1353/0.3474n
R_load = 50.0000
|
[Rising Waveform]
R_fixture = 0.5000k
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
| time           V(typ)              V(min)              V(max)
|
 0.000S          0.2264uV            6.1660uV           52.1239nV
 81.6327pS       0.2356uV            6.1723uV           68.1925nV
  0.1633nS       0.2409uV            6.1693uV            0.4050uV
  0.2449nS       0.3811uV            6.1737uV           -1.4457uV
  0.3265nS       0.6919uV            6.1692uV           72.6202uV
  0.4082nS      -2.6052uV            6.1745uV           -0.1587mV
  0.4898nS      52.6015uV            6.0997uV           -1.5344mV
  0.5714nS      38.2170uV            4.4609uV           -4.7046mV
  0.6531nS      -0.6122mV            0.9418uV           -7.7094mV
  0.7347nS      -1.6879mV            9.1579uV            6.4584mV
  0.8163nS      -3.8408mV           56.3510uV           51.1710mV
  0.8980nS      -6.4158mV           89.7821uV            0.1231V
  0.9796nS      -6.7018mV           16.0007uV            0.2272V
  1.0612nS      -3.9565mV           -0.4047mV            0.3126V
  1.1429nS       8.3712mV           -1.6538mV            0.4029V
  1.2245nS      38.5748mV           -2.5778mV            0.5337V
  1.3061nS      96.4386mV           -4.2892mV            0.6330V
  1.3878nS       0.1439V            -5.3441mV            0.8810V
  1.4694nS       0.1799V            -5.3236mV            0.9813V
  1.5510nS       0.2473V            -5.0368mV            1.1205V
  1.6327nS       0.2904V            -4.4097mV            1.1907V
  1.7143nS       0.3743V            -0.4394mV            1.2816V
  1.7959nS       0.4557V             8.5692mV            1.3200V
  1.8776nS       0.5381V            16.7308mV            1.3584V
  1.9592nS       0.6205V            38.0715mV            1.3860V
  2.0408nS       0.6763V            52.1707mV            1.4031V
  2.1224nS       0.7637V            83.5237mV            1.4201V
  2.2041nS       0.8889V             0.1188V             1.4333V
  2.2857nS       0.9377V             0.1475V             1.4378V
  2.3673nS       0.9864V             0.1761V             1.4423V
  2.4490nS       1.0502V             0.1941V             1.4454V
  2.5306nS       1.0781V             0.2322V             1.4467V
  2.6122nS       1.1061V             0.2703V             1.4480V
  2.6939nS       1.1451V             0.2997V             1.4495V
  2.7755nS       1.1561V             0.3415V             1.4498V
  2.8571nS       1.1672V             0.3833V             1.4501V
  2.9388nS       1.1783V             0.4459V             1.4504V
  3.0204nS       1.1893V             0.4832V             1.4508V
  3.1020nS       1.1985V             0.5204V             1.4510V
  3.1837nS       1.2017V             0.5577V             1.4511V
  3.2653nS       1.2050V             0.5949V             1.4512V
  3.3469nS       1.2082V             0.6188V             1.4514V
  3.4286nS       1.2114V             0.6566V             1.4515V
  3.5102nS       1.2123V             0.6945V             1.4516V
  3.5918nS       1.2131V             0.7324V             1.4517V
  3.6735nS       1.2140V             0.7825V             1.4518V
  3.7551nS       1.2148V             0.8028V             1.4519V
  3.8367nS       1.2155V             0.8231V             1.4520V
  3.9184nS       1.2158V             0.8434V             1.4520V
  4.0000nS       1.2160V             0.8637V             1.4521V
  4.0816nS       1.2163V             0.8813V             1.4522V
  4.1633nS       1.2165V             0.8918V             1.4522V
  4.2449nS       1.2167V             0.9022V             1.4523V
  4.3265nS       1.2168V             0.9127V             1.4524V
  4.4082nS       1.2170V             0.9232V             1.4524V
  4.4898nS       1.2171V             0.9313V             1.4525V
  4.5714nS       1.2172V             0.9354V             1.4525V
  4.6531nS       1.2173V             0.9395V             1.4526V
  4.7347nS       1.2174V             0.9436V             1.4526V
  4.8163nS       1.2174V             0.9477V             1.4527V
  4.8980nS       1.2175V             0.9505V             1.4527V
  4.9796nS       1.2176V             0.9520V             1.4528V
  5.0612nS       1.2176V             0.9536V             1.4528V
  5.1429nS       1.2177V             0.9551V             1.4528V
  5.2245nS       1.2178V             0.9567V             1.4529V
  5.3061nS       1.2178V             0.9576V             1.4529V
  5.3878nS       1.2179V             0.9582V             1.4529V
  5.4694nS       1.2180V             0.9588V             1.4530V
  5.5510nS       1.2180V             0.9594V             1.4530V
  5.6327nS       1.2180V             0.9603V             1.4530V
  5.7143nS       1.2181V             0.9605V             1.4530V
  5.7959nS       1.2181V             0.9608V             1.4531V
  5.8776nS       1.2182V             0.9610V             1.4531V
  5.9592nS       1.2182V             0.9612V             1.4531V
  6.0408nS       1.2182V             0.9615V             1.4531V
  6.1224nS       1.2183V             0.9616V             1.4531V
  6.2041nS       1.2183V             0.9617V             1.4532V
  6.2857nS       1.2184V             0.9618V             1.4532V
  6.3673nS       1.2184V             0.9619V             1.4532V
  6.4490nS       1.2184V             0.9621V             1.4532V
  6.5306nS       1.2184V             0.9621V             1.4532V
  6.6122nS       1.2185V             0.9622V             1.4532V
  6.6939nS       1.2185V             0.9623V             1.4533V
  6.7755nS       1.2185V             0.9624V             1.4533V
  6.8571nS       1.2185V             0.9624V             1.4533V
  6.9388nS       1.2186V             0.9625V             1.4533V
  7.0204nS       1.2186V             0.9625V             1.4533V
  7.1020nS       1.2186V             0.9626V             1.4533V
  7.1837nS       1.2186V             0.9626V             1.4533V
  7.2653nS       1.2186V             0.9627V             1.4533V
  7.3469nS       1.2187V             0.9627V             1.4533V
  7.4286nS       1.2187V             0.9628V             1.4534V
  7.5102nS       1.2187V             0.9628V             1.4534V
  7.5918nS       1.2187V             0.9629V             1.4534V
  7.6735nS       1.2187V             0.9629V             1.4534V
  7.7551nS       1.2188V             0.9629V             1.4534V
  7.8367nS       1.2188V             0.9629V             1.4534V
  7.9184nS       1.2188V             0.9630V             1.4534V
  8.0000nS       1.2188V             0.9630V             1.4534V
|
[Rising Waveform]
R_fixture = 50.0000
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
| time           V(typ)              V(min)              V(max)
|
 0.000S         88.1815nV            1.7818uV           32.1883nV
 81.6327pS      90.0526nV            1.7856uV           34.6551nV
  0.1633nS      90.8363nV            1.7816uV            0.2894uV
  0.2449nS       0.1837uV            1.7844uV           -1.1728uV
  0.3265nS       0.2555uV            1.7799uV           54.5396uV
  0.4082nS      -2.8821uV            1.7862uV           -0.1606mV
  0.4898nS      36.9661uV            1.7329uV           -1.0784mV
  0.5714nS       7.8647uV            0.6047uV           -2.7310mV
  0.6531nS      -0.5132mV           -1.0856uV           -2.8716mV
  0.7347nS      -1.3781mV            6.4038uV            8.0819mV
  0.8163nS      -2.4176mV           35.2581uV           31.2094mV
  0.8980nS      -2.1150mV           43.0850uV           55.3842mV
  0.9796nS      -1.2927mV          -23.3545uV           79.6073mV
  1.0612nS       0.5453mV           -0.2874mV           98.5085mV
  1.1429nS       6.8700mV           -0.9134mV            0.1220V
  1.2245nS      19.9144mV           -1.2745mV            0.1451V
  1.3061nS      37.7666mV           -1.7021mV            0.1663V
  1.3878nS      47.6547mV           -1.4177mV            0.1892V
  1.4694nS      53.2698mV           -0.8363mV            0.2065V
  1.5510nS      65.1844mV           -0.4301mV            0.2198V
  1.6327nS      72.5819mV          -88.3368uV            0.2322V
  1.7143nS      87.2224mV            2.0106mV            0.2359V
  1.7959nS       0.1004V             6.0081mV            0.2404V
  1.8776nS       0.1137V             9.7247mV            0.2408V
  1.9592nS       0.1271V            16.3606mV            0.2412V
  2.0408nS       0.1348V            21.8269mV            0.2417V
  2.1224nS       0.1458V            27.3619mV            0.2417V
  2.2041nS       0.1599V            34.1444mV            0.2417V
  2.2857nS       0.1638V            37.6828mV            0.2417V
  2.3673nS       0.1677V            41.2212mV            0.2417V
  2.4490nS       0.1733V            44.3127mV            0.2417V
  2.5306nS       0.1741V            49.3217mV            0.2417V
  2.6122nS       0.1749V            54.3307mV            0.2417V
  2.6939nS       0.1758V            59.3396mV            0.2417V
  2.7755nS       0.1766V            63.7377mV            0.2417V
  2.8571nS       0.1766V            69.8142mV            0.2417V
  2.9388nS       0.1766V            75.8907mV            0.2418V
  3.0204nS       0.1766V            81.9672mV            0.2418V
  3.1020nS       0.1767V            85.2228mV            0.2418V
  3.1837nS       0.1767V            90.6678mV            0.2418V
  3.2653nS       0.1767V            96.1128mV            0.2418V
  3.3469nS       0.1767V             0.1016V             0.2418V
  3.4286nS       0.1767V             0.1063V             0.2418V
  3.5102nS       0.1767V             0.1090V             0.2418V
  3.5918nS       0.1767V             0.1116V             0.2418V
  3.6735nS       0.1767V             0.1142V             0.2418V
  3.7551nS       0.1767V             0.1169V             0.2418V
  3.8367nS       0.1767V             0.1189V             0.2418V
  3.9184nS       0.1767V             0.1197V             0.2418V
  4.0000nS       0.1767V             0.1204V             0.2418V
  4.0816nS       0.1767V             0.1212V             0.2418V
  4.1633nS       0.1767V             0.1219V             0.2418V
  4.2449nS       0.1768V             0.1224V             0.2418V
  4.3265nS       0.1768V             0.1225V             0.2418V
  4.4082nS       0.1768V             0.1226V             0.2418V
  4.4898nS       0.1768V             0.1227V             0.2418V
  4.5714nS       0.1768V             0.1228V             0.2418V
  4.6531nS       0.1768V             0.1228V             0.2419V
  4.7347nS       0.1768V             0.1229V             0.2419V
  4.8163nS       0.1768V             0.1229V             0.2419V
  4.8980nS       0.1768V             0.1229V             0.2419V
  4.9796nS       0.1768V             0.1229V             0.2419V
  5.0612nS       0.1768V             0.1229V             0.2419V
  5.1429nS       0.1768V             0.1229V             0.2419V
  5.2245nS       0.1768V             0.1229V             0.2419V
  5.3061nS       0.1768V             0.1229V             0.2419V
  5.3878nS       0.1768V             0.1229V             0.2419V
  5.4694nS       0.1768V             0.1229V             0.2419V
  5.5510nS       0.1768V             0.1229V             0.2419V
  5.6327nS       0.1768V             0.1229V             0.2419V
  5.7143nS       0.1768V             0.1229V             0.2419V
  5.7959nS       0.1768V             0.1229V             0.2419V
  5.8776nS       0.1768V             0.1229V             0.2419V
  5.9592nS       0.1768V             0.1229V             0.2419V
  6.0408nS       0.1768V             0.1229V             0.2419V
  6.1224nS       0.1768V             0.1229V             0.2419V
  6.2041nS       0.1768V             0.1229V             0.2419V
  6.2857nS       0.1768V             0.1229V             0.2419V
  6.3673nS       0.1768V             0.1230V             0.2419V
  6.4490nS       0.1768V             0.1230V             0.2419V
  6.5306nS       0.1768V             0.1230V             0.2419V
  6.6122nS       0.1768V             0.1230V             0.2419V
  6.6939nS       0.1768V             0.1230V             0.2419V
  6.7755nS       0.1768V             0.1230V             0.2419V
  6.8571nS       0.1768V             0.1230V             0.2419V
  6.9388nS       0.1768V             0.1230V             0.2419V
  7.0204nS       0.1768V             0.1230V             0.2419V
  7.1020nS       0.1768V             0.1230V             0.2419V
  7.1837nS       0.1768V             0.1230V             0.2419V
  7.2653nS       0.1768V             0.1230V             0.2419V
  7.3469nS       0.1768V             0.1230V             0.2419V
  7.4286nS       0.1768V             0.1230V             0.2419V
  7.5102nS       0.1768V             0.1230V             0.2419V
  7.5918nS       0.1768V             0.1230V             0.2419V
  7.6735nS       0.1768V             0.1230V             0.2419V
  7.7551nS       0.1768V             0.1230V             0.2419V
  7.8367nS       0.1768V             0.1230V             0.2419V
  7.9184nS       0.1768V             0.1230V             0.2419V
  8.0000nS       0.1768V             0.1230V             0.2419V
|
[Falling Waveform]
R_fixture = 0.5000k
V_fixture = 1.8000
V_fixture_min = 1.6500
V_fixture_max = 1.9500
| time           V(typ)              V(min)              V(max)
|
 0.000S          1.8000V             1.6500V             1.9500V
 81.6327pS       1.8000V             1.6500V             1.9500V
  0.1633nS       1.8000V             1.6500V             1.9500V
  0.2449nS       1.8000V             1.6500V             1.9500V
  0.3265nS       1.8000V             1.6500V             1.9500V
  0.4082nS       1.8000V             1.6500V             1.9523V
  0.4898nS       1.7999V             1.6500V             1.9554V
  0.5714nS       1.8005V             1.6500V             1.9585V
  0.6531nS       1.8029V             1.6500V             1.9609V
  0.7347nS       1.8053V             1.6499V             1.9498V
  0.8163nS       1.8071V             1.6499V             1.9247V
  0.8980nS       1.8086V             1.6502V             1.8636V
  0.9796nS       1.8095V             1.6512V             1.7381V
  1.0612nS       1.8040V             1.6525V             1.5298V
  1.1429nS       1.7877V             1.6540V             1.4002V
  1.2245nS       1.7516V             1.6552V             1.2672V
  1.3061nS       1.7062V             1.6560V             1.1134V
  1.3878nS       1.6693V             1.6568V             1.0217V
  1.4694nS       1.5836V             1.6572V             0.7842V
  1.5510nS       1.5189V             1.6572V             0.7036V
  1.6327nS       1.4085V             1.6566V             0.6006V
  1.7143nS       1.2921V             1.6563V             0.5484V
  1.7959nS       1.1938V             1.6499V             0.4796V
  1.8776nS       1.0602V             1.6380V             0.4564V
  1.9592nS       0.9858V             1.6318V             0.4333V
  2.0408nS       0.9114V             1.5969V             0.4176V
  2.1224nS       0.8571V             1.5680V             0.4086V
  2.2041nS       0.7874V             1.5390V             0.3996V
  2.2857nS       0.6856V             1.5185V             0.3949V
  2.3673nS       0.6527V             1.4696V             0.3928V
  2.4490nS       0.6198V             1.4208V             0.3907V
  2.5306nS       0.5869V             1.3915V             0.3895V
  2.6122nS       0.5681V             1.3316V             0.3890V
  2.6939nS       0.5480V             1.2716V             0.3885V
  2.7755nS       0.5279V             1.2043V             0.3879V
  2.8571nS       0.5106V             1.1546V             0.3877V
  2.9388nS       0.5042V             1.1050V             0.3876V
  3.0204nS       0.4977V             1.0554V             0.3875V
  3.1020nS       0.4912V             1.0223V             0.3874V
  3.1837nS       0.4867V             0.9782V             0.3872V
  3.2653nS       0.4847V             0.9340V             0.3871V
  3.3469nS       0.4827V             0.8746V             0.3870V
  3.4286nS       0.4808V             0.8505V             0.3869V
  3.5102nS       0.4797V             0.8263V             0.3868V
  3.5918nS       0.4791V             0.8022V             0.3867V
  3.6735nS       0.4785V             0.7780V             0.3867V
  3.7551nS       0.4779V             0.7602V             0.3866V
  3.8367nS       0.4771V             0.7456V             0.3865V
  3.9184nS       0.4769V             0.7310V             0.3865V
  4.0000nS       0.4768V             0.7164V             0.3864V
  4.0816nS       0.4766V             0.7018V             0.3863V
  4.1633nS       0.4764V             0.6925V             0.3863V
  4.2449nS       0.4762V             0.6857V             0.3862V
  4.3265nS       0.4761V             0.6789V             0.3862V
  4.4082nS       0.4761V             0.6722V             0.3861V
  4.4898nS       0.4760V             0.6654V             0.3861V
  4.5714nS       0.4759V             0.6617V             0.3860V
  4.6531nS       0.4758V             0.6588V             0.3860V
  4.7347nS       0.4757V             0.6559V             0.3859V
  4.8163nS       0.4756V             0.6529V             0.3859V
  4.8980nS       0.4756V             0.6487V             0.3859V
  4.9796nS       0.4755V             0.6477V             0.3858V
  5.0612nS       0.4754V             0.6466V             0.3858V
  5.1429nS       0.4754V             0.6456V             0.3858V
  5.2245nS       0.4753V             0.6445V             0.3857V
  5.3061nS       0.4753V             0.6431V             0.3857V
  5.3878nS       0.4752V             0.6427V             0.3857V
  5.4694nS       0.4752V             0.6422V             0.3856V
  5.5510nS       0.4751V             0.6417V             0.3856V
  5.6327nS       0.4751V             0.6412V             0.3856V
  5.7143nS       0.4750V             0.6407V             0.3856V
  5.7959nS       0.4750V             0.6404V             0.3855V
  5.8776nS       0.4749V             0.6402V             0.3855V
  5.9592nS       0.4749V             0.6398V             0.3855V
  6.0408nS       0.4749V             0.6396V             0.3855V
  6.1224nS       0.4748V             0.6395V             0.3855V
  6.2041nS       0.4748V             0.6393V             0.3855V
  6.2857nS       0.4748V             0.6391V             0.3854V
  6.3673nS       0.4748V             0.6390V             0.3854V
  6.4490nS       0.4747V             0.6389V             0.3854V
  6.5306nS       0.4747V             0.6389V             0.3854V
  6.6122nS       0.4747V             0.6388V             0.3854V
  6.6939nS       0.4746V             0.6387V             0.3854V
  6.7755nS       0.4746V             0.6386V             0.3853V
  6.8571nS       0.4746V             0.6385V             0.3853V
  6.9388nS       0.4746V             0.6384V             0.3853V
  7.0204nS       0.4745V             0.6383V             0.3853V
  7.1020nS       0.4745V             0.6383V             0.3853V
  7.1837nS       0.4745V             0.6382V             0.3853V
  7.2653nS       0.4745V             0.6382V             0.3853V
  7.3469nS       0.4745V             0.6381V             0.3853V
  7.4286nS       0.4745V             0.6381V             0.3853V
  7.5102nS       0.4744V             0.6380V             0.3853V
  7.5918nS       0.4744V             0.6380V             0.3852V
  7.6735nS       0.4744V             0.6379V             0.3852V
  7.7551nS       0.4744V             0.6379V             0.3852V
  7.8367nS       0.4744V             0.6379V             0.3852V
  7.9184nS       0.4744V             0.6378V             0.3852V
  8.0000nS       0.4743V             0.6378V             0.3852V
|
[Falling Waveform]
R_fixture = 50.0000
V_fixture = 1.8000
V_fixture_min = 1.6500
V_fixture_max = 1.9500
| time           V(typ)              V(min)              V(max)
|
 0.000S          1.8000V             1.6500V             1.9500V
 81.6327pS       1.8000V             1.6500V             1.9500V
  0.1633nS       1.8000V             1.6500V             1.9500V
  0.2449nS       1.8000V             1.6500V             1.9500V
  0.3265nS       1.8000V             1.6500V             1.9500V
  0.4082nS       1.8000V             1.6500V             1.9517V
  0.4898nS       1.7999V             1.6500V             1.9530V
  0.5714nS       1.8004V             1.6500V             1.9538V
  0.6531nS       1.8018V             1.6500V             1.9528V
  0.7347nS       1.8024V             1.6500V             1.9435V
  0.8163nS       1.8026V             1.6500V             1.9287V
  0.8980nS       1.8028V             1.6502V             1.9012V
  0.9796nS       1.8020V             1.6508V             1.8591V
  1.0612nS       1.7974V             1.6514V             1.8056V
  1.1429nS       1.7882V             1.6517V             1.7851V
  1.2245nS       1.7723V             1.6518V             1.7635V
   1.3061nS       1.7589V             1.6518V             1.7505V
  1.3878nS       1.7475V             1.6516V             1.7391V
  1.4694nS       1.7269V             1.6513V             1.7345V
  1.5510nS       1.7114V             1.6508V             1.7299V
  1.6327nS       1.6918V             1.6504V             1.7267V
  1.7143nS       1.6714V             1.6501V             1.7259V
  1.7959nS       1.6612V             1.6464V             1.7250V
  1.8776nS       1.6510V             1.6414V             1.7249V
  1.9592nS       1.6458V             1.6378V             1.7248V
  2.0408nS       1.6410V             1.6298V             1.7247V
  2.1224nS       1.6361V             1.6258V             1.7247V
  2.2041nS       1.6337V             1.6165V             1.7246V
  2.2857nS       1.6326V             1.6082V             1.7246V
  2.3673nS       1.6315V             1.5997V             1.7246V
  2.4490nS       1.6304V             1.5911V             1.7246V
  2.5306nS       1.6298V             1.5838V             1.7246V
  2.6122nS       1.6297V             1.5761V             1.7246V
  2.6939nS       1.6296V             1.5685V             1.7246V
  2.7755nS       1.6295V             1.5575V             1.7246V
  2.8571nS       1.6294V             1.5539V             1.7246V
  2.9388nS       1.6294V             1.5503V             1.7246V
  3.0204nS       1.6294V             1.5466V             1.7246V
  3.1020nS       1.6294V             1.5417V             1.7246V
  3.1837nS       1.6293V             1.5405V             1.7245V
  3.2653nS       1.6293V             1.5393V             1.7245V
  3.3469nS       1.6293V             1.5380V             1.7245V
  3.4286nS       1.6293V             1.5368V             1.7245V
  3.5102nS       1.6293V             1.5353V             1.7245V
  3.5918nS       1.6293V             1.5350V             1.7245V
  3.6735nS       1.6293V             1.5348V             1.7245V
  3.7551nS       1.6293V             1.5345V             1.7245V
  3.8367nS       1.6293V             1.5343V             1.7245V
  3.9184nS       1.6293V             1.5340V             1.7245V
  4.0000nS       1.6293V             1.5340V             1.7245V
  4.0816nS       1.6293V             1.5339V             1.7245V
  4.1633nS       1.6293V             1.5339V             1.7245V
  4.2449nS       1.6293V             1.5338V             1.7245V
  4.3265nS       1.6293V             1.5338V             1.7245V
  4.4082nS       1.6293V             1.5338V             1.7245V
  4.4898nS       1.6293V             1.5338V             1.7245V
  4.5714nS       1.6293V             1.5338V             1.7245V
  4.6531nS       1.6293V             1.5337V             1.7245V
  4.7347nS       1.6293V             1.5337V             1.7245V
  4.8163nS       1.6293V             1.5337V             1.7245V
  4.8980nS       1.6293V             1.5337V             1.7245V
  4.9796nS       1.6293V             1.5337V             1.7245V
  5.0612nS       1.6293V             1.5337V             1.7245V
  5.1429nS       1.6293V             1.5337V             1.7245V
  5.2245nS       1.6293V             1.5337V             1.7245V
  5.3061nS       1.6293V             1.5337V             1.7245V
  5.3878nS       1.6293V             1.5337V             1.7245V
  5.4694nS       1.6293V             1.5337V             1.7245V
  5.5510nS       1.6293V             1.5337V             1.7245V
  5.6327nS       1.6293V             1.5337V             1.7245V
  5.7143nS       1.6293V             1.5337V             1.7245V
  5.7959nS       1.6293V             1.5337V             1.7245V
  5.8776nS       1.6293V             1.5337V             1.7245V
  5.9592nS       1.6293V             1.5337V             1.7245V
  6.0408nS       1.6293V             1.5337V             1.7245V
  6.1224nS       1.6293V             1.5337V             1.7245V
  6.2041nS       1.6293V             1.5337V             1.7245V
  6.2857nS       1.6293V             1.5337V             1.7245V
  6.3673nS       1.6293V             1.5337V             1.7245V
  6.4490nS       1.6293V             1.5337V             1.7245V
  6.5306nS       1.6293V             1.5337V             1.7245V
  6.6122nS       1.6293V             1.5337V             1.7245V
  6.6939nS       1.6293V             1.5337V             1.7245V
  6.7755nS       1.6293V             1.5337V             1.7245V
  6.8571nS       1.6293V             1.5337V             1.7245V
  6.9388nS       1.6293V             1.5337V             1.7245V
  7.0204nS       1.6293V             1.5337V             1.7245V
  7.1020nS       1.6293V             1.5337V             1.7245V
  7.1837nS       1.6293V             1.5337V             1.7245V
  7.2653nS       1.6293V             1.5337V             1.7245V
  7.3469nS       1.6293V             1.5337V             1.7245V
  7.4286nS       1.6293V             1.5337V             1.7245V
  7.5102nS       1.6293V             1.5337V             1.7245V
  7.5918nS       1.6293V             1.5337V             1.7245V
  7.6735nS       1.6293V             1.5337V             1.7245V
  7.7551nS       1.6293V             1.5337V             1.7245V
  7.8367nS       1.6293V             1.5337V             1.7245V
  7.9184nS       1.6293V             1.5337V             1.7245V
  8.0000nS       1.6293V             1.5337V             1.7245V
|
| End [Model] io_pu0_pk1_ddr0_lo
|
| End [Component] Skyeplus
|
[End]

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