From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #95 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Thursday, February 15 2007 Volume 01 : Number 095 ---------------------------------------------------------------------- Date: Thu, 25 Jan 2007 08:19:55 -0800 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] ibschk- warnings This is a multi-part message in MIME format. - ------_=_NextPart_001_01C7409C.A6CB797A Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sujit, =20 Please search the archives. I am sure you will=20 find some answers, as I have explained this about a zillion of times on these email forums. =20 Another alternative is to get help from the free IBIS model review committee. =20 http://www.eigroup.org/ibis/support.htm mailto:lgreen22@mindspring.com =20 Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.o= rg] On Behalf Of Sujit Kumar-r65837 Sent: Thursday, January 25, 2007 5:58 AM To: ibis-users@server.eda.org Subject: [IBIS-Users] ibschk- warnings hi ibis experts ibschk run on an ibis generates following warnings: IBISCHK4 V4.0.2 Checking ddr.ibs for IBIS 4.0 Compatibility... WARNING (line 219) - GND Clamp Typical data is non-monotonic WARNING (line 219) - GND Clamp Minimum data is non-monotonic WARNING (line 219) - GND Clamp Maximum data is non-monotonic WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]=20 with [R_fixture]=3D50 Ohms and [V_fixture]=3D0V has TYP column DC endpoints of 0.00V and 0.18v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.01V and 0.18V), a difference of 4.10% and 3.91%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform]=20 with [R_fixture]=3D500 Ohms and [V_fixture]=3D1.8V has TYP column DC endpoints of 0.47V and 1.80v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.50V and 1.80V), a difference of 2.18% and 0.00%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]=20 with [R_fixture]=3D500 Ohms and [V_fixture_min]=3D0V has MIN column DC endpoints of 0.00V and 0.96v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.02V and 0.96V), a difference of 2.14% and 0.59%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]=20 with [R_fixture]=3D50 Ohms and [V_fixture_min]=3D0V has MIN column DC endpoints of 0.00V and 0.12v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.01V and 0.13V), a difference of 4.58% and 4.47%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform]=20 with [R_fixture]=3D500 Ohms and [V_fixture_min]=3D1.65V has MIN column DC endpoints of 0.64V and 1.65v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.67V and 1.65V), a difference of 2.83% and 0.00%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]=20 with [R_fixture]=3D50 Ohms and [V_fixture_max]=3D0V has MAX column DC endpoints of 0.00V and 0.24v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.01V and 0.25V), a difference of 3.89% and 3.60%, respectively. WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling Waveform]=20 with [R_fixture]=3D500 Ohms and [V_fixture_max]=3D1.95V has MAX column DC endpoints of 0.39V and 1.95v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.42V and 1.95V), a difference of 2.06% and 0.01%, respectively. Errors : 0 Warnings: 10 File Passed i have following queries: > what could be the possible reason for such warnings ?=20 > as file is passing throgh ibschk, so can i neglect the above warnings ? pls suggest. .s2i and ibs file are attached for reference. - --=20 thanks sujit kumar +91-120-4396069 +91-09910168788=20 =20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is=20 believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C7409C.A6CB797A Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Sujit,
 
P= lease=20 search the archives.  I am sure you will
f= ind some=20 answers, as I have explained this about
a= zillion of=20 times on these email forums.
 
A= nother=20 alternative is to get help from the
f= ree IBIS=20 model review committee.
 
<= A=20 href=3D"http://www.eigroup.org/ibis/support.htm">http://www.eigroup.org/ibi= s/support.htm
<= A=20 href=3D"mailto:lgreen22@mindspring.com">mailto:lgreen22@mindspring.com<= /SPAN>
 
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D

From: owner-ibis-users@server.eda.org= =20 [mailto:owner-ibis-users@server.eda.org] On Behalf Of Sujit=20 Kumar-r65837
Sent: Thursday, January 25, 2007 5:58 AM
To:=20 ibis-users@server.eda.org
Subject: [IBIS-Users] ibschk-=20 warnings

hi ibis experts
ibschk run on an ibis generates following=20 warnings:

IBISCHK4 V4.0.2

Checking ddr.ibs for IBIS= 4.0=20 Compatibility...

WARNING (line  219) - GND Clamp Typical data i= s=20 non-monotonic
WARNING (line  219) - GND Clamp Minimum data is=20 non-monotonic
WARNING (line  219) - GND Clamp Maximum data is=20 non-monotonic
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising Waveform]= =20
      with [R_fixture]=3D50 Ohms and=20 [V_fixture]=3D0V
      has TYP column DC endpoi= nts=20 of  0.00V and  0.18v, but
      an=20 equivalent load applied to the model's I-V tables=20 yields
      different voltages ( 0.01V and&nbs= p;=20 0.18V),
      a difference of  4.10% and&n= bsp;=20 3.91%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling=20 Waveform]
      with [R_fixture]=3D500 Ohms an= d=20 [V_fixture]=3D1.8V
      has TYP column DC endp= oints=20 of  0.47V and  1.80v, but
      an=20 equivalent load applied to the model's I-V tables=20 yields
      different voltages ( 0.50V and&nbs= p;=20 1.80V),
      a difference of  2.18% and&n= bsp;=20 0.00%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising=20 Waveform]
      with [R_fixture]=3D500 Ohms an= d=20 [V_fixture_min]=3D0V
      has MIN column DC en= dpoints=20 of  0.00V and  0.96v, but
      an=20 equivalent load applied to the model's I-V tables=20 yields
      different voltages ( 0.02V and&nbs= p;=20 0.96V),
      a difference of  2.14% and&n= bsp;=20 0.59%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising=20 Waveform]
      with [R_fixture]=3D50 Ohms and= =20 [V_fixture_min]=3D0V
      has MIN column DC en= dpoints=20 of  0.00V and  0.12v, but
      an=20 equivalent load applied to the model's I-V tables=20 yields
      different voltages ( 0.01V and&nbs= p;=20 0.13V),
      a difference of  4.58% and&n= bsp;=20 4.47%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling=20 Waveform]
      with [R_fixture]=3D500 Ohms an= d=20 [V_fixture_min]=3D1.65V
      has MIN column DC= =20 endpoints of  0.64V and  1.65v, but
    &n= bsp;=20 an equivalent load applied to the model's I-V tables=20 yields
      different voltages ( 0.67V and&nbs= p;=20 1.65V),
      a difference of  2.83% and&n= bsp;=20 0.00%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Rising=20 Waveform]
      with [R_fixture]=3D50 Ohms and= =20 [V_fixture_max]=3D0V
      has MAX column DC en= dpoints=20 of  0.00V and  0.24v, but
      an=20 equivalent load applied to the model's I-V tables=20 yields
      different voltages ( 0.01V and&nbs= p;=20 0.25V),
      a difference of  3.89% and&n= bsp;=20 3.60%, respectively.
WARNING - Model io_pu0_pk1_ddr0_lo: The [Falling=20 Waveform]
      with [R_fixture]=3D500 Ohms an= d=20 [V_fixture_max]=3D1.95V
      has MAX column DC= =20 endpoints of  0.39V and  1.95v, but
    &n= bsp;=20 an equivalent load applied to the model's I-V tables=20 yields
      different voltages ( 0.42V and&nbs= p;=20 1.95V),
      a difference of  2.06% and&n= bsp;=20 0.01%, respectively.

Errors  : 0
Warnings: 10

File=20 Passed

i have following queries:
>  what coul= d be=20 the possible reason for such warnings ?
>  as  file is pas= sing=20 throgh ibschk, so can i neglect the above warnings ?

pls suggest..s2i=20 and ibs file are attached for reference.


--
thanks
sujit=20 kumar




+91-120-4396069
<= /SMALL>+91-09910168788=20



--=20
This message has been scanned for viruses and
dangerous content by = MailScanner, and is
be= lieved=20 to be clean.
--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------_=_NextPart_001_01C7409C.A6CB797A-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 25 Jan 2007 08:38:11 -0800 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] ibschk- warnings This is a multi-part message in MIME format. - ------_=_NextPart_001_01C7409F.359585AD Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Sujit, =20 As mentioned by others here, the errors are due to mismatches between your V-t table settling voltages and your I-V tables. The V-t appears "settled" to stable DC voltages, so the duration of your V-t tables may not be the problem; other factors may be causing the mismatch. =20 One concern: your [Rising Waveform] and [Falling Waveform] use different load resistances. One set uses 50 ohms, while the other uses 500. This is not a problem in itself, but the V-t tables should usually be generated into a load resistance roughly equivalent to the target system transmission line impedance. Is there a reason for using two different load resistances? The tables also only cover the cases of the pulldown transistors turning on or the pullup transistors turning on; the "turning off" cases are not covered (Rising only uses a 0V fixture, while Falling only uses Vcc as a fixture). "Turning off" cases can be valuable in simulation. =20 Another concern, looking at the [Pulldown] table, is that it appears to "double-count" power clamp effects shown in the [POWER Clamp] table. =20 You are also using S2IBIS2, which has since been upgraded to S2IBIS3. The updated version may address clamp double-counting and prevent this and other issues. =20 - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Sujit Kumar-r65837 Sent: Thursday, January 25, 2007 05:58 To: ibis-users@server.eda.org Subject: [IBIS-Users] ibschk- warnings hi ibis experts ibschk run on an ibis generates following warnings: i have following queries: > what could be the possible reason for such warnings ?=20 > as file is passing throgh ibschk, so can i neglect the above warnings ? pls suggest. .s2i and ibs file are attached for reference. - --=20 thanks sujit kumar +91-120-4396069 +91-09910168788=20 =20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C7409F.359585AD Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Sujit,
 
As mentioned by others here, the errors are due = to=20 mismatches between your V-t table settling voltages and your I-V tables.&nb= sp;=20 The V-t appears "settled" to stable DC voltages, so the duration of yo= ur=20 V-t tables may not be the problem; other factors may be causing the=20 mismatch.
 
One concern: your [Rising Waveform] and [Fa= lling=20 Waveform] use different load resistances.  One set uses 50 ohms, while= the=20 other uses 500.  This is not a problem in itself, but the V-t tab= les=20 should usually be generated into a load resistance roughly equiva= lent=20 to the target system transmission line impedance.  Is there a rea= son=20 for using two different load resistances?  The tables also only cover = the=20 cases of the pulldown transistors turning on or the pullup transistors turn= ing=20 on; the "turning off" cases are not covered (Rising only uses a 0V fixture,= =20 while Falling only uses Vcc as a fixture).  "Turning off" cases can be= =20 valuable in simulation.
Another concern, looking at the [Pulldown] = table,=20 is that it appears to "double-count" power clamp effects shown in the [POWE= R=20 Clamp] table.
 
You are also using S2IBIS2, which has since been= =20 upgraded to S2IBIS3.  The updated version may address clamp double-cou= nting=20 and prevent this and other issues.
 
- Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open=20 Forum

From: owner-ibis-users@server.eda.org= =20 [mailto:owner-ibis-users@server.eda.org] On Behalf Of Sujit=20 Kumar-r65837
Sent: Thursday, January 25, 2007 05:58
To:= =20 ibis-users@server.eda.org
Subject: [IBIS-Users] ibschk-=20 warnings

hi ibis experts
ibschk run on an ibis generates following=20 warnings:

i have following queries:
>  what could be the= =20 possible reason for such warnings ?
>  as  file is passing= =20 throgh ibschk, so can i neglect the above warnings ?

pls suggest..s2i=20 and ibs file are attached for reference.


--
thanks
sujit=20 kumar




+91-120-4396069
<= /SMALL>+91-09910168788=20



--=20
This message has been scanned for viruses and
dangerous content by = MailScanner, and is
be= lieved=20 to be clean.
--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------_=_NextPart_001_01C7409F.359585AD-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 25 Jan 2007 09:32:26 -0800 From: "Galindo, Javier \(Mission Systems\)" Subject: [IBIS-Users] Modeling of parasitics for discrete RLCs This is a multi-part message in MIME format. - ------_=_NextPart_001_01C740A6.C7F05487 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi, Just joined last night. I was looking into my company's IBIS model library and noticed that all our discretes passive components had the same values for parasitics, i.e. all our resistors and capacitors seemed to have the same parasitic RLC values regardless of package size, value, vendor, etc... So now I'm wondering: 1) I know depending on frequency parasitic values can have an effect, but is there a wide enough range in parasitic values from discrete passive component to discrete passive component to warrant me looking into this further? 2) Where does everyone else get their models for passive discrete components? Do most people just generate the model themselves or are their vendors you have some available? Thanks, Javy Digital Design Engineer Northrop Grumman - Rancho Carmel, San Diego CA 858 592-3014 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C740A6.C7F05487 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Modeling of parasitics for discrete RLCs

Hi,
Just joined last night. I was looking int= o my company's IBIS model library and noticed that all our discretes passiv= e components had the same values for parasitics, i.e. all our resistors and= capacitors seemed to have the same parasitic RLC values regardless of pack= age size, value, vendor, etc… So now I'm wondering:

1) I know depending on frequency parasitic= values can have an effect, but is there a wide enough range in parasitic v= alues from discrete passive component to discrete passive component to warr= ant me looking into this further?

2) Where does everyone else get their mode= ls for passive discrete components? Do most people just generate the model = themselves or are their vendors you have some available?

Thanks,
Javy
Digital Design Engineer
Northrop Grumman - Rancho Carmel, S= an Diego CA
858 592-3014


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------_=_NextPart_001_01C740A6.C7F05487-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 26 Jan 2007 11:11:48 -0800 From: "Mirmak, Michael" Subject: [IBIS-Users] Agenda, IBIS Summit Meeting at DesignCon for Feb. 1, 2007 - ------------------------------------------------------------------ AGENDA, IBIS SUMMIT MEETING Thursday, February 1, 2007 Santa Clara Convention Center Santa Clara, California Room: Cypress Room, Hyatt Regency Hotel (formerly the Westin Hotel) - ------------------------------------------------------------------ 8:00 AM Refreshments & Sign In 8:30 AM Official Opening - Welcome to Summit - Introductions - Opens for Issues, Discussion Topics 8:45 AM IBIS Chair's Report and Roadmap Michael Mirmak, Intel Corporation 9:00 AM Study of IBIS Waveform Time Offsets Mike LaBonte, Cisco Systems 9:30 AM Initial Time Delay Issue in IBIS VT Curves Lance Wang, Cadence Design Systems 10:00 AM BREAK 10:15 AM IBIS Quality Committee Report Kim Helliwell, LSI Logic 10:45 AM X Bob Ross, Teraspeed Consulting Group 11:00 AM Adaptive DFE Modeling using IBISv4.2/VHDL-AMS Luis Boluna, Ehsan Kabir, Susmita Mutsuddy and AbdulRahman Rafiq, Cisco systems 11:30 AM Statistical Eye Algorithm Implementation in VHDL-AMS Arpad Muranyi, Intel Corporation 12:00 PM LUNCH - (Hosted by Cisco Systems) Pre-registration required 1:00 PM IBIS Modeling of USB Buffers Sudarshan Honnudike, NXP Semiconductors 1:40 PM Opens/Discussions New Topics, Ad-Hoc Presentations 2:00 PM IBIS Advanced Technology Modeling Group (IBIS-ATM) Status Report Todd Westerhoff, Signal Integrity Software (SiSoft) 2:30 PM Concluding Items - Next Open Forum Meeting: February 16, 2007 - DATE 2007: April 19, 2007, Nice, France 2:45 PM BREAK, End of IBIS Summit Meeting 3:00 PM Open Discussion on ATM Proposals (You are welcome to stay or leave at any time) 7:00 PM End of Meeting Room Availability - ------------------------------------------------------------------ REGISTRATION INFORMATION People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Send to: Syed Huq (shuq@cisco.com) - ------------------------------------------------------------------ Sponsors: DesignCon, Cisco Systems DesignCon: January 29 - February 1, 2007 Santa Clara Convention Center Santa Clara, California See for more information. LIST OF NEARBY HOTELS See for travel directions, hotels and other information. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 02 Feb 2007 16:00:14 +0530 From: Anguraj K Subject: [IBIS-Users] Modeling Diff Buffers Hi Experts, Could you please answer my below questions? 1. If vdiff value varies for diff pins (due to diff modes of operation, namely speed), How do I define that in IBIS models. Through [Diff Pin] keyword, we can pass only one value to vdiff. 2. How to define common mode value in the diff signals? (I believe there are other IBIS users who raised the same question some time earlier) 3. When measuring C-Comp for drivers, I see three main variables on which die cap depends on. 1. Freq of operation 2. Data value (0 to vdd) to be sent 3. Process corners I vary these three variables and finding the max and min value for C_comp. Is that right? But, I usually see very huge die-cap for the drivers(unrealistic) - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 7 Feb 2007 10:34:01 +0530 From: Sudarshan Honnudike Subject: Re: [IBIS-Users] Modeling Diff Buffers This is a multipart message in MIME format. - --=_alternative 001B8BE26525727B_= Content-Type: text/plain; charset="US-ASCII" Hi Anguraj, I asked similar questions sometime back, but even I didnt get the answers. I will try to answer to your first 2 questions based on my experience. 1. Vdiff value can also be specified under [Receiver Thresholds] keyword. So if you have, say 2 speed modes of operation you need to have two [Model]'s for those 2 modes. As these two modes will have separate [Receiver Thresholds] section you can define 2 separate Vdiff under these 2 modes. The corresponding parameter to define Vdiff under [Receiver Thresholds] keyword is Vdiff_ac = 2. Similarly Common mode range can be specified under [Receiver Thresholds] keyword. The parameters corresponds to common mode range under [Receiver Thresholds] is Vcross_low = Vcross_high = For the third question , what i can suggest you is, to check the value what you are getting with the datasheet. That should confirm the correctness. Normally we vary the process corner and voltage applied to get the typ, min and max values of C_comp. Let me know if you find these answers helpful. Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com Anguraj K Sent by: owner-ibis-users@server.eda.org 2007-02-02 04:00 PM To ibis-users@server.eda.org cc Subject [IBIS-Users] Modeling Diff Buffers Classification Hi Experts, Could you please answer my below questions? 1. If vdiff value varies for diff pins (due to diff modes of operation, namely speed), How do I define that in IBIS models. Through [Diff Pin] keyword, we can pass only one value to vdiff. 2. How to define common mode value in the diff signals? (I believe there are other IBIS users who raised the same question some time earlier) 3. When measuring C-Comp for drivers, I see three main variables on which die cap depends on. 1. Freq of operation 2. Data value (0 to vdd) to be sent 3. Process corners I vary these three variables and finding the max and min value for C_comp. Is that right? But, I usually see very huge die-cap for the drivers(unrealistic) - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=_alternative 001B8BE26525727B_= Content-Type: text/html; charset="US-ASCII"
Hi Anguraj,

I asked similar questions sometime back, but even I didnt get the answers. I will try to answer to your first 2 questions
based on my experience.

1. Vdiff value can also be specified under [Receiver Thresholds] keyword. So if you have, say 2 speed modes of operation
you need to have two [Model]'s for those 2 modes. As these two modes will have separate [Receiver Thresholds] section
you can define 2 separate Vdiff under these 2 modes. The corresponding parameter to define Vdiff under [Receiver Thresholds] keyword is

Vdiff_ac =

2. Similarly Common mode range can be specified under [Receiver Thresholds] keyword. The parameters corresponds to common mode
range under  [Receiver Thresholds] is

Vcross_low =
Vcross_high =

For the third question , what i can suggest you is, to check the value what you are getting with the datasheet. That should confirm the correctness.
Normally we vary the process corner and voltage applied to get the typ, min and max values of C_comp.

Let me know if you find these answers helpful.

Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com







Anguraj K <b05108@freescale.com>

Sent by:
owner-ibis-users@server.eda.org

2007-02-02 04:00 PM

To
ibis-users@server.eda.org
cc
Subject
[IBIS-Users] Modeling Diff Buffers
Classification






Hi Experts,
Could you please answer my below questions?

1. If vdiff value varies for diff pins (due to diff modes of operation,
namely speed), How do I define that in IBIS models.
Through [Diff Pin] keyword, we can pass only one value to vdiff.

2. How to define common mode value in the diff signals? (I believe there
are other IBIS users who raised the same question some time earlier)

3. When measuring C-Comp for drivers,
I see three main variables on which die cap depends on.
1. Freq of operation
2. Data value (0 to vdd) to be sent
3. Process corners

I vary these three variables and finding the max and min value for
C_comp. Is that right?
But,  I usually see very huge die-cap for the drivers(unrealistic)






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This message has been scanned for viruses and
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believed to be clean. - --=_alternative 001B8BE26525727B_=-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 07 Feb 2007 18:09:11 +0530 From: Anguraj_Kothandapani-b05108 Subject: Re: [IBIS-Users] Modeling Diff Buffers - --------------060104000408020501010907 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Hi Sudharshan, Thanks a lot for your response! 1 & 2) I tried searching for the keywords in cook book but in vain.Could you help me point to the docs/pdfs where I can get all these special keywords. 3) I followed sec 4.7 of IBIS cook book to generate the C-Comp for drivers 1. Vary P,V (voltage input to data in), T 2. Find the max and min and add them to tables 3. Avg becomes the typ for C-comp Should I change this methodology? Once again thanks for your inputs! Thanks, Anguraj Sudarshan Honnudike wrote: > > Hi Anguraj, > > I asked similar questions sometime back, but even I didnt get the > answers. I will try to answer to your first 2 questions > based on my experience. > > 1. Vdiff value can also be specified under [Receiver Thresholds] > keyword. So if you have, say 2 speed modes of operation > you need to have two [Model]'s for those 2 modes. As these two modes > will have separate [Receiver Thresholds] section > you can define 2 separate Vdiff under these 2 modes. The corresponding > parameter to define Vdiff under [Receiver Thresholds] keyword is > > Vdiff_ac = > > 2. Similarly Common mode range can be specified under [Receiver > Thresholds] keyword. The parameters corresponds to common mode > range under [Receiver Thresholds] is > > Vcross_low = > Vcross_high = > > For the third question , what i can suggest you is, to check the value > what you are getting with the datasheet. That should confirm the > correctness. > Normally we vary the process corner and voltage applied to get the > typ, min and max values of C_comp. > > Let me know if you find these answers helpful. > > Best Regards, > > Sudarshan HN > NXP Semiconductors/CTO /PLT > C-4, Manyata Tech Park, Nagawara > Bangalore-560 045 , India. > Ph:+91-80-40267073 > Fax: +91-80-4026 7855 > seri:sudarsha@inpsblr > E-mail: sudarshan.honnudike@nxp.com > > > > > > > > Anguraj K > > Sent by: > owner-ibis-users@server.eda.org > > 2007-02-02 04:00 PM > > To > ibis-users@server.eda.org > cc > > Subject > [IBIS-Users] Modeling Diff Buffers > Classification > > > > > > > > > > Hi Experts, > Could you please answer my below questions? > > 1. If vdiff value varies for diff pins (due to diff modes of operation, > namely speed), How do I define that in IBIS models. > Through [Diff Pin] keyword, we can pass only one value to vdiff. > > 2. How to define common mode value in the diff signals? (I believe there > are other IBIS users who raised the same question some time earlier) > > 3. When measuring C-Comp for drivers, > I see three main variables on which die cap depends on. > 1. Freq of operation > 2. Data value (0 to vdd) to be sent > 3. Process corners > > I vary these three variables and finding the max and min value for > C_comp. Is that right? > But, I usually see very huge die-cap for the drivers(unrealistic) > > > > > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > -------------------------------------------------------------------- > |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org > |with the appropriate command message(s) in the body: > | > | help > | subscribe ibis > | subscribe ibis-users > | unsubscribe ibis > | unsubscribe ibis-users > | > |or e-mail a request to ibis-request@eda-stds.org. > | > |IBIS reflector archives exist under: > | > | http://www.eda-stds.org/pub/ibis/email_archive/ Recent > | http://www.eda-stds.org/pub/ibis/users_archive/ Recent > | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 > - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --------------060104000408020501010907 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Sudharshan,

Thanks a lot for your response!

1 & 2) I tried searching for the keywords in cook book but in vain.Could you help me point to the docs/pdfs where I can get all these special keywords.

3)  I followed sec 4.7 of IBIS cook book to generate the C-Comp for drivers
1. Vary P,V (voltage input to data in), T
2.  Find the max and min and add them to tables
3. Avg becomes the typ for C-comp

Should I change this methodology?

Once again thanks for your inputs!

Thanks,
Anguraj

Sudarshan Honnudike wrote:

Hi Anguraj,

I asked similar questions sometime back, but even I didnt get the answers. I will try to answer to your first 2 questions
based on my experience.

1. Vdiff value can also be specified under [Receiver Thresholds] keyword. So if you have, say 2 speed modes of operation
you need to have two [Model]'s for those 2 modes. As these two modes will have separate [Receiver Thresholds] section
you can define 2 separate Vdiff under these 2 modes. The corresponding parameter to define Vdiff under [Receiver Thresholds] keyword is

Vdiff_ac =

2. Similarly Common mode range can be specified under [Receiver Thresholds] keyword. The parameters corresponds to common mode
range under  [Receiver Thresholds] is

Vcross_low =
Vcross_high =

For the third question , what i can suggest you is, to check the value what you are getting with the datasheet. That should confirm the correctness.
Normally we vary the process corner and voltage applied to get the typ, min and max values of C_comp.

Let me know if you find these answers helpful.

Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com







Anguraj K <b05108@freescale.com>

Sent by:
owner-ibis-users@server.eda.org

2007-02-02 04:00 PM

To
 ibis-users@server.eda.org
cc
Subject
 [IBIS-Users] Modeling Diff Buffers
Classification








Hi Experts,
Could you please answer my below questions?

1. If vdiff value varies for diff pins (due to diff modes of operation,
namely speed), How do I define that in IBIS models.
Through [Diff Pin] keyword, we can pass only one value to vdiff.

2. How to define common mode value in the diff signals? (I believe there
are other IBIS users who raised the same question some time earlier)

3. When measuring C-Comp for drivers,
I see three main variables on which die cap depends on.
1. Freq of operation
2. Data value (0 to vdd) to be sent
3. Process corners

I vary these three variables and finding the max and min value for
C_comp. Is that right?
But,  I usually see very huge die-cap for the drivers(unrealistic)






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believed to be clean. - --------------060104000408020501010907-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 07 Feb 2007 15:51:23 +0200 From: "Dimitry Eisenshtat" Subject: Re: [IBIS-Users] Modeling Diff Buffers Hi Anguraj, about C_comp value issue, I only like to say that in Ver4 Cookbook there is a link to pdf document described so called L-tank method (http://www.eda.org/ibis/summits/jun02/hegazy.pdf by Hazem Hegazy). I use it and I think it makes sense. In this method the frequency dependence of C_comp is omitted and you get one single value of C_comp (you should still vary DC bias and corner conditions, of course) calculated from resonance equation. I do it with HSpice, feel free to ask me if you need help with this. regards, Dmitry Anguraj_Kothandapani-b05108 wrote: > Hi Sudharshan, > > Thanks a lot for your response! > > 1 & 2) I tried searching for the keywords in cook book but in vain.Could > you help me point to the docs/pdfs where I can get all these special > keywords. > > 3) I followed sec 4.7 of IBIS cook book to generate the C-Comp for drivers > 1. Vary P,V (voltage input to data in), T > 2. Find the max and min and add them to tables > 3. Avg becomes the typ for C-comp > > Should I change this methodology? > > Once again thanks for your inputs! > > Thanks, > Anguraj > > Sudarshan Honnudike wrote: > >> >> Hi Anguraj, >> >> I asked similar questions sometime back, but even I didnt get the >> answers. I will try to answer to your first 2 questions >> based on my experience. >> >> 1. Vdiff value can also be specified under [Receiver Thresholds] >> keyword. So if you have, say 2 speed modes of operation >> you need to have two [Model]'s for those 2 modes. As these two modes >> will have separate [Receiver Thresholds] section >> you can define 2 separate Vdiff under these 2 modes. The corresponding >> parameter to define Vdiff under [Receiver Thresholds] keyword is >> >> Vdiff_ac = >> >> 2. Similarly Common mode range can be specified under [Receiver >> Thresholds] keyword. The parameters corresponds to common mode >> range under [Receiver Thresholds] is >> >> Vcross_low = >> Vcross_high = >> >> For the third question , what i can suggest you is, to check the value >> what you are getting with the datasheet. That should confirm the >> correctness. >> Normally we vary the process corner and voltage applied to get the >> typ, min and max values of C_comp. >> >> Let me know if you find these answers helpful. >> >> Best Regards, >> >> Sudarshan HN >> NXP Semiconductors/CTO /PLT >> C-4, Manyata Tech Park, Nagawara >> Bangalore-560 045 , India. >> Ph:+91-80-40267073 >> Fax: +91-80-4026 7855 >> seri:sudarsha@inpsblr >> E-mail: sudarshan.honnudike@nxp.com >> >> >> >> >> >> >> >> *Anguraj K * >> >> Sent by: >> owner-ibis-users@server.eda.org >> >> 2007-02-02 04:00 PM >> >> >> To >> ibis-users@server.eda.org >> cc >> >> Subject >> [IBIS-Users] Modeling Diff Buffers >> Classification >> >> >> >> >> >> >> >> >> >> >> >> Hi Experts, >> Could you please answer my below questions? >> >> 1. If vdiff value varies for diff pins (due to diff modes of operation, >> namely speed), How do I define that in IBIS models. >> Through [Diff Pin] keyword, we can pass only one value to vdiff. >> >> 2. How to define common mode value in the diff signals? (I believe there >> are other IBIS users who raised the same question some time earlier) >> >> 3. When measuring C-Comp for drivers, >> I see three main variables on which die cap depends on. >> 1. Freq of operation >> 2. Data value (0 to vdd) to be sent >> 3. Process corners >> >> I vary these three variables and finding the max and min value for >> C_comp. Is that right? >> But, I usually see very huge die-cap for the drivers(unrealistic) >> >> >> >> >> >> >> -- >> This message has been scanned for viruses and >> dangerous content by MailScanner, and is >> believed to be clean. >> >> -------------------------------------------------------------------- >> |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org >> |with the appropriate command message(s) in the body: >> | >> | help >> | subscribe ibis >> | subscribe ibis-users >> | unsubscribe ibis >> | unsubscribe ibis-users >> | >> |or e-mail a request to ibis-request@eda-stds.org. >> | >> |IBIS reflector archives exist under: >> | >> | http://www.eda-stds.org/pub/ibis/email_archive/ Recent >> | http://www.eda-stds.org/pub/ibis/users_archive/ Recent >> | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 >> > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. - -- +----------------------------------------+ | Dimitry Eisenshtat | | Circuit Design Engineer, | | Winbond Israel | | mailto:Dimitry.Eisenshtat@winbond.com | +----------------------------------------+ =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Winbond is strictly prohibited; and any information in this email irrelevant to the official business of Winbond shall be deemed as neither given nor endorsed by Winbond. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 7 Feb 2007 19:35:41 +0530 From: Sudarshan Honnudike Subject: Re: [IBIS-Users] Modeling Diff Buffers This is a multipart message in MIME format. - --=_alternative 004D232C6525727B_= Content-Type: text/plain; charset="US-ASCII" Hi Anguraj, You can refer the 4.2 specification document. http://www.vhdl.org/pub/ibis/ver4.2/ver4_2.pdf - page 42 Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com Anguraj_Kothandapani-b05108 2007-02-07 06:09 PM To Sudarshan Honnudike cc ibis-users@eda.org owner-ibis-users@eda.org Subject Re: [IBIS-Users] Modeling Diff Buffers Classification Hi Sudharshan, Thanks a lot for your response! 1 & 2) I tried searching for the keywords in cook book but in vain.Could you help me point to the docs/pdfs where I can get all these special keywords. 3) I followed sec 4.7 of IBIS cook book to generate the C-Comp for drivers 1. Vary P,V (voltage input to data in), T 2. Find the max and min and add them to tables 3. Avg becomes the typ for C-comp Should I change this methodology? Once again thanks for your inputs! Thanks, Anguraj Sudarshan Honnudike wrote: Hi Anguraj, I asked similar questions sometime back, but even I didnt get the answers. I will try to answer to your first 2 questions based on my experience. 1. Vdiff value can also be specified under [Receiver Thresholds] keyword. So if you have, say 2 speed modes of operation you need to have two [Model]'s for those 2 modes. As these two modes will have separate [Receiver Thresholds] section you can define 2 separate Vdiff under these 2 modes. The corresponding parameter to define Vdiff under [Receiver Thresholds] keyword is Vdiff_ac = 2. Similarly Common mode range can be specified under [Receiver Thresholds] keyword. The parameters corresponds to common mode range under [Receiver Thresholds] is Vcross_low = Vcross_high = For the third question , what i can suggest you is, to check the value what you are getting with the datasheet. That should confirm the correctness. Normally we vary the process corner and voltage applied to get the typ, min and max values of C_comp. Let me know if you find these answers helpful. Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com Anguraj K Sent by: owner-ibis-users@server.eda.org 2007-02-02 04:00 PM To ibis-users@server.eda.org cc Subject [IBIS-Users] Modeling Diff Buffers Classification Hi Experts, Could you please answer my below questions? 1. If vdiff value varies for diff pins (due to diff modes of operation, namely speed), How do I define that in IBIS models. Through [Diff Pin] keyword, we can pass only one value to vdiff. 2. How to define common mode value in the diff signals? (I believe there are other IBIS users who raised the same question some time earlier) 3. When measuring C-Comp for drivers, I see three main variables on which die cap depends on. 1. Freq of operation 2. Data value (0 to vdd) to be sent 3. Process corners I vary these three variables and finding the max and min value for C_comp. Is that right? But, I usually see very huge die-cap for the drivers(unrealistic) - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=_alternative 004D232C6525727B_= Content-Type: text/html; charset="US-ASCII"
Hi Anguraj,

You can refer the 4.2 specification document.

http://www.vhdl.org/pub/ibis/ver4.2/ver4_2.pdf                 - page 42


Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com







Anguraj_Kothandapani-b05108 <b05108@freescale.com>

2007-02-07 06:09 PM

To
Sudarshan Honnudike <sudarshan.honnudike@nxp.com>
cc
ibis-users@eda.org
owner-ibis-users@eda.org
Subject
Re: [IBIS-Users] Modeling Diff Buffers
Classification





Hi Sudharshan,

Thanks a lot for your response!

1 & 2) I tried searching for the keywords in cook book but in vain.Could you help me point to the docs/pdfs where I can get all these special keywords.

3)  I followed sec 4.7 of IBIS cook book to generate the C-Comp for drivers
1. Vary P,V (voltage input to data in), T
2.  Find the max and min and add them to tables
3. Avg becomes the typ for C-comp

Should I change this methodology?

Once again thanks for your inputs!

Thanks,
Anguraj

Sudarshan Honnudike wrote:

Hi Anguraj,

I asked similar questions sometime back, but even I didnt get the answers. I will try to answer to your first 2 questions
based on my experience.

1. Vdiff value can also be specified under [Receiver Thresholds] keyword. So if you have, say 2 speed modes of operation
you need to have two [Model]'s for those 2 modes. As these two modes will have separate [Receiver Thresholds] section
you can define 2 separate Vdiff under these 2 modes. The corresponding parameter to define Vdiff under [Receiver Thresholds] keyword is

Vdiff_ac =

2. Similarly Common mode range can be specified under [Receiver Thresholds] keyword. The parameters corresponds to common mode
range under  [Receiver Thresholds] is

Vcross_low =
Vcross_high =

For the third question , what i can suggest you is, to check the value what you are getting with the datasheet. That should confirm the correctness.
Normally we vary the process corner and voltage applied to get the typ, min and max values of C_comp.

Let me know if you find these answers helpful.

Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com






Anguraj K <b05108@freescale.com>

Sent by:
owner-ibis-users@server.eda.org

2007-02-02 04:00 PM


To
ibis-users@server.eda.org
cc
Subject
[IBIS-Users] Modeling Diff Buffers
Classification








Hi Experts,
Could you please answer my below questions?

1. If vdiff value varies for diff pins (due to diff modes of operation,
namely speed), How do I define that in IBIS models.
Through [Diff Pin] keyword, we can pass only one value to vdiff.

2. How to define common mode value in the diff signals? (I believe there
are other IBIS users who raised the same question some time earlier)

3. When measuring C-Comp for drivers,
I see three main variables on which die cap depends on.
1. Freq of operation
2. Data value (0 to vdd) to be sent
3. Process corners

I vary these three variables and finding the max and min value for
C_comp. Is that right?
But,  I usually see very huge die-cap for the drivers(unrealistic)






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|  http://www.eda-stds.org/pub/ibis/users_archive/ Recent
|  http://www.eda-stds.org/pub/ibis/email/         E-mail since 1993


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believed to be clean. - --=_alternative 004D232C6525727B_=-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 7 Feb 2007 20:07:54 +0530 From: Sudarshan Honnudike Subject: [IBIS-Users] Rref and R_fixture clarifications This is a multipart message in MIME format. - --=_alternative 005016566525727B_= Content-Type: text/plain; charset="US-ASCII" Hi Lynne and all, Actually I am taking one of my previous question and I am asking this question also. Sometime back lynne has mentioned that, Rref and Cref are for timing checks and R_fixture corresponds to loading conditions. And he also mentions that one should not use reactive loads to measure V-t tables as it breaks some of the tool's algorithms. Now i have a specific case. For IIC we need to connect a load of 400 pF. Its a very slow cell. Its a IIC system requirement. In the specification they say, in a system there will be around 40 recievers connected to 1 driver through IIC bus. If you convert the distributed loading of these 40 Rcx to 1 lumped loading it comes around 400 pF. So do i need to connect a C_fixture of 400 pF load while generating V-t tables ? If not where this load should be specified and what load has to be used for generating V-t tables? Let me know your response. Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com "Lynne D. Green" 2007-01-10 04:33 PM To "'Alex Hilbers'" "'Sudarshan Honnudike'" cc Subject RE: [IBIS-Users] Information on Vref, Rref & Cref Classification I was somewhat confused about the loading question and reply. Rref and Cref are for timing checks, not for simulation. The loading for V-t tables is R_fixture. So both are needed in a model. One should not use reactive loading in a V-t table. This has been observed to "break" the algorithm as implemented by some SI tools. The underlying algorithms have been published in two papers: * The Development of Analog SPICE Behavioral Model Based on IBIS Model Ying Wang & Han Ngee Tan * Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS P. Tehrani, Y. Chen & J. Fang - - Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Alex Hilbers Sent: Wednesday, January 10, 2007 1:47 AM To: Sudarshan Honnudike; ibis-users@eda.org Subject: RE: [IBIS-Users] Information on Vref, Rref & Cref Sudarshan, Interesting question. I always wondered how a table based model (V-I, ..), such as an IBIS model, could model any form of feedback control system, as the IO pad you describe probably is. It seems that V-t waveforms, together with a simulation tool specific algorithm, must do that job. You verify this by comparing your simulation tool with actual SPICE results. This is prone to variation based on which tool you use, I donot think this 'algorithm' is standardised. To my knowledge XTK needs the curves rising/falling, for load to VCC and GND (i.e. all 4), otherwise the V-t tables are ignored. (Some vendors do provide only 1 or 2, which is useless). Interesting is what happens if you define several load conditions (Rfixture = 25, 50, 75 Ohms), not to mention capacitive and inductive loading. What will the simualtion tool choose, will it interpolate, I donot have the faintest idea. I guess it won't work within IBIS, which may be the reason you do not get answers. Maybe a good reason to provide SPICE models for this type of buffer. Either under NDA or encrypted. Level 50 HSPICE, i.e. Philips MOS Model 9, should be fine. Best regards, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Alex Hilbers Signal Integrity Analysis and Thermal Management, ASML, EDEV department Building 7J0005, P.O. Box 324, 5500 AH Veldhoven, The Netherlands Phone: +31-(0)40-268 5587, Fax: +31-(0)40-268 5530 Email: alex.hilbers@asml.com, www.asml.com < http://www.asml.com/> ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Sudarshan Honnudike Sent: Wednesday, January 10, 2007 6:35 AM To: ibis-users@eda.org Subject: [IBIS-Users] Information on Vref, Rref & Cref Hi , If we have a IO pad which works in the different applications depending on the load applied on it, then do we to provide V-t waveforms(more than normal 4 curves) for different applications with different load settings.? Or can we specify that loading conditions under Rref, Vref and Cref for that model. Which one is preferable. ? I tested my model with Hyperlynx SI tool and it is not identifying the Rref and Vref values that I am specifying in my model. It will only take Cref and Vmeas while doing simulations. In that case we can't specify the loading conditions under Vref, Cref and Vref but we need to give all possible V-t curve combinations for different loading conditions. Please let me know your reply. PS : I am also waiting for the reply to my previous mail regarding Common Mode Voltage Range support in IBIS . Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com -- This message has been scanned for viruses and dangerous content by MailScanner < http://www.mailscanner.info/> , and is believed to be clean. -- The information contained in this communication and any attachments is confidential and may be privileged, and is for the sole use of the intended recipient(s). Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please notify the sender immediately by replying to this message and destroy all copies of this message and any attachments. ASML is neither liable for the proper and complete transmission of the information contained in this communication, nor for any delay in its receipt. -- This message has been scanned for viruses and dangerous content by MailScanner < http://www.mailscanner.info/> , and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=_alternative 005016566525727B_= Content-Type: text/html; charset="US-ASCII"
Hi Lynne and all,

Actually I am taking one of my previous question and I am asking this question also.

Sometime back lynne has mentioned that, Rref and Cref are for timing checks and R_fixture corresponds to
loading conditions. And he also mentions that one should not use reactive loads to measure V-t tables as it
breaks some of the tool's algorithms.

Now i have a specific case.  For IIC we need to connect a load of 400 pF. Its a very slow cell. Its a IIC system requirement.
In the specification they say, in a system there will be around 40 recievers connected to 1 driver through IIC bus. If you convert
the distributed loading of these 40 Rcx to 1 lumped loading it comes around 400 pF.

So do i need to connect a C_fixture of 400 pF load while generating V-t tables ? If not where this load should be specified and what load has to be used for generating V-t tables?

Let me know your response.

Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com







"Lynne D. Green" <lgreen22@mindspring.com>

2007-01-10 04:33 PM

To
"'Alex Hilbers'" <alex.hilbers@asml.com>
"'Sudarshan Honnudike'" <sudarshan.honnudike@nxp.com>
<ibis-users@eda.org>
cc
Subject
RE: [IBIS-Users] Information on Vref, Rref & Cref
Classification





I was somewhat confused about the loading question and reply.

Rref and Cref are for timing checks, not for simulation.  The loading for
V-t tables is R_fixture.  So both are needed in a model.

One should not use reactive loading in a V-t table.  This has been observed
to "break" the algorithm as implemented by some SI tools.

The underlying algorithms have been published in two papers:
* The Development of Analog SPICE Behavioral Model Based on IBIS Model
Ying Wang & Han Ngee Tan  
* Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS
P. Tehrani, Y. Chen & J. Fang

- - Lynne


"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com


________________________________

                From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Alex Hilbers
                Sent: Wednesday, January 10, 2007 1:47 AM
                To: Sudarshan Honnudike; ibis-users@eda.org
                Subject: RE: [IBIS-Users] Information on Vref, Rref & Cref
               
               
                Sudarshan,
                 
                Interesting question. I always wondered how a table based model
(V-I, ..), such as an IBIS model, could model any form of feedback control
system, as the IO pad you describe probably is. It seems that V-t waveforms,
together with a simulation tool specific algorithm, must do that job. You
verify this by comparing your simulation tool with actual SPICE results.
This is prone to variation based on which tool you use, I donot think this
'algorithm' is standardised. To my knowledge XTK needs the curves
rising/falling, for load to VCC and GND (i.e. all 4), otherwise the V-t
tables are ignored. (Some vendors do provide only 1 or 2, which is useless).
Interesting is what happens if you define several load conditions (Rfixture
= 25, 50, 75 Ohms), not to mention capacitive and inductive loading. What
will the simualtion tool choose, will it interpolate, I donot have the
faintest idea. I guess it won't work within IBIS, which may be the reason
you do not get answers.
                 
                Maybe a good reason to provide SPICE models for this type of buffer.
Either under NDA or encrypted. Level 50 HSPICE, i.e. Philips MOS Model 9,
should be fine.
                 
                Best regards,
               
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                Alex Hilbers
                Signal Integrity Analysis and Thermal Management, ASML, EDEV
department

                Building 7J0005, P.O. Box 324, 5500 AH Veldhoven, The Netherlands
                Phone: +31-(0)40-268 5587, Fax: +31-(0)40-268 5530
                Email: alex.hilbers@asml.com, www.asml.com <http://www.asml.com/>
               

                                 

________________________________

                From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Sudarshan Honnudike
                Sent: Wednesday, January 10, 2007 6:35 AM
                To: ibis-users@eda.org
                Subject: [IBIS-Users] Information on Vref, Rref & Cref
               
               

                Hi ,
               
                If we have a IO pad which works in the different applications
depending on the load applied
                on it, then do we to  provide V-t waveforms(more than normal 4
curves) for different applications
                with different load settings.?
               
                Or can we specify that loading conditions under Rref, Vref and Cref
for that model. Which one is preferable. ?
               
                I tested my model with Hyperlynx SI tool and it is not identifying
the Rref and Vref values that I am specifying
                in my model. It will only take Cref and Vmeas while doing
simulations. In that case we can't specify the loading
                conditions under Vref, Cref and Vref but we need to give all
possible V-t curve combinations for different loading conditions.
               
                Please let me know your reply.
               
                PS : I am also waiting for the reply to my previous mail regarding
Common Mode Voltage Range support in IBIS .
               
                Best Regards,
               
                Sudarshan HN
                NXP Semiconductors/CTO /PLT
                C-4, Manyata Tech Park, Nagawara
                Bangalore-560 045 , India.    
                Ph:+91-80-40267073  
                Fax: +91-80-4026 7855
                seri:sudarsha@inpsblr
                E-mail: sudarshan.honnudike@nxp.com
                - --
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of the intended recipient(s). Any unauthorized review, use, disclosure or
distribution is prohibited. If you are not the intended recipient, please
notify the sender immediately by replying to this message and destroy all
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--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --=_alternative 005016566525727B_=-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 7 Feb 2007 09:50:54 -0800 From: "Tom Dagostino" Subject: RE: [IBIS-Users] Rref and R_fixture clarifications This is a multi-part message in MIME format. - ------=_NextPart_000_02A8_01C74A9D.75D01300 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Do not use the 400 pF as a load during VT table extraction. In an actual circuit implementation the load seen by the driver is a combination of transmission lines and lumped loads. in 99.999% of the cases the first thing the driver is going to see is a segment of transmission line. It will never see a 400 pF lumped load. The capacitive loads will be distributed linked together by segments of transmission lines. Let the SI simulator take care of the topology of the loads. If you slow the driver by placing heavy loads on it during VT extractions the SI simulator will have to compute the unloaded VT curves which, from my experience, does not work well. =20 The model's job is to describe the buffer's characteristics. The SI simulator's job is to show how the driver interacts with the board's environment. =20 =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Sudarshan Honnudike Sent: Wednesday, February 07, 2007 6:38 AM To: Lynne D. Green; ibis-users@server.eda.org Subject: [IBIS-Users] Rref and R_fixture clarifications Hi Lynne and all,=20 Actually I am taking one of my previous question and I am asking this question also.=20 Sometime back lynne has mentioned that, Rref and Cref are for timing checks and R_fixture corresponds to=20 loading conditions. And he also mentions that one should not use reactive loads to measure V-t tables as it=20 breaks some of the tool's algorithms.=20 Now i have a specific case. For IIC we need to connect a load of 400 pF. Its a very slow cell. Its a IIC system requirement.=20 In the specification they say, in a system there will be around 40 recievers connected to 1 driver through IIC bus. If you convert=20 the distributed loading of these 40 Rcx to 1 lumped loading it comes around 400 pF.=20 So do i need to connect a C_fixture of 400 pF load while generating V-t tables ? If not where this load should be specified and what load has to be used for generating V-t tables?=20 Let me know your response.=20 Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India.=20=20=20=20 Ph:+91-80-40267073=20=20 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com=20 "Lynne D. Green" =20 2007-01-10 04:33 PM=20 To "'Alex Hilbers'" "'Sudarshan Honnudike'" =20 cc Subject RE: [IBIS-Users] Information on Vref, Rref & Cref=20 Classification =09 I was somewhat confused about the loading question and reply. Rref and Cref are for timing checks, not for simulation. The loading for V-t tables is R_fixture. So both are needed in a model. One should not use reactive loading in a V-t table. This has been observed to "break" the algorithm as implemented by some SI tools. The underlying algorithms have been published in two papers: * The Development of Analog SPICE Behavioral Model Based on IBIS Model Ying Wang & Han Ngee Tan=20=20 * Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS P. Tehrani, Y. Chen & J. Fang - - Lynne=20 "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Alex Hilbers Sent: Wednesday, January 10, 2007 1:47 AM To: Sudarshan Honnudike; ibis-users@eda.org Subject: RE: [IBIS-Users] Information on Vref, Rref & Cref =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Sudarshan, =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Interesting question. I always wondered how a table based model (V-I, ..), such as an IBIS model, could model any form of feedback control system, as the IO pad you describe probably is. It seems that V-t waveforms, together with a simulation tool specific algorithm, must do that job. You verify this by comparing your simulation tool with actual SPICE results. This is prone to variation based on which tool you use, I donot think this 'algorithm' is standardised. To my knowledge XTK needs the curves rising/falling, for load to VCC and GND (i.e. all 4), otherwise the V-t tables are ignored. (Some vendors do provide only 1 or 2, which is useless). Interesting is what happens if you define several load conditions (Rfixture =3D 25, 50, 75 Ohms), not to mention capacitive and inductive loading. What will the simualtion tool choose, will it interpolate, I donot have the faintest idea. I guess it won't work within IBIS, which may be the reason you do not get answers.=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Maybe a good reason to provide SPICE models for this type of buffer. Either under NDA or encrypted. Level 50 HSPICE, i.e. Philips MOS Model 9, should be fine.=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Best regards, =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Alex Hilbers=20 Signal Integrity Analysis and Thermal Management, ASML, EDEV department Building 7J0005, P.O. Box 324, 5500 AH Veldhoven, The Netherlands Phone: +31-(0)40-268 5587, Fax: +31-(0)40-268 5530 Email: alex.hilbers@asml.com, www.asml.com =20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20 ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Sudarshan Honnudike Sent: Wednesday, January 10, 2007 6:35 AM To: ibis-users@eda.org Subject: [IBIS-Users] Information on Vref, Rref & Cref =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Hi ,=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 If we have a IO pad which works in the different applications depending on the load applied=20 on it, then do we to provide V-t waveforms(more than normal 4 curves) for different applications=20 with different load settings.?=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Or can we specify that loading conditions under Rref, Vref and Cref for that model. Which one is preferable. ?=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 I tested my model with Hyperlynx SI tool and it is not identifying the Rref and Vref values that I am specifying=20 in my model. It will only take Cref and Vmeas while doing simulations. In that case we can't specify the loading=20 conditions under Vref, Cref and Vref but we need to give all possible V-t curve combinations for different loading conditions.=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Please let me know your reply.=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 PS : I am also waiting for the reply to my previous mail regarding Common Mode Voltage Range support in IBIS .=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Best Regards, =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India.=20=20=20=20 Ph:+91-80-40267073=20=20 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is=20 believed to be clean.=20 -- The information contained in this communication and any attachments is confidential and may be privileged, and is for the sole use of the intended recipient(s). Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please notify the sender immediately by replying to this message and destroy all copies of this message and any attachments. ASML is neither liable for the proper and complete transmission of the information contained in this communication, nor for any delay in its receipt.=20 --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is=20 believed to be clean.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner, and is=20 believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_02A8_01C74A9D.75D01300 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Message
Do not=20 use the 400 pF as a load during VT table extraction.  In an actual cir= cuit=20 implementation the load seen by the driver is a combination of transmission= =20 lines and lumped loads.  in 99.999% of the cases the first thing the d= river=20 is going to see is a segment of transmission line.  It will never see = a 400=20 pF lumped load.  The capacitive loads will be distributed linked toget= her=20 by segments of transmission lines. Let the SI simulator take care of the=20 topology of the loads.  If you slow the driver by placing heavy loads = on it=20 during VT extractions the SI simulator will have to compute the unloaded VT= =20 curves which, from my experience, does not work well.
 
The=20 model's job is to describe the buffer's characteristics.  The SI=20 simulator's job is to show how the driver interacts with the board's=20 environment.
 
 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness=20 Lane
Beaverton, OR=20 97008
503-430-1065
tom@teraspeed.com
www.teraspeed.com

Tera= speed=20 Consulting Group LLC
121 North River Drive
Narragansett, RI=20 02882
401-284-1827

-----Original Message-----
From:=20 owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] = On=20 Behalf Of Sudarshan Honnudike
Sent: Wednesday, February 07,= 2007=20 6:38 AM
To: Lynne D. Green;=20 ibis-users@server.eda.org
Subject: [IBIS-Users] Rref and R_fixt= ure=20 clarifications


H= i Lynne=20 and all,

Actually I am ta= king one=20 of my previous question and I am asking this question also.=20

Sometime back lynne has mentione= d that,=20 Rref and Cref are for timing checks and R_fixture corresponds to= =20
loading conditions. And he also ment= ions that=20 one should not use reactive loads to measure V-t tables as it
= breaks some of the tool's algorithms.= =20

Now i have a specific case. &nbs= p;For IIC=20 we need to connect a load of 400 pF. Its a very slow cell. Its a IIC syst= em=20 requirement.
In the specifica= tion they=20 say, in a system there will be around 40 recievers connected to 1 driver= =20 through IIC bus. If you convert
the=20 distributed loading of these 40 Rcx to 1 lumped loading it comes around 4= 00=20 pF.

So do i need to conne= ct a=20 C_fixture of 400 pF load while generating V-t tables ? If not where this = load=20 should be specified and what load has to be used for generating V-t=20 tables?

Let me know your= =20 response.

Best=20 Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manya= ta=20 Tech Park, Nagawara
Bangalore-560 045 , India.  =20  
Ph:+91-80-40267073  
Fax: +91-80-4026=20 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com=20







"Lynne D. Green" <lgreen22@mindspring.com>

2007-01-10 04:33 PM

To=
"'Alex Hilbers'"=20 <alex.hilbers@asml.com>
"'Sudarshan Honnudike'"=20 <sudarshan.honnudike@nxp.com>
<ibis-users@eda.org= >=20
cc=
Subject
RE: [IBIS-Users] Informati= on on=20 Vref, Rref & Cref=20
Classification





I=20 was somewhat confused about the loading question and reply.

Rref a= nd=20 Cref are for timing checks, not for simulation.  The loading for
= V-t=20 tables is R_fixture.  So both are needed in a model.

One shou= ld=20 not use reactive loading in a V-t table.  This has been observed
= to=20 "break" the algorithm as implemented by some SI tools.

The underly= ing=20 algorithms have been published in two papers:
* The Development of Ana= log=20 SPICE Behavioral Model Based on IBIS Model
Ying Wang & Han Ngee Ta= n=20  
* Extraction of Transient Behavioral Model of Digital I/O Buffe= rs=20 from IBIS
P. Tehrani, Y. Chen & J. Fang

- Lynne=20


"IBIS training when you need it, where you need it."

D= r.=20 Lynne Green
Green Streak=20 Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen2= 2@mindspring.com


________________________________

 = =20               From:=20 owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf O= f=20 Alex Hilbers
                S= ent:=20 Wednesday, January 10, 2007 1:47 AM
         = =20       To: Sudarshan Honnudike; ibis-users@eda.org
 = ;=20               Subject: RE: [IBIS-Users= ]=20 Information on Vref, Rref & Cref
         = ;=20      
             = =20  
               =20 Sudarshan,
               =20  
                Interes= ting=20 question. I always wondered how a table based model
(V-I, ..), such as= an=20 IBIS model, could model any form of feedback control
system, as the IO= pad=20 you describe probably is. It seems that V-t waveforms,
together with a= =20 simulation tool specific algorithm, must do that job. You
verify this = by=20 comparing your simulation tool with actual SPICE results.
This is pron= e to=20 variation based on which tool you use, I donot think this
'algorithm' = is=20 standardised. To my knowledge XTK needs the curves
rising/falling, for= load=20 to VCC and GND (i.e. all 4), otherwise the V-t
tables are ignored. (So= me=20 vendors do provide only 1 or 2, which is useless).
Interesting is what= =20 happens if you define several load conditions (Rfixture
=3D 25, 50, 75= Ohms),=20 not to mention capacitive and inductive loading. What
will the simualt= ion=20 tool choose, will it interpolate, I donot have the
faintest idea. I gu= ess=20 it won't work within IBIS, which may be the reason
you do not get answ= ers.=20
                 
&nb= sp;=20               Maybe a good reason to= =20 provide SPICE models for this type of buffer.
Either under NDA or=20 encrypted. Level 50 HSPICE, i.e. Philips MOS Model 9,
should be fine.= =20
                 
&nb= sp;=20               Best regards,
 = =20              =20
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~
 =20               Alex Hilbers
 = =20               Signal Integrity Analysi= s and=20 Thermal Management, ASML, EDEV
department

     = =20           Building 7J0005, P.O. Box 324, 5500 AH= =20 Veldhoven, The Netherlands
            &= nbsp;=20   Phone: +31-(0)40-268 5587, Fax: +31-(0)40-268 5530
   = ;=20             Email: alex.hilbers@asml.com,= =20 www.asml.com <http://www.asml.com/>
       = =20        

          &n= bsp;=20                     &nb= sp;=20

________________________________

      &nbs= p;=20         From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On
Behalf Of Sudarshan=20 Honnudike
                Sent= :=20 Wednesday, January 10, 2007 6:35 AM
         = =20       To: ibis-users@eda.org
       = ;=20         Subject: [IBIS-Users] Information on Vref, Rr= ef=20 & Cref
               =20
               

 = ;=20               Hi ,
    &= nbsp;=20          
         = =20       If we have a IO pad which works in the different=20 applications
depending on the load applied
      &n= bsp;=20         on it, then do we to  provide V-t=20 waveforms(more than normal 4
curves) for different applications
&n= bsp;=20               with different load=20 settings.?
               =20
                Or can we spe= cify=20 that loading conditions under Rref, Vref and Cref
for that model. Whic= h one=20 is preferable. ?
              &nb= sp;=20
                I tested my m= odel=20 with Hyperlynx SI tool and it is not identifying
the Rref and Vref val= ues=20 that I am specifying
             = =20   in my model. It will only take Cref and Vmeas while=20 doing
simulations. In that case we can't specify the loading
 = ;=20               conditions under Vref, C= ref=20 and Vref but we need to give all
possible V-t curve combinations for= =20 different loading conditions.
          &nbs= p;=20    
               = =20 Please let me know your reply.
          &nb= sp;=20    
               = PS :=20 I am also waiting for the reply to my previous mail regarding
Common M= ode=20 Voltage Range support in IBIS .
          &n= bsp;=20    
               = Best=20 Regards,
               
&= nbsp;=20               Sudarshan HN
  &= nbsp;=20             NXP Semiconductors/CTO=20 /PLT
                C-4, Many= ata=20 Tech Park, Nagawara
              &= nbsp;=20 Bangalore-560 045 , India.    
        &= nbsp;=20       Ph:+91-80-40267073  
      &n= bsp;=20         Fax: +91-80-4026 7855
     = =20           seri:sudarsha@inpsblr
   = =20             E-mail:=20 sudarshan.honnudike@nxp.com
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believed to be clean. - ------=_NextPart_000_02A8_01C74A9D.75D01300-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 9 Feb 2007 17:43:58 +0100 From: Subject: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) This is a multi-part message in MIME format. - ------_=_NextPart_001_01C74C69.8021DD15 Content-Type: text/plain; charset="ISO-8859-2" Content-Transfer-Encoding: quoted-printable Hi experts, for long time I was hoping that I will never have to do it, but now, with D= DR4 (or NMT) knocking on the door it is finally on my schedule - IBIS model= s for differential I/O buffers. I have to say that I have read all possible documents (or at least I think = so) available on Internet (IBIS Summits, Macro Modeling Subcommittee, etc..= ), I have contacted a few people to discuss what they have actually done, I= have done the "homework" by experimenting with *-AMS Macro Library (one ye= ar later, but still), and so I would like here to share with you one summar= y on possibilities to create either IBIS models for differential buffers (w= / or w/o pre-/de-emphasis) or to create setups for simulation of these buff= er. Also, in this my "analysis", I would have some questions, so if somebod= y knows the answers, please just write me. Disclaimer: I am perfectly aware that there is a possibility that I have, perhaps, wro= te something wrong or stupid (I apologize in advance), but I am ready to ta= ke this risk, since I think that one of the purposes of this forum is discu= ssing all possible (IBIS related) topics. Also, if I have forgotten to ment= ion some work or author that is not done on purpose, but simply because of = my limited capabilities. Main question: I know that it is impossible to get one general answer on this (but still, = therefore I have done a whole analysis): What is mainstream solution/method= - what is the setup that are most customers looking for?=20 I am asking this simply, because I wouldn't like to support every possible = existing setup, but just to concentrate on one or two. In this summary, I have tried to list all kind of models/methods, starting = with (according to me) most simple and than slowly increasing complexity - = also I would like to distinguish between models of Differential buffers wit= hout Pre/De-emphasis and models of Differential buffers with Pre/De-emphasi= s. Differential Buffers w/o Pre/De-emphasis=20 1. "Traditional" IBIS modeling - treats differential buffers as two indepen= dent [Model]s driven by a stimulus and its complement=20 Method described (for example) by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf Advantages: - - simple setup and usage Disadvantages: - - not describing the coupling effects between pads - - causes DC shifts in the signal level 2. Method described by - - A. Tambone (Semiconductor Business News 2000) - no link found=20 - - http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z - - http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf - - http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf Advantages: - - relatively "smooth" and easy flow for understanding of IBIS extraction; - - relatively easy to adapt existing s2ibis2 or s2ibis3 flow; Disadvantages: - - LVDS IBIS models are accurate only when same VDDQ model was generated wit= h is used - Changing VDDQ leads to very inaccurate results; - - LVDS IBIS models assume constant Vcm - Must generate multiple models for = different values of vcm to obtain consistent accuracy driving different loa= ds and topologies; - - Device asymmetry will affect accuracy of model - Model generated for both= pads assumes perfect driver symmetry - Etch lengths of nets in differentia= l pair matched; 3. Improved IBIS modeling approach (using only v3.2 keywords) Method described by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf - - http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf Advantages: - - describes DC currents of a differential buffer completely and accurately - - DC levels of the signals are correct under all loading conditions Disadvantages: - - pretty complicated procedure for extraction of model (at least for me) - - relatively big effort needed to automate the procedure - - need to make some guesses for picking up the 'best" value for C_comp Questions: Q1: on Page 38 and Page 39, in section "4.6.3 Separating the On-die Termination= I-V Tables" of IBIS Modeling Cookbook (IBIS Open Forum) - above mentioned = http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf -is written: "The procedure for this is similar to the corresponding subtraction procedu= re used for single-ended drivers. The I-V characteristics of the driver must be obtained twice, once in the drivi= ng mode and once in the 3-stated (high impedance) mode, and the 3-stated I-V table data must be substracted from t= he driving I-V table data. The only added complexity in this procedure for differential drivers is that the sub= traction is done after the common mode I-V tables have been extracted from the raw I-V surface data." On what is exactly meant by "The only added complexity in this procedure for differential drivers is that the sub= traction is done after the common mode I-V tables have been extracted from the raw I-V surface data." . What is th= e difference comparing to procedures that are done with s2ibis2 or s2ibis3,= since there is well done substracting of 3-stated I-V tables from driving = I-V tables? Q2: is there some IBIS file available that is created with exactly this procedu= re? Can somebody send me such file? Q3: are there any public available tools (something like s2ibis2 or s2ibis3) th= at would support extraction of IBIS models described with this model? (Hereby I don't mean on HSpice, Matlab and Pearl scripts provided in http:/= /www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf) Differential Buffers w/ Pre/De-emphasis=20 1. "Traditional" IBIS modeling - Model the building blocks of the buffer wi= th independent [Model]s and tell the user to wire them up treats differential buffers as four independent [Model]s (2 Main, 2 boosts= ) driven by a stimulus and its complement=20 Disadvantage: - - This approach was used initially for many models but required manual edit= ing of files and/or simulation schematics 2. [Driver Shedule] Method for Pre-emphasis Buffer modeling=20 http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basically describe= s 2 methods: V-I Through Transient simulation and [Driver Shedule]) http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf Advantage (of V-I Through Transient simulation method): - - relatively simple method Disadvantage (of V-I Through Transient simulation method): - - Non-monotonic wave forms (For some EDA tools) - - Single clock frequency operation (Changing the frequency needs remodeling) Advantage (of [Driver Schedule] Method): - - Changing the frequency doesn't need remodeling - - Eliminates the need for connecting two separate [Model]s by hand in the - - Eliminates the need for manually connecting [Model]s to make a complete b= uffer schematics, one for the Main and one for the Boost portion of the buf= fer - - Fewer transistor level (SPICE) models will need to be released to custome= rs - - Uses no more than IBIS v3.2 syntax - - Useful for tools not supporting the *-AMS extensions of IBIS - Extends th= e life of legacy IBIS before requiring the IBIS v4.1 language extensions - - Reasonably good correlation with transistor level model Disadvantage (of [Driver Schedule] Method): - - Changing the frequency need changing of Rise_on, Rise_off, Fall_on and Fa= ll_off times. Since legacy IBIS does not have provisions for clocked buffer= s, this model doesn't have a clock input, consequently the delay parameter is "hard coded= " and will need to be changed manually in the IBIS file for every clock fre= quency and simulation corner - - The [Driver Schedule] delay parameters do not have typ., min., max. corne= rs Obtaining separate [Model] data for the Main and Boost buffers may still r= equire the editing of the SPICE netlist - - There are a few questions around proper handling of C_comp 3. IBIS modeling using v4.1 and v4.2 features (e.g. [External Circuit]) Advantage: - - flexibility (I guess so) Disadvantage: - - not all EDA tools support all features - - relatively complicated setup Question: Q4: - - can somebody send me an example of IBIS model that is using v4.1 and v4.2= features for describing Differential Buffers with Pre-/De-emphasis? 4. *-AMS Buffer Models Using IBIS v3.2 Data (although it can be applied on = Differential Buffers w/o Pre/De-emphasis as well) Method described by (and many others): http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf Advantage: - - according to my opinion absolutely the most "coolest" method (as mentione= d on the beginning, I have done the homework and really experimented with M= acro Model Library created by Arpad & Co. - please see my questions and com= ments bellow) for SI simulation - - very flexible method, gives you possibilities to do literally whatever yo= u want (the only limitation are your EDA tools - in my case HSpice 2006.09 = and it's Verilog-A interface) Disadvantage: - - "where" is IBIS here? (not really a disadvantage, but more like a questio= n) - - need to create IBIS models first and then to extract data in proper forma= t (later to be read-out by Verilog-A) - - relatively high effort to create a proper setup and flow - - one needs to know (or at least understand) all :IBIS, HSpice and *-AMS - = (at least in this case that wasn't my problem :-))) Questions: Q5: is there a possibility to make HSpice more verbose when debugging it's Veri= log-A interface?=20 In sum I spent around half 0of the day just on debugging why Verilog-A "won= 't" compile Verilog code when including extracted IBIS data.=20 Btw., please find in the attachment slightly changed Perl script (file nam= e: "ibis2ams.pl") with which one can REALLY do something used in conjunctio= n with for example http://www.vhdl.org/pub/ibis/macromodel_wip/template_lib= /Verilog-A_PreDe- - original script that is on http://www.vhdl.org/pub/ibis= /macromodel_wip/tools/IBIS-to-AMS_conversion_tool.zip can't be since origi= nal script generates array "Ipu_data", and pre/de-emphasis template (Verilo= g-A code) requires array named "I_pu" (and other similar discrepancies). U= ser just needs to change in the first row the path to his/her Perl executab= le. If IBIS model is generated with s2ibis2 user still needs to delete "S" = (from pS) from generated data file. Q6: practical question - it seems that Verilog-A doesn't support "NA" in input = array (e.g. "NA" in power or ground clamp data), although it is allowed in = IBIS. Is there intention to change this in Verilog-A standard? Or at least = how to handle "NA' in future? Q7: is it fair to say that calculation procedure (calculating/compensating of t= he I, V and C) used and described in "IBIS_macro_library.va" in module "IBI= S_IO" is expected to be used by all other simulators - I mean, is it "The A= lgorithm" (with some minor changes and vendor specialties) that every tool = that uses IBIS models should follow?=20 Many thanks to those that have read this mail until here, I am hoping on so= me your feedback! Best regards / Mit freundlichen Gr=FC=DFen / S po=B9tovanjem Radovan Vuleti=E6 Qimonda AG QAG PD PDE MEM MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 60088 1233 Fax (PC): +49 (0)89 60088 45 5305=20 E-mail: radovan.vuletic@qimonda.com <>=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C74C69.8021DD15 Content-Type: application/octet-stream; name="ibis2ams.pl" Content-Transfer-Encoding: base64 Content-Description: ibis2ams.pl Content-Disposition: attachment; filename="ibis2ams.pl" IyEgL29wdC9wZXJsLzUuNi4xL2Jpbi9wZXJsCiMKIyBQYXVsIEZlcm5hbmRv IE5DU1UsIElCSVMtTUFDUk8gMDEvMTcvMjAwNgojIHByZmVybmFuQG5jc3Uu ZWR1CiMKIyBJQklTLXRvLUFNUyBjb252ZXJ0ZXIgc2NyaXB0IHYwLjEgKEdV SSBjYXBhYmlsaXRpZXMgYWRkZWQpIC0gMS8zMC8wNgojIElCSVMtdG8tQU1T IGNvbnZlcnRlciBzY3JpcHQgdjAuMiAoVkhETC1BKE1TKSBwYXJzaW5nIGFk ZGVkKSAtIDIvMS8wNgojIElCSVMtdG8tQU1TIGNvbnZlcnRlciBzY3JpcHQg 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| subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 13 Feb 2007 11:26:15 +0530 From: Sudarshan Honnudike Subject: [IBIS-Users] Tolerant IO cell's Supply voltage range.? This is a multipart message in MIME format. - --=_alternative 0020546865257281_= Content-Type: text/plain; charset="US-ASCII" Hello All, I want to know what should be the voltage range for the tolerant cells for I-V curves like [Gnd Clamp], [Power Clamp], [Pull up] & [Pull down]. I read it from one of the presentation that, say for a 3.3 V functional 5 V tolerant cell the voltage range is from -5V to +10V. Do what curves this range applies ?. I dont think this range has to be applied for [Pull u] and [Pull down] curves as these are basically driver characteristics and maximum they can operate under 3.3V. So is it only for Clamp curves ? Please let me know your answers. Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=_alternative 0020546865257281_= Content-Type: text/html; charset="US-ASCII"
Hello All,

I want to know what should be the voltage range for the tolerant cells for I-V curves like [Gnd Clamp], [Power Clamp], [Pull up] & [Pull down].
I read it from one of the presentation that, say for a 3.3 V functional 5 V tolerant cell the voltage range is from -5V to +10V.  Do what curves
this range applies ?. I dont think this range has to be applied for [Pull u] and [Pull down] curves as these are basically driver characteristics
and maximum they can operate under 3.3V. So is it only for Clamp curves ?

Please let me know your answers.

Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com
--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --=_alternative 0020546865257281_=-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 14 Feb 2007 08:54:32 -0800 (PST) From: bhavneet aujla Subject: [IBIS-Users] Why is it necessary to take R_load/R_fixture, rather than taking only Capacitor(C_load) for V-T tables? - --0-2019749137-1171472072=:93807 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hello, For the realisation of V-T table/Ramp [Rising Waveforms and Falling Waveforms] at the output we require a Resistance [R_fixture/ R_load], but in CMOS, Capacitor acts as load so why it is'nt neccessary to take Capacitor at output for extraction of V-T. Since i know R-fixture specifies the impedance of the system transmission lines the buffer will drive, but still confused that, for CMOS load is capacitor, and finally output via transmission line has to drive CMOS (which is modeled as capacitor). Regards Bhavneet Singh Sub: Why is it necessary to take R_load/R_fixture, rather than taking only Capacitor(C_load) for V-T tables? - --------------------------------- Bored stiff? Loosen up... Download and play hundreds of games for free on Yahoo! Games. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --0-2019749137-1171472072=:93807 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit
Hello,
For the realisation of V-T table/Ramp [Rising Waveforms and Falling Waveforms] at the output we require a Resistance [R_fixture/ R_load], but in CMOS, Capacitor acts as load so why it is'nt neccessary to take Capacitor at output for extraction of V-T. Since i know R-fixture specifies the impedance of the system transmission lines the buffer will drive, but still confused that, for CMOS load is capacitor, and finally output via transmission line has to drive CMOS (which is modeled as capacitor).
Regards
Bhavneet Singh
Sub: Why is it necessary to take R_load/R_fixture, rather than taking only Capacitor(C_load) for V-T tables?

Bored stiff? Loosen up...
Download and play hundreds of games for free on Yahoo! Games.
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This message has been scanned for viruses and
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believed to be clean. - --0-2019749137-1171472072=:93807-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 14 Feb 2007 09:57:12 -0800 From: "Mirmak, Michael" Subject: [IBIS-Users] RE: Tolerant IO cell's Supply voltage range.? This is a multi-part message in MIME format. - ------_=_NextPart_001_01C75061.8D88F3E3 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Sudarshan, =20 You are indeed correct. For 5 V tolerant buffers, the clamp tables would cover a range based on a 5 V supply, to withstand any incoming high-voltage signals. The [Pullup] and/or [Pulldown] tables would cover a range based on the 3.3 V supply.=20=20 =20 - - Michael Mirmak Intel Corp. Chair, EIA BIS Open Forum ________________________________ From: Sudarshan Honnudike [mailto:sudarshan.honnudike@nxp.com]=20 Sent: Monday, February 12, 2007 21:56 To: ibis-users@server.eda.org; owner-ibis-users@server.eda.org Subject: Tolerant IO cell's Supply voltage range.? Hello All,=20 I want to know what should be the voltage range for the tolerant cells for I-V curves like [Gnd Clamp], [Power Clamp], [Pull up] & [Pull down]. I read it from one of the presentation that, say for a 3.3 V functional 5 V tolerant cell the voltage range is from -5V to +10V. Do what curves this range applies ?. I dont think this range has to be applied for [Pull u] and [Pull down] curves as these are basically driver characteristics=20 and maximum they can operate under 3.3V. So is it only for Clamp curves ?=20 Please let me know your answers.=20 Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India.=20=20=20=20 Ph:+91-80-40267073=20=20 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C75061.8D88F3E3 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Sudarshan,
 
You are indeed correct.  For 5 V tolerant buf= fers, the=20 clamp tables would cover a range based on a 5 V supply, to withstand any=20 incoming high-voltage signals.  The [Pullup] and/or [Pulldown] tables = would=20 cover a range based on the 3.3 V supply. 
 
- Michael Mirmak
  Intel Corp.
  Chair, EIA BIS Open Forum
From: Sudarshan Honnudike=20 [mailto:sudarshan.honnudike@nxp.com]
Sent: Monday, February 12, = 2007=20 21:56
To: ibis-users@server.eda.org;=20 owner-ibis-users@server.eda.org
Subject: Tolerant IO cell's Suppl= y=20 voltage range.?


Hello All,

<= FONT=20 face=3Dsans-serif size=3D2>I want to know what should be the voltage range = for the=20 tolerant cells for I-V curves like [Gnd Clamp], [Power Clamp], [Pull up] &a= mp;=20 [Pull down].
I read it from one= of the=20 presentation that, say for a 3.3 V functional 5 V tolerant cell the voltage= =20 range is from -5V to +10V.  Do what curves
this range applies ?. I = dont=20 think this range has to be applied for [Pull u] and [Pull down] curves as t= hese=20 are basically driver characteristics
and=20 maximum they can operate under 3.3V. So is it only for Clamp curves ?=20

Please let me know your answers.= =20

Best Regards,

Sudars= han=20 HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park,=20 Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073= =20  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail:=20 sudarshan.honnudike@nxp.com
--
This message has been scanned = for=20 viruses and
dangerous content by MailScanner, and is
be= lieved=20 to be clean.
--=20
This message has been scanned for viruses and
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believed to be clean. - ------_=_NextPart_001_01C75061.8D88F3E3-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 15 Feb 2007 13:33:58 -0800 From: "Lynne D. Green" Subject: re: [IBIS-Users] Why is it necessary to take R_load/R_fixture, rather than taking only Capacitor(C_load) for V-T tables? This is a multi-part message in MIME format. - ------=_NextPart_000_0004_01C75105.F2E097C0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit _____ From: Lynne D. Green [mailto:lgreen22@mindspring.com] Sent: Wednesday, February 14, 2007 12:33 PM To: 'bhavneet aujla' Subject: RE: [IBIS-Users] Why is it necessary to take R_load/R_fixture, rather than taking only Capacitor(C_load) for V-T tables? Hello, Bhavneet, Having worked on both ICs and PCBs, here is what I have learned of the history: PCBs are more sensitive to transmission line effects, because the traces are long compared to an edge delay. There is usually a reference plane (ground/power) in the stackup, making the resistor in IBIS is a good model for this transmission line. In addition, SI algorithms can have simulation problems if the V-t load is not resistive. The lumped Cload in CMOS modeling is used to generate "cell" timing tables. HOWEVER, above about 300 MHz, longer on-chip traces need to be modeled as LC circuits with capacitive coupling, rather than just a lumped Cload. Modeling traces as full transmission lines has been a hot topic for about five years; the challenge is modeling without a ground plane (the CMOS substrate being a highly-lossy plane). Hope this helps. Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com _____ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of bhavneet aujla Sent: Wednesday, February 14, 2007 8:55 AM To: ibis@eda-stds.org; ibis-users@eda.org Subject: [IBIS-Users] Why is it necessary to take R_load/R_fixture, rather than taking only Capacitor(C_load) for V-T tables? Hello, For the realisation of V-T table/Ramp [Rising Waveforms and Falling Waveforms] at the output we require a Resistance [R_fixture/ R_load], but in CMOS, Capacitor acts as load so why it is'nt neccessary to take Capacitor at output for extraction of V-T. Since i know R-fixture specifies the impedance of the system transmission lines the buffer will drive, but still confused that, for CMOS load is capacitor, and finally output via transmission line has to drive CMOS (which is modeled as capacitor). Regards Bhavneet Singh Sub: Why is it necessary to take R_load/R_fixture, rather than taking only Capacitor(C_load) for V-T tables? _____ - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0004_01C75105.F2E097C0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_0004_01C75105.F2E097C0-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #95 ************************
From: Lynne D. Green=20 [mailto:lgreen22@mindspring.com]
Sent: Wednesday, February 14,= 2007=20 12:33 PM
To: 'bhavneet aujla'
Subject: RE: [IBIS-User= s]=20 Why is it necessary to take R_load/R_fixture, rather than taking only=20 Capacitor(C_load) for V-T tables?

Hello, Bhavneet,
 
Having worked on both ICs and PCBs, here is what= I have=20 learned of the history:
 
PCBs are more sensitive to transmission line eff= ects,=20 because the traces are long compared to an edge delay.  There is usu= ally=20 a reference plane (ground/power) in the stackup, making the resistor in I= BIS=20 is a good model for this transmission line.  In addition, SI algorit= hms=20 can have simulation problems if the V-t load is not=20 resistive.
 
The lumped Cload in CMOS modeling is used t= o=20 generate "cell" timing tables.  HOWEVER, above ab= out=20 300 MHz, longer on-chip traces need to be modeled as LC circuits with=20 capacitive coupling, rather than just a lumped Cload.  Modeling= =20 traces as full transmission lines has been a hot topic for about fiv= e=20 years; the challenge is modeling without a ground plane (the CMOS substra= te=20 being a highly-lossy plane).
 
Hope this helps.
 
Lynne
 
 
"IBIS training when you need it, where you need= =20 it."
 
Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprogram= s.com
425-788-0412
lgreen22@mindspring.com
 
 
 
 

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of bhavneet=20 aujla
Sent: Wednesday, February 14, 2007 8:55 AM
To:=20 ibis@eda-stds.org; ibis-users@eda.org
Subject: [IBIS-Users] W= hy is=20 it necessary to take R_load/R_fixture, rather than taking only=20 Capacitor(C_load) for V-T tables?

Hello,
For the realisation of V-T table/Ramp [Rising Waveforms and Fallin= g=20 Waveforms] at the output we require a Resistance [R_fixture/ R_load], b= ut in=20 CMOS, Capacitor acts as load so why it is'nt neccessary to take Capacit= or at=20 output for extraction of V-T. Since i know R-fixture specifies the impe= dance=20 of the system transmission lines the buffer will drive, but still confu= sed=20 that, for CMOS load is capacitor, and finally output via transmission l= ine=20 has to drive CMOS (which is modeled as capacitor).
Regards
Bhavneet Singh
Sub: Why is it necessary to take R_load/R_fixture, rather than tak= ing=20 only Capacitor(C_load) for V-T tables?