From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #100 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Monday, June 25 2007 Volume 01 : Number 100 ---------------------------------------------------------------------- Date: Thu, 31 May 2007 13:00:05 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Radovan, On your request (in a private mail) I am going attempt to answer your questions. Please find my responses between your lines preceded by "AM:". Sorry for the delay... Arpad ==================================================== - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, February 09, 2007 8:44 AM To: ibis-users@server.eda.org Subject: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi experts, for long time I was hoping that I will never have to do it, but now, with DDR4 (or NMT) knocking on the door it is finally on my schedule - IBIS models for differential I/O buffers. AM: Welcome to the club... :-) I have to say that I have read all possible documents (or at least I think so) available on Internet (IBIS Summits, Macro Modeling Subcommittee, etc..), I have contacted a few people to discuss what they have actually done, I have done the "homework" by experimenting with *-AMS Macro Library (one year later, but still), and so I would like here to share with you one summary on possibilities to create either IBIS models for differential buffers (w/ or w/o pre-/de-emphasis) or to create setups for simulation of these buffer. Also, in this my "analysis", I would have some questions, so if somebody knows the answers, please just write me. AM: Thanks for doing your homework, you seem to have done a good job! Disclaimer: I am perfectly aware that there is a possibility that I have, perhaps, wrote something wrong or stupid (I apologize in advance), but I am ready to take this risk, since I think that one of the purposes of this forum is discussing all possible (IBIS related) topics. Also, if I have forgotten to mention some work or author that is not done on purpose, but simply because of my limited capabilities. Main question: I know that it is impossible to get one general answer on this (but still, therefore I have done a whole analysis): What is mainstream solution/method - what is the setup that are most customers looking for? I am asking this simply, because I wouldn't like to support every possible existing setup, but just to concentrate on one or two. AM: Can't answer this question, because I am not working on DDR simulations directly. In this summary, I have tried to list all kind of models/methods, starting with (according to me) most simple and than slowly increasing complexity - also I would like to distinguish between models of Differential buffers without Pre/De-emphasis and models of Differential buffers with Pre/De-emphasis. Differential Buffers w/o Pre/De-emphasis 1. "Traditional" IBIS modeling - treats differential buffers as two independent [Model]s driven by a stimulus and its complement Method described (for example) by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf Advantages: - - simple setup and usage Disadvantages: - - not describing the coupling effects between pads - - causes DC shifts in the signal level AM: This cannot be stated in general, because there are cases when this approach works perfectly fine. See my presentation at: http://www.vhdl.org/pub/ibis/summits/feb04a/muranyi1.pdf 2. Method described by - - A. Tambone (Semiconductor Business News 2000) - no link found - - http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z - - http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf - - http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf Advantages: - - relatively "smooth" and easy flow for understanding of IBIS extraction; - - relatively easy to adapt existing s2ibis2 or s2ibis3 flow; Disadvantages: - - LVDS IBIS models are accurate only when same VDDQ model was generated with is used - Changing VDDQ leads to very inaccurate results; - - LVDS IBIS models assume constant Vcm - Must generate multiple models for different values of vcm to obtain consistent accuracy driving different loads and topologies; - - Device asymmetry will affect accuracy of model - Model generated for both pads assumes perfect driver symmetry - Etch lengths of nets in differential pair matched; 3. Improved IBIS modeling approach (using only v3.2 keywords) Method described by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf - - http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf Advantages: - - describes DC currents of a differential buffer completely and accurately - - DC levels of the signals are correct under all loading conditions Disadvantages: - - pretty complicated procedure for extraction of model (at least for me) - - relatively big effort needed to automate the procedure - - need to make some guesses for picking up the 'best" value for C_comp AM: While it is true that this is more complicated, but once you have your scripts written it should be almost just a "pushbutton" solution. Making regular IV and Vt curves seemed just as hard before the various SPICE-to-IBIS tools came along... AM: Also, picking the best C_comp value is not a specific problem for differential buffers or the above technique, it is a general problem for any buffer model, even regular single ended buffers... Questions: Q1: on Page 38 and Page 39, in section "4.6.3 Separating the On-die Termination I-V Tables" of IBIS Modeling Cookbook (IBIS Open Forum) - above mentioned http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf - -is written: "The procedure for this is similar to the corresponding subtraction procedure used for single-ended drivers. The I-V characteristics of the driver must be obtained twice, once in the driving mode and once in the 3-stated (high impedance) mode, and the 3-stated I-V table data must be substracted from the driving I-V table data. The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." On what is exactly meant by "The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." . What is the difference comparing to procedures that are done with s2ibis2 or s2ibis3, since there is well done substracting of 3-stated I-V tables from driving I-V tables? AM: The traditional subtraction in the IBIS world refers to subtracting the clamp IV curves from the driving IV curves, so that the pullup and pulldown tables would contain only the drive currents. The addition subtraction described in the quoted text refers to separating the pad-to-pad, differential current from the total pad current, so that the pullup and pulldown tables would not include any differential currents (nor should they include any clamping currents, but that is taken care of doing the two measurements, driven and 3-stated). So the added complexity comes from needing to separate the differential current from the total current that is measured at the pad. Q2: is there some IBIS file available that is created with exactly this procedure? Can somebody send me such file? AM: I did generate a few IBIS files for differential buffers this way, but not too many, and honestly I don't know where they are, or whether they are available publicly... Q3: are there any public available tools (something like s2ibis2 or s2ibis3) that would support extraction of IBIS models described with this model? (Hereby I don't mean on HSpice, Matlab and Pearl scripts provided in http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf) AM: Not that I know of. However, if this technique seems to be widely used, I am sure we could talk with the NCU people and ask them to code it up in the s2ibis tool. Differential Buffers w/ Pre/De-emphasis 1. "Traditional" IBIS modeling - Model the building blocks of the buffer with independent [Model]s and tell the user to wire them up treats differential buffers as four independent [Model]s (2 Main, 2 boosts) driven by a stimulus and its complement Disadvantage: - - This approach was used initially for many models but required manual editing of files and/or simulation schematics 2. [Driver Shedule] Method for Pre-emphasis Buffer modeling http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basically describes 2 methods: V-I Through Transient simulation and [Driver Shedule]) http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf Advantage (of V-I Through Transient simulation method): - - relatively simple method Disadvantage (of V-I Through Transient simulation method): - - Non-monotonic wave forms (For some EDA tools) - - Single clock frequency operation (Changing the frequency needs remodeling) Advantage (of [Driver Schedule] Method): - - Changing the frequency doesn't need remodeling - - Eliminates the need for connecting two separate [Model]s by hand in the - - Eliminates the need for manually connecting [Model]s to make a complete buffer schematics, one for the Main and one for the Boost portion of the buffer - - Fewer transistor level (SPICE) models will need to be released to customers - - Uses no more than IBIS v3.2 syntax - - Useful for tools not supporting the *-AMS extensions of IBIS - Extends the life of legacy IBIS before requiring the IBIS v4.1 language extensions - - Reasonably good correlation with transistor level model Disadvantage (of [Driver Schedule] Method): - - Changing the frequency need changing of Rise_on, Rise_off, Fall_on and Fall_off times. Since legacy IBIS does not have provisions for clocked buffers, this model doesn't have a clock input, consequently the delay parameter is "hard coded" and will need to be changed manually in the IBIS file for every clock frequency and simulation corner - - The [Driver Schedule] delay parameters do not have typ., min., max. corners Obtaining separate [Model] data for the Main and Boost buffers may still require the editing of the SPICE netlist - - There are a few questions around proper handling of C_comp 3. IBIS modeling using v4.1 and v4.2 features (e.g. [External Circuit]) Advantage: - - flexibility (I guess so) Disadvantage: - - not all EDA tools support all features - - relatively complicated setup Question: Q4: - - can somebody send me an example of IBIS model that is using v4.1 and v4.2 features for describing Differential Buffers with Pre-/De-emphasis? 4. *-AMS Buffer Models Using IBIS v3.2 Data (although it can be applied on Differential Buffers w/o Pre/De-emphasis as well) Method described by (and many others): http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf AM: I would not recommend any of these methods in light of a better solution described in my presentation: http://www.vhdl.org/pub/ibis/summits/mar05/muranyi.pdf Advantage: - - according to my opinion absolutely the most "coolest" method (as mentioned on the beginning, I have done the homework and really experimented with Macro Model Library created by Arpad & Co. - please see my questions and comments bellow) for SI simulation - - very flexible method, gives you possibilities to do literally whatever you want (the only limitation are your EDA tools - in my case HSpice 2006.09 and it's Verilog-A interface) AM: Please use the latest version whenever possible, since Synopsys is fixing bugs all the time and add new features for more complete IBIS support. Disadvantage: - - "where" is IBIS here? (not really a disadvantage, but more like a question) AM: IBIS is more like wrapper in this case, contains the pin list, package info, and can pass parameters into the *-AMS models, which can still be useful. - - need to create IBIS models first and then to extract data in proper format (later to be read-out by Verilog-A) - - relatively high effort to create a proper setup and flow - - one needs to know (or at least understand) all :IBIS, HSpice and *-AMS - - (at least in this case that wasn't my problem :-))) AM: This is the model maker's problem. Model users do not have to know that much... Questions: Q5: is there a possibility to make HSpice more verbose when debugging it's Verilog-A interface? AM: Ask Synopsys about that... In sum I spent around half of the day just on debugging why Verilog-A "won't" compile Verilog code when including extracted IBIS data. AM: Ask Synopsys about that... Btw., please find in the attachment slightly changed Perl script (file name: "ibis2ams.pl") with which one can REALLY do something used in conjunction with for example http://www.vhdl.org/pub/ibis/macromodel_wip/template_lib/Verilog-A_PreDe - - - original script that is on http://www.vhdl.org/pub/ibis/macromodel_wip/tools/IBIS-to-AMS_conversion _tool.zip can't be since original script generates array "Ipu_data", and pre/de-emphasis template (Verilog-A code) requires array named "I_pu" (and other similar discrepancies). User just needs to change in the first row the path to his/her Perl executable. If IBIS model is generated with s2ibis2 user still needs to delete "S" (from pS) from generated data file. AM: To be honest, the Macro Modeling Library effort is not 100% finished. I am aware of the discrepancy you mention in the Perl script, and I thought we fixed it, but it may not have been uploaded to the web site yet. There are some other minor things that we need to fix and polish up in the library, such as the comments describing the various functions, etc... It kind of got pushed on the side when we started to work on the algorithmic modeling proposal in the IBIS-ATM subcommittee. So far I didn't get any requests about the Macro Modeling Library, and it seemed that it was not being used by anyone. If there is a need, we can certainly put it on a higher priority, just let me know. Q6: practical question - it seems that Verilog-A doesn't support "NA" in input array (e.g. "NA" in power or ground clamp data), although it is allowed in IBIS. Is there intention to change this in Verilog-A standard? Or at least how to handle "NA' in future? AM: You observation is correct. The Verilog-AMS (and also the VHDL-AMS) workgroup are currently discussing proposals to improve the $table_model keyword (and add a similar one to VHDL-AMS). Someone would have to bring this request to the workgroups. Although I wonder, since we are generating these tables with Perl scripts, is there a real need for this? The Perl script could very well take care of it. Q7: is it fair to say that calculation procedure (calculating/compensating of the I, V and C) used and described in "IBIS_macro_library.va" in module "IBIS_IO" is expected to be used by all other simulators - I mean, is it "The Algorithm" (with some minor changes and vendor specialties) that every tool that uses IBIS models should follow? AM: As far as I know, all simulator vendors who have IBIS support have implemented this "C_comp compensation" algorithm. The output waveform at the pad of an IBIS model must be the same as the Vt curve in that model, regardless of what the C_comp value is. This couldn't be done without the compensation algorithm. Many thanks to those that have read this mail until here, I am hoping on some your feedback! Best regards / Mit freundlichen Gru?en / S postovanjem Radovan Vuletic Qimonda AG QAG PD PDE MEM MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 60088 1233 Fax (PC): +49 (0)89 60088 45 5305 E-mail: radovan.vuletic@qimonda.com <> - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 1 Jun 2007 08:56:16 +0200 From: Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi Arpad, many thanks on your comments! Just one thing about Q6 and "NA" (specially in power and ground clamps). You have right, Perl script could take care of it, but for example in this case: [GND Clamp] ... ... 0.1500 -1.3479pA -1.3981pA -1.5422pA 0.2000 -0.5872pA -0.6494pA -0.7990pA 0.2392 0.0A NA NA 0.2408 NA 0.0A NA 0.2500 NA NA -47.2574fA 0.2532 NA NA 0.0A 3.0000 0.0A 0.0A 0.0A I agree, all "NA" in typ column and last 2 "NA" in min column could be replaced by 0.0A (already during table generation, not with Pearl script), but first "NA" in min column and all "NA" in max column can't be replaced with 0.0A, but for example, with some linear interpolation. Problem is that above table is extracted with "s2ibis like" tool (I agree, not very perfect tool) that puts "NA" when rearranging clamp tables (to avoid double counting) and we would need to make people aware they in their clamp tables they shouldn't have any "NA" but either 0.0A or interpolated values. Meaning, people would really need to take care about it in their extracting scripts. Regards, Radovan ============================================================================== Qimonda AG Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fischl Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J. Seifert Register Court/ Registergericht: München HRB 152545, Seat/ Sitz: München ============================================================================== - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Muranyi, Arpad Sent: Thursday, May 31, 2007 10:00 PM To: ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Radovan, On your request (in a private mail) I am going attempt to answer your questions. Please find my responses between your lines preceded by "AM:". Sorry for the delay... Arpad ==================================================== - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, February 09, 2007 8:44 AM To: ibis-users@server.eda.org Subject: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi experts, for long time I was hoping that I will never have to do it, but now, with DDR4 (or NMT) knocking on the door it is finally on my schedule - IBIS models for differential I/O buffers. AM: Welcome to the club... :-) I have to say that I have read all possible documents (or at least I think so) available on Internet (IBIS Summits, Macro Modeling Subcommittee, etc..), I have contacted a few people to discuss what they have actually done, I have done the "homework" by experimenting with *-AMS Macro Library (one year later, but still), and so I would like here to share with you one summary on possibilities to create either IBIS models for differential buffers (w/ or w/o pre-/de-emphasis) or to create setups for simulation of these buffer. Also, in this my "analysis", I would have some questions, so if somebody knows the answers, please just write me. AM: Thanks for doing your homework, you seem to have done a good job! Disclaimer: I am perfectly aware that there is a possibility that I have, perhaps, wrote something wrong or stupid (I apologize in advance), but I am ready to take this risk, since I think that one of the purposes of this forum is discussing all possible (IBIS related) topics. Also, if I have forgotten to mention some work or author that is not done on purpose, but simply because of my limited capabilities. Main question: I know that it is impossible to get one general answer on this (but still, therefore I have done a whole analysis): What is mainstream solution/method - what is the setup that are most customers looking for? I am asking this simply, because I wouldn't like to support every possible existing setup, but just to concentrate on one or two. AM: Can't answer this question, because I am not working on DDR simulations directly. In this summary, I have tried to list all kind of models/methods, starting with (according to me) most simple and than slowly increasing complexity - also I would like to distinguish between models of Differential buffers without Pre/De-emphasis and models of Differential buffers with Pre/De-emphasis. Differential Buffers w/o Pre/De-emphasis 1. "Traditional" IBIS modeling - treats differential buffers as two independent [Model]s driven by a stimulus and its complement Method described (for example) by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf Advantages: - - simple setup and usage Disadvantages: - - not describing the coupling effects between pads - - causes DC shifts in the signal level AM: This cannot be stated in general, because there are cases when this approach works perfectly fine. See my presentation at: http://www.vhdl.org/pub/ibis/summits/feb04a/muranyi1.pdf 2. Method described by - - A. Tambone (Semiconductor Business News 2000) - no link found - - http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z - - http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf - - http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf Advantages: - - relatively "smooth" and easy flow for understanding of IBIS extraction; - - relatively easy to adapt existing s2ibis2 or s2ibis3 flow; Disadvantages: - - LVDS IBIS models are accurate only when same VDDQ model was generated with is used - Changing VDDQ leads to very inaccurate results; - - LVDS IBIS models assume constant Vcm - Must generate multiple models for different values of vcm to obtain consistent accuracy driving different loads and topologies; - - Device asymmetry will affect accuracy of model - Model generated for both pads assumes perfect driver symmetry - Etch lengths of nets in differential pair matched; 3. Improved IBIS modeling approach (using only v3.2 keywords) Method described by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf - - http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf Advantages: - - describes DC currents of a differential buffer completely and accurately - - DC levels of the signals are correct under all loading conditions Disadvantages: - - pretty complicated procedure for extraction of model (at least for me) - - relatively big effort needed to automate the procedure - - need to make some guesses for picking up the 'best" value for C_comp AM: While it is true that this is more complicated, but once you have your scripts written it should be almost just a "pushbutton" solution. Making regular IV and Vt curves seemed just as hard before the various SPICE-to-IBIS tools came along... AM: Also, picking the best C_comp value is not a specific problem for differential buffers or the above technique, it is a general problem for any buffer model, even regular single ended buffers... Questions: Q1: on Page 38 and Page 39, in section "4.6.3 Separating the On-die Termination I-V Tables" of IBIS Modeling Cookbook (IBIS Open Forum) - above mentioned http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf - -is written: "The procedure for this is similar to the corresponding subtraction procedure used for single-ended drivers. The I-V characteristics of the driver must be obtained twice, once in the driving mode and once in the 3-stated (high impedance) mode, and the 3-stated I-V table data must be substracted from the driving I-V table data. The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." On what is exactly meant by "The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." . What is the difference comparing to procedures that are done with s2ibis2 or s2ibis3, since there is well done substracting of 3-stated I-V tables from driving I-V tables? AM: The traditional subtraction in the IBIS world refers to subtracting the clamp IV curves from the driving IV curves, so that the pullup and pulldown tables would contain only the drive currents. The addition subtraction described in the quoted text refers to separating the pad-to-pad, differential current from the total pad current, so that the pullup and pulldown tables would not include any differential currents (nor should they include any clamping currents, but that is taken care of doing the two measurements, driven and 3-stated). So the added complexity comes from needing to separate the differential current from the total current that is measured at the pad. Q2: is there some IBIS file available that is created with exactly this procedure? Can somebody send me such file? AM: I did generate a few IBIS files for differential buffers this way, but not too many, and honestly I don't know where they are, or whether they are available publicly... Q3: are there any public available tools (something like s2ibis2 or s2ibis3) that would support extraction of IBIS models described with this model? (Hereby I don't mean on HSpice, Matlab and Pearl scripts provided in http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf) AM: Not that I know of. However, if this technique seems to be widely used, I am sure we could talk with the NCU people and ask them to code it up in the s2ibis tool. Differential Buffers w/ Pre/De-emphasis 1. "Traditional" IBIS modeling - Model the building blocks of the buffer with independent [Model]s and tell the user to wire them up treats differential buffers as four independent [Model]s (2 Main, 2 boosts) driven by a stimulus and its complement Disadvantage: - - This approach was used initially for many models but required manual editing of files and/or simulation schematics 2. [Driver Shedule] Method for Pre-emphasis Buffer modeling http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basically describes 2 methods: V-I Through Transient simulation and [Driver Shedule]) http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf Advantage (of V-I Through Transient simulation method): - - relatively simple method Disadvantage (of V-I Through Transient simulation method): - - Non-monotonic wave forms (For some EDA tools) - - Single clock frequency operation (Changing the frequency needs remodeling) Advantage (of [Driver Schedule] Method): - - Changing the frequency doesn't need remodeling - - Eliminates the need for connecting two separate [Model]s by hand in the - - Eliminates the need for manually connecting [Model]s to make a complete buffer schematics, one for the Main and one for the Boost portion of the buffer - - Fewer transistor level (SPICE) models will need to be released to customers - - Uses no more than IBIS v3.2 syntax - - Useful for tools not supporting the *-AMS extensions of IBIS - Extends the life of legacy IBIS before requiring the IBIS v4.1 language extensions - - Reasonably good correlation with transistor level model Disadvantage (of [Driver Schedule] Method): - - Changing the frequency need changing of Rise_on, Rise_off, Fall_on and Fall_off times. Since legacy IBIS does not have provisions for clocked buffers, this model doesn't have a clock input, consequently the delay parameter is "hard coded" and will need to be changed manually in the IBIS file for every clock frequency and simulation corner - - The [Driver Schedule] delay parameters do not have typ., min., max. corners Obtaining separate [Model] data for the Main and Boost buffers may still require the editing of the SPICE netlist - - There are a few questions around proper handling of C_comp 3. IBIS modeling using v4.1 and v4.2 features (e.g. [External Circuit]) Advantage: - - flexibility (I guess so) Disadvantage: - - not all EDA tools support all features - - relatively complicated setup Question: Q4: - - can somebody send me an example of IBIS model that is using v4.1 and v4.2 features for describing Differential Buffers with Pre-/De-emphasis? 4. *-AMS Buffer Models Using IBIS v3.2 Data (although it can be applied on Differential Buffers w/o Pre/De-emphasis as well) Method described by (and many others): http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf AM: I would not recommend any of these methods in light of a better solution described in my presentation: http://www.vhdl.org/pub/ibis/summits/mar05/muranyi.pdf Advantage: - - according to my opinion absolutely the most "coolest" method (as mentioned on the beginning, I have done the homework and really experimented with Macro Model Library created by Arpad & Co. - please see my questions and comments bellow) for SI simulation - - very flexible method, gives you possibilities to do literally whatever you want (the only limitation are your EDA tools - in my case HSpice 2006.09 and it's Verilog-A interface) AM: Please use the latest version whenever possible, since Synopsys is fixing bugs all the time and add new features for more complete IBIS support. Disadvantage: - - "where" is IBIS here? (not really a disadvantage, but more like a question) AM: IBIS is more like wrapper in this case, contains the pin list, package info, and can pass parameters into the *-AMS models, which can still be useful. - - need to create IBIS models first and then to extract data in proper format (later to be read-out by Verilog-A) - - relatively high effort to create a proper setup and flow - - one needs to know (or at least understand) all :IBIS, HSpice and *-AMS - - (at least in this case that wasn't my problem :-))) AM: This is the model maker's problem. Model users do not have to know that much... Questions: Q5: is there a possibility to make HSpice more verbose when debugging it's Verilog-A interface? AM: Ask Synopsys about that... In sum I spent around half of the day just on debugging why Verilog-A "won't" compile Verilog code when including extracted IBIS data. AM: Ask Synopsys about that... Btw., please find in the attachment slightly changed Perl script (file name: "ibis2ams.pl") with which one can REALLY do something used in conjunction with for example http://www.vhdl.org/pub/ibis/macromodel_wip/template_lib/Verilog-A_PreDe - - - original script that is on http://www.vhdl.org/pub/ibis/macromodel_wip/tools/IBIS-to-AMS_conversion _tool.zip can't be since original script generates array "Ipu_data", and pre/de-emphasis template (Verilog-A code) requires array named "I_pu" (and other similar discrepancies). User just needs to change in the first row the path to his/her Perl executable. If IBIS model is generated with s2ibis2 user still needs to delete "S" (from pS) from generated data file. AM: To be honest, the Macro Modeling Library effort is not 100% finished. I am aware of the discrepancy you mention in the Perl script, and I thought we fixed it, but it may not have been uploaded to the web site yet. There are some other minor things that we need to fix and polish up in the library, such as the comments describing the various functions, etc... It kind of got pushed on the side when we started to work on the algorithmic modeling proposal in the IBIS-ATM subcommittee. So far I didn't get any requests about the Macro Modeling Library, and it seemed that it was not being used by anyone. If there is a need, we can certainly put it on a higher priority, just let me know. Q6: practical question - it seems that Verilog-A doesn't support "NA" in input array (e.g. "NA" in power or ground clamp data), although it is allowed in IBIS. Is there intention to change this in Verilog-A standard? Or at least how to handle "NA' in future? AM: You observation is correct. The Verilog-AMS (and also the VHDL-AMS) workgroup are currently discussing proposals to improve the $table_model keyword (and add a similar one to VHDL-AMS). Someone would have to bring this request to the workgroups. Although I wonder, since we are generating these tables with Perl scripts, is there a real need for this? The Perl script could very well take care of it. Q7: is it fair to say that calculation procedure (calculating/compensating of the I, V and C) used and described in "IBIS_macro_library.va" in module "IBIS_IO" is expected to be used by all other simulators - I mean, is it "The Algorithm" (with some minor changes and vendor specialties) that every tool that uses IBIS models should follow? AM: As far as I know, all simulator vendors who have IBIS support have implemented this "C_comp compensation" algorithm. The output waveform at the pad of an IBIS model must be the same as the Vt curve in that model, regardless of what the C_comp value is. This couldn't be done without the compensation algorithm. Many thanks to those that have read this mail until here, I am hoping on some your feedback! Best regards / Mit freundlichen Gru?en / S postovanjem Radovan Vuletic Qimonda AG QAG PD PDE MEM MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 60088 1233 Fax (PC): +49 (0)89 60088 45 5305 E-mail: radovan.vuletic@qimonda.com <> - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 1 Jun 2007 16:09:09 +0200 From: Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi Lance, in this case we were discussing what is Verilog-A doing with "NA" (after extracting of IBIS model tables with Pearl script to look-up tables) - please see below. I agree for other IBIS simulators, but problem is that in Verilog-A you can't have NA in look-up tables - code won't be even compiled. Regards, Radovan ============================================================================== Qimonda AG Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fischl Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J. Seifert Register Court/ Registergericht: München HRB 152545, Seat/ Sitz: München ============================================================================== - -----Original Message----- From: Lance Wang [mailto:lwang@iometh.com] Sent: Friday, June 01, 2007 3:54 PM To: Vuletic Radovan (QAG PD PDE MEM); arpad.muranyi@intel.com; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Radovan, Almost all the IBIS simulators will interpolate/extrapolate for the NAs in the IBIS curves. It should not be any problem if you leave NAs in IBIS. Regards, Lance Wang IO Methodology Inc. 978-764-2298 lwang@iometh.com - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, June 01, 2007 2:56 AM To: arpad.muranyi@intel.com; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi Arpad, many thanks on your comments! Just one thing about Q6 and "NA" (specially in power and ground clamps). You have right, Perl script could take care of it, but for example in this case: [GND Clamp] ... ... 0.1500 -1.3479pA -1.3981pA -1.5422pA 0.2000 -0.5872pA -0.6494pA -0.7990pA 0.2392 0.0A NA NA 0.2408 NA 0.0A NA 0.2500 NA NA -47.2574fA 0.2532 NA NA 0.0A 3.0000 0.0A 0.0A 0.0A I agree, all "NA" in typ column and last 2 "NA" in min column could be replaced by 0.0A (already during table generation, not with Pearl script), but first "NA" in min column and all "NA" in max column can't be replaced with 0.0A, but for example, with some linear interpolation. Problem is that above table is extracted with "s2ibis like" tool (I agree, not very perfect tool) that puts "NA" when rearranging clamp tables (to avoid double counting) and we would need to make people aware they in their clamp tables they shouldn't have any "NA" but either 0.0A or interpolated values. Meaning, people would really need to take care about it in their extracting scripts. Regards, Radovan ============================================================================ == Qimonda AG Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fischl Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J. Seifert Register Court/ Registergericht: München HRB 152545, Seat/ Sitz: München ============================================================================ == - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Muranyi, Arpad Sent: Thursday, May 31, 2007 10:00 PM To: ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Radovan, On your request (in a private mail) I am going attempt to answer your questions. Please find my responses between your lines preceded by "AM:". Sorry for the delay... Arpad ==================================================== - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, February 09, 2007 8:44 AM To: ibis-users@server.eda.org Subject: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi experts, for long time I was hoping that I will never have to do it, but now, with DDR4 (or NMT) knocking on the door it is finally on my schedule - IBIS models for differential I/O buffers. AM: Welcome to the club... :-) I have to say that I have read all possible documents (or at least I think so) available on Internet (IBIS Summits, Macro Modeling Subcommittee, etc..), I have contacted a few people to discuss what they have actually done, I have done the "homework" by experimenting with *-AMS Macro Library (one year later, but still), and so I would like here to share with you one summary on possibilities to create either IBIS models for differential buffers (w/ or w/o pre-/de-emphasis) or to create setups for simulation of these buffer. Also, in this my "analysis", I would have some questions, so if somebody knows the answers, please just write me. AM: Thanks for doing your homework, you seem to have done a good job! Disclaimer: I am perfectly aware that there is a possibility that I have, perhaps, wrote something wrong or stupid (I apologize in advance), but I am ready to take this risk, since I think that one of the purposes of this forum is discussing all possible (IBIS related) topics. Also, if I have forgotten to mention some work or author that is not done on purpose, but simply because of my limited capabilities. Main question: I know that it is impossible to get one general answer on this (but still, therefore I have done a whole analysis): What is mainstream solution/method - - what is the setup that are most customers looking for? I am asking this simply, because I wouldn't like to support every possible existing setup, but just to concentrate on one or two. AM: Can't answer this question, because I am not working on DDR simulations directly. In this summary, I have tried to list all kind of models/methods, starting with (according to me) most simple and than slowly increasing complexity - also I would like to distinguish between models of Differential buffers without Pre/De-emphasis and models of Differential buffers with Pre/De-emphasis. Differential Buffers w/o Pre/De-emphasis 1. "Traditional" IBIS modeling - treats differential buffers as two independent [Model]s driven by a stimulus and its complement Method described (for example) by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf Advantages: - - simple setup and usage Disadvantages: - - not describing the coupling effects between pads - - causes DC shifts in the signal level AM: This cannot be stated in general, because there are cases when this approach works perfectly fine. See my presentation at: http://www.vhdl.org/pub/ibis/summits/feb04a/muranyi1.pdf 2. Method described by - - A. Tambone (Semiconductor Business News 2000) - no link found - - http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z - - http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf - - http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf Advantages: - - relatively "smooth" and easy flow for understanding of IBIS extraction; - - relatively easy to adapt existing s2ibis2 or s2ibis3 flow; Disadvantages: - - LVDS IBIS models are accurate only when same VDDQ model was generated with is used - Changing VDDQ leads to very inaccurate results; - - LVDS IBIS models assume constant Vcm - Must generate multiple models for different values of vcm to obtain consistent accuracy driving different loads and topologies; - - Device asymmetry will affect accuracy of model - Model generated for both pads assumes perfect driver symmetry - Etch lengths of nets in differential pair matched; 3. Improved IBIS modeling approach (using only v3.2 keywords) Method described by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf - - http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf Advantages: - - describes DC currents of a differential buffer completely and accurately - - DC levels of the signals are correct under all loading conditions Disadvantages: - - pretty complicated procedure for extraction of model (at least for me) - - relatively big effort needed to automate the procedure - - need to make some guesses for picking up the 'best" value for C_comp AM: While it is true that this is more complicated, but once you have your scripts written it should be almost just a "pushbutton" solution. Making regular IV and Vt curves seemed just as hard before the various SPICE-to-IBIS tools came along... AM: Also, picking the best C_comp value is not a specific problem for differential buffers or the above technique, it is a general problem for any buffer model, even regular single ended buffers... Questions: Q1: on Page 38 and Page 39, in section "4.6.3 Separating the On-die Termination I-V Tables" of IBIS Modeling Cookbook (IBIS Open Forum) - above mentioned http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf - -is written: "The procedure for this is similar to the corresponding subtraction procedure used for single-ended drivers. The I-V characteristics of the driver must be obtained twice, once in the driving mode and once in the 3-stated (high impedance) mode, and the 3-stated I-V table data must be substracted from the driving I-V table data. The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." On what is exactly meant by "The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." . What is the difference comparing to procedures that are done with s2ibis2 or s2ibis3, since there is well done substracting of 3-stated I-V tables from driving I-V tables? AM: The traditional subtraction in the IBIS world refers to subtracting the clamp IV curves from the driving IV curves, so that the pullup and pulldown tables would contain only the drive currents. The addition subtraction described in the quoted text refers to separating the pad-to-pad, differential current from the total pad current, so that the pullup and pulldown tables would not include any differential currents (nor should they include any clamping currents, but that is taken care of doing the two measurements, driven and 3-stated). So the added complexity comes from needing to separate the differential current from the total current that is measured at the pad. Q2: is there some IBIS file available that is created with exactly this procedure? Can somebody send me such file? AM: I did generate a few IBIS files for differential buffers this way, but not too many, and honestly I don't know where they are, or whether they are available publicly... Q3: are there any public available tools (something like s2ibis2 or s2ibis3) that would support extraction of IBIS models described with this model? (Hereby I don't mean on HSpice, Matlab and Pearl scripts provided in http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf) AM: Not that I know of. However, if this technique seems to be widely used, I am sure we could talk with the NCU people and ask them to code it up in the s2ibis tool. Differential Buffers w/ Pre/De-emphasis 1. "Traditional" IBIS modeling - Model the building blocks of the buffer with independent [Model]s and tell the user to wire them up treats differential buffers as four independent [Model]s (2 Main, 2 boosts) driven by a stimulus and its complement Disadvantage: - - This approach was used initially for many models but required manual editing of files and/or simulation schematics 2. [Driver Shedule] Method for Pre-emphasis Buffer modeling http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basically describes 2 methods: V-I Through Transient simulation and [Driver Shedule]) http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf Advantage (of V-I Through Transient simulation method): - - relatively simple method Disadvantage (of V-I Through Transient simulation method): - - Non-monotonic wave forms (For some EDA tools) - - Single clock frequency operation (Changing the frequency needs remodeling) Advantage (of [Driver Schedule] Method): - - Changing the frequency doesn't need remodeling - - Eliminates the need for connecting two separate [Model]s by hand in the - - Eliminates the need for manually connecting [Model]s to make a complete buffer schematics, one for the Main and one for the Boost portion of the buffer - - Fewer transistor level (SPICE) models will need to be released to customers - - Uses no more than IBIS v3.2 syntax - - Useful for tools not supporting the *-AMS extensions of IBIS - Extends the life of legacy IBIS before requiring the IBIS v4.1 language extensions - - Reasonably good correlation with transistor level model Disadvantage (of [Driver Schedule] Method): - - Changing the frequency need changing of Rise_on, Rise_off, Fall_on and Fall_off times. Since legacy IBIS does not have provisions for clocked buffers, this model doesn't have a clock input, consequently the delay parameter is "hard coded" and will need to be changed manually in the IBIS file for every clock frequency and simulation corner - - The [Driver Schedule] delay parameters do not have typ., min., max. corners Obtaining separate [Model] data for the Main and Boost buffers may still require the editing of the SPICE netlist - - There are a few questions around proper handling of C_comp 3. IBIS modeling using v4.1 and v4.2 features (e.g. [External Circuit]) Advantage: - - flexibility (I guess so) Disadvantage: - - not all EDA tools support all features - - relatively complicated setup Question: Q4: - - can somebody send me an example of IBIS model that is using v4.1 and v4.2 features for describing Differential Buffers with Pre-/De-emphasis? 4. *-AMS Buffer Models Using IBIS v3.2 Data (although it can be applied on Differential Buffers w/o Pre/De-emphasis as well) Method described by (and many others): http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf AM: I would not recommend any of these methods in light of a better solution described in my presentation: http://www.vhdl.org/pub/ibis/summits/mar05/muranyi.pdf Advantage: - - according to my opinion absolutely the most "coolest" method (as mentioned on the beginning, I have done the homework and really experimented with Macro Model Library created by Arpad & Co. - please see my questions and comments bellow) for SI simulation - - very flexible method, gives you possibilities to do literally whatever you want (the only limitation are your EDA tools - in my case HSpice 2006.09 and it's Verilog-A interface) AM: Please use the latest version whenever possible, since Synopsys is fixing bugs all the time and add new features for more complete IBIS support. Disadvantage: - - "where" is IBIS here? (not really a disadvantage, but more like a question) AM: IBIS is more like wrapper in this case, contains the pin list, package info, and can pass parameters into the *-AMS models, which can still be useful. - - need to create IBIS models first and then to extract data in proper format (later to be read-out by Verilog-A) - - relatively high effort to create a proper setup and flow - - one needs to know (or at least understand) all :IBIS, HSpice and *-AMS - - (at least in this case that wasn't my problem :-))) AM: This is the model maker's problem. Model users do not have to know that much... Questions: Q5: is there a possibility to make HSpice more verbose when debugging it's Verilog-A interface? AM: Ask Synopsys about that... In sum I spent around half of the day just on debugging why Verilog-A "won't" compile Verilog code when including extracted IBIS data. AM: Ask Synopsys about that... Btw., please find in the attachment slightly changed Perl script (file name: "ibis2ams.pl") with which one can REALLY do something used in conjunction with for example http://www.vhdl.org/pub/ibis/macromodel_wip/template_lib/Verilog-A_PreDe - - - original script that is on http://www.vhdl.org/pub/ibis/macromodel_wip/tools/IBIS-to-AMS_conversion _tool.zip can't be since original script generates array "Ipu_data", and pre/de-emphasis template (Verilog-A code) requires array named "I_pu" (and other similar discrepancies). User just needs to change in the first row the path to his/her Perl executable. If IBIS model is generated with s2ibis2 user still needs to delete "S" (from pS) from generated data file. AM: To be honest, the Macro Modeling Library effort is not 100% finished. I am aware of the discrepancy you mention in the Perl script, and I thought we fixed it, but it may not have been uploaded to the web site yet. There are some other minor things that we need to fix and polish up in the library, such as the comments describing the various functions, etc... It kind of got pushed on the side when we started to work on the algorithmic modeling proposal in the IBIS-ATM subcommittee. So far I didn't get any requests about the Macro Modeling Library, and it seemed that it was not being used by anyone. If there is a need, we can certainly put it on a higher priority, just let me know. Q6: practical question - it seems that Verilog-A doesn't support "NA" in input array (e.g. "NA" in power or ground clamp data), although it is allowed in IBIS. Is there intention to change this in Verilog-A standard? Or at least how to handle "NA' in future? AM: You observation is correct. The Verilog-AMS (and also the VHDL-AMS) workgroup are currently discussing proposals to improve the $table_model keyword (and add a similar one to VHDL-AMS). Someone would have to bring this request to the workgroups. Although I wonder, since we are generating these tables with Perl scripts, is there a real need for this? The Perl script could very well take care of it. Q7: is it fair to say that calculation procedure (calculating/compensating of the I, V and C) used and described in "IBIS_macro_library.va" in module "IBIS_IO" is expected to be used by all other simulators - I mean, is it "The Algorithm" (with some minor changes and vendor specialties) that every tool that uses IBIS models should follow? AM: As far as I know, all simulator vendors who have IBIS support have implemented this "C_comp compensation" algorithm. The output waveform at the pad of an IBIS model must be the same as the Vt curve in that model, regardless of what the C_comp value is. This couldn't be done without the compensation algorithm. Many thanks to those that have read this mail until here, I am hoping on some your feedback! Best regards / Mit freundlichen Gru?en / S postovanjem Radovan Vuletic Qimonda AG QAG PD PDE MEM MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 60088 1233 Fax (PC): +49 (0)89 60088 45 5305 E-mail: radovan.vuletic@qimonda.com <> - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 1 Jun 2007 12:19:35 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] Variety of Approaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Radovan, I don't think that you will ever need the three columns at the same time (I mean a typical column together with a minimum or maximum column, or any other combination). So when you extract a data set for one case, you can delete those lines which contain the NA and keep the rest without needing any interpolation. Now, if this doesn't work for some reason, you could fill the NA-s with numbers in the Perl script by interpolation before the data is handed over to any of the *-AMS languages. Be careful, "NA" means "not available", not 0! There is a big difference there, as we experienced it with the [Driver Schedule] keyword. Arpad ========================================================== - -----Original Message----- From: Radovan.Vuletic@qimonda.com [mailto:Radovan.Vuletic@qimonda.com] Sent: Thursday, May 31, 2007 11:56 PM To: Muranyi, Arpad; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Approaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi Arpad, many thanks on your comments! Just one thing about Q6 and "NA" (specially in power and ground clamps). You have right, Perl script could take care of it, but for example in this case: [GND Clamp] ... ... 0.1500 -1.3479pA -1.3981pA -1.5422pA 0.2000 -0.5872pA -0.6494pA -0.7990pA 0.2392 0.0A NA NA 0.2408 NA 0.0A NA 0.2500 NA NA -47.2574fA 0.2532 NA NA 0.0A 3.0000 0.0A 0.0A 0.0A I agree, all "NA" in typ column and last 2 "NA" in min column could be replaced by 0.0A (already during table generation, not with Pearl script), but first "NA" in min column and all "NA" in max column can't be replaced with 0.0A, but for example, with some linear interpolation. Problem is that above table is extracted with "s2ibis like" tool (I agree, not very perfect tool) that puts "NA" when rearranging clamp tables (to avoid double counting) and we would need to make people aware they in their clamp tables they shouldn't have any "NA" but either 0.0A or interpolated values. Meaning, people would really need to take care about it in their extracting scripts. Regards, Radovan ============================================================================== Qimonda AG Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fischl Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J. Seifert Register Court/ Registergericht: München HRB 152545, Seat/ Sitz: München ============================================================================== - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sat, 2 Jun 2007 00:01:59 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) NA is part of the IBIS specification. If the simulator does not recognize NA then the simulator does not comply with the IBIS specification. The user should complain to the simulator's vendor to get it fixed. The user can do an interpolation of the curve to fill in the NAs to make the model work. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, June 01, 2007 7:09 AM To: lwang@iometh.com; arpad.muranyi@intel.com; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi Lance, in this case we were discussing what is Verilog-A doing with "NA" (after extracting of IBIS model tables with Pearl script to look-up tables) - please see below. I agree for other IBIS simulators, but problem is that in Verilog-A you can't have NA in look-up tables - code won't be even compiled. Regards, Radovan ============================================================================ == Qimonda AG Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fischl Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J. Seifert Register Court/ Registergericht: München HRB 152545, Seat/ Sitz: München ============================================================================ == - -----Original Message----- From: Lance Wang [mailto:lwang@iometh.com] Sent: Friday, June 01, 2007 3:54 PM To: Vuletic Radovan (QAG PD PDE MEM); arpad.muranyi@intel.com; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Radovan, Almost all the IBIS simulators will interpolate/extrapolate for the NAs in the IBIS curves. It should not be any problem if you leave NAs in IBIS. Regards, Lance Wang IO Methodology Inc. 978-764-2298 lwang@iometh.com - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, June 01, 2007 2:56 AM To: arpad.muranyi@intel.com; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi Arpad, many thanks on your comments! Just one thing about Q6 and "NA" (specially in power and ground clamps). You have right, Perl script could take care of it, but for example in this case: [GND Clamp] ... ... 0.1500 -1.3479pA -1.3981pA -1.5422pA 0.2000 -0.5872pA -0.6494pA -0.7990pA 0.2392 0.0A NA NA 0.2408 NA 0.0A NA 0.2500 NA NA -47.2574fA 0.2532 NA NA 0.0A 3.0000 0.0A 0.0A 0.0A I agree, all "NA" in typ column and last 2 "NA" in min column could be replaced by 0.0A (already during table generation, not with Pearl script), but first "NA" in min column and all "NA" in max column can't be replaced with 0.0A, but for example, with some linear interpolation. Problem is that above table is extracted with "s2ibis like" tool (I agree, not very perfect tool) that puts "NA" when rearranging clamp tables (to avoid double counting) and we would need to make people aware they in their clamp tables they shouldn't have any "NA" but either 0.0A or interpolated values. Meaning, people would really need to take care about it in their extracting scripts. Regards, Radovan ============================================================================ == Qimonda AG Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fischl Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J. Seifert Register Court/ Registergericht: München HRB 152545, Seat/ Sitz: München ============================================================================ == - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Muranyi, Arpad Sent: Thursday, May 31, 2007 10:00 PM To: ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Radovan, On your request (in a private mail) I am going attempt to answer your questions. Please find my responses between your lines preceded by "AM:". Sorry for the delay... Arpad ==================================================== - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, February 09, 2007 8:44 AM To: ibis-users@server.eda.org Subject: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi experts, for long time I was hoping that I will never have to do it, but now, with DDR4 (or NMT) knocking on the door it is finally on my schedule - IBIS models for differential I/O buffers. AM: Welcome to the club... :-) I have to say that I have read all possible documents (or at least I think so) available on Internet (IBIS Summits, Macro Modeling Subcommittee, etc..), I have contacted a few people to discuss what they have actually done, I have done the "homework" by experimenting with *-AMS Macro Library (one year later, but still), and so I would like here to share with you one summary on possibilities to create either IBIS models for differential buffers (w/ or w/o pre-/de-emphasis) or to create setups for simulation of these buffer. Also, in this my "analysis", I would have some questions, so if somebody knows the answers, please just write me. AM: Thanks for doing your homework, you seem to have done a good job! Disclaimer: I am perfectly aware that there is a possibility that I have, perhaps, wrote something wrong or stupid (I apologize in advance), but I am ready to take this risk, since I think that one of the purposes of this forum is discussing all possible (IBIS related) topics. Also, if I have forgotten to mention some work or author that is not done on purpose, but simply because of my limited capabilities. Main question: I know that it is impossible to get one general answer on this (but still, therefore I have done a whole analysis): What is mainstream solution/method - - what is the setup that are most customers looking for? I am asking this simply, because I wouldn't like to support every possible existing setup, but just to concentrate on one or two. AM: Can't answer this question, because I am not working on DDR simulations directly. In this summary, I have tried to list all kind of models/methods, starting with (according to me) most simple and than slowly increasing complexity - also I would like to distinguish between models of Differential buffers without Pre/De-emphasis and models of Differential buffers with Pre/De-emphasis. Differential Buffers w/o Pre/De-emphasis 1. "Traditional" IBIS modeling - treats differential buffers as two independent [Model]s driven by a stimulus and its complement Method described (for example) by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf Advantages: - - simple setup and usage Disadvantages: - - not describing the coupling effects between pads - - causes DC shifts in the signal level AM: This cannot be stated in general, because there are cases when this approach works perfectly fine. See my presentation at: http://www.vhdl.org/pub/ibis/summits/feb04a/muranyi1.pdf 2. Method described by - - A. Tambone (Semiconductor Business News 2000) - no link found - - http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z - - http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf - - http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf Advantages: - - relatively "smooth" and easy flow for understanding of IBIS extraction; - - relatively easy to adapt existing s2ibis2 or s2ibis3 flow; Disadvantages: - - LVDS IBIS models are accurate only when same VDDQ model was generated with is used - Changing VDDQ leads to very inaccurate results; - - LVDS IBIS models assume constant Vcm - Must generate multiple models for different values of vcm to obtain consistent accuracy driving different loads and topologies; - - Device asymmetry will affect accuracy of model - Model generated for both pads assumes perfect driver symmetry - Etch lengths of nets in differential pair matched; 3. Improved IBIS modeling approach (using only v3.2 keywords) Method described by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf - - http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf Advantages: - - describes DC currents of a differential buffer completely and accurately - - DC levels of the signals are correct under all loading conditions Disadvantages: - - pretty complicated procedure for extraction of model (at least for me) - - relatively big effort needed to automate the procedure - - need to make some guesses for picking up the 'best" value for C_comp AM: While it is true that this is more complicated, but once you have your scripts written it should be almost just a "pushbutton" solution. Making regular IV and Vt curves seemed just as hard before the various SPICE-to-IBIS tools came along... AM: Also, picking the best C_comp value is not a specific problem for differential buffers or the above technique, it is a general problem for any buffer model, even regular single ended buffers... Questions: Q1: on Page 38 and Page 39, in section "4.6.3 Separating the On-die Termination I-V Tables" of IBIS Modeling Cookbook (IBIS Open Forum) - above mentioned http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf - -is written: "The procedure for this is similar to the corresponding subtraction procedure used for single-ended drivers. The I-V characteristics of the driver must be obtained twice, once in the driving mode and once in the 3-stated (high impedance) mode, and the 3-stated I-V table data must be substracted from the driving I-V table data. The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." On what is exactly meant by "The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." . What is the difference comparing to procedures that are done with s2ibis2 or s2ibis3, since there is well done substracting of 3-stated I-V tables from driving I-V tables? AM: The traditional subtraction in the IBIS world refers to subtracting the clamp IV curves from the driving IV curves, so that the pullup and pulldown tables would contain only the drive currents. The addition subtraction described in the quoted text refers to separating the pad-to-pad, differential current from the total pad current, so that the pullup and pulldown tables would not include any differential currents (nor should they include any clamping currents, but that is taken care of doing the two measurements, driven and 3-stated). So the added complexity comes from needing to separate the differential current from the total current that is measured at the pad. Q2: is there some IBIS file available that is created with exactly this procedure? Can somebody send me such file? AM: I did generate a few IBIS files for differential buffers this way, but not too many, and honestly I don't know where they are, or whether they are available publicly... Q3: are there any public available tools (something like s2ibis2 or s2ibis3) that would support extraction of IBIS models described with this model? (Hereby I don't mean on HSpice, Matlab and Pearl scripts provided in http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf) AM: Not that I know of. However, if this technique seems to be widely used, I am sure we could talk with the NCU people and ask them to code it up in the s2ibis tool. Differential Buffers w/ Pre/De-emphasis 1. "Traditional" IBIS modeling - Model the building blocks of the buffer with independent [Model]s and tell the user to wire them up treats differential buffers as four independent [Model]s (2 Main, 2 boosts) driven by a stimulus and its complement Disadvantage: - - This approach was used initially for many models but required manual editing of files and/or simulation schematics 2. [Driver Shedule] Method for Pre-emphasis Buffer modeling http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basically describes 2 methods: V-I Through Transient simulation and [Driver Shedule]) http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf Advantage (of V-I Through Transient simulation method): - - relatively simple method Disadvantage (of V-I Through Transient simulation method): - - Non-monotonic wave forms (For some EDA tools) - - Single clock frequency operation (Changing the frequency needs remodeling) Advantage (of [Driver Schedule] Method): - - Changing the frequency doesn't need remodeling - - Eliminates the need for connecting two separate [Model]s by hand in the - - Eliminates the need for manually connecting [Model]s to make a complete buffer schematics, one for the Main and one for the Boost portion of the buffer - - Fewer transistor level (SPICE) models will need to be released to customers - - Uses no more than IBIS v3.2 syntax - - Useful for tools not supporting the *-AMS extensions of IBIS - Extends the life of legacy IBIS before requiring the IBIS v4.1 language extensions - - Reasonably good correlation with transistor level model Disadvantage (of [Driver Schedule] Method): - - Changing the frequency need changing of Rise_on, Rise_off, Fall_on and Fall_off times. Since legacy IBIS does not have provisions for clocked buffers, this model doesn't have a clock input, consequently the delay parameter is "hard coded" and will need to be changed manually in the IBIS file for every clock frequency and simulation corner - - The [Driver Schedule] delay parameters do not have typ., min., max. corners Obtaining separate [Model] data for the Main and Boost buffers may still require the editing of the SPICE netlist - - There are a few questions around proper handling of C_comp 3. IBIS modeling using v4.1 and v4.2 features (e.g. [External Circuit]) Advantage: - - flexibility (I guess so) Disadvantage: - - not all EDA tools support all features - - relatively complicated setup Question: Q4: - - can somebody send me an example of IBIS model that is using v4.1 and v4.2 features for describing Differential Buffers with Pre-/De-emphasis? 4. *-AMS Buffer Models Using IBIS v3.2 Data (although it can be applied on Differential Buffers w/o Pre/De-emphasis as well) Method described by (and many others): http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf AM: I would not recommend any of these methods in light of a better solution described in my presentation: http://www.vhdl.org/pub/ibis/summits/mar05/muranyi.pdf Advantage: - - according to my opinion absolutely the most "coolest" method (as mentioned on the beginning, I have done the homework and really experimented with Macro Model Library created by Arpad & Co. - please see my questions and comments bellow) for SI simulation - - very flexible method, gives you possibilities to do literally whatever you want (the only limitation are your EDA tools - in my case HSpice 2006.09 and it's Verilog-A interface) AM: Please use the latest version whenever possible, since Synopsys is fixing bugs all the time and add new features for more complete IBIS support. Disadvantage: - - "where" is IBIS here? (not really a disadvantage, but more like a question) AM: IBIS is more like wrapper in this case, contains the pin list, package info, and can pass parameters into the *-AMS models, which can still be useful. - - need to create IBIS models first and then to extract data in proper format (later to be read-out by Verilog-A) - - relatively high effort to create a proper setup and flow - - one needs to know (or at least understand) all :IBIS, HSpice and *-AMS - - (at least in this case that wasn't my problem :-))) AM: This is the model maker's problem. Model users do not have to know that much... Questions: Q5: is there a possibility to make HSpice more verbose when debugging it's Verilog-A interface? AM: Ask Synopsys about that... In sum I spent around half of the day just on debugging why Verilog-A "won't" compile Verilog code when including extracted IBIS data. AM: Ask Synopsys about that... Btw., please find in the attachment slightly changed Perl script (file name: "ibis2ams.pl") with which one can REALLY do something used in conjunction with for example http://www.vhdl.org/pub/ibis/macromodel_wip/template_lib/Verilog-A_PreDe - - - original script that is on http://www.vhdl.org/pub/ibis/macromodel_wip/tools/IBIS-to-AMS_conversion _tool.zip can't be since original script generates array "Ipu_data", and pre/de-emphasis template (Verilog-A code) requires array named "I_pu" (and other similar discrepancies). User just needs to change in the first row the path to his/her Perl executable. If IBIS model is generated with s2ibis2 user still needs to delete "S" (from pS) from generated data file. AM: To be honest, the Macro Modeling Library effort is not 100% finished. I am aware of the discrepancy you mention in the Perl script, and I thought we fixed it, but it may not have been uploaded to the web site yet. There are some other minor things that we need to fix and polish up in the library, such as the comments describing the various functions, etc... It kind of got pushed on the side when we started to work on the algorithmic modeling proposal in the IBIS-ATM subcommittee. So far I didn't get any requests about the Macro Modeling Library, and it seemed that it was not being used by anyone. If there is a need, we can certainly put it on a higher priority, just let me know. Q6: practical question - it seems that Verilog-A doesn't support "NA" in input array (e.g. "NA" in power or ground clamp data), although it is allowed in IBIS. Is there intention to change this in Verilog-A standard? Or at least how to handle "NA' in future? AM: You observation is correct. The Verilog-AMS (and also the VHDL-AMS) workgroup are currently discussing proposals to improve the $table_model keyword (and add a similar one to VHDL-AMS). Someone would have to bring this request to the workgroups. Although I wonder, since we are generating these tables with Perl scripts, is there a real need for this? The Perl script could very well take care of it. Q7: is it fair to say that calculation procedure (calculating/compensating of the I, V and C) used and described in "IBIS_macro_library.va" in module "IBIS_IO" is expected to be used by all other simulators - I mean, is it "The Algorithm" (with some minor changes and vendor specialties) that every tool that uses IBIS models should follow? AM: As far as I know, all simulator vendors who have IBIS support have implemented this "C_comp compensation" algorithm. The output waveform at the pad of an IBIS model must be the same as the Vt curve in that model, regardless of what the C_comp value is. This couldn't be done without the compensation algorithm. Many thanks to those that have read this mail until here, I am hoping on some your feedback! Best regards / Mit freundlichen Gru?en / S postovanjem Radovan Vuletic Qimonda AG QAG PD PDE MEM MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 60088 1233 Fax (PC): +49 (0)89 60088 45 5305 E-mail: radovan.vuletic@qimonda.com <> - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Sat, 2 Jun 2007 12:57:07 -0500 From: "Dunbar, Tony" Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) I agree with Tom that "NA" is a reserved word in the IBIS spec. and should be supported by the simulator. One question I have concerns using it in tables like the [GND Clamp] example seen below in this thread: Is it permissible to have NA at the end datapoints in such tables that have true data in them? By 'true data' I mean a table, like the Typ table, that must have datapoints as opposed to the Min and/or Max tables that can be all NA. Modifying the example [GND Clamp] table, is the following Typ table legal and should it be handled by interpolation by the simulator: - [GND Clamp] ... ... 0.1500 -1.3479pA -1.3981pA -1.5422pA 0.2000 -0.5872pA -0.6494pA -0.7990pA 0.2392 -0.4pA NA NA 0.2408 -0.3pA 0.0A NA 0.2500 -0.2pA NA -47.2574fA 0.2532 NA NA 0.0A 3.0000 NA 0.0A 0.0A Thanks! Tony - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Tom Dagostino Sent: Saturday, June 02, 2007 2:02 AM To: Radovan.Vuletic@qimonda.com; lwang@iometh.com; arpad.muranyi@intel.com; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) NA is part of the IBIS specification. If the simulator does not recognize NA then the simulator does not comply with the IBIS specification. The user should complain to the simulator's vendor to get it fixed. The user can do an interpolation of the curve to fill in the NAs to make the model work. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, June 01, 2007 7:09 AM To: lwang@iometh.com; arpad.muranyi@intel.com; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi Lance, in this case we were discussing what is Verilog-A doing with "NA" (after extracting of IBIS model tables with Pearl script to look-up tables) - please see below. I agree for other IBIS simulators, but problem is that in Verilog-A you can't have NA in look-up tables - code won't be even compiled. Regards, Radovan ============================================================================ == Qimonda AG Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fischl Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J. Seifert Register Court/ Registergericht: München HRB 152545, Seat/ Sitz: München ============================================================================ == - -----Original Message----- From: Lance Wang [mailto:lwang@iometh.com] Sent: Friday, June 01, 2007 3:54 PM To: Vuletic Radovan (QAG PD PDE MEM); arpad.muranyi@intel.com; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Radovan, Almost all the IBIS simulators will interpolate/extrapolate for the NAs in the IBIS curves. It should not be any problem if you leave NAs in IBIS. Regards, Lance Wang IO Methodology Inc. 978-764-2298 lwang@iometh.com - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, June 01, 2007 2:56 AM To: arpad.muranyi@intel.com; ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi Arpad, many thanks on your comments! Just one thing about Q6 and "NA" (specially in power and ground clamps). You have right, Perl script could take care of it, but for example in this case: [GND Clamp] ... ... 0.1500 -1.3479pA -1.3981pA -1.5422pA 0.2000 -0.5872pA -0.6494pA -0.7990pA 0.2392 0.0A NA NA 0.2408 NA 0.0A NA 0.2500 NA NA -47.2574fA 0.2532 NA NA 0.0A 3.0000 0.0A 0.0A 0.0A I agree, all "NA" in typ column and last 2 "NA" in min column could be replaced by 0.0A (already during table generation, not with Pearl script), but first "NA" in min column and all "NA" in max column can't be replaced with 0.0A, but for example, with some linear interpolation. Problem is that above table is extracted with "s2ibis like" tool (I agree, not very perfect tool) that puts "NA" when rearranging clamp tables (to avoid double counting) and we would need to make people aware they in their clamp tables they shouldn't have any "NA" but either 0.0A or interpolated values. Meaning, people would really need to take care about it in their extracting scripts. Regards, Radovan ============================================================================ == Qimonda AG Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fischl Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J. Seifert Register Court/ Registergericht: München HRB 152545, Seat/ Sitz: München ============================================================================ == - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Muranyi, Arpad Sent: Thursday, May 31, 2007 10:00 PM To: ibis-users@server.eda.org Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Radovan, On your request (in a private mail) I am going attempt to answer your questions. Please find my responses between your lines preceded by "AM:". Sorry for the delay... Arpad ==================================================== - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Radovan.Vuletic@qimonda.com Sent: Friday, February 09, 2007 8:44 AM To: ibis-users@server.eda.org Subject: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Hi experts, for long time I was hoping that I will never have to do it, but now, with DDR4 (or NMT) knocking on the door it is finally on my schedule - IBIS models for differential I/O buffers. AM: Welcome to the club... :-) I have to say that I have read all possible documents (or at least I think so) available on Internet (IBIS Summits, Macro Modeling Subcommittee, etc..), I have contacted a few people to discuss what they have actually done, I have done the "homework" by experimenting with *-AMS Macro Library (one year later, but still), and so I would like here to share with you one summary on possibilities to create either IBIS models for differential buffers (w/ or w/o pre-/de-emphasis) or to create setups for simulation of these buffer. Also, in this my "analysis", I would have some questions, so if somebody knows the answers, please just write me. AM: Thanks for doing your homework, you seem to have done a good job! Disclaimer: I am perfectly aware that there is a possibility that I have, perhaps, wrote something wrong or stupid (I apologize in advance), but I am ready to take this risk, since I think that one of the purposes of this forum is discussing all possible (IBIS related) topics. Also, if I have forgotten to mention some work or author that is not done on purpose, but simply because of my limited capabilities. Main question: I know that it is impossible to get one general answer on this (but still, therefore I have done a whole analysis): What is mainstream solution/method - - what is the setup that are most customers looking for? I am asking this simply, because I wouldn't like to support every possible existing setup, but just to concentrate on one or two. AM: Can't answer this question, because I am not working on DDR simulations directly. In this summary, I have tried to list all kind of models/methods, starting with (according to me) most simple and than slowly increasing complexity - also I would like to distinguish between models of Differential buffers without Pre/De-emphasis and models of Differential buffers with Pre/De-emphasis. Differential Buffers w/o Pre/De-emphasis 1. "Traditional" IBIS modeling - treats differential buffers as two independent [Model]s driven by a stimulus and its complement Method described (for example) by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf Advantages: - - simple setup and usage Disadvantages: - - not describing the coupling effects between pads - - causes DC shifts in the signal level AM: This cannot be stated in general, because there are cases when this approach works perfectly fine. See my presentation at: http://www.vhdl.org/pub/ibis/summits/feb04a/muranyi1.pdf 2. Method described by - - A. Tambone (Semiconductor Business News 2000) - no link found - - http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z - - http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf - - http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf Advantages: - - relatively "smooth" and easy flow for understanding of IBIS extraction; - - relatively easy to adapt existing s2ibis2 or s2ibis3 flow; Disadvantages: - - LVDS IBIS models are accurate only when same VDDQ model was generated with is used - Changing VDDQ leads to very inaccurate results; - - LVDS IBIS models assume constant Vcm - Must generate multiple models for different values of vcm to obtain consistent accuracy driving different loads and topologies; - - Device asymmetry will affect accuracy of model - Model generated for both pads assumes perfect driver symmetry - Etch lengths of nets in differential pair matched; 3. Improved IBIS modeling approach (using only v3.2 keywords) Method described by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf - - http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf Advantages: - - describes DC currents of a differential buffer completely and accurately - - DC levels of the signals are correct under all loading conditions Disadvantages: - - pretty complicated procedure for extraction of model (at least for me) - - relatively big effort needed to automate the procedure - - need to make some guesses for picking up the 'best" value for C_comp AM: While it is true that this is more complicated, but once you have your scripts written it should be almost just a "pushbutton" solution. Making regular IV and Vt curves seemed just as hard before the various SPICE-to-IBIS tools came along... AM: Also, picking the best C_comp value is not a specific problem for differential buffers or the above technique, it is a general problem for any buffer model, even regular single ended buffers... Questions: Q1: on Page 38 and Page 39, in section "4.6.3 Separating the On-die Termination I-V Tables" of IBIS Modeling Cookbook (IBIS Open Forum) - above mentioned http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf - -is written: "The procedure for this is similar to the corresponding subtraction procedure used for single-ended drivers. The I-V characteristics of the driver must be obtained twice, once in the driving mode and once in the 3-stated (high impedance) mode, and the 3-stated I-V table data must be substracted from the driving I-V table data. The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." On what is exactly meant by "The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." . What is the difference comparing to procedures that are done with s2ibis2 or s2ibis3, since there is well done substracting of 3-stated I-V tables from driving I-V tables? AM: The traditional subtraction in the IBIS world refers to subtracting the clamp IV curves from the driving IV curves, so that the pullup and pulldown tables would contain only the drive currents. The addition subtraction described in the quoted text refers to separating the pad-to-pad, differential current from the total pad current, so that the pullup and pulldown tables would not include any differential currents (nor should they include any clamping currents, but that is taken care of doing the two measurements, driven and 3-stated). So the added complexity comes from needing to separate the differential current from the total current that is measured at the pad. Q2: is there some IBIS file available that is created with exactly this procedure? Can somebody send me such file? AM: I did generate a few IBIS files for differential buffers this way, but not too many, and honestly I don't know where they are, or whether they are available publicly... Q3: are there any public available tools (something like s2ibis2 or s2ibis3) that would support extraction of IBIS models described with this model? (Hereby I don't mean on HSpice, Matlab and Pearl scripts provided in http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf) AM: Not that I know of. However, if this technique seems to be widely used, I am sure we could talk with the NCU people and ask them to code it up in the s2ibis tool. Differential Buffers w/ Pre/De-emphasis 1. "Traditional" IBIS modeling - Model the building blocks of the buffer with independent [Model]s and tell the user to wire them up treats differential buffers as four independent [Model]s (2 Main, 2 boosts) driven by a stimulus and its complement Disadvantage: - - This approach was used initially for many models but required manual editing of files and/or simulation schematics 2. [Driver Shedule] Method for Pre-emphasis Buffer modeling http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basically describes 2 methods: V-I Through Transient simulation and [Driver Shedule]) http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf Advantage (of V-I Through Transient simulation method): - - relatively simple method Disadvantage (of V-I Through Transient simulation method): - - Non-monotonic wave forms (For some EDA tools) - - Single clock frequency operation (Changing the frequency needs remodeling) Advantage (of [Driver Schedule] Method): - - Changing the frequency doesn't need remodeling - - Eliminates the need for connecting two separate [Model]s by hand in the - - Eliminates the need for manually connecting [Model]s to make a complete buffer schematics, one for the Main and one for the Boost portion of the buffer - - Fewer transistor level (SPICE) models will need to be released to customers - - Uses no more than IBIS v3.2 syntax - - Useful for tools not supporting the *-AMS extensions of IBIS - Extends the life of legacy IBIS before requiring the IBIS v4.1 language extensions - - Reasonably good correlation with transistor level model Disadvantage (of [Driver Schedule] Method): - - Changing the frequency need changing of Rise_on, Rise_off, Fall_on and Fall_off times. Since legacy IBIS does not have provisions for clocked buffers, this model doesn't have a clock input, consequently the delay parameter is "hard coded" and will need to be changed manually in the IBIS file for every clock frequency and simulation corner - - The [Driver Schedule] delay parameters do not have typ., min., max. corners Obtaining separate [Model] data for the Main and Boost buffers may still require the editing of the SPICE netlist - - There are a few questions around proper handling of C_comp 3. IBIS modeling using v4.1 and v4.2 features (e.g. [External Circuit]) Advantage: - - flexibility (I guess so) Disadvantage: - - not all EDA tools support all features - - relatively complicated setup Question: Q4: - - can somebody send me an example of IBIS model that is using v4.1 and v4.2 features for describing Differential Buffers with Pre-/De-emphasis? 4. *-AMS Buffer Models Using IBIS v3.2 Data (although it can be applied on Differential Buffers w/o Pre/De-emphasis as well) Method described by (and many others): http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf AM: I would not recommend any of these methods in light of a better solution described in my presentation: http://www.vhdl.org/pub/ibis/summits/mar05/muranyi.pdf Advantage: - - according to my opinion absolutely the most "coolest" method (as mentioned on the beginning, I have done the homework and really experimented with Macro Model Library created by Arpad & Co. - please see my questions and comments bellow) for SI simulation - - very flexible method, gives you possibilities to do literally whatever you want (the only limitation are your EDA tools - in my case HSpice 2006.09 and it's Verilog-A interface) AM: Please use the latest version whenever possible, since Synopsys is fixing bugs all the time and add new features for more complete IBIS support. Disadvantage: - - "where" is IBIS here? (not really a disadvantage, but more like a question) AM: IBIS is more like wrapper in this case, contains the pin list, package info, and can pass parameters into the *-AMS models, which can still be useful. - - need to create IBIS models first and then to extract data in proper format (later to be read-out by Verilog-A) - - relatively high effort to create a proper setup and flow - - one needs to know (or at least understand) all :IBIS, HSpice and *-AMS - - (at least in this case that wasn't my problem :-))) AM: This is the model maker's problem. Model users do not have to know that much... Questions: Q5: is there a possibility to make HSpice more verbose when debugging it's Verilog-A interface? AM: Ask Synopsys about that... In sum I spent around half of the day just on debugging why Verilog-A "won't" compile Verilog code when including extracted IBIS data. AM: Ask Synopsys about that... Btw., please find in the attachment slightly changed Perl script (file name: "ibis2ams.pl") with which one can REALLY do something used in conjunction with for example http://www.vhdl.org/pub/ibis/macromodel_wip/template_lib/Verilog-A_PreDe - - - original script that is on http://www.vhdl.org/pub/ibis/macromodel_wip/tools/IBIS-to-AMS_conversion _tool.zip can't be since original script generates array "Ipu_data", and pre/de-emphasis template (Verilog-A code) requires array named "I_pu" (and other similar discrepancies). User just needs to change in the first row the path to his/her Perl executable. If IBIS model is generated with s2ibis2 user still needs to delete "S" (from pS) from generated data file. AM: To be honest, the Macro Modeling Library effort is not 100% finished. I am aware of the discrepancy you mention in the Perl script, and I thought we fixed it, but it may not have been uploaded to the web site yet. There are some other minor things that we need to fix and polish up in the library, such as the comments describing the various functions, etc... It kind of got pushed on the side when we started to work on the algorithmic modeling proposal in the IBIS-ATM subcommittee. So far I didn't get any requests about the Macro Modeling Library, and it seemed that it was not being used by anyone. If there is a need, we can certainly put it on a higher priority, just let me know. Q6: practical question - it seems that Verilog-A doesn't support "NA" in input array (e.g. "NA" in power or ground clamp data), although it is allowed in IBIS. Is there intention to change this in Verilog-A standard? Or at least how to handle "NA' in future? AM: You observation is correct. The Verilog-AMS (and also the VHDL-AMS) workgroup are currently discussing proposals to improve the $table_model keyword (and add a similar one to VHDL-AMS). Someone would have to bring this request to the workgroups. Although I wonder, since we are generating these tables with Perl scripts, is there a real need for this? The Perl script could very well take care of it. Q7: is it fair to say that calculation procedure (calculating/compensating of the I, V and C) used and described in "IBIS_macro_library.va" in module "IBIS_IO" is expected to be used by all other simulators - I mean, is it "The Algorithm" (with some minor changes and vendor specialties) that every tool that uses IBIS models should follow? AM: As far as I know, all simulator vendors who have IBIS support have implemented this "C_comp compensation" algorithm. The output waveform at the pad of an IBIS model must be the same as the Vt curve in that model, regardless of what the C_comp value is. This couldn't be done without the compensation algorithm. Many thanks to those that have read this mail until here, I am hoping on some your feedback! Best regards / Mit freundlichen Gru?en / S postovanjem Radovan Vuletic Qimonda AG QAG PD PDE MEM MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 60088 1233 Fax (PC): +49 (0)89 60088 45 5305 E-mail: radovan.vuletic@qimonda.com <> - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 4 Jun 2007 11:01:27 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) All, I am sensing a little confusion regarding NA-s, IBIS simulators, and Verilog-AMS here, so I will attempt to set the records straight with this message. While it is true that IBIS allows NA-s in the tables, and IBIS simulators must support those, this is NOT what the original message was talking about. We don't seem to be having any problems with IBIS simulators and NA-s in IBIS files these days. The original email made a suggestion that the $table_model keyword of Verilog-AMS should also support NA-s in the tables. Verilog-AMS and IBIS are two different animals. Verilog-AMS is a hardware description (modeling) language, which is basically a specialized programming language geared towards hardware modeling. It has a keyword called $table_model which allows the programmer to reference a data file (NOT an IBIS FILE) which contains tables of data and read it into the model. This is all done inside the Verilog-AMS environment, has nothing to do with IBIS or IBIS simulators. This situation is very much like the PWL sources in HSPICE, for example. The request of the original email was to add support for NA-s in the $table_model keyword of Verilog-AMS. This may be a reasonable request considering that there may be situations when the $table_model is used to read tables that come from IBIS files. However, the problem is that Verilog-AMS's file reading and parsing capabilities are quite limited. There is no IBIS file reading and parsing built into the $table_model keyword. It has its own file format requirements which are described in the Verilog-AMS language reference manual. (I would even dare to extend the original request of supporting NA-s in $table_model to ask for a complete IBIS file parser in it). Because of the very limited file I/O capabilities of Verilog-AMS, it is very difficult if not impossible to write an IBIS file parser in Verilog-AMS, and we are much better off if we wrote that file parser with another program or script, such as Perl. Since we are currently converting from IBIS to the Verilog-AMS syntax with an external program, it is not too hard to implement the proper handling of NA-s in that program as well, so that the $table_model of Verilog-AMS can read a file that is formatted to its liking. Now, the additional complication or confusion may have come from the IBIS external language linkages which includes Verilog-AMS. The IBIS links to these external languages does not automatically mean that the external models written in these languages will have to read data tables out of IBIS files. The external models described with these languages can do anything the model writer wants to do. It is certainly possible, though, to make use of IBIS I-V and V-t tables in an *-AMS model, as it has been shown in the IBIS Macromodel Library. However, as I said it above, these models rely on another program to read and parse the IBIS file and extract and convert the syntax of the I-V and V-t tables that they need. This technique, however, does not imply that an IBIS simulator, which supports the external languages will have to impose the IBIS rules of supporting NA-s in the tables on the keywords of the external language. This is actually impossible, and nonsense, because it would practically mean that the IBIS rules are valid and applicable to the *-AMS languages. I hope that this helped to clarify the NA rules in IBIS and the capabilities of the $table_model in Verilog-AMS. Thanks, Arpad ======================================================================== ===== - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 06 Jun 2007 16:07:35 -0700 From: Bob Ross Subject: [IBIS-Users] Asian IBIS Summit (China) First Announcement To All: The IBIS Open Forum is holding an Asian IBIS Summit Meeting in Beijing, China, a major technology center on Tuesday, September 11. This is an early initial announcement for longer term travel planning. Several companies listed below are co-sponsoring this large event to be held at the Park Plaza Hotel Bejing. Like in previous years, We are planning for about 150 - 200 attendees including several IBIS experts from the USA. We encourage technical contributions from Asia. We expect a full agenda of relevant material. Note, we are also planning a Summit in Tokyo, Japan on September 14 to be announced later. You may want to consider this in you travel plans. Bob Ross Teraspeed Consulting Group Lance Wang IO Methodologies, Inc. - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (CHINA) FIRST CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- http://www.eda-stds.org/pub/ibis/summits/sep07a/announcement_chinese.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( C H I N A ) Time/Date: Tuesday, September 11, 2007, 8:00 AM to 5:30 PM Meeting starts at 9:00 AM Location: Park Plaza Hotel 25 Zhichum Road Haiden District Beijing 100083 CHINA Tel: + 86-10-82356699 E-mail: beijing@parkplaza-bj.com http://www.parkplaza.com/beijingcn_sciencepark Venue: HongYun Room, 3rd floor, Beijing Park Plaza Hotel Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Primary Sponsor: Huawei Technologies Co-sponsors (in alphabetical order): Agilent Technologies, Ansoft Corporation, Cadence Design Systems, Intel Corporation, Mentor Graphics Corporation, Signal Integrity Software (SiSoft), Sigrity, Synopsys, and ZTE Corporation. Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND We have held twp successful meetings in Shenzhen and Shanghai. This year we are meeting in Beijing, the capital city of the Peoples Republic of China. It contains many high technology companies and many development and sales offices of foreign companies. Many sites of interest are near the conference hotel. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register using the information below (in English): Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Comments: (Such as assistance for the travel requirements at the end) Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Lance Wang, IO Methologies, Inc. lwang@iometh.com SIGNUP DEADLINE: September 4, 2007 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: August 14, 2007 to produce the presentation booklet for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in a Chinese. Submissions from Asia are encouraged. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:15 - 9:00 Sign in, casual conversation, vendor tables 9:00 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 17:30 Presentations 17:30 - 18:30 Casual conversations, vendor tables The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned. Several presentations on IBIS applications and behavioral modeling issues, including interconnects and system components, are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. A link to the Park Plaza Beijing Science Park Hotel is: http://www.parkplaza.com/beijingcn_sciencepark Comply with your travel rules, such as indicated in the link below to China and Shanghai. Work with your travel agent. Notify us as a sign-up comment if you need assistance. Visas, if needed, should fall in the visit/business category: http://www.travelchinaguide.com/china-visa/ - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 22 Jun 2007 12:07:57 -0700 From: April.Hachenburg@smsc.com Subject: [IBIS-Users] time step question This is a multipart message in MIME format. - --=_alternative 0069196107257302_= Content-Type: text/plain; charset="US-ASCII" IBIS users, I have a questions regarding simulation time for the V-T curves. I'm using the s2ibis3 script with spectre to create my model. When I used a simulation time of 3.0ns, I noticed that one of the rising waveforms was still settling under min. condition. As a result, I increased the simulation time. When I did so, the simulations ran to about 3ns still, then suddenly jumps to the final simulation time. All the following values revert to zero. I've included an example below. Has anyone seen this issue? If so, how do I resolve it? Thanks, April [Rising Waveform] R_fixture= 0.1500k V_fixture= 0.0 V_fixture_min= 0.0 V_fixture_max= 0.0 |time V(typ) V(min) V(max) | 0.0S 1.1973mV 0.9612mV 1.4062mV 50.51pS 1.2588mV 1.0489mV 1.4461mV 0.10nS 1.4906mV 1.2259mV 1.5095mV 0.15nS 1.9668mV 1.2757mV 1.8304mV 0.20nS 1.8327mV 1.2233mV 2.6068mV 0.25nS 1.6557mV 1.1725mV 2.5690mV 0.30nS 1.4814mV 1.1666mV 1.9088mV 0.35nS 0.8598mV 1.1546mV 1.0696mV 0.40nS 0.4808mV 0.9128mV 0.5701mV 0.45nS 0.3503mV 0.5327mV 0.4217mV 0.51nS 0.2508mV 0.3639mV 0.4082mV 0.56nS 0.1778mV 0.2484mV 0.4607mV 0.61nS 0.1280mV 0.2066mV 0.7377mV 0.66nS 0.1119mV 0.1626mV 0.8004mV 0.71nS 0.1326mV 0.1308mV -4.2468mV 0.76nS 79.3558uV 86.8717uV 40.2760mV 0.81nS 68.8351uV 55.0637uV 0.4070V 0.86nS 0.1283mV 11.4705uV 1.0312V 0.91nS -0.5143mV -17.7110uV 1.4799V 0.96nS -4.6066mV -52.9933uV 1.6007V 1.01nS -13.5297mV -87.7087uV 1.6237V 1.06nS 11.9615mV -0.1011mV 1.6280V 1.11nS 0.1830V -0.1240mV 1.6301V 1.16nS 0.4741V -0.1881mV 1.6306V 1.21nS 0.8229V -0.2977mV 1.6308V 1.26nS 1.1539V -0.4366mV 1.6314V 1.31nS 1.3391V -0.5495mV 1.6322V 1.36nS 1.4080V -0.6636mV 1.6325V 1.41nS 1.4325V -0.8265mV 1.6328V 1.46nS 1.4405V -1.0689mV 1.6329V 1.52nS 1.4472V -1.4895mV 1.6330V 1.57nS 1.4499V -3.2821mV 1.6331V 1.62nS 1.4511V -8.6506mV 1.6332V 1.67nS 1.4518V -17.2909mV 1.6333V 1.72nS 1.4521V -21.9207mV 1.6333V 1.77nS 1.4522V -25.7696mV 1.6334V 1.82nS 1.4522V -20.9140mV 1.6334V 1.87nS 1.4522V 20.9336mV 1.6334V 1.92nS 1.4523V 36.7265mV 1.6334V 1.97nS 1.4525V 0.1150V 1.6335V 2.02nS 1.4527V 0.1640V 1.6335V 2.07nS 1.4529V 0.2180V 1.6335V 2.12nS 1.4530V 0.2661V 1.6335V 2.17nS 1.4530V 0.3576V 1.6336V 2.22nS 1.4531V 0.4671V 1.6336V 2.27nS 1.4531V 0.5537V 1.6336V 2.32nS 1.4532V 0.6729V 1.6336V 2.37nS 1.4532V 0.8132V 1.6336V 2.42nS 1.4532V 0.9478V 1.6336V 2.47nS 1.4533V 1.0134V 1.6336V 2.53nS 1.4533V 1.0858V 1.6336V 2.58nS 1.4533V 1.1636V 1.6336V 2.63nS 1.4533V 1.1870V 1.6337V 2.68nS 1.4533V 1.2040V 1.6337V 2.73nS 1.4533V 1.2175V 1.6337V 2.78nS 1.4533V 1.2270V 1.6337V 2.83nS 1.4534V 1.2327V 1.6337V 2.88nS 1.4534V 1.2387V 1.6337V 2.93nS 1.4534V 1.2431V 1.6337V 5.00nS 1.4534V 1.2457V 1.6337V 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=_alternative 0069196107257302_= Content-Type: text/html; charset="US-ASCII"
IBIS users,
I have a questions regarding simulation time for the V-T curves.  I'm using the s2ibis3 script with spectre to create my model.  When I used a simulation time of 3.0ns, I noticed that one of the rising waveforms was still settling under min. condition.  As a result, I increased the simulation time.  When I did so, the simulations ran to about 3ns still, then suddenly jumps to the final simulation time.  All the following values revert to zero.  I've included an example below.

Has anyone seen this issue?  If so, how do I resolve it?

Thanks,
April




[Rising Waveform]
R_fixture= 0.1500k
V_fixture= 0.0
V_fixture_min= 0.0
V_fixture_max= 0.0
|time     V(typ)              V(min)              V(max)
|  
0.0S                1.1973mV          0.9612mV            1.4062mV
50.51pS           1.2588mV          1.0489mV            1.4461mV
0.10nS            1.4906mV          1.2259mV            1.5095mV
0.15nS            1.9668mV          1.2757mV            1.8304mV
0.20nS            1.8327mV          1.2233mV            2.6068mV
0.25nS            1.6557mV          1.1725mV            2.5690mV
0.30nS            1.4814mV          1.1666mV            1.9088mV
0.35nS            0.8598mV          1.1546mV            1.0696mV
0.40nS            0.4808mV          0.9128mV            0.5701mV
0.45nS            0.3503mV          0.5327mV            0.4217mV
0.51nS            0.2508mV          0.3639mV            0.4082mV
0.56nS            0.1778mV          0.2484mV            0.4607mV
0.61nS            0.1280mV          0.2066mV            0.7377mV
0.66nS            0.1119mV          0.1626mV            0.8004mV
0.71nS            0.1326mV          0.1308mV            -4.2468mV
0.76nS            79.3558uV         86.8717uV           40.2760mV
0.81nS            68.8351uV         55.0637uV           0.4070V
0.86nS            0.1283mV          11.4705uV           1.0312V
0.91nS            -0.5143mV         -17.7110uV          1.4799V
0.96nS            -4.6066mV         -52.9933uV          1.6007V
1.01nS            -13.5297mV        -87.7087uV          1.6237V
1.06nS            11.9615mV         -0.1011mV           1.6280V
1.11nS            0.1830V           -0.1240mV           1.6301V
1.16nS            0.4741V           -0.1881mV           1.6306V
1.21nS            0.8229V           -0.2977mV           1.6308V
1.26nS            1.1539V           -0.4366mV           1.6314V
1.31nS            1.3391V           -0.5495mV           1.6322V
1.36nS            1.4080V           -0.6636mV           1.6325V
1.41nS            1.4325V           -0.8265mV           1.6328V
1.46nS            1.4405V           -1.0689mV           1.6329V
1.52nS            1.4472V           -1.4895mV           1.6330V
1.57nS            1.4499V           -3.2821mV           1.6331V
1.62nS            1.4511V           -8.6506mV           1.6332V
1.67nS            1.4518V           -17.2909mV          1.6333V
1.72nS            1.4521V           -21.9207mV          1.6333V
1.77nS            1.4522V           -25.7696mV          1.6334V
1.82nS            1.4522V           -20.9140mV          1.6334V
1.87nS            1.4522V           20.9336mV           1.6334V
1.92nS            1.4523V           36.7265mV           1.6334V
1.97nS            1.4525V           0.1150V             1.6335V
2.02nS            1.4527V           0.1640V             1.6335V
2.07nS            1.4529V           0.2180V             1.6335V
2.12nS            1.4530V           0.2661V             1.6335V
2.17nS            1.4530V           0.3576V             1.6336V
2.22nS            1.4531V           0.4671V             1.6336V
2.27nS            1.4531V           0.5537V             1.6336V
2.32nS            1.4532V           0.6729V             1.6336V
2.37nS            1.4532V           0.8132V             1.6336V
2.42nS            1.4532V           0.9478V             1.6336V
2.47nS            1.4533V           1.0134V             1.6336V
2.53nS            1.4533V           1.0858V             1.6336V
2.58nS            1.4533V           1.1636V             1.6336V
2.63nS            1.4533V           1.1870V             1.6337V
2.68nS            1.4533V           1.2040V             1.6337V
2.73nS            1.4533V           1.2175V             1.6337V
2.78nS            1.4533V           1.2270V             1.6337V
2.83nS            1.4534V           1.2327V             1.6337V
2.88nS            1.4534V           1.2387V             1.6337V
2.93nS            1.4534V           1.2431V             1.6337V
5.00nS            1.4534V           1.2457V             1.6337V
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA
0.0S              NA                NA                  NA




--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --=_alternative 0069196107257302_=-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 22 Jun 2007 12:50:51 -0700 From: "Lynne D. Green" Subject: RE: [IBIS-Users] time step question This is a multi-part message in MIME format. - ------=_NextPart_000_0004_01C7B4CB.F6FE9A30 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Hello, April, The 0.0s times after 5ns clearly need to be removed. There are also fewer than 100 valid lines in the table. This looks like a bug that should be reported to Ambrish Varma at NCSU. The reason you see no steps between these two lines 2.93nS 1.4534V 1.2431V 1.6337V 5.00nS 1.4534V 1.2457V 1.6337V is because s2ibis3 selects time points for best accuracy, instead of keeping evenly spaced time points. Best regards, Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com _____ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of April.Hachenburg@smsc.com Sent: Friday, June 22, 2007 12:08 PM To: ibis-users@eda.org Subject: [IBIS-Users] time step question IBIS users, I have a questions regarding simulation time for the V-T curves. I'm using the s2ibis3 script with spectre to create my model. When I used a simulation time of 3.0ns, I noticed that one of the rising waveforms was still settling under min. condition. As a result, I increased the simulation time. When I did so, the simulations ran to about 3ns still, then suddenly jumps to the final simulation time. All the following values revert to zero. I've included an example below. Has anyone seen this issue? If so, how do I resolve it? Thanks, April [Rising Waveform] R_fixture= 0.1500k V_fixture= 0.0 V_fixture_min= 0.0 V_fixture_max= 0.0 |time V(typ) V(min) V(max) | 0.0S 1.1973mV 0.9612mV 1.4062mV 50.51pS 1.2588mV 1.0489mV 1.4461mV 0.10nS 1.4906mV 1.2259mV 1.5095mV 0.15nS 1.9668mV 1.2757mV 1.8304mV 0.20nS 1.8327mV 1.2233mV 2.6068mV 0.25nS 1.6557mV 1.1725mV 2.5690mV 0.30nS 1.4814mV 1.1666mV 1.9088mV 0.35nS 0.8598mV 1.1546mV 1.0696mV 0.40nS 0.4808mV 0.9128mV 0.5701mV 0.45nS 0.3503mV 0.5327mV 0.4217mV 0.51nS 0.2508mV 0.3639mV 0.4082mV 0.56nS 0.1778mV 0.2484mV 0.4607mV 0.61nS 0.1280mV 0.2066mV 0.7377mV 0.66nS 0.1119mV 0.1626mV 0.8004mV 0.71nS 0.1326mV 0.1308mV -4.2468mV 0.76nS 79.3558uV 86.8717uV 40.2760mV 0.81nS 68.8351uV 55.0637uV 0.4070V 0.86nS 0.1283mV 11.4705uV 1.0312V 0.91nS -0.5143mV -17.7110uV 1.4799V 0.96nS -4.6066mV -52.9933uV 1.6007V 1.01nS -13.5297mV -87.7087uV 1.6237V 1.06nS 11.9615mV -0.1011mV 1.6280V 1.11nS 0.1830V -0.1240mV 1.6301V 1.16nS 0.4741V -0.1881mV 1.6306V 1.21nS 0.8229V -0.2977mV 1.6308V 1.26nS 1.1539V -0.4366mV 1.6314V 1.31nS 1.3391V -0.5495mV 1.6322V 1.36nS 1.4080V -0.6636mV 1.6325V 1.41nS 1.4325V -0.8265mV 1.6328V 1.46nS 1.4405V -1.0689mV 1.6329V 1.52nS 1.4472V -1.4895mV 1.6330V 1.57nS 1.4499V -3.2821mV 1.6331V 1.62nS 1.4511V -8.6506mV 1.6332V 1.67nS 1.4518V -17.2909mV 1.6333V 1.72nS 1.4521V -21.9207mV 1.6333V 1.77nS 1.4522V -25.7696mV 1.6334V 1.82nS 1.4522V -20.9140mV 1.6334V 1.87nS 1.4522V 20.9336mV 1.6334V 1.92nS 1.4523V 36.7265mV 1.6334V 1.97nS 1.4525V 0.1150V 1.6335V 2.02nS 1.4527V 0.1640V 1.6335V 2.07nS 1.4529V 0.2180V 1.6335V 2.12nS 1.4530V 0.2661V 1.6335V 2.17nS 1.4530V 0.3576V 1.6336V 2.22nS 1.4531V 0.4671V 1.6336V 2.27nS 1.4531V 0.5537V 1.6336V 2.32nS 1.4532V 0.6729V 1.6336V 2.37nS 1.4532V 0.8132V 1.6336V 2.42nS 1.4532V 0.9478V 1.6336V 2.47nS 1.4533V 1.0134V 1.6336V 2.53nS 1.4533V 1.0858V 1.6336V 2.58nS 1.4533V 1.1636V 1.6336V 2.63nS 1.4533V 1.1870V 1.6337V 2.68nS 1.4533V 1.2040V 1.6337V 2.73nS 1.4533V 1.2175V 1.6337V 2.78nS 1.4533V 1.2270V 1.6337V 2.83nS 1.4534V 1.2327V 1.6337V 2.88nS 1.4534V 1.2387V 1.6337V 2.93nS 1.4534V 1.2431V 1.6337V 5.00nS 1.4534V 1.2457V 1.6337V 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA 0.0S NA NA NA - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0004_01C7B4CB.F6FE9A30 Content-Type: text/html; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable
Hello, April,
 
The 0.0s times after 5ns clearly need to be remove= d. =20 There are=20 also fewer than 100 valid lines in the table.
This looks like a= bug that=20 should be reported to Ambrish Varma at NCSU.
 
The reason you see no steps between these two=20 lines
2.93nS            1.4534V   &nb= sp;=20       1.2431V            =20 1.6337V
5.00nS     &n= bsp;=20      1.4534V           1.2457V &nbs= p;=20           1.6337V
is because s2ibis3 selects time points for best ac= curacy,=20 instead of keeping evenly spaced time points.
 
Best regards,
Lynne
 
 
"IBIS training when you need it, where you need=20 it."
 
Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.= com
425-788-0412
lgreen22@mindspring.com<= /SPAN>
 
 

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of=20 April.Hachenburg@smsc.com
Sent: Friday, June 22, 2007 12:08= =20 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] time = step=20 question


IBIS users,
I have a questions regarding simulation time f= or the=20 V-T curves.  I'm using the s2ibis3 script with spectre to create my= =20 model.  When I used a simulation time of 3.0ns, I noticed that one o= f the=20 rising waveforms was still settling under min. condition.  As a resu= lt, I=20 increased the simulation time.  When I did so, the simulations ran t= o=20 about 3ns still, then suddenly jumps to the final simulation time.  = All=20 the following values revert to zero.  I've included an example below= .=20

Has anyone seen this issu= e?=20  If so, how do I resolve it?

Thanks,
April= =20




[Rising Waveform]=20
R_fixture=3D 0.1500k <= BR>V_fixture=3D 0.0
V_fixture_min=3D 0.0
V_fixture_max=3D 0.0
|time  =20   V(typ)              V(min) &nbs= p;=20            V(max)
|  
0.0S=20                1.1973mV   &n= bsp;=20      0.9612mV          =20  1.4062mV
50.51pS  =  =20       1.2588mV          1.0489mV= =20            1.4461mV
0.10nS          =20  1.4906mV          1.2259mV     &= nbsp;=20      1.5095mV
= 0.15nS=20            1.9668mV       &n= bsp;=20  1.2757mV            1.8304mV= =20
0.20nS         &= nbsp;=20  1.8327mV          1.2233mV     &= nbsp;=20      2.6068mV
= 0.25nS=20            1.6557mV       &n= bsp;=20  1.1725mV            2.5690mV= =20
0.30nS         &= nbsp;=20  1.4814mV          1.1666mV     &= nbsp;=20      1.9088mV
= 0.35nS=20            0.8598mV       &n= bsp;=20  1.1546mV            1.0696mV= =20
0.40nS         &= nbsp;=20  0.4808mV          0.9128mV     &= nbsp;=20      0.5701mV
= 0.45nS=20            0.3503mV       &n= bsp;=20  0.5327mV            0.4217mV= =20
0.51nS         &= nbsp;=20  0.2508mV          0.3639mV     &= nbsp;=20      0.4082mV
= 0.56nS=20            0.1778mV       &n= bsp;=20  0.2484mV            0.4607mV= =20
0.61nS         &= nbsp;=20  0.1280mV          0.2066mV     &= nbsp;=20      0.7377mV
= 0.66nS=20            0.1119mV       &n= bsp;=20  0.1626mV            0.8004mV= =20
0.71nS         &= nbsp;=20  0.1326mV          0.1308mV     &= nbsp;=20      -4.2468mV
0.76nS=20            79.3558uV       &= nbsp;=20 86.8717uV           40.2760mV
0.81nS          =20  68.8351uV         55.0637uV      = ;=20     0.4070V
0.86nS =  =20          0.1283mV        =20  11.4705uV           1.0312V
0.91nS          =20  -0.5143mV         -17.7110uV     &nbs= p;=20    1.4799V
0.96nS &= nbsp;=20          -4.6066mV        = =20 -52.9933uV          1.6007V
1.01nS          =20  -13.5297mV        -87.7087uV     &nbs= p;=20    1.6237V
1.06nS &= nbsp;=20          11.9615mV        = =20 -0.1011mV           1.6280V
1.11nS           &nbs= p;0.1830V=20           -0.1240mV        = =20   1.6301V
1.16nS   =  =20        0.4741V          =20 -0.1881mV           1.6306V
1.21nS           &nbs= p;0.8229V=20           -0.2977mV        = =20   1.6308V
1.26nS   =  =20        1.1539V          =20 -0.4366mV           1.6314V
1.31nS           &nbs= p;1.3391V=20           -0.5495mV        = =20   1.6322V
1.36nS   =  =20        1.4080V          =20 -0.6636mV           1.6325V
1.41nS           &nbs= p;1.4325V=20           -0.8265mV        = =20   1.6328V
1.46nS   =  =20        1.4405V          =20 -1.0689mV           1.6329V
1.52nS           &nbs= p;1.4472V=20           -1.4895mV        = =20   1.6330V
1.57nS   =  =20        1.4499V          =20 -3.2821mV           1.6331V
1.62nS           &nbs= p;1.4511V=20           -8.6506mV        = =20   1.6332V
1.67nS   =  =20        1.4518V          =20 -17.2909mV          1.6333V
1.72nS           &nbs= p;1.4521V=20           -21.9207mV        = =20  1.6333V
1.77nS   &= nbsp;=20        1.4522V          =20 -25.7696mV          1.6334V
1.82nS           &nbs= p;1.4522V=20           -20.9140mV        = =20  1.6334V
1.87nS   &= nbsp;=20        1.4522V          =20 20.9336mV           1.6334V
1.92nS           &nbs= p;1.4523V=20           36.7265mV        = =20   1.6334V
1.97nS   =  =20        1.4525V           0.1= 150V=20             1.6335V
2.02nS           &nbs= p;1.4527V=20           0.1640V         &n= bsp;=20   1.6335V
2.07nS   =  =20        1.4529V           0.2= 180V=20             1.6335V
2.12nS           &nbs= p;1.4530V=20           0.2661V         &n= bsp;=20   1.6335V
2.17nS   =  =20        1.4530V           0.3= 576V=20             1.6336V
2.22nS           &nbs= p;1.4531V=20           0.4671V         &n= bsp;=20   1.6336V
2.27nS   =  =20        1.4531V           0.5= 537V=20             1.6336V
2.32nS           &nbs= p;1.4532V=20           0.6729V         &n= bsp;=20   1.6336V
2.37nS   =  =20        1.4532V           0.8= 132V=20             1.6336V
2.42nS           &nbs= p;1.4532V=20           0.9478V         &n= bsp;=20   1.6336V
2.47nS   =  =20        1.4533V           1.0= 134V=20             1.6336V
2.53nS           &nbs= p;1.4533V=20           1.0858V         &n= bsp;=20   1.6336V
2.58nS   =  =20        1.4533V           1.1= 636V=20             1.6336V
2.63nS           &nbs= p;1.4533V=20           1.1870V         &n= bsp;=20   1.6337V
2.68nS   =  =20        1.4533V           1.2= 040V=20             1.6337V
2.73nS           &nbs= p;1.4533V=20           1.2175V         &n= bsp;=20   1.6337V
2.78nS   =  =20        1.4533V           1.2= 270V=20             1.6337V
2.83nS           &nbs= p;1.4534V=20           1.2327V         &n= bsp;=20   1.6337V
2.88nS   =  =20        1.4534V           1.2= 387V=20             1.6337V
2.93nS           &nbs= p;1.4534V=20           1.2431V         &n= bsp;=20   1.6337V
5.00nS   =  =20        1.4534V           1.2= 457V=20             1.6337V
0.0S            =  NA=20                NA     &= nbsp;=20            NA
0.0S              NA   &= nbsp;=20            NA         &= nbsp;=20        NA
0.0S=20              NA       &= nbsp;=20        NA             &= nbsp;=20    NA
0.0S   &= nbsp;=20          NA           &= nbsp;=20    NA                = =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA
0.0S     &= nbsp;=20        NA             &= nbsp;=20  NA                =20  NA



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believed to be clean. - ------=_NextPart_000_0004_01C7B4CB.F6FE9A30-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 25 Jun 2007 09:21:16 -0500 From: Roy Leventhal Subject: [IBIS-Users] IEEE EMC 2007 features a lot of SI this year All, The IEEE EMC Symposium features a lot of Signal Integrity, Power Integrity, and EMC/EMI EDA papers this year. It's in Hawaii July 8-13 this year. Check it out: http://www.emc2007.org/pages/techsessions.htm Best Regards, Roy Leventhal http://www.semiconductorsimulation.com - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 25 Jun 2007 19:11:11 -0700 From: Bob Ross Subject: [IBIS-Users] Asian IBIS Summit (China) Second Announcement To All: The IBIS Open Forum is holding an Asian IBIS Summit Meeting in Beijing, China, a major technology center on Tuesday, September 11. This is an early initial announcement for longer term travel planning. Several companies listed below are co-sponsoring this large event to be held at the Park Plaza Hotel Bejing. Like in previous years, We are planning for about 150 - 200 attendees including several IBIS experts from the USA. We encourage technical contributions from Asia. We expect a full agenda of relevant material. Note, we are also planning a Summit in Tokyo, Japan on September 14 to be announced later. You may want to consider this in you travel plans. Bob Ross Teraspeed Consulting Group Lance Wang IO Methodologies, Inc. - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (CHINA) SECOND CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- http://www.eda-stds.org/pub/ibis/summits/sep07a/announcement_chinese.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( C H I N A ) Time/Date: Tuesday, September 11, 2007, 8:00 AM to 5:30 PM Meeting starts at 9:00 AM Location: Park Plaza Hotel 25 Zhichum Road Haiden District Beijing 100083 CHINA Tel: + 86-10-82356699 E-mail: beijing@parkplaza-bj.com http://www.parkplaza.com/beijingcn_sciencepark Venue: HongYun Room, 3rd floor, Beijing Park Plaza Hotel Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Primary Sponsor: Huawei Technologies Co-sponsors (in alphabetical order): Agilent Technologies, Ansoft Corporation, Cadence Design Systems, Intel Corporation, Mentor Graphics Corporation, Signal Integrity Software (SiSoft), Sigrity, Synopsys, and ZTE Corporation. Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND We have held twp successful meetings in Shenzhen and Shanghai. This year we are meeting in Beijing, the capital city of the Peoples Republic of China. It contains many high technology companies and many development and sales offices of foreign companies. Many sites of interest are near the conference hotel. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register using the information below (in English): Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Comments: (Such as assistance for the travel requirements at the end) Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Lance Wang, IO Methologies, Inc. lwang@iometh.com SIGNUP DEADLINE: September 4, 2007 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: August 14, 2007 to produce the presentation booklet for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in a Chinese. Submissions from Asia are encouraged. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:15 - 9:00 Sign in, casual conversation, vendor tables 9:00 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 17:30 Presentations 17:30 - 18:30 Casual conversations, vendor tables The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned. Several presentations on IBIS applications and behavioral modeling issues, including interconnects and system components, are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. A link to the Park Plaza Beijing Science Park Hotel is: http://www.parkplaza.com/beijingcn_sciencepark Comply with your travel rules, such as indicated in the link below to China and Shanghai. Work with your travel agent. Notify us as a sign-up comment if you need assistance. Visas, if needed, should fall in the visit/business category: http://www.travelchinaguide.com/china-visa/ - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #100 *************************