From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #102 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Friday, September 21 2007 Volume 01 : Number 102 ---------------------------------------------------------------------- Date: Thu, 23 Aug 2007 12:22:57 -0700 From: Bob Ross Subject: Re: [IBIS-Users] EBD file syntax Hi Nam: I agree with Randy's response that C3 is to ground. I want to add that the EBD format also has syntax rules to bring in Series models (such as a series capacitor), if that is needed for some other configuration. Bob rrwolff@micron.com wrote: > Nam, > > Your syntax looks fine to me. Capacitor C3 would be to an ideal > ground. In fact, all capacitors are connected to an ideal ground, even > in the transmission line case, where the capacitance is part of a > transmission line that references ideal ground. > > Regards, > Randy > > > Randy Wolff > SI Modeling Manager > Signal Integrity R&D Group > Micron Technology, Inc. > > > ------------------------------------------------------------------------ > From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On > Behalf Of Nguyen, Duynam > Sent: Wednesday, August 22, 2007 1:25 PM > To: ibis@eda.org > Cc: ibis-users@eda.org > Subject: [IBIS-Users] EBD file syntax > > > > Dear expert, > > I am trying to describe the following situation in an EBD file: a signal > net that goes from a die pad to a package pin A9. Physically, this > signal net consists of two traces. Each trace is on a different layer > and they are connected together by a via which is modeled as a small > capacitor of value c3 to ground. The die > > pad and the package pin are modeled by a series L and a grounded C. > > My EBD file attempt is depicted as follows > > > > [Path Description] SIGNAL_NAME > > Pin A9 > > Len = 0 L = l1 C = c1 / > > Len = length2 L=l2 C = c2 R=r2 / > > Len = 0 C = c3 / ç Allowed ? > > Len = length4 L=l4 C = c4 R=r4 / > > Len = 0 L = l5 C = c5 / > > Node DIE.5085 > > > > I have 2 questions: > > 1. About the representation of the capacitance c3 in the EBD file, do I > violate any EBD file specification by doing this ? > > Assuming the specification allows it, would the capacitance c3 be > interpreted as grounded or in-series ? > > 2. If the representation of the capacitance c3 as above is not allowed, > can I take out the offending line and the rest is still permitted ? > > In other words, there are still two traces with an electrical > discontinuity connecting them as follow: > > [Path Description] SIGNAL_NAME > > Pin A9 > > Len = 0 L = l1 C = c1 / > > Len = length2 L=l2 C = c2 R=r2 / > > Len = length4 L=l4 C = c4 R=r4 / > > Len = 0 L = l5 C = c5 / > > Node DIE.5085 > > > > Thank you much, > > Nam > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner , and is > believed to be clean. > > -- > > This message has been scanned for viruses and > > dangerous content by MailScanner , and is > > believed to be clean. - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 24 Aug 2007 18:30:58 -0500 From: Chitiz Mathema Subject: [IBIS-Users] IBIS question on C_comp Hello, I have some questions about C_Comp parameter in IBIS models. I am trying to resolve some issues for IBIS models of high frequency differential output buffers. I am trying to compare my SPICE model transient simulations with the IBIS model I generated for a differential output buffer. At low frequencies (eg ~ 100MHz), the SPICE and IBIS model output simulation waveforms correlate closely. But at higher frequencies (>400MHz), the SPICE and IBIS model simulations don't match as well. I am trying to see if the mismatch is due to the C_comp parameter, or if this is just a limitation of IBIS models not being able to capture high frequency effects. 1. How IBIS simulators use the C_comp parameter during simulations? 2. Don't the V-T tables and ramp information already take into account the effect of C_comp? 3. What does the C_comp parameter exactly represent? - -should it include die routes, pad capacitance, etc? 4. How should it be measured? 5. Should C_comp be measured in a special manner for differential buffers like LVDS buffers? I would appreciate your response. Thank you, - -Chitiz Mathema Cypress Semiconductor - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 24 Aug 2007 16:26:39 -0700 From: "Mirmak, Michael" Subject: [IBIS-Users] Asian IBIS Summit (Japan) Fifth Announcement To All: The IBIS Open Forum is holding its second Asian IBIS Summit (Japan) Meeting in Tokyo, Japan, where several major companies have design operations and use IBIS. JEITA (Japan Electronics and Information Technology Industries Association) is the primary event sponsor with several companies, listed below, acting as co-sponsors. The event will held at JEITA headquarters in Tokyo. Several US experts are expected to participate. This announcement is primarily for participation only. While we might be able to add a submission, we already expect to have a full program of technical content based on planned submissions so far. We have adjusted some times below from previous announcements to allow for the additional content. Also we are pleased to add two additional sponsors to those previously announced. Note that we are also holding a Summit in Beijing, China on September 11. You may want to consider this in your travel plans. Michael Mirmak Intel Corporation Takeshi Watanabe NEC Electronics Corporation - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (JAPAN) FIFTH CALL FOR PARTICIPATION - ----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( J A P A N ) Date/Time: Friday September 14, 2007, 8:30 AM to 4:00 PM Meeting starts at 9:00 AM Location: JEITA Headquarters 3rd Fl., Mitsui Sumitomo Kaijo Bldg. Annex 11, Kanda Surugadai 3-chome, Chiyoda-ku, Tokyo 101-0062 JAPAN http://www.jeita.or.jp/english/about/location/index.htm Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) EIA IBIS Open Forum Co-sponsors (in alphabetical order): Agilent Technologies ATE Service Corporation (Sigrity) Cadence Design Systems Cybernet Systems IVIS (Signal Integrity Software (SiSoft)) Mentor Graphics Corporation Zuken Cost: FREE, including refreshments and lunch Contact us for details regarding sponsorship BACKGROUND This year we are holding the second open Asian IBIS Summit (Japan) meeting. Participants include major Japanese companies operating in Tokyo and affiliated with JEITA and IBIS. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Japanese. Presenters may optionally deliver in Japanese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summit site and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Takeshi Watanabe, NEC Electronics Corp. takeshi.watanabe@necel.com SIGNUP DEADLINE: September 7, 2007 Because of limited space, advance registration is required. CALL FOR PRESENTATIONS NOTE: Our program is nearly full based on the expected submissions. We are seeking presentations from individuals who have IBIS experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Microsoft PowerPoint or Adobe PDF Presentation Copies: Available at the meeting for all attendees Presentation Deadline: September 7, 2007 to produce the presentation copies for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in either Japanese or English. Submissions from Asian are encouraged. AGENDA 8:30 Sign in Asian IBIS Summit (Japan) 9:00 Presentations 12:00 Free lunch 12:40 Presentations 16:00 End of Meeting 16:00 Open Discussion about EDA Model (JEITA-EIA/IBIS Meeting) Everyone is welcome 17:00 Welcome Party The specific agenda is being developed. While some expected submissions have not been finalized, we expect a full program covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned Several presentations on IBIS applications or modeling issues are expected from co-sponsor companies or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. JEITA suggests the Tokyo Dome Hotel. JEITA headquarters is located near several train stations (click image): http://www.jeita.or.jp/english/about/location/index.htm - ---------------------------------------------------------------- - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 24 Aug 2007 17:09:38 -0700 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] IBIS question on C_comp Chitiz, Thanks for your questions on IBIS. Here are some hopefully useful answers... 1,2) The purpose of C_comp is to describe the capacitance of the buffer at the pad, as it appears "looking in." You are correct that the V-t tables and ramp information already take C_comp into account, for drivers. However, C_comp is still needed in order to describe the capacitive load the buffer presents to waveforms (reflections) coming back into the driver. In general, tools ensure that C_comp as a discrete number and its effects in the table and ramp data are not double-counted. This may be implemented by simply "backing out" or derating the V-t tables for the effects of C_comp, then adding an actual capacitor to the driver circuit in simulation. In that way, the derated-table-plus-capacitor waveforms will match the original IBIS driver data, but the system will "see" the capacitance of the buffer as a load. Specific tools may have different ways to approach the problem. 3) C_comp should exclude the effects of the package, but include all the buffer's on-die parasitic capacitances -- pad, die routing, etc. 4) Information on extraction methods for C_comp, as well as differential treatments, can be found in the IBIS Cookbook: http://www.eda.org/ibis/cookbook/cookbook-v4.pdf In addition, several presentations on C_comp issues are available in the IBIS Summit archive: http://www.eda.org/ibis/summits/index-bytitle.htm To address your concern, I would not say that IBIS per se is not properly addressing high-frequency effects. However, C_comp in traditional table-driven IBIS is a single value. Capacitance for a buffer is frequency- and voltage-dependent. Therefore, the method of extraction and the frequency at which the extracted value applies are critical when correlating the resulting IBIS model. In the case you describe, I would check to make sure that the C_comp value was not extracted at a frequency below 400 MHz. A more comprehensive treatment of buffer capacitance is possible using advanced IBIS techniques, including multi-lingual methods (IBIS 4.1, 4.2). I hope this helps! - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chitiz Mathema Sent: Friday, August 24, 2007 4:31 PM To: ibis-users@server.eda.org Subject: [IBIS-Users] IBIS question on C_comp Hello, I have some questions about C_Comp parameter in IBIS models. I am trying to resolve some issues for IBIS models of high frequency differential output buffers. I am trying to compare my SPICE model transient simulations with the IBIS model I generated for a differential output buffer. At low frequencies (eg ~ 100MHz), the SPICE and IBIS model output simulation waveforms correlate closely. But at higher frequencies (>400MHz), the SPICE and IBIS model simulations don't match as well. I am trying to see if the mismatch is due to the C_comp parameter, or if this is just a limitation of IBIS models not being able to capture high frequency effects. 1. How IBIS simulators use the C_comp parameter during simulations? 2. Don't the V-T tables and ramp information already take into account the effect of C_comp? 3. What does the C_comp parameter exactly represent? - -should it include die routes, pad capacitance, etc? 4. How should it be measured? 5. Should C_comp be measured in a special manner for differential buffers like LVDS buffers? I would appreciate your response. Thank you, - -Chitiz Mathema Cypress Semiconductor - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 27 Aug 2007 08:12:45 -0700 From: April.Hachenburg@smsc.com Subject: RE: [IBIS-Users] IBIS question on C_comp This is a multipart message in MIME format. - --=_alternative 0053914907257344_= Content-Type: text/plain; charset="US-ASCII" Michael, Your response is helpful. I too am doing my first differential buffer so on a slightly different note .... Does the s2ibis3 script handle generation of differential buffers? If not, is there a similar script available? - - April - --------------------------------------------------- April Hachenburg Core Technology Design Engineer SMSC - Phoenix "Mirmak, Michael" Sent by: owner-ibis-users@server.eda.org 08/24/2007 05:10 PM To "Chitiz Mathema" , cc Subject RE: [IBIS-Users] IBIS question on C_comp Chitiz, Thanks for your questions on IBIS. Here are some hopefully useful answers... 1,2) The purpose of C_comp is to describe the capacitance of the buffer at the pad, as it appears "looking in." You are correct that the V-t tables and ramp information already take C_comp into account, for drivers. However, C_comp is still needed in order to describe the capacitive load the buffer presents to waveforms (reflections) coming back into the driver. In general, tools ensure that C_comp as a discrete number and its effects in the table and ramp data are not double-counted. This may be implemented by simply "backing out" or derating the V-t tables for the effects of C_comp, then adding an actual capacitor to the driver circuit in simulation. In that way, the derated-table-plus-capacitor waveforms will match the original IBIS driver data, but the system will "see" the capacitance of the buffer as a load. Specific tools may have different ways to approach the problem. 3) C_comp should exclude the effects of the package, but include all the buffer's on-die parasitic capacitances -- pad, die routing, etc. 4) Information on extraction methods for C_comp, as well as differential treatments, can be found in the IBIS Cookbook: http://www.eda.org/ibis/cookbook/cookbook-v4.pdf In addition, several presentations on C_comp issues are available in the IBIS Summit archive: http://www.eda.org/ibis/summits/index-bytitle.htm To address your concern, I would not say that IBIS per se is not properly addressing high-frequency effects. However, C_comp in traditional table-driven IBIS is a single value. Capacitance for a buffer is frequency- and voltage-dependent. Therefore, the method of extraction and the frequency at which the extracted value applies are critical when correlating the resulting IBIS model. In the case you describe, I would check to make sure that the C_comp value was not extracted at a frequency below 400 MHz. A more comprehensive treatment of buffer capacitance is possible using advanced IBIS techniques, including multi-lingual methods (IBIS 4.1, 4.2). I hope this helps! - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chitiz Mathema Sent: Friday, August 24, 2007 4:31 PM To: ibis-users@server.eda.org Subject: [IBIS-Users] IBIS question on C_comp Hello, I have some questions about C_Comp parameter in IBIS models. I am trying to resolve some issues for IBIS models of high frequency differential output buffers. I am trying to compare my SPICE model transient simulations with the IBIS model I generated for a differential output buffer. At low frequencies (eg ~ 100MHz), the SPICE and IBIS model output simulation waveforms correlate closely. But at higher frequencies (>400MHz), the SPICE and IBIS model simulations don't match as well. I am trying to see if the mismatch is due to the C_comp parameter, or if this is just a limitation of IBIS models not being able to capture high frequency effects. 1. How IBIS simulators use the C_comp parameter during simulations? 2. Don't the V-T tables and ramp information already take into account the effect of C_comp? 3. What does the C_comp parameter exactly represent? - -should it include die routes, pad capacitance, etc? 4. How should it be measured? 5. Should C_comp be measured in a special manner for differential buffers like LVDS buffers? I would appreciate your response. Thank you, - -Chitiz Mathema Cypress Semiconductor - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=_alternative 0053914907257344_= Content-Type: text/html; charset="US-ASCII"
Michael,
Your response is helpful.  I too am doing my first differential buffer so on a slightly different note ....

Does the s2ibis3 script handle generation of differential buffers?  If not, is there a similar script available?

- April

- ---------------------------------------------------
April Hachenburg
Core Technology Design Engineer
SMSC - Phoenix


"Mirmak, Michael" <michael.mirmak@intel.com>
Sent by: owner-ibis-users@server.eda.org

08/24/2007 05:10 PM

To
"Chitiz Mathema" <cit@cypress.com>, <ibis-users@server.eda.org>
cc
Subject
RE: [IBIS-Users] IBIS question on C_comp





Chitiz,

Thanks for your questions on IBIS.  Here are some hopefully useful
answers...

1,2) The purpose of C_comp is to describe the capacitance of the buffer
at the pad, as it appears "looking in."  You are correct that the V-t
tables and ramp information already take C_comp into account, for
drivers.  However, C_comp is still needed in order to describe the
capacitive load the buffer presents to waveforms (reflections) coming
back into the driver.

In general, tools ensure that C_comp as a discrete number and its
effects in the table and ramp data are not double-counted.  This may be
implemented by simply "backing out" or derating the V-t tables for the
effects of C_comp, then adding an actual capacitor to the driver circuit
in simulation.  In that way, the derated-table-plus-capacitor waveforms
will match the original IBIS driver data, but the system will "see" the
capacitance of the buffer as a load.  Specific tools may have different
ways to approach the problem.

3) C_comp should exclude the effects of the package, but include all the
buffer's on-die parasitic capacitances -- pad, die routing, etc.

4) Information on extraction methods for C_comp, as well as differential
treatments, can be found in the IBIS Cookbook:

http://www.eda.org/ibis/cookbook/cookbook-v4.pdf

In addition, several presentations on C_comp issues are available in the
IBIS Summit archive:

http://www.eda.org/ibis/summits/index-bytitle.htm

To address your concern, I would not say that IBIS per se is not
properly addressing high-frequency effects.    However, C_comp in
traditional table-driven IBIS is a single value.  Capacitance for a
buffer is frequency- and voltage-dependent.  Therefore, the method of
extraction and the frequency at which the extracted value applies are
critical when correlating the resulting IBIS model.  In the case you
describe, I would check to make sure that the C_comp value was not
extracted at a frequency below 400 MHz.

A more comprehensive treatment of buffer capacitance is possible using
advanced IBIS techniques, including multi-lingual methods (IBIS 4.1,
4.2).

I hope this helps!

- - Michael Mirmak
 Intel Corp.
 Chair, EIA IBIS Open Forum


- -----Original Message-----
From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Chitiz Mathema
Sent: Friday, August 24, 2007 4:31 PM
To: ibis-users@server.eda.org
Subject: [IBIS-Users] IBIS question on C_comp

Hello,

I have some questions about C_Comp parameter in IBIS models. I am trying

to resolve some issues for IBIS models of high frequency differential
output buffers.
I am trying to compare my SPICE model transient simulations with the
IBIS model I generated for a differential output buffer. At low
frequencies (eg ~ 100MHz), the SPICE and IBIS model output simulation
waveforms correlate closely. But at higher frequencies (>400MHz), the
SPICE and IBIS model simulations don't match as well. I am trying to see

if the mismatch is due to the C_comp parameter, or if this is just a
limitation of IBIS models not being able to capture high frequency
effects.

1. How IBIS simulators use the C_comp parameter during simulations?
2. Don't the V-T tables and ramp information already take into account
the effect of C_comp?
3. What does the C_comp parameter exactly represent?
- -should it include die routes, pad capacitance, etc?
4. How should it be measured?
5. Should C_comp be measured in a special manner for differential
buffers like LVDS buffers?

I would appreciate your response.

Thank you,
- -Chitiz Mathema
Cypress Semiconductor




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believed to be clean. - --=_alternative 0053914907257344_=-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 28 Aug 2007 08:12:43 +0200 From: Subject: RE: [IBIS-Users] IBIS question on C_comp This is a multi-part message in MIME format. - ------_=_NextPart_001_01C7E93A.72B812C7 Content-Type: multipart/alternative; boundary="----_=_NextPart_002_01C7E93A.72B812C7" - ------_=_NextPart_002_01C7E93A.72B812C7 Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Hi April, =20 if it will help you I was discussing on this topic some 6 months ago (pleas= e find in the attachment mail with subject: " IBIS-Users Variety of Aproac= hes on IBIS Modeling on Differential I O Buffers (with and without Pre- De-= Emphasis).msg") - but shortly, there are many approaches, you have to find = your own or if you like message is that there is no straight-forward soluti= on. =20 Best regards / Mit freundlichen Gr=FC=DFen / S po=B9tovanjem=20 Radovan Vuleti=E6=20 Qimonda AG=20 QAG PD PDE MEM=20 MUC/10.2.236 AP 3=20 Am Campeon 1-12=20 D-85579 Neuebiberg=20 Phone: +49 (0)89 60088 1233=20 Fax (PC): +49 (0)89 60088 45 5305=20 E-mail: radovan.vuletic@qimonda.com =20= =20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=20 Qimonda AG=20 Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fisc= hl=20 Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Micha= el Majerus, Thomas J. Seifert=20 Register Court/ Registergericht: M=FCnchen HRB 152545, Seat/ Sitz: M=FCnche= n=20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=20 =20 ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.o= rg] On Behalf Of April.Hachenburg@smsc.com Sent: Monday, August 27, 2007 5:13 PM To: Mirmak, Michael Cc: Chitiz Mathema; ibis-users@server.eda.org; owner-ibis-users@server.eda.= org Subject: RE: [IBIS-Users] IBIS question on C_comp Michael,=20 Your response is helpful. I too am doing my first differential buffer so o= n a slightly different note ....=20 Does the s2ibis3 script handle generation of differential buffers? If not,= is there a similar script available?=20 - - April - --------------------------------------------------- April Hachenburg Core Technology Design Engineer SMSC - Phoenix "Mirmak, Michael" =20 Sent by: owner-ibis-users@server.eda.org=20 08/24/2007 05:10 PM=20 To "Chitiz Mathema" , =20 cc Subject RE: [IBIS-Users] IBIS question on C_comp =09 Chitiz, Thanks for your questions on IBIS. Here are some hopefully useful answers... 1,2) The purpose of C_comp is to describe the capacitance of the buffer at the pad, as it appears "looking in." You are correct that the V-t tables and ramp information already take C_comp into account, for drivers. However, C_comp is still needed in order to describe the capacitive load the buffer presents to waveforms (reflections) coming back into the driver. In general, tools ensure that C_comp as a discrete number and its effects in the table and ramp data are not double-counted. This may be implemented by simply "backing out" or derating the V-t tables for the effects of C_comp, then adding an actual capacitor to the driver circuit in simulation. In that way, the derated-table-plus-capacitor waveforms will match the original IBIS driver data, but the system will "see" the capacitance of the buffer as a load. Specific tools may have different ways to approach the problem. 3) C_comp should exclude the effects of the package, but include all the buffer's on-die parasitic capacitances -- pad, die routing, etc. 4) Information on extraction methods for C_comp, as well as differential treatments, can be found in the IBIS Cookbook: http://www.eda.org/ibis/cookbook/cookbook-v4.pdf In addition, several presentations on C_comp issues are available in the IBIS Summit archive: http://www.eda.org/ibis/summits/index-bytitle.htm To address your concern, I would not say that IBIS per se is not properly addressing high-frequency effects. However, C_comp in traditional table-driven IBIS is a single value. Capacitance for a buffer is frequency- and voltage-dependent. Therefore, the method of extraction and the frequency at which the extracted value applies are critical when correlating the resulting IBIS model. In the case you describe, I would check to make sure that the C_comp value was not extracted at a frequency below 400 MHz. A more comprehensive treatment of buffer capacitance is possible using advanced IBIS techniques, including multi-lingual methods (IBIS 4.1, 4.2). I hope this helps! - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chitiz Mathema Sent: Friday, August 24, 2007 4:31 PM To: ibis-users@server.eda.org Subject: [IBIS-Users] IBIS question on C_comp Hello, I have some questions about C_Comp parameter in IBIS models. I am trying to resolve some issues for IBIS models of high frequency differential=20 output buffers. I am trying to compare my SPICE model transient simulations with the=20 IBIS model I generated for a differential output buffer. At low=20 frequencies (eg ~ 100MHz), the SPICE and IBIS model output simulation=20 waveforms correlate closely. But at higher frequencies (>400MHz), the=20 SPICE and IBIS model simulations don't match as well. I am trying to see if the mismatch is due to the C_comp parameter, or if this is just a=20 limitation of IBIS models not being able to capture high frequency effects. 1. How IBIS simulators use the C_comp parameter during simulations? 2. Don't the V-T tables and ramp information already take into account=20 the effect of C_comp? 3. What does the C_comp parameter exactly represent? - -should it include die routes, pad capacitance, etc? 4. How should it be measured? 5. Should C_comp be measured in a special manner for differential=20 buffers like LVDS buffers? I would appreciate your response. Thank you, - -Chitiz Mathema Cypress Semiconductor - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is=20 believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_002_01C7E93A.72B812C7 Content-Type: text/html; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable
Hi=20 April,
 
if it=20 will help you I was discussing on this topic some 6 months ago (please find= in=20 the attachment mail with subject: " IBIS-Users  Variety of Aproac= hes=20 on IBIS Modeling on Differential I O Buffers (with and without Pre-=20 De-Emphasis).msg") - but shortly, there are many approaches, you have to fi= nd=20 your own or if you like message is that there is no straight-forward=20 solution.
 

Best regards / Mit freundlichen Gr=FC=DFe= n / S=20 po=B9tovanjem
Radovan=20 Vuleti=E6

Qimonda AG
QAG PD PDE MEM
MUC/10.2.236 AP 3
Am Campeon 1-12
D-85579 Neuebiberg

Phone:&nb= sp;=20         +49 (0)89 60088 1233=20
Fax=20 (PC):       +49 (0)89 60088 45 5305=20

E-mail:= =20 radovan.vuletic@qimonda.com=20


=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=20
Qimonda AG=20
Chairman of the = Supervisory=20 Board/ Aufsichtsratsvorsitzender: Peter J. Fischl
Management Board/ Vorstand= : Kin Wah=20 Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J.=20 Seifert
Register=20 Court/ Registergericht: M=FCnchen HRB 152545, Seat/ Sitz: M=FCnchen<= /SPAN>=20
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=20



 

From: owner-ibis-users@server.eda.org= =20 [mailto:owner-ibis-users@server.eda.org] On Behalf Of=20 April.Hachenburg@smsc.com
Sent: Monday, August 27, 2007 5:13= =20 PM
To: Mirmak, Michael
Cc: Chitiz Mathema;=20 ibis-users@server.eda.org; owner-ibis-users@server.eda.org
Subject:=20 RE: [IBIS-Users] IBIS question on C_comp


Michael,
Your response is helpful.  I too am doing m= y first=20 differential buffer so on a slightly different note ....

Does the s2ibis3 script handle generation of dif= ferential=20 buffers?  If not, is there a similar script available?

= -=20 April

---------------------------------------------------
April= =20 Hachenburg
Core Technology Design Engineer
SMSC -=20 Phoenix



"Mirmak, Michael"= =20 <michael.mirmak@intel.com>
Sent by: owner-ibis-users@server.eda.org=20

08/24/2007 05:10 PM

To
"Chitiz Mathema"=20 <cit@cypress.com>, <ibis-users@server.eda.org>=20
cc
Subject
RE: [IBIS-Users] IBIS questi= on on=20 C_comp





Chitiz,

Thanks for your questions on IBIS.  Here are s= ome=20 hopefully useful
answers...

1,2) The purpose of C_comp is to desc= ribe=20 the capacitance of the buffer
at the pad, as it appears "looking in."=20  You are correct that the V-t
tables and ramp information already t= ake=20 C_comp into account, for
drivers.  However, C_comp is still needed = in=20 order to describe the
capacitive load the buffer presents to waveforms= =20 (reflections) coming
back into the driver.

In general, tools ensu= re=20 that C_comp as a discrete number and its
effects in the table and ramp d= ata=20 are not double-counted.  This may be
implemented by simply "backing= out"=20 or derating the V-t tables for the
effects of C_comp, then adding an act= ual=20 capacitor to the driver circuit
in simulation.  In that way, the=20 derated-table-plus-capacitor waveforms
will match the original IBIS driv= er=20 data, but the system will "see" the
capacitance of the buffer as a load.= =20  Specific tools may have different
ways to approach the=20 problem.

3) C_comp should exclude the effects of the package, but in= clude=20 all the
buffer's on-die parasitic capacitances -- pad, die routing,=20 etc.

4) Information on extraction methods for C_comp, as well as=20 differential
treatments, can be found in the IBIS=20 Cookbook:

http://www.eda.org/ibis/cookbook/cookbook-v4.pdf

In= =20 addition, several presentations on C_comp issues are available in the
IB= IS=20 Summit=20 archive:

http://www.eda.org/ibis/summits/index-bytitle.htm

To= =20 address your concern, I would not say that IBIS per se is not
properly= =20 addressing high-frequency effects.    However, C_comp=20 in
traditional table-driven IBIS is a single value.  Capacitance fo= r=20 a
buffer is frequency- and voltage-dependent.  Therefore, the metho= d=20 of
extraction and the frequency at which the extracted value applies=20 are
critical when correlating the resulting IBIS model.  In the cas= e=20 you
describe, I would check to make sure that the C_comp value was=20 not
extracted at a frequency below 400 MHz.

A more comprehensive= =20 treatment of buffer capacitance is possible using
advanced IBIS techniqu= es,=20 including multi-lingual methods (IBIS 4.1,
4.2).

I hope this=20 helps!

- Michael Mirmak
 Intel Corp.
 Chair, EIA IBI= S=20 Open Forum


-----Original Message-----
From:=20 owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org]= On=20 Behalf Of Chitiz Mathema
Sent: Friday, August 24, 2007 4:31 PM
To:=20 ibis-users@server.eda.org
Subject: [IBIS-Users] IBIS question on=20 C_comp

Hello,

I have some questions about C_Comp parameter in= IBIS=20 models. I am trying

to resolve some issues for IBIS models of high= =20 frequency differential
output buffers.
I am trying to compare my SPI= CE=20 model transient simulations with the
IBIS model I generated for a=20 differential output buffer. At low
frequencies (eg ~ 100MHz), the SPICE= and=20 IBIS model output simulation
waveforms correlate closely. But at higher= =20 frequencies (>400MHz), the
SPICE and IBIS model simulations don't ma= tch=20 as well. I am trying to see

if the mismatch is due to the C_comp=20 parameter, or if this is just a
limitation of IBIS models not being abl= e to=20 capture high frequency
effects.

1. How IBIS simulators use the C_= comp=20 parameter during simulations?
2. Don't the V-T tables and ramp informati= on=20 already take into account
the effect of C_comp?
3. What does the C_c= omp=20 parameter exactly represent?
-should it include die routes, pad capacita= nce,=20 etc?
4. How should it be measured?
5. Should C_comp be measured in a= =20 special manner for differential
buffers like LVDS buffers?

I wou= ld=20 appreciate your response.

Thank you,
-Chitiz Mathema
Cypress= =20 Semiconductor




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This message has been scanned for viruses and
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believed to be clean. - ------_=_NextPart_002_01C7E93A.72B812C7-- - ------_=_NextPart_001_01C7E93A.72B812C7 Content-Type: message/rfc822 Content-Transfer-Encoding: 7bit Received: from mucse305.eu.infineon.com ([172.23.30.5]) by mucse306.eu.infineon.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.1830); Fri, 9 Feb 2007 17:55:11 +0100 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----_=_NextPart_003_01C74C6B.0F954180" Received: from appmail1.eu.infineon.com ([172.23.30.11]) by mucse305.eu.infineon.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.1830); Fri, 9 Feb 2007 17:55:11 +0100 Received: from mucse315.eu.infineon.com ([172.23.30.15]) by appmail1.eu.infineon.com with Microsoft SMTPSVC(6.0.3790.1830); Fri, 9 Feb 2007 17:55:10 +0100 Received: from smtp2.infineon.com ([172.28.181.199]) by mucse315.eu.infineon.com with InterScan Message Security Suite; Fri, 09 Feb 2007 17:55:09 +0100 Received: from agp.stanford.edu ([171.67.73.10]) by smtp2.infineon.com with ESMTP; 09 Feb 2007 17:58:38 +0100 Received: from cis.stanford.edu ([171.64.100.178]) by agp.stanford.edu with esmtp (Exim 4.43) id 1HFYsb-00015T-WD; Fri, 09 Feb 2007 08:45:46 -0800 Received: from server.eda-stds.org (eda-stds.ORG [171.64.101.101]) by cis.Stanford.EDU (Postfix) with ESMTP id 9B01F13DA7; Fri, 9 Feb 2007 08:45:38 -0800 (PST) Received: from server.eda-stds.org (localhost [127.0.0.1]) by server.eda-stds.org (8.12.10/8.12.0.Beta7) with ESMTP id l19GiZYS020870; Fri, 9 Feb 2007 08:44:35 -0800 (PST) Received: (from majordom@localhost) by server.eda-stds.org (8.12.10/8.12.10/Submit) id l19GiZd3020869; Fri, 9 Feb 2007 08:44:35 -0800 (PST) Content-class: urn:content-classes:message Return-Path: X-MIMEOLE: Produced By Microsoft Exchange V6.5 X-OriginalArrivalTime: 09 Feb 2007 16:44:00.0395 (UTC) FILETIME=[7FDF0DB0:01C74C69] X-SBRS: None X-Spam-Status: No, No X-Authentication-Warning: server.eda-stds.org: majordom set sender to owner-ibis-users@eda.org using -f X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AgAAAAc2zEWrQ0kKh2dsb2JhbACNWHsBAQEIDiqRGQEBAQ Subject: [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Date: Fri, 9 Feb 2007 18:43:58 +0200 Message-ID: X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Thread-topic: Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis) Thread-index: AcdMaX6buXIMgsT0Rf60/ZpqCELv0Q== From: Sender: To: This is a multi-part message in MIME format. - ------_=_NextPart_003_01C74C6B.0F954180 Content-Type: multipart/alternative; boundary="----_=_NextPart_004_01C74C6B.0F954180" - ------_=_NextPart_004_01C74C6B.0F954180 Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Hi experts, for long time I was hoping that I will never have to do it, but now, with D= DR4 (or NMT) knocking on the door it is finally on my schedule - IBIS model= s for differential I/O buffers. I have to say that I have read all possible documents (or at least I think = so) available on Internet (IBIS Summits, Macro Modeling Subcommittee, etc..= ), I have contacted a few people to discuss what they have actually done, I= have done the "homework" by experimenting with *-AMS Macro Library (one ye= ar later, but still), and so I would like here to share with you one summar= y on possibilities to create either IBIS models for differential buffers (w= / or w/o pre-/de-emphasis) or to create setups for simulation of these buff= er. Also, in this my "analysis", I would have some questions, so if somebod= y knows the answers, please just write me. Disclaimer: I am perfectly aware that there is a possibility that I have, perhaps, wro= te something wrong or stupid (I apologize in advance), but I am ready to ta= ke this risk, since I think that one of the purposes of this forum is discu= ssing all possible (IBIS related) topics. Also, if I have forgotten to ment= ion some work or author that is not done on purpose, but simply because of = my limited capabilities. Main question: I know that it is impossible to get one general answer on this (but still, = therefore I have done a whole analysis): What is mainstream solution/method= - what is the setup that are most customers looking for?=20 I am asking this simply, because I wouldn't like to support every possible = existing setup, but just to concentrate on one or two. In this summary, I have tried to list all kind of models/methods, starting = with (according to me) most simple and than slowly increasing complexity - = also I would like to distinguish between models of Differential buffers wit= hout Pre/De-emphasis and models of Differential buffers with Pre/De-emphasi= s. Differential Buffers w/o Pre/De-emphasis=20 1. "Traditional" IBIS modeling - treats differential buffers as two indepen= dent [Model]s driven by a stimulus and its complement=20 Method described (for example) by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf Advantages: - - simple setup and usage Disadvantages: - - not describing the coupling effects between pads - - causes DC shifts in the signal level 2. Method described by - - A. Tambone (Semiconductor Business News 2000) - no link found=20 - - http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z - - http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf - - http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf Advantages: - - relatively "smooth" and easy flow for understanding of IBIS extraction; - - relatively easy to adapt existing s2ibis2 or s2ibis3 flow; Disadvantages: - - LVDS IBIS models are accurate only when same VDDQ model was generated wit= h is used - Changing VDDQ leads to very inaccurate results; - - LVDS IBIS models assume constant Vcm - Must generate multiple models for = different values of vcm to obtain consistent accuracy driving different loa= ds and topologies; - - Device asymmetry will affect accuracy of model - Model generated for both= pads assumes perfect driver symmetry - Etch lengths of nets in differentia= l pair matched; 3. Improved IBIS modeling approach (using only v3.2 keywords) Method described by: - - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf - - http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf Advantages: - - describes DC currents of a differential buffer completely and accurately - - DC levels of the signals are correct under all loading conditions Disadvantages: - - pretty complicated procedure for extraction of model (at least for me) - - relatively big effort needed to automate the procedure - - need to make some guesses for picking up the 'best" value for C_comp Questions: Q1: on Page 38 and Page 39, in section "4.6.3 Separating the On-die Termination= I-V Tables" of IBIS Modeling Cookbook (IBIS Open Forum) - above mentioned = http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf -is written: "The procedure for this is similar to the corresponding subtraction procedu= re used for single-ended drivers. The I-V characteristics of the driver must be obtained twice, once in the drivi= ng mode and once in the 3-stated (high impedance) mode, and the 3-stated I-V table data must be substracted from t= he driving I-V table data. The only added complexity in this procedure for differential drivers is that the sub= traction is done after the common mode I-V tables have been extracted from the raw I-V surface data." On what is exactly meant by "The only added complexity in this procedure for differential drivers is that the sub= traction is done after the common mode I-V tables have been extracted from the raw I-V surface data." . What is th= e difference comparing to procedures that are done with s2ibis2 or s2ibis3,= since there is well done substracting of 3-stated I-V tables from driving = I-V tables? Q2: is there some IBIS file available that is created with exactly this procedu= re? Can somebody send me such file? Q3: are there any public available tools (something like s2ibis2 or s2ibis3) th= at would support extraction of IBIS models described with this model? (Hereby I don't mean on HSpice, Matlab and Pearl scripts provided in http:/= /www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf) Differential Buffers w/ Pre/De-emphasis=20 1. "Traditional" IBIS modeling - Model the building blocks of the buffer wi= th independent [Model]s and tell the user to wire them up treats differential buffers as four independent [Model]s (2 Main, 2 boosts= ) driven by a stimulus and its complement=20 Disadvantage: - - This approach was used initially for many models but required manual edit= ing of files and/or simulation schematics 2. [Driver Shedule] Method for Pre-emphasis Buffer modeling=20 http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basically describe= s 2 methods: V-I Through Transient simulation and [Driver Shedule]) http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf Advantage (of V-I Through Transient simulation method): - - relatively simple method Disadvantage (of V-I Through Transient simulation method): - - Non-monotonic wave forms (For some EDA tools) - - Single clock frequency operation (Changing the frequency needs remodeling) Advantage (of [Driver Schedule] Method): - - Changing the frequency doesn't need remodeling - - Eliminates the need for connecting two separate [Model]s by hand in the - - Eliminates the need for manually connecting [Model]s to make a complete b= uffer schematics, one for the Main and one for the Boost portion of the buf= fer - - Fewer transistor level (SPICE) models will need to be released to custome= rs - - Uses no more than IBIS v3.2 syntax - - Useful for tools not supporting the *-AMS extensions of IBIS - Extends th= e life of legacy IBIS before requiring the IBIS v4.1 language extensions - - Reasonably good correlation with transistor level model Disadvantage (of [Driver Schedule] Method): - - Changing the frequency need changing of Rise_on, Rise_off, Fall_on and Fa= ll_off times. Since legacy IBIS does not have provisions for clocked buffer= s, this model doesn't have a clock input, consequently the delay parameter is "hard coded= " and will need to be changed manually in the IBIS file for every clock fre= quency and simulation corner - - The [Driver Schedule] delay parameters do not have typ., min., max. corne= rs Obtaining separate [Model] data for the Main and Boost buffers may still r= equire the editing of the SPICE netlist - - There are a few questions around proper handling of C_comp 3. IBIS modeling using v4.1 and v4.2 features (e.g. [External Circuit]) Advantage: - - flexibility (I guess so) Disadvantage: - - not all EDA tools support all features - - relatively complicated setup Question: Q4: - - can somebody send me an example of IBIS model that is using v4.1 and v4.2= features for describing Differential Buffers with Pre-/De-emphasis? 4. *-AMS Buffer Models Using IBIS v3.2 Data (although it can be applied on = Differential Buffers w/o Pre/De-emphasis as well) Method described by (and many others): http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf Advantage: - - according to my opinion absolutely the most "coolest" method (as mentione= d on the beginning, I have done the homework and really experimented with M= acro Model Library created by Arpad & Co. - please see my questions and com= ments bellow) for SI simulation - - very flexible method, gives you possibilities to do literally whatever yo= u want (the only limitation are your EDA tools - in my case HSpice 2006.09 = and it's Verilog-A interface) Disadvantage: - - "where" is IBIS here? (not really a disadvantage, but more like a questio= n) - - need to create IBIS models first and then to extract data in proper forma= t (later to be read-out by Verilog-A) - - relatively high effort to create a proper setup and flow - - one needs to know (or at least understand) all :IBIS, HSpice and *-AMS - = (at least in this case that wasn't my problem :-))) Questions: Q5: is there a possibility to make HSpice more verbose when debugging it's Veri= log-A interface?=20 In sum I spent around half 0of the day just on debugging why Verilog-A "won= 't" compile Verilog code when including extracted IBIS data.=20 Btw., please find in the attachment slightly changed Perl script (file nam= e: "ibis2ams.pl") with which one can REALLY do something used in conjunctio= n with for example http://www.vhdl.org/pub/ibis/macromodel_wip/template_lib= /Verilog-A_PreDe- - original script that is on http://www.vhdl.org/pub/ibis= /macromodel_wip/tools/IBIS-to-AMS_conversion_tool.zip can't be since origi= nal script generates array "Ipu_data", and pre/de-emphasis template (Verilo= g-A code) requires array named "I_pu" (and other similar discrepancies). U= ser just needs to change in the first row the path to his/her Perl executab= le. If IBIS model is generated with s2ibis2 user still needs to delete "S" = (from pS) from generated data file. Q6: practical question - it seems that Verilog-A doesn't support "NA" in input = array (e.g. "NA" in power or ground clamp data), although it is allowed in = IBIS. Is there intention to change this in Verilog-A standard? Or at least = how to handle "NA' in future? Q7: is it fair to say that calculation procedure (calculating/compensating of t= he I, V and C) used and described in "IBIS_macro_library.va" in module "IBI= S_IO" is expected to be used by all other simulators - I mean, is it "The A= lgorithm" (with some minor changes and vendor specialties) that every tool = that uses IBIS models should follow?=20 Many thanks to those that have read this mail until here, I am hoping on so= me your feedback! Best regards / Mit freundlichen Gr=FC=DFen / S po=B9tovanjem Radovan Vuleti=E6 Qimonda AG QAG PD PDE MEM MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 60088 1233 Fax (PC): +49 (0)89 60088 45 5305=20 E-mail: radovan.vuletic@qimonda.com <>=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_004_01C74C6B.0F954180 Content-Type: text/html; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable [IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I= /O Buffers (with and without Pre-/De-Emphasis)

Hi experts,

for long time I was hoping that I will never have to do i= t, but now, with DDR4 (or NMT) knocking on the door it is finally on my sch= edule - IBIS models for differential I/O buffers.

I have to say that I have read all possible documents (or= at least I think so) available on Internet (IBIS Summits, Macro Modeling S= ubcommittee, etc..), I have contacted a few people to discuss what they hav= e actually done, I have done the "homework" by experimenting with= *-AMS Macro Library (one year later, but still), and so I would like here = to share with you one summary on possibilities to create either IBIS models= for differential buffers (w/ or w/o pre-/de-emphasis) or to create setups = for simulation of these buffer. Also, in this my "analysis", I wo= uld have some questions, so if somebody knows the answers, please just writ= e me.

Disclaimer:
I am perfectly aware that there is a possibility that I = have, perhaps,  wrote something wrong or stupid (I apologize in advanc= e), but I am ready to take this risk, since I think that one of the purpose= s of this forum is discussing all possible (IBIS related) topics. Also, if = I have forgotten to mention some work or author that is not done on purpose= , but simply because of my limited capabilities.

Main question:
I know that it is impossible to get one general answer o= n this (but still, therefore I have done a whole analysis): What is mainstr= eam solution/method - what is the setup that are most customers looking for= ?

I am asking this simply, because I wouldn't like to suppo= rt every possible existing setup, but just to concentrate on one or two.

In this summary, I have tried to list all kind of models/= methods, starting with (according to me) most simple and than slowly increa= sing complexity - also I would like to distinguish between models of Differ= ential buffers without Pre/De-emphasis and models of Differential buffers w= ith Pre/De-emphasis.

Differential Buffers w/o Pre/De-emphasis

1. "Traditional" IBIS modeling - treats differe= ntial buffers as two independent [Model]s driven by a stimulus and its comp= lement

Method described (for example) by:
- http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf
- http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf

Advantages:
- simple setup and usage

Disadvantages:
- not describing the coupling effects between pads
- causes DC shifts in the signal level


2. Method described by
- A. Tambone (Semiconductor Business News 2000) - no lin= k found
- http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z
- http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf
- http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf

Advantages:
- relatively "smooth" and easy flow for unders= tanding of IBIS extraction;
- relatively easy to adapt existing s2ibis2 or s2ibis3 f= low;

Disadvantages:
- LVDS IBIS models are accurate only when same VDDQ mode= l was generated with is used - Changing VDDQ leads to very inaccurate resul= ts;

- LVDS IBIS models assume constant Vcm - Must generate mu= ltiple models for different values of vcm to obtain consistent accuracy dri= ving different loads and topologies;

- Device asymmetry will affect accuracy of model - Model = generated for both pads assumes perfect driver symmetry - Etch lengths of n= ets in differential pair matched;

3. Improved IBIS modeling approach (using only v3.2 keywo= rds)
Method described by:
- http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf
- http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf
- http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf

Advantages:
- describes DC currents of a differential buffer complet= ely and accurately
- DC levels of the signals are correct under all loading= conditions

Disadvantages:
- pretty complicated procedure for extraction of model (= at least for me)
- relatively big effort needed to automate the procedure=
- need to make some guesses for picking up the 'best&quo= t; value for C_comp

Questions:
Q1:
on Page 38 and Page 39, in section "4.6.3 Separatin= g the On-die Termination I-V Tables" of IBIS Modeling Cookbook (IBIS O= pen Forum) - above mentioned http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf -is written:

"The procedure for this is similar to the correspond= ing subtraction procedure used for single-ended drivers. The
I-V characteristics of the driver must be obtained twice= , once in the driving mode and once in the 3-stated (high
impedance) mode, and the 3-stated I-V table data must be= substracted from the driving I-V table data. The only
added complexity in this procedure for differential driv= ers is that the subtraction is done after the common mode
I-V tables have been extracted from the raw I-V surface = data."

On what is exactly meant by "The only
added complexity in this procedure for differential driv= ers is that the subtraction is done after the common mode
I-V tables have been extracted from the raw I-V surface = data." . What is the difference comparing to procedures that are done = with s2ibis2 or s2ibis3, since there is well done substracting of 3-stated = I-V tables from driving I-V tables?

Q2:
is there some IBIS file available that is created with e= xactly this procedure? Can somebody send me such file?

Q3:
are there any public available tools (something like s2i= bis2 or s2ibis3) that would support extraction of IBIS models described wit= h this model?

(Hereby I don't mean on HSpice, Matlab and Pearl scripts = provided in http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf)


Differential Buffers w/ Pre/De-emphasis

1. "Traditional" IBIS modeling - Model the buil= ding blocks of the buffer with independent [Model]s and tell the user to wi= re them up

treats differential buffers as four independent [Model]s&= nbsp; (2 Main, 2 boosts) driven by a stimulus and its complement

Disadvantage:
- This approach was used initially for many models but r= equired manual editing of files and/or simulation schematics


2. [Driver Shedule] Method for Pre-emphasis Buffer modeli= ng

http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basic= ally describes 2 methods: V-I Through Transient simulation and [Driver Shed= ule])

http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf

Advantage (of  V-I Through Transient simulation meth= od):
- relatively simple method

Disadvantage (of  V-I Through Transient simulation m= ethod):
- Non-monotonic wave forms (For some EDA tools)
- Single clock frequency operation (Changing the frequen= cy needs remodeling)

Advantage (of [Driver Schedule] Method):
- Changing the frequency doesn't need remodeling
- Eliminates the need for connecting two separate [Model= ]s by hand in the
- Eliminates the need for manually connecting [Model]s t= o make a complete buffer schematics, one for the Main and one for the Boost= portion of the buffer

- Fewer transistor level (SPICE) models will need to be r= eleased to customers
- Uses no more than IBIS v3.2 syntax
- Useful for tools not supporting the *-AMS extensions o= f IBIS - Extends the life of legacy IBIS before requiring the IBIS v4.1 lan= guage extensions

- Reasonably good correlation with transistor level model=

Disadvantage (of [Driver Schedule] Method):
- Changing the frequency need changing of Rise_on, Rise_= off, Fall_on and Fall_off times. Since legacy IBIS does not have provisions= for clocked buffers, this model

doesn't have a clock input, consequently the delay parame= ter is "hard coded" and will need to be changed manually in the I= BIS file for every clock frequency and

simulation corner
- The [Driver Schedule] delay parameters do not have typ= ., min., max. corners
 Obtaining separate [Model] data for the Main and B= oost buffers may still require the editing of the SPICE netlist
- There are a few questions around proper handling of C_= comp

3. IBIS modeling using v4.1 and v4.2 features (e.g. [Exte= rnal Circuit])

Advantage:
- flexibility (I guess so)

Disadvantage:
- not all EDA tools support all features
- relatively complicated setup

Question:
Q4:
- can somebody send me an example of IBIS model that is = using v4.1 and v4.2 features for describing Differential Buffers with Pre-/= De-emphasis?

4. *-AMS Buffer Models Using IBIS v3.2 Data (although it = can be applied on Differential Buffers w/o Pre/De-emphasis  as well)

Method described by (and many others):
http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf
http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf
http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf
http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf
http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf

Advantage:
- according to my opinion absolutely the most "cool= est" method (as mentioned on the beginning, I have done the homework a= nd really experimented with Macro Model Library created by Arpad & Co. = - - please see my questions and comments bellow) for SI simulation

- very flexible method, gives you possibilities to do lit= erally whatever you want (the only limitation are your EDA tools - in my ca= se HSpice 2006.09 and it's Verilog-A interface)

Disadvantage:
- "where" is IBIS here? (not really a disadvan= tage, but more like a question)
- need to create IBIS models first and then to extract d= ata in proper format (later to be read-out by Verilog-A)
- relatively high effort to create a proper setup and fl= ow
- one needs to know (or at least understand) all :IBIS, = HSpice and *-AMS - (at least in this case that wasn't my problem :-)))

Questions:
Q5:
is there a possibility to make HSpice more verbose when = debugging it's Verilog-A interface?
In sum I spent around half 0of the day just on debugging= why Verilog-A "won't" compile Verilog code when including extrac= ted IBIS data.

Btw., please find in the attachment slightly changed Perl= script  (file name: "ibis2ams.pl") with which one can REALL= Y do something used in conjunction with for example http://www.v= hdl.org/pub/ibis/macromodel_wip/template_lib/Verilog-A_PreDe- - origina= l script that is on http://www.vhdl.org/pub/ibis/macromo= del_wip/tools/IBIS-to-AMS_conversion_tool.zip can't be  since orig= inal script generates array "Ipu_data", and pre/de-emphasis templ= ate (Verilog-A code) requires array named  "I_pu" (and other= similar discrepancies). User just needs to change in the first row the pat= h to his/her Perl executable. If IBIS model is generated with s2ibis2 user = still needs to delete "S" (from pS) from generated data file.

Q6:
practical question - it seems that Verilog-A doesn't sup= port "NA" in input array (e.g. "NA" in power or ground = clamp data), although it is allowed in IBIS. Is there intention to change t= his in Verilog-A standard? Or at least how to handle "NA' in future?

Q7:
is it fair to say that calculation procedure (calculatin= g/compensating of the I, V and C) used and described in "IBIS_macro_li= brary.va" in module "IBIS_IO" is expected to be used by all = other simulators - I mean, is it "The Algorithm" (with some minor= changes and vendor specialties) that every tool that uses IBIS models shou= ld follow?


Many thanks to those that have read this mail until here,= I am hoping on some your feedback!


Best regards / Mit freundlichen Gr=FC=DFen / S po=B9tovan= jem
Radovan Vuleti=E6

Qimonda AG
QAG PD PDE MEM
MUC/10.2.236 AP 3
Am Campeon 1-12
D-85579 Neuebiberg

Phone:          += 49 (0)89 60088 1233
Fax (PC):       +49 (0)89 = 60088 45 5305

E-mail: radovan.vuletic@qimonda.com
 <<ibis2ams.pl>>

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http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 29 Aug 2007 16:11:28 -0700 From: Bob Ross Subject: [IBIS-Users] Asian IBIS Summit (China) - Agenda All: This message is earlier than normal, but the meeting Agenda is fixed. We have significant signup already, and this is sent mostly for information for the sponsors and Asian community to continue registering. Please provide: Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Lance Wang, IO Methology, Inc. lwang@iometh.com SIGNUP DEADLINE: September 4, 2007 Bob Ross Teraspeed Consulting Group Lance Wang IO Methodology, Inc. - ------------------------------------------------------------------ A S I A N I B I S S U M M I T I N F O R M A T I O N Time/Date: 8:15 - 17:30, Tuesday September 11, 2007 Location: Park Plaza Hotel Beijing 25 Zhichum Road Haiden District Beijing 100083 CHINA Tel: + 86-10-82356699 E-mail: beijing@parkplaza-bj.com Room: HongYun Room, 3rd floot Check Hotel Meeting Listing Sponsors: Huawei Technologies (Primary) Agilent Technologies Ansoft Cadence Design Systems, Intel Corporation Mentor Graphics Corporation, Signal Integrity Software (SiSoft) Sigrity Synopsys. ZTE Corporation - ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 8:15 REFRESHMENTS & SIGN IN - Vendor Tables Open 9:00 Welcome and Keynote Comments - Jiang, XiangZhong (Huawei Technologies, China) - Mirmak, Michael (Chair., EIA IBIS Open Forum, Intel Corporation, USA) - Invited Chinese Representative Remarks 9:30 Wang Algebra and Interconnects Ross, Bob (Teraspeed Consulting Group, USA) 9:50 IBIS-ATM Update: SerDes Modeling in IBIS Westerhoff, Todd (Signal Integrity Software (SiSoft), USA) 10:15 BREAK (Refreshments) 10:30 Serial Link Analysis and PLL Model Huang, ChunXing (Huawei Technologies, China) 11:00 A Review of Existing Multi-Gbps Serial Channel Analysis Methods and the Evolution of the Proposed ATM Algorithmic Modeling Standard Dodd, Ian*, Ward, Richard** and Gupta, Sanjeev* (*Agilent Technologies, USA and **Texas Instruments, USA) 11:30 An Overview of High-Speed Serial Bus Validation Techniques Muranyi, Arpad and Dmitriev-Zdorov, Vladimir (Mentor Graphics Corporation, USA) 12:00 FREE BUFFET LUNCH (Hosted by Sponsors) - Vendor Tables - Press Luncheon for IBIS Officers and Sponsors 13:30 Modeling and Simulation for Multi-Gigabit Interconnect System Zhu, ShunLin, Hu, WeiDong, and Chen, SongRui (ZTE Corporation, China) 14:00 Power Deliver System Design Automation Xu, Tao (Sigrity, China) 14:30 IBIS 4.2/AMS for DDR2 Timing Analysis Guan, Tao (Huawei Technologies, China) 15:00 Validation for IBIS Models Wang, Lance*, Zhang, XinJun**, and Yan, Benny** (IO Methodology, *USA, **China) 15:25 IBIS Algorithm Including Reactive Loads Chen, XueFeng (Synopsys, China) 15:40 BREAK (Refreshments) 15:55 Understanding and Using ICM Models Meng, YuBao (Cadence Design Systems, China) 16:25 Using S-Parameters for High Performance Simulation Li, BaoLong (Ansoft, China) 16:55 Issues Combining Buffer and Interconnect Model Mirmak, Michael (Intel Corporation, USA) 17:15 SerDes Modeling: IBIS-AMI Evaluation Toolkit Westerhoff, Todd (Signal Integrity Software (SiSoft), USA) 17:20 IBIS AMI Model Developers Toolbox Shah, Hemant (Cadence Design Systems, USA) 17:25 Concluding Items 17:30 END OF IBIS SUMMIT MEETING - Final Vendor Tables and Teardown - ------------------------------------------------------------------ - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 30 Aug 2007 17:48:08 -0400 From: "Todd Westerhoff" Subject: [IBIS-Users] SerDes modeling - SiSoft IBIS-AMI Toolkit version 1.00 is available This is a multi-part message in MIME format. - ------=_NextPart_000_00BB_01C7EB2D.ED4C8860 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit As I hope you're aware, the IBIS Advanced Technology Modeling (IBIS-ATM) task group has been working to define a modeling standard for Serdes Rx/Tx models that will provide interoperability across EDA tools and IP vendor models. This group has been working on a proposal for modeling SerDes equalization and clock recovery behavior using "executable" models that conform to a standardized calling interface. The proposal addresses how models are loaded and executed, how waveform data is passed to/from the model and how model-specific control settings are managed. These models are known as IBIS Algorithmic Modeling Interface (IBIS-AMI) models. You can find information on the task group's efforts on-line: http://www.eda-stds.org/pub/ibis/macromodel_wip/ The task group approved a draft version of the proposal for "prototype implementation" this past May. Sample models and EDA integrations were developed, and we've demonstrated that the sample models are operable across different EDA platforms. SiSoft is providing a free "IBIS-AMI Evaluation Toolkit" for public evaluation. Release 1.00 of the toolkit has been posted in the "Work Archive" section of: http://www.eda-stds.org/pub/ibis/macromodel_wip/ The toolkit is posted as a .zip file that contains the IBIS_AMI_test program that allows AMI models to be run from the command line, a sample 4-tap Tx model (both executable and source code), along with sample data and basic documentation. Executables are provided for both Windows and Linux platforms. You can use this toolkit to perform analyses with the channel data provided, or you can substitute data for your own channel design. Please note that the input/output data for the model conforms to the IBIS-AMI proposal; some programming and scripting skill will be needed if you plan to adapt the kit for your own design use. The toolkit is provided free by SiSoft; you are welcome to use it as you wish, subject to the conditions laid out in the "license.txt" file. We have established the mailer ibis-ami-toolkit@freelists.org for discussions about SiSoft's toolkit and toolkits to follow from other EDA vendors. You can join the ibis-ami-toolkit mailer by sending an email with "subscribe" in the subject line to ibis-ami-toolkit-subscribe@freelists.org . You can also join the discussion group through the following URL: http://www.freelists.org/list/ibis-ami-toolkit Future releases of SiSoft's toolkit will be announced on the ibis-ami-toolkit mailer. Any comments are welcome and greatly appreciated; we will gauge updates to the kit based on the feedback we receive. Thanks for your interest, and happy modeling! Todd. Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@sisoft.com www.sisoft.com - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_00BB_01C7EB2D.ED4C8860 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

As I hope you’re aware, the IBIS Advanced Technolo= gy Modeling (IBIS-ATM) task group has been working to define a modeling standa= rd for Serdes Rx/Tx models that will provide interoperability across EDA tools= and IP vendor models.  This group has been working on a proposal for model= ing SerDes equalization and clock recovery behavior using “executableR= 21; models that conform to a standardized calling interface.  The proposal addresses how models are loaded and executed, how waveform data is passed t= o/from the model and how model-specific control settings are managed.

These models are known as IBIS Algorithmic Modeling Interface (IBIS-AMI) models.

 

You can find information on the task group’s effor= ts on-line:

 

http://www.eda-stds.org/pub/ibis/macromodel_wip/=

 

The task group approved a draft version of the proposal = for “prototype implementation” this past May.  Sample models and EDA integratio= ns were developed, and we’ve demonstrated that the sample models are operable across different EDA platforms.

 

SiSoft is providing a free “IBIS-AMI Evaluation Toolkit” for public evaluation.  Release 1.00 of the toolkit has been posted in the “Work Archive” section of:=

 

http://www.eda-stds.org/pub/ibis/macromodel_wip/=

 

The toolkit is posted as a .zip file that contains the IBIS_AMI_test program that allows AMI models to be run from the command lin= e, a sample 4-tap Tx model (both executable and source code), along with sample = data and basic documentation.  Executables are provided for both Windows and Linux platforms.  You can use this toolkit to perform analyses with the channel data provided, or you can substitute data for your own channel desi= gn.  Please note that the input/output data for the model conforms to the IBIS-AMI proposal; some programming and scripting skill will be needed if you plan to adapt the kit for your own design use.

 

The toolkit is provided free by SiSoft; you are welcome = to use it as you wish, subject to the conditions laid out in the “license.txt” file. 

 

We have established the mailer ibis-ami-toolkit@freelists.o= rg for discussions about SiSoft’s toolkit and toolkits to follow from ot= her EDA vendors.  You can join the ibis-ami-toolkit mailer by sending an e= mail with "subscribe" in the subject line to ibis-ami-toolkit-s= ubscribe@freelists.org .  You can also join the discussion group through the following URL:

 

http://www.freelists.org/list/ibis-ami-toolkit

 

Future releases of SiSoft’s toolkit will be announ= ced on the ibis-ami-toolkit mailer.   Any comments are welcome and greatly appreciated; we will gauge updates to the kit based on the feedback= we receive.

 

Thanks for your interest, and happy modeling!=

 

Todd.


Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite= 250
Maynard, MA 01754
(978) 461-0449 x24
twesterh@sisoft.com
www.sisoft.com

 


--=20
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believed to be clean. - ------=_NextPart_000_00BB_01C7EB2D.ED4C8860-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 7 Sep 2007 06:56:38 -0700 From: "Mirmak, Michael" Subject: [IBIS-Users] Agenda, Asian IBIS Summit (Japan), September 14, 2007 - Agenda All, We are pleased to announce the agenda for the Asian IBIS Summit (Japan) meeting, to be held in Tokyo on September 14. Those interested in attending are invited to register using the form and addresses below. We look forward to a successful event. Takeshi Watanabe NEC Electronics Corp. Michael Mirmak Intel Corp. - ------------------------------------------------------------------ S U M M I T I N F O R M A T I O N Time/Date: 8:30 - 16:00, Friday September 14, 2007 Location: JEITA Headquarters 3rd Fl., Mitsui Sumitomo Kaijo Bldg. Annex 11, Kanda Surugadai 3-chome, Chiyoda-ku, Tokyo 101-0062 JAPAN http://www.jeita.or.jp/english/about/location/index.htm Registration: FREE, send to both addresses below: Name: E-mail address: Company: Telephone: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Takeshi Watanabe, NEC Electronics Corp. takeshi.watanabe@necel.com Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) EIA IBIS Open Forum Co-Sponsors: (in alphabetical order) Agilent Technologies ATE Service Corporation (Sigrity) Cadence Design Systems Cybernet Systems IVIS (Signal Integrity Software (SiSoft)) Mentor Graphics Corporation Zuken - ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 8:30 REFRESHMENTS & SIGN IN - Vendor Tables Open 9:00 Meeting Welcome Watanabe, Takashi (NEC Electronics Corp. and JEITA, Japan) Mirmak, Michael (Intel Corporation, USA) 9:10 JEITA EDA Activity Overview Watanabe, Takashi (NEC Electronics Corp. and JEITA, Japan) 9:25 IBIS Quality Activities Overview in JEITA EDA WG Kondo, Yasumasa (Toshiba, Japan) 9:50 Validation for IBIS Models Wang, Lance*, Zhang, XinJun**, and Yan, Benny** (IO Methodology, *USA, **China) [Presented by Wang, Lance (IO Methodology USA)] 10:20 IBIS Tree and Evolution Document Update Ross, Bob (Teraspeed Consulting Group, USA) 10:30 BREAK (Refreshments) 10:45 JEITA Activity, IBIS Guide for the Japanese Engineer Shoji, Kazuyoshi (Hitachi ULSI Systems, Japan) 11:10 Understanding and Using ICM Models Meng, YuBao (Cadence Design Systems, China) [Presented by Masuko, Yukio, Japan] 11:40 Study of the Interconnect Model Ikeda, Hiroaki (Japan Aviation Electronic Industries, Japan) 12:00 FREE BUFFET LUNCH (Hosted by Sponsors) 13:00 Issues Combining Buffer and Interconnect Models Mirmak, Michael (Intel Corporation, USA) 13:30 Power Delivery System Design Automation Xu, Tao (Sigrity, China) [Presented by Chitwood, Sam (Sigrity, USA)] 14:00 IBIS-ATM Update: SerDes Modeling in IBIS Westerhoff, Todd (Signal Integrity Software (SiSoft), USA 14:25 SerDes Modeling: IBIS-AMI Evaluation Toolkit Westerhoff, Todd (Signal Integrity Software (SiSoft), USA) 14:35 IBIS AMI Model Developers Toolbox Shah, Hemant (Cadence Design Systems, USA) [Presented by Masuko, Yukio, Japan] 14:45 BREAK (Refreshments) 15:00 A Review of Existing Multi-Gbps Serial Channel Analysis Methods and the Evolution of the Proposed ATM Algorithmic Modeling Standard Dodd, Ian*, Ward, Richard** and Gupta, Sanjeev* (*Agilent Technologies, USA and **Texas Instruments, USA) [Presented by Dodd, Ian, Agilent Technologies, USA) 15:30 An Overview of High-Speed Serial Bus Validation Techniques Muranyi, Arpad and Dmitriev-Zdorov, Vladimir (Mentor Graphics Corporation, USA) [Presented by Muranyi, Arpad, Mentor Graphics Corp., USA)] 16:00 Open Discussions 16:25 Concluding Items 16:30 END OF MEETING (POST-SUMMIT REFRESHMENTS) - ------------------------------------------------------------------ - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 18 Sep 2007 08:26:36 -0700 From: "Mirmak, Michael" Subject: [IBIS-Users] Asian IBIS Summit Presentations On-line! This is a multi-part message in MIME format. - ------_=_NextPart_001_01C7FA08.4C82B6B0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable The IBIS Summits in Beijing and Tokyo last week were a great success, and the IBIS Open Forum extends its thanks to the co-sponsors, participants and presenters.=20 The presentation material from both events is now available on-line, at the link below. Topics include serial-differential bus design, the IBIS-ATM algorithmic modeling toolkits, power delivery issues, application of Wang algebra to interconnects, and many others.=20=20 http://www.eda.org/ibis/summits/index-bydate.htm - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum http://www.eigroup.org/ibis/ http://www.eda.org/ibis/ - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C7FA08.4C82B6B0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Asian IBIS Summit Presentations On-line!

The IBIS Summits in Beijing and Tokyo last= week were a great success, and the IBIS Open Forum extends its thanks to t= he co-sponsors, participants and presenters.

The presentation material from both events= is now available on-line, at the link below.  Topics include serial-d= ifferential bus design, the IBIS-ATM algorithmic modeling toolkits, power d= elivery issues, application of Wang algebra to interconnects, and many othe= rs. 

        http://www.eda.org/ibis/summits/index-bydate.htm

- Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum
  http://www.eigroup.org/ibis/
  htt= p://www.eda.org/ibis/



--=20
This message has been scanned for viruses and
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believed to be clean. - ------_=_NextPart_001_01C7FA08.4C82B6B0-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 20 Sep 2007 02:09:11 -0700 (PDT) From: Ibis Model Subject: [IBIS-Users] Package Modeling for W-element - --0-686556029-1190279351=:50637 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi I'm just wondering if there are already keywords available in the IBIS v4.1 Specification to represent the package modeling for W-element model. From the IBIS Spec, I notice that there is the [Define Package Model] keyword; however, there aren’t any sub parameters that actually represent the frequency dependant element. I would be glad if someone can answer my concern on bringing this W-element package modeling in the IBIS file by using new keywords. The current [Define Package Model] only cater for Lumped RLC and Segmented RLC package modeling at the moment (please correct me if I’m wrong). So is there any plan that the IBIS open Forum will look into the W-element package modeling and add in extra keywords to support this? If yes, when will it be available? Looking forward for your reply. Appreciate your attention on this. Regards Timmy - --------------------------------- Pinpoint customers who are looking for what you sell. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --0-686556029-1190279351=:50637 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit
Hi
 
I'm just wondering if there are already keywords available in the IBIS v4.1 Specification to represent the package modeling for W-element model. From the IBIS Spec, I notice that there is the [Define Package Model] keyword; however, there aren’t any sub parameters that actually represent the frequency dependant element.
 
I would be glad if someone can answer my concern on bringing this W-element package modeling in the IBIS file by using new keywords. The current [Define Package Model] only cater for Lumped RLC and Segmented RLC package modeling at the moment (please correct me if I’m wrong). So is there any plan that the IBIS open Forum will look into the W-element package modeling and add in extra keywords to support this? If yes, when will it be available?  
 
Looking forward for your reply. Appreciate your attention on this.
 
Regards
Timmy   
 

Pinpoint customers who are looking for what you sell.
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This message has been scanned for viruses and
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believed to be clean. - --0-686556029-1190279351=:50637-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 20 Sep 2007 09:22:11 -0700 From: "Mirmak, Michael" Subject: RE: [IBIS-Users] Package Modeling for W-element This is a multi-part message in MIME format. - ------_=_NextPart_001_01C7FBA2.6504E191 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Timmy, =20 Thanks for your note. At present, neither IBIS 4.2 nor any earlier version support trace modeling using the W-element (the W-element is a proprietary format). =20 You are correct that the IBIS package model options under [Package], [Pin] and [Package Model]/[Define Package Model] include lumped and segmented RLC formats. A third option using matrices is also available under [Package Model]. We do recognize that all three capabilities in IBIS may not be appropriate for today's fast-edge-rate designs, particularly as the loss terms available are not frequency-dependent.=20=20 =20 At present, work is underway in the IBIS Open Forum to link the ICM specification under IBIS to describe packages. ICM (the IBIS Interconnect Modeling specification) is available now and defines an IBIS-like interface to interconnect data, including frequency-dependent RLGC matrices and S-parameter data using the Touchstone(R) format. Until ICM can be linked to a model directly under IBIS, users with access to both can link IBIS buffers and ICM package models within the system topology. =20 Support for ICM is growing in support in the industry, both in terms of model providers and EDA tool vendors. Check with your suppliers regarding support. The ICM specification and parser are available through the IBIS websites linked below. =20 Coincidentally, presentations on both the package modeling problem and the use of ICM were given at the recent IBIS Summits in Asia: http://www.eda.org/ibis/summits/index-bydate.htm. =20 I hope this helps! =20 - - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum http://www.eigroup.org/ibis/ http://www.eda.org/ibis/ ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Ibis Model Sent: Thursday, September 20, 2007 2:09 AM To: ibis-users@server.eda.org Subject: [IBIS-Users] Package Modeling for W-element Hi =20 I'm just wondering if there are already keywords available in the IBIS v4.1 Specification to represent the package modeling for W-element model. From the IBIS Spec, I notice that there is the [Define Package Model] keyword; however, there aren't any sub parameters that actually represent the frequency dependant element.=20 =20 I would be glad if someone can answer my concern on bringing this W-element package modeling in the IBIS file by using new keywords. The current [Define Package Model] only cater for Lumped RLC and Segmented RLC package modeling at the moment (please correct me if I'm wrong). So is there any plan that the IBIS open Forum will look into the W-element package modeling and add in extra keywords to support this? If yes, when will it be available?=20=20 =20 Looking forward for your reply. Appreciate your attention on this. =20 Regards Timmy=20=20=20 =20 ________________________________ Pinpoint customers who are looking for what you sell.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C7FBA2.6504E191 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Timmy,
 
Thanks for your note.  At present, neither IB= IS 4.2=20 nor any earlier version support trace modeling using the W-element (the=20 W-element is a proprietary format).
 
You are correct that the IBIS package model option= s under=20 [Package], [Pin] and [Package Model]/[Define Package Model] include lumped = and=20 segmented RLC formats.  A third option using matrices is also availabl= e=20 under [Package Model].  We do recognize that all three c= apabilities=20 in IBIS may not be appropriate for today's fast-edge-rate designs, particul= arly=20 as the loss terms available are not frequency-dependent. =20
 
At present, work is underway in the IBIS Open Foru= m=20 to link the ICM specification under IBIS to describe packages.  I= CM=20 (the IBIS Interconnect Modeling specification) is available now and defines= an=20 IBIS-like interface to interconnect data, including frequency-dependent RLG= C=20 matrices and S-parameter data using the Touchstone(R) format.  Until I= CM=20 can be linked to a model directly under IBIS, users with access to=20 both can link IBIS buffers and ICM package models within the syst= em=20 topology.
 
Support for ICM is growing in support in the indus= try, both=20 in terms of model providers and EDA tool vendors.  Check with=20 your suppliers regarding support.  The ICM specification and pars= er=20 are available through the IBIS websites linked below.
 
Coincidentally, presentations on both the package = modeling=20 problem and the use of ICM were given at the recent IBIS Summits in Asia: <= A=20 href=3D"http://www.eda.org/ibis/summits/index-bydate.htm">http://www.eda.or= g/ibis/summits/index-bydate.htm.
 
I hope this helps!
 
- Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum
  http://www.eigroup.org/ibis/
&nbs= p; http://www.eda.org/ibis/

From: owner-ibis-users@server.eda.org= =20 [mailto:owner-ibis-users@server.eda.org] On Behalf Of Ibis=20 Model
Sent: Thursday, September 20, 2007 2:09 AM
To:=20 ibis-users@server.eda.org
Subject: [IBIS-Users] Package Modeling = for=20 W-element

Hi
 
I'm just wondering= if=20 there are already keywords available in the IBIS v4.1 Specification to= =20 represent the package modeling for W-element model. From the IBIS Spec= , I=20 notice that there is the [Define Package Model] keyword; however, there are= n’t=20 any sub parameters that actually represent the frequency dependant ele= ment.=20
 
I would be glad if= =20 someone can answer my concern on bringing this W-element pac= kage=20 modeling in the IBIS file by using new keywords. The current [Define Packag= e=20 Model] only cater for Lumped RLC and Segmented RLC package modeling at the= =20 moment (please correct me if I’m wrong). So is there any plan that th= e IBIS open=20 Forum will look into the W-element package modeling and add in extra= =20 keywords to support this? If yes, when will it be available?  
 
Looking forward fo= r your=20 reply. Appreciate your attention on this.
 
Regards
Timmy   <= /o:p>
 

Pinpoint=20 customers who are looking for what you sell.
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This message ha= s=20 been scanned for viruses and
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This message has been scanned for viruses and
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believed to be clean. - ------_=_NextPart_001_01C7FBA2.6504E191-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 20 Sep 2007 14:57:07 -0500 From: "Dunbar, Tony" Subject: RE: [IBIS-Users] Package Modeling for W-element This is a multi-part message in MIME format. - ------_=_NextPart_001_01C7FBC0.6C9781B9 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Timmy, =20 I'm taking note of Michael's response in providing this response. =20 Depending on which simulator you are using, you may be able to use the IBIS v4.1 [External Circuit] keyword to accommodate your W Element package model. It all depends if the simulator supports that. Another alternative, again depending on the simulator tool, is to add the W Element as a 'black-box' separate entity in the overall circuit to be simulated. =20 Yet another approach I've used before, if your target simulator is a SPICE engine that supports IBIS models, is to write a SPICE .SUBCKT that includes both the W Element and the IBIS model. =20 Regards, Tony ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Ibis Model Sent: Thursday, September 20, 2007 4:09 AM To: ibis-users@server.eda.org Subject: [IBIS-Users] Package Modeling for W-element Hi =20 I'm just wondering if there are already keywords available in the IBIS v4.1 Specification to represent the package modeling for W-element model. From the IBIS Spec, I notice that there is the [Define Package Model] keyword; however, there aren't any sub parameters that actually represent the frequency dependant element.=20 =20 I would be glad if someone can answer my concern on bringing this W-element package modeling in the IBIS file by using new keywords. The current [Define Package Model] only cater for Lumped RLC and Segmented RLC package modeling at the moment (please correct me if I'm wrong). So is there any plan that the IBIS open Forum will look into the W-element package modeling and add in extra keywords to support this? If yes, when will it be available?=20=20 =20 Looking forward for your reply. Appreciate your attention on this. =20 Regards Timmy=20=20=20 =20 ________________________________ Pinpoint customers who are looking for what you sell.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C7FBC0.6C9781B9 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hi Timmy,
 
I'm taking note of Michael's response in providing this=20 response.
 
Depending on which simulator you are using, you may be able to use= the=20 IBIS v4.1 [External Circuit] keyword to accommodate your W Element package= =20 model. It all depends if the simulator supports that. Another alternative, = again=20 depending on the simulator tool, is to add the W Element as a 'black-box'= =20 separate entity in the overall circuit to be simulated.
 
Yet another approach I've used before, if your target simulator is= a=20 SPICE engine that supports IBIS models, is to write a SPICE .SUBCKT that=20 includes both the W Element and the IBIS model.
 
Regards,
Tony

From: owner-ibis-users@server.eda.org= =20 [mailto:owner-ibis-users@server.eda.org] On Behalf Of Ibis=20 Model
Sent: Thursday, September 20, 2007 4:09 AM
To:=20 ibis-users@server.eda.org
Subject: [IBIS-Users] Package Modeling = for=20 W-element

Hi
 
I'm just wondering= if=20 there are already keywords available in the IBIS v4.1 Specification to= =20 represent the package modeling for W-element model. From the IBIS Spec= , I=20 notice that there is the [Define Package Model] keyword; however, there are= n’t=20 any sub parameters that actually represent the frequency dependant ele= ment.=20
 
I would be glad if= =20 someone can answer my concern on bringing this W-element pac= kage=20 modeling in the IBIS file by using new keywords. The current [Define Packag= e=20 Model] only cater for Lumped RLC and Segmented RLC package modeling at the= =20 moment (please correct me if I’m wrong). So is there any plan that th= e IBIS open=20 Forum will look into the W-element package modeling and add in extra= =20 keywords to support this? If yes, when will it be available?  
 
Looking forward fo= r your=20 reply. Appreciate your attention on this.
 
Regards
Timmy   <= /o:p>
 

Pinpoint=20 customers who are looking for what you sell.
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This message ha= s=20 been scanned for viruses and
dangerous content by MailScanner, and is
be= lieved=20 to be clean.
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This message has been scanned for viruses and
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believed to be clean. - ------_=_NextPart_001_01C7FBC0.6C9781B9-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 21 Sep 2007 18:48:42 +0530 From: Amit KUMAR Subject: [IBIS-Users] Problem in developin NMOS Open Drain type IBIS Hello all, I am generating IBIS model(ver 4.2) for a circuit which is working in Open drain mode. I have included in the IBIS file one pulldown curve and 2 V-T waveforms (both with high fixture, one falling and one rising). Simulations show that the operating point for high input is different in case of original circuit and IBIS file. For low input it is the same. So when i give some Falling input at the input of model both the IBIS waveform and original waveform fall to the same voltage but at the start they are at different voltage. Infact i get operating point for high input half of the voltage which i should actually get.. Is their something tricky in modelling of Open Drain model ?? I have modelled a few IBIS models of output type and I/O type but never did i get such a problem. Thanks for your support Amit Kumar Design Engineer ST Microelectronics India - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 21 Sep 2007 10:32:31 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] Problem in developin NMOS Open Drain type IBIS Open drain models are not tricky at all. The output hi voltage is dependent on three things. Vdd, Rload and the off current of the open drain driver. Vdd is normally the power supply voltage. The resistor used in IBIS modeling is usually 50 Ohms and the current in an off FET is usually 0.00mA. So the off voltage is usually Vdd. Vout = Vdd - Ioff*50Ohms = Vdd - 0 = Vdd If you are getting a different value you are mostly likely not having the proper Vdd value, the off current is not zero or you have other currents in your model that are being summed with the FET's current in such a way that there is current flowing in the load causing an IR drop. I would check the power and ground clamp tables to see if they are contributing any current to the output. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 - -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Amit KUMAR Sent: Friday, September 21, 2007 6:19 AM To: ibis-users@server.eda.org Cc: amit kumar Subject: [IBIS-Users] Problem in developin NMOS Open Drain type IBIS Hello all, I am generating IBIS model(ver 4.2) for a circuit which is working in Open drain mode. I have included in the IBIS file one pulldown curve and 2 V-T waveforms (both with high fixture, one falling and one rising). Simulations show that the operating point for high input is different in case of original circuit and IBIS file. For low input it is the same. So when i give some Falling input at the input of model both the IBIS waveform and original waveform fall to the same voltage but at the start they are at different voltage. Infact i get operating point for high input half of the voltage which i should actually get.. Is their something tricky in modelling of Open Drain model ?? I have modelled a few IBIS models of output type and I/O type but never did i get such a problem. Thanks for your support Amit Kumar Design Engineer ST Microelectronics India - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #102 *************************