From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #120 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Thursday, August 28 2008 Volume 01 : Number 120 ---------------------------------------------------------------------- Date: Mon, 18 Aug 2008 19:21:13 +0530 From: Chetana Raghuwanshi Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence - --0__=EABBFE3ADFD860D28f9e8a93df938690918cEABBFE3ADFD860D2 Content-type: multipart/alternative; Boundary="1__=EABBFE3ADFD860D28f9e8a93df938690918cEABBFE3ADFD860D2" - --1__=EABBFE3ADFD860D28f9e8a93df938690918cEABBFE3ADFD860D2 Content-type: text/plain; charset=US-ASCII Content-transfer-encoding: quoted-printable Hi Sudarshan, You are right. My concern is IV VT mismatch error. How would it disappear by increasing the simulation time ? Best Regards Chetana - -------------------------------------------------------- Chetana Raghuwanshi CTO / Process & Library Technology NXP Semiconductors India NXP Block C, 4th Floor MFAR Manyata Tech Park Nagavara, Bangalore-560045 Tel : +91 80 4024 7072 - -------------------------------------------------------- =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 To "Chetana Raghuwanshi"=20=20=20=20=20= =20=20=20=20=20=20 =20=20= =20 "Sudarshan H N" cc ibis-users@server.eda.org,=20=20=20= =20=20=20 Sent by: ibis@server.eda.org=20=20=20=20=20= =20=20=20=20=20=20=20=20 Subject owner-ibis-users@server.e [IBIS-Users] Re: [IBIS] Different da.org PMOS and NMOS driver impedence=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 2008-08-18 06:43 PM=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Hello Chetana, You can use any of the 2 values for Rfixture to generate Vt curves. There is no rule that , your Rfixture should match to the PMOS or NMOS driver resistance. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any errors with respect to IV and Vt curve mismatch , just simulate for more time so that it will reach the saturation. Regards Sudarshan On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi < chetana.raghuwanshi@nxp.com> wrote: Hello Experts, One of my IO cell has a buffer with different PMOS and NMOS impedences. PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms. In this case what should be the value of Rfixture for calculating IV VT curves ? Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ? If I do rise/pullup and fall/pulldown simulations with different Rfixture values, is it acceptable ? Best Regards Chetana -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --1__=EABBFE3ADFD860D28f9e8a93df938690918cEABBFE3ADFD860D2 Content-type: text/html; charset=US-ASCII Content-Disposition: inline Content-transfer-encoding: quoted-printable

Hi Sudarshan,

You are right. My concern is IV VT mismatch error.
How would it disappear by increasing the simulation time ?

Best Regards
Chetana

- --------------------------------------------------------
Chetana Raghuwanshi
CTO / Process & Library Technology
NXP Semiconductors India
NXP Block C, 4th Floor
MFAR Manyata Tech Park
Nagavara, Bangalore-560045
Tel : +91 80 4024 7072
- --------------------------------------------------------
3D"Inactive"Sudarshan H N" <hn.sudarshan= @gmail.com>


    "Sudarshan H N" <hn.sudarshan@gmail.co= m>
    Sent by:

    owner-ibis-users@server.eda.org

    2008-08-18 06:43 PM

 =
3D""
To
3D""
"Chetana Raghuwanshi" <chetana.raghuwanshi@nx= p.com>
3D""
cc
3D""
ibis-users@server.eda.org, ibis@server.eda.org
3D""
Subject
3D""
[IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver imp= edence
3D""3D""

Hello Chetana,

You can use any of the 2 values for Rfixture to generate Vt curves. There i= s no rule that , your Rfixture should match to the PMOS or NMOS driver resi= stance. But you should always use one value to generate the one set of risi= ng and falling waveforms(experts, correct me if i am wrong). If you are see= ing any errors with respect to IV and Vt curve mismatch , just simulate fo= r more time so that it will reach the saturation.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi <<= /font>chetana.raghuwanshi@nxp.com= > wrote:

    Hello Experts,

    One of my IO cell has a buffer with different PMOS and NMOS impedences.
    PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms.
    In this case what should be the value of Rfixture for calculating IV VT cur= ves ?
    Would it be Rfixture1 for calculating pull down and falling waveforms and R= fixture2 for calculating pull up and rising waveforms ?
    If I do rise/pullup and fall/pulldown simulations with different Rfixture v= alues, is it acceptable ?

    Best Regards
    Chetana


    - --
    This message has been scanned for viruses and
    dangerous content by     MailScanner= , and is
    believed to be clean.


- --
This message has been scanned for viruses and
dangerous content by = MailScanner, and is
believed to be clean.

--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --1__=EABBFE3ADFD860D28f9e8a93df938690918cEABBFE3ADFD860D2-- - --0__=EABBFE3ADFD860D28f9e8a93df938690918cEABBFE3ADFD860D2 Content-type: image/gif; name="graycol.gif" Content-Disposition: inline; filename="graycol.gif" Content-ID: <10__=EABBFE3ADFD860D28f9e8a93df938690@nxp.com> Content-transfer-encoding: base64 R0lGODlhEAAQAKECAMzMzAAAAP///wAAACH5BAEAAAIALAAAAAAQABAAAAIX lI+py+0PopwxUbpuZRfKZ2zgSJbmSRYAIf4fT3B0aW1pemVkIGJ5IFVsZWFk IFNtYXJ0U2F2ZXIhAAA7 - --0__=EABBFE3ADFD860D28f9e8a93df938690918cEABBFE3ADFD860D2 Content-type: image/gif; name="pic30333.gif" Content-Disposition: inline; filename="pic30333.gif" Content-ID: <20__=EABBFE3ADFD860D28f9e8a93df938690@nxp.com> Content-transfer-encoding: base64 R0lGODlhWABDALP/AAAAAK04Qf79/o+Gm7WuwlNObwoJFCsoSMDAwGFsmIue zf///wAAAAAAAAAAAAAAACH5BAEAAAgALAAAAABYAEMAQAT/EMlJq7046827 70RiFMRinqggEUNSHIchG0BCfHhOjAuhEDeUqTASLCbBhQrhG7xis2j0lssN DopE4jfIJhDaggI8YB1sZeZgLVA9YVCpnGagVjV171aRVrYRRghXcAGFhoUE TwYxcXNyADJ3GlcSKGAwLwllVC1vjIUHBWsFilKQdI8GA5IcpApeJQt8L09l mgkHLZikoU5wjqcyAMMFrJIDPAKvCFletKSev1HBw8KrxtjZ2tvc3d5VyKtC KW3jfz4uMKmq3xu4N0nKBVoJQmx2LGVOmrqNjjJf2hHAQo/eDwJGTKhQMcgQ EEAnEjFS98+RnW3smGkZU6ncCWav/4wYOnAITihRL/4FEwbp28BXMMcoscQC VxlepL4IGDSCyJyVQOu0o7CjmLN50OZlqWmyFy5/6yBBuji0AxFRM00oQAqN IstqI6qKHUsWRAEAvagsmfUEAImyxgbmUpJk3IklNUtJOUAVLoUr1+wqDGTE 4zk+T6FGuQb3SizBCwatiiUgCBN8vrz+zFjVyQ8FWkOlg4NQiZMB5QS8QO3m pOaKnL0Z2EKvNMSILEThKhCgzMKPVxYJh23qm9KNW7pArPynMqZDiErsTMqI +LRi3QAgkFUbXpuFKhSYZALd0O5RKa2z9EYKBbpbqxIKsjUPRgD7I2XYV6wy rOw92ykExP8NW4URhknC5dKGE4v4NENQj2jXjmfNgOZDaXb5glRmXQ33YEWQ YNcZFnrYcIQLNzyTFDQNkXIff0ExVlY4srziQk43inZgL4rwxxINMvpFFAz1 KOODHiu+4aEwNEjFl5B3JIKWKF3k6I9bfUGp5ZZcdunll5IA4cuHvQQJ5gcs oCWOOUwgltIwAKRxJgbIkJAQZEq02YliZnpZZ4BH3CnYOXldOUOfQoYDqF1L FHbXCrO8xmRsfoXDXJ6ChjCAH3QlhJcT6VWE6FCkfCcoCgrMFsROrIEX3o2w hVjWDjoJccN3LdggSGXLCdLEgHr1lyU3O3QxhgohNKXJCWv8JQr/PDdaqd6w 2rj1inLiGeiCJoDspAoQlYE6QWLSECehcWIYxIQES6zhbn1iImTHEQyqJ4eI xJJoUBc+3CbBuwZEV5cJPPkIjFDdeEabQbd6WgICTxiiz0f5dBKquXF6k4se nwEhYGnKEFJeGrxUZy8dB8gmAXI/sPvHESfCwVt5hTgYiqQqtdRNHQIU1PJ3 3ZqmzgE90OwLaoJcnMop1WiMmgkPHQRIrwgFuNV90A3doNKTmrKIN07AnGcI 9BQjhCBN4RfA1qIZnMqorJCogKfGQnxSCDilTVIA0yl5ciTovgLuBDKFUDE9 aQcw9SA+rjSNf9/M1gxrj6VwDTS0IUSElMzBfsj0NFXR2kwsV1A5IF1grLgL L/r1R40BZEnuBWgmQEybjqRwSAt6bqMCOFkvKFN2GPPkUzIm/SCF8z8pVzpb jVnMsy0vOr1hw3SaSRUhpY09v0z0J1FnwzPlfmh+xl4WtR0zGu24I4KbMQm3 lnVu2oNWxI9W/lcyzA+mCKF4DBikxb/+UWtOGRiFP8qEwAayIgIAOw== - --0__=EABBFE3ADFD860D28f9e8a93df938690918cEABBFE3ADFD860D2 Content-type: image/gif; name="ecblank.gif" Content-Disposition: inline; filename="ecblank.gif" Content-ID: <30__=EABBFE3ADFD860D28f9e8a93df938690@nxp.com> Content-transfer-encoding: base64 R0lGODlhEAABAIAAAAAAAP///yH5BAEAAAEALAAAAAAQAAEAAAIEjI8ZBQA7 - --0__=EABBFE3ADFD860D28f9e8a93df938690918cEABBFE3ADFD860D2-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 18 Aug 2008 09:38:25 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance This is a multipart message in MIME format. - ------=_NextPart_000_01EB_01C90116.2A5658E0 Content-Type: multipart/alternative; boundary="----=_NextPart_001_01EC_01C90116.2A58C9E0" - ------=_NextPart_001_01EC_01C90116.2A58C9E0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit No, no and no. The load resistor used for extracting the VT waveforms should represent the load seen by the driver on the circuit board. Most reasonable circuit boards will have trace impedances between 40 and 75 Ohms and usually the design targets 50 Ohms. So the IBIS model should characterize the buffer into an impedance close to that. The generally accepted value is 50 Ohms. It has nothing at all to do with the output impedance of the driver. You are not trying to match load/output impedance or maximize power transfer, you are trying to get a macro model to be characterized near its operating conditions. There are no such things as IV VT curves. There are no loads associated with extracting IV curves. Extending the simulation time may or may not "fix" IV/VT curve mismatches. Extending simulations times will only fix mismatches if the original simulations did not allow the VT waveforms to reach their final value. If you have a problem understand the cause before jumping to a solution. Just jumping to a solution in most cases will not work. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 503-430-1285 FAX tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chetana Raghuwanshi Sent: Monday, August 18, 2008 6:51 AM To: Sudarshan H N Cc: ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence Hi Sudarshan, You are right. My concern is IV VT mismatch error. How would it disappear by increasing the simulation time ? Best Regards Chetana - -------------------------------------------------------- Chetana Raghuwanshi CTO / Process & Library Technology NXP Semiconductors India NXP Block C, 4th Floor MFAR Manyata Tech Park Nagavara, Bangalore-560045 Tel : +91 80 4024 7072 - -------------------------------------------------------- Inactive hide details for "Sudarshan H N" "Sudarshan H N" "Sudarshan H N" Sent by: owner-ibis-users@server.eda.org 2008-08-18 06:43 PM To "Chetana Raghuwanshi" cc ibis-users@server.eda.org, ibis@server.eda.org Subject [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence Hello Chetana, You can use any of the 2 values for Rfixture to generate Vt curves. There is no rule that , your Rfixture should match to the PMOS or NMOS driver resistance. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any errors with respect to IV and Vt curve mismatch , just simulate for more time so that it will reach the saturation. Regards Sudarshan On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi < chetana.raghuwanshi@nxp.com> wrote: Hello Experts, One of my IO cell has a buffer with different PMOS and NMOS impedences. PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms. In this case what should be the value of Rfixture for calculating IV VT curves ? Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ? If I do rise/pullup and fall/pulldown simulations with different Rfixture values, is it acceptable ? Best Regards Chetana - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_001_01EC_01C90116.2A58C9E0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

No, no and no.

 

The load resistor used for extracting the VT waveforms should represent the load seen by the driver on the circuit board.  Most reasonable circuit boards will have trace impedances between 40 and 75 Ohms= and usually the design targets 50 Ohms.  So the IBIS model should characte= rize the buffer into an impedance close to that. The generally accepted value is= 50 Ohms.  It has nothing at all to do with the output impedance of the driver.  You are not trying to match load/output impedance or maximize power transfer, you are trying to get a macro model to be characterized near its operating conditions.

 

There are no such things as IV VT curves. There are no loads associated with extracting IV curves.

 

Extending the simulation time may or may not “fix̶= 1; IV/VT curve mismatches.  Extending simulations times will only fix mismatches if the original simulations did not allow the VT waveforms to re= ach their final value.  If you have a problem understand the cause before jumping to a solution.  Just jumping to a solution in most cases will = not work.

 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

 

From: owner-ibis-us= ers@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chetana Raghuwanshi
Sent: Monday, August 18, 2008 6:51 AM
To: Sudarshan H N
Cc: ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence

 

Hi Sudarshan,

You are right. My concern is IV VT mismatch error.
How would it disappear by increasing the simulation time ?

Best Regards
Chetana

- --------------------------------------------------------
Chetana Raghuwanshi
CTO / Process & Library Technology
NXP Semiconductors India
NXP Block C, 4th Floor
MFAR Manyata Tech Park
Nagavara, Bangalore-560045
Tel : +91 80 4024 7072
- --------------------------------------------------------
3D"Inactive"Sudarshan H N" <hn.sudarshan@gmail.com>

"Sudarshan H N" <hn.sudarshan@gmail.com>
Sent by:

owner-ibis= - -users@server.eda.org

2008-08-18= 06:43 PM

To


"Chetana Raghuwanshi" <chetana.raghuwanshi@nxp.com>

cc


ibis-users@server.eda.org, ibis@server.eda.org

Subject


[IBIS-Users] Re: [IBIS] Different PMOS= and NMOS driver impedence

 


Hello Chetana,

You can use any of the 2 values for Rfixture to generate Vt curves. There i= s no rule that , your Rfixture should match to the PMOS or NMOS driver resistanc= e. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any errors with respect to IV and Vt curve mismatch , just simulate for more ti= me so that it will reach the saturation.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi <chetana.raghuwanshi@nxp.com> wrote:

Hello Experts,

One of my IO cell has a buffer with different PMOS and NMOS impedences.
PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms.
In this case what should be the value of Rfixture for calculating IV VT cur= ves ?
Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ?
If I do rise/pullup and fall/pulldown simulations with different Rfixture values, is it acceptable ?

Best Regards
Chetana


- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.



- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


- --
This message has been scanned for viruses and
dangerous content by MailScanne= r, and is
believed to be clean.


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_001_01EC_01C90116.2A58C9E0-- - ------=_NextPart_000_01EB_01C90116.2A5658E0 Content-Type: image/gif; name="image001.gif" Content-Transfer-Encoding: base64 Content-ID: R0lGODlhEAAQAKECAMzMzAAAAP///wAAACH5BAEAAAIALAAAAAAQABAAAAIX lI+py+0PopwxUbpuZRfKZ2zgSJbmSRYAIf4fT3B0aW1pemVkIGJ5IFVsZWFk IFNtYXJ0U2F2ZXIhAAA7 - ------=_NextPart_000_01EB_01C90116.2A5658E0 Content-Type: image/png; name="image003.png" Content-Transfer-Encoding: base64 Content-ID: iVBORw0KGgoAAAANSUhEUgAAADoAAAABCAMAAAC42E10AAAAAXNSR0ICQMB9 xQAAAANQTFRFAAAAp3o92gAAAAF0Uk5TAEDm2GYAAAAJcEhZcwAADsQAAA7E AZUrDhsAAAAZdEVYdFNvZnR3YXJlAE1pY3Jvc29mdCBPZmZpY2V/7TVxAAAA DElEQVQY02NgIBsAAAA7AAFzMF3lAAAAAElFTkSuQmCC - ------=_NextPart_000_01EB_01C90116.2A5658E0 Content-Type: image/png; name="image004.png" Content-Transfer-Encoding: base64 Content-ID: iVBORw0KGgoAAAANSUhEUgAAAAEAAAABCAMAAAAoyzS7AAAAAXNSR0ICQMB9 xQAAAANQTFRFAAAAp3o92gAAAAF0Uk5TAEDm2GYAAAAJcEhZcwAADsQAAA7E AZUrDhsAAAAZdEVYdFNvZnR3YXJlAE1pY3Jvc29mdCBPZmZpY2V/7TVxAAAA CklEQVQY02NgAAAAAgABmGNs1wAAAABJRU5ErkJggg== - ------=_NextPart_000_01EB_01C90116.2A5658E0-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 19 Aug 2008 09:28:11 +0530 From: "Muniswara Reddy Vorugu" Subject: RE: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence This is a multi-part message in MIME format. - ------_=_NextPart_001_01C901AF.CCFCEB79 Content-Type: multipart/alternative; boundary="----_=_NextPart_002_01C901AF.CCFCEB79" - ------_=_NextPart_002_01C901AF.CCFCEB79 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable Hi Chetana,=20 Slide-20 of the presentation in the link can help you, in correcting IV-VT mismatch. http://www.eda.org/ibis/summits/jan02/bell1.pdf =20 This presentation discusses some more common errors and warnings. =20 Thanks, Muniswar =20 ________________________________ From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Chetana Raghuwanshi Sent: Monday, August 18, 2008 7:21 PM To: Sudarshan H N Cc: ibis@eda.org; ibis-users@eda.org; owner-ibis-users@eda.org Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence =20 Hi Sudarshan, You are right. My concern is IV VT mismatch error. How would it disappear by increasing the simulation time ? Best Regards Chetana - -------------------------------------------------------- Chetana Raghuwanshi CTO / Process & Library Technology NXP Semiconductors India NXP Block C, 4th Floor MFAR Manyata Tech Park Nagavara, Bangalore-560045 Tel : +91 80 4024 7072 - -------------------------------------------------------- "Sudarshan H N" "Sudarshan H N" =20 Sent by:=20 owner-ibis-users@server.eda.org=20 2008-08-18 06:43 PM =20 To =20 "Chetana Raghuwanshi" cc ibis-users@server.eda.org, ibis@server.eda.org Subject [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence =20 Hello Chetana, You can use any of the 2 values for Rfixture to generate Vt curves. There is no rule that , your Rfixture should match to the PMOS or NMOS driver resistance. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any errors with respect to IV and Vt curve mismatch , just simulate for more time so that it will reach the saturation. Regards Sudarshan On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi < chetana.raghuwanshi@nxp.com > wrote:=20 Hello Experts, One of my IO cell has a buffer with different PMOS and NMOS impedences. PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms. In this case what should be the value of Rfixture for calculating IV VT curves ? Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ? If I do rise/pullup and fall/pulldown simulations with different Rfixture values, is it acceptable ? Best Regards Chetana - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_002_01C901AF.CCFCEB79 Content-Type: text/html; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable

Hi Chetana, <= /p>

Slide-20 of the presentation in the li= nk can help you, in correcting IV-VT mismatch.

http://www.eda.org= /ibis/summits/jan02/bell1.pdf

 

This presentation discusses some more common errors and warnings.

 

Thanks,

Muniswar

 

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Chetana Raghuwanshi
Sent: Monday, August 18, 200= 8 7:21 PM
To: Sudarshan H N
Cc: ibis@eda.org; ibis-users@eda.org; owner-ibis-users@eda.org
Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence

 

<= span style=3D'font-size:12.0pt'>Hi Sudarshan,

You are right. My concern is I= V VT mismatch error.
How would it disappear by increasing the simulation time ?

Best Regards
Chetana

- --------------------------------------------------------
Chetana Raghuwanshi
CTO / Process & Library Technology
NXP Semiconductors I= ndia
NXP Block C, 4th Floor
MFAR Manyata Tech Park
Nagavara, Bangalore-560045
Tel : +91 80 4024 7072
- --------------------------------------------------------
3D"Inactive"Sudarshan H N" <hn.sudarshan@gmail.com>

"Sudarshan H N" <hn.sudarshan@gmail.com>=
Sent by:

owner-ibis-users@server.eda.org =

2008-08-18 06:43 PM

To


"Che= tana Raghuwanshi" <chetana.raghuwanshi@nxp.com>

cc


ibis-user= s@server.eda.org, ibis@server.eda.org

Subject


[IBIS-Use= rs] Re: [IBIS] Different PMOS and NMOS driver impedence

 


Hello Chetana= ,

You can use any of the 2 values for Rfixture to generate Vt curves. There i= s no rule that , your Rfixture should match to the PMOS or NMOS driver resistanc= e. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any= errors with respect to IV and Vt curve mismatch , just simulate for more time so t= hat it will reach the saturation.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 6:3= 7 PM, Chetana Raghuwanshi <chetana.raghuwanshi@nxp.com> wrote:

Hello Experts,

One of my IO cell has a buffer with different PMOS and NMOS impedences.
PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms.
In this case what should be the value of Rfixture for calculating IV VT curves ?
Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ?
If I do rise/pullup and fall/pulldown simulations with different Rfixture values, is it acceptable ?

Best Regards
Chetana


- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.



- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------_=_NextPart_002_01C901AF.CCFCEB79-- - ------_=_NextPart_001_01C901AF.CCFCEB79 Content-Type: image/gif; name="image001.gif" Content-Transfer-Encoding: base64 Content-ID: Content-Description: image001.gif Content-Location: image001.gif R0lGODlhEAAQAKECAMzMzAAAAP///wAAACH5BAEAAAIALAAAAAAQABAAAAIX lI+py+0PopwxUbpuZRfKZ2zgSJbmSRYAIf4fT3B0aW1pemVkIGJ5IFVsZWFk IFNtYXJ0U2F2ZXIhAAA7 - ------_=_NextPart_001_01C901AF.CCFCEB79 Content-Type: image/gif; name="image004.gif" Content-Transfer-Encoding: base64 Content-ID: Content-Description: image004.gif Content-Location: image004.gif R0lGODlhOgABAHcAMSH+GlNvZnR3YXJlOiBNaWNyb3NvZnQgT2ZmaWNlACH5 BAEAAAAALAAAAAABAAEAgAAAAAECAwICRAEAOw== - ------_=_NextPart_001_01C901AF.CCFCEB79 Content-Type: image/gif; name="image005.gif" Content-Transfer-Encoding: base64 Content-ID: Content-Description: image005.gif Content-Location: image005.gif R0lGODlhAQABAHcAMSH+GlNvZnR3YXJlOiBNaWNyb3NvZnQgT2ZmaWNlACH5 BAEAAAAALAAAAAABAAEAgAAAAAECAwICRAEAOw== - ------_=_NextPart_001_01C901AF.CCFCEB79-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 19 Aug 2008 11:56:48 +0530 From: "Sudarshan H N" Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance - ------=_Part_89251_13703713.1219127208798 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline HI, I had a similar discussion about the value of the Rfixture some time back with the IBIS group, and that time the conclusion was, as you said we should select Rfixture close to the impedance seen by the driver on the board i.e, around 50ohm. But the exact value might be different and hence these V-t curves in IBIS will just give one set of values for given Rfixture, and board level simulation tools will use these V-t curves as a reference to get the actual V-t waveforms for a given load. Still my doubt is, the pad will see some value of RLC on the board, and IBIS discourages to use reactive loads when generating Vt curves. So how much accuracy these V-t curves will give , assuming its only generated with Rfixture and not with other reactive loads. Regards Sudarshan On Mon, Aug 18, 2008 at 10:08 PM, Tom Dagostino wrote: > No, no and no. > > > > The load resistor used for extracting the VT waveforms should represent the > load seen by the driver on the circuit board. Most reasonable circuit > boards will have trace impedances between 40 and 75 Ohms and usually the > design targets 50 Ohms. So the IBIS model should characterize the buffer > into an impedance close to that. The generally accepted value is 50 Ohms. > It has nothing at all to do with the output impedance of the driver. You > are not trying to match load/output impedance or maximize power transfer, > you are trying to get a macro model to be characterized near its operating > conditions. > > > > There are no such things as IV VT curves. There are no loads associated > with extracting IV curves. > > > > Extending the simulation time may or may not "fix" IV/VT curve mismatches. > Extending simulations times will only fix mismatches if the original > simulations did not allow the VT waveforms to reach their final value. If > you have a problem understand the cause before jumping to a solution. Just > jumping to a solution in most cases will not work. > > > > Tom Dagostino > Teraspeed(R) Labs > 13610 SW Harness Lane > Beaverton, OR 97008 > 503-430-1065 > > 503-430-1285 FAX > tom@teraspeed.com > www.teraspeed.com > > Teraspeed Consulting Group LLC > 121 North River Drive > Narragansett, RI 02882 > 401-284-1827 > > > > *From:* owner-ibis-users@server.eda.org [mailto: > owner-ibis-users@server.eda.org] *On Behalf Of *Chetana Raghuwanshi > *Sent:* Monday, August 18, 2008 6:51 AM > *To:* Sudarshan H N > *Cc:* ibis@server.eda.org; ibis-users@server.eda.org; > owner-ibis-users@server.eda.org > *Subject:* Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver > impedence > > > > Hi Sudarshan, > > You are right. My concern is IV VT mismatch error. > How would it disappear by increasing the simulation time ? > > Best Regards > Chetana > > -------------------------------------------------------- > Chetana Raghuwanshi > CTO / Process & Library Technology > NXP Semiconductors India > NXP Block C, 4th Floor > MFAR Manyata Tech Park > Nagavara, Bangalore-560045 > Tel : +91 80 4024 7072 > -------------------------------------------------------- > [image: Inactive hide details for "Sudarshan H N" ]"Sudarshan > H N" > > *"Sudarshan H N" * > Sent by: > > owner-ibis-users@server.eda.org > > 2008-08-18 06:43 PM > > To > > > "Chetana Raghuwanshi" > > cc > > > ibis-users@server.eda.org, ibis@server.eda.org > > Subject > > > [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence > > > > > Hello Chetana, > > You can use any of the 2 values for Rfixture to generate Vt curves. There > is no rule that , your Rfixture should match to the PMOS or NMOS driver > resistance. But you should always use one value to generate the one set of > rising and falling waveforms(experts, correct me if i am wrong). If you are > seeing any errors with respect to IV and Vt curve mismatch , just simulate > for more time so that it will reach the saturation. > > Regards > Sudarshan > > On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi < > chetana.raghuwanshi@nxp.com> wrote: > > Hello Experts, > > One of my IO cell has a buffer with different PMOS and NMOS impedences. > PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms. > In this case what should be the value of Rfixture for calculating IV VT > curves ? > Would it be Rfixture1 for calculating pull down and falling waveforms and > Rfixture2 for calculating pull up and rising waveforms ? > If I do rise/pullup and fall/pulldown simulations with different Rfixture > values, is it acceptable ? > > Best Regards > Chetana > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_Part_89251_13703713.1219127208798 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline
HI,

I had a similar discussion about the value of the Rfixture some time back  with the IBIS group, and that time the conclusion was, as you said we should select Rfixture close to the impedance seen by the driver on the board i.e, around 50ohm. But the exact value might be different and hence these  V-t curves in IBIS will just give one set of values for given Rfixture,  and  board level simulation tools will use these V-t curves as a reference to get the actual V-t waveforms for a given load.

Still my doubt is, the pad will see some value of RLC on the board, and IBIS discourages to use reactive loads when generating Vt curves. So how much accuracy these V-t curves will give , assuming its only generated with Rfixture and not with other reactive loads.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 10:08 PM, Tom Dagostino <tom@teraspeed.com> wrote:

No, no and no.

 

The load resistor used for extracting the VT waveforms should represent the load seen by the driver on the circuit board.  Most reasonable circuit boards will have trace impedances between 40 and 75 Ohms and usually the design targets 50 Ohms.  So the IBIS model should characterize the buffer into an impedance close to that. The generally accepted value is 50 Ohms.  It has nothing at all to do with the output impedance of the driver.  You are not trying to match load/output impedance or maximize power transfer, you are trying to get a macro model to be characterized near its operating conditions.

 

There are no such things as IV VT curves. There are no loads associated with extracting IV curves.

 

Extending the simulation time may or may not "fix" IV/VT curve mismatches.  Extending simulations times will only fix mismatches if the original simulations did not allow the VT waveforms to reach their final value.  If you have a problem understand the cause before jumping to a solution.  Just jumping to a solution in most cases will not work.

 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

 

From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chetana Raghuwanshi
Sent: Monday, August 18, 2008 6:51 AM
To: Sudarshan H N
Cc: ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence

 

Hi Sudarshan,

You are right. My concern is IV VT mismatch error.
How would it disappear by increasing the simulation time ?

Best Regards
Chetana

- --------------------------------------------------------
Chetana Raghuwanshi
CTO / Process & Library Technology
NXP Semiconductors India
NXP Block C, 4th Floor
MFAR Manyata Tech Park
Nagavara, Bangalore-560045
Tel : +91 80 4024 7072
- --------------------------------------------------------
Inactive hide details for "Sudarshan H N" <hn.sudarshan@gmail.com>"Sudarshan H N" <hn.sudarshan@gmail.com>

"Sudarshan H N" <hn.sudarshan@gmail.com>
Sent by:

owner-ibis-users@server.eda.org

2008-08-18 06:43 PM

To


"Chetana Raghuwanshi" <chetana.raghuwanshi@nxp.com>

cc


ibis-users@server.eda.org, ibis@server.eda.org

Subject


[IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence

 


Hello Chetana,

You can use any of the 2 values for Rfixture to generate Vt curves. There is no rule that , your Rfixture should match to the PMOS or NMOS driver resistance. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any errors with respect to IV and Vt curve mismatch , just simulate for more time so that it will reach the saturation.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi <chetana.raghuwanshi@nxp.com> wrote:

Hello Experts,

One of my IO cell has a buffer with different PMOS and NMOS impedences.
PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms.
In this case what should be the value of Rfixture for calculating IV VT curves ?
Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ?
If I do rise/pullup and fall/pulldown simulations with different Rfixture values, is it acceptable ?

Best Regards
Chetana


- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.



- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.



--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_Part_89251_13703713.1219127208798-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 19 Aug 2008 00:32:56 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance This is a multipart message in MIME format. - ------=_NextPart_000_0283_01C90193.20598DD0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit My experience with simulators is consistent with IBIS' recommendations. If you put reactive loads in the VT curve load many times the simulations blow up. If you allow the SI simulator to simulate the actual load seen by the driver - a transmission line plus package plus any other parasitics, the simulations tend to match measurements. As a model maker you will never know what kinds of loads the end user places on the driver. So you cannot anticipate what reactive load to put in the model. Once you get on the board and assuming (and at times this is a big assumption) there is power/ground plane beneath the trace from the driver to the load, the load seen by the driver will be a transmission line load. If the end product's board looks like lumped RLCs there are going to be problems. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 503-430-1285 FAX tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 From: Sudarshan H N [mailto:hn.sudarshan@gmail.com] Sent: Monday, August 18, 2008 11:27 PM To: tom@teraspeed.com Cc: Chetana Raghuwanshi; ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance HI, I had a similar discussion about the value of the Rfixture some time back with the IBIS group, and that time the conclusion was, as you said we should select Rfixture close to the impedance seen by the driver on the board i.e, around 50ohm. But the exact value might be different and hence these V-t curves in IBIS will just give one set of values for given Rfixture, and board level simulation tools will use these V-t curves as a reference to get the actual V-t waveforms for a given load. Still my doubt is, the pad will see some value of RLC on the board, and IBIS discourages to use reactive loads when generating Vt curves. So how much accuracy these V-t curves will give , assuming its only generated with Rfixture and not with other reactive loads. Regards Sudarshan On Mon, Aug 18, 2008 at 10:08 PM, Tom Dagostino wrote: No, no and no. The load resistor used for extracting the VT waveforms should represent the load seen by the driver on the circuit board. Most reasonable circuit boards will have trace impedances between 40 and 75 Ohms and usually the design targets 50 Ohms. So the IBIS model should characterize the buffer into an impedance close to that. The generally accepted value is 50 Ohms. It has nothing at all to do with the output impedance of the driver. You are not trying to match load/output impedance or maximize power transfer, you are trying to get a macro model to be characterized near its operating conditions. There are no such things as IV VT curves. There are no loads associated with extracting IV curves. Extending the simulation time may or may not "fix" IV/VT curve mismatches. Extending simulations times will only fix mismatches if the original simulations did not allow the VT waveforms to reach their final value. If you have a problem understand the cause before jumping to a solution. Just jumping to a solution in most cases will not work. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 503-430-1285 FAX tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chetana Raghuwanshi Sent: Monday, August 18, 2008 6:51 AM To: Sudarshan H N Cc: ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence Hi Sudarshan, You are right. My concern is IV VT mismatch error. How would it disappear by increasing the simulation time ? Best Regards Chetana - -------------------------------------------------------- Chetana Raghuwanshi CTO / Process & Library Technology NXP Semiconductors India NXP Block C, 4th Floor MFAR Manyata Tech Park Nagavara, Bangalore-560045 Tel : +91 80 4024 7072 - -------------------------------------------------------- Error! Filename not specified."Sudarshan H N" "Sudarshan H N" Sent by: owner-ibis-users@server.eda.org 2008-08-18 06:43 PM Error! Filename not specified. To Error! Filename not specified. "Chetana Raghuwanshi" Error! Filename not specified. cc Error! Filename not specified. ibis-users@server.eda.org, ibis@server.eda.org Error! Filename not specified. Subject Error! Filename not specified. [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence Error! Filename not specified. Error! Filename not specified. Hello Chetana, You can use any of the 2 values for Rfixture to generate Vt curves. There is no rule that , your Rfixture should match to the PMOS or NMOS driver resistance. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any errors with respect to IV and Vt curve mismatch , just simulate for more time so that it will reach the saturation. Regards Sudarshan On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi < chetana.raghuwanshi@nxp.com> wrote: Hello Experts, One of my IO cell has a buffer with different PMOS and NMOS impedences. PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms. In this case what should be the value of Rfixture for calculating IV VT curves ? Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ? If I do rise/pullup and fall/pulldown simulations with different Rfixture values, is it acceptable ? Best Regards Chetana - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0283_01C90193.20598DD0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

My experience with simulators is consistent with IBIS’ recommendations. If you put reactive loads in the VT curve load many times = the simulations blow up.  If you allow the SI simulator to simulate the ac= tual load seen by the driver - a transmission line plus package plus any other parasitics, the simulations tend to match measurements.  As a model ma= ker you will never know what kinds of loads the end user places on the driver.  So you cannot anticipate what reactive load to put in the model. 

 

Once you get on the board and assuming (and at times this is= a big assumption) there is power/ground plane beneath the trace from the driv= er to the load, the load seen by the driver will be a transmission line load.&= nbsp; If the end product’s board looks like lumped RLCs there are going to = be problems.

 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

 

From: Sudarshan H N [mailto:hn.sudarshan@gmail.com]
Sent: Monday, August 18, 2008 11:27 PM
To: tom@teraspeed.com
Cc: Chetana Raghuwanshi; ibis@server.eda.org; ibis-users@server.eda.= org; owner-ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance

 

HI,

I had a similar discussion about the value of the Rfixture some time back&n= bsp; with the IBIS group, and that time the conclusion was, as you said we should select Rfixture close to the impedance seen by the driver on the board i.e, around 50ohm. But the exact value might be different and hence these  = V-t curves in IBIS will just give one set of values for given Rfixture,  and  board level simulation tools will use these V-t curves as a refer= ence to get the actual V-t waveforms for a given load.

Still my doubt is, the pad will see some value of RLC on the board, and IBIS discourages to use reactive loads when generating Vt curves. So how much accuracy these V-t curves will give , assuming its only generated with Rfix= ture and not with other reactive loads.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 10:08 PM, Tom Dagostino <tom@teraspeed.com> wrote:

No, no and no.

 <= /p>

The load resistor used for extracting the VT waveforms should represent the load seen by the driver on= the circuit board.  Most reasonable circuit boards will have trace impedan= ces between 40 and 75 Ohms and usually the design targets 50 Ohms.  So the IBIS model should characterize the buffer into an impedance close to that. = The generally accepted value is 50 Ohms.  It has nothing at all to do with= the output impedance of the driver.  You are not trying to match load/outp= ut impedance or maximize power transfer, you are trying to get a macro model t= o be characterized near its operating conditions.

 <= /p>

There are no such things = as IV VT curves. There are no loads associated with extracting IV curves.<= o:p>

 <= /p>

Extending the simulation = time may or may not "fix" IV/VT curve mismatches.  Extending simulations times will only fix mismatches if the original simulations did = not allow the VT waveforms to reach their final value.  If you have a prob= lem understand the cause before jumping to a solution.  Just jumping to a solution in most cases will not work.

 <= /p>

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827 <= o:p>

 <= /p>

From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chetana Raghuwanshi
Sent: Monday, August 18, 2008 6:51 AM
To: Sudarshan H N
Cc: ibis@se= rver.eda.org; ibis-users@s= erver.eda.org; owner-= ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence

 

Hi Sudarshan,

You are right. My concern is IV VT mismatch error.
How would it disappear by increasing the simulation time ?

Best Regards
Chetana

- --------------------------------------------------------
Chetana Raghuwanshi
CTO / Process & Library Technology
NXP Semiconductors India
NXP Block C, 4th Floor
MFAR Manyata Tech Park
Nagavara, Bangalore-560045
Tel : +91 80 4024 7072
- --------------------------------------------------------
Error! Filename not specified."Sudarshan H N" <hn.sudarshan@gmail= .com>

"S= udarshan H N" <hn.sudarshan@gmail.com>
Sent by:

owner-i= bis-users@server.eda.org

2008-08-18= 06:43 PM

Error! Filename not specified.

To

Error! Filename not specified.
"Chetana Raghuwanshi" <chetana.r= aghuwanshi@nxp.com>

Error! Filename not specified.

cc

Error! Filename not specified.
ibis-users@server.eda.org, ibis@server.eda.o= rg

Error! Filename not specified.

Subject

Error! Filename not specified.
[IBIS-Users] Re: [IBIS] Different PMOS= and NMOS driver impedence

 

Error! Filename not specified.

Error! Filename not specified.


Hello Chetana,

You can use any of the 2 values for Rfixture to generate Vt curves. There i= s no rule that , your Rfixture should match to the PMOS or NMOS driver resistanc= e. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any errors with respect to IV and Vt curve mismatch , just simulate for more ti= me so that it will reach the saturation.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi <chetana.raghuwanshi@nxp.= com> wrote:

Hello Expert= s,

One of my IO cell has a buffer with different PMOS and NMOS impedences.
PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms.
In this case what should be the value of Rfixture for calculating IV VT cur= ves ?
Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ?
If I do rise/pullup and fall/pulldown simulations with different Rfixture v= alues, is it acceptable ?

Best Regards
Chetana


- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.



- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.

 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_0283_01C90193.20598DD0-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 19 Aug 2008 07:55:10 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance This is a multi-part message in MIME format. - ------_=_NextPart_001_01C9020B.95AF593E Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I gave a presentation on this subject and it is available on the IBIS web site: =20 http://www.vhdl.org/pub/ibis/summits/mar06/muranyi1.pdf =20 It is not in the presentation, but I remember while I was working on it I experimented with different arrangements of the reactive elements. For example, a series versus a parallel capacitor and/or inductor. A parallel capacitor is not as problematic as a series capacitor can be and a series inductor may not be as bad as a parallel inductor. But they all have di/dt or dV/dt in their equations, which is what is missing in the basic 2EQ/2UK IBIS equations. =20 Of course, there is nothing that should prevent an EDA vendor or even a model maker using the *-AMS languages to write algorithms that use differential equations to handle the reactive loads correctly... =20 Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D ________________________________ From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf Of Tom Dagostino Sent: Tuesday, August 19, 2008 2:33 AM To: 'Sudarshan H N' Cc: 'Chetana Raghuwanshi'; ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org Subject: RE: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance My experience with simulators is consistent with IBIS' recommendations. If you put reactive loads in the VT curve load many times the simulations blow up. If you allow the SI simulator to simulate the actual load seen by the driver - a transmission line plus package plus any other parasitics, the simulations tend to match measurements. As a model maker you will never know what kinds of loads the end user places on the driver. So you cannot anticipate what reactive load to put in the model.=20=20 =20 Once you get on the board and assuming (and at times this is a big assumption) there is power/ground plane beneath the trace from the driver to the load, the load seen by the driver will be a transmission line load. If the end product's board looks like lumped RLCs there are going to be problems. =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 503-430-1285 FAX tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 =20 From: Sudarshan H N [mailto:hn.sudarshan@gmail.com]=20 Sent: Monday, August 18, 2008 11:27 PM To: tom@teraspeed.com Cc: Chetana Raghuwanshi; ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance =20 HI, I had a similar discussion about the value of the Rfixture some time back with the IBIS group, and that time the conclusion was, as you said we should select Rfixture close to the impedance seen by the driver on the board i.e, around 50ohm. But the exact value might be different and hence these V-t curves in IBIS will just give one set of values for given Rfixture, and board level simulation tools will use these V-t curves as a reference to get the actual V-t waveforms for a given load.=20 Still my doubt is, the pad will see some value of RLC on the board, and IBIS discourages to use reactive loads when generating Vt curves. So how much accuracy these V-t curves will give , assuming its only generated with Rfixture and not with other reactive loads. Regards Sudarshan On Mon, Aug 18, 2008 at 10:08 PM, Tom Dagostino wrote: No, no and no. =20 The load resistor used for extracting the VT waveforms should represent the load seen by the driver on the circuit board. Most reasonable circuit boards will have trace impedances between 40 and 75 Ohms and usually the design targets 50 Ohms. So the IBIS model should characterize the buffer into an impedance close to that. The generally accepted value is 50 Ohms. It has nothing at all to do with the output impedance of the driver. You are not trying to match load/output impedance or maximize power transfer, you are trying to get a macro model to be characterized near its operating conditions. =20 There are no such things as IV VT curves. There are no loads associated with extracting IV curves. =20 Extending the simulation time may or may not "fix" IV/VT curve mismatches. Extending simulations times will only fix mismatches if the original simulations did not allow the VT waveforms to reach their final value. If you have a problem understand the cause before jumping to a solution. Just jumping to a solution in most cases will not work. =20 Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 503-430-1285 FAX tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827=20 =20 From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chetana Raghuwanshi Sent: Monday, August 18, 2008 6:51 AM To: Sudarshan H N Cc: ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence =20 Hi Sudarshan, You are right. My concern is IV VT mismatch error. How would it disappear by increasing the simulation time ? Best Regards Chetana - -------------------------------------------------------- Chetana Raghuwanshi CTO / Process & Library Technology NXP Semiconductors India NXP Block C, 4th Floor MFAR Manyata Tech Park Nagavara, Bangalore-560045 Tel : +91 80 4024 7072 - -------------------------------------------------------- Error! Filename not specified."Sudarshan H N" "Sudarshan H N" =20 Sent by:=20 owner-ibis-users@server.eda.org=20 2008-08-18 06:43 PM Error! Filename not specified. To Error! Filename not specified. "Chetana Raghuwanshi" Error! Filename not specified. cc Error! Filename not specified. ibis-users@server.eda.org, ibis@server.eda.org Error! Filename not specified. Subject Error! Filename not specified. [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence =20 Error! Filename not specified. Error! Filename not specified. Hello Chetana, You can use any of the 2 values for Rfixture to generate Vt curves. There is no rule that , your Rfixture should match to the PMOS or NMOS driver resistance. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any errors with respect to IV and Vt curve mismatch , just simulate for more time so that it will reach the saturation. Regards Sudarshan On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi > wrote:=20 Hello Experts, One of my IO cell has a buffer with different PMOS and NMOS impedences. PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms. In this case what should be the value of Rfixture for calculating IV VT curves ? Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ? If I do rise/pullup and fall/pulldown simulations with different Rfixture values, is it acceptable ? Best Regards Chetana - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 =20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C9020B.95AF593E Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
I gave a presentation on this subject and it is
available on the IBIS web site:
 
http://www= .vhdl.org/pub/ibis/summits/mar06/muranyi1.pdf
 
It is not in the presentation, but I remember while<= /DIV>
I was working on it I experimented with different
arrangements of the reactive elements.  For=20 example,
a series versus a parallel capacitor and/or=20 inductor.
A parallel capacitor is not as problematic as a=20 series
capacitor can be and a series inductor may not be as=
bad as a parallel inductor.  But they all have=20 di/dt
or dV/dt in their equations, which is what is missing
in the basic 2EQ/2UK IBIS equations.
 
Of course, there is nothing that should prevent an
EDA vendor or even a model maker using the *-AMS
languages to write algorithms that use differential<= /DIV>
equations to handle the reactive loads correctly...<= /DIV>
 
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D

From: owner-ibis@server.eda.org=20 [mailto:owner-ibis@server.eda.org] On Behalf Of Tom=20 Dagostino
Sent: Tuesday, August 19, 2008 2:33 AM
To:=20 'Sudarshan H N'
Cc: 'Chetana Raghuwanshi'; ibis@server.eda.org;= =20 ibis-users@server.eda.org; owner-ibis-users@server.eda.org
Subject:=20 RE: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver=20 impedance

My=20 experience with simulators is consistent with IBIS’ recommendations. = If you put=20 reactive loads in the VT curve load many times the simulations blow up.&nbs= p; If=20 you allow the SI simulator to simulate the actual load seen by the driver -= a=20 transmission line plus package plus any other parasitics, the simulations t= end=20 to match measurements.  As a model maker you will never know what kind= s of=20 loads the end user places on the driver.  So you cannot anticipate wha= t=20 reactive load to put in the model. 

 

Once=20 you get on the board and assuming (and at times this is a big assumption) t= here=20 is power/ground plane beneath the trace from the driver to the load, the lo= ad=20 seen by the driver will be a transmission line load.  If the end produ= ct’s=20 board looks like lumped RLCs there are going to be=20 problems.

 

Tom=20 Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR=20 97008
503-430-1065

503-430-1285=20 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting G= roup=20 LLC
121 North River Drive
Narragansett, RI=20 02882
401-284-1827=20

 

From:<= /B> Sudarshan H = N=20 [mailto:hn.sudarshan@gmail.com]
Sent: Monday, August 18, 2008 11= :27=20 PM
To: tom@teraspeed.com
Cc: Chetana Raghuwanshi;=20 ibis@server.eda.org; ibis-users@server.eda.org;=20 owner-ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Re: [IB= IS]=20 Different PMOS and NMOS driver impedance

 

HI,

I had a simil= ar=20 discussion about the value of the Rfixture some time back  with the IB= IS=20 group, and that time the conclusion was, as you said we should select Rfixt= ure=20 close to the impedance seen by the driver on the board i.e, around 50ohm. B= ut=20 the exact value might be different and hence these  V-t curves in IBIS= will=20 just give one set of values for given Rfixture,  and  board level= =20 simulation tools will use these V-t curves as a reference to get the actual= V-t=20 waveforms for a given load.

Still my doubt is, the pad will see som= e=20 value of RLC on the board, and IBIS discourages to use reactive loads when= =20 generating Vt curves. So how much accuracy these V-t curves will give , ass= uming=20 its only generated with Rfixture and not with other reactive=20 loads.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 10:08 PM, Tom Dagostino <tom@teraspeed.com> wrote:

No, no and=20 no.

 =

The load resistor used f= or=20 extracting the VT waveforms should represent the load seen by the driver on= the=20 circuit board.  Most reasonable circuit boards will have trace impedan= ces=20 between 40 and 75 Ohms and usually the design targets 50 Ohms.  So the= IBIS=20 model should characterize the buffer into an impedance close to that. The= =20 generally accepted value is 50 Ohms.  It has nothing at all to do with= the=20 output impedance of the driver.  You are not trying to match load/outp= ut=20 impedance or maximize power transfer, you are trying to get a macro model t= o be=20 characterized near its operating conditions.

 =

There are no such things= as IV=20 VT curves. There are no loads associated with extracting IV=20 curves.

 =

Extending the simulation= time=20 may or may not "fix" IV/VT curve mismatches.  Extending simulations ti= mes=20 will only fix mismatches if the original simulations did not allow the VT= =20 waveforms to reach their final value.  If you have a problem understan= d the=20 cause before jumping to a solution.  Just jumping to a solution in mos= t=20 cases will not work.

 =

Tom Dagostino
Teraspe= ed(R)=20 Labs
13610 SW Harness Lane
Beaverton, OR=20 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
= www.teraspeed.com

Teraspeed Consulting Group LLC=
121=20 North River Drive
Narragansett, RI 02882
401-284-1827

 =

From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Ch= etana=20 Raghuwanshi
Sent: Monday, August 18, 2008 6:51 AM
To:= =20 Sudarshan H N
Cc: ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org
Subject: Re:= =20 [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver=20 impedence

 

Hi Sudarshan,

You are right. My con= cern is=20 IV VT mismatch error.
How would it disappear by increasing the simulatio= n=20 time ?

Best=20 Regards
Chetana

-------------------------------------------------= - -------
Chetana=20 Raghuwanshi
CTO / Process & Library Technology
NXP Semiconductors= =20 India
NXP Block C, 4th Floor
MFAR Manyata Tech Park
Nagavara,=20 Bangalore-560045
Tel : +91 80 4024=20 7072
--------------------------------------------------------
Erro= r!=20 Filename not specified."Sudarshan H N" <hn.sudarshan@gmail.com>

"S= udarshan=20 H N" <hn.sudarshan@gmail.com>
Sent=20 by:

owner-ibis-users@server.eda.org

2008-= 08-18=20 06:43 PM

Error! Filename not specified.

To

Error! Filename not specified.
"Chetana Raghuwanshi" <chetana.raghuwanshi@nxp.com>=

Error! Filename not specified.

cc

Error! Filename not specified.
ibis-users@server.eda.org, ibis@server.eda.org

Error! Filename not specified.

Subject

Error! Filename not specified.
[IBIS-Users] Re: [IBIS] Different PMO= S and=20 NMOS driver impedence

 

Error! Filename not specified.

Error! Filename not=20 specified.


Hello Chetana,

You can use = any of=20 the 2 values for Rfixture to generate Vt curves. There is no rule that , yo= ur=20 Rfixture should match to the PMOS or NMOS driver resistance. But you should= =20 always use one value to generate the one set of rising and falling=20 waveforms(experts, correct me if i am wrong). If you are seeing any errors = with=20 respect to IV and Vt curve mismatch , just simulate for more time so that i= t=20 will reach the saturation.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuw= anshi=20 <<= SPAN=20 style=3D"FONT-SIZE: 13.5pt">chetana.raghuwanshi@nxp.com> wrote:

Hello=20 Experts,

One of my IO cell has a buffer with different PMOS and NMOS= =20 impedences.
PMOS impedence is approx 200 Ohms and that for NMOS is 96=20 Ohms.
In this case what should be the value of Rfixture for calculating = IV VT=20 curves ?
Would it be Rfixture1 for calculating pull down and falling=20 waveforms and Rfixture2 for calculating pull up and rising waveforms ?
I= f I=20 do rise/pullup and fall/pulldown simulations with different Rfixture values= , is=20 it acceptable ?

Best Regards
Chetana


--
This message has been scanned for vi= ruses=20 and
dangerous content by MailScanner= , and is
believed to be clean.=20



--
This message has been s= canned=20 for viruses and
dangerous content by MailScanner, and is
believed to be clean.=20


--
This message has been scanned = for=20 viruses and
dangerous content by MailScanner, and is
believed to be clean.=20

 


--
This messa= ge has=20 been scanned for viruses and
dangerous content by MailScanner, and is
be= lieved=20 to be clean.
--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------_=_NextPart_001_01C9020B.95AF593E-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 19 Aug 2008 11:15:26 -0400 From: Todd Westerhoff Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedance Sudarshan,

Are you concerned about the mismatch between your driver's NMOS/PMOS impedances and the 50 ohm load used to generate the V-T curves?

I wouldn't be.  The 50 ohm load is meant to be a reasonable match to the PCB impedance, as Tom said - not the driver's output impedance, which can vary substantially.  Simulators don't use the V-T data directly - they use the V-T curves to extract turn-on/turn-off timing data for the pullup and pulldown devices.  The simulator computes how much the pullup/pulldown is "on" or "off" at each point in time, and uses that information in conjunction with the I-V curves (which aren't predicated on a reference resistance) to predict the output's response.

The topics of V-T curves and Kt coefficients have been presented and discussed at length.  I don't have a pointer handy, but I'm guessing Arpad does ...

Todd.
Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA 01754
(978) 461-0449 x24
twesterh@sisoft.com
www.sisoft.com


Sudarshan H N wrote:
HI,

I had a similar discussion about the value of the Rfixture some time back  with the IBIS group, and that time the conclusion was, as you said we should select Rfixture close to the impedance seen by the driver on the board i.e, around 50ohm. But the exact value might be different and hence these  V-t curves in IBIS will just give one set of values for given Rfixture,  and  board level simulation tools will use these V-t curves as a reference to get the actual V-t waveforms for a given load.

Still my doubt is, the pad will see some value of RLC on the board, and IBIS discourages to use reactive loads when generating Vt curves. So how much accuracy these V-t curves will give , assuming its only generated with Rfixture and not with other reactive loads.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 10:08 PM, Tom Dagostino <tom@teraspeed.com> wrote:

No, no and no.

 

The load resistor used for extracting the VT waveforms should represent the load seen by the driver on the circuit board.  Most reasonable circuit boards will have trace impedances between 40 and 75 Ohms and usually the design targets 50 Ohms.  So the IBIS model should characterize the buffer into an impedance close to that. The generally accepted value is 50 Ohms.  It has nothing at all to do with the output impedance of the driver.  You are not trying to match load/output impedance or maximize power transfer, you are trying to get a macro model to be characterized near its operating conditions.

 

There are no such things as IV VT curves. There are no loads associated with extracting IV curves.

 

Extending the simulation time may or may not "fix" IV/VT curve mismatches.  Extending simulations times will only fix mismatches if the original simulations did not allow the VT waveforms to reach their final value.  If you have a problem understand the cause before jumping to a solution.  Just jumping to a solution in most cases will not work.

 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

 

From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chetana Raghuwanshi
Sent: Monday, August 18, 2008 6:51 AM
To: Sudarshan H N
Cc: ibis@server.eda.org; ibis-users@server.eda.org; owner-ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence

 

Hi Sudarshan,

You are right. My concern is IV VT mismatch error.
How would it disappear by increasing the simulation time ?

Best Regards
Chetana

- --------------------------------------------------------
Chetana Raghuwanshi
CTO / Process & Library Technology
NXP Semiconductors India
NXP Block C, 4th Floor
MFAR Manyata Tech Park
Nagavara, Bangalore-560045
Tel : +91 80 4024 7072
- --------------------------------------------------------
Inactive hide details for "Sudarshan H N" <hn.sudarshan@gmail.com>"Sudarshan H N" <hn.sudarshan@gmail.com>

"Sudarshan H N" <hn.sudarshan@gmail.com>
Sent by:

owner-ibis-users@server.eda.org

2008-08-18 06:43 PM

To


"Chetana Raghuwanshi" <chetana.raghuwanshi@nxp.com>

cc


ibis-users@server.eda.org, ibis@server.eda.org

Subject


[IBIS-Users] Re: [IBIS] Different PMOS and NMOS driver impedence

 


Hello Chetana,

You can use any of the 2 values for Rfixture to generate Vt curves. There is no rule that , your Rfixture should match to the PMOS or NMOS driver resistance. But you should always use one value to generate the one set of rising and falling waveforms(experts, correct me if i am wrong). If you are seeing any errors with respect to IV and Vt curve mismatch , just simulate for more time so that it will reach the saturation.

Regards
Sudarshan

On Mon, Aug 18, 2008 at 6:37 PM, Chetana Raghuwanshi <chetana.raghuwanshi@nxp.com> wrote:

Hello Experts,

One of my IO cell has a buffer with different PMOS and NMOS impedences.
PMOS impedence is approx 200 Ohms and that for NMOS is 96 Ohms.
In this case what should be the value of Rfixture for calculating IV VT curves ?
Would it be Rfixture1 for calculating pull down and falling waveforms and Rfixture2 for calculating pull up and rising waveforms ?
If I do rise/pullup and fall/pulldown simulations with different Rfixture values, is it acceptable ?

Best Regards
Chetana


- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.



- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.



- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.

--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 19 Aug 2008 18:15:13 -0700 (PDT) From: bi yuanbi Subject: [IBIS-Users] problem from spectre to IBIS model Dear Experts, I'm using Spectre simulator to generate IBIS model, but at the I/V curve simulation, there are a lot of warnings, and the simulation result is much different from Hspice simulation result. Such as: WARNING (CMI-2139): xgnd_clamp.x_pad_io.xmxidrv2/mpout@39: The bulk-source junction current exceeds `imelt'. The results computed by Virtuoso(R) Spectre(R) are now incorrect because the junction current model has been linearized. These happen for gnd clamp, power clamp, pulldown and pullup simulation, the voltage sweep is -VDD ~ 2VDD, when the voltage is too low, the simulation results (include ESD circuit) seems not correct. for example: i_gnd_clamp=40A, the current is bigger, and the Hspice simulation result is about 20A. Could you tell me how can I do that? Thanks a lot!! bi - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 22 Aug 2008 08:02:29 -0700 From: Bob Ross Subject: [IBIS-Users] Asian IBIS Summit (China) Second Announcement To All: The IBIS Open Forum is holding an Asian IBIS Summit Meeting in Shanghai, China, a major technology center on Tuesday, November 11, 2008 This is an early second announcement for longer term travel planning. Eleven companies listed below are co-sponsoring this large event to be held at the Shanghai Mart. Like in previous years, We are planning for about 150 - 200 attendees including several IBIS experts from the USA. We encourage technical contributions from Asia. We expect a full agenda of relevant material. Note, we are also planning a Summit in Tokyo, Japan on November 14 to be announced later. You may want to consider this in you travel plans. Bob Ross Teraspeed Consulting Group Lance Wang IO Methodology Inc. - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (CHINA) SECOND CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- http://www.eda.org/pub/ibis/summits/nov08a/announcement_chinese.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( C H I N A ) Time/Date: Tuesday, November 11, 2008, 8:00 AM to 5:30 PM Meeting starts at 9:00 AM Location: Shanghai Mart 2299 Yan An Road (West) Shanghai P. R. China, 200336 http://shanghaimart.kex168.com/English/aboutus/corporate.asp Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Primary Sponsor: Huawei Technologies Co-sponsors (in alphabetical order): Agilent Technologies Ansoft Cadence Design Systems Cybernet Systems Intel Corporation Mentor Graphics Corporation Signal Integrity Software (SiSoft) Sigrity Synopsys ZTE Corporation Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND We have held three successful meetings in Shenzhen, Shanghai and Beijing. This year we are meeting again in Shanghai where many Chinese and foreign high technology companies have operations. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register using the information below (in English): Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Comments: (Such as assistance for the travel requirements at the end) Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Lance Wang, IO Methology Inc. lwang@iometh.com SIGNUP DEADLINE: November 4, 2008 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: October 13, 2008 to produce the presentation booklet for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in a Chinese. Submissions from Asia are encouraged. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:15 - 9:00 Sign in, casual conversation, vendor tables 9:00 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 17:30 Presentations 17:30 - 18:30 Casual conversations, vendor tables The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned. Several presentations on IBIS applications and behavioral modeling issues, including interconnects and system components, are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. Nearby hotels are shown in the following map: http://shanghaimart.kex168.com/English/ourservices/place.asp Comply with your travel rules, such as indicated in the link below to China and Shanghai. Work with your travel agent. Notify us as a sign-up comment if you need assistance. Visas, if needed, should fall in the visit/business category: http://travel.state.gov/travel/cis_pa_tw/cis/cis_1089.html - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 26 Aug 2008 12:34:53 -0600 From: "Mirmak, Michael" Subject: [IBIS-Users] Asian IBIS Summit (Japan) Second Announcement The IBIS Open Forum will hold its third Asian IBIS Summit (Japan) Meeting on November 14 in Tokyo, Japan. This is an early second announcement to aid in advance travel planning. JEITA (Japan Electronics and Information Technology Industries Association) is the primary event sponsor with several companies, listed below, acting as co-sponsors. The event will held at JEITA headquarters in Tokyo. Several experts from outside Japan are expected to participate. We encourage technical contributions from Asia. We expect a full agenda of relevant material. Note that we are also holding a Summit in Shanghai, People's Republic of China on November 11. You may want to consider this in your travel plans. Michael Mirmak Intel Corporation Takeshi Watanabe NEC Electronics Corporation - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (JAPAN) SECOND CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( J A P A N ) Time/Date: Friday November 14, 2008, 8:30 AM to 4:00 PM Meeting starts at 9:00 AM Location: JEITA Headquarters (New Location) Chiyoda First Bldg. South Wing, 3-2-1 Nishi-Kanda, Chiyoda-ku Tokyo, 101-0065 JAPAN http://www.jeita.or.jp/english/about/location/index.htm Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) IBIS Open Forum Co-sponsors (in alphabetical order): ATE Service Corporation (Sigrity) Cybernet Systems Others to be listed after confirmation Cost: FREE, including refreshments and lunch Contact us for details regarding sponsorship BACKGROUND This year we holding the third open Asian IBIS Summit (Japan) meeting. Major Japanese companies operate in Tokyo and are affiliated with JEITA and IBIS. Our objective is to reach out internationally to communicate with the local experts, foster information exchange and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Japanese. Presenters are welcome to deliver the presentation in Japanese for the convenience of attendees so long as an English printed version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summit site and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS model development, EDA tool development, signal integrity simulation, platform and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Send to BOTH: Bob ROSS, Teraspeed Consulting Group bob@teraspeed.com Kazuyoshi SHOJI, Hitachi ULSI Systems kazuyoshi.shohji.aj@hitachi.com SIGNUP DEADLINE: November 7, 2008 Because of limited space, advance registration is required. CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Microsoft PowerPoint or Adobe PDF Presentation Copies: Available at the meeting for all attendees Presentation Deadline: November 7, 2008 to produce the presentation copies for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submissions from Asia-based presenters are encouraged. AGENDA (Tentative) 8:30 Sign in Asian IBIS Summit (Japan) 9:00 Presentations 12:00 Free lunch 12:40 Presentations 16:00 End of Meeting 16:00 Open Discussion about EDA Model (JEITA-EIA/IBIS Meeting) Everyone is welcome 17:00 Welcome Party The specific agenda is being developed. We expect seven or eight presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned. Several presentations on IBIS applications or modeling issues are expected from co-sponsor companies or their customers. Also, we will have sponsor booths this year. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. JEITA suggests the Tokyo Dome Hotel as convenient accommodation. JEITA headquarters is located near several train stations (click image): http://www.jeita.or.jp/english/about/location/index.htm - ----------------------------------------------------------------- - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 28 Aug 2008 00:59:12 +0530 From: "Prabhat Ranjan" Subject: [IBIS-Users] Dynamic behaviour of buffer - ------=_Part_79175_32605521.1219865352525 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Hello Experts, I have a driver with Slope control circuit at output pin. This circuit controls driver behaviour according to the Load on output pin. IBIS model of this buffer has only R_fixture but when I am simulating IBIS model with certain capacitive load then IBIS is not able to produce exact SPICE behaviour. My observation for mismatch is dynamic behavior of Slope control circuit with load which I am not able to model in IBIS. My question is how can I model the dynamic behaviour of Slope control circuit in IBIS ? Regards Prabhat - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_Part_79175_32605521.1219865352525 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline
Hello Experts,
 
I have a driver with Slope control circuit at output pin. This circuit controls driver behaviour according to the Load on output pin.
 
IBIS model of this buffer has only R_fixture but when I am simulating IBIS model with certain capacitive load then IBIS is not able to produce exact SPICE behaviour.
 
My observation for mismatch is dynamic behavior of Slope control circuit with load which I am not able to model in IBIS.
 
My question is how can I model the dynamic behaviour of Slope control circuit in IBIS ?
 
Regards
Prabhat

--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_Part_79175_32605521.1219865352525-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 28 Aug 2008 10:39:50 +0530 From: "Muniswara Reddy Vorugu" Subject: RE: [IBIS-Users] Dynamic behaviour of buffer This is a multi-part message in MIME format. - ------_=_NextPart_001_01C908CC.4C7CD5B7 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable Hi Prabhat, I have also, faced the same problem, while modeling Low-speed mode of USB1.1.=20 Tried many options of R_fixture and C_fixture, but did not find any improvement. =20 It looks like, we should be very lucky to get proper matching using the VT tables. To understand the cause of the inability of VT table methodology, look at=20 slide4-5 of the following presentation. http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf =20 It looks like; AMS-VHDL is the only solution.=20 The above presentation contains the concept of AMS-VHDL also. =20 Hope this helps you. =20 Regards, Muniswar =20 ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Prabhat Ranjan Sent: Thursday, August 28, 2008 12:59 AM To: ibis-users@eda.org Subject: [IBIS-Users] Dynamic behaviour of buffer =20 Hello Experts, =20 I have a driver with Slope control circuit at output pin. This circuit controls driver behaviour according to the Load on output pin. =20 IBIS model of this buffer has only R_fixture but when I am simulating IBIS model with certain capacitive load then IBIS is not able to produce exact SPICE behaviour. =20 My observation for mismatch is dynamic behavior of Slope control circuit with load which I am not able to model in IBIS. =20 My question is how can I model the dynamic behaviour of Slope control circuit in IBIS ? =20 Regards Prabhat - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01C908CC.4C7CD5B7 Content-Type: text/html; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable

Hi Prabhat,

I have also, faced the same problem, w= hile modeling Low-speed mode of USB1.1.

Tried many options of R_fixture and C_= fixture, but did not find any improvement.

 

It looks like, we should be very lucky= to get proper matching using the VT tables.

To understand the cause of the inabili= ty of VT table methodology, look at

slide4-5 of the following presentation= .

http://w= ww.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf

 

It looks like; AMS-VHDL is the only solution.

The above presentation contains the concept of AMS-VHDL also.

 

Hope this helps you.=

 

Regards,

Muniswar

 

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Prabhat Ranjan
Sent: Thursday, August 28, 2= 008 12:59 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Dynamic behaviour of buffer

 

Hello Experts,

 

I have a driver with Slope control circuit at output pin. This circ= uit controls driver behaviour according to the Load on output pin.

 

IBIS model of this buffer has only R_fixture but whe= n I am simulating IBIS model with certain capacitive load then IBIS is not able to produce exact SPICE behaviour.

 

My observation for mismatch is dynamic behavior of Slope control circuit with load which I am not able to model in IBIS.

 

My question is how can I model the dynamic behaviour of Slope contr= ol circuit in IBIS ?

 

Regards

Prabhat


- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------_=_NextPart_001_01C908CC.4C7CD5B7-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 28 Aug 2008 08:36:53 -0400 From: Todd Westerhoff Subject: Re: [IBIS-Users] Dynamic behaviour of buffer This is a multi-part message in MIME format. - --------------060708060601030004040900 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Muniswara, The other possible solution the obvious one - use a SPICE model for the buffer - which could be either a transistor model or a behavioral structural model using controlled sources. The issue here is one of portability; there are a number of EDA/SI tools that use SPICE (or HSPICE) as their simulation engine, and could therefore make use of such a model. VHDL-AMS is certainly capable of modeling this behavior, but there are far fewer tools that would be able to run the model. If you're a semiconductor vendor producing a model for end-users, that's usually a consideration - you want a model that will run in as many tools as possible. Wouldn't it be nice if we could run SPICE models as easily as we use IBIS models? It's really not that hard. You simply need a traditional IBIS buffer model that also points to a corresponding SPICE model. The traditional IBIS buffer model only represents a single case of output loading, as you pointed out. The SPICE model works in any loading condition. If a particular EDA tool can't use the SPICE model directly, it still has a conventional IBIS buffer model based on the specific loading condition. If the EDA tool is able to use the SPICE model, then the user gets both the increased precision of the SPICE model and the benefit of the IBIS use model (graphically place the device in the schematic, connect it up, and simulate). The use of the SPICE model is transparent to the user, who gets the benefit of SPICE modeling without any changes to the way they run their simulations. I'm sure you've already guessed - but that's exactly how our software works, and also _why_ it works that way. We think combining the IBIS use model with the enhanced precision of SPICE models makes good practical sense. Todd. Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@sisoft.com www.sisoft.com Muniswara Reddy Vorugu wrote: > > Hi Prabhat, > > I have also, faced the same problem, while modeling Low-speed mode of > USB1.1. > > Tried many options of R_fixture and C_fixture, but did not find any > improvement. > > > > It looks like, we should be very lucky to get proper matching using > the VT tables. > > To understand the cause of the inability of VT table methodology, look at > > slide4-5 of the following presentation. > > http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf > > > > It looks like; AMS-VHDL is the only solution. > > The above presentation contains the concept of AMS-VHDL also. > > > > Hope this helps you. > > > > Regards, > > Muniswar > > > > ------------------------------------------------------------------------ > > *From:* owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] *On > Behalf Of *Prabhat Ranjan > *Sent:* Thursday, August 28, 2008 12:59 AM > *To:* ibis-users@eda.org > *Subject:* [IBIS-Users] Dynamic behaviour of buffer > > > > Hello Experts, > > > > I have a driver with Slope control circuit at output pin. This circuit > controls driver behaviour according to the Load on output pin. > > > > IBIS model of this buffer has only R_fixture but when I am simulating > IBIS model with certain capacitive load then IBIS is not able to > produce exact SPICE behaviour. > > > > My observation for mismatch is dynamic behavior of Slope control > circuit with load which I am not able to model in IBIS. > > > > My question is how can I model the dynamic behaviour of Slope control > circuit in IBIS ? > > > > Regards > > Prabhat > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --------------060708060601030004040900 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Muniswara,

The other possible solution the obvious one - use a SPICE model for the buffer - which could be either a transistor model or a behavioral structural model using controlled sources.

The issue here is one of portability; there are a number of EDA/SI tools that use SPICE (or HSPICE) as their simulation engine, and could therefore make use of such a model.    VHDL-AMS is certainly capable of modeling this behavior, but there are far fewer tools that would be able to run the model.  If you're a semiconductor vendor producing a model for end-users, that's usually a consideration - you want a model that will run in as many tools as possible.

Wouldn't it be nice if we could run SPICE models as easily as we use IBIS models?  It's really not that hard. You simply need a traditional IBIS buffer model that also points to a corresponding SPICE model.  The traditional IBIS buffer model only represents a single case of output loading, as you pointed out.  The SPICE model works in any loading condition.  If a particular EDA tool can't use the SPICE model directly, it still has a conventional IBIS buffer model based on the specific loading condition.  If the EDA tool is able to use the SPICE model, then the user gets both the increased precision of the SPICE model and the benefit of the IBIS use model (graphically place the device in the schematic, connect it up, and simulate).
The use of the SPICE model is transparent to the user, who gets the benefit of SPICE modeling without any changes to the way they run their simulations.

I'm sure you've already guessed - but that's exactly how our software works, and also _why_ it works that way.  We think combining the IBIS use model with the enhanced precision of SPICE models makes good practical sense.

Todd.

Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA 01754
(978) 461-0449 x24
twesterh@sisoft.com
www.sisoft.com


Muniswara Reddy Vorugu wrote:

Hi Prabhat,

I have also, faced the same problem, while modeling Low-speed mode of USB1.1.

Tried many options of R_fixture and C_fixture, but did not find any improvement.

 

It looks like, we should be very lucky to get proper matching using the VT tables.

To understand the cause of the inability of VT table methodology, look at

slide4-5 of the following presentation.

http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf

 

It looks like; AMS-VHDL is the only solution.

The above presentation contains the concept of AMS-VHDL also.

 

Hope this helps you.

 

Regards,

Muniswar

 

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Prabhat Ranjan
Sent: Thursday, August 28, 2008 12:59 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Dynamic behaviour of buffer

 

Hello Experts,

 

I have a driver with Slope control circuit at output pin. This circuit controls driver behaviour according to the Load on output pin.

 

IBIS model of this buffer has only R_fixture but when I am simulating IBIS model with certain capacitive load then IBIS is not able to produce exact SPICE behaviour.

 

My observation for mismatch is dynamic behavior of Slope control circuit with load which I am not able to model in IBIS.

 

My question is how can I model the dynamic behaviour of Slope control circuit in IBIS ?

 

Regards

Prabhat


- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.

--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --------------060708060601030004040900-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #120 *************************