From: owner-ibis-users@eda.org (ibis-users)
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Subject: ibis-users V1 #145
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ibis-users          Thursday, August 26 2010          Volume 01 : Number 145




----------------------------------------------------------------------

Date: Wed, 25 Aug 2010 10:45:49 -0700
From: "Muranyi, Arpad" <Arpad_Muranyi@mentor.com>
Subject: RE: [IBIS-Users] input stimulus for extracting IBIS VT curves

Scott,

Actually IBIS v5.0 does have a few new features which attempt to
give ways to modeling those effects.  They may not be perfect,
but do allow some amount of modeling them.  Also, if the "built-in"
keywords are not sufficient, one can always make use of the *-AMS
languages...  (I know this is a red herring to some, but it is 
there, and I see more and more simulators come out with at least
Verilog-A capabilities, which is one of those languages in IBIS).

But the problem is that the behavioral modeling of the intricate
details of edge rate degradation and gate modulation effects due
to power noise is very difficult.  There are lots of interrelated
interactions between the various stages of the buffer through the
parasitic capacitances (including Mr. Miller) which makes it very
difficult to write a behavioral model that includes all these
effects especially during transitions.

Arpad
====================================================================

- -----Original Message-----
From: Scott McMorrow [mailto:scott@teraspeed.com] 
Sent: Wednesday, August 25, 2010 12:33 PM
To: Muranyi, Arpad
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] input stimulus for extracting IBIS VT curves


  Arpad

I agree with you on input edge rate to a buffer.  Most devices have 
extremely fast input rise/fall time into the predriver, since loading is

so low at this point in the circuit.  What is more important for IBIS 
buffer modeling is the predriver voltage rail.  Unfortunately, in IBIS 
there is no way to correctly model predriver power supply voltage 
modulation effects, which are very real under SSO conditions.

regards,

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed(r) is the registered service mark of
Teraspeed Consulting Group LLC


On 8/25/2010 1:26 PM, Muranyi, Arpad wrote:
> Andy,
>
> Regarding your comments on the transistor models, while it is
> a reasonable concept, it usually doesn't matter.  I verified
> this by sweeping the stimulus edge rate from very fast to very
> slow, and overlaid the output waveforms, and didn't see any
> difference, other than a time shift due to the input stimulus
> reaching the threshold levels increasingly later with the slower
> slopes.  This can be explained by the fact that most transistor
> buffer models have multiple stages in them, and the final stage
> is so far removed from the first stage that its waveform is
> only determined by the transistor sizing relationships between
> the stages, but not by the stimulus waveform.
>
> Your reasoning would only be true when the transistor model
> doesn't have any pre-driver stage(s), or very few of them.  But
> I would strongly advise against using such transistor models
> for IBIS data extractions, because if the output waveform is
> a factor of the stimulus, then the model maker can end up making
> all kinds of incorrect IBIS models if they don't know what the
> waveform looks like on the core side of this model.
>
> Regarding the stimulus to the B-element (or the like), it is true
> that in terms of its operation it doesn't matter what the edge
> rate is, the output waveform will still be the same.  But you
> need to consider that due to the slow stimulus waveforms you will
> get a certain delay in the transition.  This can cause complications
> if the user forgets that the stimulus supposed to be a 0-1 volt
> waveform, and the thresholds are set to 0.2 and 0.8 if I remember
> correctly.  I have seen many times people applying a source to the
> input of the B-element with a voltage swing that used the supply
> voltage value of the buffer, for example 0 to 3.3 volts.  With a
> slow stimulus edge rate, the rising edge will trigger sooner than
> the falling edge very noticeably.  (In other words you get duty
> cycle distortions from the IBIS model while the transistor model
> didn't do that).
>
> Even if this was handled properly by the user, similar shifting
> could occur due to the different stimulus edge rates between the
> transistor and IBIS buffer stimuli.  I had people often show me
> "discrepancies" between the transistor waveforms and the IBIS
> waveforms which were due to that, and they had no clue why the
> IBIS and transistor waveforms were shifted apart in time.
>
> These are the reasons I am suggesting the use of fast edge rates...
>
> Arpad
> ===================================================================
>
>
>
>
>
> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
> Behalf Of Andrew Ingraham
> Sent: Wednesday, August 25, 2010 11:14 AM
> To: ibis-users@eda.org
> Subject: Re: [IBIS-Users] input stimulus for extracting IBIS VT curves
>
> I disagree that the edge should be "as fast as possible".
>
> For the IBIS models used in HSPICE, my recollection is that HSPICE
> treats it as a switch, waiting until the (digital) input waveform
> crosses a threshold, then switching the IBIS model.  The edge rate of
> that digital stimulus waveform therefore shouldn't matter ... except
> that very slow edge rate causes a known time delay before the IBIS
> modeled device switches, and extremely fast edge rates might make the
> simulation run slow or lead to convergence problems.  Theoretically
> it's good to make it fast so that it works like an instantaneous
> binary switch, but there could be practical problems if you try to do
> that.
>
> For the transistor (SPICE) models, ideally you should attempt to match
> the actual waveform (edge rate and amplitude) that is at that point
> inside the IC, NOT the "fastest possible edge rate".  Hopefully that
> is what the IBIS modeler did too.  Using a faster edge rate than what
> those transistors normally see, makes it unrealistic.
>
> Andy
>

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------------------------------

Date: Fri, 30 Jul 2010 17:41:39 +0800
From: Amit KUMAR <amit-hpc.kumar@st.com>
Subject: [IBIS-Users] Parser for verifying syntax of .EBD file

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 Hello All,

Do we have any parser which can check the syntax of .ebd file?

Regards
Amit


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<p class=3DMsoNormal><span style=3D'color:#1F497D'>&nbsp;Hello All,<o:p></o=
:p></span></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>Do we have any parser wh=
ich can
check the syntax of .ebd file?<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>Regards<o:p></o:p></span=
></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>Amit<o:p></o:p></span></=
p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

</div>

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------------------------------

Date: Wed, 25 Aug 2010 12:13:42 -0400
From: Andrew Ingraham <a.ingraham@ieee.org>
Subject: Re: [IBIS-Users] input stimulus for extracting IBIS VT curves

I disagree that the edge should be "as fast as possible".

For the IBIS models used in HSPICE, my recollection is that HSPICE
treats it as a switch, waiting until the (digital) input waveform
crosses a threshold, then switching the IBIS model.  The edge rate of
that digital stimulus waveform therefore shouldn't matter ... except
that very slow edge rate causes a known time delay before the IBIS
modeled device switches, and extremely fast edge rates might make the
simulation run slow or lead to convergence problems.  Theoretically
it's good to make it fast so that it works like an instantaneous
binary switch, but there could be practical problems if you try to do
that.

For the transistor (SPICE) models, ideally you should attempt to match
the actual waveform (edge rate and amplitude) that is at that point
inside the IC, NOT the "fastest possible edge rate".  Hopefully that
is what the IBIS modeler did too.  Using a faster edge rate than what
those transistors normally see, makes it unrealistic.

Andy

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------------------------------

Date: Mon, 2 Aug 2010 18:54:20 +0530
From: <suraj.sukumarannair@wipro.com>
Subject: [IBIS-Users] Ramp calculation in O/P, Tri-state, I/O, buffer ibis model

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Hi All,



 I had a query regarding the ramp calculation done in ibis file. Why is
it that we consider the falling waveform w.r.t Vfix=3Dvdd and rising
waveform w.r.t Vfix=3D0 tables instead of the other two tables while
calculating Ramp?



Regards

Suraj


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<p class=3DMsoNormal><font size=3D2 face=3DArial><span style=3D'font-size:1=
0.0pt;
font-family:Arial'>Hi All,<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span style=3D'font-size:1=
0.0pt;
font-family:Arial'><o:p>&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span style=3D'font-size:1=
0.0pt;
font-family:Arial'>&nbsp;I had a query regarding the ramp calculation done =
in ibis
file. Why is it that we consider the falling waveform w.r.t Vfix=3Dvdd and =
rising
waveform w.r.t Vfix=3D0 tables instead of the other two tables while calcul=
ating
Ramp?<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span style=3D'font-size:1=
0.0pt;
font-family:Arial'><o:p>&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span style=3D'font-size:1=
0.0pt;
font-family:Arial'>Regards<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span style=3D'font-size:1=
0.0pt;
font-family:Arial'>Suraj<o:p></o:p></span></font></p>

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------------------------------

Date: Fri, 30 Jul 2010 09:26:47 +0200
From: "Lenski, Eckhard (NSN - DE/Munich)" <eckhard.lenski@nsn.com>
Subject: [IBIS-Users] RE: [IBIS] Mismatch between ibischk and load lines

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Hello Peggy,
=20
as Arpad pointed out, there might be many reason that causes the ibischeck =
message.
=20
but please be aware, that the checker is using the sum of the static curves=
 .
=20
so for High  :  [pullup] + [gnd clamp] + [power clamp]
and for Low :  [pulldown] + [gnd clamp] + [power clamp]
=20
=20
regards
Eckhard


Mit freundlichen Gr=FC=DFen / Best regards / Cordiali saluti / yst=E4v=E4ll=
isin terveisin=20

Eckhard Lenski=20

Nokia Siemens Networks GmbH & Co. KG=20


NWS EP CP HW RD CAD libraries=20

Balanstr. 59=20

80240 M=FCnchen=20
Germany=20
phone : +49 89 5159 17080=20
email: eckhard.lenski@nsn.com=20

http://www.nokiasiemensnetworks.com/ibis=20


Nokia Siemens Networks GmbH & Co. KG=20

Sitz der Gesellschaft: M=FCnchen / Registered office: Munich=20

Registergericht: M=FCnchen / Commercial registry: Munich, HRA 88537=20

WEEE-Reg.-Nr.: DE 52984304=20

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works Management GmbH=20

Gesch=E4ftsleitung / Board of Directors: Lydia Sommer, Olaf Horsthemke=20

Vorsitzender des Aufsichtsrats / Chairman of supervisory board: Herbert Mer=
z=20

Sitz der Gesellschaft: M=FCnchen / Registered office: Munich=20

Registergericht: M=FCnchen / Commercial registry: Munich, HRB 163416=20

=20

________________________________

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of ext Alavi=
, Peggy
Sent: Thursday, July 29, 2010 11:52 PM
To: ibis-users@eda.org; ibis@eda-stds.org
Subject: [IBIS] Mismatch between ibischk and load lines



Hello,

=20

I am working on an IBIS Model and the golden parser (I have used 4.1, 4.2, =
and 5.0 and my model is IBIS 4.2) gives me errors (on the high side - pull =
up curve) on one of my outputs. I have independently verified the load line=
 and where it crosses the PD and PU curves, and the crossing exactly matche=
s my transient end values, and does not match what the parser is claiming t=
he crossings are. What could I be doing wrong?

=20

Best,

=20

- -Peggy

=20


- --=20
This message has been scanned for viruses and=20
dangerous content by MailScanner <http://www.mailscanner.info/> , and is=20
believed to be clean.=20

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<BODY lang=3DEN-US link=3Dblue vLink=3Dpurple>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2 face=
=3DArial>Hello=20
Peggy,</FONT></SPAN></DIV>
<DIV><FONT color=3D#0000ff size=3D2 face=3DArial></FONT>&nbsp;</DIV>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2 face=
=3DArial>as=20
Arpad pointed out, there might be many reason that causes the ibischeck=20
message.</FONT></SPAN></DIV>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2=20
face=3DArial></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2 face=
=3DArial>but=20
please be aware, that the checker is using the sum of the static curves=20
.</FONT></SPAN></DIV>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2=20
face=3DArial></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2 face=
=3DArial>so for=20
High&nbsp; :&nbsp; [pullup] + [gnd clamp] + [power clamp]</FONT></SPAN></DI=
V>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2 face=
=3DArial>and=20
for Low : &nbsp;[pulldown] + [gnd clamp] + [power clamp]</FONT></SPAN></DIV>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2=20
face=3DArial></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2=20
face=3DArial></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2=20
face=3DArial>regards</FONT></SPAN></DIV>
<DIV><SPAN class=3D433032307-30072010><FONT color=3D#0000ff size=3D2=20
face=3DArial>Eckhard</FONT></SPAN></DIV><!-- Converted from text/rtf format=
 --><BR>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Mit freundlichen Gr=
=FC=DFen / Best=20
regards / Cordiali saluti / yst=E4v=E4llisin terveisin</FONT></SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Eckhard Lenski=20
</FONT></SPAN></P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Nokia Siemens Networ=
ks GmbH=20
&amp; Co. KG</FONT></SPAN> </P><BR>
<P><SPAN lang=3Den-gb><FONT size=3D2 face=3D"Courier New">NWS EP CP HW RD C=
AD=20
libraries </FONT></SPAN></P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Balanstr. 59</FONT><=
/SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">80240 M=FCnchen</FON=
T></SPAN>=20
<BR><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Germany=20
</FONT></SPAN><BR><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">phone=
 : +49 89=20
5159 17080</FONT></SPAN> <BR><SPAN lang=3Dde><FONT size=3D2=20
face=3D"Courier New">email: eckhard.lenski@nsn.com</FONT></SPAN> </P>
<P><SPAN lang=3Den-gb><FONT size=3D2 face=3D"Courier New"><A=20
href=3D"http://www.nokiasiemensnetworks.com/ibis">http://www.nokiasiemensne=
tworks.com/ibis</A>=20
</FONT></SPAN></P><BR>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Nokia Siemens Networ=
ks GmbH=20
&amp; Co. KG</FONT></SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Sitz der Gesellschaf=
t: M=FCnchen=20
/ Registered office: Munich</FONT></SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Registergericht: M=
=FCnchen /=20
Commercial registry: Munich, HRA 88537</FONT></SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">WEEE-Reg.-Nr.: DE=20
52984304</FONT></SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Pers=F6nlich haftend=
e=20
Gesellschafterin / General Partner: Nokia Siemens Networks Management=20
GmbH</FONT></SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Gesch=E4ftsleitung /=
 Board of=20
Directors: Lydia Sommer, Olaf Horsthemke</FONT></SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Vorsitzender des Auf=
sichtsrats=20
/ Chairman of supervisory board: Herbert Merz</FONT></SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Sitz der Gesellschaf=
t: M=FCnchen=20
/ Registered office: Munich</FONT></SPAN> </P>
<P><SPAN lang=3Dde><FONT size=3D2 face=3D"Courier New">Registergericht: M=
=FCnchen /=20
Commercial registry: Munich, HRB 163416</FONT></SPAN> </P>
<DIV>&nbsp;</DIV><BR>
<DIV dir=3Dltr lang=3Dde class=3DOutlookMessageHeader align=3Dleft>
<HR tabIndex=3D-1>
<FONT size=3D2 face=3DTahoma><B>From:</B> owner-ibis@eda.org=20
[mailto:owner-ibis@eda.org] <B>On Behalf Of </B>ext Alavi, Peggy<BR><B>Sent=
:</B>=20
Thursday, July 29, 2010 11:52 PM<BR><B>To:</B> ibis-users@eda.org;=20
ibis@eda-stds.org<BR><B>Subject:</B> [IBIS] Mismatch between ibischk and lo=
ad=20
lines<BR></FONT><BR></DIV>
<DIV></DIV>
<DIV class=3DWordSection1>
<P class=3DMsoNormal><SPAN=20
style=3D"FONT-FAMILY: 'Arial','sans-serif'; COLOR: navy; FONT-SIZE: 10pt">H=
ello,<o:p></o:p></SPAN></P>
<P class=3DMsoNormal><SPAN=20
style=3D"FONT-FAMILY: 'Arial','sans-serif'; COLOR: navy; FONT-SIZE: 10pt"><=
o:p>&nbsp;</o:p></SPAN></P>
<P class=3DMsoNormal><SPAN=20
style=3D"FONT-FAMILY: 'Arial','sans-serif'; COLOR: navy; FONT-SIZE: 10pt">I=
 am=20
working on an IBIS Model and the golden parser (I have used 4.1, 4.2, and 5=
.0=20
and my model is IBIS 4.2) gives me errors (on the high side =96 pull up cur=
ve) on=20
one of my outputs. I have independently verified the load line and where it=
=20
crosses the PD and PU curves, and the crossing exactly matches my transient=
 end=20
values, and does not match what the parser is claiming the crossings are. W=
hat=20
could I be doing wrong?<o:p></o:p></SPAN></P>
<P class=3DMsoNormal><SPAN=20
style=3D"FONT-FAMILY: 'Arial','sans-serif'; COLOR: navy; FONT-SIZE: 10pt"><=
o:p>&nbsp;</o:p></SPAN></P>
<P class=3DMsoNormal><SPAN=20
style=3D"FONT-FAMILY: 'Arial','sans-serif'; COLOR: navy; FONT-SIZE: 10pt">B=
est,<o:p></o:p></SPAN></P>
<P class=3DMsoNormal><SPAN=20
style=3D"FONT-FAMILY: 'Arial','sans-serif'; COLOR: navy; FONT-SIZE: 10pt"><=
o:p>&nbsp;</o:p></SPAN></P>
<P class=3DMsoNormal><SPAN=20
style=3D"FONT-FAMILY: 'Arial','sans-serif'; COLOR: navy; FONT-SIZE: 10pt">-=
Peggy<o:p></o:p></SPAN></P>
<P class=3DMsoNormal><SPAN=20
style=3D"FONT-FAMILY: 'Arial','sans-serif'; COLOR: navy; FONT-SIZE: 10pt"><=
o:p>&nbsp;</o:p></SPAN></P></DIV><BR>--=20
<BR>This message has been scanned for viruses and <BR>dangerous content by =
<A=20
href=3D"http://www.mailscanner.info/"><B>MailScanner</B></A>, and is <BR>be=
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<br />This message has been scanned for viruses and
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------------------------------

Date: Thu, 26 Aug 2010 22:38:54 -0400
From: Andrew Ingraham <a.ingraham@ieee.org>
Subject: Re: [IBIS-Users] IBIS Simulation algorithm

> I also observe that, even if I remove the V-T table and supply only the
> [Ramp] information, HSPICE is able to simulate the buffer model with almost
> the same accuracy. [I have 4 VT (2 Rise and 2 Fall) tables originally]

Originally, IBIS had no V-T tables, and it worked OK.  They were added
in a later revision to improve the transient accuracy.

Even after they were added to the IBIS spec, many simulators did not
use them.  (Hspice took a while to catch up.)

How or why does it work without V-T tables?  For most buffers,
waveforms are largely determined by the interaction between the
transistors (by way of their drive strengths in their On state), and
the load.  How a driver gets from Off to On, is far less important
than how it interacts with the load, as described by its I-V curves.

For many buffers, their transistors are switched between Off and On
states faster than their outputs slew from L to H or H to L, because
of that interaction with the load.  That means they spend most of the
time either Off (I=0), or fully On (I described by I-V table).

Without V-T tables, the simulator transitions between one transistor
fully On, to the other transistor fully On, over some short period of
time.  The Ramp data helps the simulator control how quickly it should
go from one state to the other.

Andy

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------------------------------

Date: Tue, 24 Aug 2010 09:48:56 -0700
From: Bob Ross <bob@teraspeed.com>
Subject: [IBIS-Users] [IBIS] Asian IBIS Summit (China) Second Announcement

To All:

The IBIS Open Forum is holding an Asian IBIS Summit Meeting in
Shenzhen, China, a major technology center on Tuesday, November 9, 2010
This is the second announcement for longer term travel planning.

Several companies listed below are co-sponsoring this large event
to be held at the Four Points by Sheraton, Shenzhen.  Like in previous
years, we are planning for a large number of attendees including
several IBIS experts from the USA.

We encourage technical contributions from Asia.  We expect a full
agenda of relevant material.

For travel consideration, two other Asian IBIS Summits follow this
event:

   Taipei, Taiwan, Friday, November 12, Sherwood Hotel
   Tokyo, Japan, Monday, November 15, JEITA headquarters

Announcements for these will be issued later.

Bob Ross
Teraspeed Consulting Group

Lance Wang
IO Methodology Inc.


- -----------------------------------------------------------------------
                          ASIAN IBIS SUMMIT (CHINA)
                              SECOND CALL FOR
                       PARTICIPATION AND PRESENTATIONS
- -----------------------------------------------------------------------

http://www.eda.org/pub/ibis/summits/nov10a/announcement_chinese.pdf

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

               A S I A N   I B I S   S U M M I T   ( C H I N A )

Time/Date:  Tuesday, November 9, 2010, 8:00 AM to 5:30 PM
             Meeting starts at 9:00 AM

Location:   Four Points by Sheraton
             5 Guihua Road
             Futian Free Trade Zone
             Shenzhen, Guangdong 518038
             P. R. China

http://www.starwoodhotels.com/fourpoints/property/overview/index.html?propertyID=1489&

EM=VTY_FP_1489_shenzhen_overview

or http://tinyurl.com/2s6esb

Content:    Presentations and Discussions

Purpose:    Solicit and exchange IBIS and interconnect model related
             information and ideas.

Primary Sponsor:
             Huawei Technologies

Co-sponsors (in alphabetical order):
             Agilent Technologies, Ansoft Corporation,
             Cadence Design Systems, Cybernet, Intel Corporation,
             IO Methodology, Mentor Graphics Corporation,
             Signal Integrity Software (SiSoft),
             Sigrity, Synopsys, and ZTE Corporation.

Cost:       FREE, including refreshments and buffet lunch

Vendors:    Some vendors will have information tables outside
             the meeting room

             Contact us for details regarding sponsorship.

BACKGROUND

    We have held five successful meetings in Shenzhen, Shanghai and Beijing.
    This year we are meeting again in Shenzhen where many Chinese and
    foreign high technology companies operate.  These events are archived
    along with all our other Summits:

      http://www.eda.org/pub/ibis/summits/

    Our objective is to reach out internationally to communicate with
    the local experts and to learn of regional concerns.

CONFERENCE LANGUAGE

    The conference language is English, but we will plan for technical
    translations in English and Chinese.  So presenters can optionally
    deliver in Chinese as long as an English version of the material is
    available.

IBIS SUMMIT

    This meeting will be conducted as a formal IBIS Summit Meeting.
    Presentations will be archived in an electronic format on our
    Summits site, and minutes of the meeting will be issued.  However,
    no formal decisions requiring votes will be planned.

CALL FOR PARTICIPANTS

    People involved in IBIS and interconnect model development, EDA
    tool development, and digital circuit design are invited to
    participate to the Summit meeting.  If you plan to participate,
    please register using the information below (in English):

      Name:
      E-mail address:

      Company:
      Top-level Web Link:

      Country:
      Telephone:

      Comments:
        (Such as assistance for the travel requirements at the end)

    Send to BOTH:

      Bob Ross, Teraspeed Consulting Group    bob@teraspeed.com
      Lance Wang, IO Methology Inc.           lwang@iometh.com

    SIGNUP DEADLINE: November 4, 2010

CALL FOR PRESENTATIONS

    We are seeking presentations from individuals who have IBIS and
    interconnect modeling experiences or issues.  If we have to
    select presentations for the number of time slots available, we
    will give preferential consideration to presentations from Asia.

    Presentation Format:   LCD Projection from meeting laptop computer

    Time:                  15-30 Minutes including questions

    Electronic Archival:   All presentations will uploaded to our public
                           IBIS Summit archives

    Electronic Format:     Power Point or Acrobat

    Presentation Booklet:  Available at the meeting for all attendees

    Presentation Deadline: October 12, 2010 to produce the presentation
                           booklet for the meeting

    If you plan a presentation, please ADD to the above registration
    information:

      Title of Presentation:

      Estimated Time:
        (30 minutes or less)

    We will notify you of acceptance and may follow up with questions
    when we form the program agenda.

    Note: Vendor promotional or business information is prohibited.
    Submitted presentations must be in English, although the delivery
    can be in Mandarin.

    Submissions from Asia are encouraged along with other submissions
    world-wide.  Topics may include behavioral modeling of buffers,
    interconnects or other system components.

AGENDA

    8:15 -   9:00  Vendor table setup and tables
    8:30 -   9:00  Sign in
    9:00 -  12:00  Presentations
    12:00 - 13:30  Free buffet lunch, vendor tables
    13:30 - 17:00  Presentations

    The specific agenda is being developed.  We expect nine or ten
    presentations covering a range of issues from existing customer
    experiences, existing clarifications and some future technical
    directions in IBIS.

    Several major IBIS Committee presentations from IBIS officers or
    active members are planned.

    Several presentations on IBIS applications and behavioral modeling
    issues, including interconnects and system components, are expected
    from co-sponsor companies and/or their customers.

LIST OF NEARBY HOTELS AND TRAVEL RULES

    Hotels in all price ranges can be found through internet searches.

    Comply with your travel rules, such as indicated in the link
    below to China and Shenzhen.  Work with your travel agent.  Notify
    us as a sign-up comment if you need assistance.  Visas, if needed,
    should fall in the visit/business category:

      http://travel.state.gov/travel/cis_pa_tw/cis/cis_1089.html

- -----------------------------------------------------------------
- -- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
121 North River Drive              13610 SW Harness Lane
Narragansett, RI 02882             Beaverton, OR 97008
401-284-1827                       503-430-1065
http://www.teraspeed.com           503-246-8048 Direct
bob@teraspeed.com

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC


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------------------------------

Date: Mon, 09 Aug 2010 13:45:44 -0700
From: Bob Ross <bob@teraspeed.com>
Subject: [IBIS-Users] Asian IBIS Summit (China) First Announcement

To All:

The IBIS Open Forum is holding an Asian IBIS Summit Meeting in
Shenzhen, China, a major technology center on Tuesday, November 9, 2010
This is an early initial announcement for longer term travel planning.

Several companies listed below are co-sponsoring this large event
to be held at the Four Points by Sheraton, Shenzhen.  Like in previous
years, we are planning for a large number of attendees including
several IBIS experts from the USA.

We encourage technical contributions from Asia.  We expect a full
agenda of relevant material.

For travel consideration, two other Asian IBIS Summits follow this
event:

   Taipei, Taiwan, Friday, November 12, Sherwood Hotel
   Tokyo, Japan, Monday, November 15, JEITA headquarters

Announcements for these will be issued later.

Bob Ross
Teraspeed Consulting Group

Lance Wang
IO Methodology Inc.


- -----------------------------------------------------------------------
                          ASIAN IBIS SUMMIT (CHINA)
                               FIRST CALL FOR
                       PARTICIPATION AND PRESENTATIONS
- -----------------------------------------------------------------------

http://www.eda.org/pub/ibis/summits/nov10a/announcement_chinese.pdf

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

               A S I A N   I B I S   S U M M I T   ( C H I N A )

Time/Date:  Tuesday, November 9, 2010, 8:00 AM to 5:30 PM
             Meeting starts at 9:00 AM

Location:   Four Points by Sheraton
             5 Guihua Road
             Futian Free Trade Zone
             Shenzhen, Guangdong 518038
             P. R. China

http://www.starwoodhotels.com/fourpoints/property/overview/index.html?propertyID=1489&EM=VTY_FP_1489_shenzhen_overview

or http://tinyurl.com/2s6esb

Content:    Presentations and Discussions

Purpose:    Solicit and exchange IBIS and interconnect model related
             information and ideas.

Primary Sponsor:
             Huawei Technologies

Co-sponsors (in alphabetical order):
             Agilent Technologies, Ansoft Corporation,
             Cadence Design Systems, Cybernet, Intel Corporation,
             IO Methodology, Mentor Graphics Corporation,
             Signal Integrity Software (SiSoft),
             Sigrity, Synopsys, and ZTE Corporation.

Cost:       FREE, including refreshments and buffet lunch

Vendors:    Some vendors will have information tables outside
             the meeting room

             Contact us for details regarding sponsorship.

BACKGROUND

    We have held five successful meetings in Shenzhen, Shanghai and Beijing.
    This year we are meeting again in Shenzhen where many Chinese and
    foreign high technology companies operate.  These events are archived
    along with all our other Summits:

      http://www.eda.org/pub/ibis/summits/

    Our objective is to reach out internationally to communicate with
    the local experts and to learn of regional concerns.

CONFERENCE LANGUAGE

    The conference language is English, but we will plan for technical
    translations in English and Chinese.  So presenters can optionally
    deliver in Chinese as long as an English version of the material is
    available.

IBIS SUMMIT

    This meeting will be conducted as a formal IBIS Summit Meeting.
    Presentations will be archived in an electronic format on our
    Summits site, and minutes of the meeting will be issued.  However,
    no formal decisions requiring votes will be planned.

CALL FOR PARTICIPANTS

    People involved in IBIS and interconnect model development, EDA
    tool development, and digital circuit design are invited to
    participate to the Summit meeting.  If you plan to participate,
    please register using the information below (in English):

      Name:
      E-mail address:

      Company:
      Top-level Web Link:

      Country:
      Telephone:

      Comments:
        (Such as assistance for the travel requirements at the end)

    Send to BOTH:

      Bob Ross, Teraspeed Consulting Group    bob@teraspeed.com
      Lance Wang, IO Methology Inc.           lwang@iometh.com

    SIGNUP DEADLINE: November 4, 2010

CALL FOR PRESENTATIONS

    We are seeking presentations from individuals who have IBIS and
    interconnect modeling experiences or issues.  If we have to
    select presentations for the number of time slots available, we
    will give preferential consideration to presentations from Asia.

    Presentation Format:   LCD Projection from meeting laptop computer

    Time:                  15-30 Minutes including questions

    Electronic Archival:   All presentations will uploaded to our public
                           IBIS Summit archives

    Electronic Format:     Power Point or Acrobat

    Presentation Booklet:  Available at the meeting for all attendees

    Presentation Deadline: October 12, 2010 to produce the presentation
                           booklet for the meeting

    If you plan a presentation, please ADD to the above registration
    information:

      Title of Presentation:

      Estimated Time:
        (30 minutes or less)

    We will notify you of acceptance and may follow up with questions
    when we form the program agenda.

    Note: Vendor promotional or business information is prohibited.
    Submitted presentations must be in English, although the delivery
    can be in Mandarin.

    Submissions from Asia are encouraged along with other submissions
    world-wide.  Topics may include behavioral modeling of buffers,
    interconnects or other system components.

AGENDA

    8:15 -   9:00  Vendor table setup and tables
    8:30 -   9:00  Sign in
    9:00 -  12:00  Presentations
    12:00 - 13:30  Free buffet lunch, vendor tables
    13:30 - 17:00  Presentations

    The specific agenda is being developed.  We expect nine or ten
    presentations covering a range of issues from existing customer
    experiences, existing clarifications and some future technical
    directions in IBIS.

    Several major IBIS Committee presentations from IBIS officers or
    active members are planned.

    Several presentations on IBIS applications and behavioral modeling
    issues, including interconnects and system components, are expected
    from co-sponsor companies and/or their customers.

LIST OF NEARBY HOTELS AND TRAVEL RULES

    Hotels in all price ranges can be found through internet searches.

    Comply with your travel rules, such as indicated in the link
    below to China and Shenzhen.  Work with your travel agent.  Notify
    us as a sign-up comment if you need assistance.  Visas, if needed,
    should fall in the visit/business category:

      http://travel.state.gov/travel/cis_pa_tw/cis/cis_1089.html

- -----------------------------------------------------------------

- -- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
121 North River Drive              13610 SW Harness Lane
Narragansett, RI 02882             Beaverton, OR 97008
401-284-1827                       503-430-1065
http://www.teraspeed.com           503-246-8048 Direct
bob@teraspeed.com

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC


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|with the appropriate command message(s) in the body:
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|  unsubscribe ibis-users <optional e-mail address, if different>
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|
|  http://www.eda-stds.org/pub/ibis/email_archive/ Recent
|  http://www.eda-stds.org/pub/ibis/users_archive/ Recent
|  http://www.eda-stds.org/pub/ibis/email/         E-mail since 1993

------------------------------

Date: Fri, 6 Aug 2010 10:26:12 -0400
From: "Lance Wang" <lwang@iometh.com>
Subject: RE: [IBIS-Users] error msg in s2ibis3

This is a multi-part message in MIME format.

- ------=_NextPart_000_002D_01CB3551.CB92CDD0
Content-Type: text/plain;
	charset="us-ascii"
Content-Transfer-Encoding: 7bit

Check out the runlvl setting in HSpice. S2ibis3 expecting to control the
time steps. You can set runlvl=0 to make it happens.

 

 

Lance Wang

978-764-2298

IO Methodology Inc.

www.iometh.com

 

 

 

 

  _____  

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of Ramesh Raghavan
Sent: Friday, August 06, 2010 4:11 AM
To: 'ji xiao'
Cc: 'ibis-users'
Subject: RE: [IBIS-Users] error msg in s2ibis3

 

Hi   Yauncheng,

                          If the issue is that you have more than 100 points
in .out files. Then,there is  a way to do this but I do not know if this is
the really the best/efficient way. 

1.       You can use the iterate command option in .s2i.  Edit the .spi
files and reduce the step/range in .spi file   and do a hspice simulation of
all .spi files (which have more than 100 points)   and generate the .out
files and rerun the s2ibis3 tool for the IBIS model

 

 Does this help you?

 

Thanks,

Ramesh

 

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of ji xiao
Sent: Friday, August 06, 2010 12:59 PM
To: ibis-users
Subject: [IBIS-Users] error msg in s2ibis3

 

Dear all,
when I use s2ibis3 to convert an HSPICE file to IBIS file, I got the error
msg shown as below:
Exception in thread "main" java.lang.ArrayIndexOutOfBoundsException: -1
   at sortVIData.sortVIData(ibisModel, ibisVItable, ibisVItable,
ibisVItable, ibisVItable) (Unknown Source)
   at analyzePin.analyzePin(ibisPin, ibisPin, ibisPin, ibisPin, ibisPin,
ibisPin, int, java.lang.String, java.lang.String, java.lang.String, int,
int) (Unknown Source)
   at analyzeComponent.analyzeComponent(int, int, int, java.lang.String)
(Unknown Source)
   at s2ibis3.main(java.lang.String[]) (Unknown Source)

It seems that the data points number of IV curves out of the range--100. Is
there any way to solve the problem?

Thanks and regards,
Yuancheng

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<p class=3DMsoNormal><font size=3D2 color=3Dblue face=3D"Franklin Gothic Bo=
ok"><span
style=3D'font-size:11.0pt;font-family:"Franklin Gothic Book";color:blue'>Ch=
eck
out the runlvl setting in HSpice. S2ibis3 expecting to control the time ste=
ps. You
can set runlvl=3D0 to make it happens.<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3Dblue face=3D"Franklin Gothic Bo=
ok"><span
style=3D'font-size:11.0pt;font-family:"Franklin Gothic Book";color:blue'><o=
:p>&nbsp;</o:p></span></font></p>

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ok"><span
style=3D'font-size:11.0pt;font-family:"Franklin Gothic Book";color:blue'><o=
:p>&nbsp;</o:p></span></font></p>

<div>

<p class=3DMsoNormal><font size=3D2 color=3Dblue face=3DArial><span style=
=3D'font-size:
10.0pt;font-family:Arial;color:blue'>Lance Wang</span></font><font color=3D=
blue
face=3D"Franklin Gothic Book"><span style=3D'font-family:"Franklin Gothic B=
ook";
color:blue'><o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3Dblue face=3DArial><span style=
=3D'font-size:
10.0pt;font-family:Arial;color:blue'>978-764-2298</span></font><font
color=3Dblue face=3D"Franklin Gothic Book"><span style=3D'font-family:"Fran=
klin Gothic Book";
color:blue'><o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3Dblue face=3D"Franklin Gothic Bo=
ok"><span
style=3D'font-size:10.0pt;font-family:"Franklin Gothic Book";color:blue'>IO
Methodology Inc.<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3Dblue face=3D"Franklin Gothic Bo=
ok"><span
style=3D'font-size:10.0pt;font-family:"Franklin Gothic Book";color:blue'>ww=
w.iometh.com<o:p></o:p></span></font></p>

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span
style=3D'font-size:12.0pt;color:blue'><o:p>&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal><font size=3D3 color=3Dblue face=3D"Times New Roman"><=
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<p class=3DMsoNormal><font size=3D3 color=3Dblue face=3D"Times New Roman"><=
span
style=3D'font-size:12.0pt;color:blue'>&nbsp;<o:p></o:p></span></font></p>

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<p class=3DMsoNormal><font size=3D2 color=3Dblue face=3D"Franklin Gothic Bo=
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<p class=3DMsoNormal style=3D'margin-left:.5in'><b><font size=3D2 face=3DTa=
homa><span
style=3D'font-size:10.0pt;font-family:Tahoma;font-weight:bold'>From:</span>=
</font></b><font
size=3D2 face=3DTahoma><span style=3D'font-size:10.0pt;font-family:Tahoma'>
owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] <b><span
style=3D'font-weight:bold'>On Behalf Of </span></b>Ramesh Raghavan<br>
<b><span style=3D'font-weight:bold'>Sent:</span></b> Friday, August 06, 201=
0 4:11
AM<br>
<b><span style=3D'font-weight:bold'>To:</span></b> 'ji xiao'<br>
<b><span style=3D'font-weight:bold'>Cc:</span></b> 'ibis-users'<br>
<b><span style=3D'font-weight:bold'>Subject:</span></b> RE: [IBIS-Users] er=
ror
msg in s2ibis3</span></font><o:p></o:p></p>

</div>

<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 face=3D"Time=
s New Roman"><span
style=3D'font-size:12.0pt'><o:p>&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 color=3D"#1f=
497d"
face=3DCalibri><span style=3D'font-size:11.0pt;font-family:Calibri;color:#1=
F497D'>Hi&nbsp;&nbsp;
Yauncheng,<o:p></o:p></span></font></p>

<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 color=3D"#1f=
497d"
face=3DCalibri><span style=3D'font-size:11.0pt;font-family:Calibri;color:#1=
F497D'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;If the issue is that you ha=
ve
more than 100 points in .out files. Then,there is&nbsp; a way to do this bu=
t I
do not know if this is the really the best/efficient way. <o:p></o:p></span=
></font></p>

<p class=3Dmsolistparagraph style=3D'margin-left:1.0in;text-indent:-.25in;
mso-list:l0 level1 lfo2'><![if !supportLists]><font size=3D2 color=3D"#1f49=
7d"
face=3DCalibri><span style=3D'font-size:11.0pt;font-family:Calibri;color:#1=
F497D'><span
style=3D'mso-list:Ignore'>1.<font size=3D1 face=3D"Times New Roman"><span
style=3D'font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
 </span></font></span></span></font><![endif]><font
size=3D2 color=3D"#1f497d" face=3DCalibri><span style=3D'font-size:11.0pt;f=
ont-family:
Calibri;color:#1F497D'>You can use the iterate command option in .s2i.
&nbsp;Edit the .spi files and reduce the step/range in .spi file
&nbsp;&nbsp;and do a hspice simulation of all .spi files (which have more t=
han
100 points) &nbsp;&nbsp;and generate the .out files and rerun the s2ibis3 t=
ool
for the IBIS model<o:p></o:p></span></font></p>

<p class=3DMsoNormal style=3D'margin-left:.75in'><font size=3D2 color=3D"#1=
f497d"
face=3DCalibri><span style=3D'font-size:11.0pt;font-family:Calibri;color:#1=
F497D'><o:p>&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal style=3D'margin-left:.75in'><font size=3D2 color=3D"#1=
f497d"
face=3DCalibri><span style=3D'font-size:11.0pt;font-family:Calibri;color:#1=
F497D'>&nbsp;Does
this help you?<o:p></o:p></span></font></p>

<p class=3DMsoNormal style=3D'margin-left:.75in'><font size=3D2 color=3D"#1=
f497d"
face=3DCalibri><span style=3D'font-size:11.0pt;font-family:Calibri;color:#1=
F497D'><o:p>&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal style=3D'margin-left:.75in'><font size=3D2 color=3D"#1=
f497d"
face=3DCalibri><span style=3D'font-size:11.0pt;font-family:Calibri;color:#1=
F497D'>Thanks,<o:p></o:p></span></font></p>

<p class=3DMsoNormal style=3D'margin-left:.75in'><font size=3D2 color=3D"#1=
f497d"
face=3DCalibri><span style=3D'font-size:11.0pt;font-family:Calibri;color:#1=
F497D'>Ramesh<o:p></o:p></span></font></p>

<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 color=3D"#1f=
497d"
face=3DCalibri><span style=3D'font-size:11.0pt;font-family:Calibri;color:#1=
F497D'><o:p>&nbsp;</o:p></span></font></p>

<div style=3D'border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in =
0in 0in'>

<p class=3DMsoNormal style=3D'margin-left:.5in'><b><font size=3D2 face=3DTa=
homa><span
style=3D'font-size:10.0pt;font-family:Tahoma;font-weight:bold'>From:</span>=
</font></b><font
size=3D2 face=3DTahoma><span style=3D'font-size:10.0pt;font-family:Tahoma'>
owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] <b><span
style=3D'font-weight:bold'>On Behalf Of </span></b>ji xiao<br>
<b><span style=3D'font-weight:bold'>Sent:</span></b> Friday, August 06, 2010
12:59 PM<br>
<b><span style=3D'font-weight:bold'>To:</span></b> ibis-users<br>
<b><span style=3D'font-weight:bold'>Subject:</span></b> [IBIS-Users] error =
msg in
s2ibis3<o:p></o:p></span></font></p>

</div>

<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 face=3D"Time=
s New Roman"><span
style=3D'font-size:12.0pt'><o:p>&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 face=3D"Time=
s New Roman"><span
style=3D'font-size:12.0pt'>Dear all,<br>
when I use s2ibis3 to convert an HSPICE file to IBIS file, I got the error =
msg
shown as below:<br>
Exception in thread &quot;main&quot; java.lang.ArrayIndexOutOfBoundsExcepti=
on:
- -1<br>
&nbsp;&nbsp; at sortVIData.sortVIData(ibisModel, ibisVItable, ibisVItable,
ibisVItable, ibisVItable) (Unknown Source)<br>
&nbsp;&nbsp; at analyzePin.analyzePin(ibisPin, ibisPin, ibisPin, ibisPin,
ibisPin, ibisPin, int, java.lang.String, java.lang.String, java.lang.String,
int, int) (Unknown Source)<br>
&nbsp;&nbsp; at analyzeComponent.analyzeComponent(int, int, int,
java.lang.String) (Unknown Source)<br>
&nbsp;&nbsp; at s2ibis3.main(java.lang.String[]) (Unknown Source)<br>
<br>
It seems that the data points number of IV curves out of the range--100. Is=
 there
any way to solve the problem?<br>
<br>
Thanks and regards,<br>
Yuancheng<br>
<br>
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------------------------------

Date: Wed, 25 Aug 2010 06:07:05 -0700
From: "Muranyi, Arpad" <Arpad_Muranyi@mentor.com>
Subject: RE: [IBIS-Users] input stimulus for extracting IBIS VT curves

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Yuangcheng,
=20
When you put a load on the IBIS model which was used to
extract the V-t curves from the transistor model (i.e.
the same V_fixture and R_fixture combination), you should
get the same waveforms at the output of the IBIS buffer
as the V-t curve inside the IBIS model.
=20
The stimulus to the IBIS model is usually not accessible
in most tools.  However, in some tools, like the HSPICE
B-element case you can still define your own stimulus.
This should be as fast as possible, since in theory this
should be a perfect digital transition.
=20
When you extract the V-t curves from the transistor models
it is important to set the fastest possible edge rate for
the stimulus, because a relatively slow edge can have an
effect on the apparent delay since the stimulus will take
a certain time to reach the threshold levels of the input
causing some unwanted delays.
=20
If you set fast stimulus edge rates, you will usually not
have to massage anything in the waveforms you get from the
transistor model when you make your IBIS model.
=20
I hope this helps.
=20
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D

________________________________

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of ji xiao
Sent: Wednesday, August 25, 2010 4:53 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] input stimulus for extracting IBIS VT curves


Dear all,
I am trying to validate the IBIS VT data from SPICE simulation. Many
technical papers described the setup as 'apply an appropriate input
stimulus', can anyone tell me in detail how to set the 'appropriate'
one, such as any standards for setting the delay, rise and falling time?
As the original IBIS file does not describe the input stimulus
condition, how can I set it to make me get a totally same rising and
falling waveform?
Thanks and regards,
=20
Yuancheng

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Dus-ascii" http-equiv=3DContent-Type>
<META name=3DGENERATOR content=3D"MSHTML 8.00.6001.18939"></HEAD>
<BODY>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">Yuangcheng,</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">When you put a load on the IBIS model which was used=
=20
to</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">extract the V-t curves from the transistor model=20
(i.e.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">the same V_fixture and R_fixture combination), you=20
should</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">get the same waveforms at the output of the IBIS=20
buffer</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">as the V-t curve inside the IBIS model.</FONT></SPAN><=
/DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">The stimulus to the IBIS model is usually not=20
accessible</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">in most tools.&nbsp; However, in some tools, like the=
=20
HSPICE</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">B-element case you can still define your own=20
stimulus.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">This should be as fast as possible, since in theory=20
this</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">should be a perfect digital transition.</FONT></SPAN><=
/DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010></SPAN><SPAN=
=20
class=3D382595812-25082010><FONT size=3D2=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">When you extract the V-t curves from the transistor=20
models</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">it is important to set the fastest possible edge rate=
=20
for</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">the stimulus, because a relatively slow edge can have=
=20
an</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">effect on the apparent delay since the stimulus will=
=20
take</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">a certain time to reach the threshold levels of the=20
input</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">causing some unwanted delays.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">If you set fast stimulus edge rates, you will=20
</FONT></SPAN><SPAN class=3D382595812-25082010><FONT size=3D2=20
face=3D"Courier New">usually not</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">have to massage anything in the waveforms </FONT></SPA=
N><SPAN=20
class=3D382595812-25082010><FONT size=3D2 face=3D"Courier New">you get from=
=20
the</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">transistor model when you make your </FONT></SPAN><SPA=
N=20
class=3D382595812-25082010><FONT size=3D2 face=3D"Courier New">IBIS=20
model.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">I hope this helps.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">Arpad</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D382595812-25082010><FONT size=3D2=
=20
face=3D"Courier New">=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D</FONT></SPAN></DIV><BR>
<DIV dir=3Dltr lang=3Den-us class=3DOutlookMessageHeader align=3Dleft>
<HR tabIndex=3D-1>
<FONT size=3D2 face=3DTahoma><B>From:</B> owner-ibis-users@eda.org=20
[mailto:owner-ibis-users@eda.org] <B>On Behalf Of </B>ji xiao<BR><B>Sent:</=
B>=20
Wednesday, August 25, 2010 4:53 AM<BR><B>To:</B>=20
ibis-users@eda.org<BR><B>Subject:</B> [IBIS-Users] input stimulus for extra=
cting=20
IBIS VT curves<BR></FONT><BR></DIV>
<DIV></DIV>
<DIV>Dear all,</DIV>
<DIV>I am&nbsp;trying to&nbsp;validate the IBIS VT data from SPICE simulati=
on.=20
Many technical papers described the setup as 'apply an appropriate input=20
stimulus', can anyone tell me in detail how to set the 'appropriate' one, s=
uch=20
as any standards for setting the delay, rise and falling time?</DIV>
<DIV>As the original IBIS file does not describe the input stimulus conditi=
on,=20
how can I set it to make me get a totally same rising and falling=20
waveform?</DIV>
<DIV>Thanks and regards,</DIV>
<DIV>&nbsp;</DIV>
<DIV>Yuancheng</DIV><BR>-- <BR>This message has been scanned for viruses an=
d=20
<BR>dangerous content by <A=20
href=3D"http://www.mailscanner.info/"><B>MailScanner</B></A>, and is <BR>be=
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to be clean. <br />--=20
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------------------------------

Date: Mon, 2 Aug 2010 07:48:03 -0700
From: "Muranyi, Arpad" <Arpad_Muranyi@mentor.com>
Subject: RE: [IBIS-Users] Ramp calculation in O/P, Tri-state, I/O, buffer ibis model

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Suraj,
=20
In simple complementary CMOS buffers they usually turn off
one side of the buffer quickly before they turn on the other
side.  When you do a falling edge, the pullup turns off quickly
and then the pulldown starts turning on (usually slower).  If
you connect a resistor to the supply rail for the falling
edge, then the output is not going to do anything while the
pullup is being turned off.  The resistor just keeps it at
the supply rail when it was to begin with.  When the pulldown
starts turning on, the pulldown will pull the voltage down
while fighting the resistor, forming a voltage divider.  This
way you get the turn on characteristics of the pulldown.
=20
If the resistor was connected to GND, the pullup would be holding
the voltage high fighting that resistor.  As soon as the falling
edge's transition begins, the pullup will let go and the waveform
will go to GND.  This way you get the characteristics of the pullup
turning off.
=20
The [Ramp] contains how the devices turn on.  The [Ramp] doesn't
tell you how the devices turn off.  This was a major deficiency
in IBIS 1.1 and this is why we added the waveform tables in IBIS
2.1 rapidly after IBIS 1.1 was released, and this is why we
recommend very strongly to use a minimum of four waveform tables
for each buffer model.
=20
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
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=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

________________________________

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of suraj.sukumarannair@wipro.com
Sent: Monday, August 02, 2010 8:24 AM
To: ibis-users@eda.org; ibis@eda-stds.org
Subject: [IBIS-Users] Ramp calculation in O/P, Tri-state, I/O, buffer
ibis model



Hi All,

=20

 I had a query regarding the ramp calculation done in ibis file. Why is
it that we consider the falling waveform w.r.t Vfix=3Dvdd and rising
waveform w.r.t Vfix=3D0 tables instead of the other two tables while
calculating Ramp?

=20

Regards

Suraj

Please do not print this email unless it is absolutely necessary.=20

The information contained in this electronic message and any attachments
to this message are intended for the exclusive use of the addressee(s)
and may contain proprietary, confidential or privileged information. If
you are not the intended recipient, you should not disseminate,
distribute or copy this e-mail. Please notify the sender immediately and
destroy all copies of this message and any attachments.=20

WARNING: Computer viruses can be transmitted via email. The recipient
should check this email and any attachments for the presence of viruses.
The company accepts no liability for any damage caused by any virus
transmitted by this email.=20

www.wipro.com=20


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<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">Suraj,</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">In simple complementary CMOS buffers they usually turn=
=20
off</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">one side of the buffer quickly before they turn on the=
=20
other</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">side.&nbsp; When you do a falling edge, the pullup tur=
ns off=20
quickly</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">and then the pulldown starts turning on (usually=20
slower).&nbsp; If</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">you connect a resistor to the supply rail for the=20
falling</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">edge, then the output is not going to do anything whil=
e=20
the</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">pullup is being turned off.&nbsp; The resistor just ke=
eps it=20
at</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">the supply rail when it was to begin with.&nbsp; When =
the=20
pulldown</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">starts turning on, the pulldown will pull the voltage=
=20
down</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">while fighting the resistor, forming a voltage divider=
.&nbsp;=20
This</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">way you get the turn on characteristics of the=20
pulldown.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">If the resistor was connected to GND, the pullup would=
 be=20
holding</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">the voltage high fighting that resistor.&nbsp; As soon=
 as the=20
falling</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">edge's transition </FONT></SPAN><SPAN=20
class=3D354473814-02082010><FONT size=3D2 face=3D"Courier New">begins, the =
pullup will=20
let go and the waveform</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">will go to GND.&nbsp; This way you get the characteris=
tics of=20
the pullup</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">turning off.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">The [Ramp] contains how the devices turn on.&nbsp; The=
 [Ramp]=20
doesn't</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">tell you how the devices turn off.&nbsp; This was a ma=
jor=20
deficiency</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">in IBIS 1.1 and this is why we added the waveform tabl=
es in=20
IBIS</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">2.1 rapidly after IBIS 1.1 was released, and this is w=
hy=20
we</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">recommend very strongly to use a minimum of four wavef=
orm=20
tables</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">for&nbsp;each buffer model.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">Arpad</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D354473814-02082010><FONT size=3D2=
=20
face=3D"Courier New">=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D</FONT></=
SPAN></DIV><BR>
<DIV dir=3Dltr lang=3Den-us class=3DOutlookMessageHeader align=3Dleft>
<HR tabIndex=3D-1>
<FONT size=3D2 face=3DTahoma><B>From:</B> owner-ibis-users@eda.org=20
[mailto:owner-ibis-users@eda.org] <B>On Behalf Of=20
</B>suraj.sukumarannair@wipro.com<BR><B>Sent:</B> Monday, August 02, 2010 8=
:24=20
AM<BR><B>To:</B> ibis-users@eda.org; ibis@eda-stds.org<BR><B>Subject:</B>=
=20
[IBIS-Users] Ramp calculation in O/P, Tri-state, I/O, buffer ibis=20
model<BR></FONT><BR></DIV>
<DIV></DIV>
<DIV class=3DSection1>
<P class=3DMsoNormal><FONT size=3D2 face=3DArial><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">Hi All,<o:p></o:p></SPAN></FO=
NT></P>
<P class=3DMsoNormal><FONT size=3D2 face=3DArial><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt"><o:p>&nbsp;</o:p></SPAN></FON=
T></P>
<P class=3DMsoNormal><FONT size=3D2 face=3DArial><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">&nbsp;I had a query regarding=
 the=20
ramp calculation done in ibis file. Why is it that we consider the falling=
=20
waveform w.r.t Vfix=3Dvdd and rising waveform w.r.t Vfix=3D0 tables instead=
 of the=20
other two tables while calculating Ramp?<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT size=3D2 face=3DArial><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt"><o:p>&nbsp;</o:p></SPAN></FON=
T></P>
<P class=3DMsoNormal><FONT size=3D2 face=3DArial><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">Regards<o:p></o:p></SPAN></FO=
NT></P>
<P class=3DMsoNormal><FONT size=3D2 face=3DArial><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">Suraj<o:p></o:p></SPAN></FONT=
></P></DIV>
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Date: Fri, 30 Jul 2010 09:53:57 -0400
From: "Timothy Coyle" <tim.coyle@siconsultant.com>
Subject: RE: [IBIS-Users] Parser for verifying syntax of .EBD file

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Hi Amit,

I believe the standard IBIS Parser will check the syntax of an .ebd file
with the -ebd flag. Take a look at the readme/help for the parser on the
instructions.

 

Best,

 

Tim

 

 

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of Amit KUMAR
Sent: Friday, July 30, 2010 5:42 AM
To: Muranyi, Arpad; ibis-users@eda.org; ibis@eda-stds.org
Subject: [IBIS-Users] Parser for verifying syntax of .EBD file

 

 Hello All,

 

Do we have any parser which can check the syntax of .ebd file?

 

Regards

Amit

 


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<div class=3DWordSection1>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>Hi Amit,<o:p></o:p></spa=
n></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>I believe the standard I=
BIS
Parser will check the syntax of an .ebd file with the -ebd flag. Take a loo=
k at
the readme/help for the parser on the instructions.<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>Best,<o:p></o:p></span><=
/p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>Tim<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

<div>

<div style=3D'border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in =
0in 0in'>

<p class=3DMsoNormal><b><span style=3D'font-size:10.0pt;font-family:"Tahoma=
","sans-serif"'>From:</span></b><span
style=3D'font-size:10.0pt;font-family:"Tahoma","sans-serif"'>
owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] <b>On Behalf Of =
</b>Amit
KUMAR<br>
<b>Sent:</b> Friday, July 30, 2010 5:42 AM<br>
<b>To:</b> Muranyi, Arpad; ibis-users@eda.org; ibis@eda-stds.org<br>
<b>Subject:</b> [IBIS-Users] Parser for verifying syntax of .EBD file<o:p><=
/o:p></span></p>

</div>

</div>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>&nbsp;Hello All,<o:p></o=
:p></span></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>Do we have any parser wh=
ich can
check the syntax of .ebd file?<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>Regards<o:p></o:p></span=
></p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'>Amit<o:p></o:p></span></=
p>

<p class=3DMsoNormal><span style=3D'color:#1F497D'><o:p>&nbsp;</o:p></span>=
</p>

<p class=3DMsoNormal><span style=3D'font-size:12.0pt;font-family:"Times New=
 Roman","serif"'><br>
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------------------------------

Date: Thu, 26 Aug 2010 10:49:51 +0530
From: <shiju.abraham@wipro.com>
Subject: [IBIS-Users] IBIS Simulation algorithm

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Hi,



Can any one explain me, how an IBIS Simulator (say, HSPICE) is
interpreting an IBIS file given to it?



Suppose that I am simulating an IBIS file of a 2-state output buffer,
using HSPICE by giving a square wave [swing is from 0 to 5V and period
is 33ns] as input.  Let's assume that it's a non-inverting buffer, and I
observe that am getting the same square wave at the output.

Can you tell me how exactly HSPICE finds the voltage values for each
time, t? Which table(s) is used by HSPICE for this?



I also observe that, even if I remove the V-T table and supply only the
[Ramp] information, HSPICE is able to simulate the buffer model with
almost the same accuracy. [I have 4 VT (2 Rise and 2 Fall) tables
originally]

Can you please clarify my doubts?



Thanks,

Shiju


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<div class=3DSection1>

<p class=3DMsoNormal><font size=3D2 color=3D"#4e4e4e" face=3D"Century Gothi=
c"><span
style=3D'font-size:10.0pt;font-family:"Century Gothic";color:#4E4E4E'>Hi, <=
o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3D"#4e4e4e" face=3D"Century Gothi=
c"><span
style=3D'font-size:10.0pt;font-family:"Century Gothic";color:#4E4E4E'><o:p>=
&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3D"#4e4e4e" face=3D"Century Gothi=
c"><span
style=3D'font-size:10.0pt;font-family:"Century Gothic";color:#4E4E4E'>Can a=
ny one
explain me, how an IBIS Simulator (say, HSPICE) is interpreting an IBIS file
given to it? <o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3D"#4e4e4e" face=3D"Century Gothi=
c"><span
style=3D'font-size:10.0pt;font-family:"Century Gothic";color:#4E4E4E'><o:p>=
&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3D"#4e4e4e" face=3D"Century Gothi=
c"><span
style=3D'font-size:10.0pt;font-family:"Century Gothic";color:#4E4E4E'>Suppo=
se
that I am simulating an IBIS file of a 2-state output buffer, using HSPICE =
by
giving a square wave [swing is from 0 to 5V and period is 33ns] as input. &=
nbsp;Let&#8217;s
assume that it&#8217;s a non-inverting buffer, and I observe that am getting
the same square wave at the output.<br>
<br>
Can you tell me how exactly HSPICE finds the voltage values for each time, =
t?
Which table(s) is used by HSPICE for this?<br>
<br>
<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3D"#4e4e4e" face=3D"Century Gothi=
c"><span
style=3D'font-size:10.0pt;font-family:"Century Gothic";color:#4E4E4E'>I also
observe that, even if I remove the V-T table and supply only the [Ramp]
information, HSPICE is able to simulate the buffer mo<st1:State w:st=3D"on"=
><st1:place
 w:st=3D"on">del</st1:place></st1:State> with almost the same accuracy. [I =
have 4
VT (2 Rise and 2 Fall) tables originally]<br>
<br>
Can you please clarify my doubts?<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3D"#4e4e4e" face=3D"Century Gothi=
c"><span
style=3D'font-size:10.0pt;font-family:"Century Gothic";color:#4E4E4E'><o:p>=
&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3D"#4e4e4e" face=3D"Century Gothi=
c"><span
style=3D'font-size:10.0pt;font-family:"Century Gothic";color:#4E4E4E'>Thank=
s,<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3D"#4e4e4e" face=3D"Century Gothi=
c"><span
style=3D'font-size:10.0pt;font-family:"Century Gothic";color:#4E4E4E'>Shiju=
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ould check this email and any attachments for the presence of viruses. The =
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<p>
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------------------------------

Date: Fri, 6 Aug 2010 15:29:04 +0800
From: ji xiao <xiaoji86@gmail.com>
Subject: [IBIS-Users] error msg in s2ibis3

- --0016364ed3461d42bd048d229fed
Content-Type: text/plain; charset=ISO-8859-1

Dear all,
when I use s2ibis3 to convert an HSPICE file to IBIS file, I got the error
msg shown as below:
Exception in thread "main" java.lang.ArrayIndexOutOfBoundsException: -1
   at sortVIData.sortVIData(ibisModel, ibisVItable, ibisVItable,
ibisVItable, ibisVItable) (Unknown Source)
   at analyzePin.analyzePin(ibisPin, ibisPin, ibisPin, ibisPin, ibisPin,
ibisPin, int, java.lang.String, java.lang.String, java.lang.String, int,
int) (Unknown Source)
   at analyzeComponent.analyzeComponent(int, int, int, java.lang.String)
(Unknown Source)
   at s2ibis3.main(java.lang.String[]) (Unknown Source)

It seems that the data points number of IV curves out of the range--100. Is
there any way to solve the problem?

Thanks and regards,
Yuancheng

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Dear all,<br>when I use s2ibis3 to convert an HSPICE file to IBIS file, I g=
ot the error msg shown as below:<br>Exception in thread &quot;main&quot; ja=
va.lang.ArrayIndexOutOfBoundsException: -1<br>=A0=A0 at sortVIData.sortVIDa=
ta(ibisModel, ibisVItable, ibisVItable, ibisVItable, ibisVItable) (Unknown =
Source)<br>
=A0=A0 at analyzePin.analyzePin(ibisPin, ibisPin, ibisPin, ibisPin, ibisPin=
, ibisPin, int, java.lang.String, java.lang.String, java.lang.String, int, =
int) (Unknown Source)<br>=A0=A0 at analyzeComponent.analyzeComponent(int, i=
nt, int, java.lang.String) (Unknown Source)<br>
=A0=A0 at s2ibis3.main(java.lang.String[]) (Unknown Source)<br><br>It seems=
 that the data points number of IV curves out of the range--100. Is there a=
ny way to solve the problem?<br><br>Thanks and regards,<br>Yuancheng<br>
<br />--=20
<br />This message has been scanned for viruses and
<br />dangerous content by
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|  http://www.eda-stds.org/pub/ibis/email/         E-mail since 1993

------------------------------

Date: Thu, 26 Aug 2010 21:34:52 -0700
From: "Muranyi, Arpad" <Arpad_Muranyi@mentor.com>
Subject: RE: [IBIS-Users] IBIS Simulation algorithm

Andy,

You are making some really good points, but some of the
detail in your writing may be misleading or incorrect.

First, in modeling the transitions, we need to describe
two things.  One is how the transistor of the buffer is
turning on, and the other is how it turns off.  In plain
vanilla CMOS buffers we have a pullup and a pulldown
transistor in the output.  When the buffer goes High to
Low, the pullup transistor gets turned off, and the
pulldown gets turned on.  For Low to High transitions
the pulldown turns off and the pullup turns on.  Since
designers try to avoid crow bar currents, they usually
turn the transistors off much faster then they turn the
other transistor on, so that they wouldn't be on together.

You can observe this very easily with a few simple
simulations.  Take a buffer and put a resistor between
its output and ground.  Take a second copy of the same
buffer and put a resistor of the same value between its
output and the power supply.  Simulate a H to L and a
L to H transition with both and compare the four waveforms.

1)  With the L to H transition with R to GND, rising edge
you see how the PU turns on.  Initially the PD was on,
which is a low impedance path to GND, but the resistor was
also connected to GND, so the resistor and the transistor
are in parallel between the output and GND.  No matter
whether this transistor is on or off, the resistor will
keep the output at 0 V.  The only time the output voltage
will become different is when the pullup starts turning
on.  When this happens, the output voltage will have a
value which is determined by the voltage division between
the pullup transistor connected to the supply rail and the
resistor connected to GND.  This is why this waveform tells
us how the PU turns on.

2)  With a H to L transition and the R still connected to
GND, we start with the pullup being on.  As described above,
this creates a voltage divider between the power and GND.
As soon as the pullup transistor begins to turn off, the
resistor will start lowering the voltage towards GND.  The
voltage will reach 0 V before the pulldown transistor
even begins to turn on.  So this falling waveform will
show us how the pullup turned off.

The same thinking can also be applied to the situation
when the resistor is connected to the power rail.  In that
case the rising edge will tell us how the pulldown turned
off and the falling edge will tell us how the pulldown
turned on.


If you looked at the loading conditions of [Ramp], you will
see that it gives you only the information about how the
transistors turn on, but it doesn't tell us how they turn
off (unless the buffer is an open_*** type).  You will have
a hard time to implement a behavioral buffer algorithm
without knowing how to turn off the transistors.  You will
have to guess, or assume something.  (By the way, this is
what the "tune" parameters are for in the HSPICE B-element,
if I remember correctly).  Since guessing leaves a lot of
room for inaccuracies, this is why we added the waveform
tables so quickly in IBIS v2.1 and stated that it was
highly recommended to have at least four waveform tables
in each [Model].  The added benefit of the waveform tables
is that the data contained in them can describe the shape
of the transition also, instead of just a straight line
(trapezoidal) edge.

Since I don't like to leave things to be guessed in my
simulations, I tend to stay away from using the [Ramp]
and tend to highly recommend the usage of the waveform
tables, and recommend four tables per CMOS buffer.

I hope my reasons are clear...

Arpad
============================================================


- -----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Andrew Ingraham
Sent: Thursday, August 26, 2010 9:39 PM
To: ibis-users@eda.org
Subject: Re: [IBIS-Users] IBIS Simulation algorithm

> I also observe that, even if I remove the V-T table and supply only
the
> [Ramp] information, HSPICE is able to simulate the buffer model with
almost
> the same accuracy. [I have 4 VT (2 Rise and 2 Fall) tables originally]

Originally, IBIS had no V-T tables, and it worked OK.  They were added
in a later revision to improve the transient accuracy.

Even after they were added to the IBIS spec, many simulators did not
use them.  (Hspice took a while to catch up.)

How or why does it work without V-T tables?  For most buffers,
waveforms are largely determined by the interaction between the
transistors (by way of their drive strengths in their On state), and
the load.  How a driver gets from Off to On, is far less important
than how it interacts with the load, as described by its I-V curves.

For many buffers, their transistors are switched between Off and On
states faster than their outputs slew from L to H or H to L, because
of that interaction with the load.  That means they spend most of the
time either Off (I=0), or fully On (I described by I-V table).

Without V-T tables, the simulator transitions between one transistor
fully On, to the other transistor fully On, over some short period of
time.  The Ramp data helps the simulator control how quickly it should
go from one state to the other.

Andy

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|with the appropriate command message(s) in the body:
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|  unsubscribe ibis-users <optional e-mail address, if different>
|
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|  http://www.eda-stds.org/pub/ibis/users_archive/ Recent
|  http://www.eda-stds.org/pub/ibis/email/         E-mail since 1993

------------------------------

Date: Wed, 25 Aug 2010 17:52:39 +0800
From: ji xiao <xiaoji86@gmail.com>
Subject: [IBIS-Users] input stimulus for extracting IBIS VT curves

- --0015175cb0589425ee048ea2d7f6
Content-Type: text/plain; charset=ISO-8859-1

Dear all,
I am trying to validate the IBIS VT data from SPICE simulation. Many
technical papers described the setup as 'apply an appropriate input
stimulus', can anyone tell me in detail how to set the 'appropriate' one,
such as any standards for setting the delay, rise and falling time?
As the original IBIS file does not describe the input stimulus condition,
how can I set it to make me get a totally same rising and falling waveform?
Thanks and regards,

Yuancheng

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<div>Dear all,</div>
<div>I am=A0trying to=A0validate the IBIS VT data from SPICE simulation. Ma=
ny technical papers described the setup as &#39;apply an appropriate input =
stimulus&#39;, can anyone tell me in detail how to set the &#39;appropriate=
&#39; one, such as any standards for setting the delay, rise and falling ti=
me?</div>

<div>As the original IBIS file does not describe the input stimulus conditi=
on, how can I set it to make me get a totally same rising and falling wavef=
orm?</div>
<div>Thanks and regards,</div>
<div>=A0</div>
<div>Yuancheng</div>
<br />--=20
<br />This message has been scanned for viruses and
<br />dangerous content by
<a href=3D"http://www.mailscanner.info/"><b>MailScanner</b></a>, and is
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- --0015175cb0589425ee048ea2d7f6--
- --------------------------------------------------------------------
|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org
|with the appropriate command message(s) in the body:
|
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|  http://www.eda-stds.org/pub/ibis/users_archive/ Recent
|  http://www.eda-stds.org/pub/ibis/email/         E-mail since 1993

------------------------------

Date: Fri, 6 Aug 2010 13:41:09 +0530
From: "Ramesh Raghavan" <rame@cypress.com>
Subject: RE: [IBIS-Users] error msg in s2ibis3

This is a multi-part message in MIME format.

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Content-Type: text/plain;
	charset="us-ascii"
Content-Transfer-Encoding: 7bit

Hi   Yauncheng,

                          If the issue is that you have more than 100 points
in .out files. Then,there is  a way to do this but I do not know if this is
the really the best/efficient way. 

1.       You can use the iterate command option in .s2i.  Edit the .spi
files and reduce the step/range in .spi file   and do a hspice simulation of
all .spi files (which have more than 100 points)   and generate the .out
files and rerun the s2ibis3 tool for the IBIS model

 

 Does this help you?

 

Thanks,

Ramesh

 

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of ji xiao
Sent: Friday, August 06, 2010 12:59 PM
To: ibis-users
Subject: [IBIS-Users] error msg in s2ibis3

 

Dear all,
when I use s2ibis3 to convert an HSPICE file to IBIS file, I got the error
msg shown as below:
Exception in thread "main" java.lang.ArrayIndexOutOfBoundsException: -1
   at sortVIData.sortVIData(ibisModel, ibisVItable, ibisVItable,
ibisVItable, ibisVItable) (Unknown Source)
   at analyzePin.analyzePin(ibisPin, ibisPin, ibisPin, ibisPin, ibisPin,
ibisPin, int, java.lang.String, java.lang.String, java.lang.String, int,
int) (Unknown Source)
   at analyzeComponent.analyzeComponent(int, int, int, java.lang.String)
(Unknown Source)
   at s2ibis3.main(java.lang.String[]) (Unknown Source)

It seems that the data points number of IV curves out of the range--100. Is
there any way to solve the problem?

Thanks and regards,
Yuancheng

- -- 
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believed to be clean. 


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<body lang=3DEN-US link=3Dblue vlink=3Dpurple>

<div class=3DWordSection1>

<p class=3DMsoNormal><span style=3D'font-size:11.0pt;font-family:"Calibri",=
"sans-serif";
color:#1F497D'>Hi&nbsp;&nbsp; Yauncheng,<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:11.0pt;font-family:"Calibri",=
"sans-serif";
color:#1F497D'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;If the issue is that you have more
than 100 points in .out files. Then,there is&nbsp; a way to do this but I d=
o not
know if this is the really the best/efficient way. <o:p></o:p></span></p>

<p class=3DMsoListParagraph style=3D'text-indent:-.25in;mso-list:l1 level1 =
lfo2'><![if !supportLists]><span
style=3D'font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'=
><span
style=3D'mso-list:Ignore'>1.<span style=3D'font:7.0pt "Times New Roman"'>&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
</span></span></span><![endif]><span style=3D'font-size:11.0pt;font-family:=
"Calibri","sans-serif";
color:#1F497D'>You can use the iterate command option in .s2i. &nbsp;Edit t=
he .spi
files and reduce the step/range in .spi file &nbsp;&nbsp;and do a hspice si=
mulation of
all .spi files (which have more than 100 points) &nbsp;&nbsp;and generate t=
he .out files and
rerun the s2ibis3 tool for the IBIS model<o:p></o:p></span></p>

<p class=3DMsoNormal style=3D'margin-left:.25in'><span style=3D'font-size:1=
1.0pt;
font-family:"Calibri","sans-serif";color:#1F497D'><o:p>&nbsp;</o:p></span><=
/p>

<p class=3DMsoNormal style=3D'margin-left:.25in'><span style=3D'font-size:1=
1.0pt;
font-family:"Calibri","sans-serif";color:#1F497D'>&nbsp;Does this help you?=
<o:p></o:p></span></p>

<p class=3DMsoNormal style=3D'margin-left:.25in'><span style=3D'font-size:1=
1.0pt;
font-family:"Calibri","sans-serif";color:#1F497D'><o:p>&nbsp;</o:p></span><=
/p>

<p class=3DMsoNormal style=3D'margin-left:.25in'><span style=3D'font-size:1=
1.0pt;
font-family:"Calibri","sans-serif";color:#1F497D'>Thanks,<o:p></o:p></span>=
</p>

<p class=3DMsoNormal style=3D'margin-left:.25in'><span style=3D'font-size:1=
1.0pt;
font-family:"Calibri","sans-serif";color:#1F497D'>Ramesh<o:p></o:p></span><=
/p>

<p class=3DMsoNormal><span style=3D'font-size:11.0pt;font-family:"Calibri",=
"sans-serif";
color:#1F497D'><o:p>&nbsp;</o:p></span></p>

<div style=3D'border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in =
0in 0in'>

<p class=3DMsoNormal><b><span style=3D'font-size:10.0pt;font-family:"Tahoma=
","sans-serif"'>From:</span></b><span
style=3D'font-size:10.0pt;font-family:"Tahoma","sans-serif"'>
owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] <b>On Behalf Of =
</b>ji
xiao<br>
<b>Sent:</b> Friday, August 06, 2010 12:59 PM<br>
<b>To:</b> ibis-users<br>
<b>Subject:</b> [IBIS-Users] error msg in s2ibis3<o:p></o:p></span></p>

</div>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

<p class=3DMsoNormal>Dear all,<br>
when I use s2ibis3 to convert an HSPICE file to IBIS file, I got the error =
msg
shown as below:<br>
Exception in thread &quot;main&quot; java.lang.ArrayIndexOutOfBoundsExcepti=
on:
- -1<br>
&nbsp;&nbsp; at sortVIData.sortVIData(ibisModel, ibisVItable, ibisVItable,
ibisVItable, ibisVItable) (Unknown Source)<br>
&nbsp;&nbsp; at analyzePin.analyzePin(ibisPin, ibisPin, ibisPin, ibisPin,
ibisPin, ibisPin, int, java.lang.String, java.lang.String, java.lang.String,
int, int) (Unknown Source)<br>
&nbsp;&nbsp; at analyzeComponent.analyzeComponent(int, int, int,
java.lang.String) (Unknown Source)<br>
&nbsp;&nbsp; at s2ibis3.main(java.lang.String[]) (Unknown Source)<br>
<br>
It seems that the data points number of IV curves out of the range--100. Is
there any way to solve the problem?<br>
<br>
Thanks and regards,<br>
Yuancheng<br>
<br>
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------------------------------

Date: Wed, 25 Aug 2010 10:26:41 -0700
From: "Muranyi, Arpad" <Arpad_Muranyi@mentor.com>
Subject: RE: [IBIS-Users] input stimulus for extracting IBIS VT curves

Andy,

Regarding your comments on the transistor models, while it is
a reasonable concept, it usually doesn't matter.  I verified
this by sweeping the stimulus edge rate from very fast to very
slow, and overlaid the output waveforms, and didn't see any
difference, other than a time shift due to the input stimulus
reaching the threshold levels increasingly later with the slower
slopes.  This can be explained by the fact that most transistor
buffer models have multiple stages in them, and the final stage
is so far removed from the first stage that its waveform is
only determined by the transistor sizing relationships between
the stages, but not by the stimulus waveform.

Your reasoning would only be true when the transistor model
doesn't have any pre-driver stage(s), or very few of them.  But
I would strongly advise against using such transistor models
for IBIS data extractions, because if the output waveform is
a factor of the stimulus, then the model maker can end up making
all kinds of incorrect IBIS models if they don't know what the
waveform looks like on the core side of this model.

Regarding the stimulus to the B-element (or the like), it is true
that in terms of its operation it doesn't matter what the edge
rate is, the output waveform will still be the same.  But you
need to consider that due to the slow stimulus waveforms you will
get a certain delay in the transition.  This can cause complications
if the user forgets that the stimulus supposed to be a 0-1 volt
waveform, and the thresholds are set to 0.2 and 0.8 if I remember
correctly.  I have seen many times people applying a source to the
input of the B-element with a voltage swing that used the supply
voltage value of the buffer, for example 0 to 3.3 volts.  With a
slow stimulus edge rate, the rising edge will trigger sooner than
the falling edge very noticeably.  (In other words you get duty
cycle distortions from the IBIS model while the transistor model
didn't do that).

Even if this was handled properly by the user, similar shifting
could occur due to the different stimulus edge rates between the
transistor and IBIS buffer stimuli.  I had people often show me
"discrepancies" between the transistor waveforms and the IBIS
waveforms which were due to that, and they had no clue why the
IBIS and transistor waveforms were shifted apart in time.

These are the reasons I am suggesting the use of fast edge rates...

Arpad
===================================================================





- -----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Andrew Ingraham
Sent: Wednesday, August 25, 2010 11:14 AM
To: ibis-users@eda.org
Subject: Re: [IBIS-Users] input stimulus for extracting IBIS VT curves

I disagree that the edge should be "as fast as possible".

For the IBIS models used in HSPICE, my recollection is that HSPICE
treats it as a switch, waiting until the (digital) input waveform
crosses a threshold, then switching the IBIS model.  The edge rate of
that digital stimulus waveform therefore shouldn't matter ... except
that very slow edge rate causes a known time delay before the IBIS
modeled device switches, and extremely fast edge rates might make the
simulation run slow or lead to convergence problems.  Theoretically
it's good to make it fast so that it works like an instantaneous
binary switch, but there could be practical problems if you try to do
that.

For the transistor (SPICE) models, ideally you should attempt to match
the actual waveform (edge rate and amplitude) that is at that point
inside the IC, NOT the "fastest possible edge rate".  Hopefully that
is what the IBIS modeler did too.  Using a faster edge rate than what
those transistors normally see, makes it unrealistic.

Andy

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------------------------------

Date: Wed, 25 Aug 2010 13:32:55 -0400
From: Scott McMorrow <scott@teraspeed.com>
Subject: Re: [IBIS-Users] input stimulus for extracting IBIS VT curves

  Arpad

I agree with you on input edge rate to a buffer.  Most devices have 
extremely fast input rise/fall time into the predriver, since loading is 
so low at this point in the circuit.  What is more important for IBIS 
buffer modeling is the predriver voltage rail.  Unfortunately, in IBIS 
there is no way to correctly model predriver power supply voltage 
modulation effects, which are very real under SSO conditions.

regards,

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC


On 8/25/2010 1:26 PM, Muranyi, Arpad wrote:
> Andy,
>
> Regarding your comments on the transistor models, while it is
> a reasonable concept, it usually doesn't matter.  I verified
> this by sweeping the stimulus edge rate from very fast to very
> slow, and overlaid the output waveforms, and didn't see any
> difference, other than a time shift due to the input stimulus
> reaching the threshold levels increasingly later with the slower
> slopes.  This can be explained by the fact that most transistor
> buffer models have multiple stages in them, and the final stage
> is so far removed from the first stage that its waveform is
> only determined by the transistor sizing relationships between
> the stages, but not by the stimulus waveform.
>
> Your reasoning would only be true when the transistor model
> doesn't have any pre-driver stage(s), or very few of them.  But
> I would strongly advise against using such transistor models
> for IBIS data extractions, because if the output waveform is
> a factor of the stimulus, then the model maker can end up making
> all kinds of incorrect IBIS models if they don't know what the
> waveform looks like on the core side of this model.
>
> Regarding the stimulus to the B-element (or the like), it is true
> that in terms of its operation it doesn't matter what the edge
> rate is, the output waveform will still be the same.  But you
> need to consider that due to the slow stimulus waveforms you will
> get a certain delay in the transition.  This can cause complications
> if the user forgets that the stimulus supposed to be a 0-1 volt
> waveform, and the thresholds are set to 0.2 and 0.8 if I remember
> correctly.  I have seen many times people applying a source to the
> input of the B-element with a voltage swing that used the supply
> voltage value of the buffer, for example 0 to 3.3 volts.  With a
> slow stimulus edge rate, the rising edge will trigger sooner than
> the falling edge very noticeably.  (In other words you get duty
> cycle distortions from the IBIS model while the transistor model
> didn't do that).
>
> Even if this was handled properly by the user, similar shifting
> could occur due to the different stimulus edge rates between the
> transistor and IBIS buffer stimuli.  I had people often show me
> "discrepancies" between the transistor waveforms and the IBIS
> waveforms which were due to that, and they had no clue why the
> IBIS and transistor waveforms were shifted apart in time.
>
> These are the reasons I am suggesting the use of fast edge rates...
>
> Arpad
> ===================================================================
>
>
>
>
>
> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
> Behalf Of Andrew Ingraham
> Sent: Wednesday, August 25, 2010 11:14 AM
> To: ibis-users@eda.org
> Subject: Re: [IBIS-Users] input stimulus for extracting IBIS VT curves
>
> I disagree that the edge should be "as fast as possible".
>
> For the IBIS models used in HSPICE, my recollection is that HSPICE
> treats it as a switch, waiting until the (digital) input waveform
> crosses a threshold, then switching the IBIS model.  The edge rate of
> that digital stimulus waveform therefore shouldn't matter ... except
> that very slow edge rate causes a known time delay before the IBIS
> modeled device switches, and extremely fast edge rates might make the
> simulation run slow or lead to convergence problems.  Theoretically
> it's good to make it fast so that it works like an instantaneous
> binary switch, but there could be practical problems if you try to do
> that.
>
> For the transistor (SPICE) models, ideally you should attempt to match
> the actual waveform (edge rate and amplitude) that is at that point
> inside the IC, NOT the "fastest possible edge rate".  Hopefully that
> is what the IBIS modeler did too.  Using a faster edge rate than what
> those transistors normally see, makes it unrealistic.
>
> Andy
>

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------------------------------

Date: Thu, 26 Aug 2010 08:31:24 -0700
From: "Muranyi, Arpad" <Arpad_Muranyi@mentor.com>
Subject: RE: [IBIS-Users] IBIS Simulation algorithm

This is a multi-part message in MIME format.

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	charset="us-ascii"
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Shiju,
=20
Look at this presentation:
=20
http://www.eda.org/ibis/summits/jun03b/muranyi1.pdf
=20
Hopefully the first eight or so pages will=20
answer your questions.
=20
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

________________________________

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of shiju.abraham@wipro.com
Sent: Thursday, August 26, 2010 12:20 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] IBIS Simulation algorithm



Hi,=20

=20

Can any one explain me, how an IBIS Simulator (say, HSPICE) is
interpreting an IBIS file given to it?=20

=20

Suppose that I am simulating an IBIS file of a 2-state output buffer,
using HSPICE by giving a square wave [swing is from 0 to 5V and period
is 33ns] as input.  Let's assume that it's a non-inverting buffer, and I
observe that am getting the same square wave at the output.

Can you tell me how exactly HSPICE finds the voltage values for each
time, t? Which table(s) is used by HSPICE for this?



I also observe that, even if I remove the V-T table and supply only the
[Ramp] information, HSPICE is able to simulate the buffer model with
almost the same accuracy. [I have 4 VT (2 Rise and 2 Fall) tables
originally]

Can you please clarify my doubts?

=20

Thanks,

Shiju

Please do not print this email unless it is absolutely necessary.=20

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to this message are intended for the exclusive use of the addressee(s)
and may contain proprietary, confidential or privileged information. If
you are not the intended recipient, you should not disseminate,
distribute or copy this e-mail. Please notify the sender immediately and
destroy all copies of this message and any attachments.=20

WARNING: Computer viruses can be transmitted via email. The recipient
should check this email and any attachments for the presence of viruses.
The company accepts no liability for any damage caused by any virus
transmitted by this email.=20

www.wipro.com=20


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<BODY lang=3DEN-US link=3Dblue vLink=3Dpurple>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New">Shiju,</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New">Look at this presentation:</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New"><A=20
href=3D"http://www.eda.org/ibis/summits/jun03b/muranyi1.pdf">http://www.eda=
.org/ibis/summits/jun03b/muranyi1.pdf</A></FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New">Hopefully the first eight or so pages will=20
</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New">answer your questions.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New"></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New">Arpad</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D890363015-26082010><FONT size=3D2=
=20
face=3D"Courier New">=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
</FONT></SPAN></DIV><BR>
<DIV dir=3Dltr lang=3Den-us class=3DOutlookMessageHeader align=3Dleft>
<HR tabIndex=3D-1>
<FONT size=3D2 face=3DTahoma><B>From:</B> owner-ibis-users@eda.org=20
[mailto:owner-ibis-users@eda.org] <B>On Behalf Of=20
</B>shiju.abraham@wipro.com<BR><B>Sent:</B> Thursday, August 26, 2010 12:20=
=20
AM<BR><B>To:</B> ibis-users@eda.org<BR><B>Subject:</B> [IBIS-Users] IBIS=20
Simulation algorithm<BR></FONT><BR></DIV>
<DIV></DIV>
<DIV class=3DSection1>
<P class=3DMsoNormal><FONT color=3D#4e4e4e size=3D2 face=3D"Century Gothic"=
><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; COLOR: #4e4e4e; FONT-SIZE: 10pt">Hi=
,=20
<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3D#4e4e4e size=3D2 face=3D"Century Gothic"=
><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; COLOR: #4e4e4e; FONT-SIZE: 10pt"><o=
:p>&nbsp;</o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3D#4e4e4e size=3D2 face=3D"Century Gothic"=
><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; COLOR: #4e4e4e; FONT-SIZE: 10pt">Ca=
n any=20
one explain me, how an IBIS Simulator (say, HSPICE) is interpreting an IBIS=
 file=20
given to it? <o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3D#4e4e4e size=3D2 face=3D"Century Gothic"=
><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; COLOR: #4e4e4e; FONT-SIZE: 10pt"><o=
:p>&nbsp;</o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3D#4e4e4e size=3D2 face=3D"Century Gothic"=
><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; COLOR: #4e4e4e; FONT-SIZE: 10pt">Su=
ppose=20
that I am simulating an IBIS file of a 2-state output buffer, using HSPICE =
by=20
giving a square wave [swing is from 0 to 5V and period is 33ns] as input.=
=20
&nbsp;Let&#8217;s assume that it&#8217;s a non-inverting buffer, and I obse=
rve that am=20
getting the same square wave at the output.<BR><BR>Can you tell me how exac=
tly=20
HSPICE finds the voltage values for each time, t? Which table(s) is used by=
=20
HSPICE for this?<BR><BR><o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3D#4e4e4e size=3D2 face=3D"Century Gothic"=
><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; COLOR: #4e4e4e; FONT-SIZE: 10pt">I =
also=20
observe that, even if I remove the V-T table and supply only the [Ramp]=20
information, HSPICE is able to simulate the buffer mo<st1:State=20
w:st=3D"on"><st1:place w:st=3D"on">del</st1:place></st1:State> with almost =
the same=20
accuracy. [I have 4 VT (2 Rise and 2 Fall) tables originally]<BR><BR>Can yo=
u=20
please clarify my doubts?<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3D#4e4e4e size=3D2 face=3D"Century Gothic"=
><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; COLOR: #4e4e4e; FONT-SIZE: 10pt"><o=
:p>&nbsp;</o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3D#4e4e4e size=3D2 face=3D"Century Gothic"=
><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; COLOR: #4e4e4e; FONT-SIZE: 10pt">Th=
anks,<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3D#4e4e4e size=3D2 face=3D"Century Gothic"=
><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; COLOR: #4e4e4e; FONT-SIZE: 10pt">Sh=
iju</SPAN></FONT><FONT=20
size=3D2 face=3D"Century Gothic"><SPAN=20
style=3D"FONT-FAMILY: 'Century Gothic'; FONT-SIZE: 10pt"><o:p></o:p></SPAN>=
</FONT></P></DIV>
<P><STRONG><SPAN=20
style=3D"FONT-FAMILY: 'Palatino Linotype','serif'; COLOR: green; FONT-SIZE:=
 10pt">Please=20
do not print this email unless it is absolutely necessary. </SPAN></STRONG>=
<SPAN=20
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<P>The information contained in this electronic message and any attachments=
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Please notify the sender immediately and destroy all copies of this message=
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any attachments. </P>
<P>WARNING: Computer viruses can be transmitted via email. The recipient sh=
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------------------------------

Date: Sat, 24 Apr 2010 13:44:43 -0600
From: "Mirmak, Michael" <michael.mirmak@intel.com>
Subject: [IBIS-Users] Use of IBIS-AMI models for standard interfaces by standards groups?

- --_000_F12A5FAAC7FFD14384BFFEFA94744FBEA70263CErrsmsx502amrcor_
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

I have been studying several industry interface specifications in detail la=
tely; specifically, SAS2 (available through www.t10.org<http://www.t10.org>=
) and PCI Express Gen. 3 (consult www.pci-sig.com<http://www.pci-sig.com>; =
membership may be required for document access).  Because of the high speed=
s of both, equalization is required and schemes such as DFE and CTLE are de=
scribed in considerable detail.  Some of these kinds of specifications incl=
ude equations for how a "spec reference" receiver is supposed to operate fo=
r simulation purposes.

None of the industry interface documents I have read so far mentions IBIS-A=
MI however, though some explicitly mention StatEye or even refer to the sta=
ndard group's own software or code for performing some simulation tasks.  S=
AS2 even provides MATLAB code for one analysis procedure as part of the spe=
cification document.

Is this not an opportunity?  Could one of our more enterprising readers use=
 the industry specification equations to create a "spec reference" IBIS-AMI=
 model for simulation purposes?  This would certainly be a benefit both to =
the standard involved as well as to IBIS-AMI adoption, not to mention the i=
ndividual or organization that actually releases the model.  While I'm cert=
ain that private versions may exist, I would like to suggest a public relea=
se of one or more of these specification models.

Any volunteers?

- -       MM



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<html>
<head>
<meta http-equiv=3D"Content-Type" content=3D"text/html; charset=3Dus-ascii">
<meta name=3D"Generator" content=3D"Microsoft Exchange Server">
<!-- converted from rtf -->
<style><!-- .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left:=
 #800000 2px solid; } --></style>
</head>
<body>
<font face=3D"Calibri, sans-serif" size=3D"2">
<div>I have been studying several industry interface specifications in deta=
il lately; specifically, SAS2 (available through <a href=3D"http://www.t10.=
org"><font color=3D"#0000FF"><u>www.t10.o</u></font><font color=3D"#0000FF"=
><u>rg</u></font></a>) and PCI Express
Gen. 3 (consult <a href=3D"http://www.pci-sig.com"><font color=3D"#0000FF">=
<u>www.pci-sig.com</u></font></a>; membership may be required for document =
access).&nbsp; Because of the high speeds of both, equalization is required=
 and schemes such as DFE and CTLE are described
in considerable detail.&nbsp; Some of these kinds of specifications include=
 equations for how a &#8220;spec reference&#8221; receiver is supposed to o=
perate for simulation purposes.</div>
<div><font face=3D"Times New Roman, serif">&nbsp;</font></div>
<div>None of the industry interface documents I have read so far mentions I=
BIS-AMI however, though some explicitly mention StatEye or even refer to th=
e standard group&#8217;s own software or code for performing some simulatio=
n tasks.  SAS2 even provides MATLAB code
for one analysis procedure as part of the specification document.</div>
<div>&nbsp;</div>
<div>Is this not an opportunity?&nbsp; Could one of our more enterprising r=
eaders use the industry specification equations to create a &#8220;spec ref=
erence&#8221; IBIS-AMI model for simulation purposes?&nbsp; This would cert=
ainly be a benefit both to the standard involved as well
as to IBIS-AMI adoption, not to mention the individual or organization that=
 actually releases the model.&nbsp; While I&#8217;m certain that private ve=
rsions may exist, I would like to suggest a public release of one or more o=
f these specification models.</div>
<div><font face=3D"Times New Roman, serif">&nbsp;</font></div>
<div>Any volunteers?</div>
<div>&nbsp;</div>
<ul style=3D"margin-top: 0pt; margin-bottom: 0pt; margin-left: 36pt; ">
<li>MM</li></ul>
<div><font face=3D"Times New Roman, serif">&nbsp;</font></div>
<div><font face=3D"Times New Roman, serif">&nbsp;</font></div>
</font>
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|
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------------------------------

Date: Wed, 9 Jun 2010 11:13:55 -0400
From: Eric Monteiro <Eric.Monteiro@gennum.com>
Subject: [IBIS-Users] AMI Cable EQ using QFB/AGC

Hello Everyone

I was wondering if anyone out there has implemented (or tied to) an IBIS AMI model of an AGC feedback loop.  If so (and you are willing to share), I am having some speed issues that I could use help solving.

In short, does anyone have experience using fft sample by sample using internal states(e.g. choosing how many samples to track)? I.e. similar to how veriloga does it.  Note:  I am doing this in C, not Matlab.

Details:
Right now my loop updates the AGC coeffients ( 3 to be exact, for 3 EQ stages ) 1 per sample (maybe I should do once per bit?).  This means that the 2nd and 3rd stage inputs change if the 1st AGC coeff changes, meaning I  have to revaluate the outputs of the 2nd and 3rd linear stages using fft in AMI GetWave instead of AMI init.  To help speed this up, I am opting for convolution for simple low pass filters, however I still need the fft for the linear EQ.

Source for any fucntion is avaible at any time for review or re-use (though I wouldn't ever consider myself a software engineer).

Best Regards,
Eric

This communication contains confidential information intended only for the addressee(s). If you have received this communication in error, please notify us immediately and delete this communication from your mail box.

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------------------------------

Date: Tue, 1 Jun 2010 10:03:57 -0400
From: "Lance Wang" <lwang@iometh.com>
Subject: [IBIS-Users] IBIS Summit Fourth Call of Papers and Participations - DAC June15th, 2010, Anaheim CA

All:

This is the fourth announcement for the IBIS Summit Meeting scheduled along
with the Design Automation Conference in Anaheim, California on June 15,
2010.

We have several presentations lined up, but have room for more.  Please sign
up if you are coming.  Also, you can sign up for the free pass at DAC
exhibition on Monday if you are on site.


Lance Wang
IO Methodology Inc.
www.iometh.com




- -----------------------------------------------------------------------
                          IBIS SUMMIT
                        FOURTH CALL FOR
                 PARTICIPATION & PRESENTATIONS
- -----------------------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

              I B I S   S U M M I T   M E E T I N G

Time/Date:  Tuesday June 15, 2010,  8:00 AM to 5:00 PM

Location:   Anaheim Marriott 
            777 Convention Way,
            Anaheim, California 92802
            Tel: 1-714-750-4321

Content:    Presentations and Discussions

Purpose:    Solicit and Exchange IBIS Model Related Information
            and Ideas.

Sponsors:   IBIS Open Forum

            If your company would be interested in sponsoring this
            event, please contact Lance Wang (lwang@iometh.com)
            Sponsorship is available for the room, lunch, and coffee breaks.

DAC:        June 13 - 18, 2010
            Anaheim Convention Center
            Anaheim, California

            FREE Exhibit Pass on Monday, June 14, 2010
            See <http://www.dac.com/> for more information.


BACKGROUND

    The Design Automation Conference (DAC) is the premier Electronic
    Design Automation (EDA) and silicon solution event.  Several vendors
    active in the IBIS Open Forum attend DAC.

    This meeting will be conducted as a formal IBIS Summit Meeting.
    Presentations are expected to be available and archived in an
    electronic format, and minutes of the meeting will be issued.
    Any pending formal decisions (votes) will be announced at least
    two weeks prior to the meeting.

    The annual election of officers will be held.  Nominations can
    be sent to Lance Wang (lwang@iometh.com) or made at the meeting.


CALL FOR PARTICIPANTS

   People involved in IBIS Model development, EDA tool development,
   and digital circuit design are invited to participate to the
   Summit meeting. If you plan to participate, please register with
   the information below:

   Name:
   E-mail address:
   Company:
   Telephone:

   Deadline, June 10, 2010.

Send to:

   Lance Wang (lwang@iometh.com)

CALL FOR PRESENTATIONS

   We are seeking presentations from individuals who have IBIS
   experiences or issues.

   Format of Presentation:  LCD Projection with Windows laptop.
   Time: 15-30 Minutes
   Electronic Archival: We request electronic versions so that the
         presentations can be archived and also made available to
         non-attendees.  Formats used in the past have been text,
         Power Point, Word, Postscript, and Acrobat.  Electronic
         presentations should be made available by June 7, 2010
         for uploading and copying to the presentation laptop.

If you plan a presentation, please supply

   Title:
   Presenter:
   E-mail address:
   Company:
   Telephone:

   Estimate Time:

Send this to:

   Lance Wang (lwang@iometh.com)


AGENDA

   The agenda includes presentations, discussions, breaks, and a
   luncheon (which will be provided).  This will be developed as
   presentation proposals are received.

LIST OF NEARBY HOTELS

   See (http://www.dac.com/) for travel directions, hotels and
   other information or use other search engines.





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|  http://www.eda-stds.org/pub/ibis/users_archive/ Recent
|  http://www.eda-stds.org/pub/ibis/email/         E-mail since 1993

------------------------------

Date: Wed, 19 May 2010 18:17:58 +0800
From: ji xiao <xiaoji86@gmail.com>
Subject: [IBIS-Users] problems about extracting IV curves from SPICE model

- --0016e64b009ab160ee0486efc539
Content-Type: text/plain; charset=ISO-8859-1

Hi, everyone.
For my research purpose, I want to extract IV data (pullup, pulldown, etc.)
from the SPICE model of inverter 74lvc04a, and the result is supposed to be
similar to the IBIS IV table. However, for my case, there is a large
difference (around 10 times smaller than the IV table in IBIS file) although
the whole curve trend looks similar. And it exists for all IV curves.
For my circuit connection, let's take pulldown curve as an example, I give
corresponding Vdd voltage source to power suply, ground input and connect
the output to a variable voltage source (V1) and use a current probe to
measure the output current(I1) at the output port. I plot the IV curve I1
vs. V1 and treat it as the pulldown curve. No floating voltage source in the
circuit.
Can anyone tell me what's wrong with my connection?

Thanks and regards,
Yuancheng

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<div>Hi, everyone.</div>
<div>For my research purpose, I want to extract IV=A0data (pullup, pulldown=
, etc.) from the SPICE model of inverter 74lvc04a, and the result is suppos=
ed to be similar to the IBIS IV table. However, for my case, there is a lar=
ge difference (around 10 times smaller than the IV table in IBIS file) alth=
ough the whole curve trend looks similar. And it exists for all IV curves.<=
/div>

<div>For my circuit connection, let&#39;s take pulldown curve as an example=
, I give corresponding Vdd voltage source=A0to power suply, ground input an=
d connect the output to a variable voltage source (V1) and use a current pr=
obe to measure the output current(I1) at the output port. I plot the IV cur=
ve I1 vs. V1 and treat it as the pulldown curve. No floating voltage source=
 in the circuit.</div>

<div>Can anyone tell me=A0what&#39;s wrong with my connection?</div>
<div>=A0</div>
<div>Thanks and regards,</div>
<div>Yuancheng</div>
<div>=A0</div>
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------------------------------

Date: Thu, 29 Jul 2010 14:51:50 -0700
From: "Alavi, Peggy" <Peggy.Alavi@nsc.com>
Subject: [IBIS-Users] Mismatch between ibischk and load lines

- --_000_CB2B044BB730A04391E9C27D23E3A82935AA9395BFEXMAIL02scwfn_
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 charset=us-ascii
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Hello,

I am working on an IBIS Model and the golden parser (I have used 4.1, 4.2, =
and 5.0 and my model is IBIS 4.2) gives me errors (on the high side - pull =
up curve) on one of my outputs. I have independently verified the load line=
 and where it crosses the PD and PU curves, and the crossing exactly matche=
s my transient end values, and does not match what the parser is claiming t=
he crossings are. What could I be doing wrong?

Best,

- -Peggy


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<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Arial","s=
ans-serif";
color:navy'>Hello,<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Arial","s=
ans-serif";
color:navy'><o:p>&nbsp;</o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Arial","s=
ans-serif";
color:navy'>I am working on an IBIS Model and the golden parser (I have used
4.1, 4.2, and 5.0 and my model is IBIS 4.2) gives me errors (on the high si=
de &#8211;
pull up curve) on one of my outputs. I have independently verified the load
line and where it crosses the PD and PU curves, and the crossing exactly
matches my transient end values, and does not match what the parser is clai=
ming
the crossings are. What could I be doing wrong?<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Arial","s=
ans-serif";
color:navy'><o:p>&nbsp;</o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Arial","s=
ans-serif";
color:navy'>Best,<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Arial","s=
ans-serif";
color:navy'><o:p>&nbsp;</o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Arial","s=
ans-serif";
color:navy'>-Peggy<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Arial","s=
ans-serif";
color:navy'><o:p>&nbsp;</o:p></span></p>

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