=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of=20 surendra.deshmukh@wipro.com
Sent: Thursday, September 16, 201= 0=20 6:33 AM
To: ibis-users@eda.org
Subject: [IBIS-Users]=20 Simulation with VT tables for different load conditions

Hi,<= /P>

= ; =20 The IBIS specification permits up to 100 (VT) waveforms to be included to= =20 describe buffer transitions, using a variety of loading conditions. Can I g= et=20 the answer how these tables are used during simulation for a different load= =20 condition?

= ; =20 E.g. If VT tables are generated for C_fixture of 5pf and 10pf and=20 simulation has to be done with C_fixture of 8pf then how simulator will tak= e=20 these 5pf and 10pf tables for its simulation at 8pf of=20 load?

Thanks in=20 advance.

Regards

Surendra.

Please=20 do not print this email unless it is absolutely necessary. =

The information contained in this electronic message and any attachments= to=20 this message are intended for the exclusive use of the addressee(s) and may= =20 contain proprietary, confidential or privileged information. If you are not= the=20 intended recipient, you should not disseminate, distribute or copy this e-m= ail.=20 Please notify the sender immediately and destroy all copies of this message= and=20 any attachments.

WARNING: Computer viruses can be transmitted via email. The recipient sh= ould=20 check this email and any attachments for the presence of viruses. The compa= ny=20 accepts no liability for any damage caused by any virus transmitted by this= =20 email.

www.wipro.com

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This message has been scanned for viruses a= nd=20
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This message has been scanned for viruses and
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believed to be clean. - ------_=_NextPart_001_01CB55C9.09A5CB98-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 10 Sep 2010 18:03:12 -0400 From: "Fraser, Bryan" Subject: [IBIS-Users] Differential V-I bench measurement This is a multi-part message in MIME format. - ------_=_NextPart_001_01CB5133.F7BD2150 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I'm working on creating my first ibis model based on bench data and was wondering if anyone might be able to help... =20 How would you make the V-I measurement on a differential input with pure differential on chip termination. I've read the cookbook... and it doesn't really explain how to do this on the bench. =20 Thanks, Bryan =20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01CB5133.F7BD2150 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

I’m working on cre= ating my first ibis model based on bench data and was wondering if anyone might be a= ble to help…

How would you make the V= - -I measurement on a differential input with pure differential on chip termin= ation.

I’ve read the cookbook… and it doesn’t really explain how to do this on the b= ench.

Thanks,

Bryan<= /p>

--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------_=_NextPart_001_01CB5133.F7BD2150-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 27 Aug 2010 14:22:31 -0700 From: Bob Ross Subject: [IBIS-Users] [SI-LIST] Asain IBIS Summit (Taiwan) - First Announcement To All: The IBIS Open Forum is holding an Asian IBIS Summit Meeting in Taipei, Taiwan a major technology center on Friday, November 12, 2010. This is an early initial announcement for travel planning. Several companies listed below are co-sponsoring this major event to be held at the Sherwood Hotel, Taipei. We are planning for many local attendees and also several IBIS experts from the USA. We encourage technical contributions from Asia. We expect a full agenda of relevant material. Note we are also holding these Asian IBIS Summit meetings: Shenzhen, P.R. China, Tuesday November 9, Four Points Hotel Tokyo, Japan, Monday, November 15, JEITA headquarters Bob Ross Teraspeed Consulting Group Polin Chi Sigrity - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (TAIWAN) FIRST CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- A S I A N I B I S S U M M I T ( T A I W A N ) Time/Date: Tuesday, November 9, 2010, 8:00 AM to 4:30 PM Meeting starts at 8:30 AM Location: Sherwood Hotel 11 Min Sheng E Road, Sec. 3 Taipei, Taiwan Rooms: Ballroom I and II Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Co-sponsors (in alphabetical order): Agilent Technologies Avant Technology (IO Methodology) Foxconn ICT-Lanto Intel Corporation Sigrity Synopsys Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND We have held many successful Summit meetings across Asia in previous years. This year we are adding a meeting in Taipei where many national and international high technology companies have operations. Presentations from past events are available at our Summit archive: http://www.eda.org/pub/ibis/summits/ Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register using the information below (in English): Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Comments: Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Polin Chi, Sigrity polinchi@sigrity.com SIGNUP DEADLINE: November 4, 2010 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: October 22, 2010 to produce the presentation copies for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in Chinese. Submissions from Taiwan and across Asia are strongly encouraged, though submissions from other regions are very welcome. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:00 - 8:30 Vendor table setup and tables 8:00 - 8:30 Sign in 8:30 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 16:30 Presentations The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several major IBIS Committee presentations from IBIS officers or active members are planned. Several presentations on IBIS applications and behavioral modeling issues, including interconnects and system components, are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@freelists.org with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@freelists.org with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: http://www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 22 Sep 2010 18:55:00 -0700 From: Bob Ross Subject: [IBIS-Users] [SI-LIST] Asian IBIS Summit (China) Fourth Announcement To All: The IBIS Open Forum is holding an Asian IBIS Summit Meeting in Shenzhen, China, a major technology center on Tuesday, November 9, 2010 Several companies listed below are co-sponsoring this large event to be held at the Four Points by Sheraton, Shenzhen. Like in previous years, we are planning for a large number of attendees including several IBIS experts from the USA. We encourage technical contributions from Asia. We expect a full agenda of relevant material. For travel consideration, two other Asian IBIS Summits follow this event: Taipei, Taiwan, Friday, November 12, Sherwood Hotel Tokyo, Japan, Monday, November 15, JEITA headquarters Bob Ross Teraspeed Consulting Group Lance Wang IO Methodology Inc. - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (CHINA) FOURTH CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- http://www.eda.org/pub/ibis/summits/nov10a/announcement_chinese.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( C H I N A ) Time/Date: Tuesday, November 9, 2010, 8:00 AM to 5:30 PM Meeting starts at 9:00 AM Location: Four Points by Sheraton 5 Guihua Road Futian Free Trade Zone Shenzhen, Guangdong 518038 P. R. China http://www.starwoodhotels.com/fourpoints/property/overview/index.html?propertyID=1489& EM=VTY_FP_1489_shenzhen_overview or http://tinyurl.com/2s6esb Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Primary Sponsor: Huawei Technologies Co-sponsors (in alphabetical order): Agilent Technologies, Ansoft Corporation, Cadence Design Systems, Cybernet, Intel Corporation, IO Methodology, Mentor Graphics Corporation, Signal Integrity Software (SiSoft), Sigrity, Synopsys, and ZTE Corporation. Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND We have held five successful meetings in Shenzhen, Shanghai and Beijing. This year we are meeting again in Shenzhen where many Chinese and foreign high technology companies operate. These events are archived along with all our other Summits: http://www.eda.org/pub/ibis/summits/ Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register using the information below (in English): Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Comments: (Such as assistance for the travel requirements at the end) Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Lance Wang, IO Methology Inc. lwang@iometh.com SIGNUP DEADLINE: November 4, 2010 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: October 12, 2010 to produce the presentation booklet for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in Mandarin. Submissions from Asia are encouraged along with other submissions world-wide. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:15 - 9:00 Vendor table setup and tables 8:30 - 9:00 Sign in 9:00 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 17:00 Presentations The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some future technical directions in IBIS. Several major IBIS Committee presentations from IBIS officers or active members are planned. Several presentations on IBIS applications and behavioral modeling issues, including interconnects, and system components are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. Comply with your travel rules, such as indicated in the link below to China and Shenzhen. Work with your travel agent. Notify us as a sign-up comment if you need assistance. Visas, if needed, should fall in the visit/business category: http://travel.state.gov/travel/cis_pa_tw/cis/cis_1089.html - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@freelists.org with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@freelists.org with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: http://www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 10 Sep 2010 15:58:11 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] Differential V-I bench measurement This is a multi-part message in MIME format. - ------=_NextPart_000_0AC2_01CB5100.F8B54430 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Bryan We do this all the time. From your description you want to have the final model have a floating 100 Ohm termination. The best way to achieve this is to model the termination as a series resistor between the two inputs. You then model the inputs without any resistance between them making sure when you measure them you don't pass any current in the resistor. You use the Diff Pin table to connect the two inputs as a differential pair. You use the Series Pin Mapping to place the termination between the two inputs. And use a R Series as the termination. Arpad came up with another method to do this using multiple IV tables but I'm not sure how much support there is in simulators for this. See the IBIS archives for details. Tom Dagostino Teraspeed Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 www.teraspeed.com From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Fraser, Bryan Sent: Friday, September 10, 2010 3:03 PM To: ibis-users@eda-stds.org Subject: [IBIS-Users] Differential V-I bench measurement I'm working on creating my first ibis model based on bench data and was wondering if anyone might be able to help. How would you make the V-I measurement on a differential input with pure differential on chip termination. I've read the cookbook. and it doesn't really explain how to do this on the bench. Thanks, Bryan - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0AC2_01CB5100.F8B54430 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Bryan<= /p>

We do this all the time.=

From your description yo= u want to have the final model have a floating 100 Ohm termination. The best= way to achieve this is to model the termination as a series resistor between the two inputs. You then model the inputs without any resistance between them making sure when you measure them you don’t pass any current in the resistor. You use the Diff Pin table to connect the two inputs as a differential pair. You use the Series Pin Mapping to place the termin= ation between the two inputs. And use a R Series as the termination.<= o:p>

Arpad came up with anoth= er method to do this using multiple IV tables but I’m not sure how much support there is in simulators for this. See the IBIS archives for details.

Tom Dagostino=

Teraspeed Labs

13610 SW Harness Lane

Beaverton, OR 97008=

503-430-1065<= /span>

tom@teraspeed.com <= /o:p>

www.teraspeed.com <= /o:p>

Teraspeed Consulting Gro= up LLC

121 North River Drive
Narragansett, RI 02882

401-284-1827<= /span>

www.teraspeed.com =

From: owner-ibis-us= ers@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Fraser, Bryan
Sent: Friday, September 10, 2010 3:03 PM
To: ibis-users@eda-stds.org
Subject: [IBIS-Users] Differential V-I bench measurement<= /span>

I’m working on cre= ating my first ibis model based on bench data and was wondering if anyone might be a= ble to help…

How would you make the V= - -I measurement on a differential input with pure differential on chip terminat= ion.

I’ve read the cookbook… and it doesn’t really explain how to do this on the bench.

Thanks,

Bryan<= /p>

- --
This message has been scanned for viruses and
dangerous content by MailScanne= r, and is
believed to be clean.

--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_0AC2_01CB5100.F8B54430-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 16 Sep 2010 09:15:18 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] Non-existence of C_load in [Ramp] keyword This is a multi-part message in MIME format. - ------_=_NextPart_001_01CB55BA.5AEF3FA7 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Tom's comments are also valid for L_fixture. If you ever wonder how you can design a test load that looks like a pure resistor, just make a nice long T-line so that the reflection doesn't come back to the driver before it is done with the transition... =20 To understand why Tom's suggestions are correct, look at my presentation: =20 http://www.eda.org/ibis/summits/mar06/muranyi1.pdf =20 Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Tom Dagostino Sent: Thursday, September 16, 2010 11:07 AM To: surendra.deshmukh@wipro.com; ibis-users@eda.org Subject: RE: [IBIS-Users] Non-existence of C_load in [Ramp] keyword The RAMP key word only allows a purely resistive load which is the load that should be used for extraction of VT curves and thus ramps. My experience with models that have had non zero C_fixture is not good. The simulators that I used with these models did not produce acceptable results showing incredible amounts of waveform distortion. It is my recommendation (and from members of the IBIS committee that I have discussed this with) not to use C_fixture when extracting the VT curves. If you are making a model from SPICE there is no need to have any capacitance in the load when doing the simulations. If you are making the model from measurements you should be able to design the test fixture to minimize any stray parasitic. BUT IN ANY CASE DO NOT INCLUDE CREF IN THE MODEL UNDER C_FIXTURE!!! =20 Regards, =20 Tom Dagostino Teraspeed Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com=20 www.teraspeed.com=20 =20 Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 www.teraspeed.com=20=20 =20 From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of surendra.deshmukh@wipro.com Sent: Thursday, September 16, 2010 4:56 AM To: ibis-users@eda.org Subject: [IBIS-Users] Non-existence of C_load in [Ramp] keyword =20 Hi, The [Ramp] keyword used in IBIS initial version is still there in new versions along with VT tables. This Ramp keyword also gives Rload value.=20 My question is as far as these VT tables are calculated only for Rixture (or Rload), simulator has a choice to take value from [Ramp] keyword without any problem but if these tables are generated for Rfixture and C_fixture values (non-zero C_fixture value) then there is no any keyword C_load inside the [Ramp] section.=20 How the simulator handles this case where [Ramp] is calculated for Rfixture and C_fixture but there is no any C_load keyword in ramp section? Does [Ramp] require any C_load keyword?=20=20 =20 Regards Surendra Please do not print this email unless it is absolutely necessary.=20 The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments.=20 WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email.=20 www.wipro.com=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner , and is believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------_=_NextPart_001_01CB55BA.5AEF3FA7 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Tom's comments are also valid for=20 L_fixture.

If you ever wonder how you can design a=20 test

load that looks like a pure resistor,=20 just

make a nice long T-line so that the=20 reflection

doesn't come back to the driver before it=20 is

done with the transition...

To understand why Tom's suggestions are=20 correct,

look at my presentation:

http://www.eda.= org/ibis/summits/mar06/muranyi1.pdf

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D

From: owner-ibis-users@eda.org=20 [mailto:owner-ibis-users@eda.org] On Behalf Of Tom=20 Dagostino
Sent: Thursday, September 16, 2010 11:07 AM
To:=20 surendra.deshmukh@wipro.com; ibis-users@eda.org
Subject: RE:=20 [IBIS-Users] Non-existence of C_load in [Ramp] keyword

The=20 RAMP key word only allows a purely resistive load which is the load that sh= ould=20 be used for extraction of VT curves and thus ramps. My experience wit= h=20 models that have had non zero C_fixture is not good. The simulators t= hat I=20 used with these models did not produce acceptable results showing incredibl= e=20 amounts of waveform distortion. It is my recommendation (and from mem= bers=20 of the IBIS committee that I have discussed this with) not to use C_fixture= when=20 extracting the VT curves. If you are making a model from SPICE there = is no=20 need to have any capacitance in the load when doing the simulations. = If=20 you are making the model from measurements you should be able to desi= gn=20 the test fixture to minimize any stray parasitic. BUT IN ANY CASE DO = NOT=20 INCLUDE CREF IN THE MODEL UNDER C_FIXTURE!!!

Regards,

Tom=20 Dagostino

Teraspeed=20 Labs

13610=20 SW Harness Lane

Beaverton,=20 OR 97008

503-430-1065

tom@teraspeed.com=20

www.teraspeed.com=20

Teraspeed=20 Consulting Group LLC

121=20 North River Drive
Narragansett, RI 02882

401-284-1827

www.teraspeed.com =20

From:<= /B>=20 owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of= =20 surendra.deshmukh@wipro.com
Sent: Thursday, September 16, 201= 0=20 4:56 AM
To: ibis-users@eda.org
Subject: [IBIS-Users]=20 Non-existence of C_load in [Ramp] keyword

Hi,=

= =20 The [Ramp] keyword used in IBIS initial version is still there in new= =20 versions along with VT tables. This Ramp keyword also gives Rload value.=20

My quest= ion is=20 as far as these VT tables are calculated only for Rixture (or Rload), simul= ator=20 has a choice to take value from [Ramp] keyword without any problem but if t= hese=20 tables are generated for Rfixture and C_fixture values (non-zero C_fixture= =20 value) then there is no any keyword C_load inside the [Ramp] section.=20

&n= bsp; =20 How the simulator handles this case where [Ramp] is calculated for=20 Rfixture and C_fixture but there is no any C_load keyword in ramp section? = Does=20 [Ramp] require any C_load keyword?

Regards

Surendra<= /o:p>

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