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To: ibis-users-digest@eda.org
Subject: ibis-users V1 #163
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ibis-users          Monday, November 15 2010          Volume 01 : Number 163




----------------------------------------------------------------------

Date: Mon, 25 Oct 2010 17:03:29 -0700
From: "Muranyi, Arpad" <Arpad_Muranyi@mentor.com>
Subject: RE: [IBIS-Users] Bus Switch IBIS Models

This is a multi-part message in MIME format.

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Tim,

=20

It all depends on the device, but in the off state I

would not expect it to have any significant series

current that you would need to model with [Series=20

Current].  Series bus switches are usually in a fairly

high impedance state when they are turned off...

=20

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D

=20

=20

From: Timothy Coyle [mailto:tim.coyle@siconsultant.com]=20
Sent: Friday, October 22, 2010 12:50 PM
To: 'Mike LaBonte'; Muranyi, Arpad; 'IBIS'
Subject: RE: [IBIS-Users] Bus Switch IBIS Models

=20

How about when the switch is in the Off state. Is there a situation
where you need to simulate that with actual data such as [Series
Current] or is [R Series] sufficient? Does the EDA tool just need a way
to disable the switch in a batch mode type simulation?

=20

Thanks

=20

Tim

=20

=20

From: Mike LaBonte [mailto:milabont@cisco.com]=20
Sent: Friday, October 22, 2010 11:04 AM
To: Arpad Muranyi; Timothy Coyle; IBIS
Subject: Re: [IBIS-Users] Bus Switch IBIS Models

=20

More exactly, IBIS does not have time profile data to model the
transition of a series switch between on and off states. It is certainly
possible to convert the IBIS series switch model data to a circuit model
using table elements, in which a control signal makes the switch
transition dynamically from on to off and vice-versa. The switching time
profile would have to be set by the control signal. I believe the
Cadence implementation works this way, but I have heard of only one
instance of someone using the capability (experimentally).

I agree with Tim that automation of [Series Switch Groups] and on/off
control at the EDA tool end is lacking. I think Tim is asking the right
question, "does anyone really need it?"

Mike

On 10/22/10 10:25 AM, "Arpad Muranyi" <Arpad_Muranyi@mentor.com> wrote:

Tim,
=20
IBIS doesn't support modeling the transitions between the On/Off state.
The assumption is that this is not changing during simulations.  There
is no information in the models that describes how these devices would
transition from one state to the other.  We would need something like
the V-t tables in order to do that, but they don't exist for this
purpose.
=20
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
=20

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Timothy Coyle
Sent: Thursday, October 21, 2010 11:35 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Bus Switch IBIS Models

Hi,
When you have MOSFET switch and model it using [Series Mosfet] keyword
in IBIS there are two ways to pin map it. The first way is to use
[Model] Series and just use [Series Pin Mapping] and this assumes that
the switch is always in On state. The other way is to use [Model]
Series_switch with [Series Pin Mapping] and [Series Switch Groups] and
this way there can be configured On and Off states. However I have found
that most simulation/cad tools do not fully support [Series Switch
Groups] without manual modification by end user. Modeling the switch as
a Series device just Series Pin Mapping seems to be the default
supported state.
=20
Has anyone else seen this issues of Series Switch Groups not being
supported? Even when I do some modifications for a tool to support it
many do not seem to use the Off state data. I would also be interested
to hear of the simulation usage case where someone needs the ability to
switch between On and Off states.=20
=20
Thanks,
=20
Timothy Coyle
President
Signal Consulting Group LLC
405 Western Ave #430=20
South Portland, ME  04106
Tel: 617.297.2566
Email: tim.coyle@siconsultant.com <mailto:tim.coyle@siconsultant.com>=20
Web: http://www.siconsultant.com <http://www.siconsultant.com/>=20
SharkSim <http://www.sharksim.com/> - Signal Integrity IBIS Modeling
Software


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<div class=3DWordSection1>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'>Tim,<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'><o:p>&nbsp;</o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'>It all depends on the device, but in the off state I<o:p></o:p=
></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'>would not expect it to have any significant series<o:p></o:p><=
/span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'>current that you would need to model with [Series <o:p></o:p><=
/span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'>Current].&nbsp; Series bus switches are usually in a fairly<o:=
p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'>high impedance state when they are turned off&#8230;<o:p></o:p=
></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'><o:p>&nbsp;</o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'>Arpad<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'><o:p>&nbsp;</o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:10.0pt;font-family:"Courier N=
ew";
color:black'><o:p>&nbsp;</o:p></span></p>

<div>

<div style=3D'border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in =
0in 0in'>

<p class=3DMsoNormal><b><span style=3D'font-size:10.0pt;font-family:"Tahoma=
","sans-serif"'>From:</span></b><span
style=3D'font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Timothy Coyle
[mailto:tim.coyle@siconsultant.com] <br>
<b>Sent:</b> Friday, October 22, 2010 12:50 PM<br>
<b>To:</b> 'Mike LaBonte'; Muranyi, Arpad; 'IBIS'<br>
<b>Subject:</b> RE: [IBIS-Users] Bus Switch IBIS Models<o:p></o:p></span></=
p>

</div>

</div>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

<p class=3DMsoNormal><span style=3D'font-size:11.0pt;font-family:"Calibri",=
"sans-serif";
color:#1F497D'>How about when the switch is in the Off state. Is there a
situation where you need to simulate that with actual data such as [Series
Current] or is [R Series] sufficient? Does the EDA tool just need a way to
disable the switch in a batch mode type simulation?<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:11.0pt;font-family:"Calibri",=
"sans-serif";
color:#1F497D'><o:p>&nbsp;</o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:11.0pt;font-family:"Calibri",=
"sans-serif";
color:#1F497D'>Thanks<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:11.0pt;font-family:"Calibri",=
"sans-serif";
color:#1F497D'><o:p>&nbsp;</o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:11.0pt;font-family:"Calibri",=
"sans-serif";
color:#1F497D'>Tim<o:p></o:p></span></p>

<p class=3DMsoNormal><span style=3D'font-size:11.0pt;font-family:"Calibri",=
"sans-serif";
color:#1F497D'><o:p>&nbsp;</o:p></span></p>

<p class=3DMsoNormal><a name=3D"_MailEndCompose"></a><span style=3D'font-si=
ze:11.0pt;
font-family:"Calibri","sans-serif";color:#1F497D'><o:p>&nbsp;</o:p></span><=
/p>

<div>

<div style=3D'border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in =
0in 0in'>

<p class=3DMsoNormal><b><span style=3D'font-size:10.0pt;font-family:"Tahoma=
","sans-serif"'>From:</span></b><span
style=3D'font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Mike LaBonte
[mailto:milabont@cisco.com] <br>
<b>Sent:</b> Friday, October 22, 2010 11:04 AM<br>
<b>To:</b> Arpad Muranyi; Timothy Coyle; IBIS<br>
<b>Subject:</b> Re: [IBIS-Users] Bus Switch IBIS Models<o:p></o:p></span></=
p>

</div>

</div>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

<p class=3DMsoNormal style=3D'margin-bottom:12.0pt'><span style=3D'font-siz=
e:11.0pt;
font-family:"Calibri","sans-serif"'>More exactly, IBIS does not have time
profile data to model the transition of a series switch between on and off
states. It is certainly possible to convert the IBIS series switch model da=
ta
to a circuit model using table elements, in which a control signal makes the
switch transition dynamically from on to off and vice-versa. The switching =
time
profile would have to be set by the control signal. I believe the Cadence i=
mplementation
works this way, but I have heard of only one instance of someone using the
capability (experimentally).<br>
<br>
I agree with Tim that automation of [Series Switch Groups] and on/off contr=
ol
at the EDA tool end is lacking. I think Tim is asking the right question,
&#8220;does anyone really need it?&#8221;<br>
<br>
Mike<br>
<br>
On 10/22/10 10:25 AM, &quot;Arpad Muranyi&quot; &lt;<a
href=3D"Arpad_Muranyi@mentor.com">Arpad_Muranyi@mentor.com</a>&gt; wrote:</=
span><o:p></o:p></p>

<p class=3DMsoNormal style=3D'margin-bottom:12.0pt'><span style=3D'font-siz=
e:10.0pt;
font-family:"Courier New"'>Tim,<br>
&nbsp;<br>
IBIS doesn&#8217;t support modeling the transitions between the On/Off stat=
e.<br>
The assumption is that this is not changing during simulations. &nbsp;There=
<br>
is no information in the models that describes how these devices would<br>
transition from one state to the other. &nbsp;We would need something like<=
br>
the V-t tables in order to do that, but they don&#8217;t exist for this<br>
purpose.<br>
&nbsp;<br>
Arpad<br>
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<br>
&nbsp;<br>
</span><span style=3D'font-size:11.0pt;font-family:"Calibri","sans-serif"'>=
<br>
</span><b><span style=3D'font-size:10.0pt;font-family:"Tahoma","sans-serif"=
'>From:</span></b><span
style=3D'font-size:10.0pt;font-family:"Tahoma","sans-serif"'> <a
href=3D"owner-ibis-users@eda.org">owner-ibis-users@eda.org</a> [<a
href=3D"mailto:owner-ibis-users@eda.org">mailto:owner-ibis-users@eda.org</a=
>] <b>On
Behalf Of </b>Timothy Coyle<br>
<b>Sent:</b> Thursday, October 21, 2010 11:35 AM<br>
<b>To:</b> <a href=3D"ibis-users@eda.org">ibis-users@eda.org</a><br>
<b>Subject:</b> [IBIS-Users] Bus Switch IBIS Models<br>
</span><span style=3D'font-size:11.0pt;font-family:"Calibri","sans-serif"'>=
<br>
Hi,<br>
When you have MOSFET switch and model it using [Series Mosfet] keyword in I=
BIS
there are two ways to pin map it. The first way is to use [Model] Series and
just use [Series Pin Mapping] and this assumes that the switch is always in=
 On
state. The other way is to use [Model] Series_switch with [Series Pin Mappi=
ng]
and [Series Switch Groups] and this way there can be configured On and Off
states. However I have found that most simulation/cad tools do not fully
support [Series Switch Groups] without manual modification by end user.
Modeling the switch as a Series device just Series Pin Mapping seems to be =
the
default supported state.<br>
&nbsp;<br>
Has anyone else seen this issues of Series Switch Groups not being supporte=
d?
Even when I do some modifications for a tool to support it many do not seem=
 to
use the Off state data. I would also be interested to hear of the simulation
usage case where someone needs the ability to switch between On and Off sta=
tes.
<br>
&nbsp;<br>
Thanks,<br>
&nbsp;<br>
</span><span style=3D'font-size:11.0pt;font-family:"Arial","sans-serif";
color:#1F497D'>Timothy Coyle<br>
President<br>
Signal Consulting Group LLC<br>
405 Western Ave #430 <br>
South Portland, ME &nbsp;04106<br>
Tel: 617.297.2566<br>
Email: </span><span style=3D'font-size:11.0pt;font-family:"Arial","sans-ser=
if"'><a
href=3D"tim.coyle@siconsultant.com">tim.coyle@siconsultant.com</a></span><s=
pan
style=3D'font-size:11.0pt;font-family:"Calibri","sans-serif"'> &lt;<a
href=3D"mailto:tim.coyle@siconsultant.com">mailto:tim.coyle@siconsultant.co=
m</a>&gt;
<br>
</span><span style=3D'font-size:11.0pt;font-family:"Arial","sans-serif";
color:#1F497D'>Web: </span><span style=3D'font-size:11.0pt;font-family:"Ari=
al","sans-serif"'><a
href=3D"http://www.siconsultant.com">http://www.siconsultant.com</a></span>=
<span
style=3D'font-size:11.0pt;font-family:"Calibri","sans-serif"'> &lt;<a
href=3D"http://www.siconsultant.com/">http://www.siconsultant.com/</a>&gt; =
<br>
</span><span style=3D'font-size:11.0pt;font-family:"Arial","sans-serif"'>Sh=
arkSim</span><span
style=3D'font-size:11.0pt;font-family:"Calibri","sans-serif"'> &lt;<a
href=3D"http://www.sharksim.com/">http://www.sharksim.com/</a>&gt; </span><=
span
style=3D'font-size:11.0pt;font-family:"Arial","sans-serif";color:#1F497D'>-
Signal Integrity IBIS Modeling Software</span><o:p></o:p></p>

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------------------------------

Date: Fri, 28 May 2010 10:16:29 -0700
From: "Tom Dagostino" <tom@teraspeed.com>
Subject: RE: [IBIS-Users] IBIS DIFF input buffers

Tim

There problem with including the ODT in a power or ground clamp if that
differential termination is meant to float.  Once you put that resistive
characteristic in one or both of the clamp table the resistor is now tied to
a voltage - it won't float anymore.  Many if not all LVDS IBIS drivers
behave totally different when driving a floating differential termination
vs. a termination to a fixed voltage.  A clamp based termination works well
for CML receivers that typically have the 50 Ohm termination tied to Vdd but
many technologies such as LVDS use floating terminations.

Regards,

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827 


- -----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of Timothy Coyle
Sent: Friday, May 28, 2010 9:45 AM
To: 'Eric Monteiro'; ibis-users@eda.org
Subject: RE: [IBIS-Users] IBIS DIFF input buffers

Hi Eric,
If I understand you correctly you are using single-ended buffers to model
the inverting and non-inverting pins of a differential input buffer and you
are using the Series R keyword in IBIS to represent the on-die termination.

If so, then in general, your approach will be valid. Basically you will want
to generate the ground and power clamp IV curve on one differential input
pin. Depending on the differential buffer design and technology
(LVDS,CML,etc) you can leave the other differential input pin floating or
you may have to put some type of load on it as a feedback loop. Other
assumptions are that there is not differential current flowing as in a true
differential buffer and that you can essentially treat your differential
design as pseudo differential. If your differential design is unbalanced
then you should create separate buffer models for each differential input
pin. 

Unfortunately there are still a lot of EDA tool issues with using Series pin
mapping and keywords so be aware of your end customers target environment.
You could also always try and include the on-die termination current in the
clamp IV curves to avoid using the Series keywords.

Hope this helps.

Best,

Tim


- -----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of Eric Monteiro
Sent: Thursday, May 27, 2010 4:45 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] IBIS DIFF input buffers

Hello Everyone

I need a little validation/clarification.

I have a differential input IBIS model, however my IBIS simulator is so out
of date that it does not recognize the Series Keywords.  So instead what I
did was remove the series maping, and placed 2 single ended buffers with a
resitor whos value equalled that in the Series R definition:  i.e.

- ------------|BUFFER|
        |
        Z
        Z
        |
- ------------|BUFFER|

My understanding is that the Diff buffer in IBIS DC tables should be the
COMMON mode current into ONE of the diffential pins (i.e. I assume its not
the sum of the current into the 2 pins, or 2 times the current I think it
is).  Based on that, the above should be valid.  Can anyone confirm?

Cheers,
Eric

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------------------------------

Date: Wed, 19 May 2010 14:45:39 -0400
From: "Andrew Ingraham" <a.ingraham@ieee.org>
Subject: Re: [IBIS-Users] problems about extracting IV curves from SPICE model

> For my circuit connection, let's take pulldown curve as an example, I give
> corresponding Vdd voltage source to power suply, ground input and connect
> the output to a variable voltage source (V1) and use a current probe to
> measure the output current(I1) at the output port. I plot the IV curve I1
> vs. V1 and treat it as the pulldown curve. No floating voltage source in
> the circuit.
> Can anyone tell me what's wrong with my connection?

Yuancheng,

Other than the fact that the 74lvc04a is an inverter, so grounding the input
drives the output high (pullup not pulldown ... I'm thinking it was a typo),
your connections seem about right.

Did you do this as a .DC sweep, or a slow transient simulation?

The LVC part has a very wide supply voltage range.  Did you use a supply
voltage consistent with the IBIS table you compared it to?

How well does both your simulated data, and the IBIS data, compare with the
part's DC specifications for Voh and Vol?

Regards,
Andy



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------------------------------

Date: Tue, 04 May 2010 10:38:57 -0700
From: Bob Ross <bob@teraspeed.com>
Subject: [IBIS-Users] European IBIS Summit Meeting Agenda - May 12, 2010

All:

The 13th European IBIS Summit is on Wednesday afternoon and
follows the IEEE Workshop on Signal Propagation on Interconnects:

   http://www.spi.uni-hannover.de/

Below is the meeting agenda.  The IBIS meetng is free.  If
you plan to attend, please register with Ralf Bruening as
noted below.

Bob Ross
Teraspeed Consulting Group

Ralf Bruening
Zuken EMC Technology Center

- ------------------------------------------------------------------

                 AGENDA, EUROPEAN IBIS SUMMIT MEETING
                       Wednesday, May 12, 2010

                         Van der Valk Hotel
                        Hildesheim, Germany
                (in the old city center of Hildesheim)

                Room: Wollenweber I, Check at Entrance

- ------------------------------------------------------------------

12:30  REFRESHMENTS & SIGN IN

12:45  WELCOME AND INTRODUCTIONS
        Bob ROSS, Teraspeed Consulting Group, USA

13:00  IBIS Activities
        Bob ROSS, Teraspeed Consulting Group, USA

13:15  IBIS Model Verification
        Hans KLOS, Sintecs BV, The Netherlands

13:45  More on C_comp: How to Represent C_comp in IBIS Buffer
        Model
        Lance WANG, IO Methodology, USA

14:15  IBIS [Driver Schedule] Modeling
        Eckhard LENSKI, Nokia Siemens Networks, Germany

14:45  Enhanced M(pi)log Models for Power Integrity Analysis: Modeling
        from Simulation and Measurement, IBIS Data Extraction,
        Crossvalidation
        Antonio GIRADI*, Igor STIEVANO**, Roberto IZZI*, T. LESSIO*,
        Flavio CANAVERO**, Ivan MAIO**, and Luca RIGAZIO**
        *Nymonyx and **Politecnico di Torino, Italy
        (Presented by Antonio GIRADI*, Igor STIEVANO**)

15:15  BREAK (15 Minutes)

15:30  Qualification of Tabulated Scattering Parameters
        Stefano GRIVET-TALOCIA, Politecnico di Torino and
        IdemWorks, Italy

16:00  IBIS-AMI and Modeling Recommendations
        Kumar KESHAVAN and Ken WILLIS, Sigriy, USA
        (Presented by Srdjan DJORDJEVIC, Sigrity, Germany)

16:30  Matlab Co-simulation for IBIS-AMI Models
        Danil KIRSANOV, Ansys, USA

16:55  Automating AMI Model-Generation using ESL
        (Electronic-System-Level) Tools
        Amolak BADESHA, Agilent Technologies, USA

17:25  CLOSING REMARKS
        Bob ROSS, Teraspeed Consulting Group

17:30  END OF MEETING

- ------------------------------------------------------------------

REGISTRATION INFORMATION

People involved in IBIS Model development, EDA tool development, and
digital circuit design are invited to participate to the Summit
meeting. If you plan to participate, please register with the
information below:

    Name:
    E-mail address:
    Company:
    Telephone:

Send to:

    Ralf BRUENING (ralf.bruening@zuken.com)

SPONSORS:
    Agilent Technologies, Mentor Graphics, Sintecs, Sigrity, and Zuken

SPI CONFERENCE INFORMATION AND TRAVEL DIRECTIONS

    See <http://www.spi.uni-hannover.de/> for travel directions,
    conference hotel and other information.

- ------------------------------------------------------------------

- -- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
121 North River Drive              13610 SW Harness Lane
Narragansett, RI 02882             Beaverton, OR 97008
401-284-1827                       503-430-1065
http://www.teraspeed.com           503-246-8048 Direct
bob@teraspeed.com

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC


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------------------------------

Date: Mon, 07 Jun 2010 12:21:19 -0700
From: Bob Ross <bob@teraspeed.com>
Subject: [IBIS-Users] Agenda, IBIS Summit at DAC - June 15, 2010

All:

We are holding our annual IBIS Summit meeting at DAC per the
Agenda below.  You are welcome to attend.

Note, that the meeting is at the Hilton Anaheim Hotel next to
the Anaheim Convention Center (and not the Marriott as in the
previous announcements).

Please register with Lance Wang (lwang@iometh.com) if you
plan to come.

Bob

- ------------------------------------------------------------------

                   AGENDA, IBIS SUMMIT MEETING
                          June 15, 2010

                       Hilton Anaheim Hotel
                        Anaheim, CA 92802

                        Room San Simeon A
                      (check signs at site)

- ------------------------------------------------------------------

8:00 AM     Refreshments & Sign In

8:30 AM     Introductions
             - Welcome to Summit
             - Introductions
             - Opens for Issues, Discussion Topics

8:45 AM     IBIS Open Forum Review
             Bob Ross, Teraspeed Consulting Group

9:05 AM     Correlation Update
             Anders Ekholm* and Mike LaBonte**, *Ericsson and
             **Cisco Systems

9:30 AM     Model Versus Measurement Correlation Report
             Amolak Badesha, Agilent Technologies

10:00 AM    BREAK

10:15 AM    Simple ODT Extraction
             Bob Ross, Teraspeed Consulting Group

10:45 AM    IBIS-AMI Update
             Arpad Muranyi, Mentor Graphics Corporation

11:15 AM    Election of Officers

11:45 AM    Opens/Discussions

12:00 PM    LUNCH - Pre-registration required

1:00 PM     Statistical Coverage in SI System Simulations and
             Implications for Models
             Michael Mirmak, Intel Corporation

2:00 PM     Predicting Low BER Probabilities
             Arpad Muranyi, Mentor Graphics Corporation

2:30 PM     BREAK

2:45 PM     Best Practices for Developing IBIS-AMI Models
             Walter Katz, Michael Steinberger, and Todd Westerhoff,
             Signal Integrity Software (SiSoft)

3:15 PM     Opens/Discussion and Ad Hoc Presentations

4:55 PM     Concluding Items
            - Next Meeting - July 2, 2010 (or July 9)
            - Next Summits in Asia

5:00 PM     End of IBIS Summit Meeting

- ------------------------------------------------------------------------

REGISTRATION

     People involved in IBIS Model development, EDA tool development,
     and digital circuit design are invited to participate to the
     Summit meeting. If you plan to participate, please register with
     the information below:

     Name:
     E-mail address:
     Company:
     Telephone:
     Please send registrations to lwang@iometh.com.

- ------------------------------------------------------------------------

- -- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
121 North River Drive              13610 SW Harness Lane
Narragansett, RI 02882             Beaverton, OR 97008
401-284-1827                       503-430-1065
http://www.teraspeed.com           503-246-8048 Direct
bob@teraspeed.com

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC


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------------------------------

End of ibis-users V1 #163
*************************

