From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #173 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Tuesday, May 31 2011 Volume 01 : Number 173 ---------------------------------------------------------------------- Date: Tue, 31 May 2011 19:48:22 -0400 From: Andrew Ingraham Subject: Re: [IBIS-Users] Requesting for some help / information regarding the use of IBIS in SI simulation. Yes. I am usually tempted to start with an evenly distributed RLC model ... unless I have reason to think that the distribution is otherwise. For example, wirebonds might have most of the inductance and resistance, whereas the leadframe may have more capacitance, which might influence one to imbalance those factors unequally between die end and pin end. But without hard data to back it up, that is just guessing. Andy - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 31 May 2011 16:12:57 -0700 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] Requesting for some help / information regarding the use of IBIS in SI simulation. Andy, Regarding "The order of the three elements (R,L,C)...", while what you say is true, I don't think IBIS intended them to be a single resistor, inductor and capacitor element in the package model. I remember talking about a "T" or "PI" structure to make this "RLC" model symmetric, but the specification doesn't mention any of these options. Thanks, Arpad ==================================================================== - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andrew Ingraham Sent: Tuesday, May 31, 2011 6:00 PM To: ibis-users Subject: Re: [IBIS-Users] Requesting for some help / information regarding the use of IBIS in SI simulation. In addition to the IBIS Cookbook, carefully read the documentation for your simulator. Some simulators (or some versions of some simulators) do not support package parasitics from the IBIS file, meaning that you have to add those elements yourself, external to the IBIS model in the simulator. Read your simulator's documentation to see if you need to do this. As Arpad notes, they are low frequency lumped parasitics and may get you only so far for doing high frequency SI. The order of the three elements (R,L,C) is undefined because it makes little difference at low frequencies. Andy - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 10 May 2011 16:20:32 -0400 From: "Lance Wang" Subject: [IBIS-Users] 2011 DAC IBIS SUMMIT third Call for Participation and Presentations This is a multipart message in MIME format. - ------=_NextPart_000_0215_01CC0F2E.3204CF30 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit This is the third announcement for the IBIS Summit Meeting scheduled along with the Design Automation Conference in San Diego, California on June 7, 2011. Lance Wang IO Methodology Inc. www.iometh.com - ----------------------------------------------------------------------- IBIS SUMMIT THIRD CALL FOR PARTICIPATION & PRESENTATIONS - ----------------------------------------------------------------------- Time/Date: Tuesday, June 7, 2011, 8:00 AM to 5:00 PM Location: Omni San Diego Hotel 675 L St. San Diego, California 92101 Content: Presentations and Discussions Purpose: Solicit and exchange IBIS model-related information and ideas Sponsors: IBIS Open Forum, Mentor Graphics Corp. If your company would be interested in sponsoring this event, please contact Lance Wang (lwang@iometh.com). Sponsorship is available for lunch and coffee breaks. DAC: June 5 - 9, 2011 San Diego Convention Center San Diego, California See http://www.dac.com for more information BACKGROUND The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. Several vendors active in the IBIS Open Forum attend DAC. This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. Any pending formal decisions (votes) will be announced at least two weeks prior to the meeting. The annual election of officers will be held at the summit. Nominations can be sent to Lance Wang (lwang@iometh.com) or made at the meeting. CALL FOR PARTICIPANTS People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Send to: Lance Wang (lwang@iometh.com) CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. Format of Presentation: LCD Projection with Microsoft Windows* laptop Time: 15-30 Minutes (not including questions) Electronic Archival: We request electronic versions so that the presentations may be archived and made available to non-attendees. Formats used in the past have been text, Microsoft PowerPoint*, Word*, Adobe Postscript*, and Acrobat*. Electronic presentations should be made available by June 1, 2011 for uploading and copying to the presentation laptop. If you plan to deliver a presentation, please supply the following: Title: Presenter: E-mail address: Company: Telephone: Estimated Duration: Send this to: Lance Wang (lwang@iometh.com) AGENDA The agenda includes presentations, discussions, breaks, and a luncheon (which will be provided). An official agenda will be published one week before the event. LIST OF NEARBY HOTELS See http://www.dac.com/attendee+hotel+reservations.aspx for travel directions, hotels and other information. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0215_01CC0F2E.3204CF30 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

This is the third announcement for the IBIS = Summit Meeting scheduled along with the Design Automation Conference in San= Diego, California on June 7, 2011.

 

&n= bsp;

Lance Wang

IO Methodology Inc.

www.iometh.com

 

 

<= span style=3D'font-family:"Courier New"'>----------------------------------= - -------------------------------------

    =             &nb= sp;  IBIS SUMMIT

      = ;            TH= IRD CALL FOR

        &= nbsp;   PARTICIPATION & PRESENTATIONS =

-----= - ------------------------------------------------------------------

        Time/Date:  =    Tuesday, June 7, 2011, 8:00 AM to 5:00 PM

 &= nbsp;      Location:    &= nbsp; Omni San Diego Hotel

      =             &nb= sp;    675 L St.

     &= nbsp;           &nbs= p;     San Diego, California 92101

 &n= bsp;      Content:     &n= bsp; Presentations and Discussions

    &nb= sp;   Purpose:       Solicit a= nd exchange IBIS model-related information and ideas

<= p class=3DMsoPlainText> &nbs= p;      Sponsors:      IB= IS Open Forum, Mentor Graphics Corp.

  <= /p>

 =        If your company would be interest= ed in sponsoring this event, please

contact Lance Wang (lwang@iometh.com).  Sponsorship is av= ailable for lunch

and coffee breaks.

  =

        DAC: &nbs= p;  June 5 - 9, 2011

      =           San Diego Conve= ntion Center

        &= nbsp;       San Diego, California <= /o:p>

           &n= bsp;    See http://www.d= ac.com for more information

    <= /o:p>

BACKGROUND

The Design Automation Conference (DAC) is th= e premier Electronic Design

Automation (EDA) and silicon soluti= on event. Several vendors active in the

IBIS Open Forum attend = DAC.

This meeting will be conducted as a formal IBIS Summit Me= eting.

Presentations are expected to be available and archived = in an electronic

format, and minutes of the meeting will be i= ssued.  Any pending formal

decisions (votes) will be annou= nced at least two weeks prior to the meeting.

 =

be sent to Lance Wang (l= wang@iometh.com) or made at the meeting.

   = ;

CALL FOR PARTICIPANTS

People involved in IBIS Mo= del development, EDA tool development, and digital

circuit desi= gn are invited to participate to the Summit meeting. If you plan=

=    Name:

   E-mail address:

   Company:

   Telephon= e:

  

<= span style=3D'font-family:"Courier New"'>Send to:

  =    Lance Wang (lwang@iom= eth.com) 

  

CALL FOR PRESENTA= TIONS

We are seeking presentations from individuals who have I= BIS experiences or

issues.

   Forma= t of Presentation:      LCD Projection with Micros= oft Windows* laptop

   Time:    &= nbsp;           &nbs= p;       15-30 Minutes (not including questio= ns)

   Electronic Archival:    &n= bsp;    We request electronic versions so that the

used in the past have been text, Microsoft PowerPoint*, Word= *, Adobe

Postscript*, and Acrobat*.  Electronic presentati= ons should be made

available by June 1, 2011 for uploading and = copying to the presentation

laptop.

  

If you plan to deliver a presentation, please supply the followi= ng:

   Title:

   Presente= r:

   E-mail address:

  =  Company:

   Telephone: =

 = ;  Estimated Duration:

    =

Send this to:

     Lance Wang= (lwang@iometh.com) 

  

AGENDA

The agenda includes pres= entations, discussions, breaks, and a luncheon

(which will be p= rovided). An official agenda will be published one week

before = the event.

 

LIST OF NEARBY HOTELS

http= ://www.dac.com/attendee+hotel+reservations.aspx for travel

= directions, hotels and other information. 

 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_0215_01CC0F2E.3204CF30-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 10 May 2011 15:56:29 -0400 From: "Timothy Coyle" Subject: RE: [IBIS-Users] DDR4 simulations using IBIS models This is a multi-part message in MIME format. - ------=_NextPart_000_004B_01CC0F2A.D46CB980 Content-Type: multipart/alternative; boundary="----=_NextPart_001_004C_01CC0F2A.D46CB980" - ------=_NextPart_001_004C_01CC0F2A.D46CB980 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Ray, Having dealt with this issue myself before (not with DDR4 but other interfa= ces) here are my thoughts: =C2=B7 Give both .pkg RLC and S-Parameter models to users. Sometime= s it's easier to run larger solution space simulations with less accurate R= LC package models and then use more accurate S-Parameter models for specifi= c corner cases. I do this a lot with DDR connectors in early simulations. =C2=B7 Strongly suggest leaving in .pkg RLC as default if just for = EDA tool checking/processing/library management etc. =C2=B7 I'm not a big fan of the w-element external package model fo= rmats as they are difficult to import into other tools depending on how its= done. =C2=B7 Pre-layout will be easy to add S-Parameter models but post-l= ayout will be more difficult for users.=20 =C2=B7 You may even want to consider using some type of broadband s= pice equivalent package model rather than S-Parameter to see if they simula= te faster. These often have generic connector SPICE style syntax and can be= easier to use in post-layout situations. =C2=B7 You've probably already done the work but you want to qualif= y the impact of .pkg RLC versus S-Parameter in DDRx system environment. You= may find the impact is not as significant as you think especially for spec= ific usage cases. =C2=B7 The .pkg format in IBIS allows for sparse matrices/etc so th= ere may be some field solver/conversion tricks to put more accurate data in= the matrix. I think some past Micron presentations at IBIS Summit meetings= have shown some work on DDR3 1667 with IBIS .pkg exploration. =20 Hope this helps. =20 Best, =20 Tim =20 =20 From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf = Of Gregory R Edlund Sent: Tuesday, May 10, 2011 1:38 PM To: Ray Anderson Cc: ibis-users; owner-ibis-users@eda.org; Ray Anderson Subject: Re: [IBIS-Users] DDR4 simulations using IBIS models =20 Ray, I haven't simulated DDR4 myself, but I have similar experience. I would use= a w-element with a lumped C to represent the package via, pad, and solder = ball. Try 25 um line width, 60 um edge-to-edge spacing, Er =3D 3.3, and tan= d =3D 0.02. That should get you in the ball park. I've been using s-parameter models for circuit board vias for some years no= w.=20 Greg Edlund Senior Engineer Signal Integrity and System Timing IBM Systems & Technology Group 3605 Hwy. 52 N Bldg 050-3 Rochester, MN 55901 Inactive hide details for Ray Anderson ---05/10/2011 12:18:57 PM--- For rel= atively low bandwidth signals (say < 1GHz) IBIS .pkRay Anderson ---05/10/20= 11 12:18:57 PM--- For relatively low bandwidth signals (say < 1GHz) IBIS .p= kg style RLC From: Ray Anderson To: ibis-users Cc: Ray Anderson Date: 05/10/2011 12:18 PM Subject: [IBIS-Users] DDR4 simulations using IBIS models Sent by: owner-ibis-users@eda.org _____=20=20 For relatively low bandwidth signals (say < 1GHz) IBIS .pkg style RLC packa= ge models are an adequate solution. As we move into the realm of DDR4 where= the bitrate is say 4 GB/s and the risetime is on the order of 70psec I am = wondering what sort of package models IBIS users tend to use these days. A 70psec ristime equates to a knee frequency of about 5.7 GHz. For good sig= nal fidelity the package model should be accurate up to at least 3 times th= at frequency (and preferably 5 times). Looking at the options available it is looking like s-parameter models may = be the only variety that is up to the task. The problem with those from a u= ser=E2=80=99s perspective is that the simulation speed is quite slow compar= ed to RLC based models. From the model makers perspective, it is impractica= l to do a =E2=80=9Cfull package=E2=80=9D s-parameter extraction to provide = separate models for each net in large packages. It also appears that in IBI= S 5.0 there is no good method to automatically include the proper s-paramet= er model (as one can do in current tools by just selecting the proper pin n= ame or netname to pull in the correct RLC parasitic). If IBIS BIRD 125 is adopted allowing IBIS-ISS available for package modelin= g it seems that will provide a mechanism for the inclusion of s-parameter p= ackage models. Until the enhancements described in BIRD125 become reality what is current = solution most users are adopting? Ray Anderson Xilinx Inc. This email and any attachments are intended for the sole use of the named r= ecipient(s) and contain(s) confidential information that may be proprietary= , privileged or copyrighted under applicable law. If you are not the intend= ed recipient, do not read, copy, or forward this email message or any attac= hments. Delete this email message and any attachments immediately.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner, and is=20 believed to be clean.=20 - --=20 This message has been scanned for viruses and=20 dangerous content by MailScanner, and is=20 believed to be clean.=20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_001_004C_01CC0F2A.D46CB980 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Hi Ray,

Having dealt with this issu= e myself before (not with DDR4 but other interfaces) here are my thoughts:<= o:p>

=C2= =B7    &nb= sp;    Give both .pkg = RLC and S-Parameter models to users. Sometimes it's easier to run larger so= lution space simulations with less accurate RLC package models and then use= more accurate S-Parameter models for specific corner cases. I do this a lo= t with DDR connectors in early simulations.

=C2=B7         <= /span>Strongly suggest leaving in .pkg RLC as defau= lt if just for EDA tool checking/processing/library management etc.

=C2=B7      = ;   I'm not a big fan of th= e w-element external package model formats as they are difficult to import = into other tools depending on how its done.

=C2=B7         <= /span>Pre-layout will be easy to add S-Parameter mo= dels but post-layout will be more difficult for users.

=C2=B7        = ; You may even want to consider using= some type of broadband spice equivalent package model rather than S-Parame= ter to see if they simulate faster. These often have generic connector SPIC= E style syntax and can be easier to use in post-layout situations.

=C2=B7      =    You've probably already = done the work but you want to qualify the impact of .pkg RLC versus S-Param= eter in DDRx system environment. You may find the impact is not as signific= ant as you think especially for specific usage cases.

=

=C2=B7         = The .pkg format in IBIS allows for sp= arse matrices/etc so there may be some field solver/conversion tricks to pu= t more accurate data in the matrix. I think some past Micron presentations = at IBIS Summit meetings have shown some work on DDR3 1667 with IBIS .pkg ex= ploration.

 

Hope this helps.=

 

Best,

&n= bsp;

Tim

<= p class=3DMsoNormal> 

 

From: owner-ibis-users@eda.org [mailto:owner-ibis= - -users@eda.org] On Behalf Of Gregory R Edlund
Sent: Tuesda= y, May 10, 2011 1:38 PM
To: Ray Anderson
Cc: ibis-users= ; owner-ibis-users@eda.org; Ray Anderson
Subject: Re: [IBIS-Users= ] DDR4 simulations using IBIS models

 

Ray,

I haven't simulated DDR4 myself, b= ut I have similar experience. I would use a w-element with a lumped C to re= present the package via, pad, and solder ball. Try 25 um line width, 60 um = edge-to-edge spacing, Er =3D 3.3, and tand =3D 0.02. That should get you in= the ball park.

I've been using s-parameter models for circuit board v= ias for some years now.

Greg Edlund
Senior Engineer
Signal Inte= grity and System Timing
IBM Systems & Technology Group
3605 Hwy. = 52 N Bldg 050-3
Rochester, MN 55901



3D"InactiveRay = Anderson ---05/10/2011 12:18:57 PM--- For relatively low bandwidth signals = (say < 1GHz) IBIS .pkg style RLC

From: Ray Anderson <r= ay.anderson@xilinx.com>
To: ibis-users <ibis-users@eda.org= >
Cc: Ray Anderson <raya@xilinx.com>
Date= : 0= 5/10/2011 12:18 PM
Subject: [IBIS-Users] DDR4 simulations using = IBIS models
Sent by: owner-ibis-users@eda.org<= /p>





F= or relatively low bandwidth signals (say < 1GHz) IBIS .pkg style RLC pac= kage models are an adequate solution. As we move into the realm of DDR4 whe= re the bitrate is say 4 GB/s and the risetime is on the order of 70psec I a= m wondering what sort of package models IBIS users tend to use these days.<= /span>
A 70psec ristime equates to a knee frequency of about 5.7 = GHz. For good signal fidelity the package model should be accurate up to at= least 3 times that frequency (and preferably 5 times).

Looking at the options available it is looking like s-parameter models ma= y be the only variety that is up to the task. The problem with those from a= user=E2=80=99s perspective is that the simulation speed is quite slow comp= ared to RLC based models. From the model makers perspective, it is impracti= cal to do a =E2=80=9Cfull package=E2=80=9D s-parameter extraction to provid= e separate models for each net in large packages. It also appears that in I= BIS 5.0 there is no good method to automatically include the proper s-param= eter model (as one can do in current tools by just selecting the proper pin= name or netname to pull in the correct RLC parasitic).

If IBIS BIRD 125 is adopted allowing IBIS-ISS available for package model= ing it seems that will provide a mechanism for the inclusion of s-parameter= package models.

Until the enhancements described in B= IRD125 become reality what is current solution most users are adopting?

Ray Anderson
Xilinx Inc.


This email and any attachments are intended for the sole use o= f the named recipient(s) and contain(s) confidential information that may b= e proprietary, privileged or copyrighted under applicable law. If you are n= ot the intended recipient, do not read, copy, or forward this email message= or any attachments. Delete this email message and any attachments immediat= ely.
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This message has been scanned for viruses and
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believed to be clean.


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This messag= e has been scanned for viruses and
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believed to be= clean.


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True, only typ values are required. 

What I intended to say was that corner data, if available, goes in the same [Model] and file.  And that the other two columns must have entries, even if these are just NA.

[Note to modelers]
* To create a separate min or max IBIS model requires a different model name.  There are known "bad" options: a) Keep typ data, and replace one NA column with data values.  b) Reduce "typ" column to two entries, with NA for intermediate points, and replace one NA column with data values.  c) Create 3 files with only "typ" data (each file a different physical corner).
* This BREAKS automated tool flow, since [Pin] can assign only one model to an I/O.
* Also, any of these methods can quickly become a can of worms (= completely unmanageable) for model users.  And a rat hole (= much time wasted)  for whoever supports (created) that model.

Cheers,
Lynne



On 5/10/2011 1:12 PM, Muranyi, Arpad wrote:

Lynne,

 

Strictly speaking only typical is REQUIRED in an

IBIS file…

 

Arpad

==================================================

 

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Lynne D. Green
Sent: Tuesday, May 10, 2011 2:13 PM
To: Muniswara Reddy Vorugu
Cc: 'ibis-users'
Subject: Re: [IBIS-Users] IBIS Model Usage:

 

Hello, Muniswara,

IBIS _requires_ all 3 corners in the SAME file, and IBIS-related tools expect this.  As Arpad noted, submodels can be used to model additional corners.  Separate models or files for the 3 corners might be useful for other tools, but not for IBIS.

The IBIS Model Review Committee exists to help model makers.  Files should be checked with ibischk5 prior to submission.
http://www.eda.org/ibis/home/support/support.htm

Regards,
Lynne Green

Chair, IBIS Model Review Committee


On 5/9/2011 10:20 PM, Muniswara Reddy Vorugu wrote:

Hi,

For better  delivery of IBIS model, we want to know better ways to get usablility and manage our deliverables.

To make this balance, I want to understand the following:

 

1:  What are the advantages of min/typ/max corners merged in single file, over 3 files with one corner per file?

What is the difficulty for running Min/Typ/Max corners analysis.

Are there any Fundamental analysis limitations?

 

 

Regards,

Muniswara

 

 



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This message has been scanned for viruses and
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believed to be clean. - --------------020609090204000707000100-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis | subscribe ibis-users | unsubscribe ibis | unsubscribe ibis-users | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 25 May 2011 09:18:48 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] VT Data Length Mismatch and Over Clocking This is a multipart message in MIME format. - ------=_NextPart_000_030A_01CC1ABC.C31D8F90 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit I guess I'm surprised this causes an issue. I don't recall seeing anything in the IBIS spec requiring equal length VT tables. By definition all time after a VT table has ended should equal the last point in the VT table until a new transition occurs. I also see a lot of parts that have different output amplitude specifications at low frequencies vs. high frequency. This implies the part was never designed to have finished transitions at the fastest toggle rate of the buffer. So overclocking is a reality in modern parts. There are many parts that have much faster falling transition than rising. A good example of this is an open sink. Others include RS232 and the like. And I've seen many more normal totem pole outputs exhibit the same characteristics. And I've seen the reverse where the rise is much faster than the fall by a factor or 3 to 5. Why should the rising table(s) have the same time duration as the falling? Tom Dagostino Teraspeed Labs 9999 SW Wilshire St. Suite 102 Portland, OR 97225 USA 971-279-5325 Office 971-279-5326 FAX 503-430-1065 Cell tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Prabhat Ranjan Sent: Wednesday, May 25, 2011 8:22 AM To: Timothy Coyle Cc: ibis-users@eda.org Subject: Re: [IBIS-Users] VT Data Length Mismatch and Over Clocking Hello Timothy, I have also came across the same problem with one simulator where different time lengths of V-T waveform gave me completely wrong results and just making all tables equal by adding same last point has solved the problem. Simulator vendor has accepted it as bug in tool. Various simulators take care this issue internally by extending the last points to make them equal.Thats why, somewhere it is recommended to have same two last points in VT curve. I have checked the same model with 2-3 another simulators and all of them give correct results with different time length. Regards Prabhat On Wed, May 25, 2011 at 8:14 PM, Timothy Coyle wrote: Hi, I'm starting to run across quite a few IBIS models that have different time lengths in the V-T waveforms even for corresponding loads. For example, a Rising Waveform with 50 Ohms to Ground may have a total time of 5ns but the equivalent Falling Waveform with 50 Ohms to Ground may have a total time of 10ns. So between the four different V-T waveforms they can all have a different total time length. All of the waveforms transition to a "steady state" but I'm wondering if this will cause potential problems in IBIS simulators? I know a lot of IBIS simulators say they can handle an over-clocked IBIS model but will this cause even more issues? I've also actually started to see a few models that say they must be over clocked to run properly (apparently model developer had issues getting VT waveform to reach steady state within bit time) I would think that the VT waveform total lengths should be matched based upon that they are used to define rise/fall transitions but clearly it all depends on how EDA IBIS simulator processes this data. It's difficult to do this type of correlation in multiple tools and without access to the original SPICE model but wanted to see if anyone else is running into this issue or can see potential issues with this type of model? Best, Timothy Coyle President Signal Consulting Group LLC 405 Western Ave #430 South Portland, ME 04106 Tel: 617.297.2566 Email: tim.coyle@siconsultant.com Web: http://www.siconsultant.com SharkSim - Signal Integrity IBIS Modeling Software - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_030A_01CC1ABC.C31D8F90 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

I guess I= ’m surprised this causes an issue.  I don’t recall seeing = anything in the IBIS spec requiring equal length VT tables.  By defini= tion all time after a VT table has ended should equal the last point in the= VT table until a new transition occurs.

 

I al= so see a lot of parts that have different output amplitude specifications a= t low frequencies vs. high frequency.  This implies the part was never= designed to have finished transitions at the fastest toggle rate of the bu= ffer.  So overclocking is a reality in modern parts.=

 

There are many parts that have much faster falling transition = than rising.  A good example of this is an open sink.  Others inc= lude RS232 and the like.  And I’ve seen many more normal totem p= ole outputs exhibit the same characteristics.  And I’ve seen the= reverse where the rise is much faster than the fall by a factor or 3 to 5.=   Why should the rising table(s) have the same time duration as the fa= lling?

 

Tom Dagostino

 

<= span style=3D'font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F= 497D'>Teraspeed Labs

9999= SW Wilshire St.

Suite 102=

Portland, OR 97225

USA

 

971-279-5325  Office

971-279-5326   FAX

503-430-1065  Cell

 

tom@teraspeed.com

www.teraspeed.com=

 

Teraspeed Consulting Group LLC

121 North River Drive

Narragansett, RI 02882

401-284-1827

 

From: o= wner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of <= /b>Prabhat Ranjan
Sent: Wednesday, May 25, 2011 8:22 AM
To:= Timothy Coyle
Cc: ibis-users@eda.org
Subject: Re: = [IBIS-Users] VT Data Length Mismatch and Over Clocking

 

Hello Timothy,

I have also came across the same = problem with one simulator where different time lengths of V-T waveform gav= e me completely wrong results and just making all tables equal by adding sa= me last point has solved the problem.  Simulator vendor has accepted i= t as bug in tool.

Various simulators take care this issue internally= by extending the last points to make them equal.Thats why, somewhere it is= recommended to have same two last points in  VT curve.  I have c= hecked the same model with 2-3 another simulators and all of them give corr= ect results with different time length.


Regards
Prabhat


On Wed, May 25, 2011 at = 8:14 PM, Timothy Coyle <ti= m.coyle@siconsultant.com> wrote:

Hi,<= o:p>

I'm starting to run across quite a few IBIS models tha= t have different time lengths in the V-T waveforms even for corresponding l= oads. For example, a Rising Waveform with 50 Ohms to Ground may have a tota= l time of 5ns but the equivalent Falling Waveform with 50 Ohms to Ground ma= y have a total time of 10ns. So between the four different V-T waveforms th= ey can all have a different total time length. All of the waveforms transit= ion to a "steady state" but I'm wondering if this will cause pote= ntial problems in IBIS simulators?

 <= /p>

I know a lot of IBIS simulators say they can handle an over-clock= ed IBIS model but will this cause even more issues? I've also actually star= ted to see a few models that say they must be over clocked to run properly = (apparently model developer had issues getting VT waveform to reach steady = state within bit time)

 

I= would think that the VT waveform total lengths should be matched based upo= n that they are used to define rise/fall transitions but clearly it all dep= ends on how EDA IBIS simulator processes this data. It's difficult to do th= is type of correlation in multiple tools and without access to the original= SPICE model but wanted to see if anyone else is running into this issue or= can see potential issues with this type of model?

&= nbsp;

Best,

 

Timothy Coyle

<= p class=3DMsoNormal style=3D'mso-margin-top-alt:auto;mso-margin-bottom-alt:= auto'>President

<= span style=3D'color:#1F497D'>Signal Consulting Group LLC<= /p>

405 Western Ave #430

South Portland, ME  04106=

Tel: 617.297.256= 6

Email: <= a href=3D"mailto:tim.coyle@siconsultant.com" target=3D"_blank">tim.coyle@si= consultant.com

Web: = http://ww= w.siconsultant.com

SharkSim - Signal= Integrity IBIS Modeling Software

 


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