------------------------------------------------------------------

If you plan to participate, please register with the information below= :

Name:

E-mail address:

Company:

Telephone:

Send to: Lance Wang (lwang@iometh.com)

Sponsors: Agilent Technologies, DesignCon, IBIS Open Forum=

DesignCon: January 28 - 31, 2013

San= ta Clara Convention Center

San= ta Clara, California

See= http://www.designcon.com/ for mo= re information.

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This message has been scanned for viruses and
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believed to be clean. - --_000_942B8AE05D9831409A64517FFA4C460140792A0BFMSMSX104amrcor_-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Sun, 10 Mar 2013 17:31:45 +0500 From: PristineSignals Subject: [IBIS-Users] Question - --Apple-Mail-533E7991-2F02-4D5E-BC8E-9A5F2B1D557C Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Folks, I have quick question, has anyone here attempted to=20 write. PHP wrapper for the IBIS parser? Also for=20 GNUPlot? Please advise Thanks Abbey (Abdulrahman Rafiq) Sent from my iPhone On Mar 8, 2013, at 9:01 PM, Rinsha Reghunath wrote: > Hi, >=20=20 > I am trying to validate an IBIS 5.1 model generated for DDR3 with ISSO_PU= /PD and Composite Current data. The V-T and I-T data is not clipped in orde= r to capture pre-driver current better and the I-T table has 1000 points. W= hen I tried to do a transient analysis for validation, SPICE and IBIS V-T w= aveforms are matching at the DDR3 frequency, but IBIS I-T curves are gettin= g truncated at the rise and fall transitions and doesnot correlate well wit= h SPICE. The pre-driver current is being lost. When the frequency is reduce= d, there is good SPICE =E2=80=93 IBIS matching for I-T. >=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 > Is this issue known or is it an issue in the IBIS model? >=20=20 > I have read in http://www.eda.org/ibis/summits/may11/m051111.pdf that =E2= =80=9Cadding [Composite Current] data to the model reduced the valid switch= ing rate of the model.=E2=80=9D Is the above issue related to this? >=20=20 > Thanks. >=20=20 > Regards, > Rinsha >=20=20 >=20 > --=20 > This message has been scanned for viruses and=20 > dangerous content by MailScanner, and is=20 > believed to be clean. - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --Apple-Mail-533E7991-2F02-4D5E-BC8E-9A5F2B1D557C Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

Folks,

I = have quick question, has anyone here attempted to

write. PH= P wrapper for the IBIS parser? Also for

GNUPlot?

Please advise

Thanks

Abbey

(Abdulrahman Rafiq)

Sent from my iPhone

On Mar 8, 2013, at 9:01 PM, Rinsha Reghunath <Rinsha.Raghunath@synopsys.com> w= rote:

Hi,

I am trying to validate an IBIS 5.1 model generated = for DDR3 with ISSO_PU/PD and Composite Current data. The V-T and I-T data i= s not clipped in order to capture pre-driver current better and the I-T tab= le has 1000 points. When I tried to do a transient analysis for validation, SPICE and IBIS V-T waveforms are m= atching at the DDR3 frequency, but IBIS I-T curves are getting truncated at= the rise and fall transitions and doesnot correlate well with SPICE. The p= re-driver current is being lost. When the frequency is reduced, there is good SPICE =E2=80=93 IBIS matching= for I-T.

&nbs= p; &= nbsp; &nbs= p; &= nbsp; &nbs= p; &= nbsp; &nbs= p; &= nbsp; &nbs= p; &= nbsp; &nbs= p; &= nbsp; &nbs= p; &= nbsp;

Is this issue known or is it an issue in the IBIS mo= del?

I have read in http://www.eda.org/ibis/summits/may11/m051111.pdf that =E2=80=9Cadding = [Composite Current] data to the model reduced the valid switching rate of t= he model.=E2=80=9D Is the above issue related to this?

Thanks.

Regards,

Rinsha

--=20
This message has been scanned for viruses and
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This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --Apple-Mail-533E7991-2F02-4D5E-BC8E-9A5F2B1D557C-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 18 Jan 2013 17:42:56 +0000 From: "Mirmak, Michael" Subject: [IBIS-Users] IBIS Summit at DesignCon 2013 - Final Call for Participation and Presentations - --_000_942B8AE05D9831409A64517FFA4C46014078E5E5FMSMSX104amrcor_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable The IBIS Open Forum will hold an IBIS Summit meeting at DesignCon 2013. The= Summit will be held at the Santa Clara Convention Center in Santa Clara, C= alifornia on Thursday, January 31, 2013. IBIS Summits are designed to enable face-to-face interactions between model= users, model makers and tool developers in the IBIS community. Those inte= rested in presenting at or in attending the event may register using the in= formation below. The IBIS Open Forum is sponsoring the event, but we welcome additional spon= sors to cover some of the meeting expenses, including the FREE lunch and re= freshments. We look forward to seeing you in Santa Clara! Best Regards, Michael Mirmak Intel Corp. Chair, IBIS Open Forum - ----------------------------------------------------------------------- I B I S S U M M I T M E E T I N G FINAL CALL FOR PARTICIPATION & PRESENTATIONS - ----------------------------------------------------------------------- Time/Date: Thursday, January 31, 2013 8:00 AM to 5:00 PM Location: Santa Clara Convention Center 5101 Great America Parkway, Santa Clara, California, USA Room: Mission City M1 Room (look for signs) Santa Clara Convention Center Content: Presentations and Discussions Cost: FREE Sponsors: IBIS Open Forum, DesignCon We are seeking more co-sponsors. The benefits to sponsors inclu= de recognition at the meeting and acknowledgement in the Calls for Papers and meeting minutes. Your financial support strengthens the organization by allowing IBIS to focus resources on industry activities rather than raising money. You will receive generous thanks and public acknowledgement for your support. Please contact Lance Wang > for co-sponsorship information. DesignCon 2013 Conference: January 28 - 31, 2013 Santa Clara Convention Center Santa Clara, CA http://www.designcon.com/ Conference Schedule: http://www.designcon.com/santaclara/conference BACKGROUND DesignCon is the premier annual Silicon Valley event for the electronic des= ign automation (EDA) and semiconductor industry. Topics of current interest= to the IBIS Open Forum are addressed at DesignCon. This meeting will be conducted as a formal IBIS meeting. Presentations are expected to be available in an electronic format, and min= utes of the meeting will be issued. Any pending formal decisions (votes) wi= ll be announced at least two weeks prior to the meeting. CALL FOR PARTICIPANTS People involved in IBIS or related model development, EDA tool development,= and digital circuit design are invited to participate in the Summit meetin= g. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Send your registration information to Lance Wang >. Registration deadline is Thursday, January 24, 2013 to receive the free lun= ch. CALL FOR PRESENTATIONS We are seeking presentations from individuals who have experiences of inter= est to the IBIS modeling community. These can include, but are not limited = to: Demonstrations of modeling techniques Explanations of behavioral algorithms Descriptions of difficulties encountered Model correlation Modeling building experiences Comparisons to other modeling methods New technologies for modeling buffers and components New technologies for modeling packaging and interconnects Algorithmic modeling topics Presentations may be addressed to any and all levels of IBIS experience, fr= om beginner to expert. Presentation Format: Microsoft PowerPoint* or Adobe Acrobat* electronic formats are favored and will be pre-loaded on a Microsoft Windows*-based meeting laptop prior to the meeting. Materials will be projected but handouts or other physical media are welcome. Time: Usually 15-45 minutes (allow time for questions) Electronic Archival: Presentations will be archived under the IBIS Summit website. Final submission deadline is Monday, January 21, 2013 If you plan a presentation, please supply the following information as soon= as possible: Presentation Title: Presenter Name: E-mail address: Company: Telephone: Estimated Time: Send to Michael Mirmak > All submissions will be reviewed by the IBIS Board and are subject to appro= val before Presentation at the Summit. Note, vendor-specific, confidential or product promotion material is forbid= den at IBIS summits. Presentations MUST be submitted by the deadline for re= view. The IBIS Open Forum reserves the right to reject submitted presentati= ons or stop a scheduled presentation containing content that has not been r= eviewed. AGENDA The agenda includes presentations, discussions, breaks, and a FREE lunch. A= formal list of speakers and topics will be released one week prior to the = event. HOTEL AND TRAVEL INFORMATION The Hotel and Travel Link below provides a conference hotel discount, as we= ll as transportation suggestions: http://www.designcon.com/santaclara/registration/travel-and-venue.php - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --_000_942B8AE05D9831409A64517FFA4C46014078E5E5FMSMSX104amrcor_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

The IBIS Open Forum will hold an IBIS S= ummit meeting at DesignCon 2013. The Summit will be held at the Santa Clara= Convention Center in Santa Clara, California on Thursday, January 31, 2013.

IBIS Summits are designed to enable fac= e-to-face interactions between model users, model makers and tool developer= s in the IBIS community. Those interested in presenting at or in attending the event may register using the information below.

The IBIS Open Forum is sponsoring the e= vent, but we welcome additional sponsors to cover some of the meeting expen= ses, including the FREE lunch and refreshments.

We look forward to seeing you in Santa = Clara!

Best Regards,

Michael Mirmak

Intel Corp.

Chair, IBIS Open Forum

---------------------------------------= - --------------------------------

&nb= sp; = I B I S S U M M I T M E E T I N G

&nb= sp; &nbs= p; FINAL = CALL FOR

&nb= sp; PARTICIPATION &am= p; PRESENTATIONS

---------------------------------------= - --------------------------------

Time/Date: = ; Thursday, January 31, 2013 8:00 AM to 5:00 PM

Location: = Santa Clara Convention Center

5101 Great America Parkway,

Santa Clara, California, USA

&nb= sp;

Room: &nbs= p; Missio= n City M1 Room (look for signs)

Santa Clara Convention Center

Content: &= nbsp; Presentations and Discussio= ns

Cost: &nbs= p; &= nbsp; FREE

Sponsors: = IBIS Open Forum, DesignCon

&nb= sp; We are seeking more co-sponsors. The benefits t= o sponsors include

&nb= sp; recognition at the meeting and acknowledgement = in the Calls

&nb= sp; for Papers and meeting minutes.

&nb= sp; Your financial support strengthens the organiza= tion by

&nb= sp; allowing IBIS to focus resources on industry ac= tivities

&nb= sp; rather than raising money. You will receive gen= erous

&nb= sp; thanks and public acknowledgement for your supp= ort.

&nb= sp; Please contact Lance Wang <lwang@iometh.com> for co-sponsorship

&nb= sp; information.

&nb= sp; DesignCon 2013 Conference:

&nb= sp; January 28 - 31, 2013

&nb= sp; Santa Clara Convention Center

&nb= sp; Santa Clara, CA

&nb= sp; http://www.designcon.com/ =

&nb= sp; Conference Schedule:

&nb= sp; http://www.desig= ncon.com/santaclara/conference

BACKGROUND

DesignCon is the premier annual Silicon= Valley event for the electronic design automation (EDA) and semiconductor = industry. Topics of current interest to the IBIS Open Forum are addressed at DesignCon. <= /o:p>

This meeting will be conducted as a for= mal IBIS meeting.

Presentations are expected to be availa= ble in an electronic format, and minutes of the meeting will be issued. Any= pending formal decisions (votes) will be announced at least two weeks prior to the meeting.

CALL FOR PARTICIPANTS

People involved in IBIS or related mode= l development, EDA tool development, and digital circuit design are invited= to participate in the Summit meeting. If you plan to participate, please register with the information below:

Name:

E-mail address:

Company:

Telephone:

Send your registration information to L= ance Wang <lwang@iometh.com>.

Registration deadline is Thursday, January 24, 2013 to receive the free lunch.

CALL FOR PRESENTATIONS

We are seeking presentations from indiv= iduals who have experiences of interest to the IBIS modeling community. The= se can include, but are not limited to:

Demonstrations of modeling= techniques

Explanations of behavioral= algorithms

Descriptions of difficulti= es encountered

Model correlation

Modeling building experien= ces

Comparisons to other model= ing methods

New technologies for model= ing buffers and components

New technologies for model= ing packaging and interconnects

Algorithmic modeling topics

Presentations may be addressed to any a= nd all levels of IBIS experience, from beginner to expert.

Presentation Format:

Microsoft PowerPoint* or A= dobe Acrobat* electronic formats are favored

and will be pre-loaded on = a Microsoft Windows*-based meeting laptop

prior to the meeting. Mate= rials will be projected but handouts or

other physical media are w= elcome.

Time: Usually 15-45 minutes (allow time= for questions)

Electronic Archival:

Presentations will be arch= ived under the IBIS Summit website.

Final submission deadline = is Monday, January 21, 2013

If you plan a presentation, please supp= ly the following information as soon as possible:

Presentation Title:

Presenter Name:

E-mail address:

Company:

Telephone:

Estimated Time:

Send to Michael Mirmak <michael.mirmak@intel.com>

All submissions will be reviewed by the= IBIS Board and are subject to approval before Presentation at the Summit.&= nbsp;

Note, vendor-specific, confidential or = product promotion material is forbidden at IBIS summits. Presentations MUST= be submitted by the deadline for review. The IBIS Open Forum reserves the right to reject submitted presentations or stop a sched= uled presentation containing content that has not been reviewed.

AGENDA

The agenda includes presentations, disc= ussions, breaks, and a FREE lunch. A formal list of speakers and topics wil= l be released one week prior to the event.

HOTEL AND TRAVEL INFORMATION

The Hotel and Travel Link below provide= s a conference hotel discount, as well as transportation suggestions:

http://www.designcon.com/santaclara/registration/travel-and-venue.ph= p

--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --_000_942B8AE05D9831409A64517FFA4C46014078E5E5FMSMSX104amrcor_-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 11 Mar 2013 16:53:57 +0000 From: "Muranyi, Arpad" Subject: [IBIS-Users] RE: [IBIS] Validation of composite current - --_000_EB55FD6CF8C21444BE032D68DDA5FB998B9FD98DNAMBX02mgcmento_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Mike, Regarding your answer #1, that was not the only intent. In addition to that, the information in [Composite Current] can also be used to calculate the supply currents more accurately so that the noise in the non-ideal supply would be simulated more accurately in SI/PI simulations. In these situations the pre-driver current can also be important if it comes from the same supply terminals as the output stage. Thanks, Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Mike LaBo= nte Sent: Sunday, March 10, 2013 3:09 PM To: Rinsha Reghunath Cc: ibis@eda.org; ibis-users@eda.org Subject: Re: [IBIS] Validation of composite current When you write "IBIS I-T curves are getting truncated at the rise and fall = transitions" do you mean EDA tools are doing the truncating? There are seve= ral behaviors among the tools, and the tendency is to reduce the length of = the V-T curves to the minimum needed to represent an edge, to avoid overclo= cking issues. But the fact that current changes often appear before the vol= tage changes at the output does raise does raise some questions: 1) Is it necessary to capture pre-driver current? The intention of [Composi= te Current] was to improve k-factor determination for Pullup/Pulldown turno= n/turnoff. Currents before the start of the output transition should be irr= elevant. 2) Should IBIS add features to model transition intervals that are shorter = than the waveforms needed to fully characterize each transition, without di= scarding data? This was discussed recently, and I believe it was seen as a = significant challenge. Mike On Fri, Mar 8, 2013 at 11:01 AM, Rinsha Reghunath > wrote: Hi, I am trying to validate an IBIS 5.1 model generated for DDR3 with ISSO_PU/P= D and Composite Current data. The V-T and I-T data is not clipped in order = to capture pre-driver current better and the I-T table has 1000 points. Whe= n I tried to do a transient analysis for validation, SPICE and IBIS V-T wav= eforms are matching at the DDR3 frequency, but IBIS I-T curves are getting = truncated at the rise and fall transitions and doesnot correlate well with = SPICE. The pre-driver current is being lost. When the frequency is reduced,= there is good SPICE - IBIS matching for I-T. Is this issue known or is it an issue in the IBIS model? I have read in http://www.eda.org/ibis/summits/may11/m051111.pdf that "addi= ng [Composite Current] data to the model reduced the valid switching rate o= f the model." Is the above issue related to this? Thanks. Regards, Rinsha - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --_000_EB55FD6CF8C21444BE032D68DDA5FB998B9FD98DNAMBX02mgcmento_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Mike,

Regarding your answer #1, that was not the onl= y intent. In addition

to that, the information in [Composite Current= ] can also be used to

calculate the supply currents more accurately = so that the noise in

the non-ideal supply would be simulated more a= ccurately in SI/PI

simulations. In these situations the pre= - -driver current can also be

important if it comes from the same supply ter= minals as the output

stage.

Thanks,

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D

From: owner-ib= is@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Mike LaBonte
Sent: Sunday, March 10, 2013 3:09 PM
To: Rinsha Reghunath
Cc: ibis@eda.org; ibis-users@eda.org
Subject: Re: [IBIS] Validation of composite current

When you write "IBIS I-T curves are = getting truncated at the rise and fall transitions" do you mean EDA to= ols are doing the truncating? There are several behaviors among the tools, and the tendency is to reduce the length of the V-T curves to the m= inimum needed to represent an edge, to avoid overclocking issues. But the f= act that current changes often appear before the voltage changes at the out= put does raise does raise some questions:

1) Is it necessary to capture pre-driver = current? The intention of [Composite Current] was to improve k-factor deter= mination for Pullup/Pulldown turnon/turnoff. Currents before the start of the output transition should be irrelevant.=

2) Should IBIS add features to model tran= sition intervals that are shorter than the waveforms needed to fully charac= terize each transition, without discarding data? This was discussed recently, and I believe it was seen as a significant challenge.<= /span>

Mike

On Fri, Mar 8, 2013 at 11:01 AM, Rinsha Reghunath &l= t;Rinsha= .Raghunath@synopsys.com> wrote:

Hi,

I am trying to validate an IBIS 5.1 model generated for DDR3 with = ISSO_PU/PD and Composite Current data. The V-T and I-T data is not clipped = in order to capture pre-driver current better and the I-T table has 1000 points. When I tried to do a transient a= nalysis for validation, SPICE and IBIS V-T waveforms are matching at the DD= R3 frequency, but IBIS I-T curves are getting truncated at the rise and fal= l transitions and doesnot correlate well with SPICE. The pre-driver current is being lost. When the frequency = is reduced, there is good SPICE – IBIS matching for I-T.

= &nb= sp; = &nb= sp; = &nb= sp; = &nb= sp; = &nb= sp; = &nb= sp; =

Is this issue known or is it an issue in the IBIS model?

I have read in http://www.eda.org/ibis/summits/may11/m051111.pdf that “addi= ng [Composite Current] data to the model reduced the valid switching rate o= f the model.” Is the above issue related to this?

Thanks.

Regards,

Rinsha

--
This message has been scanned for viruses and
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This message has been scanned for viruses and
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This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --_000_EB55FD6CF8C21444BE032D68DDA5FB998B9FD98DNAMBX02mgcmento_-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #210 *************************