From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #212 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Tuesday, April 2 2013 Volume 01 : Number 212 ---------------------------------------------------------------------- Date: Tue, 26 Mar 2013 10:13:28 -0700 From: "Bob Ross" Subject: [IBIS-Users] European IBIS Summit at SPI 2013 - First Call for Presentations/Participation This is a multipart message in MIME format. - ------=_NextPart_000_0049_01CE2A0A.904E1940 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable All: =20 We are holding the 16th European IBIS Summit Meeting along with the 17th IEEE Workshop on Signal and Power Integrity (SPI 2013), on Wednesday, May 15, 2013 in Paris, France. =20 The purpose is to promote communication among users and developers of IBIS models in Europe. =20 The meeting is FREE and OPEN to everyone. =20 Below is some information on the IBIS Summit and the SPI2013 Workshop. =20 You are invited to register and also to submit presentation proposals. We already plan for several topics listed below =20 Lance Wang IO Methodology =20 Bob Ross Teraspeed Consulting Group =20 =20 =20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 European IBIS Summit at SPI 2013 First Call for Participation and Presentations =20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 http://www.eda.org/ibis/summits/may13/announcement.pdf =20 - ---------------------------------------------------------------------- E U R O P E A N I B I S S U M M I T M E E T I N G=20 - ---------------------------------------------------------------------- =20 Time/Date: 13:00 - 18:00, Wednesday, May 15, 2013=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Location: Hotel Concorde La Fayette http://www.concorde-lafayette.com/en/? 3, Place du G=E9n=E9ral Koenig 75017 Paris, France Tel: +33 1 40 68 50 68 =20=20=20=20=20=20=20=20=20=20=20=20=20=20 Room: To Be Determined =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Content: Presentations and Discussions =20 Purpose: Solicit and Exchange IBIS Model Related Information and Ideas =20 Sponsors: Micron Technology, Zuken and others to be determined =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 If your company would be interested in sponsoring this=20 event, please contact Bob Ross bob@teraspeed.com =20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20 SPI 2013: May 12 - 15, 2013 Location: Hotel Concorde La Fayette, Paris France URL: http://www.spi2013.org/ =20 - ----------------------------------------------------------------------- =20 BACKGROUND =20 We have had successful IBIS meeting along the DATe conference for many years, and more recently the IEEE Workshop on Signal and Power Integrity (formerly Signal Propagation on Interconnects). =20 This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. =20=20=20=20=20=20=20=20 The meeting is FREE and OPEN to everyone. Refreshments & coffee breaks are planned. =20 CALL FOR PARTICIPANTS =20 People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate. If you want to participate, please register with the information below: =20 Name:=20 E-mail address:=20 Company:=20 Telephone:=20 =20 Send to: =20 Lance Wang (lwang@iometh.com) =20 Deadline: May 8, 2013 =20 CALL FOR PRESENTATIONS =20 We are seeking presentations from individuals who have IBIS experiences or issues. Some suggested subjects of interest are: =20=20=20=20=20=20 - IBIS Model Development Experiences - Company IBIS Standards and Requirements - Generating & Validating IBIS Models - Future IBIS Developments and Requirements (e.g., IBIS-AMI) - Modeling of dedicated technology issues (e.g., connectors, and very high speed interfaces) - EMC/EMI and Power Integrity Issues - Related modeling issues (e.g., SPICE, S-Parameter modeling) - Experiences using IBIS in the PCB Design process =20=20=20 Format of Presentation: LCD Projections Time: 15-30 Minutes =20 Electronic Archival: We require electronic versions for so they can be archived and also made available to non-attendees. =20 We prefer Power Point or Acrobat formats. =20 Please send presentations for processing and brief review. Otherwise please bring 20 copies to the meeting. =20=20=20=20=20=20=20=20=20=20 If you plan a presentation, please supply: =20 Title: Presenter: E-mail address: Company: Telephone: Estimated Time: =20 Send this to BOTH: =20 Lance Wang (lwang@iometh.com)=20 Bob Ross (bob@teraspeed.com) =20 Deadline: May 3, 2013 =20 Note, Vendor-specific or product promotional material is forbidden at IBIS Summits. We strongly advise that the presentations be submitted by the deadline for review. The IBIS Open Forum reserves the right to stop or reject a scheduled presentation that has not been reviewed. =20 AGENDA=20 =20 The agenda includes presentations, discussions, breaks and refreshments. This will be developed as presentation proposals are received. =20 =20 LIST OF NEARBY HOTELS=20 =20 Use a search engine to find nearby hotels =20 =20=20 - ----------------------------------------------------------------------=20= =20 =20 - -- Bob Ross Teraspeed Consulting Group, LCC http://www.teraspeed.com bob@teraspeeed.com Direct : 503-246-8048 Teraspeed Labs: 971-279-5325 Headquarters: 401-284-1827 =20 Teraspeed is a registered service mark of Teraspeed Consulting Group LLC =20 =20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0049_01CE2A0A.904E1940 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

All:

 

We are h= olding the 16th European IBIS Summit Meeting along with the

17t= h IEEE Workshop on Signal and Power Integrity (SPI 2013),=

on We= dnesday, May 15, 2013 in Paris, France.

 

The = purpose is to promote communication among users and developers of

 

The meeting is FR= EE and OPEN to everyone.

 

Below is some inf= ormation on the IBIS Summit and the SPI2013 Workshop.

=

&nbs= p;

You are invited to register and also to submit presentation propo= sals.

We already plan for several topics listed below

Lance Wang

IO Methodology

 

Bob Ross

Teraspeed Consulting Group<= /span>

 

 

 

=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

 =

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 First Call for Parti= cipation and Presentations

 

=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

 =

 

-------------------------------------------= - ---------------------------

=A0=A0=A0=A0=A0 E U R O P E A N=A0= =A0 I B I S=A0=A0 S U M M I T=A0=A0 M E E T I N G

------------= - ----------------------------------------------------------

 

Time/Date:=A0=A0=A0=A0 13:00 - 18:00, Wednesday, May 15, 201= 3=A0

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0

Location:=A0=A0=A0=A0=A0 Hotel Concorde La Fayette

= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 http://www.concorde-lafayette.co= m/en/?

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 3, Place du G= =E9n=E9ral Koenig 75017

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0 Paris, France

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 T= el: +33 1 40 68 50 68

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <= o:p>

Room:=A0=A0=A0=A0=A0=A0=A0=A0=A0 To Be Determined

= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0

C= ontent:=A0=A0=A0=A0=A0=A0 Presentations and Discussions

&n= bsp;

Purpose:=A0=A0=A0=A0=A0=A0 Solicit and Exchange IBIS Model Rela= ted Information

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 and = Ideas

 

Sponsors:=A0=A0=A0=A0=A0 Micron Techno= logy, Zuken and others to be determined

=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0

=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0If your company would be interested in sponso= ring this

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0event, = please contact Bob Ross bob@teraspeed.com

 

= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0

SPI 2013:=A0=A0=A0=A0=A0 May 12 - 15, 2013

Location:=A0=A0=A0=A0=A0 Hotel Concorde La Fayette, Paris France=

URL:=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 http://www.spi2013.org/

 

-----------------------------------------------= - ------------------------

 

BACKGROUND

 

=A0 We have had successful IBIS meeting along the = DATe conference

=A0 for many years, and more recently the IEEE = Workshop on Signal

=A0 and Power Integrity (formerly Signal Pro= pagation on Interconnects).

 

=A0 This meeting= will be conducted as a formal IBIS Summit Meeting.

=A0 Present= ations are expected to be available and archived in an

=A0 elec= tronic format, and minutes of the meeting will be issued.=

=A0= =A0=A0=A0=A0=A0=A0

=A0=A0The meeting is FREE and OPEN to every= one.=A0 Refreshments & coffee

=A0 breaks are planned.<= /o:p>

 

CALL FOR PARTICIPANTS

 

=A0 People involved in IBIS Model development, EDA tool development,

=A0 and digital circuit design are invited to=A0 participate. If = you

=A0 want to participate, please register with the informati= on below:

 

<= span style=3D'font-family:"Courier New"'>=A0=A0=A0 Name: =

=A0= =A0=A0=A0E-mail address:

=A0=A0=A0=A0Company:

=A0= =A0=A0=A0Telephone:

 

=A0 Send to:=

=A0 Lance Wang=A0=A0=A0=A0=A0 (lwang@iometh.com)<= /o:p>

 

=A0 Deadline: May 8, 2013

 =

CALL FOR PRESENTATIONS

 

=A0 We are se= eking presentations from individuals who have IBIS

=A0 experien= ces or issues. Some suggested subjects of interest are:

=A0=A0= =A0=A0=A0

=A0=A0- IBIS Model Development Experiences

=A0 - Generati= ng & Validating IBIS Models

=A0 - Future IBIS Developments = and Requirements (e.g., IBIS-AMI)

=A0 - Modeling of dedicated t= echnology issues (e.g., connectors,

=A0=A0=A0 and very high spe= ed interfaces)

=A0 - EMC/EMI and Power Integrity Issues

=A0 - Related modeling issues (e.g., SPICE, S-Parameter modeling)=

=A0 - Experiences using IBIS in the PCB Design process

= =A0=A0

=A0=A0Format of Presentation:=A0 LCD Projections

=A0 Time:=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 15= - -30 Minutes

 

=A0 Electronic Archival:

=A0 We require electronic versions for so they can be archived and

=A0 also made available to non-attendees.

 <= /o:p>

=A0 We prefer Power Point or Acrobat formats.

<= p class=3DMsoPlainText> = ;

=A0 Please send presentations for processing and brief review.

=A0 Otherwise please bring 20 copies to the meeting.

= =A0=A0=A0=A0=A0=A0=A0=A0=A0

<= span style=3D'font-family:"Courier New"'>=A0=A0If you plan a presentation, = please supply:

 

=A0=A0=A0 Title:

= =A0=A0=A0 Presenter:

=A0=A0=A0 E-mail address:

=A0= =A0=A0 Company:

=A0=A0=A0 Telephone:

=A0=A0=A0 Esti= mated Time:

 

=A0 Send this to BOTH:

=A0 Lance Wang=A0=A0 (lwang@iometh.com)

= =A0=A0Bob Ross=A0=A0=A0=A0 (bob@teraspeed.com)

 

 

=A0 Note, Vendo= r-specific or product promotional material is forbidden

=A0 at = IBIS Summits.=A0 We strongly advise that the presentations be

= =A0 submitted by the deadline for review. The IBIS Open Forum reserves=

=A0 the right to stop or reject a scheduled presentation that has n= ot

=A0 been reviewed.

 

<= p class=3DMsoPlainText>AGENDA

 

=A0 The agenda includes presentations, discu= ssions, breaks and

=A0 refreshments. This will be developed as = presentation proposals

=A0 are received.

<= p class=3DMsoPlainText> = ;

 

LIST OF NEARBY HOTELS

 <= /o:p>

=A0 Use a search engine to find nearby hotels

<= p class=3DMsoPlainText> = ;

=A0

-------------------------------------------------= - ---------------------=A0

 

--

Bob Ross

Teraspeed Consulting Group, LCC

=

http://www.teraspeed.com

bob@teraspeeed.com

Direct= : 503-246-8048

Teraspeed Labs: 971-2= 79-5325

Headquarters: 401-284-1827

 

Teraspeed is a registered service mark of Teraspeed Consulting Group = LLC

 

 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_0049_01CE2A0A.904E1940-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 2 Apr 2013 22:56:18 +0000 From: "Mirmak, Michael" Subject: [IBIS-Users] IBISCHK5, Version 5.1.3 Executables Now Available! - --_000_942B8AE05D9831409A64517FFA4C4601491FDED3FMSMSX104amrcor_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable The IBIS Open Forum is pleased to announce the availability of executables = for the IBISCHK5 Golden Parser, version 5.1.3. This latest version continu= es support for IBIS Version 5.1 and resolves parser BUGs 139 through 144, a= s listed at http://www.eda.org/ibis/bugs/ibischk/ The executables, available free of charge, can be found at: http://www.eda.org/ibis/ibischk5/ Executables are available for DOS32 (Microsoft Windows*), and Red Hat Enter= prise Linux 32-bit and 64-bit, though these may work under other Linux oper= ating systems. Note that these are command-line executables, not installer= s. Source code licensees have already received updates. Those wishing to obta= in a source code license may feel free to contact me or any member of the I= BIS Open Forum board directly (please do not reply to all). Thank you for your support of IBIS! - - Michael Mirmak Intel Corp. Chair, IBIS Open Forum http://www.eda.org/ibis/ - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --_000_942B8AE05D9831409A64517FFA4C4601491FDED3FMSMSX104amrcor_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

The IBIS Open Forum is pleased to announce the avail= ability of executables for the IBISCHK5 Golden Parser, version 5.1.3. = This latest version continues support for IBIS Version 5.1 and resolves pa= rser BUGs 139 through 144, as listed at http://www.eda.org/ibis/b= ugs/ibischk/

 

The executables, available free of charge, can be fo= und at:

http:/= /www.eda.org/ibis/ibischk5/

 

Executables are available for DOS32 (Microsoft Windo= ws*), and Red Hat Enterprise Linux 32-bit and 64-bit, though these may work= under other Linux operating systems.  Note that these are command-lin= e executables, not installers. 

 

Source code licensees have already received updates.=   Those wishing to obtain a source code license may feel free to conta= ct me or any member of the IBIS Open Forum board directly (please do not re= ply to all).

 

Thank you for your support of IBIS!

 

- Michael Mirmak

  Intel Corp.

  Chair, IBIS Open Forum

  http://w= ww.eda.org/ibis/

 

 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --_000_942B8AE05D9831409A64517FFA4C4601491FDED3FMSMSX104amrcor_-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 26 Mar 2013 14:57:11 +0000 From: "Muranyi, Arpad" Subject: {Spam?} [IBIS-Users] RE: C_comp subparameters extraction - --_004_EB55FD6CF8C21444BE032D68DDA5FB998BA034D0NAMBX02mgcmento_ Content-Type: multipart/alternative; boundary="_000_EB55FD6CF8C21444BE032D68DDA5FB998BA034D0NAMBX02mgcmento_" - --_000_EB55FD6CF8C21444BE032D68DDA5FB998BA034D0NAMBX02mgcmento_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Rinsha, That drawing doesn't show the input terminal for the buffer, because it assumes that it has enough separation for not having any capacitance currents flow that way, but for debugging your case it would be useful to put a current measurement there too to see if your summation is not working because of that. If you can't get all the terminal currents to add up to zero you must have something inside the buffer which creates or loses energy. This could be in the form of an ideal source, a connection to the infamous global ground node in SPICE (node zero), or similar. By the laws of electronics/physics the all currents in/out of a box has to sum up to zero. I hope this helps, Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D From: Rinsha Reghunath [mailto:Rinsha.Raghunath@synopsys.com] Sent: Tuesday, March 26, 2013 4:55 AM To: Muranyi, Arpad; ibis@eda.org; ibis-users@eda.org Subject: RE: C_comp subparameters extraction Hi Arpad, I have used the same setup for measuring both C_comp and its subparameters = as per the following method specified in the cookbook, where it is mentione= d that "The circuit for measuring split C_comp values is very similar to th= at used for the basic C_comp simulation, except the current will be measure= d at the supply connections, instead of the I/O pad." In the buffer which I= am modeling, there is only one Vcc and one GND terminal, and the currents = are measured through these. But the resulting C_comp subparameter values ca= lculated based on these measured currents doesnot add up to the original C_= comp. [cid:image001.jpg@01CE2A08.00D50AF0] Thanks, Rinsha From: owner-ibis@eda.org [mailto:owner-ibis@eda.= org] On Behalf Of Muranyi, Arpad Sent: Tuesday, March 26, 2013 1:54 AM To: ibis@eda.org; ibis-users@eda.org Subject: [IBIS] RE: C_comp subparameters extraction One more thing I forgot to mention: How many power and ground terminals does your buffer have? If there is more than just one Vcc and one GND terminal, are you sure you are measuring all the possible paths the current might take (including the input terminal)? This might be an "obvious" point, but are you sure that there are no internal sources in your buffer model providing power to any part of the buffer? I hope this helps too... Thanks, Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D From: owner-ibis@eda.org [mailto:owner-ibis@eda.= org] On Behalf Of Muranyi, Arpad Sent: Monday, March 25, 2013 3:18 PM To: ibis@eda.org; ibis-users@eda.org Subject: [IBIS] RE: C_comp subparameters extraction Rinsha, Are you making sure that the conditions between your measurements are the same? C_comp is a tricky thing. It can vary with lots of things. For example, the C_comp you measure could be different when the buffer is 3-stated, diving high or driving low. It also varies with bias voltage, i.e. with the voltage at the pad of the buffer. In order for the numbers to "add up" you have to make sure that you add them up when they are under the same conditions. I hope this helps, Arpad From: owner-ibis@eda.org [mailto:owner-ibis@eda.= org] On Behalf Of Rinsha Reghunath Sent: Monday, March 25, 2013 5:41 AM To: ibis@eda.org; ibis-users@eda.org Subject: [IBIS] C_comp subparameters extraction Hello, I was trying out the extraction of C-comp subparameters, namely, C_comp_pul= lup, C_comp_pulldown, C_comp_power_clamp, and C_comp_gnd_clamp according to= the methodology specified in IBIS cookbook version 4.0, section 3.3.1. But= the extracted C_comp subparameter values doesnot sum up to the actual C_co= mp value extracted. How is the Miller cap being taken care of in this case?= Is there any documentation on the same? Thanks & Regards, Rinsha - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --_000_EB55FD6CF8C21444BE032D68DDA5FB998BA034D0NAMBX02mgcmento_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Rinsha,

 

That drawing doesn’t show the input term= inal for the

buffer, because it assumes that it has enough = separation

for not having any capacitance currents flow t= hat way,

but for debugging your case it would be useful= to put

a current measurement there too to see if your= summation

is not working because of that.

 

If you can’t get all the terminal curren= ts to add up to

zero you must have something inside the buffer= which

creates or loses energy.  This could be i= n the form of

an ideal source, a connection to the infamous = global

ground node in SPICE (node zero), or similar.&= nbsp; By the

laws of electronics/physics the all currents i= n/out of

a box has to sum up to zero.=

 

I hope this helps,

 

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

 

From: Rinsha R= eghunath [mailto:Rinsha.Raghunath@synopsys.com]
Sent: Tuesday, March 26, 2013 4:55 AM
To: Muranyi, Arpad; ibis@eda.org; ibis-users@eda.org
Subject: RE: C_comp subparameters extraction

 

Hi Arpad,

 

I have used the same setup for measuring both C_comp and its subpar= ameters as per the following method specified in the cookbook, where it is = mentioned that “The circuit for measuring split C_comp values is very similar to that used for the basic C_comp simu= lation, except the current will be measured at the supply connections, inst= ead of the I/O pad.” In the buffer which I am modeling, there is only= one Vcc and one GND terminal, and the currents are measured through these. But the resulting C_comp subparameter= values calculated based on these measured currents doesnot add up to the o= riginal C_comp.

 

 

Thanks,

Rinsha

 

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Muranyi, Arpad
Sent: Tuesday, March 26, 2013 1:54 AM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS] RE: C_comp subparameters extraction

 

One more thing I forgot to mention:=

 

How many power and ground terminals does your = buffer have?

If there is more than just one Vcc and one GND= terminal,

are you sure you are measuring all the possibl= e paths the

current might take (including the input termin= al)?

 

This might be an “obvious” point, = but are you sure that

there are no internal sources in your buffer m= odel

providing power to any part of the buffer?

 

I hope this helps too...

 

Thanks,

 

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=

 

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Muranyi, Arpad
Sent: Monday, March 25, 2013 3:18 PM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS] RE: C_comp subparameters extraction

 

Rinsha,

 

Are you making sure that the conditions betwee= n your

measurements are the same?

 

C_comp is a tricky thing.  It can vary wi= th lots of

things.  For example, the C_comp you meas= ure could

be different when the buffer is 3-stated, divi= ng high

or driving low.  It also varies with bias= voltage, i.e.

with the voltage at the pad of the buffer.&nbs= p; In order

for the numbers to “add up” you ha= ve to make sure that

you add them up when they are under the same c= onditions.

 

I hope this helps,

 

Arpad

 

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Rinsha Reghunath
Sent: Monday, March 25, 2013 5:41 AM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS] C_comp subparameters extraction

 

Hello,

 

I was trying out the e= xtraction of C-comp subparameters, namely, C_comp_pullup, C_comp_pulldown, = C_comp_power_clamp, and C_comp_gnd_clamp according to the methodology speci= fied in IBIS cookbook version 4.0, section 3.3.1. But the extracted C_comp subparameter values doesnot sum up to the = actual C_comp value extracted. How is the Miller cap being taken care of in= this case? Is there any documentation on the same?

 

Thanks & Regards,<= o:p>

Rinsha


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e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Sat, 3 Nov 2012 16:07:21 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] Question regarding IBIS for current source type IO This is a multipart message in MIME format. - ------=_NextPart_000_1083_01CDB9DD.4E9793C0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Your driver sounds like an open sink or CML driver for example when it sinks current or an open source or (HSCL) when it sources current. Both types of models work well in IBIS. You will just have a very large Model Selector to create. Tom Dagostino Teraspeed Labs 9999 SW Wilshire St. Suite 102 Portland, OR 97225 USA 971-279-5325 Office 971-279-5326 FAX 503-430-1065 Cell tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Chetan Kumar Sent: Saturday, November 03, 2012 9:20 AM To: ibis-users@eda.org Subject: [IBIS-Users] Question regarding IBIS for current source type IO Hi All, Currently I have an IO which basically works like an current source. The IO can be programmed to source/sink current upto 32 levels. The polarity of the current can be changed based upon internal pin setting. Can I generate IBIS for such a cell. If it is possible then should I model it as a open source type or an output type? Thanks and Best Regards Chethan Kumar - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_1083_01CDB9DD.4E9793C0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Your driver sounds like an open sink or CML driver for exampl= e when it sinks current or an open source or (HSCL) when it sources current= .  Both types of models work well in IBIS.  You will just have a = very large Model Selector to create.

 

Tom Dagostino<= /p>

 

Teraspeed Labs

9999 = SW Wilshire St.

Suite 102

Portland, OR 97225

USA

 

971-279-5325  Office

971-279-5= 326   FAX

503-430-1065  Cell

 

tom@teraspeed.com

www.teraspe= ed.com

 

Teraspeed Consulting Group LLC

121 North River Drive=

Narragansett,= RI 02882

401-284-1827

 

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]= On Behalf Of Chetan Kumar
Sent: Saturday, November 03, 20= 12 9:20 AM
To: ibis-users@eda.org
Subject: [IBIS-Users]= Question regarding IBIS for current source type IO

 

Hi= All,

 

Currently I have an IO which basically works like an current source= . The IO can be programmed to source/sink current upto 32 levels. The polar= ity of the current can be changed based upon internal pin setting. Can I ge= nerate IBIS for such a cell. If it is possible then should I model it as a = open source type or an output type?

 

Than= ks and Best Regards

Chethan Kumar

 


--
This message has = been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean= .


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_1083_01CDB9DD.4E9793C0-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Sat, 20 Oct 2012 17:30:43 -0700 From: "Bob Ross" Subject: [IBIS-Users] Asian IBIS Summit (Hsinchu) - Agenda This is a multipart message in MIME format. - ------=_NextPart_000_0019_01CDAEE8.A26B5040 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit All: We have a full program with ten presentations Registration information is at the bottom We are looking forward to seeing you at the meeting. Best Regards, Lance and Bob - ------------------------------------------------------------------ A S I A N I B I S S U M M I T I N F O R M A T I O N Time/Date: 8:00 - 16:30, Tuesday November 13, 2012 Location: Ambassador Hotel Hsinchu No.188 Section 2, Chung Hwa Road Hsinchu 300, Taiwan Rooms: Ballroom D (look for signs) Sponsors: ANSYS Agilent Technologies Avant Technology (IO Methodology) Cadence Design Systems Intel Corporation - ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 8:15 SIGN IN - Vendor Tables Open at 8:30 9:00 Welcome - Lance Wang (Vice Chair IBIS Open Forum, IO Methodology, USA) - Daniel Chang (ANSYS, ROC) 9:15 Electronic Interconnect Challenges Steven Pytel (ANSYS, USA) 9:30 IBIS 5.1: An Overview Michael Mirmak (Intel Corporation, USA) 9:55 BREAK (Refreshments and Vendor Tables) 10:20 Using Latency Insertion Method to Handle IBIS Models Ping Liu*#, Jilin Tan*##, and Jose Schutt-Aine** (*Cadence Design Systems, #PRC, ##USA and **University of Illinois, USA) 10:55 IBIS-AMI, Industry Adoption, and Current Challenges Naijen Hsuan and TingHao Yeh (ANSYS, ROC) 11:25 Efficient End-to-end Simulations of 25G Optical Links Jing-Tao Liu*#, Fangyi Rao*##, Sanjeev Gupta** and Amolak Badesha** (*Technologies, #PRC, ##USA; and **Avago Technologies, USA) 12:00 FREE BUFFET LUNCH (Hosted by Sponsors) - Vendor Tables 13:30 Chip PDN Model for Power Aware Signal Integrity Analysis Jack W.C. Lin# and Raymond Y. Chen## (Cadence Design Systems, #ROC, ##USA) 14:00 IBIS Parser Update Bob Ross (Teraspeed Consulting Group, USA) 14:25 IBIS Validation Method Review Lance Wang (IO Methodology, USA) 14:50 BREAK (Refreshments and Vendor Tables) 15:15 The Evolution of DDR Memory and Overcoming Challenges of DDR3/4 Design Steven Pytel (ANSYS, USA) 15:50 Designing DDR3 System Using Static Timing Analysis in Conjunction with IBIS Simulations Taranjit Kukal#, Zhangmin Zhong##, and Heiko Dudek### (Cadence Design Systems, #India, ##China, ###Germany) 16;25 Concluding Items 16:30 END OF IBIS SUMMIT MEETING - ------------------------------------------------------------------ To Register by November 6, 2012: Name: E-mail address: Company: Top-level Web Link: Country: Telephone: Send to BOTH: Bob Ross, Teraspeed Consulting Group bob@teraspeed.com Lance Wang, IO Methodology lwang@iometh.com - -- Bob Ross Teraspeed Consulting Group, LCC http://www.teraspeed.com bob@teraspeeed.com Direct : 503-246-8048 Teraspeed Labs: 503-430-1065 Headquarters: 401-284-1827 Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0019_01CDAEE8.A26B5040 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

All:

 

We have = a full program with ten presentations  Registration<= /p>

inform= ation is at the bottom  We are looking forward to seeing

y= ou at the meeting.

 

Best Regards,<= /span>

Lance and Bob

 

-----------------------------= - -------------------------------------

 <= /p>

 =       A S I A N   I B I S   S = U M M I T    I N F O R M A T I O N

 

Time/Date:  8:00 - 16:30, Tuesday November 13, 2012

=  

Location:   Ambassador Hotel Hsinchu

      = ;      Hsinchu 300, Taiwan

 =

Rooms:      Ballroom D (look for signs)

 

Sponsors:   ANSYS

&nbs= p;           Agilent Tech= nologies

         =    Avant Technology (IO Methodology)

   &nb= sp;        Cadence Design Systems

          &nbs= p; Intel Corporation

 

-----------------------= - -------------------------------------------

 =

 =

     =      - Vendor Tables Open at 8:30

=

&nbs= p;

9:00    Welcome

   &nbs= p;      - Lance Wang

   = ;         (Vice Chair IBIS Open For= um, IO Methodology, USA)

      &n= bsp;   - Daniel Chang (ANSYS, ROC)

 =

&nb= sp;         Steven Pytel (ANSYS, US= A)

 

9:30    IBIS 5.1: An Overv= iew

          Mich= ael Mirmak (Intel Corporation, USA)

 

9:55&nbs= p;   BREAK (Refreshments and Vendor Tables)

=

&nbs= p;

10:20   Using Latency Insertion Method to Handle IBIS M= odels

          Pi= ng Liu*#, Jilin Tan*##, and Jose Schutt-Aine**

  &nbs= p;       (*Cadence Design Systems, #PRC, ##US= A and

          **= University of Illinois, USA)

<= span style=3D'font-family:"Courier New"'> 

10:55 &nbs= p; IBIS-AMI, Industry Adoption, and Current Challenges

 &n= bsp;        Naijen Hsuan and TingHao Yeh= (ANSYS, ROC)

 

11:25   Efficient En= d-to-end Simulations of 25G Optical Links

   &nb= sp;      Jing-Tao Liu*#, Fangyi Rao*##, Sanjeev Gu= pta** and

         = ; Amolak Badesha** (*Technologies, #PRC, ##USA; and

  = ;        **Avago Technologies, USA)=

 

12:00   FREE BUFFET LUNCH (Hosted by S= ponsors)

         = - Vendor Tables

 

13:30   Chip PD= N Model for Power Aware Signal Integrity Analysis

  &= nbsp;       Jack W.C. Lin# and Raymond Y. Che= n##

          (Cad= ence Design Systems, #ROC, ##USA)

 

<= p class=3DMsoPlainText>14:00 = ;  IBIS Parser Update

      =     Bob Ross (Teraspeed Consulting Group, USA)

<= o:p> 

14:25   IBIS Validation Method Review

 

14:50   BREAK (Ref= reshments and Vendor Tables)

<= span style=3D'font-family:"Courier New"'> 

15:15 &nbs= p; The Evolution of DDR Memory and Overcoming Challenges of

&nb= sp;       DDR3/4 Design

=

 &nb= sp;        Steven Pytel (ANSYS, USA)

 

15:50   Designing DDR3 System Using S= tatic Timing Analysis in

      &n= bsp; Conjunction with IBIS Simulations

    =       Taranjit Kukal#, Zhangmin Zhong##, and Heiko= Dudek###

         = ; (Cadence Design Systems, #India, ##China, ###Germany)

&n= bsp;

16;25   Concluding Items

 

 

------------------------------------------------------------------=

 

To Register by November 6, 2012:

 

     Name:

  &nbs= p;  E-mail address:

 

   = ;  Company:

     Top-level Web Link:=

 

     Country:

 =

 = ;  Send to BOTH:

 

   &nbs= p; Bob Ross, Teraspeed Consulting Group    bob@teraspeed.com=

     Lance Wang, IO Methodology  = ;            lwang@i= ometh.com

 

 

=  

--

Bob Ross

Teraspeed Consulting G= roup, LCC

http://www.teraspeed.com

bob@teraspeeed.com

Direct : 503-246-8048

Teraspeed Labs: 503-430-1065

Headq= uarters: 401-284-1827

 

Teraspeed is a registered service mark of Ter= aspeed Consulting Group LLC

&nbs= p;


--=20
This message has been scanned for viruses and
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believed to be clean. - ------=_NextPart_000_0019_01CDAEE8.A26B5040-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 6 Nov 2012 17:21:41 -0800 From: "Bob Ross" Subject: [IBIS-Users] Asian IBIS Summit (Yokohama) - Agenda This is a multipart message in MIME format. - ------=_NextPart_000_0017_01CDBC43.3054D8B0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit All: The Agenda showing nine presentations is below. Registration information is given at the end. We are looking forward to seeing everyone in Yokohama. Bob Ross Teraspeed Consulting Group Atsushi Ishikawa JEITA EC Center - ------------------------------------------------------------------ A S I A N I B I S S U M M I T I N F O R M A T I O N Time/Date: Friday November 16, 2012, 13:00 to 18:00 Meeting starts at 13:30 Location: Pacifico Yokohama Annex Hall 1-1-1, Minato Mirai, Nishi-ku Yokohama, JAPAN http://www.pacifico.co.jp/english/index.html Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) IBIS Open Forum Sponsors: ANSYS ATE Service Corporation Cadence Design Systems Mentor Graphics Corporation Zuken - ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 13:00 SIGN IN 13:30 Meeting Welcome Haruhiro Saito (Sony, JEITA EC Center, Japan) Lance Wang (IO Methodology, Vice Chair IBIS Open Forum) 13:40 IBIS 5.1 An Overview Michael Mirmak (Intel Corporation, USA) 14:05 IBIS Parser Update Bob Ross (Teraspeed Consulting Group, USA) 14;30 S-Parameter: What You Can Read, What You Have To Read Shinichi Maeda (KEI Systems, Japan) 15:00 Chip PDN Model for Power Aware Signal Integrity Analysis Jack W.C. Lin# and Raymond Y. Chen## (Cadence Design Systems, #ROC, ###USA) 15:30 BREAK 15:45 The Voice from Practical Designing with SI Simulation Hironari Kibe (Zuken, Japan) 16:10 IBIS Validation Method Review Lance Wang (IO Methodology, USA) 16:35 Over-clocking Model Validation Yasuki Torigoshi (Toshiba Corporation, Japan) 17:00 Designing DDR3 System Using Static Timing Analysis in Conjunction with IBIS Simulations Taranjit Kukal#, Zhangmin Zhong##, and Heiko Dudek### (Cadence Design Systems, #India, ##China, ###Germany) 17:30 The Application of Simulation Kit Using USB3.0 IBIS-AMI Model Motoaki Matsumura (Fujitsu Semiconductor, Japan) 17:55 Concluding Items 18:00 END OF MEETING - ---------------------------------------------------------------- Registration: Please Register with the information below: Name: E-mail address: Company: Country: Send to BOTH: Bob ROSS, Teraspeed Consulting Group bob@teraspeed.com Atsushi ISHIKAWA, JEITA EC Center a-ishikawa@jeita.or.jp - -- Bob Ross Teraspeed Consulting Group, LCC http://www.teraspeed.com bob@teraspeeed.com Direct : 503-246-8048 Teraspeed Labs: 503-430-1065 Headquarters: 401-284-1827 Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0017_01CDBC43.3054D8B0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

All:

 

The Agen= da showing nine presentations is below. Registration

<= p class=3DMsoPlainText>informatio= n is given at the end. We are looking forward to

seeing everyon= e in Yokohama.

 

Bob Ross

Teraspee= d Consulting Group

 

Atsushi Ishikawa

JEITA EC Center

 

------------------------= - ------------------------------------------

 

&= nbsp;     A S I A N   I B I S   S U= M M I T    I N F O R M A T I O N

 

Time/Date:  Friday November 16, 2012, 13:00 to 18:00

=             Meeting = starts at 13:30

 

Location:   Pacifi= co Yokohama Annex Hall

      &nbs= p;     1-1-1, Minato Mirai, Nishi-ku<= /p>

 =            Yokohama, JAPA= N

 

       =      http://www.pacifico.co.jp/english/index.html<= /o:p>

 

Organizational Sponsors:

  =           Japan Electronics an= d Information Technology Industries

    &nb= sp;          Association (JEIT= A)

          =   IBIS Open Forum

 

Sponsors:  = ANSYS

         &n= bsp;  ATE Service Corporation

    &nbs= p;       Cadence Design Systems

&= nbsp;           Mentor Gr= aphics Corporation

       &n= bsp;    Zuken

<= span style=3D'font-family:"Courier New"'> 

---------------= - ---------------------------------------------------

 =

         I B I S = ; S U M M I T  M E E T I N G  A G E N D A

 =

13:00   SIGN IN

 

<= p class=3DMsoPlainText>13:30 = ;  Meeting Welcome

      &nb= sp;   Haruhiro Saito (Sony, JEITA EC Center, Japan)

&= nbsp;         Lance Wang (IO Method= ology, Vice Chair IBIS Open Forum)

 

=

13:40&nbs= p;  IBIS 5.1 An Overview

     &n= bsp;    Michael Mirmak (Intel Corporation, USA)

 

14:05   IBIS Parser Update

&n= bsp;         Bob Ross (Teraspeed Co= nsulting Group, USA)

 

14;30   S-Par= ameter: What You Can Read, What You Have To Read

  &n= bsp;       Shinichi Maeda (KEI Systems, Japan= )

 

15:00   Chip PDN Model for Power= Aware Signal Integrity Analysis

     =      Jack W.C. Lin# and Raymond Y. Chen##

&= nbsp;         (Cadence Design Syste= ms, #ROC, ###USA)

 

15:30   BREAK

 

15:45   The Voice from Practical D= esigning with SI Simulation

      = ;    Hironari Kibe (Zuken, Japan)

 

16:10   IBIS Validation Method Review

<= p class=3DMsoPlainText> &nbs= p;        Lance Wang (IO Methodology, US= A)

 

16:35   Over-clocking Model Val= idation

          = Yasuki Torigoshi (Toshiba Corporation, Japan)

 =

        Conjunction with IBIS= Simulations

        &n= bsp; Taranjit Kukal#, Zhangmin Zhong##, and Heiko Dudek###

&nbs= p;         (Cadence Design Systems,= #India, ##China, ###Germany)

=  

17:30 &nb= sp; The Application of Simulation Kit Using USB3.0 IBIS-AMI

&nb= sp;       Model

   = ;       Motoaki Matsumura (Fujitsu Semiconduc= tor, Japan)

 

17:55   Concluding Ite= ms

 

18:00   END OF MEETING

 

----------------------------------------------------= - ------------

Registration:

<= p class=3DMsoPlainText> = ;

  Please Register with the information below:

 

    Name:

    E-m= ail address:

 

    Company:

    Country:

 

  = Send to BOTH:

 

     Bob R= OSS, Teraspeed Consulting Group    bob@teraspeed.com

     Atsushi ISHIKAWA, JEITA EC Center  =      a-ishikawa@jeita.or.jp

 

 

--

Bob Ross

Teraspeed Consulting Group, LCC

http://www.teraspeed.com

bob@teraspeeed.com

Direct : 503-2= 46-8048

Teraspeed Labs: 503-430-1065<= o:p>

Headquarters: 401-284-1827=

 

Te= raspeed is a registered service mark of Teraspeed Consulting Group LLC=

 


--=20
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