From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #218 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Tuesday, August 27 2013 Volume 01 : Number 218 ---------------------------------------------------------------------- Date: Mon, 26 Aug 2013 13:18:36 -0500 From: Aubrey Sparkman Subject: [IBIS-Users] Re: [IBIS] SI_location / Timing_Location I have used these switches, though I'm not sure I gave them different values. Possible scenario... Interface specs timing at pin, but I want to make sure edges are monotonic at the silicon. Just a though. Aubrey Sparkman Sent from my iPhone On Aug 26, 2013, at 11:44 AM, "Muranyi, Arpad" wrote: > Hello IBIS experts, > > Someone asked me the question whether Si_location and Timing_Location > can have two different values because they have an IBIS file which > does that. > > In attempt to answer their question, I searched the IBIS specification > for Si_location and only found this sentence on pg. 16 (in v5.1): > > "Si_location and Timing_location are optional and specify where the Signal Integrity and Timing measurements are made for the component. Allowed values for either subparameter are "Die" or "Pin". The default location is at the "Pin"." > > I found no other occurrences of "Si_location" or "Timing_location" > in the entire specification, i.e. their meaning, usage and purpose > are not defined. Or am I missing something? > > Going back to the original question, does it make sense to have two > different values for these two parameters? > > Thanks, > > Arpad > ===================================================================== > > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > > -------------------------------------------------------------------- > |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org > |or ibis-request@eda-stds.org > | > |IBIS reflector archives exist under: > | > | http://www.eda-stds.org/ibis/email_archive/ Recent > | http://www.eda-stds.org/ibis/users_archive/ Recent > | http://www.eda-stds.org/ibis/email/ E-mail since 1993 > - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 26 Aug 2013 17:54:07 -0700 From: "Bob Ross" Subject: [IBIS-Users] Asian IBIS Summit (Shanghai) - First Announcement This is a multipart message in MIME format. - ------=_NextPart_000_0026_01CEA285.43A722A0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To All: The IBIS Open Forum is holding an Asian IBIS Summit Meeting in Shanghai, China on Friday, November 15, 2013. Several companies listed below are co-sponsoring this large event to be held again at the Parkyard Hotel, Shanghai. We encourage technical contributions from Asia. For travel consideration, two other Asian IBIS Summits follow this event: Taipei, Taiwan, Tuesday, November 19, Sherwood Hotel Yokohama, Japan, Friday, November 22, Pacifico Yokohama Announcements for these Summits will be issued later. Lance Wang IO Methodology Inc. Bob Ross Teraspeed Consulting Group - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (SHANGHAI) FIRST CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- http://www.eda.org/ibis/summits/nov13a/announcement_chinese.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( S H A N G H A I ) Time/Date: Friday, November 15, 2013, 8:00 AM to 5:30 PM Meeting starts at 9:00 AM Location: Parkyard Hotel Shanghai 699 Bibo Road Zhangjiang Hi-Tech Park Shanghai 201203 P.R. China http://www.parkyard.com/en/hotel_index.aspx?currenthotelid=6 Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Primary Sponsor: Huawei Technologies Co-sponsors (in alphabetical order): Intel Corporation, IO Methodology and others TBD Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables Contact us for details regarding sponsorship. BACKGROUND We have held seven successful meetings in Shenzhen, Shanghai and Beijing. This year we are meeting again in Shanghai where many Chinese and foreign high technology companies operate. These events are archived along with all our other Summits: http://www.eda.org/pub/ibis/summits/ Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Mandarin. So presenters can optionally deliver in Mandarin as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register using the information below (in English): Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Lance Wang, IO Methodology Inc. lwang@iometh.com Bob Ross, Teraspeed Consulting Group bob@teraspeed.com SIGNUP DEADLINE: November 8, 2013 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: October 11, 2013 to produce the presentation booklet for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Submitted presentations must be in English, although the delivery can be in Mandarin. Submissions from Asia are encouraged along with other submissions world-wide. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:15 - 9:00 Vendor table setup and tables 8:30 - 9:00 Sign in 9:00 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 17:00 Presentations The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some future technical directions in IBIS. Several major IBIS Committee presentations from IBIS officers or active members are planned. Several presentations on IBIS applications and behavioral modeling issues, including interconnects and system components, are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels in all price ranges can be found through internet searches. Comply with your travel rules, such as indicated in the link below to China and Shanghai. Work with your travel agent. Notify us as a sign-up comment if you need assistance. Visas, if needed, should fall in the visit/business category: http://travel.state.gov/travel/cis_pa_tw/cis/cis_1089.html - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group, LCC http://www.teraspeed.com bob@teraspeeed.com Direct : 503-246-8048 Teraspeed Labs: 971-279-5325 Headquarters: 401-284-1827 Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0026_01CEA285.43A722A0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

To All:

 

The IBIS Open Forum is hold= ing an Asian IBIS Summit Meeting in

Shanghai, = China on Friday, November 15, 2013.

 = ;

Several companies listed below are co-sponsoring = this large event

to be held again at the Par= kyard Hotel, Shanghai.

 

We encourage technical contributions from Asia.

 

For travel consideration= , two other Asian IBIS Summits follow this

eve= nt:

 

 = Taipei, Taiwan, Tuesday, November 19, Sherwood Hotel

=

  Yokohama, Japan, Friday, November 22, Pacifico Yokohama=

 

Announcements = for these Summits will be issued later.

&= nbsp;

Lance Wang

IO Me= thodology Inc.

 

Bob Ross

Teraspeed Consulting Group<= /o:p>

 

 

 

------------------= - -----------------------------------------------------

=

           &= nbsp;           ASIAN IBI= S SUMMIT (SHANGHAI)

    &n= bsp;            = ;             F= IRST CALL FOR

     &n= bsp;            = ;    PARTICIPATION AND PRESENTATIONS

---------------------------------------------------------------------= - --

 

http://= www.eda.org/ibis/summits/nov13a/announcement_chinese.pdf<= /p>

 

~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

=  

      &nb= sp;    A S I A N   I B I S   S U M M I T=   ( S H A N G H A I )

 

Time/Date:  Friday, November 15, 2013, 8:00 AM = to 5:30 PM

      = ;      Meeting starts at 9:00 AM=

 

Location:   Parky= ard Hotel Shanghai

    &nb= sp;       699 Bibo Road

=

            = Zhangjiang Hi-Tech Park

   &nbs= p;        Shanghai 201203

          =  P.R. China

 

      http://www.parkyard.com/en/hotel_in= dex.aspx?currenthotelid=3D6

 <= /span>

Content:    Presentations and Discussions<= o:p>

 

Purpose:&n= bsp;   Solicit and exchange IBIS and interconnect model related

        = ;    information and ideas.

 

Primary Sponsor:

            Huaw= ei Technologies

 

Co-sponsors (in alphabetical order):

&nb= sp;           Intel Corpo= ration, IO Methodology and others TBD

&nb= sp;

Cost:       FREE,= including refreshments and buffet lunch

=  

Vendors:    Some vendors will= have information tables

 

          =   Contact us for details regarding sponsorship.

<= p class=3DMsoPlainText> 

BACKGROUND

=

 

   We have held seven= successful meetings in Shenzhen, Shanghai and Beijing.

   This year we are meeting again in Shanghai where man= y Chinese and

   foreign high techno= logy companies operate.  These events are archived

   along with all our other Summits:<= /p>

 

     ht= tp://www.eda.org/pub/ibis/summits/

 =

   Our objective is to reach out interna= tionally to communicate with

<= span style=3D'font-size:10.0pt;font-family:"Courier New"'>   the = local experts and to learn of regional concerns.

CONFERENCE LANGUAGE

 

   The conferenc= e language is English, but we will plan for technical

=

   translations in English and Mandarin.  So present= ers can optionally

   deliver in Man= darin as long as an English version of the material is

   available.

 

IBIS SUMMIT

 =

   This meeting will be conducted as a f= ormal IBIS Summit Meeting.

   Presen= tations will be archived in an electronic format on our

   Summits site, and minutes of the meeting will be iss= ued.  However,

   no formal dec= isions requiring votes will be planned.

&= nbsp;

CALL FOR PARTICIPANTS

 

   People involved in I= BIS and interconnect model development, EDA

=    tool development, and digital circuit design are invited to

   participate in the Summit meeting.&= nbsp; If you plan to participate,

  = please register using the information below (in English):

 

     N= ame:

     E-mail address:<= o:p>

 

 &nbs= p;   Company:

   &nbs= p; Top-level Web Link:

 

     Country:

 

   Send to BOTH:<= /span>

 

   &nb= sp; Lance Wang, IO Methodology Inc.       &nb= sp; lwang@iometh.com

   &n= bsp; Bob Ross, Teraspeed Consulting Group    bob@teraspeed.c= om

 

&n= bsp;

   SIGNUP DEADLINE: November 8, 2013=

 

CALL FOR = PRESENTATIONS

 

   We are seeking presentations from individuals who have IBI= S and

   interconnect modeling exper= iences or issues.  If we have to

 &n= bsp; select presentations for the number of time slots available, we

   will give preferential consideration to= presentations from Asia.

 

   Presentation Format:   LCD Projectio= n from meeting laptop computer

 

   Time:      =             15-30 Mi= nutes including questions

 

   Electronic Archival:   All presentat= ions will uploaded to our public

  &= nbsp;           &nbs= p;           IBIS Summit = archives

 

=    Electronic Format:     Power Point or Acro= bat

 

 =   Presentation Booklet:  Available at the meeting for all attende= es

 

 &= nbsp; Presentation Deadline: October 11, 2013 to produce the presentation

        = ;            &n= bsp;     booklet for the meeting

<= p class=3DMsoPlainText> 

   If you plan a prese= ntation, please ADD to the above registration

=    information:

 

     Title of Presentation:<= /span>

 

   &nb= sp; Estimated Time:

     &= nbsp; (30 minutes or less)

 

   We will notify you of acceptance and may= follow up with questions

   when we= form the program agenda.

 

   Note: Vendor promotional or business informati= on is prohibited.

   Submitted pres= entations must be in English, although the delivery

   can be in Mandarin.

&n= bsp;

   Submissions from Asia are encoura= ged along with other submissions

   = world-wide.  Topics may include behavioral modeling of buffers,

   interconnects or other system component= s.

 

AGENDA<= o:p>

 

 &nbs= p; 8:15 -   9:00  Vendor table setup and tables

   8:30 -   9:00  Sign in

   9:00 -  12:00  Presentations

   12:00 - 13:30  Free buffet lu= nch, vendor tables

   13:30 - 17:00&= nbsp; Presentations

 

   The specific agenda is being developed.  We exp= ect nine or ten

   presentations cov= ering a range of issues from existing customer

   experiences, existing clarifications and some future technica= l

   directions in IBIS.<= /span>

 

   Several = major IBIS Committee presentations from IBIS officers or<= /p>

   active members are planned.

 

   Several presentation= s on IBIS applications and behavioral modeling

   issues, including interconnects and system components, are ex= pected

   from co-sponsor companies = and/or their customers.

 

LIST OF NEARBY HOTELS AND TRAVEL RULES

<= p class=3DMsoPlainText> 

   Hotels in all price= ranges can be found through internet searches.

   Comply with your travel = rules, such as indicated in the link

 &nb= sp; below to China and Shanghai.  Work with your travel agent.  N= otify

   us as a sign-up comment if = you need assistance.  Visas, if needed,

=    should fall in the visit/business category:<= /p>

 

     ht= tp://travel.state.gov/travel/cis_pa_tw/cis/cis_1089.html<= /p>

 

---------------------------= - --------------------------------------

&n= bsp;

 

--

Bob Ross

Teraspeed Consulting Group, LCC

http://www.teraspeed.com

bob@teraspeeed.com

Direct : 503-2= 46-8048

Teraspeed Labs: 971-279-5325<= o:p>

Headquarters: 401-284-1827=

 

Te= raspeed is a registered service mark of Teraspeed Consulting Group LLC=

 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_0026_01CEA285.43A722A0-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 26 Aug 2013 16:44:15 +0000 From: "Muranyi, Arpad" Subject: [IBIS-Users] SI_location / Timing_Location Hello IBIS experts, Someone asked me the question whether Si_location and Timing_Location can have two different values because they have an IBIS file which does that. In attempt to answer their question, I searched the IBIS specification for Si_location and only found this sentence on pg. 16 (in v5.1): "Si_location and Timing_location are optional and specify where the Signal Integrity and Timing measurements are made for the component. Allowed values for either subparameter are "Die" or "Pin". The default location is at the "Pin"." I found no other occurrences of "Si_location" or "Timing_location" in the entire specification, i.e. their meaning, usage and purpose are not defined. Or am I missing something? Going back to the original question, does it make sense to have two different values for these two parameters? Thanks, Arpad ===================================================================== - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 27 Aug 2013 13:38:44 -0400 From: Scott McMorrow Subject: [IBIS-Users] Re: [IBIS] SI_location / Timing_Location - --047d7b15a3c533140204e4f158a9 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Actually, Si_location and Timing_location go back to 1997 and were introduced by Bob Ross of Interconnectix (pre-Mentor) http://www.eda.org/ibis/birds/bird43.txt Timing_location may also need to be changed to die for large FPGA type devices, because of large non-monotonic signals at the pins. On Tue, Aug 27, 2013 at 1:30 PM, Robert Haller wrote: > I think the SiSoft guys probably pushed for this a while ago. Their > software can do chip to chip timing either at pin or pad (on either end of > transmission line). Usually one performs static timing from pin to pin > because then there is no double counting when using data sheet timing > specs. But if you are designing the silicon and the package, there are > good reasons to perform timing pad to pad when you are trying to shave > picoseconds. > Regards > Bob > > -----Original Message----- > From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Aubrey > Sparkman > Sent: Monday, August 26, 2013 2:19 PM > To: Muranyi, Arpad > Cc: IBIS; IBIS-users > Subject: Re: [IBIS] SI_location / Timing_Location > > I have used these switches, though I'm not sure I gave them different > values. > > Possible scenario... Interface specs timing at pin, but I want to make > sure edges are monotonic at the silicon. > > Just a though. > > Aubrey Sparkman > > Sent from my iPhone > > On Aug 26, 2013, at 11:44 AM, "Muranyi, Arpad" > wrote: > > > Hello IBIS experts, > > > > Someone asked me the question whether Si_location and Timing_Location > > can have two different values because they have an IBIS file which > > does that. > > > > In attempt to answer their question, I searched the IBIS specification > > for Si_location and only found this sentence on pg. 16 (in v5.1): > > > > "Si_location and Timing_location are optional and specify where the > Signal Integrity and Timing measurements are made for the component. > Allowed values for either subparameter are "Die" or "Pin". The default > location is at the "Pin"." > > > > I found no other occurrences of "Si_location" or "Timing_location" > > in the entire specification, i.e. their meaning, usage and purpose are > > not defined. Or am I missing something? > > > > Going back to the original question, does it make sense to have two > > different values for these two parameters? > > > > Thanks, > > > > Arpad > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > > > > > > -- > > This message has been scanned for viruses and dangerous content by > > MailScanner, and is believed to be clean. > > > > > > -------------------------------------------------------------------- > > |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org > > |or ibis-request@eda-stds.org > > | > > |IBIS reflector archives exist under: > > | > > | http://www.eda-stds.org/ibis/email_archive/ Recent > > | http://www.eda-stds.org/ibis/users_archive/ Recent > > | http://www.eda-stds.org/ibis/email/ E-mail since 1993 > > > > -- > This message has been scanned for viruses and dangerous content by > MailScanner, and is believed to be clean. > > > -------------------------------------------------------------------- > |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org > |or ibis-request@eda-stds.org > | > |IBIS reflector archives exist under: > | > | http://www.eda-stds.org/ibis/email_archive/ Recent > | http://www.eda-stds.org/ibis/users_archive/ Recent > | http://www.eda-stds.org/ibis/email/ E-mail since 1993 > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > -------------------------------------------------------------------- > |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org > |or ibis-request@eda-stds.org > | > |IBIS reflector archives exist under: > | > | http://www.eda-stds.org/ibis/email_archive/ Recent > | http://www.eda-stds.org/ibis/users_archive/ Recent > | http://www.eda-stds.org/ibis/email/ E-mail since 1993 > - --=20 Scott McMorrow Teraspeed Consulting Group LLC 16 Stormy Brook Rd Falmouth, ME 04105 (401) 284-1827 Business http://www.teraspeed.com Teraspeed=AE is the registered service mark of Teraspeed Consulting Group LLC - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --047d7b15a3c533140204e4f158a9 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Actually, Si_location and Timing_location go back to 1997 = and were introduced by Bob Ross of Interconnectix (pre-Mentor)


Timing_location may also need to be changed to di= e for large FPGA type devices, because of large non-monotonic signals at th= e pins.




On Tue, Aug 27, 2013 at 1:30 PM, Robert = Haller <rhaller@enterasys.com> wrote:
I think the SiSoft guys probably pushed for this a while ago. Their
software can do chip to chip timing either at pin or pad (on either end of<= br> transmission line). Usually one performs static timing from pin to pin
because then there is no double counting when using data sheet timing
specs. But if you are designing the silicon and the package, there are
good reasons to perform timing pad to pad when you are trying to shave
picoseconds.
Regards
Bob

- -----Original Message-----
From: owner-ibis@eda.org [mailto:= owner-ibis@eda.org] On Behalf Of = Aubrey
Sparkman
Sent: Monday, August 26, 2013 2:19 PM
To: Muranyi, Arpad
Cc: IBIS; IBIS-users
Subject: Re: [IBIS] SI_location / Timing_Location

I have used these switches, though I'm not sure I gave them different values.

Possible scenario... =A0 Interface specs timing at pin, but I want to make<= br> sure edges are monotonic at the silicon.

Just a though.

Aubrey Sparkman

Sent from my iPhone

On Aug 26, 2013, at 11:44 AM, "Muranyi, Arpad" <Arpad_Muranyi@mentor.com>
wrote:

> Hello IBIS experts,
>
> Someone asked me the question whether Si_location and Timing_Location<= br> > can have two different values because they have an IBIS file which
> does that.
>
> In attempt to answer their question, I searched the IBIS specification=
> for Si_location and only found this sentence on pg. 16 (in v5.1):
>
> "Si_location and Timing_location are optional and specify where t= he
Signal Integrity and Timing measurements are made for the component.
Allowed values for either subparameter are "Die" or "Pin&quo= t;. The default
location is at the "Pin"."
>
> I found no other occurrences of "Si_location" or "Timin= g_location"
> in the entire specification, i.e. their meaning, usage and purpose are=
> not defined. =A0Or am I missing something?
>
> Going back to the original question, does it make sense to have two
> different values for these two parameters?
>
> Thanks,
>
> Arpad
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>
>
>
> --
> This message has been scanned for viruses and dangerous content by
> MailScanner, and is believed to be clean.
>
>
> -------------------------------------------------------------------- > |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org
> |or ibis-request@eda-stds= .org
> |
> |IBIS reflector archives exist under:
> |
> | =A0http://www.eda-stds.org/ibis/email_archive/ Recent
> | http://www.eda-stds.org/ibis/users_archive/ Recent
> | =A0http://www.eda-stds.org/ibis/email/ =A0 =A0 =A0 =A0 E-mail since 1993<= br> >

- --
This message has been scanned for viruses and dangerous content by
MailScanner, and is believed to be clean.


- --------------------------------------------------------------------
|For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org
|or ibis-request@eda-stds.org<= /a>
|
|IBIS reflector archives exist under:
|
| =A0http://www.eda-stds.org/ibis/email_archive/ Recent
| =A0http://www.eda-stds.org/ibis/users_archive/ Recent
| =A0http= ://www.eda-stds.org/ibis/email/ =A0 =A0 =A0 =A0 E-mail since 1993

- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.

- --------------------------------------------------------------------
|For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org
|or ibis-request@eda-stds.org<= /a>
|
|IBIS reflector archives exist under:
|
| =A0http://www.eda-stds.org/ibis/email_archive/ Recent
| =A0http://www.eda-stds.org/ibis/users_archive/ Recent
| =A0http= ://www.eda-stds.org/ibis/email/ =A0 =A0 =A0 =A0 E-mail since 1993



--

Scott Mc= Morrow
Teraspeed Consulting Group LLC
16 Stormy Brook Rd
Falmouth,= ME 04105

(401) 284-1827 Business

http://www.teraspeed.com

Teraspeed=AE is the registered service mark of
Teraspeed Consulting = Group LLC



--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --047d7b15a3c533140204e4f158a9-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 27 Aug 2013 13:30:49 -0400 From: Robert Haller Subject: [IBIS-Users] RE: [IBIS] SI_location / Timing_Location I think the SiSoft guys probably pushed for this a while ago. Their software can do chip to chip timing either at pin or pad (on either end of transmission line). Usually one performs static timing from pin to pin because then there is no double counting when using data sheet timing specs. But if you are designing the silicon and the package, there are good reasons to perform timing pad to pad when you are trying to shave picoseconds. Regards Bob - -----Original Message----- From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Aubrey Sparkman Sent: Monday, August 26, 2013 2:19 PM To: Muranyi, Arpad Cc: IBIS; IBIS-users Subject: Re: [IBIS] SI_location / Timing_Location I have used these switches, though I'm not sure I gave them different values. Possible scenario... Interface specs timing at pin, but I want to make sure edges are monotonic at the silicon. Just a though. Aubrey Sparkman Sent from my iPhone On Aug 26, 2013, at 11:44 AM, "Muranyi, Arpad" wrote: > Hello IBIS experts, > > Someone asked me the question whether Si_location and Timing_Location > can have two different values because they have an IBIS file which > does that. > > In attempt to answer their question, I searched the IBIS specification > for Si_location and only found this sentence on pg. 16 (in v5.1): > > "Si_location and Timing_location are optional and specify where the Signal Integrity and Timing measurements are made for the component. Allowed values for either subparameter are "Die" or "Pin". The default location is at the "Pin"." > > I found no other occurrences of "Si_location" or "Timing_location" > in the entire specification, i.e. their meaning, usage and purpose are > not defined. Or am I missing something? > > Going back to the original question, does it make sense to have two > different values for these two parameters? > > Thanks, > > Arpad > ===================================================================== > > > > -- > This message has been scanned for viruses and dangerous content by > MailScanner, and is believed to be clean. > > > -------------------------------------------------------------------- > |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org > |or ibis-request@eda-stds.org > | > |IBIS reflector archives exist under: > | > | http://www.eda-stds.org/ibis/email_archive/ Recent > | http://www.eda-stds.org/ibis/users_archive/ Recent > | http://www.eda-stds.org/ibis/email/ E-mail since 1993 > - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 24 Jun 2013 08:04:24 -0500 From: Gregory R Edlund Subject: Re: [IBIS-Users] IBIS query - --0__=09BBF107DFD487F68f9e8a93df938690918c09BBF107DFD487F6 Content-type: multipart/alternative; Boundary="1__=09BBF107DFD487F68f9e8a93df938690918c09BBF107DFD487F6" - --1__=09BBF107DFD487F68f9e8a93df938690918c09BBF107DFD487F6 Content-type: text/plain; charset=US-ASCII Content-transfer-encoding: quoted-printable Girija, IBIS uses the following syntax to identify a tri-state model: Model_type 3-state Are you making a new IBIS model or using one that's already made? The IBIS community has free tools available for making IBIS models. If you are new to IBIS, I recommend reading the original IBIS 1.1 specification and the Cookbook. http://www.eda.org/ibis/ver1.1/ver1_1.ibs http://www.eda.org/ibis/tools/ Greg Edlund Senior Engineer Signal Integrity and System Timing IBM Systems & Technology Group 3605 Hwy. 52 N Bldg 050-3 Rochester, MN 55901 From: Girija V Chougala To: "ibis-users@eda.org" Date: 06/24/2013 02:11 AM Subject: [IBIS-Users] IBIS query Sent by: owner-ibis-users@eda.org Hi, Please guide me in the following query which I got from one of my customer, Question: How i can assign a tri state model? I need to simulate a local bus data line in which ibis model is a member which need to be tri stated. Please let me know what need to be done and what is he asking. I appreciate quick response. Regards, Girija This message and any attachments may contain Cypress (or its subsidiaries) confidential information. If it has been received in error, please advise the sender and immediately delete this message. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --1__=09BBF107DFD487F68f9e8a93df938690918c09BBF107DFD487F6 Content-type: text/html; charset=US-ASCII Content-Disposition: inline Content-transfer-encoding: quoted-printable

Girija,

IBIS uses the following syntax to iden= tify a tri-state model:

Model_type      3-state=

Are you making a new IBIS model or usi= ng one that's already made?  The IBIS community has free tools availab= le for making IBIS models.  If you are new to IBIS, I recommend readin= g the original IBIS 1.1 specification and the Cookbook.

http://www.eda.org/ibis/ver1.1/ver1_1.ibs

http://www.eda.org/ibis/tools/

Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N  Bldg 050-3
Rochester, MN 55901



3D"InactiveGirij= a V Chougala ---06/24/2013 02:11:00 AM---Hi, Please guide me in the followi= ng query which I got from one of my customer,

From: Girija V Chougala <gvch@cypress.com>
To: "ibis-users@eda.org" <ibis-users@e= da.org>
Date: 06/24/2013 02:11 AM
Subject: [IBIS-Users] IBIS query
Sent by: owner-ibis-users@eda.org




Hi,
Please guide me in the following query wh= ich I got from one of my customer,
Question: How i can assign a tri state= model? I need to simulate a local bus data line in which ibis model is a m= ember which need to be tri stated.
 
Please let me know what need to be done a= nd what is he asking.
I appreciate quick response.
 
Regards,
Girija

This message and any attachments may con= tain Cypress (or its subsidiaries) confidential information. If it has been= received in error, please advise the sender and immediately delete this me= ssage.
- --
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


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This message has been scanned for viruses and
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believed to be clean. - --1__=09BBF107DFD487F68f9e8a93df938690918c09BBF107DFD487F6-- - --0__=09BBF107DFD487F68f9e8a93df938690918c09BBF107DFD487F6 Content-type: image/gif; name="graycol.gif" Content-Disposition: inline; filename="graycol.gif" Content-ID: <1__=09BBF107DFD487F68f9e8a93df938@us.ibm.com> Content-transfer-encoding: base64 R0lGODlhEAAQAKECAMzMzAAAAP///wAAACH5BAEAAAIALAAAAAAQABAAAAIX lI+py+0PopwxUbpuZRfKZ2zgSJbmSRYAIf4fT3B0aW1pemVkIGJ5IFVsZWFk IFNtYXJ0U2F2ZXIhAAA7 - --0__=09BBF107DFD487F68f9e8a93df938690918c09BBF107DFD487F6-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 23 Apr 2013 21:03:31 -0700 From: "Bob Ross" Subject: [IBIS-Users] European IBIS Summit at SPI 2013 - Third Call This is a multipart message in MIME format. - ------=_NextPart_000_0001_01CE4066.03723020 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable All: =20 We are holding the 16th European IBIS Summit Meeting along with the 17th IEEE Workshop on Signal and Power Integrity (SPI 2013), on Wednesday, May 15, 2013 in Paris, France. =20 The purpose is to promote communication among users and developers of IBIS models in Europe. =20 The meeting is FREE and OPEN to everyone. =20 Below is some information on the IBIS Summit and the SPI2013 Workshop. =20 You are invited to register and also to submit presentation proposals. We already plan for several topics listed below =20 Lance Wang IO Methodology =20 Bob Ross Teraspeed Consulting Group =20 =20 =20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 European IBIS Summit at SPI 2013 Third Call for Participation and Presentations =20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 http://www.eda.org/ibis/summits/may13/announcement.pdf =20 - ---------------------------------------------------------------------- E U R O P E A N I B I S S U M M I T M E E T I N G=20 - ---------------------------------------------------------------------- =20 Time/Date: 13:00 - 18:00, Wednesday, May 15, 2013=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Location: Hotel Concorde La Fayette http://www.concorde-lafayette.com/en/? 3, Place du G=E9n=E9ral Koenig 75017 Paris, France Tel: +33 1 40 68 50 68 =20=20=20=20=20=20=20=20=20=20=20=20=20=20 Room: To Be Determined =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Content: Presentations and Discussions =20 Purpose: Solicit and Exchange IBIS Model Related Information and Ideas =20 Sponsors: Micron Technology, Zuken and others to be determined =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 If your company would be interested in sponsoring this=20 event, please contact Bob Ross bob@teraspeed.com =20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20 SPI 2013: May 12 - 15, 2013 Location: Hotel Concorde La Fayette, Paris France URL: http://www.spi2013.org/ =20 - ---------------------------------------------------------------------- =20 BACKGROUND =20 We have had successful IBIS meeting along the DATe conference for many years, and more recently the IEEE Workshop on Signal and Power Integrity (formerly Signal Propagation on Interconnects). =20 This meeting will be conducted as a formal IBIS Summit Meeting. Presentations are expected to be available and archived in an electronic format, and minutes of the meeting will be issued. =20=20=20=20=20=20=20=20 The meeting is FREE and OPEN to everyone. Refreshments & coffee breaks are planned. =20 CALL FOR PARTICIPANTS =20 People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate. If you want to participate, please register with the information below: =20 Name:=20 E-mail address:=20 Company:=20 Telephone:=20 =20 Send to: =20 Lance Wang (lwang@iometh.com) =20 Deadline: May 8, 2013 =20 CALL FOR PRESENTATIONS =20 We are seeking presentations from individuals who have IBIS experiences or issues. Some suggested subjects of interest are: =20=20=20=20=20=20 - IBIS Model Development Experiences - Company IBIS Standards and Requirements - Generating & Validating IBIS Models - Future IBIS Developments and Requirements (e.g., IBIS-AMI) - Modeling of dedicated technology issues (e.g., connectors, and very high speed interfaces) - EMC/EMI and Power Integrity Issues - Related modeling issues (e.g., SPICE, S-Parameter modeling) - Experiences using IBIS in the PCB Design process =20=20=20 Format of Presentation: LCD Projections Time: 15-30 Minutes =20 Electronic Archival: We require electronic versions for so they can be archived and also made available to non-attendees. =20 We prefer Power Point or Acrobat formats. =20 Please send presentations for processing and brief review. Otherwise please bring 20 copies to the meeting. =20=20=20=20=20=20=20=20=20=20 If you plan a presentation, please supply: =20 Title: Presenter: E-mail address: Company: Telephone: Estimated Time: =20 Send this to BOTH: =20 Lance Wang (lwang@iometh.com)=20 Bob Ross (bob@teraspeed.com) =20 Deadline: May 3, 2013 =20 Note, Vendor-specific or product promotional material is forbidden at IBIS Summits. We strongly advise that the presentations be submitted by the deadline for review. The IBIS Open Forum reserves the right to stop or reject a scheduled presentation that has not been reviewed. =20 AGENDA=20 =20 The agenda includes presentations, discussions, breaks and refreshments. This will be developed as presentation proposals are received. =20 =20 LIST OF NEARBY HOTELS=20 =20 Use a search engine to find nearby hotels =20 - ---------------------------------------------------------------------- =20 =20 - -- Bob Ross Teraspeed Consulting Group, LCC http://www.teraspeed.com bob@teraspeeed.com Direct : 503-246-8048 Teraspeed Labs: 971-279-5325 Headquarters: 401-284-1827 =20 Teraspeed is a registered service mark of Teraspeed Consulting Group LLC =20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0001_01CE4066.03723020 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

All:

 

We are h= olding the 16th European IBIS Summit Meeting along with the

17t= h IEEE Workshop on Signal and Power Integrity (SPI 2013),=

on We= dnesday, May 15, 2013 in Paris, France.

 

The = purpose is to promote communication among users and developers of

 

The meeting is FR= EE and OPEN to everyone.

 

Below is some inf= ormation on the IBIS Summit and the SPI2013 Workshop.

=

&nbs= p;

You are invited to register and also to submit presentation propo= sals.

We already plan for several topics listed below

Lance Wang

IO Methodology

 

Bob Ross

Teraspeed Consulting Group<= /span>

 

 

 

=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

 =

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 Third Call for Particip= ation and Presentations

 

=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

 

= =A0=A0=A0=A0=A0=A0 http://www.eda.org/ibis/summits/may13/announcement.pdf

 

--------------------------------------------= - --------------------------

=A0=A0=A0=A0=A0 E U R O P E A N=A0= =A0 I B I S=A0=A0 S U M M I T=A0=A0 M E E T I N G

------------= - ----------------------------------------------------------

 

Time/Date:=A0=A0=A0=A0 13:00 - 18:00, Wednesday, May 15, 201= 3=A0

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0

Location:=A0=A0=A0=A0=A0 Hotel Concorde La Fayette

= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 http://www.concorde-lafayette.co= m/en/?

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 3, Place du G= =E9n=E9ral Koenig 75017

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0 Paris, France

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 T= el: +33 1 40 68 50 68

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <= o:p>

Room: =A0=A0=A0=A0=A0=A0=A0=A0=A0To Be Determined

= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0

C= ontent:=A0=A0=A0=A0=A0=A0 Presentations and Discussions

&n= bsp;

Purpose:=A0=A0=A0=A0=A0=A0 Solicit and Exchange IBIS Model Rela= ted Information

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 and = Ideas

 

Sponsors:=A0=A0=A0=A0=A0 Micron Techno= logy, Zuken and others to be determined

=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0

=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0If your company would be interested in sponsorin= g this

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0event, ple= ase contact Bob Ross bob@teraspeed.com

 =

=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0

SPI 2013:=A0=A0=A0=A0=A0 May 12 - 15, 2013

Location:=A0=A0=A0=A0=A0 Hotel Concorde La Fayette, Paris France=

URL:=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 http://www.spi2013.org/

 

----------------------------------------------------= - ------------------

 

BACKGROUND

 

=A0 We have had successful IBIS meeting along the DATe con= ference

=A0 for many years, and more recently the IEEE Workshop= on Signal

=A0 and Power Integrity (formerly Signal Propagation= on Interconnects).

 

=A0 This meeting will be= conducted as a formal IBIS Summit Meeting.

=A0 Presentations= are expected to be available and archived in an

=A0 electronic= format, and minutes of the meeting will be issued.

=A0=A0=A0= =A0=A0=A0=A0

=A0=A0The meeting is FREE and OPEN to everyone.= =A0 Refreshments & coffee

= =A0 breaks are planned.

CALL FOR PARTICIPANTS

 =

=A0 and digital circuit design are invited to=A0 participate. If yo= u

=A0 want to participate, please register with the information= below:

 

=A0=A0=A0 Name:

=A0=A0= =A0=A0E-mail address:

=A0=A0=A0=A0Company: <= /p>

=A0=A0= =A0=A0Telephone:

 

=A0 Send to:

=  

=A0 Lance Wang=A0=A0=A0=A0=A0 (lwang@iometh.com)

 

=A0 Deadline: May 8, 2013

 

CALL FOR PRESENTATIONS

<= span style=3D'font-family:"Courier New"'> 

=A0 We are seek= ing presentations from individuals who have IBIS

=A0 experience= s or issues. Some suggested subjects of interest are:

=

=A0=A0=A0= =A0=A0

=A0=A0- IBIS Model Development Experiences

= =A0 - Company IBIS Standards and Requirements

=A0 - Generating = & Validating IBIS Models

<= span style=3D'font-family:"Courier New"'>=A0 - Future IBIS Developments and= Requirements (e.g., IBIS-AMI)

=A0 - Modeling of dedicated tech= nology issues (e.g., connectors,

=A0=A0=A0 and very high speed = interfaces)

=A0 - EMC/EMI and Power Integrity Issues=

=A0 - Experiences using IBIS in the PCB Design process

=A0= =A0

=A0=A0Format of Presentation:=A0 LCD Projections

 

=A0 Electronic Archival:=

=A0 also made available to non-attendees.

 

=A0 We prefer Power Point or Acrobat formats.

 

=A0 Please send presentations for processing and brief review.

=A0 Otherwise please bring 20 copies to the meeting.

=A0= =A0=A0=A0=A0=A0=A0=A0=A0

=A0=A0If you plan a presentation, ple= ase supply:

 

=A0=A0=A0 Title:

=A0= =A0=A0 Presenter:

=A0=A0=A0 E-mail address:<= /p>

=A0=A0= =A0 Company:

=A0=A0=A0 Telephone:

=A0=A0=A0 Estimat= ed Time:

 

=A0 Send this to BOTH:

=  

=A0 Lance Wang=A0=A0 (lwang@iometh.com)

=A0= =A0Bob Ross=A0=A0=A0=A0 (bob@teraspeed.com)

 =

 

=A0 Note, Vendor= - -specific or product promotional material is forbidden

=A0 at I= BIS Summits.=A0 We strongly advise that the presentations be

= =A0 submitted by the deadline for review. The IBIS Open Forum reserves=

=A0 the right to stop or reject a scheduled presentation that has n= ot

=A0 been reviewed.

 

<= p class=3DMsoPlainText>AGENDA

 

=A0 The agenda includes presentations, discu= ssions, breaks and

=A0 refreshments. This will be developed as = presentation proposals

=A0 are received.

<= p class=3DMsoPlainText> = ;

 

LIST OF NEARBY HOTELS

 <= /o:p>

=A0 Use a search engine to find nearby hotels

<= p class=3DMsoPlainText> = ;

------------------------------------------------------------------= - ----

 

&= nbsp;

--

Bob Ross

Teraspeed Consulting Gr= oup, LCC

http://www.teraspeed.com

bob@teraspeeed.com

Direct : 503-246-8048

Teraspeed Labs: 971-279-5325

Headqu= arters: 401-284-1827

 

Teraspeed is a registered service mark of Tera= speed Consulting Group LLC

 = ;


--=20
This message has been scanned for viruses and
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believed to be clean. - ------=_NextPart_000_0001_01CE4066.03723020-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 4 Apr 2013 10:59:07 -0700 From: Sam Chitwood Subject: [IBIS-Users] RE: Validation of IBIS 5.0 model with package parasitics - --_000_A66C83F04198D24E82D005D1C2D51A300B2B6E8A20MAILSJ4global_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Randy and Rinsha, The I/O model is three terminals (if we ignore the clamps for a moment). C= omposite Current forces the power net current. The classic IBIS algorithm = forces the I/O pin's current. So the pull down net's current has to be der= ived to make the net sum be zero. Thus, there is no need for a return net = current table. (Your core PDN noise likely has to be modeled with another = technique.) I typically see customers solve this correlation issue by switching from a = partial-based parasitic model to a loop-based / S-parameter approach, after= the limitations above are understood. Thanks, Sam From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Randy Wol= ff (rrwolff) Sent: Thursday, April 04, 2013 11:59 AM To: Rinsha Reghunath; ibis@eda.org; ibis-users@eda.org Subject: [IBIS] RE: Validation of IBIS 5.0 model with package parasitics Hi Rinsha, I've run across this same issue recently with an IBIS 5.0 power aware model= I created. I believe the problem is related to not having [Composite Curr= ent] waveforms for the ground currents. The DDR4 memory device I modeled i= ncludes two supplies (VDD (core) and VDDQ (IO)) and two grounds (VSS (core)= and VSSQ (IO)). EDA software might assume that pre-driver currents for VC= CQ are balanced for VSSQ, but this is not totally valid. When significant = parasitics are added to VSSQ, the correlation gets bad. What I've found he= lps me is that VSS and VSSQ are shorted on the die. The result is that the= package impedance for VSSQ becomes quite small since it is now in parallel= with VSS (which typically has low inductance in the package). With a smal= l package impedance on VSSQ/VSS, the correlation is pretty good to Spice. It may be worth starting a conversation about whether [Composite Current] n= eeds to be expanded to include modeling of ground currents. Regards, Randy Randy Wolff Micron Technology From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf = Of Rinsha Reghunath Sent: Thursday, April 04, 2013 5:39 AM To: ibis@eda.org; ibis-users@eda.org Subject: [IBIS-Users] Validation of IBIS 5.0 model with package parasitics Hi all, I am trying to validate an IBIS 5.0 model at 500Mbps with package parasitic= s (R, L, C for supply, ground and pad) and on-die RC decoupling. The issue = is that the I-T waveforms are not matching when I add inductance to the gro= und terminal. When I remove the inductance on the ground terminal keeping t= he rest of the setup same, the I-T waveforms correlate. Has anyone come acr= oss this issue or any suggestions on rectifying the same? Thanks & Regards, Rinsha - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --_000_A66C83F04198D24E82D005D1C2D51A300B2B6E8A20MAILSJ4global_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi Randy and = Rinsha,

 

The I/O model is three terminals (if we ignor= e the clamps for a moment).  Composite Current forces the power net cu= rrent.  The classic IBIS algorithm forces the I/O pin’s current.=   So the pull down net’s current has to be derived to make the n= et sum be zero.  Thus, there is no need for a return net current table= .  (Your core PDN noise likely has to be modeled with another techniqu= e.)

 

I typically see customers solve this correlation = issue by switching from a partial-based parasitic model to a loop-based / S= - -parameter approach, after the limitations above are understood.=

 

Thanks,

Sam=

 

 

=  

From: owner-ibis@ed= a.org [mailto:owner-ibis@eda.org] On Behalf Of Randy Wolff (rrwolff)=
Sent: Thursday, April 04, 2013 11:59 AM
To: Rinsha Reg= hunath; ibis@eda.org; ibis-users@eda.org
Subject: [IBIS] RE: Vali= dation of IBIS 5.0 model with package parasitics

 

Hi Rinsha,

 

I’ve run across this same issue = recently with an IBIS 5.0 power aware model I created.  I believe the = problem is related to not having [Composite Current] waveforms for the grou= nd currents.  The DDR4 memory device I modeled includes two supplies (= VDD (core) and VDDQ (IO)) and two grounds (VSS (core) and VSSQ (IO)).  = ;EDA software might assume that pre-driver currents for VCCQ are balanced f= or VSSQ, but this is not totally valid.  When significant parasitics a= re added to VSSQ, the correlation gets bad.  What I’ve found hel= ps me is that VSS and VSSQ are shorted on the die.  The result is that= the package impedance for VSSQ becomes quite small since it is now in para= llel with VSS (which typically has low inductance in the package).  Wi= th a small package impedance on VSSQ/VSS, the correlation is pretty good to= Spice.

 

It may be worth starting a conversation about whether [Composite C= urrent] needs to be expanded to include modeling of ground currents.

&nbs= p;

Regar= ds,

Randy

 

Randy Wolff

Micron Technology

 

From: owner-ibis-users@eda.org [mailto:owner-ibis-users= @eda.org] On Behalf Of Rinsha Reghunath
Sent: Thursday, Ap= ril 04, 2013 5:39 AM
To: ibis@eda.org; ibis-users@eda.org
S= ubject: [IBIS-Users] Validation of IBIS 5.0 model with package parasiti= cs

 <= /p>

Hi all,

&nb= sp;

I am trying to validate an IBIS 5.0 model= at 500Mbps with package parasitics (R, L, C for supply, ground and pad) an= d on-die RC decoupling. The issue is that the I-T waveforms are not matchin= g when I add inductance to the ground terminal. When I remove the inductanc= e on the ground terminal keeping the rest of the setup same, the I-T wavefo= rms correlate. Has anyone come across this issue or any suggestions on rect= ifying the same?

 

Thanks & Regards,

Rinsha


--
This message has been sca= nned for viruses and
dangerous content by MailScanner, and is
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--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --_000_A66C83F04198D24E82D005D1C2D51A300B2B6E8A20MAILSJ4global_-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 6 May 2013 10:48:57 -0700 From: "Bob Ross" Subject: [IBIS-Users] European IBIS Summit Agenda - May 15, 2013 This is a multipart message in MIME format. - ------=_NextPart_000_00AE_01CE4A47.4F9AEDD0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable All: =20 The 16th European IBIS Summit is on Wednesday afternoon and follows the IEEE Workshop on Signal and Power Integrity: =20 http://www.spi2013.org/ =20 Below is the meeting agenda. The IBIS meeting is free. If you plan to attend, please register with Lance Wang as noted at the end. =20 Lance Wang IO Methodology =20 - ------------------------------------------------------------------ =20 AGENDA, EUROPEAN IBIS SUMMIT MEETING Wednesday, May 15, 2013 =20 Hyatt Regency Paris Etoile (NOTE: formerly Hotel Concorde La Fayette) 3, Place du G=E9n=E9ral Koenig=20 Paris, France, 75017 =20 http://tinyurl.com/bna6xrz =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 Room: Pissaro-Cezanne (Check at Entrance) =20 - ------------------------------------------------------------------ =20 13:00 SIGN IN =20 13:15 WELCOME AND INTRODUCTIONS Lance WANG, IO Methodology, IBIS Vice Chair, USA =20 13:30 IBIS Modeling for Load Dependent Current Model Differential Driver Lance WANG, IO Methodology, USA =20 13:50 X2IBIS: Using X-parameters to Generate IBIS Models Thomas COMBERIATE and Jose SCHUTT-AINE University of Illinois, USA (Presented by Thomas COMBERIATE, USA) =20 14:30 Thevenin's Theorem Revisited. A New Approach to IC Buffer Modeling and It's Relation to IBIS Igor STIEVANO*, Cherif DIOUF**, Mihai TELESCU**, N. TANGUY**, and Flavio CANAVERO* *Politecnico di Torino, Italy;=20=20=20=20=20=20 **Universit=E9 Europ=E9enne de Bretagne, Universit=E9 de Brest, France (Presented by Mihai TELESCU, France)=20=20=20=20=20=20 =20 15:00 A Novel Two-Port Behavioral Model for I/O Buffer Overclocking Simulation Wael DGHAIS, University of Averio, Institue of Telecommunications, Portugal =20 15:30 BREAK (15 Minutes) =20 15:45 Novel Extraction of Table-Based I-Q Behavioral Model for High-Speed Digital Buffers/Drivers Wael DGHAIS, University of Averio, Institue of Telecommunications, Portugal =20 16:15 Interconnect Modeling Update - EMD Specification Randy WOLFF, Micron Technology, USA =20 16:45 Ibischk5 Specification and Parser Bob ROSS* and Mike LABONTE**, *Teraspeed Consulting Group and **Signal Integrity Software (SiSoft), USA (Presented by Anders EKHOLM, Ericsson, Sweden) =20 17:30 DISCUSSION AND CLOSING REMARKS Lance WANG, IO Methodology, USA =20 18:00 END OF MEETING =20 - ------------------------------------------------------------------ =20 REGISTRATION INFORMATION =20 People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: =20 Name: E-mail address: Company: Telephone: =20 Send to: =20 Lance WANG (lwang@iometh.com) =20 SPONSORS: =20 Micron Technology and Zuken SPI CONFERENCE INFORMATION AND TRAVEL DIRECTIONS =20 See http://www.spi2013.org/ for travel directions, IBIS meeting hotel and other information. =20 - ------------------------------------------------------------------ =20 - -- Bob Ross Teraspeed Consulting Group, LCC http://www.teraspeed.com bob@teraspeeed.com Direct : 503-246-8048 Teraspeed Labs: 971-279-5325 Headquarters: 401-284-1827 =20 Teraspeed is a registered service mark of Teraspeed Consulting Group LLC =20 =20 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_00AE_01CE4A47.4F9AEDD0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

All:

 

The 16th= European IBIS Summit is on Wednesday afternoon and

follows the= IEEE Workshop on Signal and Power Integrity:

 =

 

Below is the m= eeting agenda.=A0 The IBIS meeting is free.=A0 If

you plan to a= ttend, please register with Lance Wang as noted at

the end.

 

Lance Wang

IO Methodology

-----------------------------------------------------= - -------------

 

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0 AGENDA, EUROPEAN IBIS SUMMIT MEETING

<= p class=3DMsoPlainText>=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 Wednesday, May 15, 2= 013

 

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0 Hyatt Regency Paris Etoile

=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0 (NOTE: formerly Hotel Concorde La Fayette)

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 3, Place = du G=E9n=E9ral Koenig

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0Paris, France, 75017<= /p>

&= nbsp;

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 h= ttp://tinyurl.com/bna6xrz

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0

=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0Room= : Pissaro-Cezanne (Check at Entrance)

 <= /p>

------= - ------------------------------------------------------------

 

13:00=A0 SIGN IN

 

<= p class=3DMsoPlainText>13:15=A0 W= ELCOME AND INTRODUCTIONS

=A0=A0=A0=A0=A0=A0 Lance WANG, IO Meth= odology, IBIS Vice Chair, USA

=  

13:30=A0 IBIS = Modeling for Load Dependent Current Model Differential

=A0=A0= =A0=A0=A0=A0 Driver

=A0=A0=A0=A0=A0=A0 Lance WANG, IO Methodolo= gy, USA

 

13:50=A0 X2IBIS: Using X-parameters = to Generate IBIS Models

=A0=A0=A0=A0=A0=A0 Thomas COMBERIATE an= d Jose SCHUTT-AINE

=A0=A0=A0=A0=A0=A0 University of Illinois, U= SA

=A0=A0=A0=A0=A0=A0 (Presented by Thomas COMBERIATE, USA)

 

14:30=A0 Thevenin's Theorem Revisited. A New Ap= proach to IC Buffer

=A0=A0=A0=A0=A0=A0 Modeling and It's Relati= on to IBIS

=A0=A0=A0=A0=A0=A0 Igor STIEVANO*, Cherif DIOUF**, M= ihai TELESCU**, N. TANGUY**,

<= span style=3D'font-family:"Courier New"'>=A0=A0=A0=A0=A0=A0 and Flavio CANA= VERO*

=A0=A0=A0=A0=A0=A0 *Politecnico di Torino, Italy;=A0=A0= =A0=A0=A0

=A0=A0=A0=A0=A0=A0=A0**Universit=E9 Europ=E9enne de = Bretagne, Universit=E9 de Brest,

=A0=A0=A0=A0=A0=A0 France=

=A0=A0=A0=A0=A0=A0 (Presented by Mihai TELESCU, France)=A0=A0=A0=A0= =A0

 

15:00=A0 A Novel Two-Port Behavioral Mo= del for I/O Buffer

=A0=A0=A0=A0=A0=A0 Overclocking Simulation

=A0=A0=A0=A0=A0=A0 Wael DGHAIS,

=A0=A0=A0=A0=A0=A0 U= niversity of Averio, Institue of Telecommunications,

<= p class=3DMsoPlainText>=A0=A0=A0= =A0=A0=A0 Portugal

 

15:30=A0 BREAK (15 Minute= s)

 

15:45=A0 Novel Extraction of Table-Based = I-Q Behavioral Model for

=A0=A0=A0=A0=A0=A0 High-Speed Digital = Buffers/Drivers

=A0=A0=A0=A0=A0=A0 Wael DGHAIS,

=A0= =A0=A0=A0=A0=A0 University of Averio, Institue of Telecommunications,<= /o:p>

=A0=A0=A0=A0=A0=A0 Portugal

 

=

16:15=A0 = Interconnect Modeling Update - EMD Specification

=A0=A0=A0=A0= =A0=A0 Randy WOLFF, Micron Technology, USA

 

1= 6:45=A0 Ibischk5 Specification and Parser

=A0=A0=A0=A0=A0=A0 Bo= b ROSS* and Mike LABONTE**,

=A0=A0=A0=A0=A0=A0 *Teraspeed Consu= lting Group and

=A0=A0=A0=A0=A0=A0 **Signal Integrity Software = (SiSoft), USA

=A0=A0=A0=A0=A0=A0 (Presented by Anders EKHOLM, E= ricsson, Sweden)

 

17:30=A0 DISCUSSION AND C= LOSING REMARKS

=A0=A0=A0=A0=A0=A0 Lance WANG, IO Methodology, U= SA

 

18:00=A0 END OF MEETING=

=  

-------------------------------------------------------------= - -----

 

REGISTRATION INFORMATION

<= o:p> 

People involved in IBIS Model development, EDA tool devel= opment, and

digital circuit design are invited to participate t= o the Summit

meeting. If you plan to participate, please regist= er with the

information below:

 

= =A0=A0 Name:

=A0=A0 E-mail address:

=A0=A0 Company:=

=A0=A0 Telephone:

 

Send to:=

 

=A0=A0 Lance WANG (lwang@iometh.com)<= /span>

 

SPONSORS:

=  

=A0=A0 Micron = Technology and Zuken

SPI CONFERENCE INFORMATION A= ND TRAVEL DIRECTIONS

 

=A0=A0 See http://www.s= pi2013.org/ for travel directions,

=A0=A0 IBIS meeting hotel an= d other information.

 

-----------------------= - -------------------------------------------

 

--<= /p>

Bob Ross

T= eraspeed Consulting Group, LCC

http:/= /www.teraspeed.com

bob@teraspeeed.com=

Direct : 503-246-8048

=

Teraspeed Labs: 971-279-5325

Headquarters: 401-284-1827

 

Teraspeed is a registere= d service mark of Teraspeed Consulting Group LLC

 

 <= /p>


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_00AE_01CE4A47.4F9AEDD0-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 27 Aug 2013 17:48:44 +0000 From: "Muranyi, Arpad" Subject: [IBIS-Users] RE: [IBIS] SI_location / Timing_Location - --_000_EB55FD6CF8C21444BE032D68DDA5FB998BA7701DNAMBX02mgcmento_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks for all who responded so far. I got the general idea, but what I am still missing is a list of parameters or subparameters in [Model] or [Model Spec] (or any other keyword) on which these two parameters "operate". Do we have an unambiguous answer to that by reading the IBIS specification? Thanks, Arpad =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D From: Scott McMorrow [mailto:scott@teraspeed.com] Sent: Tuesday, August 27, 2013 12:39 PM To: Robert Haller Cc: Aubrey Sparkman; Muranyi, Arpad; IBIS; IBIS-users Subject: Re: [IBIS] SI_location / Timing_Location Actually, Si_location and Timing_location go back to 1997 and were introduc= ed by Bob Ross of Interconnectix (pre-Mentor) http://www.eda.org/ibis/birds/bird43.txt Timing_location may also need to be changed to die for large FPGA type devi= ces, because of large non-monotonic signals at the pins. On Tue, Aug 27, 2013 at 1:30 PM, Robert Haller > wrote: I think the SiSoft guys probably pushed for this a while ago. Their software can do chip to chip timing either at pin or pad (on either end of transmission line). Usually one performs static timing from pin to pin because then there is no double counting when using data sheet timing specs. But if you are designing the silicon and the package, there are good reasons to perform timing pad to pad when you are trying to shave picoseconds. Regards Bob - -----Original Message----- From: owner-ibis@eda.org [mailto:owner-ibis@eda.= org] On Behalf Of Aubrey Sparkman Sent: Monday, August 26, 2013 2:19 PM To: Muranyi, Arpad Cc: IBIS; IBIS-users Subject: Re: [IBIS] SI_location / Timing_Location I have used these switches, though I'm not sure I gave them different values. Possible scenario... Interface specs timing at pin, but I want to make sure edges are monotonic at the silicon. Just a though. Aubrey Sparkman Sent from my iPhone On Aug 26, 2013, at 11:44 AM, "Muranyi, Arpad" > wrote: > Hello IBIS experts, > > Someone asked me the question whether Si_location and Timing_Location > can have two different values because they have an IBIS file which > does that. > > In attempt to answer their question, I searched the IBIS specification > for Si_location and only found this sentence on pg. 16 (in v5.1): > > "Si_location and Timing_location are optional and specify where the Signal Integrity and Timing measurements are made for the component. Allowed values for either subparameter are "Die" or "Pin". The default location is at the "Pin"." > > I found no other occurrences of "Si_location" or "Timing_location" > in the entire specification, i.e. their meaning, usage and purpose are > not defined. Or am I missing something? > > Going back to the original question, does it make sense to have two > different values for these two parameters? > > Thanks, > > Arpad > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --_000_EB55FD6CF8C21444BE032D68DDA5FB998BA7701DNAMBX02mgcmento_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Thanks for all who responded so far.

 

I got the general idea, but what I am still mi= ssing

is a list of parameters or subparameters in [M= odel]

or [Model Spec] (or any other keyword) on whic= h these

two parameters “operate”.  Do= we have an unambiguous

answer to that by reading the IBIS specificati= on?

 

Thanks,

 

Arpad

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

 

From: Scott Mc= Morrow [mailto:scott@teraspeed.com]
Sent: Tuesday, August 27, 2013 12:39 PM
To: Robert Haller
Cc: Aubrey Sparkman; Muranyi, Arpad; IBIS; IBIS-users
Subject: Re: [IBIS] SI_location / Timing_Location<= /p>

 

Actually, Si_location and Timing_location go back to= 1997 and were introduced by Bob Ross of Interconnectix (pre-Mentor)

 

 

Timing_location may also need to be changed to die f= or large FPGA type devices, because of large non-monotonic signals at the p= ins.

 

 

 

On Tue, Aug 27, 2013 at 1:30 PM, Robert Haller <<= a href=3D"mailto:rhaller@enterasys.com" target=3D"_blank">rhaller@enterasys= .com> wrote:

I think the SiSoft guys probably pushed for this a w= hile ago. Their
software can do chip to chip timing either at pin or pad (on either end of<= br> transmission line). Usually one performs static timing from pin to pin
because then there is no double counting when using data sheet timing
specs. But if you are designing the silicon and the package, there are
good reasons to perform timing pad to pad when you are trying to shave
picoseconds.
Regards
Bob

- -----Original Message-----
From: owner-ibis@eda.org [mailto:= owner-ibis@eda.org] On Behalf Of = Aubrey
Sparkman
Sent: Monday, August 26, 2013 2:19 PM
To: Muranyi, Arpad
Cc: IBIS; IBIS-users
Subject: Re: [IBIS] SI_location / Timing_Location

I have used these switches, though I'm not sure I gave them different
values.

Possible scenario...   Interface specs timing at pin, but I want to ma= ke
sure edges are monotonic at the silicon.

Just a though.

Aubrey Sparkman

Sent from my iPhone

On Aug 26, 2013, at 11:44 AM, "Muranyi, Arpad" <Arpad_Muranyi@mentor.com>
wrote:

> Hello IBIS experts,
>
> Someone asked me the question whether Si_location and Timing_Location<= br> > can have two different values because they have an IBIS file which
> does that.
>
> In attempt to answer their question, I searched the IBIS specification=
> for Si_location and only found this sentence on pg. 16 (in v5.1):
>
> "Si_location and Timing_location are optional and specify where t= he
Signal Integrity and Timing measurements are made for the component.
Allowed values for either subparameter are "Die" or "Pin&quo= t;. The default
location is at the "Pin"."
>
> I found no other occurrences of "Si_location" or "Timin= g_location"
> in the entire specification, i.e. their meaning, usage and purpose are=
> not defined.  Or am I missing something?
>
> Going back to the original question, does it make sense to have two
> different values for these two parameters?
>
> Thanks,
>
> Arpad
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D


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