To All:

The I= BIS Open Forum is holding an Asian IBIS Summit Meeting in=

Shang= hai, China on Friday, November 15, 2013.

Sev= eral companies listed below are co-sponsoring this large event

= to be held again at the Parkyard Hotel, Shanghai.

We encourage technical contributions from Asia.

&nbs= p;

For travel consideration, two other Asian IBIS Summits follow thi= s

event:

Taipei, Taiwan, = Tuesday, November 19, Sherwood Hotel

Yokohama, Japan, Fr= iday, November 22, Pacifico Yokohama

Announc= ements for these Summits will be issued later.

IO Methodology Inc.

Teraspeed Consulting Group

---------------------------------------------------------------------= - -

&= nbsp; ASI= AN IBIS SUMMIT (SHANGHAI)

&= nbsp; &nbs= p; THIRD CALL FOR

= PARTICIPATION = AND PRESENTATIONS

--------------------------------------------= - --------------------------

http://www.eda.org/ibis/summits/nov1= 3a/announcement_chinese.pdf

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

&n= bsp; A S I A N = I B I S S U M M I T ( S H A N G H A I )<= /span>

Time/Date: Friday, November 15, 2013, 8:00 AM to = 5:30 PM

&= nbsp; Meeting starts at 9:00 AM

<= /p>

Locati= on: Parkyard Hotel Shanghai

= ; 699 Bibo Road=

= ; Zhangjiang Hi= - -Tech Park

&nbs= p; Shanghai 201203

&n= bsp; P.R. China

Content: &nb= sp; Presentations and Discussions

<= p class=3DMsoPlainText>Purpose:&n= bsp; Solicit and exchange IBIS and interconnect model related

&nbs= p; information and ideas.

Primary Sponsor:<= o:p>

&nb= sp; Huawei Technologies

Co-sponsors (in alph= abetical order):

&n= bsp; Agilent Technologies

= ; ANSYS

&= nbsp; Cadence Design = Systems

&= nbsp; Intel Corporation

= &nb= sp; IO Methodology

&n= bsp; Synopsys

&= nbsp; others TB= D

Cost: = FREE, including refreshments and buffet lunch

= Contact us for details regarding sponsorship.=

BACKGROUND

= We have held seven successful meetings in Shenzhen, Shanghai and

Chinese and foreign high technology companies = operate. These

events are archived along wit= h all our other Summits:

= ; http://www.eda.org/pub/ibis/summits/

the local experts and to learn of regional c= oncerns.

CONFERENCE LANGUAGE

The conference language is English, but we wil= l plan for technical

translations in English and M= andarin. So presenters can optionally

deli= ver in Mandarin as long as an English version of the material

= is available.

IBIS SUMMIT<= o:p>

This meeting will be conducted = as a formal IBIS Summit Meeting.

Presentations wil= l be archived in an electronic format on our

Summ= its site, and minutes of the meeting will be issued. However,

no formal decisions requiring votes will be planned.=

CALL FOR PARTICIPANTS

People involved in IBIS and interconnect model developmen= t, EDA

tool development, and digital circuit desig= n are invited to

participate in the Summit meeti= ng. If you plan to participate,

please regis= ter using the information below (in English):

E-mai= l address:

= Company:=

Top-level Web Link:=

Country:

Send to BOTH:

&= nbsp; Lance Wang, IO Methodology Inc. &n= bsp; lwang@iometh.com

Bob = Ross, Teraspeed Consulting Group bob@teraspeed.com

SIGNUP DEADLINE: N= ovember 8, 2013

CALL FOR PRESENTATIONS<= /o:p>

We are seeking presentations from in= dividuals who have IBIS and

interconnect modeling = experiences or issues. If we have to

select = presentations for the number of time slots available, we<= /p>

= will give preferential consideration to presentations from Asia.

Presentation Format: L= CD Projection from meeting laptop computer

&= nbsp; Time: &nbs= p; 15-30 Minutes including questi= ons

Electronic Archival: &= nbsp; All presentations will uploaded to our

= ; &n= bsp; public IBIS= Summit archives

Electronic F= ormat: Power Point or Acrobat

&nbs= p;

Presentation Booklet: Available at the meeting= for all attendees

Presentation= Deadline: October 11, 2013 to produce the presentation

&= nbsp; &nbs= p; bookle= t for the meeting

If you plan = a presentation, please ADD to the above registration

<= p class=3DMsoPlainText> &nbs= p; information:

Tit= le of Presentation:

= Estimated Time:

(30 min= utes or less)

We will notify yo= u of acceptance and may follow up with questions

w= hen we form the program agenda.

= Note: Vendor promotional or business information is prohibited.=

can be in Mandarin.

<= /o:p>

Submissions from Asia are encouraged along with other s= ubmissions

world-wide. Topics may include be= havioral modeling of buffers,

= interconnects or oth= er system components.

AGENDA

8:15 - 9:00 Vendor table set= up and tables

8:30 - 9:00 Sign i= n

9:00 - 12:00 Presentations

13:30 - 17:00 Presentations

<= p class=3DMsoPlainText> = ;

The specific agenda is being developed. We expe= ct nine or ten

presentations covering a range of i= ssues from existing customer

<= span style=3D'font-family:"Courier New"'> experiences, existing= clarifications and some future technical

directio= ns in IBIS.

Several major IBIS = Committee presentations from IBIS officers or

acti= ve members are planned.

Several= presentations on IBIS applications and behavioral modeling

&nb= sp; issues, including interconnects and system components, are expect= ed

from co-sponsor companies and/or their customer= s.

LIST OF NEARBY HOTELS AND TRAVEL RULES

Hotels in all price ranges can = be found through internet searches.

&n= bsp; Comply with your travel rules, such as indicated in the link

us as a sign-up comment if you = need assistance. Visas, if needed,

should fa= ll in the visit/business category:

&nb= sp; http://travel.state.gov/travel/cis_pa_tw/cis/cis_1089.html<= o:p>

--------------------------------------------= - ---------------------

Bob Ross

Terasp= eed Consulting Group, LCC

http://www.= teraspeed.com

bob@teraspeeed.com=

Direct : 503-246-8048

Teraspeed Labs: 971-279-5325

Headquarters: 401-284-1827

Teraspeed is a registered ser= vice mark of Teraspeed Consulting Group LLC

--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_001F_01CEBB88.E6D5F110-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 18 Sep 2013 11:39:14 -0700 From: "Tom Dagostino" Subject: RE: [IBIS-Users] {Spam?} {Filename?} LVDS IBIS model - simulation issue This is a multipart message in MIME format. - ------=_NextPart_000_08F6_01CEB463.B3EDEF40 Content-Type: multipart/alternative; boundary="----=_NextPart_001_08F7_01CEB463.B3EDEF40" - ------=_NextPart_001_08F7_01CEB463.B3EDEF40 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Andrey I've modeled a lot of LVDS buffers in the past and this is definitely the strangest looking pulldown IV curve I've ever seen. And as Arpad says it does not at all look like a reasonable result. First, why are you loading your LVDS buffer with a 50 Ohm differential termination? Most I have seen are looking for 100Ohms. Have you inverted the pulldown's polarity? I would also expect to see the pulldown curve to have positive current between ground and Vdd. LVDS buffers have a feedback loop in them so stabilize the Vcm of the buffer. Usually this only affect the pullup IV curve but sometimes only the pulldown. This makes extracting the IV characteristics of the controlled device difficult. The feedback is fighting the curve tracer that is measuring the IV characteristics. While you are doing the IV sweep you are by definition changing Vcm and the feedback is trying to correct for this. BTW, Ip = -In. One is sourcing current and the other sinking. The sourcing should have negative currents and the sinking positive. Tom Dagostino Teraspeed Labs 9999 SW Wilshire St. Suite 102 Portland, OR 97225 USA 971-279-5325 Office 971-279-5326 FAX 503-430-1065 Cell tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 16 Stormy Brook Road Falmouth, ME 04105 401-284-1827 From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Muranyi, Arpad Sent: Wednesday, September 18, 2013 8:31 AM To: ibis-users@eda.org Subject: RE: [IBIS-Users] {Spam?} {Filename?} LVDS IBIS model - simulation issue Andrey, I am not sure that your PD I-V curve is correct. First of all, it should have a positive sign, but its shape doesn't look right either. Can you describe how you generated these I-V curves? Thanks, Arpad ======================================================== From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Andrey Babintsev Sent: Wednesday, September 18, 2013 9:38 AM To: ibis-users@eda.org Subject: Re: [IBIS-Users] {Spam?} {Filename?} LVDS IBIS model - simulation issue Re-sending with updated attachment Hi, I am making IBIS models for LVDS (low voltage differential signal) IO buffer. To model an LVDS buffer I created the following test circuit, assigned the generated IBIS model to both buffers, set one buffer as inverted output. Problem: In the image below the YELLOW waveform is what I saw and the PURPLE waveform is what I expected to see. YELLOW = IBIS model PURPLE = Spice ( reference ) model Here is combined pullUp (yellow) and pullDown (green) IV curves (actually it is spice curves from which IV tables were derived): Lets assume that simulator tries to find operational point for LVDS buffer driving high. Then for the non-inverted buffer a point (Vp, Ip) will be taken from pullUp table, for the inverted buffer a point (Vn, In) from pullDown table, the following conditions should be satisfied: Ip = In, Vp - Vn = Ip*50. On the image above it is seen that there are 2 points satisfying the condition: Vp =~ 1.45V and Vp =~ 2.2V. Seems that something like that happened during simulation and simulator got to the second point. (BTW, there are 60 points for the region 0.9 - 1.6V and 10 points for the region 1.6-2.5V in the IBIS model IV tables). Question: What can be done to resolve this situation? Should IV tables or another IBIS structures be modified and how? I am making ibis ver. 4.2 models. Thanks, Andrey On 09/18/2013 06:33 PM, Andrey Babintsev wrote: Warning: This message has had one or more attachments removed (fail.min.png). Please read the "EDA-Attachment-Warning.txt" attachment(s) for more information. Hi, I am making IBIS models for LVDS (low voltage differential signal) IO buffer. To model an LVDS buffer I created the following test circuit, assigned the generated IBIS model to both buffers, set one buffer as inverted output. Problem: In the image below the YELLOW waveform is what I saw and the PURPLE waveform is what I expected to see. YELLOW = IBIS model PURPLE = Spice ( reference ) model Here is combined pullUp (yellow) and pullDown (green) IV curves (actually it is spice curves from which IV tables were derived): Lets assume that simulator tries to find operational point for LVDS buffer driving high. Then for the non-inverted buffer a point (Vp, Ip) will be taken from pullUp table, for the inverted buffer a point (Vn, In) from pullDown table, the following conditions should be satisfied: Ip = In, Vp - Vn = Ip*50. On the image above it is seen that there are 2 points satisfying the condition: Vp =~ 1.45V and Vp =~ 2.2V. Seems that something like that happened during simulation and simulator got to the second point. (BTW, there are 60 points for the region 0.9 - 1.6V and 10 points for the region 1.6-2.5V in the IBIS model IV tables). Question: What can be done to resolve this situation? Should IV tables or another IBIS structures be modified and how? I am making ibis ver. 4.2 models. Thanks, Andrey - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_001_08F7_01CEB463.B3EDEF40 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

= Andrey

<= /o:p>

I’ve modeled a lot of LVD= S buffers in the past and this is definitely the strangest looking pulldown= IV curve I’ve ever seen. And as Arpad says it does not at all = look like a reasonable result.

First, why are= you loading your LVDS buffer with a 50 Ohm differential termination? = Most I have seen are looking for 100Ohms.

Ha= ve you inverted the pulldown’s polarity? I would also expect to= see the pulldown curve to have positive current between ground and Vdd.

LVDS buffers have a feedback loop in them so st= abilize the Vcm of the buffer. Usually this only affect the pullup IV= curve but sometimes only the pulldown. This makes extracting the IV = characteristics of the controlled device difficult. The feedback is f= ighting the curve tracer that is measuring the IV characteristics. Wh= ile you are doing the IV sweep you are by definition changing Vcm and the f= eedback is trying to correct for this.

BTW,= Ip =3D -In. One is sourcing current and the other sinking. The= sourcing should have negative currents and the sinking positive.

Tom Dagostino

Tera= speed Labs

9999 SW Wilshir= e St.

Suite 102=

Portland, OR 97225=

USA

971-279-5= 325 Office

971-279-5= 326 FAX

503-= 430-1065 Cell

tom@teraspeed.com

www.teraspeed.com

<= p class=3DMsoNormal>Teraspeed Consulting Group LLC=

16 Stormy Brook Road

Falmouth, ME 04105

401-284-1827

From: owner-ibis-users@eda.org [mailto:ow= ner-ibis-users@eda.org] On Behalf Of Muranyi, Arpad
Sent: = Wednesday, September 18, 2013 8:31 AM
To: ibis-users@eda.org
<= b>Subject: RE: [IBIS-Users] {Spam?} {Filename?} LVDS IBIS model - simul= ation issue

&nbs= p;

Andrey,

I am not sure that your PD I-V curve is correct.=

First of all, it should have a po= sitive sign, but

its shape doesn’t look rig= ht either.

Can= you describe how you generated these I-V curves?

Thanks,

&n= bsp;

Arpad

<= span style=3D'font-size:10.0pt;font-family:"Courier New"'>=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D

<= /o:p>

From:= owner-ibis-users@= eda.org [mailto:owner-ibis-= users@eda.org] On Behalf Of Andrey Babintsev
Sent: Wed= nesday, September 18, 2013 9:38 AM
To: ibis-users@eda.org
Subject: Re: [IBIS-Users] {Spa= m?} {Filename?} LVDS IBIS model - simulation issue

Re-sending with updated attachment

Hi,

I am making IBIS mod= els for LVDS (low voltage differential signal) IO buffer.
To model an L= VDS buffer I created the following test circuit, assigned the generated IBI= S model to both buffers, set one buffer as inverted output.

Problem:
In the image below the YELLOW = waveform is what I saw and the PURPLE waveform is what I expected to see. <= br>
YELLOW =3D IBIS model
PURPLE =3D Spi= ce ( reference ) model

Here is combined pullUp (yellow) and pullDown= (green) IV curves (actually it is spice curves from which IV tables were d= erived):

Lets assume that simulator= tries to find operational point for LVDS buffer driving high. Then for the= non-inverted buffer a point (Vp, Ip) will be taken from pullUp table, for = the inverted buffer a point (Vn, In) from pullDown table, the following con= ditions should be satisfied: Ip =3D In, Vp - Vn =3D Ip*50. On the image abo= ve it is seen that there are 2 points satisfying the condition: Vp =3D~&nbs= p; 1.45V and Vp =3D~ 2.2V. Seems that something like that happened during s= imulation and simulator got to the second point. (BTW, there are 60 points = for the region 0.9 - 1.6V and 10 points for the region 1.6-2.5V in the IBIS= model IV tables).

Question:
What can be done to resolve t= his situation? Should IV tables or another IBIS structures be modified and = how? I am making ibis ver. 4.2 models.

Thanks,
Andrey
<= br>

On 09/18/2013 06:33 PM, Andrey Babintsev wrote:

Warning: This message has had one or more attach= ments removed (fail.min.png). Please read the "EDA-Attachment-Warning.= txt" attachment(s) for more information.
Hi,

I am making IBIS models for LVDS (low voltage differen= tial signal) IO buffer.
To model an LVDS buffer I created the following= test circuit, assigned the generated IBIS model to both buffers, set one b= uffer as inverted output.

Problem:
In the image below the YELLOW waveform is what I saw and t= he PURPLE waveform is what I expected to see.

YELLOW =3D IBIS model
PURPLE =3D Spice ( reference ) mode= l

Here is combined pullUp (yellow) and pullDown (green) IV curves (a= ctually it is spice curves from which IV tables were derived):

Lets assume that simulator tries to find= operational point for LVDS buffer driving high. Then for the non-inverted = buffer a point (Vp, Ip) will be taken from pullUp table, for the inverted b= uffer a point (Vn, In) from pullDown table, the following conditions should= be satisfied: Ip =3D In, Vp - Vn =3D Ip*50. On the image above it is seen = that there are 2 points satisfying the condition: Vp =3D~ 1.45V and V= p =3D~ 2.2V. Seems that something like that happened during simulation and = simulator got to the second point. (BTW, there are 60 points for the region= 0.9 - 1.6V and 10 points for the region 1.6-2.5V in the IBIS model IV tabl= es).

Question:
What can be done to resolve this situation?= Should IV tables or another IBIS structures be modified and how? I am maki= ng ibis ver. 4.2 models.

Thanks,
Andrey

--
This message has been scanned for = viruses and
dangerous content by MailScanner, and is
believed to be clean.
=

--
This messa= ge has been scanned for viruses and
dangerous content by MailScanner, and is
believed to b= e clean.

--=20
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Meeting in Taiwan. We are meeting again in Taipei on Tuesday, November 19, 2013. Several companies listed below are co-sponsoring this major event to be held at the Sherwood Hotel in Taipei. Like in previous years, We are planning for many attendees. We encourage technical contributions from Asia. Other Asian IBIS Summit meetings are scheduled for: Shanghai, P.R. China, Friday November 15, Parkyard Hotel Yokohama, Japan, Friday, November 22, Pacifico Yokohama Lance Wang IO Methodology Bob Ross Teraspeed Consulting Group - ---------------------------------------------------------------------- ASIAN IBIS SUMMIT (TAIPEI) THIRD CALL FOR PARTICIPATION AND PRESENTATIONS - ---------------------------------------------------------------------- A S I A N I B I S S U M M I T ( T A I P E I ) Time/Date: Tuesday, November 19, 2013, 8:00 AM to 4:30 PM Meeting starts at 8:30 AM Location: Sherwood Hotel 11 Min Sheng E Road, Sec. 3 Taipei, Taiwan http://www.sherwood.com.tw/ Room: Tentatively Ballroom D Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Co-sponsors (in alphabetical order): ANSYS Cadence Design Systems Intel Corporation IO Methodology Synopsys Others to be determined. Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND We have held many successful Summit meetings across Asia in previous years. This will be our third meeting in Taiwan where many national and international high technology companies have operations. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register using the information below (in English): Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Lance Wang, IO Methodology lwang@iometh.com Bob Ross, Teraspeed Consulting Group bob@teraspeed.com SIGNUP DEADLINE: November 15, 2013 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: October 15, 2013 to produce the presentation copies for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Presentations must be in English, although the delivery can be in Chinese. Submissions from Taiwan and across Asia are strongly encouraged, though submissions from other regions are very welcome. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:00 - 8:30 Vendor table setup and tables 8:00 - 8:30 Sign in 8:30 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 16:30 Presentations The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several presentations on IBIS applications and behavioral modeling issues, including interconnects and system components, are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL Hotels in all price ranges can be found through internet searches. The conference hotel link is http://www.sherwood.com.tw/ - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Consulting Group, LCC http://www.teraspeed.com bob@teraspeeed.com Direct : 503-246-8048 Teraspeed Labs: 971-279-5325 Headquarters: 401-284-1827 Teraspeed is a registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_000C_01CEBECD.99F95330 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

To All:

The I= BIS Open Forum is holding its third Asian IBIS Summit Meeting in=

Several companies listed below are co-sponsorin= g this major event

to be held at the Sherwood Hotel in Taipei. = Like in previous

years, We are planning for many attendees.

We encourage technical contributions from As= ia.

Other Asian IBIS Summit meetings are sch= eduled for:

Shanghai, P.R. China, Fri= day November 15, Parkyard Hotel

Yokohama, Japan, Friday,= November 22, Pacifico Yokohama

Lance Wang

IO Methodology

Bob Ross

Teraspeed Consulting Group

-------------= - ---------------------------------------------------------=

= ; &n= bsp; ASIAN IBIS= SUMMIT (TAIPEI)

&n= bsp; = ; THIRD CALL FOR=

&= nbsp; PARTICIPATION A= ND PRESENTATIONS

--------------------------------------------= - --------------------------

= ; A S I A N I B= I S S U M M I T ( T A I P E I )<= /p>

&= nbsp;

Time/Date: Tuesday, November 19, 2013, 8:00 AM to 4:30 P= M

&= nbsp; Meeting starts at 8:30 AM

Location:&nb= sp; Sherwood Hotel

&n= bsp; 11 Min Sheng E Road, Sec. 3<= /p>

= Taipei, Taiwan=

&= nbsp; http://www.sherwood.com.tw/

Room: Tentatively Ballroom D

Content: Presentations and= Discussions

Purpose: Soli= cit and exchange IBIS and interconnect model related

<= p class=3DMsoPlainText> &nbs= p; information and id= eas.

Co-sponsors (in alph= abetical order):

&n= bsp; ANSYS

<= span style=3D'font-family:"Courier New"'> &nbs= p; Cadence Design Systems

&= nbsp; Intel Corporati= on

= IO Methodology

= ; Synopsys

&nbs= p; Others to be determined.<= /span>

Cost: FREE, includi= ng refreshments and buffet lunch

Vendors:&nb= sp; Some vendors will have information tables outside the<= /o:p>

m= eeting room

&n= bsp; Contact us for details regarding sponsor= ship.

BACKGROUND

We have held many successful Summit meetings across Asia i= n

previous years. This will be our third mee= ting in Taiwan where

many national and internation= al high technology companies have

operations.=

Our objective is to reach out inter= nationally to communicate with

the local experts a= nd to learn of regional concerns.

<= p class=3DMsoPlainText>CONFERENCE= LANGUAGE

<= span style=3D'font-family:"Courier New"'> The conference langua= ge is English, but we will plan for technical

tran= slations in English and Chinese. So presenters can optionally

deliver in Chinese as long as an English version of the m= aterial is

available.

This meeting wil= l be conducted as a formal IBIS Summit Meeting.

Pr= esentations will be archived in an electronic format on our

&nb= sp; Summits site, and minutes of the meeting will be issued. Ho= wever,

no formal decisions requiring votes will be= planned.

<= span style=3D'font-family:"Courier New"'>CALL FOR PARTICIPANTS

People involved in IBIS and interconnect mo= del development, EDA

tool development, and digital= circuit design are invited to

participate in the = Summit meeting. If you plan to participate,

= please register using the information below (in English):=

Name:

= ; E-mail address:

&n= bsp; Company:

Top-level Web Link:=

Country:

Send to BOTH:

Bob Ross, Teraspeed Consulting Group &nb= sp; bob@teraspeed.com

SIGNUP DE= ADLINE: November 15, 2013

CALL FOR PRESENTA= TIONS

We are seeking presentati= ons from individuals who have IBIS and

interconnec= t modeling experiences or issues. If we have to

&nb= sp; select presentations for the number of time slots available, we

will give preferential consideration to presentations fro= m Asia.

Presentation Format:&nb= sp; LCD Projection from meeting laptop computer

&nbs= p;

Time: = ; 15-30 Minutes inclu= ding questions

Electronic Archi= val: All presentations will uploaded to our <= /p>

= &nb= sp; = public IBIS Summit archives

Ele= ctronic Format: Power Point or Acrobat

Presentation Booklet: Available at th= e meeting for all attendees

Pre= sentation Deadline: October 15, 2013 to produce the presentation=

If y= ou plan a presentation, please ADD to the above registration

&n= bsp; information:

&n= bsp; Title of Presentation:

&nbs= p; Estimated Time:

(= 30 minutes or less)

We will not= ify you of acceptance and may follow up with questions

&n= bsp; when we form the program agenda.

<= /p>

= Note: Vendor promotional or business information is prohibited.=

Presentations must be in English, although the deliver= y can be in

Chinese.

though submissions from other regions are ver= y welcome. Topics may

include behavioral mod= eling of buffers, interconnects or other

system co= mponents.

<= span style=3D'font-family:"Courier New"'>AGENDA

8:00 - 8:30 Vendor table setup and table= s

8:00 - 8:30 Sign in=

&nb= sp; 12:00 - 13:30 Free buffet lunch, vendor tables<= /p>

= 13:30 - 16:30 Presentations

&nb= sp; The specific agenda is being developed. We expect nine or t= en

presentations covering a range of issues from e= xisting customer

experiences, existing clarifica= tions and some of the future

<= span style=3D'font-family:"Courier New"'> directions in IBIS to= deal with technical advances.

= Several presentations on IBIS applications and behavioral modeling

issues, including interconnects and system components, are= expected

from co-sponsor companies and/or their c= ustomers.

<= span style=3D'font-family:"Courier New"'>LIST OF NEARBY HOTELS AND TRAVEL

Hotels in all price ranges can = be found through internet searches.

The conference= hotel link is

http://www.sherw= ood.com.tw/

--------------------------------= - ---------------------------------

&nbs= p;

Bob Ross

Teraspeed Consultin= g Group, LCC

http://www.teraspeed.com=

bob@teraspeeed.com

Direct : 503-246-8048

Teraspeed Labs: 971-279-5325

He= adquarters: 401-284-1827

<= /o:p>

Teraspeed is a registered service mark of = Teraspeed Consulting Group LLC

&= nbsp;

--=20
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