From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #240 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Friday, August 15 2014 Volume 01 : Number 240 ---------------------------------------------------------------------- Date: Wed, 6 Aug 2014 23:34:19 -0700 From: Bradley Brim Subject: [IBIS-Users] RE: Node "0" in IBIS, IBIS External Model, IBIS Interconnect Models - --_000_F91EA69A3545344A87391E8C1C6694C60A86BAB19CMAILSJ4global_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello all, This is a message to solicit feedback to the IBIS interconnect task group. = It is not to initiate an extended e-mail exchange among this entire distrib= ution list. Please consider replying to ibis-interconn@freelists.org with any thoughts you wish to share. The interconnect task group has been working on a BIRD to enable more gener= al package/on-die interconnect models inside the IBIS topology through the = application of ISS subcircuits. ISS supports the application of global grou= nd. There is a vote scheduled for 8:00am this Wednesday August 13 in the in= terconnect task group meeting to decide whether or not we allow access to g= lobal ground for this new package/on-die interconnect modeling. We delayed = the vote because there are only a handful of active participants in this ta= sk group and we wished to allow for broader comment before making such an i= mportant decision. Views among the active participants vary, as we suspect = they will throughout the IBIS user/developer community. Cadence believes that global ground should not be accessible from within IB= IS package/on-die interconnect models. We do not believe an industry standa= rd should allow access to any electrical node outside the topology of IBIS = except for connectivity through one of the formally declared external pins.= Any current that flows to global ground in the electrical model that does = not connect through a pin in the external pin list is non-physical and inco= rrect. If global ground access is disallowed for these new models, a very s= mall incremental effort is required by model developers to apply package/o= n-die interconnect models which now apply global ground (see examples below= ). We believe it would be a benefit to the IBIS community to revisit the buffe= r portion of the specification formally disallow access to global ground an= d clarify all local references, such as to where C_comp or legacy package p= in capacitances are referenced. We perceive this activity as a separate, th= ough related, discussion and wish to focus now on the decision for intercon= nect. If global ground is available in the new package/on-die interconnect = portion we perceive much less value in revisiting the buffer portion of the= spec to clean-up references and global ground issues. Thanks in advance for sharing your thoughts with the interconnect task grou= p, - -Brad Brim The motion being considered is to disallow the application of global ground= for the new IBIS Package/On-die Interconnect modeling capability. The moti= on addresses only the new section of the specification we are now consideri= ng. Specifically, it does not resolve questions such as: to where is C_com= p or a legacy package pin capacitances referenced. Further, the motion does= not restrict the application of global ground for other present or future = ISS applications. The motion does not include a proposed implementation, th= ough a few alternatives are discussed below. The only ISS element that implicitly applies global ground is the S-element= in its N-node form. The proposal could either (a) disallow application of = this form of the S-element, or (b) impose two requirements: (1) model maker= specification of a reference terminal to replace any occurrence of global = ground, and (2) EDA tool application of this terminal as local reference in= stead of the implicit global ground. It seems there are two potential implementations. One choice would be to co= nsider all occurrences of what would otherwise be global ground (i.e. '0', = GROUND, GND, !GND, GND!) as any other locally-scoped node. These nodes woul= d be connected to each other within the subcircuit but outside the domain o= f the subcircuit would remain floating unless explicitly exposed in the ext= ernal node list and connected to something in a higher level circuit. The N= - -node form of the S-element would be disallowed. Alternately, an implementa= tion similar to that described above as option (b) for the N-node form of t= he S-element could be pursued. It is likely a local reference terminal will require model maker specificat= ion to enable termination of unused terminals for Package/On-die Interconne= ct Models. This terminal could also serve as local reference for any explic= it or implicit formerly global ground if an EDA tool solution is pursued. If the choice of explicitly exposing global ground nodes is chosen, then ED= A tools are not likely to require any changes for immediate support of this= new Package/On-die Interconnect modeling capability; except for the model = developer convenience feature being considered for terminating unused termi= nals. A small incremental burden of exposing these nodes in subcircuit call= s will be required from model developers for all these new models. If the p= ath of EDA tool mapping of global ground to a local reference terminal is p= ursued, then all EDA tools will require significant enhancement to support = the new capability. Due to development resource allocations and commercial = release schedule synchronization it is likely to require a year or more for= the capability to be broadly supported once the specification becomes avai= lable. The timeframe for support of terminating unused terminals may be sim= ilarly long even for the explicit exposure choice, though the effort seems = significantly less because no updating of model maker specified netlists wi= ll be required prior to internal consumption by the EDA tool. A ISS subcircuit could presently be referenced as xThruPath in out For any of the following cases 1. Node 0 global ground nodes .subckt ThruPath 1 4 L1 1 2 1pH L2 2 3 1pH L3 3 4 1pH C1 2 0 1fF C2 3 0 1fF .ends 2. Alternate global ground nodes .subckt ThruPath 1 4 L1 1 2 1pH L2 2 3 1pH L3 3 4 1pH C1 2 GND 1fF C2 3 GROUND 1fF .ends 3. Implicit reference node using global ground .subckt ThruPath 1 2 S1 1 2 mname=3Dthru .model thru S 2 TSTONEFILE=3D'TSthru.s2p' .ends 4. Explicit reference node using global ground .subckt ThruPath 1 2 S1 1 2 GND mname=3Dthru .model thru S 2 TSTONEFILE=3D'TSthru.s2p' .ends 5. Explicit reference nodes using global ground .subckt ThruPath 1 2 S1 1 0 2 0 mname=3Dthru .model thru S 2 TSTONEFILE=3D'TSthru.s2p' .ends 6. Explicit reference nodes using various forms of global ground .subckt ThruPath 1 2 S1 1 GND 2 GROUND mname=3Dthru .model thru S 2 TSTONEFILE=3D'TSthru.s2p' .ends If the present global ground nodes ('0' and its aliases) are treated the sa= me as any other locally-scoped node with required explicit exposure in the = subcircuit node list, the above forms would change as follows: 1. Node 0 as global ground xThruPath in out ref_node .subckt ThruPath 1 4 0 L1 1 2 1pH L2 2 3 1pH L3 3 4 1pH C1 2 0 1fF C2 3 0 1fF .ends 2. Alternate nodes as global ground xThruPath in out local_ref local_ref .subckt ThruPath 1 4 GND GROUND L1 1 2 1pH L2 2 3 1pH L3 3 4 1pH C1 2 GND 1fF C2 3 GROUND 1fF .ends 3. Implicit reference node using global ground would be a disallowed = form. 4. Explicit reference node using global ground xThruPath in out ref .subckt ThruPath 1 2 S1 1 2 GND mname=3Dthru .model thru S 2 TSTONEFILE=3D'TSthru.s2p' .ends 5. Explicit reference nodes global ground xThruPath in out ref .subckt ThruPath 1 2 GND S1 1 0 2 0 mname=3Dthru .model thru S 2 TSTONEFILE=3D'TSthru.s2p' .ends 6. Explicit reference nodes using various forms of global ground xThruPath in out ref ref .subckt ThruPath 1 2 GND GROUND S1 1 GND 2 GROUND mname=3Dthru .model thru S 2 TSTONEFILE=3D'TSthru.s2p' .ends From: ibis-macro-bounce@freelists.org [mailto:ibis-macro-bounce@freelists.o= rg] On Behalf Of Walter Katz Sent: Tuesday, August 05, 2014 6:50 AM To: IBIS-ATM Subject: [ibis-macro] Node "0" in IBIS, IBIS External Model, IBIS Interconn= ect Models All, There is currently a debate in the IBIS Interconnect meeting on the allowed= usage of Node "0" in the new IBIS and EBD Interconnect IBIS-ISS and Touchs= tone models. There is a vote scheduled on August 13 in IBIS Interconnect to= forbid the use of Node "0" (aka GND, !GND and GROUND) in IBIS-ISS subckts = reference by IBIS interconnect models. SiSoft does believe that there are circumstances where using Node "0" in in= terconnect and I/O Buffer Models is problematic and should be avoided. The = IBIS Interconnect draft BIRDs allow the model maker to create interconnect = circuits without using Node "0", but we also think that the proposal to for= bid Node "0" should be defeated: We believe that to "outlaw" node 0 would merely remove a convenient simplif= ication to the circuit equations, forcing an accounting for a bunch of volt= ages and currents that don't matter in the first place. However, this is an important opportunity to understand Node "0" in the con= text of the IBIS I/O buffers, so that I/O buffers can be created or impleme= nted without using Node "0". I will simply point out a number of places in = the IBIS 6.0 specification which explicitly reference SPICE Node "0" or "GN= D" ( I am sure I missed a number of cases but this should indicate the magn= itude of the effort to remove the usage of Node 0 in the IBIS specification= , or how to create IBIS I/O buffers that do not use Node "0"): 1. Page 93, 6.3 Multilingual Model Extensions: a. A_gnd is a universal reference node, similar to SPICE ideal node "= 0." Ports 14 and 15 are only available under [External Model] for support = of true differential buffers. b. Can multilingual models be written without using A_gnd, and connect= this terminal of the multilingual model directly to a Signal_name defined = in the Component [Pins] list? c. Also not Page 121, 6.3 i. One = of these port entries must name a reference for the other port (for example= , A_gnd). d. Also note page 125 i. Ports vcc gnd io1 io2 e. 2. Page 33, 6.1 Model Statement a. C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and C_comp_gnd_= clamp are intended to represent the parasitic capacitances of those structu= res whose I-V characteristics are described by the [Pullup], [Pulldown], [P= OWER Clamp] and [GND Clamp] I-V tables. For this reason, the simulator sho= uld generate a circuit netlist so that, if defined, each of the C_comp_* ca= pacitors are connected in parallel with their corresponding I-V tables, whe= ther or not the I-V table exists. That is, the C_comp_* capacitors are posi= tioned between the signal pad and the nodes defined by the [Pullup Referenc= e], [Pulldown Reference], [POWER Clamp Reference] and [GND Clamp Reference]= keywords, or the [Voltage Range] keyword and GND. 3. Page 51, 6.1 Model Statement a. C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and C_comp_gnd= _clamp are intended to represent the parasitic capacitances of those struct= ures whose I-V characteristics are described by the [Pullup], [Pulldown], [= POWER Clamp] and [GND Clamp] I-V tables. For this reason, the simulator sh= ould generate a circuit netlist so that, if defined, each of the C_comp_* c= apacitors is connected in parallel with its corresponding I-V table(s), whe= ther or not the I-V table(s) exist(s). That is, the C_comp_* capacitors ar= e positioned between the signal pad and the nodes defined by the [Pullup Re= ference], [Pulldown Reference], [POWER Clamp Reference] and [GND Clamp Refe= rence] keywords, or the [Voltage Range] keyword and GND. 4. Page 56,..., Model Statement a. The effective current table for the Isso_pd current is extracted by= the following process. The buffer is set to "logic zero." A Vtable volta= ge source is inserted between the [Pulldown Reference] node and the buffer = as shown in Figure 7. This Vtable voltage is swept from -Vcc (typical) to = +Vcc (typical) and is relative to the [Pulldown Reference] typ/min/max valu= es for the corresponding columns. The output is connected to the GND (typi= cal) value as shown in Figure 7. b. The effective current table for the Isso_pu current is extracted by= the following process. The buffer is set to "logic one". A Vtable voltag= e source is inserted between the [Pullup Reference] node and the buffer as = shown below. This Vtable voltage is swept from -Vcc (typical) to +Vcc (typ= ical) and is relative to the [Pullup Reference] typ/min/max values for the = corresponding columns. The output is connected to the GND (typical) value = as shown in Figure 8. c. For example, for a typ/min/max [Voltage Range] of 5.0V, 4.5V and 5= .5V, and with the negative reference set to GND, the Isso_pu(0) and Isso_pd= (0) values for typ/min/max should be equal to the column values as shown in d. Description: The data for these keywords define the resistance = values of Rgnd and Rpower connected to GND and the POWER pins, respectively= , and the resistance and capacitance values for an AC terminator. e. Other Notes: [Rpower] is connected to "Vcc" and [Rgnd] is connect= ed to "GND". However, [GND Clamp Reference] voltages, if defined, apply to= [Rgnd]. [POWER Clamp Reference] voltages, if defined, apply to [Rpower]. = Either or both [Rgnd] and [Rpower] may be defined and may coexist with [GN= D Clamp] and [POWER Clamp] tables. f. Figure 16 illustrates a general configuration from which a [Risin= g Waveform] or [Falling Waveform] is extracted. The DUT die shows all of th= e available power and ground pin reference voltage terminals. For many buf= fers, only one power pin and one common ground pin terminal are used. The = absolute GND is the reference for the V_fixture voltage and the package mod= el equivalent network. It can also serve as a reference for C_comp, unless= C_comp is optionally split into component attached to the other reference = voltages. g. Other Notes: Figure 17 documents some expected internal paths for= a useful special case where only one common power pin (VDDQ) and one commo= n ground exists (GND). h. The power reference terminal (VDDQ) is usually the [Pullup Referenc= e], or the default [Voltage Range] terminal. The [Pulldown Reference] term= inal is usually at the GND connection. i. In most cases six [Composite Current] tables are recommended for = accurate modeling. The first four tables correspond to the recommended fix= ture conditions for [Rising Waveform] and [Falling Waveform] tables (normal= ly 50 ohm loads to Vdd and GND). j. The [Composite Current] table can be derived from currents measur= ed at the [Pulldown Reference] (GND) node, but adjusted for the current flo= wing through the output pin and at other terminals. 5. There are a number of Figures that include a GND symbols, or a GND= node a. Examples. i. Page= 57, 6.1 Model Statement, Figure 7 ii. Page = 72, 6.1 Model Statement, Figure 16 6. Page 162 ..., 9. Notes on Data Derivation Method a. Then: Attach a 50 ohm resistor to GND to derive the rising edge ram= p. Attach a 50 ohm resistor to POWER to derive the falling edge ramp. b. Then: Attach either a 50 ohm resistor or the semiconductor vendor s= uggested termination resistance to either GND or the suggested termination = voltage. Use this load to derive both the rising and falling edges. Walter Walter Katz wkatz@sisoft.com Phone 303.449-2308 Mobile 303.335-6156 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --_000_F91EA69A3545344A87391E8C1C6694C60A86BAB19CMAILSJ4global_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hello all,<= /o:p>

 

Thi= s is a message to solicit feedback to the IBIS interconnect task group. It = is not to initiate an extended e-mail exchange among this entire distributi= on list. Please consider replying to ibis-interconn@freelists.org with any thoughts you wish to sh= are.

 

The interconnect task group has been working on a BIRD to enable mor= e general package/on-die interconnect models inside the IBIS topology throu= gh the application of ISS subcircuits. ISS supports the application of glob= al ground. There is a vote scheduled for 8:00am this Wednesday August 13 in= the interconnect task group meeting to decide whether or not we allow acce= ss to global ground for this new package/on-die interconnect modeling. We d= elayed the vote because there are only a handful of active participants in = this task group and we wished to allow for broader comment before making su= ch an important decision. Views among the active participants vary, as we s= uspect they will throughout the IBIS user/developer community.

 

Cadence be= lieves that global ground should not be accessible from within IBIS package= /on-die interconnect models. We do not believe an industry standard should = allow access to any electrical node outside the topology of IBIS except for= connectivity through one of the formally declared external pins. Any curre= nt that flows to global ground in the electrical model that does not connec= t through a pin in the external pin list is non-physical and incorrect. If = global ground access is disallowed for these new models, a very small incre= mental effort is required  by model developers to apply package/on-die= interconnect models which now apply global ground (see examples below). &n= bsp;

 

We believe it would be a benefit to the IBIS community to revisit th= e buffer portion of the specification formally disallow access to global gr= ound and clarify all local references, such as to where C_comp or legacy pa= ckage pin capacitances are referenced. We perceive this activity as a separ= ate, though related, discussion and wish to focus now on the decision for i= nterconnect. If global ground is available in the new package/on-die interc= onnect portion we perceive much less value in revisiting the buffer portion= of the spec to clean-up references and global ground issues.

 

Thanks in a= dvance for sharing your thoughts with the interconnect task group,

-Brad Brim

<= o:p> 

 

The motion being considered is to dis= allow the application of global ground for the new IBIS Package/On-die Inte= rconnect modeling capability. The motion addresses only the new section of = the specification we are now considering. Specifically, it does not resolve= questions such as:  to where is C_comp or a legacy package pin capaci= tances referenced. Further, the motion does not restrict the application of= global ground for other present or future ISS applications. The motion doe= s not include a proposed implementation, though a few alternatives are disc= ussed below.

 

The only ISS element that implicitly applies global ground is= the S-element in its N-node form. The proposal could either (a) disallow a= pplication of this form of the S-element, or (b) impose two requirements: (= 1) model maker specification of a reference terminal to replace any occurre= nce of global ground, and (2) EDA tool application of this terminal as loca= l reference instead of the implicit global ground.

 

It seems there are two = potential implementations. One choice would be to consider all occurrences = of what would otherwise be global ground (i.e. ‘0’, GROUND, GND= , !GND, GND!) as any other locally-scoped node. These nodes would be connec= ted to each other within the subcircuit but outside the domain of the subci= rcuit would remain floating unless explicitly exposed in the external node = list and connected to something in a higher level circuit. The N-node form = of the S-element would be disallowed. Alternately, an implementation simila= r to that described above as option (b) for the N-node form of the S-elemen= t could be pursued.

 

It is likely a local reference terminal will require= model maker specification to enable termination of unused terminals for Pa= ckage/On-die Interconnect Models. This terminal could also serve as local r= eference for any explicit or implicit formerly global ground if an EDA tool= solution is pursued.

 

If the choice of explicitly exposing global ground n= odes is chosen, then EDA tools are not likely to require any changes for im= mediate support of this new Package/On-die Interconnect modeling capability= ; except for the model developer convenience feature being considered for t= erminating unused terminals. A small incremental burden of exposing these n= odes in subcircuit calls will be required from model developers for all the= se new models. If the path of EDA tool mapping of global ground to a local = reference terminal is pursued, then all EDA tools will require significant = enhancement to support the new capability. Due to development resource allo= cations and commercial release schedule synchronization it is likely to req= uire a year or more for the capability to be broadly supported once the spe= cification becomes available. The timeframe for support of terminating unus= ed terminals may be similarly long even for the explicit exposure choice, t= hough the effort seems significantly less because no updating of model make= r specified netlists will be required prior to internal consumption by the = EDA tool.

 

 

A ISS subcircuit could presently be referenced as=

    xThruPath in out

For any of the following case= s

1.       Node 0 global ground node= s

.subckt ThruPath 1 4

    L1 1 2= 1pH

=     = L2 2 3 1pH

  &= nbsp; L3 3 4 1pH

 &= nbsp;  C1 2 0 1fF

&= nbsp;   C2 3 0 1fF

.ends

2.       Alternate global= ground nodes

.subckt Th= ruPath 1 4

  &= nbsp; L1 1 2 1pH

 &= nbsp;  L2 2 3 1pH

&= nbsp;   L3 3 4 1pH

    C1 2 GND 1fF

    C2 3 GROUND 1fF

.ends

= 3.   &n= bsp;   Implicit reference node using global ground

.subckt ThruPath 1 2

    S1 1 2 mname=3Dthru

    .model thru S 2 TST= ONEFILE=3D’TSthru.s2p’

.ends

4.     &nb= sp; Explicit r= eference node using global ground

.subckt ThruPath 1 2

    S1 1 2 GND mname=3Dthru

    .model thru S 2 TSTONEFILE=3D&= #8217;TSthru.s2p’

= .ends

5.       = Explicit reference no= des using global ground

= .subckt ThruPath 1 2

&nb= sp;   S1 1 0 2 0 mname=3Dthru

    .model thru S 2 TSTONEFILE=3D’TSth= ru.s2p’

.ends=

6.       <= /span>Explicit reference nodes usin= g various forms of global ground

.subckt ThruPath 1 2

    S1 1 GND 2 GROUND mname=3Dthru

    .model thru S 2 TSTONEFI= LE=3D’TSthru.s2p’

.ends

 

If the present global ground nodes (‘0’ and its al= iases) are treated the same as any other locally-scoped node with required = explicit exposure in the subcircuit node list, the above forms would change= as follows:

1.       = Node 0 as glob= al ground

xThruPath in o= ut ref_node

.subckt Thru= Path 1 4 0

  &= nbsp; L1 1 2 1pH

 &= nbsp;  L2 2 3 1pH

&= nbsp;   L3 3 4 1pH

    C1 2 0 1fF

    C2 3 0 1fF

    &nb= sp;  Alte= rnate nodes as global ground

xThruPath in out local_ref local_ref

.subckt ThruPath 1 4 GND GROUND

    L1 1 2 1pH

    L2 2 3 1pH

    L3 3 4 1pH

    C1 2 GND 1f= F

    C2 = 3 GROUND 1fF

.ends<= /o:p>

3.       Implicit reference node= using global ground would be a disallowed form.

4.       = Explicit reference node using global ground

xThruPath in out ref=

.subckt ThruPath 1 2

    S1 1 2 GND = mname=3Dthru

  = ;  .model thru S 2 TSTONEFILE=3D’TSthru.s2p’

.ends

5.&nbs= p;      Explicit reference nodes global ground

xThruPath in out ref

.subckt ThruPath 1 2 GND<= /p>

    S1 1 0 2 0 mname=3Dthru=

    .mod= el thru S 2 TSTONEFILE=3D’TSthru.s2p’

.ends

6.       Explicit reference nodes using va= rious forms of global ground

xThruPath in out ref ref

.subckt ThruPath 1 2 GND GROUND

    S1 1 GND 2 GROUND mname=3Dthru<= /span>

    .model thru S 2 = TSTONEFILE=3D’TSthru.s2p’

.ends<= /p>

 

 =

From: ibis-macro-bounce@freelis= ts.org [mailto:ibis-macro-bounce@freelists.org] On Behalf Of Walter = Katz
Sent: Tuesday, August 05, 2014 6:50 AM
To: IBIS-AT= M
Subject: [ibis-macro] Node "0" in IBIS, IBIS External= Model, IBIS Interconnect Models

 

All,

<= p class=3DMsoNormal> 

There is curr= ently a debate in the IBIS Interconnect meeting on the allowed usage of Nod= e “0” in the new IBIS and EBD Interconnect IBIS-ISS and Touchst= one models. There is a vote scheduled on August 13 in IBIS Interconnect to = forbid the use of Node “0” (aka GND, !GND and GROUND) in IBIS-I= SS subckts reference by IBIS interconnect models.

 

SiSoft does believe tha= t there are circumstances where using Node “0” in interconnect = and I/O Buffer Models is problematic and should be avoided. T= he IBIS Interconnect draft BIRDs allow the model maker to create interconne= ct circuits without using Node “0”, but we also think that the = proposal to forbid Node “0” should be defeated:

<= p class=3DMsoNormal> 

We believe t= hat to "outlaw" node 0 would merely remove a convenient simplific= ation to the circuit equations, forcing an accounting for a bunch of voltag= es and currents that don't matter in the first place.

=

 

However, thi= s is an important opportunity to understand Node “0” in the con= text of the IBIS I/O buffers, so that I/O buffers can be created or impleme= nted without using Node “0”. I will simply point out a number o= f places in the IBIS 6.0 specification which explicitly reference SPICE Nod= e “0” or “GND” ( I am sure I missed a number of cas= es but this should indicate the magnitude of the effort to remove the usage= of Node 0 in the IBIS specification, or how to create IBIS I/O buffers tha= t do not use Node “0”):

 

1.    &nb= sp;  Page 93, 6.3 Multilingual Model Extension= s:

a. &= nbsp;     A_gnd is a universal = reference node, similar to SPICE ideal node “0.”  Ports 14= and 15 are only available under [External Model] for support of true diffe= rential buffers.

b.      Can multilingua= l models be written without using A_gnd, and connect this terminal of the m= ultilingual model directly to a Signal_name defined in the Component [Pins]= list?

c. = ;      Also not Page 121, = 6.3

         &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;   i. =      One of these port entries = must name a reference for the other port (for example, A_gnd).

d.    =   Also note page 125

   = ;            &n= bsp;       i.   Ports vcc gnd io1 = io2

e. &= nbsp;     

= 2.       Page 33, 6.1 Model Statement

a.      C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and C_comp_g= nd_clamp are intended to represent the parasitic capacitances of those stru= ctures whose I-V characteristics are described by the [Pullup], [Pulldown],= [POWER Clamp] and [GND Clamp] I-V tables.  For this reason, the simul= ator should generate a circuit netlist so that, if defined, each of the C_c= omp_* capacitors are connected in parallel with their corresponding I-V tab= les, whether or not the I-V table exists. That is, the C_comp_* capacitors = are positioned between the signal pad and the nodes defined by the [Pullup = Reference], [Pulldown Reference], [POWER Clamp Reference] and [GND Clamp Re= ference] keywords, or the [Voltage Range] keyword and GND.

3.  &= nbsp;    Page 51, 6.1 Model Statemen= t

a.       <=
/span>C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and C_comp_=
gnd_clamp are intended to represent the parasitic capacitances of those str=
uctures whose I-V characteristics are described by the [Pullup], [Pulldown]=
, [POWER Clamp] and [GND Clamp] I-V tables.  For this reason, the simu=
lator should generate a circuit netlist so that, if defined, each of the C_=
comp_* capacitors is connected in parallel with its corresponding I-V table=
(s), whether or not the I-V table(s) exist(s).  That is, the C_comp_* =
capacitors are positioned between the signal pad and the nodes defined by t=
he [Pullup Reference], [Pulldown Reference], [POWER Clamp Reference] and [G=
ND Clamp Reference] keywords, or the [Voltage Range] keyword and GND.

4.       Page 56= ,…, Model Statement

a.      The= effective current table for the Isso_pd current is extracted by the follow= ing process.  The buffer is set to “logic zero.”  A V= table voltage source is inserted between the [Pulldown Reference] node and = the buffer as shown in Figure 7.  This Vtable voltage is swept from -V= cc (typical) to +Vcc (typical) and is relative to the [Pulldown Reference] = typ/min/max values for the corresponding columns.  The output is conne= cted to the GND (typical) value as shown in Figure 7.

b.=      = The effective current table for the Isso_pu curren= t is extracted by the following process.  The buffer is set to “= logic one”.  A Vtable voltage source is inserted between the [Pu= llup Reference] node and the buffer as shown below.  This Vtable volta= ge is swept from -Vcc (typical) to +Vcc (typical) and is relative to the [P= ullup Reference] typ/min/max values for the corresponding columns.  Th= e output is connected to the GND (typical) value as shown in Figure 8.=

c.  &= nbsp;    For example, for a typ/min/= max [Voltage Range] of 5.0V, 4.5V and 5.5V, and with the negative reference= set to GND, the Isso_pu(0) and Isso_pd(0) values for typ/min/max should be= equal to the column values as shown in

d.      Description:     The data for thes= e keywords define the resistance values of Rgnd and Rpower connected to GND= and the POWER pins, respectively, and the resistance and capacitance value= s for an AC terminator.

e.      O= ther Notes:   [Rpower] is connected to “Vcc” and [Rgnd= ] is connected to “GND”.  However, [GND Clamp Reference] v= oltages, if defined, apply to [Rgnd].  [POWER Clamp Reference] voltage= s, if defined, apply to [Rpower].  Either or both [Rgnd] and [Rpower] = may be defined and may coexist with [GND Clamp] and [POWER Clamp] tables.&n= bsp;

f.&nb= sp;       Figure 16 i= llustrates a general configuration from which a [Rising Waveform] or [Falli= ng Waveform] is extracted. The DUT die shows all of the available power and= ground pin reference voltage terminals.  For many buffers, only one p= ower pin and one common ground pin terminal are used.  The absolute GN= D is the reference for the V_fixture voltage and the package model equivale= nt network.  It can also serve as a reference for C_comp, unless C_com= p is optionally split into component attached to the other reference voltag= es.

g. = ;     Other Notes: =   Figure 17 documents some expected internal paths for a useful specia= l case where only one common power pin (VDDQ) and one common ground exists = (GND).

h.&n= bsp;     The power reference te= rminal (VDDQ) is usually the [Pullup Reference], or the default [Voltage Ra= nge] terminal.  The [Pulldown Reference] terminal is usually at the GN= D connection.

i.        In = most cases six [Composite Current] tables are recommended for accurate mode= ling.  The first four tables correspond to the recommended fixture con= ditions for [Rising Waveform] and [Falling Waveform] tables (normally 50 oh= m loads to Vdd and GND). 

j.        The [Composite Current] table can be derived from currents m= easured at the [Pulldown Reference] (GND) node, but adjusted for the curren= t flowing through the output pin and at other terminals.

5.       There are a number of Figures that include a GND symbols, or a= GND node

a.&n= bsp;      Examples.

           &n= bsp;            = ;            &n= bsp;            = ;            &n= bsp; i.  &nbs= p;   Page 57, 6.1 Model Statement, Figure= 7

          = ;            &n= bsp;            = ;            &n= bsp;            = ; ii.   =    Page 72, 6.1 Model Statement, Figure 1= 6

= 6.    &nbs= p;  Page 162 …, 9. Notes on Data Derivat= ion Method

a. &= nbsp;    Then: Attach a 50 ohm resis= tor to GND to derive the rising edge ramp.  Attach a 50 ohm resistor t= o POWER to derive the falling edge ramp.

b.      Then: Attach either a 50 ohm resistor or the semiconductor vendor sugges= ted termination resistance to either GND or the suggested termination volta= ge.  Use this load to derive both the rising and falling edges.

 

Walt= er

 

Walter Katz

wkatz@sisoft.com

= Phon= e 303.449-2308

Mobile 303.335-6156

 


--= =20
This message has been scanned for viruses and
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believed to be clean. - --_000_F91EA69A3545344A87391E8C1C6694C60A86BAB19CMAILSJ4global_-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 30 Jan 2014 09:58:50 -0800 From: Sam Chitwood Subject: [IBIS-Users] RE: [IBIS] package number pins - --_000_A66C83F04198D24E82D005D1C2D51A300DE9DCC958MAILSJ4global_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Fabio, One of my IBIS presentations covers this subject: http://www.eda.org/ibis/summits/feb08/chitwood.pdf To directly answer your question, x > y is correct and feasible. Power and= ground net pins are routinely shorted together on a per-net basis while cr= eating a Matrix model. The reasons why are covered in the presentation. B= ut if you have a mismatch if signal pins, that would be a problem. Don't say "unfortunately" x > y. It's usually a good thing! Thanks, Sam From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Fabio BRI= NA Sent: Thursday, January 30, 2014 5:24 AM To: ibis@eda.org; ibis-users@eda.org Subject: [IBIS] package number pins Hello experts, I have an IBIS model with x pins (defined under [Pin] keyword). Inside this model I have a Package structure in matrix format (with [Def= ine Package Model]). Here the number of pins is y: [Number of Pin] y Usually I have x =3D y , and all it's ok. In this case, unfortunately, I have x > y , the Check Parser don't generate any Errors (or Warnings) . Is that correct? Is this a feasible condition? That means that the x - y pins (out of Package) will work without para= sitic elements? (to complete this comment I have to say that if y > x , the Parser gene= rate Errors, like this: ERROR - Pin 'A5' found in package_model 'Pack1' Pin_numbers list not fo= und in Component 'COMP1' Pin list) Thanks for any suggestions, Regards, Fabio - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --_000_A66C83F04198D24E82D005D1C2D51A300DE9DCC958MAILSJ4global_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi Fabio,

 

One of my IBIS presentations covers this subject:

http://www.eda.org/ibis/summits/feb08/chitwood.p= df

 

To directly answer your question, x > y is = correct and feasible.  Power and ground net pins are routinely shorted= together on a per-net basis while creating a Matrix model.  The reaso= ns why are covered in the presentation.  But if you have a mismatch if= signal pins, that would be a problem.

 

Don’t sa= y “unfortunately” x > y.  It’s usually a good thi= ng!

 

Thanks,

Sam

 

 

<= p class=3DMsoNormal>From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] O= n Behalf Of Fabio BRINA
Sent: Thursday, January 30, 2014 5:24= AM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS= ] package number pins

 

Hello experts,  <= /o:p>

 

   I have an IBIS model with x pins (defined= under [Pin] keyword). 

 

   Inside= this model I have a Package structure in matrix format (with [Define Packa= ge Model]).

   Her= e the number of pins is  y:   [Number of Pin]  y  =

 

  Usually I have  x =3D y , = and all it’s ok.

 

   In this cas= e, unfortunately,  I have  x > y ,

 

=    the Check Parser don’t generate any Errors (or Warnings)= .

   <= /o:p>

   Is that correct= ?    Is this a feasible condition?

   That means that the  x – y &n= bsp;pins (out of Package) will work without parasitic elements? =

 

   (to complete this comment I have to say that= if  y > x , the Parser generate Errors, like this:

    ERROR – Pin ‘= ;A5’ found in package_model ‘Pack1’ Pin_numbers list not = found in Component ‘COMP1’ Pin list)

 

 

Thanks for any sugge= stions,

Regards,<= /span>

 

Fabio

&= nbsp;

 

   


--
This message has been scanned for viruses and
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believed to be clean.


--=20
This message has been scanned for viruses and
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believed to be clean. - --_000_A66C83F04198D24E82D005D1C2D51A300DE9DCC958MAILSJ4global_-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 3 Feb 2014 15:50:02 -0500 From: Scott McMorrow Subject: [IBIS-Users] Re: [IBIS] Overclocking effect with composite current - --e89a8f234a25f24b9d04f186aad1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable joy we at Teraspeed would like to see comparisons between physical measurements and simulation that validate your proposed approach. Without this, your approach is an interesting academic exercise in translating from one approximate modeling format (Spice) to another approximate modeling format (Cadence-IBIS-Spice). You may be solving a problem, but not "the problem." I recognize that "the problem" may not be solved without non-linear modeling. regards, Scott On Mon, Feb 3, 2014 at 2:45 PM, Joy Li wrote: > Hi Rinsha, > > > > At this time, there is no further documentation available publicly. > > > > To enable the industry to consolidate on a single approach, we may at some > time in the future disclose more details concerning our approach to the > IBIS committee for consideration as part of the standard or best practices > documentation. > > > > Joy Li > > Cadence > > > > *From:* owner-ibis@eda.org [mailto:owner-ibis@eda.org] *On Behalf Of *Rin= sha > Reghunath > *Sent:* Monday, February 03, 2014 9:29 AM > *To:* ibis@eda.org; ibis-users@eda.org > *Subject:* [IBIS] Overclocking effect with composite current > > > > Hello, > > > > The following paper discusses about the solution for overclocking with > composite current: http://www.eda.org/ibis/summits/nov13c/sun.pdf > > > > Is there any other documentation further explaining this technique or > could someone please give more insight on this? > > > > Thanks, > > Rinsha > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > - --=20 Scott McMorrow Teraspeed Consulting Group LLC 16 Stormy Brook Rd Falmouth, ME 04105 (401) 284-1827 Business http://www.teraspeed.com Teraspeed=AE is the registered service mark of Teraspeed Consulting Group LLC - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --e89a8f234a25f24b9d04f186aad1 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
joy

we at Teraspeed would like to see c= omparisons between physical measurements and simulation that validate your = proposed approach. Without this, your approach is an interesting academic e= xercise in translating from one approximate modeling format (Spice) to anot= her approximate modeling format (Cadence-IBIS-Spice). =A0You may be solving= a problem, but not "the problem." =A0I recognize that "the = problem" may not be solved without non-linear modeling.

regards,

Scott



On Mon, Feb 3, 2014 at 2:45 PM, Joy Li <joyli@cadence.com> wrote:

Hi Rinsha,=

=A0

At this time, th= ere is no further documentation available publicly.

=A0

To enable the industry to consolidate o= n a single approach, we may at some time in the future disclose more detail= s concerning our approach to the IBIS committee for consideration as part o= f the standard or best practices documentation.

=A0

Joy Li=

Cadence=

=A0

From:<= span style=3D"font-size:10.0pt;font-family:"Tahoma","sans-se= rif""> owner-i= bis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Rinsha Reghunath
Sent: Monday, February 03, 2014 9:29 AM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS] Overclocking effect with composite current

=A0=

Hello,

<= u>=A0

The following paper discusses ab= out the solution for overclocking with composite current: http://www.eda.= org/ibis/summits/nov13c/sun.pdf

=A0

Is there= any other documentation further explaining this technique or could someone= please give more insight on this?

= =A0

Thanks,

Rins= ha


--
This= message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


--=20
This message has been scanned for viruses and
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--

Scott Mc= Morrow
Teraspeed Consulting Group LLC
16 Stormy Brook Rd
Falmouth,= ME 04105

(401) 284-1827 Business

http://www.teraspeed.com

Teraspeed=AE is the registered service mark of
Teraspeed Consulting = Group LLC



--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - --e89a8f234a25f24b9d04f186aad1-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Mon, 3 Feb 2014 17:35:48 -0500 From: Scott McMorrow Subject: [IBIS-Users] Re: [IBIS] Overclocking effect with composite current - --047d7b1636c32b060504f18825ce Content-Type: text/plain; charset=ISO-8859-1 brad since power aware models require modeling of the device physics, the redistribution layer, and the package, it seems to me that a comprehensive physical model correlation effort is necessary to show that you actually can show modeling correlation to physical measurements. If your modeling is correct, there is no reason why very excellent waveform overlay cannot be accomplished, especially in the presence of power system impairments. to do otherwise would be design malpractice, as designers will use these models and simulations for design sign-off. you have reached an important milestone insofar as being able to model the overclocked buffer with all power impairments. Now go to the next step to show that your approach matches physical measurements. If it does, you have an incredible case to make. If not, it would provide interesting information about weaknesses in the methods, or areas that require additional modeling support. Ether way Cadence and the ibis cmmunity win On Mon, Feb 3, 2014 at 4:58 PM, Bradley Brim wrote: > Hi Scott, > > > > We began to discuss this topic last Friday afternoon at the IBIS Summit in > Santa Clara ... > > I understand your points now and then as: > > (1) Even a transistor-level model may not represent all the relevant > behavior of some buffers > > (2) Converting a transistor-level model to an IBIS model does not > address (1) > > (3) To address (1) a more complex nonlinear transistor-level model is > likely required > > Completely agree with all these points. Your points are not specific to > the contribution of the paper cited by Rinsha originally presented in Japan > or the follow-up paper presented last Friday in Santa Clara. > > > > We believe it is highly interesting and much more than an academic > exercise to enable the application of IBIS models instead of > transistor-level models. Why? Because for analyses such as SSO where > multiple buffers are applied transient circuit simulation times may be > literally days when transistor-level models are applied versus minutes when > IBIS buffers are applied. Memory consumption is also dramatically reduced. > For specific example please refer to Romi Mayder's paper from DesignCon > 2013: *"Simulating Simultaneous Switching Noise with IBIS v5.0 Models"*. > That paper demonstrates the successful application of BIRDs 95 and 98 for > power-aware IBIS models with quantitative comparisons. The paper cited by > Rinsha and the similar paper in last Friday's IBIS Summit discuss an > extension to over-clocking for such power-aware models. > > > > Correlation to physical measurements would help judge the quality of > present transistor-level models and guide the development of more complex > nonlinear transistor-level models. However, the efforts of enabling more > efficient (w.r.t both time and memory) simulations with IBIS models should > be judged on correlation between existing transistor-level models and the > IBIS macromodels applied in their stead. One could envision producing > power-aware IBIS models directly from measurements, but as your colleague > Tom Dagostino pointed out last Friday in the IBIS Summit, the required PDN > current measurements are extremely difficult (if not impossible) to perform > with the required accuracy. The correlation with which you seem to be > concerned is less the added detail of overclocking and more one of the core > IBIS macromodel itself. > > > > I don't recall the effects you cited as specific concern last Friday but > another common concern is that pre-driver currents may be from a different > power rail than for the analog portion of the buffer. This is not supported > by the IBIS topology with its present single-rail power. > > > > Suggest you document your specific concerns with transistor-level and IBIS > macromodel representation for consideration by IBIS-ATM. > > > > Best regards, > > -Brad > > > > *From:* owner-ibis@eda.org [mailto:owner-ibis@eda.org] *On Behalf Of *Scott > McMorrow > *Sent:* Monday, February 03, 2014 12:50 PM > > *To:* Joy Li > *Cc:* Rinsha Reghunath; ibis@eda.org; ibis-users@eda.org > *Subject:* Re: [IBIS] Overclocking effect with composite current > > > > joy > > > > we at Teraspeed would like to see comparisons between physical > measurements and simulation that validate your proposed approach. Without > this, your approach is an interesting academic exercise in translating from > one approximate modeling format (Spice) to another approximate modeling > format (Cadence-IBIS-Spice). You may be solving a problem, but not "the > problem." I recognize that "the problem" may not be solved without > non-linear modeling. > > > > regards, > > > > Scott > > > > > > On Mon, Feb 3, 2014 at 2:45 PM, Joy Li wrote: > > Hi Rinsha, > > At this time, there is no further documentation available publicly. > > To enable the industry to consolidate on a single approach, we may at some > time in the future disclose more details concerning our approach to the > IBIS committee for consideration as part of the standard or best practices > documentation. > > Joy Li > Cadence > > *From:* owner-ibis@eda.org [mailto:owner-ibis@eda.org] *On Behalf Of *Rinsha > Reghunath > *Sent:* Monday, February 03, 2014 9:29 AM > *To:* ibis@eda.org; ibis-users@eda.org > *Subject:* [IBIS] Overclocking effect with composite current > > Hello, > > The following paper discusses about the solution for overclocking with > composite current: http://www.eda.org/ibis/summits/nov13c/sun.pdf > > Is there any other documentation further explaining this technique or > could someone please give more insight on this? > > Thanks, > Rinsha > > > - -- Scott McMorrow Teraspeed Consulting Group LLC 16 Stormy Brook Rd Falmouth, ME 04105 (401) 284-1827 Business http://www.teraspeed.com Teraspeed(R) is the registered service mark of Teraspeed Consulting Group LLC - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - --047d7b1636c32b060504f18825ce Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
brad

since power aware models require m= odeling of the device physics, the redistribution layer, and the package, i= t seems to me that a comprehensive physical model correlation effort is nec= essary to show that you actually can show modeling correlation to physical = measurements.  If your modeling is correct, there is no reason why ver= y excellent waveform overlay cannot be accomplished, especially in the pres= ence of power system impairments.  to do otherwise would be design mal= practice, as designers will use these models and simulations for design sig= n-off.

you have reached an important milestone insofar as bein= g able to model the overclocked buffer with all power impairments.  No= w go to the next step to show that your approach matches physical measureme= nts.   If it does, you have an incredible case to make.  If not, = it would provide interesting information about weaknesses in the methods, o= r areas that require additional modeling support.  Ether way Cadence a= nd the ibis cmmunity win




On Mon, Feb 3, 2014 at 4:58 PM, Bradley Brim <bradb= @cadence.com> wrote:

Hi Scott,<= /u>

 

We began to discuss= this topic last Friday afternoon at the IBIS Summit in Santa Clara &hellip= ;

I understand your points = now and then as:

    (1) Even a transistor-level model may no= t represent all the relevant behavior of some buffers<= /p>

    (2) Co= nverting a transistor-level model to an IBIS model does not address (1)<= /u>

    (3) To= address (1) a more complex nonlinear transistor-level model is likely requ= ired

Completely agree with all= these points.  Your points are not specific to the contribution of th= e paper cited by Rinsha originally presented in Japan or the follow-up pape= r presented last Friday in Santa Clara.

 

We believe it is hi= ghly interesting and much more than an academic exercise to enable the appl= ication of IBIS models instead of transistor-level models. Why? Because for= analyses such as SSO where multiple buffers are applied transient circuit = simulation times may be literally days when transistor-level models are app= lied versus minutes when IBIS buffers are applied. Memory consumption is al= so dramatically reduced. For specific example please refer to Romi Mayder&r= squo;s paper from DesignCon 2013: "Simulating = Simultaneous Switching Noise with IBIS v5.0 Models". That paper demonstrates the successful applicatio= n of BIRDs 95 and 98 for power-aware IBIS models with quantitative comparis= ons. The paper cited by Rinsha and the similar paper in last Friday’s= IBIS Summit discuss an extension to over-clocking for such power-aware mod= els.

 

Correlation to phys= ical measurements would help judge the quality of present transistor-level = models and guide the development of more complex nonlinear transistor-level= models. However, the efforts of enabling more efficient (w.r.t both time a= nd memory) simulations with IBIS models should be judged on correlation bet= ween existing transistor-level models and the IBIS macromodels applied in t= heir stead. One could envision producing power-aware IBIS models directly f= rom measurements, but as your colleague Tom Dagostino pointed out last Frid= ay in the IBIS Summit, the required PDN current measurements are extremely = difficult (if not impossible) to perform with the required accuracy. The co= rrelation with which you seem to be concerned is less the added detail of o= verclocking and more one of the core IBIS macromodel itself.<= /span>

 

I don’t recal= l the effects you cited as specific concern last Friday but another common = concern is that pre-driver currents may be from a different power rail than= for the analog portion of the buffer. This is not supported by the IBIS to= pology with its present single-rail power.

 

Suggest you documen= t your specific concerns with transistor-level and IBIS macromodel represen= tation for consideration by IBIS-ATM.

 

Best regards,

-Brad

 

From: owner-ibis@eda.or= g [mailto:owner= - -ibis@eda.org] On Behalf Of Scott McMorrow
Sent: Monday, February 03, 2014 12:50 PM


To: Joy Li
Cc: Rinsha Reghunath; ibis@eda.org; ibis-users@eda.org
Subject: Re: [IBIS] Overclocking effect with composite current=

=  

joy

 

we at Teraspeed w= ould like to see comparisons between physical measurements and simulation t= hat validate your proposed approach. Without this, your approach is an inte= resting academic exercise in translating from one approximate modeling form= at (Spice) to another approximate modeling format (Cadence-IBIS-Spice). &nb= sp;You may be solving a problem, but not "the problem."  I r= ecognize that "the problem" may not be solved without non-linear = modeling.

 

regards,

 

Scott=

 

 

On Mon, Feb 3, 2014 at 2:45 PM, Joy Li <joyli@cadence.com> w= rote:

Hi Rinsha,

At this time, there is no further doc= umentation available publicly.<= u>

To enable the industry= to consolidate on a single approach, we may at some time in the future dis= close more details concerning our approach to the IBIS committee for consid= eration as part of the standard or best practices documentation.

Joy Li
Cadence

From: owner-ibis@eda.org [ma= ilto:owner-ibis@eda= .org] On Behalf Of Rinsha Reghunath
Sent: Monday, February 03, 2014 9:29 AM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS] Overclocking effect with composite current

Hello,

The following paper d= iscusses about the solution for overclocking with composite current: http= ://www.eda.org/ibis/summits/nov13c/sun.pdf

Is there any other documentation further explaining = this technique or could someone please give more insight on this?

Thanks,=
Rinsha

 




--

Scott McMorrow
Teraspe= ed Consulting Group LLC
16 Stormy Brook Rd
Falmouth, ME 04105

(401) 284-1827 Business
=
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting = Group LLC



--=20
This message has been scanned for viruses and
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believed to be clean. - --047d7b1636c32b060504f18825ce-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #240 *************************