From: owner-ibis-users@eda.org (ibis-users) To: ibis-users-digest@eda.org Subject: ibis-users V1 #248 Reply-To: Sender: owner-ibis-users@eda.org Errors-To: owner-ibis-users@eda.org Precedence: bulk ibis-users Wednesday, November 5 2014 Volume 01 : Number 248 ---------------------------------------------------------------------- Date: Tue, 4 Nov 2014 17:28:40 -0800 From: "Bob Ross" Subject: [IBIS-Users] Asian IBIS Summit (Yokohama) - Fourth Announcement This is a multipart message in MIME format. - ------=_NextPart_000_008C_01CFF854.C7816100 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To All: The IBIS Open Forum will hold its ninth Asian IBIS Summit Meeting on Thursday, November 20, 2014 in Yokohama, Japan. We have a full program and are starting the meeting on Thursday afternoon. Note, the sign in time has changed to 12:30, and the meeting will end at 16:30. The tentative presentations and sponsors are given below An Embedded Technology Conference and Exhibition on November 19-21, 2014 is co-located with the IBIS Summit. Note that we are also holding two other Asian IBIS Summits: Shanghai, China Friday, November 14, 2014 Taipei, Taiwan Monday, November 17, 2014 Bob Ross Teraspeed Labs Yukio Masuko Cadence Design Systems - ---------------------------------------------------------------------- ASIAN IBIS SUMMIT (YOKOHAMA) FOURTH CALL FOR PARTICIPATION - ---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( Y O K O H A M A ) Time/Date: Thursday, November 20, 2014, 12:30 to 16:30 Meeting starts at 13:00 Location: Pacifico Yokohama Conference Center 1-1-1, Minato Mirai, Nishi-ku Yokohama, JAPAN URL: http://www.pacifico.co.jp/english/index.html ROOM 503 Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) IBIS Open Forum Co-sponsors (in alphabetical order): ANSYS Cadence Design Systems Cybernet Systems Mentor Graphics Corp. MoDeCH Zuken Cost: FREE, including refreshments Exhibition: Embedded Technology Conference and Exhibition Date: November 19-21,2014 URL: http://10times.com/embedded-technology-exhibition BACKGROUND This year we holding the ninth Asian IBIS Summit meeting in Japan. Several high-technology Japanese companies operate in the Tokyo and Yokohama area and are affiliated with JEITA and IBIS. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and in Japanese. Presenters may deliver in Japanese, but the presentation slides should be in English. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summit site, and meeting minutes will be issued. However no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS model development, EDA tool development and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Bob ROSS, Teraspeed Labs bob@teraspeedlabs.com Yukio MASUKO, Cadence Design Systems masuko@cadence.com SIGNUP DEADLINE: November 17, 2014 Advance registration is requested for refreshments planning. AGENDA (Tentative) 12:30 Sign in Asian IBIS Summit (Yokohama) 13:00 Presentations 14:45 Refreshments 15:00 Presentations 16:30 End of Meeting TENTATIVE PRESENTATIONS Intel Corporation Activities and Direction of IBIS Fujitsu Advanced Technology Introduction of IBIS Promotion Working Group Inconsistency of EBD (Electrical Board Description) in DDR3 DIMM KEI Systems IBIS Package Model (Past, Present, What's Next) IO Methodology Differential Buffer Using IBIS Models for PDN Simulations Cadence Design Systems True Differential IBIS Model for SerDes Analog Buffer Ericsson IBIS AMI Validation Wadow IBIS Model Engineering Application Possibility Toshiba Semiconductor & Storage Introduction of P2401 LSI-Package-Board Standard Format LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels at and near the Pacifico Yokohama can be found through internet searches. - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Labs http://www.teraspeedlabs.com bob@teraspeedlabs.com Direct: 503-246-8048 Office: 971-279-5325 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_008C_01CFF854.C7816100 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

To All:

 

The IBIS Open Forum will ho= ld its ninth Asian IBIS Summit Meeting

on Thur= sday, November 20, 2014 in Yokohama, Japan.  We have a full=

program and are starting the meeting on Thursday afterno= on.

 

Note, = the sign in time has changed to 12:30, and the meeting will

end at 16:30.  The tentative presentations and sponsors = are given

below

=  

An Embedded Technology Conference and E= xhibition on November

19-21, 2014 is co-locate= d with the IBIS Summit.

 

Note that we are also holding two other Asian IBIS Summits:

 

  Shan= ghai, China   Friday, November 14, 2014

  Taipei, Taiwan    Monday, November 17, 2014<= /o:p>

 

Bob Ross

Teraspeed Labs

&nb= sp;

Yukio Masuko

Caden= ce Design Systems

 

------------------------------------------------------------------= - ----

       = ;            &n= bsp;     ASIAN IBIS SUMMIT (YOKOHAMA)=

          &nb= sp;            = FOURTH CALL FOR PARTICIPATION

---------------= - -------------------------------------------------------

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~

 

&nbs= p;         A S I A N   I = B I S   S U M M I T   ( Y O K O H A M A )

 

Time/Date:  Thursd= ay, November 20, 2014, 12:30 to 16:30

 &n= bsp;          Meeting starts a= t 13:00

 

= Location:   Pacifico Yokohama Conference Center=

          &nb= sp; 1-1-1, Minato Mirai, Nishi-ku

  =           Yokohama, JAPAN=

 

URL: &nbs= p;      http://www.pacifico.co.jp/english/index.ht= ml

 

ROOM&nb= sp;       503

=  

Content:    Presentation= s and Discussions

 

Purpose:    Solicit and Exchange IBIS Model Related= Information

     &nb= sp;      and Ideas.

=  

Organizational Sponsors:

          =   Japan Electronics and Information Technology Industries

         &nbs= p;     Association (JEITA)

            IBIS Op= en Forum

 

= Co-sponsors (in alphabetical order):

 &nb= sp;          ANSYS<= /span>

         &nb= sp;  Cadence Design Systems

  &= nbsp;         Cybernet Systems=

        &n= bsp;   Mentor Graphics Corp.

 &= nbsp;          MoDeCH

         =    Zuken

 

Cost:       FREE, including refreshm= ents

 

Exhib= ition: Embedded Technology Conference and Exhibition

<= p class=3DMsoPlainText>Date:       November 19-21,2014

URL:        http:= //10times.com/embedded-technology-exhibition

=  

 

BAC= KGROUND

   This year we holding the = ninth Asian IBIS Summit meeting in Japan.

&nbs= p;  Several high-technology Japanese companies operate in the Tokyo

   and Yokohama area and are affiliate= d with JEITA and IBIS.

 

   Our objective is to reach out internationally to = communicate with

   the local expe= rts and to learn of regional concerns.

&n= bsp;

CONFERENCE LANGUAGE

   The conference language= is English, but we will plan for technical

=    translations in English and in Japanese. Presenters may delive= r in

   Japanese, but the presentati= on slides should be in English.

 

IBIS SUMMIT

 <= /o:p>

   This meeting will be conducted as a fo= rmal IBIS Summit Meeting.

   Present= ations will be archived in an electronic format on our

   Summit site, and meeting minutes will be issued. Howe= ver no formal

   decisions req= uiring votes will be planned.

=  

CALL FOR PARTICIPANTS

 

   People involved in IBIS model = development, EDA tool development and

 &n= bsp; digital circuit design are invited to participate in the Summit

   meeting. If you plan to participate, pl= ease register with the

   informatio= n below:

 

=      Name:

  &nb= sp;  E-mail address:

 

     Company:

     Top-level Web Link:

     Country:

 

  = Send to BOTH:

 

     Bob ROSS, Teraspeed Labs   &nb= sp;            bob@t= eraspeedlabs.com

     Yu= kio MASUKO, Cadence Design Systems    masuko@cadence.com

 

   = SIGNUP DEADLINE: November 17, 2014

 =

     Advance registration is r= equested for refreshments planning.

 = ;

AGENDA (Tentative)

=  

   12:30    Si= gn in Asian IBIS Summit (Yokohama)

  = ; 13:00    Presentations

 =   14:45    Refreshments

=    15:00    Presentations

   16:30    End of Meeting<= /p>

 

TENTATIVE PRESENTATIONS

 

   = Intel Corporation

     Ac= tivities and Direction of IBIS

 

   Fujitsu Advanced Technology

     Introduction of IBIS Promotion Wor= king Group

 

     Inconsistency of EBD (Electrical Board Descriptio= n) in DDR3

      = ; DIMM

 

&nb= sp;  KEI Systems

    = IBIS Package Model (Past, Present, What's Next)

   IO Methodology

     Differential Buffer Using IBI= S Models for PDN Simulations

<= span style=3D'font-size:10.0pt;font-family:"Courier New"'> =

   Cadence Design Systems

     True Differential IBIS Model for SerDes A= nalog Buffer

 

   &nb= sp; IBIS AMI Validation

 

   Wadow

  &= nbsp;  IBIS Model Engineering Application Possibility

 

   Toshiba Semic= onductor & Storage

    = ; Introduction of P2401 LSI-Package-Board Standard Format=

 

LIST OF NEARBY HOTELS AND T= RAVEL RULES

 

   internet searches.

 

----------------------= - -------------------------------------------

=  

 

--

 <= /o:p>

Bob Ross

Teraspeed Labs

http://www.terasp= eedlabs.com

bob@teraspeedlabs.com

Direct: 503-246-8048

Office: 971-279-5325

 

 

=
--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_008C_01CFF854.C7816100-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 5 Nov 2014 21:08:29 -0800 From: "Bob Ross" Subject: [IBIS-Users] Asian IBIS Summit (Shanghai) - Agenda This is a multipart message in MIME format. - ------=_NextPart_000_0058_01CFF93C.A65BC5E0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit All: Attached is the tentative Agenda for a full meeting with 11 presentations. We look forward to seeing you in Shanghai. Registration information is at the end. Lance and Bob - ------------------------------------------------------------------ A S I A N I B I S S U M M I T I N F O R M A T I O N Time/Date: 8:15 - 17:30, Tuesday November 14, 2014 Location: Parkyard Hotel Shanghai 699 Bibo Road Zhangjiang Hi-Tech Park Shanghai 201203 P.R. China Rooms: Ballroom ABC (Look for signs) Sponsors: Huawei Technologies (Primary) ANSYS Intel Corporation IO Methodology Keysight Technologies Synopsys Teledyne LeCroy ZTE Corporation - ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 8:15 SIGN IN - Vendor Tables Open at 8:30 8:45 Welcome - Li, JinJun (Huawei Technologies, China) - Mirmak, Michael (Chair IBIS Open Forum) (Intel Corporation, USA) 9:00 Activities and Direction of IBIS Mirmak, Michael (Intel Corporation, USA) 9:25 Handling of Overclocking Caused by Delay in Waveform Tables Biernacki, Radek*; Yan, Ming*; Wolff, Randy**; Butterfield, Justin** (*Keysight Technologies, **Micron Technology, USA) 9:55 An Effective Solution to Simulate Composite Current When Over-clocking Chen, XueFeng (Synopsys, China) 10:25 BREAK (Refreshments and Vendor Tables) 10:45 True Differential IBIS Model for SerDes Analog Buffer Sharma, Shivani; Malik, Tushar; Kukal, Taranjit (Cadence Design Systems, India) 11:20 Best Practices for High-Speed Serial Link Simulation Hou, MingGang (ANSYS, China) 12:00 FREE BUFFET LUNCH (Hosted by Sponsors) - Vendor Tables 13:30 Connector Via Footprint Optimization for 25Gbps Channel Design Dai, WenLiang; Su, ZhouXiang (Xpeedic Technology, China) 14:00 Using IBIS-AMI Model for 25Gbps Retimer Simulation Wei, MaoXian; Yin, ChangGang; Zhu, ShunLin (ZTE Corporation, China) 14:30 IBIS AMI Validation Mahmod, Zilwan; Ekholm, Anders (Ericsson, Sweden) 15:00 BREAK (Refreshments and Vendor Tables) 15:20 Signing IBIS Model Against DDR4 Spec Malik, Tushar; Kukal, Taranjit (Cadence Design Systems, India) 15:55 Corner Considerations Ross, Bob (Teraspeed Labs, USA) 16:30 Ad Hoc Presentations and Discussion Skew Effect Analysis Using IBIS-AMI Model Dong, XiaoQing (Huawei Technologies, China) 17:20 CONCLUDING ITEMS 17:30 END OF IBIS SUMMIT MEETING - ------------------------------------------------------------------ To Register by November 11, 2014: Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Lance Wang, IO Methodology Inc. lwang@iometh.com Bob Ross, Teraspeed Labs bob@teraspeedlabs.com - -- Bob Ross Teraspeed Labs http://www.teraspeedlabs.com bob@teraspeedlabs.com Direct: 503-246-8048 Office: 971-279-5325 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0058_01CFF93C.A65BC5E0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

All:

<= p class=3DMsoPlainText> 

Attached is the tentative Agenda= for a full meeting with 11

presentations.&nbs= p; We look forward to seeing you in Shanghai.

=  

Registration information is at the end.=

 

Lance and= Bob

 

-----= - -------------------------------------------------------------

 

    = ;   A S I A N   I B I S   S U M M I T &n= bsp;  I N F O R M A T I O N

 

Time/Date:  8:15 - 17:30, Tuesday November 14, = 2014

 

Locat= ion:   Parkyard Hotel Shanghai

 = ;           699 Bibo Road=

       &nb= sp;    Zhangjiang Hi-Tech Park

=             Shanghai= 201203

      &n= bsp;     P.R. China

&= nbsp;

Rooms:      Ballroom= ABC (Look for signs)

 =

Sponsors:   Huawei Technologies (Primary)<= /span>

         &nb= sp;  ANSYS

     =        Intel Corporation

           = IO Methodology

     =        Keysight Technologies

          &n= bsp; Synopsys

     &n= bsp;      Teledyne LeCroy

            ZTE= Corporation

 

 

  &nb= sp;       I B I S  S U M M I T  M E= E T I N G  A G E N D A

<= span style=3D'font-size:10.0pt;font-family:"Courier New"'> =

8:15    SIGN IN

         - Vendor Tables Open a= t 8:30

 

8:4= 5    Welcome

   =        - Li, JinJun

            (Hua= wei Technologies, China)

   &nb= sp;      - Mirmak, Michael (Chair IBIS Open Forum)=

       &nb= sp;    (Intel Corporation, USA)

 

9:00    Activities and = Direction of IBIS

    &nb= sp;     Mirmak, Michael (Intel Corporation, USA)

 

= 9:25  =   Handling of Overclocking Caused by Delay in Waveform

        Tables<= /span>

          Bi= ernacki, Radek*; Yan, Ming*; Wolff, Randy**;

=           Butterfield, Justin*= *

       &n= bsp;  (*Keysight Technologies, **Micron Technology, USA)

 

9:55    = An Effective Solution to Simulate Composite Current When<= /p>

        Over-clocking

         = ; Chen, XueFeng (Synopsys, China)

 <= /o:p>

10:25   BREAK (Refreshments and Vendor Ta= bles)

 

10:4= 5   True Differential IBIS Model for SerDes Analog Buffer

         = ; Sharma, Shivani; Malik, Tushar; Kukal, Taranjit

          (Cadence Design = Systems, India)

 

11:20   Best Practices for High-Speed Serial Link Simulatio= n

       &n= bsp;  Hou, MingGang (ANSYS, China)

&= nbsp;

12:00   FREE BUFFET LUNCH (Hosted b= y Sponsors)

     &nbs= p;    - Vendor Tables

&nbs= p;

13:30   Connector Via Footprint Optimi= zation for 25Gbps Channel

   &n= bsp;    Design

=   &nbs= p;       Dai, WenLiang; Su, ZhouXiang

         = ; (Xpeedic Technology, China)

=  

14:00   Using IBIS-AMI Model for 25Gbps Retim= er Simulation

     &n= bsp;    Wei, MaoXian; Yin, ChangGang; Zhu, ShunLin

          = (ZTE Corporation, China)

 

14:30   IBIS AMI Validation

<= p class=3DMsoPlainText>          Mahmod, Zilwa= n; Ekholm, Anders (Ericsson, Sweden)

&nbs= p;

15:00   BREAK (Refreshments and Vendor= Tables)

 

= 15:20   Signing IBIS Model Against DDR4 Spec

          Malik, Tush= ar; Kukal, Taranjit

    &n= bsp;     (Cadence Design Systems, India)

 

15:55   Corner= Considerations

     =      Ross, Bob (Teraspeed Labs, USA)<= /p>

 

16:30   Ad Hoc Pr= esentations and Discussion

 

        Skew Effect Ana= lysis Using IBIS-AMI Model

   &= nbsp;      Dong, XiaoQing (Huawei Technologies, Ch= ina)

 

17:20=    CONCLUDING ITEMS

=  

17:30   END OF IBIS SUMMIT MEETING=

 

--------------------= - ----------------------------------------------

 

To Register by November 11, 2014:=

 

  &n= bsp;  Name:

     E-= mail address:

 

     Company:

 &n= bsp;   Top-level Web Link:

&nbs= p;

     Country:

 

   Send to BOT= H:

 

 &= nbsp;   Lance Wang, IO Methodology Inc.   lwang@iometh.= com

     Bob Ross, Teraspe= ed Labs          bob@teraspeed= labs.com

 

--

 <= /p>

Bob Ross

T= eraspeed Labs

http://www.teraspeedlab= s.com

bob@teraspeedlabs.com

Direct: 503-246-8048

Office: 971-279-5325

 

 


= - --=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_0058_01CFF93C.A65BC5E0-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Sun, 2 Nov 2014 16:57:48 -0800 From: "Bob Ross" Subject: [IBIS-Users] {Spam?} Asian IBIS Summit (Taipei) - Fourth Announcement This is a multipart message in MIME format. - ------=_NextPart_000_0014_01CFF6BE.22E3D750 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To All: The IBIS Open Forum is holding its fifth Asian IBIS Summit Meeting in Taiwan. We are meeting again in Taipei on Monday, November 17, 2014. The planned presentation topics are given below. Several companies listed below are co-sponsoring this major event to be held at the Sherwood Hotel in Taipei. Like in previous years, We are planning for many attendees. Other Asian IBIS Summit meetings are scheduled for: Shanghai, P.R. China, Friday November 14, Parkyard Hotel Yokohama, Japan, Thursday, November 20, Pacifico Yokohama Lance Wang IO Methodology Bob Ross Teraspeed Labs - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (TAIPEI) FOURTH CALL FOR PARTICIPATION - ----------------------------------------------------------------------- A S I A N I B I S S U M M I T ( T A I P E I ) Time/Date: Tuesday, November 17, 2014, 8:00 AM to 4:30 PM Meeting starts at 8:30 AM Location: Sherwood Hotel 11 Min Sheng E Road, Sec. 3 Taipei, Taiwan http://www.sherwood.com.tw/ Room: Tentatively Ballroom 3F Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Co-sponsors (in alphabetical order): ANSYS Cadence Design Systems Intel Corporation IO Methodology Synopsys Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND We have held many successful Summit meetings across Asia in previous years. This will be our fifth meeting in Taiwan where many national and international high technology companies have operations. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register using the information below (in English): Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Lance Wang, IO Methodology lwang@iometh.com Bob Ross, Teraspeed Labs bob@teraspeedlabs.com SIGNUP DEADLINE: November 12, 2014 AGENDA 8:00 - 8:30 Vendor table setup and tables 8:00 - 8:30 Sign in 8:30 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 16:30 Presentations TENTATIVE PRESENTATIONS Intel Corporation Activities and Direction of IBIS Keysight Technologies and Micron Technology Handling of Overclocking Caused by Delay in Waveform Tables Cadence Design Systems True Differential IBIS Model for SerDes Analog Buffer Signing IBIS Model Against DDR4 Spec IO Methodology Differential Buffer Using IBIS Models for PDN Simulations Ericsson IBIS AMI Validation Teraspeed Labs Corner Considerations ANSYS Best Practices for High-Speed Serial Link Simulation LIST OF NEARBY HOTELS AND TRAVEL Hotels in all price ranges can be found through internet searches. The conference hotel link is http://www.sherwood.com.tw/ - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Labs http://www.teraspeedlabs.com bob@teraspeedlabs.com Direct: 503-246-8048 Office: 971-279-5325 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0014_01CFF6BE.22E3D750 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

To All:

 

The IBIS Open Forum is hold= ing its fifth Asian IBIS Summit Meeting in

Tai= wan. We are meeting again in Taipei on Monday, November 17, 2014.

The planned presentation topics are given below.

 

= Several companie= s listed below are co-sponsoring this major event

to be held at the Sherwood Hotel in Taipei. Like in previous=

years, We are planning for many attendees.

 

 

Other Asian IBIS Summit meetings are scheduled for:=

 

  Shanghai, P.R= . China, Friday November 14, Parkyard Hotel

=   Yokohama, Japan, Thursday, November 20, Pacifico Yokohama=

 

Lance Wang

IO Methodology

 =

Bob Ross

Teraspeed La= bs

 

-------= - ----------------------------------------------------------------=

         &n= bsp;            = ;   ASIAN IBIS SUMMIT (TAIPEI)

 = ;            &n= bsp;         FOURTH CALL FOR PARTIC= IPATION

--------------------------------------= - ---------------------------------

 <= /o:p>

        &nb= sp;   A S I A N   I B I S   S U M M I T =   ( T A I P E I )

 

Time/Date:  Tuesday, November 17, 2014, 8:00 AM to 4:30 P= M

       &n= bsp;    Meeting starts at 8:30 AM

Location:   Sherwood Hotel=

       &nb= sp;    11 Min Sheng E Road, Sec. 3

            Taip= ei, Taiwan

 

            http://= www.sherwood.com.tw/

 <= /p>

Room:       Tentatively Ballroom 3= F

 

Content:=     Presentations and Discussions

Purpose:    Solicit a= nd exchange IBIS and interconnect model related

 

 

Co-sponsors (in alphabetical o= rder):

      &nb= sp;     ANSYS

  =           Cadence Design Syste= ms

       &= nbsp;    Intel Corporation

&nbs= p;           IO Methodolo= gy

       &= nbsp;    Synopsys

 

Cost:       FREE, incl= uding refreshments and buffet lunch

 = ;

Vendors:    Some vendors will have= information tables outside the

  &n= bsp;         meeting room

 

   &= nbsp;        Contact us for details rega= rding sponsorship.

 

BACKGROUND

 

   We have held many successful Summit meetings across = Asia in previous

   years.&nb= sp; This will be our fifth meeting in Taiwan where many national=

   and international high technology companies= have operations.

 

   Our objective is to reach out internationally to comm= unicate with

   the local experts an= d to learn of regional concerns.

 

CONFERENCE LANGUAGE

 

   The conference language is En= glish, but we will plan for technical

 &n= bsp; translations in English and Chinese.  So presenters can optionall= y

   deliver in Chinese as long as a= n English version of the material is

 &nb= sp; available.

 

IBIS SUMMIT

 

   This meeting will be conducted as a formal IBIS Summi= t Meeting.

   Presentations will be = archived in an electronic format on our

 =   Summits site, and minutes of the meeting will be issued.  Howev= er,

   no formal decisions requiring= votes will be planned.

 

CALL FOR PARTICIPANTS

 = ;

   People involved in IBIS and intercon= nect model development, EDA

   tool = development, and digital circuit design are invited to

   participate in the Summit meeting.  If you plan = to participate,

   please register u= sing the information below (in English):

=  

     Name:

     E-mail address:<= /p>

 

     Co= mpany:

     Top-level Web = Link:

 

&nbs= p;    Country:

=  

   Send to BOTH:

 

     Lance Wang, I= O Methodology      lwang@iometh.com

     Bob Ross, Teraspeed Labs  = ;      bob@teraspeedlabs.com

=

 

   SIGNUP DEADLINE: N= ovember 12, 2014

 

 

AGENDA

 

   8:00 -   8= :30  Vendor table setup and tables

 =   8:00 -   8:30  Sign in

=    8:30 -  12:00  Presentations

   12:00 - 13:30  Free buffet lunch, vendor tables

   13:30 - 16:30  Presentations

 

 <= /o:p>

TENTATIVE PRESENTATIONS

   Intel Corporation

     Activities and Direction of= IBIS

 

&nbs= p;  Keysight Technologies and Micron Technology

<= p class=3DMsoPlainText>     Handling of Overclocking Caused by Delay in= Waveform Tables

 

   Cadence Design Systems

=      True Differential IBIS Model for SerDes Analog Buf= fer

 

 =     Signing IBIS Model Against DDR4 Spec

 

   IO Methodology=

     Differential Buffer = Using IBIS Models for PDN Simulations

&nb= sp;

   Ericsson

     IBIS AMI Validation

   Teraspeed Labs

     Corner Considerations

 

<= span style=3D'font-size:10.0pt;font-family:"Courier New"'>   ANSY= S

     Best Practices for = High-Speed Serial Link Simulation

 <= /o:p>

 

LIST OF NEARBY = HOTELS AND TRAVEL

 

   Hotels in all price ranges can be found through inter= net searches.

   The conference hote= l link is

 

=    http://www.sherwood.com.tw/

=  

 

--------= - ---------------------------------------------------------=

 

 =

--

=  

Bob Ross

Teraspeed Labs

http:= //www.teraspeedlabs.com

bob@teraspeed= labs.com

Direct: 503-246-8048

Office: 971-279-5325

 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_0014_01CFF6BE.22E3D750-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 21 Oct 2014 16:38:28 -0700 From: "Bob Ross" Subject: [IBIS-Users] Asian IBIS Summit (Yokohama) - Third Announcement This is a multipart message in MIME format. - ------=_NextPart_000_00DD_01CFED4D.733A0280 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To All: The IBIS Open Forum will hold its ninth Asian IBIS Summit Meeting on Thursday, November 20, 2014 in Yokohama, Japan. We have a full program and are starting the meeting on Thursday afternoon. JEITA (Japan Electronics and Information Technology Industries Association) is the primary event sponsor. An Embedded Technology Conference and Exhibition on November 19-21, 2014 is co-located with the IBIS Summit. Note that we are also holding two other Asian IBIS Summits: Shanghai, China Friday, November 14, 2014 Taipei, Taiwan Monday, November 17, 2014 Bob Ross Teraspeed Labs Yukio Masuko Cadence Design Systems - ---------------------------------------------------------------------- ASIAN IBIS SUMMIT (YOKOHAMA) THIRD CALL FOR PARTICIPATION - ---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( Y O K O H A M A ) Time/Date: Thursday, November 20, 2014, 13:00 to 18:00 Meeting starts at 13:30 Location: Pacifico Yokohama Annex Hall 1-1-1, Minato Mirai, Nishi-ku Yokohama, JAPAN URL: http://www.pacifico.co.jp/english/index.html ROOM 503 Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) IBIS Open Forum Co-sponsors (in alphabetical order): ANSYS, Cadence Design Systems, Cybernet Systems, Mentor Graphics Corp., MoDeCH, Zuken Cost: FREE, including refreshments Exhibition: Embedded Technology Conference and Exhibition Date: November 19-21,2014 URL: http://10times.com/embedded-technology-exhibition BACKGROUND This year we holding the ninth Asian IBIS Summit meeting in Japan. Several high-technology Japanese companies operate in the Tokyo and Yokohama area and are affiliated with JEITA and IBIS. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and in Japanese. Presenters may deliver in Japanese, but the presentation slides should be in English. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summit site, and meeting minutes will be issued. However no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS model development, EDA tool development and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Bob ROSS, Teraspeed Labs bob@teraspeedlabs.com Yukio MASUKO, Cadence Design Systems masuko@cadence.com SIGNUP DEADLINE: November 17, 2014 Advance registration is requested for refreshments planning. AGENDA (Tentative) 13:00 Sign in Asian IBIS Summit (Yokohama) 13:30 Presentations 15:30 Refreshments 15:45 Presentations 18:00 End of Meeting The specific agenda is being developed. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels at and near the Pacifico Yokohama can be found through internet searches. - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Labs http://www.teraspeedlabs.com bob@teraspeedlabs.com Direct: 503-246-8048 Office: 971-279-5325 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_00DD_01CFED4D.733A0280 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

To All:

 

The IBIS Open Forum will ho= ld its ninth Asian IBIS Summit Meeting

on Thur= sday, November 20, 2014 in Yokohama, Japan.  We have a full=

program and are starting the meeting on Thursday afterno= on.

 

JEITA = (Japan Electronics and Information Technology Industries<= /p>

Association) is the primary event sponsor.  An Embedded Tec= hnology

Conference and Exhibition on November = 19-21, 2014 is co-located with

the IBIS Summit= .

 

Note tha= t we are also holding two other Asian IBIS Summits:

 

  Shanghai, China  = ; Friday, November 14, 2014

  Taipei, Tai= wan    Monday, November 17, 2014

Bob Ross

Teraspeed Labs

 

Yukio Masuko

Cadence Design Systems=

 

--------------= - --------------------------------------------------------<= /p>

          &nbs= p;            &= nbsp; ASIAN IBIS SUMMIT (YOKOHAMA)

  = ;            &n= bsp;         THIRD CALL FOR PARTICI= PATION

---------------------------------------= - -------------------------------

~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<= /p>

 

    &nb= sp;     A S I A N   I B I S   S U M= M I T   ( Y O K O H A M A )

&n= bsp;

Time/Date:  Thursday, November 20, 2014, = 13:00 to 18:00

     &= nbsp;      Meeting starts at 13:30

 

Location:   Pac= ifico Yokohama Annex Hall

   &n= bsp;        1-1-1, Minato Mirai, Nishi-k= u

       &n= bsp;    Yokohama, JAPAN

&n= bsp;

URL:       = http://www.pacifico.co.jp/english/index.html

=  

ROOM      = ;  503

 

 

Purpose:   = Solicit and Exchange IBIS Model Related Information

<= p class=3DMsoPlainText>            a= nd Ideas.

 

= Organizational Sponsors:

   &nb= sp;        Japan Electronics and Informa= tion Technology Industries

   &= nbsp;           Associati= on (JEITA)

      = ;      IBIS Open Forum

Co-sponsors (in alphabetical order):<= o:p>

       &nbs= p;    ANSYS, Cadence Design Systems, Cybernet Systems,<= /o:p>

        &nb= sp;   Mentor Graphics Corp., MoDeCH, Zuken

<= p class=3DMsoPlainText> 

Cost:    &nb= sp;  FREE, including refreshments

&n= bsp;

Exhibition: Embedded Technology Conference and= Exhibition

Date:     = ;  November 19-21,2014

URL:  &n= bsp;     http://10times.com/embedded-technology-exhibit= ion

 

&= nbsp;

BACKGROUND

 = ;  This year we holding the ninth Asian IBIS Summit meeting in Japan.<= o:p>

   Several high-technology Japanese = companies operate in the Tokyo

   an= d Yokohama area and are affiliated with JEITA and IBIS.

 

   Our objective = is to reach out internationally to communicate with

   the local experts and to learn of regional concerns.

 

CONFERENCE LA= NGUAGE

 

&nb= sp;  The conference language is English, but we will plan for technica= l

   translations in English and in = Japanese. Presenters may deliver in

 &nbs= p; Japanese, but the presentation slides should be in English.

 

IBIS SUMMIT=

 

   This me= eting will be conducted as a formal IBIS Summit Meeting.<= /p>

   Presentations will be archived in an electronic for= mat on our

   Summit site, and meeti= ng minutes will be issued. However no formal

=    decisions requiring votes will be planned.

 

CALL FOR PARTICIPANTS

 

   = ;People involved in IBIS model development, EDA tool development and

   digital circuit design are invited to p= articipate in the Summit

   meeting.= If you plan to participate, please register with the

=

   information below:

&= nbsp;

     Name:

     E-mail address:

 

     Co= mpany:

     Top-level Web = Link:

 

&nbs= p;    Country:

=  

   Send to BOTH:

 

     Bob ROSS, Ter= aspeed Labs          &nbs= p;     bob@teraspeedlabs.com

 

   SIGNUP DEADLINE: November 17, 2014=

 

   &n= bsp; Advance registration is requested for refreshments planning.

 

AGENDA (Tentative)<= o:p>

 

 &nbs= p; 13:00    Sign in Asian IBIS Summit (Yokohama)<= /span>

   13:30    Presentations

   15:30    Refreshments

   15:45    Presentatio= ns

   18:00    End of= Meeting

 

=    The specific agenda is being developed.

<= p class=3DMsoPlainText> 

 

LIST OF NEARBY HOTELS AND TRAVEL RULES

 

   Hotels at and near the Pacifi= co Yokohama can be found through

   = internet searches.

 

-----------------------------------------------------------------<= o:p>

 

--

 <= /p>

Bob Ross

T= eraspeed Labs

http://www.teraspeedlab= s.com

bob@teraspeedlabs.com

Direct: 503-246-8048

Office: 971-279-5325

 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_00DD_01CFED4D.733A0280-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Thu, 16 Oct 2014 17:16:12 -0800 From: "Bob Ross" Subject: [IBIS-Users] Asian IBIS Summit (Taipei) - Third Announcement This is a multipart message in MIME format. - ------=_NextPart_000_0059_01CFE964.E3071F90 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To All: The IBIS Open Forum is holding its fifth Asian IBIS Summit Meeting in Taiwan. We are meeting again in Taipei on Monday, November 17, 2014. Several companies listed below are co-sponsoring this major event to be held at the Sherwood Hotel in Taipei. Like in previous years, We are planning for many attendees. We encourage technical contributions from Asia. Other Asian IBIS Summit meetings are scheduled for: Shanghai, P.R. China, Friday November 14, Parkyard Hotel Yokohama, Japan, Thursday, November 20, Pacifico Yokohama Lance Wang IO Methodology Bob Ross Teraspeed Labs - ----------------------------------------------------------------------- ASIAN IBIS SUMMIT (TAIPEI) THIRD CALL FOR PARTICIPATION AND PRESENTATIONS - ----------------------------------------------------------------------- A S I A N I B I S S U M M I T ( T A I P E I ) Time/Date: Tuesday, November 17, 2014, 8:00 AM to 4:30 PM Meeting starts at 8:30 AM Location: Sherwood Hotel 11 Min Sheng E Road, Sec. 3 Taipei, Taiwan http://www.sherwood.com.tw/ Room: Tentatively Ballroom D Content: Presentations and Discussions Purpose: Solicit and exchange IBIS and interconnect model related information and ideas. Co-sponsors (in alphabetical order): ANSYS Cadence Design Systems Intel Corporation IO Methodology Synopsys Others to be determined. Cost: FREE, including refreshments and buffet lunch Vendors: Some vendors will have information tables outside the meeting room Contact us for details regarding sponsorship. BACKGROUND We have held many successful Summit meetings across Asia in previous years. This will be our fifth meeting in Taiwan where many national and international high technology companies have operations. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and Chinese. So presenters can optionally deliver in Chinese as long as an English version of the material is available. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summits site, and minutes of the meeting will be issued. However, no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS and interconnect model development, EDA tool development, and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register using the information below (in English): Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Lance Wang, IO Methodology lwang@iometh.com Bob Ross, Teraspeed Labs bob@teraspeedlabs.com SIGNUP DEADLINE: November 12, 2014 CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS and interconnect modeling experiences or issues. If we have to select presentations for the number of time slots available, we will give preferential consideration to presentations from Asia. Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Power Point or Acrobat Presentation Booklet: Available at the meeting for all attendees Presentation Deadline: October 20, 2014 to produce the presentation copies for the meeting If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. Presentations must be in English, although the delivery can be in Chinese. Submissions from Taiwan and across Asia are strongly encouraged, though submissions from other regions are very welcome. Topics may include behavioral modeling of buffers, interconnects or other system components. AGENDA 8:00 - 8:30 Vendor table setup and tables 8:00 - 8:30 Sign in 8:30 - 12:00 Presentations 12:00 - 13:30 Free buffet lunch, vendor tables 13:30 - 16:30 Presentations The specific agenda is being developed. We expect nine or ten presentations covering a range of issues from existing customer experiences, existing clarifications and some of the future directions in IBIS to deal with technical advances. Several presentations on IBIS applications and behavioral modeling issues, including interconnects and system components, are expected from co-sponsor companies and/or their customers. LIST OF NEARBY HOTELS AND TRAVEL Hotels in all price ranges can be found through internet searches. The conference hotel link is http://www.sherwood.com.tw/ - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Labs http://www.teraspeedlabs.com bob@teraspeedlabs.com Direct: 503-246-8048 Office: 971-279-5325 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_0059_01CFE964.E3071F90 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

To All:

 

The IBIS Open Forum is holding i= ts fifth Asian IBIS Summit Meeting in

Taiwan. We = are meeting again in Taipei on Monday, November 17, 2014.=

 

Several companies listed below ar= e co-sponsoring this major event

= to be held at th= e Sherwood Hotel in Taipei. Like in previous

yea= rs, We are planning for many attendees.

&nbs= p;

We encourage technical contributions from Asia.

 

Other Asian IBIS Su= mmit meetings are scheduled for:

=  

  Shanghai, P.R. China, Friday November 14, Parkyard = Hotel

  Yokohama, Japan, Thursday, November = 20, Pacifico Yokohama

 

Lance Wang

IO Methodology=

 

Bob Ross

 

-----------------------------------------------------------------------

        &nb= sp;            =     ASIAN IBIS SUMMIT (TAIPEI)

&nb= sp;            =             &nb= sp;    THIRD CALL FOR

  =             &nb= sp;       PARTICIPATION AND PRESENTATIONS

----------------------------------------------------= - -------------------

 

            A = S I A N   I B I S   S U M M I T   ( T A I P E= I )

 

Time/Date:&= nbsp; Tuesday, November 17, 2014, 8:00 AM to 4:30 PM

<= p class=3DMsoNormal>            Meet= ing starts at 8:30 AM

 

Location:   Sherwood Hotel

 =            11 Min Sheng E= Road, Sec. 3

      = ;      Taipei, Taiwan

 

       &n= bsp;    http://www.sherwood.com.tw/

Room:      = ; Tentatively Ballroom D

 =

Content:    Presentations and Discussions

 

Purpose:   = ; Solicit and exchange IBIS and interconnect model related

           = ; information and ideas.

 =

 

Co-sponsors (in alphabetical orde= r):

       &nb= sp;    ANSYS

   &nb= sp;        Cadence Design Systems

         &= nbsp;  Intel Corporation

   &= nbsp;        IO Methodology

          &= nbsp; Synopsys

     &nbs= p;      Others to be determined.=

 

Cost:    &nbs= p;  FREE, including refreshments and buffet lunch

 

Vendors:    Some vend= ors will have information tables outside the

&nb= sp;           meeting roo= m

 

  &n= bsp;         Contact us for details= regarding sponsorship.

 <= /p>

BACKGROUND

 

   years.  This wi= ll be our fifth meeting in Taiwan where many national

=

   and international high technology companies have operatio= ns.

 

  = Our objective is to reach out internationally to communicate with

   the local experts and to learn of regional c= oncerns.

 

CONFERE= NCE LANGUAGE

 

&nb= sp;  The conference language is English, but we will plan for technica= l

   translations in English and Chines= e.  So presenters can optionally

  = ; deliver in Chinese as long as an English version of the material is<= /o:p>

   available.

 

IBIS SUMMIT

&n= bsp;

   This meeting will be conducted as a = formal IBIS Summit Meeting.

   Presenta= tions will be archived in an electronic format on our

=

   Summits site, and minutes of the meeting will be issued.&= nbsp; However,

   no formal decisions r= equiring votes will be planned.

<= span style=3D'font-size:10.0pt;font-family:"Courier New"'> =

CALL FOR PARTICIPANTS

 =

   People involved in IBIS and interconnect= model development, EDA

   tool develop= ment, and digital circuit design are invited to

&= nbsp;  participate in the Summit meeting.  If you plan to partici= pate,

   please register using the info= rmation below (in English):

 

     Name:

 =     E-mail address:

 

     Company:

<= p class=3DMsoNormal>     Top-level Web Link:

=  

     Country:

 

   Send to BOT= H:

 

  &= nbsp;  Lance Wang, IO Methodology      lwang@= iometh.com

     Bob Ross, Ter= aspeed Labs        bob@teraspeedlabs.com=

 

   SI= GNUP DEADLINE: November 12, 2014

=  

CALL FOR PRESENTATIONS

&nbs= p;

   We are seeking presentations from indi= viduals who have IBIS and

   interconne= ct modeling experiences or issues.  If we have to

   select presentations for the number of time slots availa= ble, we

   will give preferential consi= deration to presentations from Asia.

 <= /o:p>

   Presentation Format:   LCD Proj= ection from meeting laptop computer

 

   Time:      &= nbsp;           15-30 Min= utes including questions

 =

   Electronic Archival:   All presentations wi= ll uploaded to our public

    = ;            &n= bsp;         IBIS Summit archives

 

<= span style=3D'font-size:10.0pt;font-family:"Courier New"'>   Elec= tronic Format:     Power Point or Acrobat

 

   Presentation B= ooklet:  Available at the meeting for all attendees<= /p>

 

   Presentation Deadline= : October 20, 2014 to produce the presentation

&n= bsp;            = ;             c= opies for the meeting

 

   If you plan a presentation, please ADD to the above regi= stration

   information:

 

     Title= of Presentation:

 

 =       (30 minutes or less)

   We will notify you of acce= ptance and may follow up with questions

 &nb= sp; when we form the program agenda.

 <= /o:p>

   Note: Vendor promotional or business info= rmation is prohibited.

   Presentations= must be in English, although the delivery can be in

<= p class=3DMsoNormal>   Chinese.

 

   Submissions from Taiwan and across Asia are strongly= encouraged,

   though submissions from= other regions are very welcome.  Topics may

   include behavioral modeling of buffers, interconnects or othe= r system

   components.

 

AGENDA

   8:00 -   8:30&nbs= p; Vendor table setup and tables

=    8:0= 0 -   8:30  Sign in

   8= :30 -  12:00  Presentations

  = ; 12:00 - 13:30  Free buffet lunch, vendor tables

   13:30 - 16:30  Presentations

<= p class=3DMsoNormal> 

   The specific agenda is be= ing developed.  We expect nine or ten

 =   presentations covering a range of issues from existing customer=

   experiences, existing clarifications and= some of the future

   directions in = IBIS to deal with technical advances.

 =

   Several presentations on IBIS applicatio= ns and behavioral modeling

   issues, i= ncluding interconnects and system components, are expected

   from co-sponsor companies and/or their customers.

 

LIST OF NEARBY HOT= ELS AND TRAVEL

 

&= nbsp;  Hotels in all price ranges can be found through internet search= es.

   The conference hotel link is

 

   http:/= /www.sherwood.com.tw/

 

 

------------------------------------= - -----------------------------

 

--

 

Bob Ross

Teraspeed Labs

bob@teraspeedlabs.= com

Direct: 503-246-8048

wrote: > Shivani, > > It is not unusual to see “no” current between the P and N > pins of a differential buffer. It all depends on how the > internal circuit of the buffer is designed. > > Thanks, > > Arpad > ========================================================== > > From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf > Of Shivani Sharma > Sent: Wednesday, October 15, 2014 12:19 PM > To: ibis-users@eda.org > Subject: [IBIS-Users] Fwd: FW: ddr103_v.scs true differential buffer IBIS > modelling > > Hi all > > I am trying to model true differential buffer following the “Series model > approach” at http://www.vhdl.org/ibis/summits/oct03/muranyi.pdf. ). > I am assuming that a differential buffer should have some sort of > differential current that would flow from PADP to PADN when the two nodes > are at different voltages. > > I am trying to sweep PADP and PADN voltages to see current between the two > PADS. However. the currents I see are in nano-Amps indicating that there is > almost no differential current. Current into PADN is almost independent of > DC-voltage forced on PADP. Is this an expected behavior or am I missing > something in this activity? > > DC sweep is applied on padn and padp is kept at different voltages (-1.2 to > 2.4 in steps of 0.4V) . > > Regards > Shivani > > > > > Detailed snapshots shown here > > > https://www.blogger.com/blogger.g?blogID=1357760498839013626#editor/target=post;postID=2986411014708903686;onPublishedMenu=posts;onClosedMenu=posts;postNum=0;src=postname > > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Fri, 17 Oct 2014 03:46:33 +0000 From: "Muranyi, Arpad" Subject: RE: [IBIS-Users] Fwd: FW: ddr103_v.scs true differential buffer IBIS modelling Shivani, In the IBIS specification we use "pseudo differential" for buffer models which make use of two single ended [Model]-s to make up a differential pair and "true differential" for buffers which make use of the [External Model] feature under [Model] to describe a differential buffer. In the end it basically boils down to your summary from an electrical point of view. If the buffer has no currents flowing between the P and the N pins, you might as well model it with two single ended [Model]s and be done... But from a modeling perspective, you can use a "true differential" model even if there is no current flow between the P and N pins, but you really don't gain any benefit from going through the extra hurdle to do it that way. Thanks, Arpad ===================================================================== - -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Shivani Sharma Sent: Thursday, October 16, 2014 10:36 PM To: ibis-users@eda.org Subject: Re: [IBIS-Users] Fwd: FW: ddr103_v.scs true differential buffer IBIS modelling Arpad, What is a true differential buffer?if there is no dc current between p and n , shouldn't it be psuedo differential buffer? since there is just cseries between p and n Thanks Shivani On 10/15/14, Muranyi, Arpad wrote: > Shivani, > > It is not unusual to see “no” current between the P and N > pins of a differential buffer. It all depends on how the > internal circuit of the buffer is designed. > > Thanks, > > Arpad > ========================================================== > > From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf > Of Shivani Sharma > Sent: Wednesday, October 15, 2014 12:19 PM > To: ibis-users@eda.org > Subject: [IBIS-Users] Fwd: FW: ddr103_v.scs true differential buffer IBIS > modelling > > Hi all > > I am trying to model true differential buffer following the “Series model > approach” at http://www.vhdl.org/ibis/summits/oct03/muranyi.pdf. ). > I am assuming that a differential buffer should have some sort of > differential current that would flow from PADP to PADN when the two nodes > are at different voltages. > > I am trying to sweep PADP and PADN voltages to see current between the two > PADS. However. the currents I see are in nano-Amps indicating that there is > almost no differential current. Current into PADN is almost independent of > DC-voltage forced on PADP. Is this an expected behavior or am I missing > something in this activity? > > DC sweep is applied on padn and padp is kept at different voltages (-1.2 to > 2.4 in steps of 0.4V) . > > Regards > Shivani > > > > > Detailed snapshots shown here > > > https://www.blogger.com/blogger.g?blogID=1357760498839013626#editor/target=post;postID=2986411014708903686;onPublishedMenu=posts;onClosedMenu=posts;postNum=0;src=postname > > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 23 Sep 2014 16:34:57 -0700 From: "Bob Ross" Subject: [IBIS-Users] Asian IBIS Summit (Yokohama) - First Announcement This is a multipart message in MIME format. - ------=_NextPart_000_00A7_01CFD74C.51586E70 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To All: The IBIS Open Forum will hold its ninth Asian IBIS Summit Meeting on Thursday, November 20, 2014 in Yokohama, Japan. We are starting Friday afternoon. JEITA (Japan Electronics and Information Technology Industries Association) is the primary event sponsor. An Embedded Technology Conference and Exhibition on November 19-21, 2014 is co-located with the IBIS Summit. Note that we are also holding two other Asian IBIS Summits: Shanghai, China Friday, November 14, 2014 Taipei, Taiwan Monday, November 17, 2014 Bob Ross Teraspeed Labs Yukio Masuko Cadence Design Systems - ---------------------------------------------------------------------- ASIAN IBIS SUMMIT (YOKOHAMA) FIRST CALL FOR PARTICIPATION - ---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( Y O K O H A M A ) Time/Date: Thursday, November 20, 2014, 13:00 to 18:00 Meeting starts at 13:30 Location: Pacifico Yokohama Annex Hall 1-1-1, Minato Mirai, Nishi-ku Yokohama, JAPAN URL: http://www.pacifico.co.jp/english/index.html ROOM TBD Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) IBIS Open Forum Co-sponsors (in alphabetical order): To Be Determined Cost: FREE, including refreshments Exhibition: Embedded Technology Conference and Exhibition Date: November 19-21,2014 URL: http://10times.com/embedded-technology-exhibition BACKGROUND This year we holding the ninth Asian IBIS Summit meeting in Japan. Several high-technology Japanese companies operate in the Tokyo and Yokohama area and are affiliated with JEITA and IBIS. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and in Japanese. Presenters may deliver in Japanese, but the presentation slides should be in English. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summit site, and meeting minutes will be issued. However no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS model development, EDA tool development and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Bob ROSS, Teraspeed Labs bob@teraspeedlabs.com Yukio MASUKO, Cadence Design Systems masuko@cadence.com SIGNUP DEADLINE: November 17, 2014 Advance registration is requested for refreshments planning. CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. Presentations from Asia are encouraged/ Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Microsoft PowerPoint or Adobe PDF Presentation Copies: Available at the meeting for all attendees PRESENTATION DEADLINE: October 24, 2014 to produce meeting copies If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. We review all submitted presentations and may request modifications. Submissions from Asia are encouraged. AGENDA (Tentative) 13:00 Sign in Asian IBIS Summit (Yokohama) 13:30 Presentations 15:30 Refreshments 15:45 Presentations 18:00 End of Meeting The specific agenda is being developed. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels at and near the Pacifico Yokohama can be found through internet searches. - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Labs http://www.teraspeedlabs.com bob@teraspeedlabs.com Direct: 503-246-8048 Office: 971-279-5325 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_00A7_01CFD74C.51586E70 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

To All:

 

The IBIS Open Forum will ho= ld its ninth Asian IBIS Summit Meeting

on Thur= sday, November 20, 2014 in Yokohama, Japan.  We are starting

Friday afternoon.

&nb= sp;

JEITA (Japan Electronics and Information Techno= logy Industries

Association) is the primary ev= ent sponsor.  An Embedded Technology

Conf= erence and Exhibition on November 19-21, 2014 is co-located with=

the IBIS Summit.

 = ;

Note that we are also holding two other Asian IBI= S Summits:

 

  Shanghai, China   Friday, November 14, 2014

  Taipei, Taiwan    Monday, November 17= , 2014

 

Bob= Ross

Teraspeed Labs

 

Yukio Masuko

<= p class=3DMsoPlainText>Cadence Design Systems

=  

-------------------------------------------------------= - ---------------

     =             &nb= sp;       ASIAN IBIS SUMMIT (YOKOHAMA)

        &nbs= p;             =    FIRST CALL FOR PARTICIPATION

----------------------------------------------------------------------

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~

 =

          A S I A = N   I B I S   S U M M I T   ( Y O K O H A M A= )

 

Time/Da= te:  Thursday, November 20, 2014, 13:00 to 18:00

=

            = Meeting starts at 13:30

 

Location:   Pacifico Yokohama Annex Hall=

         &n= bsp;  1-1-1, Minato Mirai, Nishi-ku

 = ;           Yokohama, JAP= AN

 

URL:&nb= sp;       http://www.pacifico.co.jp/english/i= ndex.html

 

= ROOM        TBD

 

Content:    Present= ations and Discussions

 

Purpose:    Solicit and Exchange IBIS Model Rel= ated Information

    &nb= sp;       and Ideas.

 

Organizational Sponsors:

         &= nbsp;  Japan Electronics and Information Technology Industries

         &nbs= p;     Association (JEITA)

            IB= IS Open Forum

 

Co-sponsors (in alphabetical order):

 = ;           To Be Determi= ned

 

Cost:&= nbsp;      FREE, including refreshments=

 

Exhibition: Embedded= Technology Conference and Exhibition

Date:&nb= sp;      November 19-21,2014

=

URL:        http://10times.com/e= mbedded-technology-exhibition

=  

 

BACKGROUND

   This year we holding the ninth Asian IBIS= Summit meeting in Japan.

   Several= high-technology Japanese companies operate in the Tokyo<= /p>

   and Yokohama area and are affiliated with JEITA and= IBIS.

 

&nb= sp;  Our objective is to reach out internationally to communicate with=

   the local experts and to learn o= f regional concerns.

 <= /p>

CONFERENCE LANGUAGE

 

   The conference language is English, but w= e will plan for technical

   transla= tions in English and in Japanese. Presenters may deliver in

   Japanese, but the presentation slides should be = in English.

 

 

   This meeting will be conducted as a formal IBIS Summit Mee= ting.

   Presentations will be archi= ved in an electronic format on our

  = ; Summit site, and meeting minutes will be issued. However no formal <= /o:p>

   decisions requiring votes will be= planned.

 

= CALL FOR PARTICIPANTS

 =

   People involved in IBIS model development, EDA too= l development and

   digital circui= t design are invited to participate in the Summit

   meeting. If you plan to participate, please register with = the

   information below:=

 

   &n= bsp; Name:

     E-mail add= ress:

 

&nbs= p;    Company:

=   &nbs= p;  Top-level Web Link:

<= span style=3D'font-size:10.0pt;font-family:"Courier New"'> =

     Country:

<= p class=3DMsoPlainText> 

   Send to BOTH:<= /o:p>

 

  &nb= sp;  Bob ROSS, Teraspeed Labs       = ;         bob@teraspeedlabs.com

     Yukio MASUKO, Cadence De= sign Systems    masuko@cadence.com

 

   SIGNUP DEADLINE: Novem= ber 17, 2014

 

 

 

CALL FOR PRESENTATIONS

 

   We are se= eking presentations from individuals who have IBIS

   experiences or issues.  Presentations from Asia are = encouraged/

 

   Time: &nb= sp;            =     15-30 Minutes including questions

<= p class=3DMsoPlainText>   Electronic Archival:   All presentations will= uploaded to our

    &nb= sp;            =          public IBIS Summit ar= chives

   Electronic Format: &n= bsp;   Microsoft PowerPoint or Adobe PDF

   Presentation Copies:   Available at the meeting= for all attendees

 

   PRESENTATION DEADLINE: October 24, 2014 to produce me= eting copies

 

   information:

 

    = Title of Presentation:

 

     Estimated Time:

       (30 minutes or less)

 

   We wi= ll notify you of acceptance and may follow up with questions

   when we form the program agenda.

 

   Note: Vendo= r promotional or business information is prohibited.

<= p class=3DMsoPlainText>   We review all submitted presentations and may request <= o:p>

   modifications.

 

   Submission= s from Asia are encouraged.

 <= /span>

AGENDA (Tentative)

&nbs= p;

   13:00    Sign in Asi= an IBIS Summit (Yokohama)

   13:30&n= bsp;   Presentations

   15= :30    Refreshments

  = ; 15:45    Presentations

 =   18:00    End of Meeting

=  

   The specific agenda is bei= ng developed.

 

 

LIST OF NEARBY HOTELS AND TRAVEL RU= LES

 

 =   Hotels at and near the Pacifico Yokohama can be found through

   internet searches.

 

------------------------------= - -----------------------------------

 = ;

--

 

Bob Ross

Teraspeed Labs

http://www.teraspeedlabs.com

bob@t= eraspeedlabs.com

Direct: 503-246-8048=

Office: 971-279-5325

<= p class=3DMsoPlainText> 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_00A7_01CFD74C.51586E70-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Tue, 7 Oct 2014 19:55:05 -0700 From: "Bob Ross" Subject: [IBIS-Users] Asian IBIS Summit (Yokohama) - Second Announcement This is a multipart message in MIME format. - ------=_NextPart_000_00B0_01CFE268.97B2FE40 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To All: The IBIS Open Forum will hold its ninth Asian IBIS Summit Meeting on Thursday, November 20, 2014 in Yokohama, Japan. We are starting Friday afternoon. JEITA (Japan Electronics and Information Technology Industries Association) is the primary event sponsor. An Embedded Technology Conference and Exhibition on November 19-21, 2014 is co-located with the IBIS Summit. Note that we are also holding two other Asian IBIS Summits: Shanghai, China Friday, November 14, 2014 Taipei, Taiwan Monday, November 17, 2014 Bob Ross Teraspeed Labs Yukio Masuko Cadence Design Systems - ---------------------------------------------------------------------- ASIAN IBIS SUMMIT (YOKOHAMA) SECOND CALL FOR PARTICIPATION - ---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A S I A N I B I S S U M M I T ( Y O K O H A M A ) Time/Date: Thursday, November 20, 2014, 13:00 to 18:00 Meeting starts at 13:30 Location: Pacifico Yokohama Annex Hall 1-1-1, Minato Mirai, Nishi-ku Yokohama, JAPAN URL: http://www.pacifico.co.jp/english/index.html ROOM TBD Content: Presentations and Discussions Purpose: Solicit and Exchange IBIS Model Related Information and Ideas. Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) IBIS Open Forum Co-sponsors (in alphabetical order): ANSYS, Cadence Design Systems, Cybernet Systems, Mentor Graphics Corp., MoDeCH, Zuken Cost: FREE, including refreshments Exhibition: Embedded Technology Conference and Exhibition Date: November 19-21,2014 URL: http://10times.com/embedded-technology-exhibition BACKGROUND This year we holding the ninth Asian IBIS Summit meeting in Japan. Several high-technology Japanese companies operate in the Tokyo and Yokohama area and are affiliated with JEITA and IBIS. Our objective is to reach out internationally to communicate with the local experts and to learn of regional concerns. CONFERENCE LANGUAGE The conference language is English, but we will plan for technical translations in English and in Japanese. Presenters may deliver in Japanese, but the presentation slides should be in English. IBIS SUMMIT This meeting will be conducted as a formal IBIS Summit Meeting. Presentations will be archived in an electronic format on our Summit site, and meeting minutes will be issued. However no formal decisions requiring votes will be planned. CALL FOR PARTICIPANTS People involved in IBIS model development, EDA tool development and digital circuit design are invited to participate in the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Bob ROSS, Teraspeed Labs bob@teraspeedlabs.com Yukio MASUKO, Cadence Design Systems masuko@cadence.com SIGNUP DEADLINE: November 17, 2014 Advance registration is requested for refreshments planning. CALL FOR PRESENTATIONS We are seeking presentations from individuals who have IBIS experiences or issues. Presentations from Asia are encouraged/ Presentation Format: LCD Projection from meeting laptop computer Time: 15-30 Minutes including questions Electronic Archival: All presentations will uploaded to our public IBIS Summit archives Electronic Format: Microsoft PowerPoint or Adobe PDF Presentation Copies: Available at the meeting for all attendees PRESENTATION DEADLINE: October 24, 2014 to produce meeting copies If you plan a presentation, please ADD to the above registration information: Title of Presentation: Estimated Time: (30 minutes or less) We will notify you of acceptance and may follow up with questions when we form the program agenda. Note: Vendor promotional or business information is prohibited. We review all submitted presentations and may request modifications. Submissions from Asia are encouraged. AGENDA (Tentative) 13:00 Sign in Asian IBIS Summit (Yokohama) 13:30 Presentations 15:30 Refreshments 15:45 Presentations 18:00 End of Meeting The specific agenda is being developed. LIST OF NEARBY HOTELS AND TRAVEL RULES Hotels at and near the Pacifico Yokohama can be found through internet searches. - ----------------------------------------------------------------- - -- Bob Ross Teraspeed Labs http://www.teraspeedlabs.com bob@teraspeedlabs.com Direct: 503-246-8048 Office: 971-279-5325 - -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ------=_NextPart_000_00B0_01CFE268.97B2FE40 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

To All:

 =

The I= BIS Open Forum will hold its ninth Asian IBIS Summit Meeting

on= Thursday, November 20, 2014 in Yokohama, Japan.  We are starting=

Friday afternoon.

 

JEITA (Japan Elec= tronics and Information Technology Industries

Association) is t= he primary event sponsor.  An Embedded Technology

Conferen= ce and Exhibition on November 19-21, 2014 is co-located with

th= e IBIS Summit.

 

Note that we are also holding= two other Asian IBIS Summits:

 

  Shangh= ai, China   Friday, November 14, 2014

  Taipei, = Taiwan    Monday, November 17, 2014

 <= /o:p>

Bob Ross

Teraspeed Labs

 

Y= ukio Masuko

Cadence Design Systems

 

          &nbs= p;            &= nbsp; ASIAN IBIS SUMMIT (YOKOHAMA)

    &nbs= p;            &= nbsp;      SECOND CALL FOR PARTICIPATION

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~

 

      &= nbsp;   A S I A N   I B I S   S U M M I T&nbs= p;  ( Y O K O H A M A )

<= span style=3D'font-family:"Courier New"'> 

Time/Date: = ; Thursday, November 20, 2014, 13:00 to 18:00

   = ;         Meeting starts at 13:30

 

Location:   Pacifico Yokohama Anne= x Hall

         &n= bsp;  1-1-1, Minato Mirai, Nishi-ku

   &nbs= p;        Yokohama, JAPAN

 

URL:        http://www.= pacifico.co.jp/english/index.html

 

<= p class=3DMsoPlainText>ROOM =        TBD

 

Con= tent:    Presentations and Discussions

=

&nbs= p;

Purpose:    Solicit and Exchange IBIS Model Relate= d Information

        &= nbsp;   and Ideas.

<= span style=3D'font-family:"Courier New"'> 

Organizational = Sponsors:

         = ;   Japan Electronics and Information Technology Industries<= /o:p>

           &n= bsp;   Association (JEITA)

    &n= bsp;       IBIS Open Forum<= /p>

&= nbsp;

Co-sponsors (in alphabetical order):

  &= nbsp;         ANSYS, Cadence Design= Systems, Cybernet Systems,

      = ;      Mentor Graphics Corp., MoDeCH, Zuken

 

Cost:       FREE, in= cluding refreshments

 

Exhibition: Embedded Te= chnology Conference and Exhibition

Date:    = ;   November 19-21,2014

URL:    &= nbsp;   http://10times.com/embedded-technology-exhibition

 

 

BACKGROUND

=

 &nb= sp; This year we holding the ninth Asian IBIS Summit meeting in Japan.=

   Several high-technology Japanese companies operate in = the Tokyo

   and Yokohama area and are affiliated wit= h JEITA and IBIS.

 

   Our objectiv= e is to reach out internationally to communicate with

=

 &nb= sp; the local experts and to learn of regional concerns.<= /p>

&= nbsp;

CONFERENCE LANGUAGE

 

  = ; The conference language is English, but we will plan for technical

   translations in English and in Japanese. Presenters may = deliver in

   Japanese, but the presentation slides s= hould be in English.

 

IBIS SUMMIT<= /span>

 

   This meeting will be conducted as a formal= IBIS Summit Meeting.

   Presentations will be archiv= ed in an electronic format on our

   Summit site, and= meeting minutes will be issued. However no formal

  = ; decisions requiring votes will be planned.

 

CALL FOR PARTICIPANTS

 

   Peo= ple involved in IBIS model development, EDA tool development and=

   meeting. If you plan to participate, please re= gister with the

   information below:

 

     Name:

  &nbs= p;  E-mail address:

 

   = ;  Company:

     Top-level Web Link:=

 

     Country:

   Send to BOTH:

 

     Bob ROSS, Teraspeed Labs   &nb= sp;            bob@t= eraspeedlabs.com

     Yukio MASUKO, Caden= ce Design Systems    masuko@cadence.com

&nb= sp;

   SIGNUP DEADLINE: November 17, 2014

 

     Advance registration is requested f= or refreshments planning.

 

 =

 

   We a= re seeking presentations from individuals who have IBIS

 &= nbsp; experiences or issues.  Presentations from Asia are encouraged/<= o:p>

 

   Presentation Format:  = ; LCD Projection from meeting laptop computer

   Time= :            &n= bsp;     15-30 Minutes including questions

=    Electronic Archival:   All presentations will upload= ed to our

        &nbs= p;            &= nbsp;    public IBIS Summit archives<= /p>

 =   Electronic Format:     Microsoft PowerPoint or A= dobe PDF

   Presentation Copies:   Availabl= e at the meeting for all attendees

 

=

 &nb= sp; PRESENTATION DEADLINE: October 24, 2014 to produce meeting copies<= /o:p>

 

   If you plan a presentation, please A= DD to the above registration

<= span style=3D'font-family:"Courier New"'>   information:

 

     Title of Presentation:=

 

     Estimated Time:

       (30 minutes or less)

=  

   We will notify you of acceptance and may fo= llow up with questions

   when we form the program ag= enda.

 

   Note: Vendor promotional = or business information is prohibited.

   We review a= ll submitted presentations and may request

   = ;modifications.

 

   Submissions fro= m Asia are encouraged.

 

AGENDA (Tentative)

 

   13:00    Sign in= Asian IBIS Summit (Yokohama)

=    13:30  &nb= sp; Presentations

   15:30    Refresh= ments

   15:45    Presentations

   18:00    End of Meeting=

=  

   The specific agenda is being developed.

 

 

= LIST OF NEARBY HOTELS AND TRAVEL = RULES

 

   Hotels at and near the Pa= cifico Yokohama can be found through

   internet sear= ches.

 

--------------------------------------= - ---------------------------

 

 

--=

 

Bo= b Ross

Teraspeed Labs

<= p class=3DMsoPlainText>http://www.teraspeedlabs.com

bob@teraspeedlabs.com

Direct: 503-246-8048

Office: 971-279= - -5325

 

 


--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ------=_NextPart_000_00B0_01CFE268.97B2FE40-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ Date: Wed, 15 Oct 2014 14:00:58 +0800 From: abhishek goswami Subject: [IBIS-Users] Re: Regarding IBIS Validation - ---488649105-269005109-1413352858=:24562 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Hi All, I am not very expert in IBIS modelling and have very small query. In our sy= stem, we have tool which generate IBIS file and contain information about r= ise and fall waveform. In current scenario, I have to change r_fixture valu= e and need to generate IBIS file. I am able to generate IBIS file and conta= in all data points. I want to very all data points which is present in IBIS= file. Is there any tool/mythology available to verify IBIS data points. I= have run ibischk5 and did not get any error. In brief, I want to verify al= l points in IBIS. =20 Thanks Abhishek Goswami Phone No -07829580867/9962270999 Skype : abhishekgoswami1 - --=20 This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. - ---488649105-269005109-1413352858=:24562 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable
Hi All,
<= div style=3D"font-family: arial, helvetica, sans-serif; font-size: 16px;"><= div style=3D"font-family: HelveticaNeue, Helvetica Neue, Helvetica, Arial, = Lucida Grande, Sans-Serif; font-size: 12px;">
=
I am n= ot very expert in IBIS modelling and have very small query. In our system, = we have tool which generate IBIS file and contain information about rise an= d fall waveform. In current scenario, I have to change r_fixture value and = need to generate IBIS file. I am able to generate IBIS file and contain all= data points. I want to very all data points which is present in IBIS file. Is t= here any tool/mythology available to  verify IBIS data points. I have = run ibischk5 and did not get any error. In brief, I want to verify all poin= ts
in IBIS.
 
Thanks
Abhishek = Goswami
Phone No -07829580867/9962270999
Skype : abhishekgoswami1



--=20
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean. - ---488649105-269005109-1413352858=:24562-- - -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993 ------------------------------ End of ibis-users V1 #248 *************************