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From: Betty Luk <Betty@genesis-microchip.com>
To: "'Muranyi, Arpad'" <arpad.muranyi@intel.com>,
   "'ibis-users@eda.org'"
	 <ibis-users@eda.org>
Subject: RE: measuring c_comp using simulation
Date: Mon, 4 Dec 2000 09:38:01 -0500 
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Hi Arpad,
 
I'm still not clear on what you wrote in your first email about using the
correct edge rate for my buffer.  I am modelling an output buffer.  Do you
mean to use the output edge rate of my buffer (based on what load?) as the
edge rate?
 
I have also tried to use CAPTAB, but as you said, the results are quite
different from the c_meter simulation.
 
Thanks,
Betty

-----Original Message-----
From: Muranyi, Arpad [mailto:arpad.muranyi@intel.com]
Sent: Wednesday, November 29, 2000 6:03 PM
To: 'Betty Luk'; 'ibis-users@eda.org'
Cc: Muranyi, Arpad
Subject: RE: measuring c_comp using simulation


Betty,
 
I am not sure what you mean by "my buffer" and "example", but if
your buffer is a different design from what I used in the lab
exercises, I wouldn't be surprised that the input capacitance
is different.  However, I don't think that you would expect them
to be the same, so I feel I have to look for a better answer.
 
I just looked up my lab example's result file "c_meter.mt0" and
got the following data:
 
    capv    sw_i1      sw_i2      cap         temper     alter#
 
    0.     -7.947e-04  8.069e-04  1.335e-12   25.0000    1.0000  
    0.2500 -1.182e-02 -9.822e-03  1.666e-12   25.0000    1.0000  
    0.5000 -2.149e-02 -1.903e-02  2.045e-12   25.0000    1.0000  
    0.7500 -2.985e-02 -2.692e-02  2.442e-12   25.0000    1.0000  
    1.0000 -3.699e-02 -3.358e-02  2.841e-12   25.0000    1.0000  
    1.2500 -4.297e-02 -3.910e-02  3.230e-12   25.0000    1.0000  
    1.5000 -4.786e-02 -4.354e-02  3.600e-12   25.0000    1.0000  
    1.7500 -5.173e-02 -4.700e-02  3.943e-12   25.0000    1.0000  
    2.0000 -5.464e-02 -4.955e-02  4.249e-12   25.0000    1.0000  
    2.2500 -5.665e-02 -5.124e-02  4.512e-12   25.0000    1.0000  
    2.5000 -5.781e-02 -5.207e-02  4.777e-12   25.0000    1.0000  
    2.7500 -5.801e-02 -5.232e-02  4.742e-12   25.0000    1.0000  
    3.0000 -5.801e-02 -5.259e-02  4.522e-12   25.0000    1.0000  
    3.2500 -5.800e-02 -5.286e-02  4.280e-12   25.0000    1.0000  
    3.5000 -5.796e-02 -5.314e-02  4.015e-12   25.0000    1.0000  
    3.7500 -5.791e-02 -5.342e-02  3.737e-12   25.0000    1.0000  
    4.0000 -5.783e-02 -5.367e-02  3.467e-12   25.0000    1.0000  
    4.2500 -5.771e-02 -5.380e-02  3.259e-12   25.0000    1.0000  
    4.5000 -5.765e-02 -5.389e-02  3.128e-12   25.0000    1.0000  
 
from which the minimum is 1.335 pF and the maximum is 4.777 pF.
These values are clearly different from what is shown in the
plot in my presentation.  Looking at the dates I may have
corrected something in the lab examples since I prepared that
plot for the presentation, or changed the buffer, or something.
I also noticed that I did not use the results of the c_meter
simulation for the IBIS files in the "solved" directories,
which may cause even more confusion.  I must have been in a big
hurry when I did those, but the point of preparing those files
was not really to have correct content in them, it was just to
have something so that my class attendees should be able to go
on to the next step in case they were not able to get that far.
Please do not get hung up on these differences.
 
To give you an answer to which number to use, here is the rule I use:
Take the lowest number generated with the c_meter simulation file
with the fast corner conditions (usually low temp, high voltage,
fast process) and use it for the minimum C_comp, and take the
highest number from the c_meter simulation using the slow corner 
conditions (high temp, low voltage, slow process).  Average the
two for the typical value for C_comp.
 
It is important that you only sweep the chip on that voltage range
which corresponds to the signal swing.  For example, if you have a
3.3 V device with a GTL buffer, don't sweep it 0 to 3.3 V to obtain
the capacitance curve, sweep it only between 0 to 1.5 V.  The signal
will never see the capacitance values that would occur on other
voltages.
 
Also note that the edge rate at which you sweep the buffer may also
influence the results you get.  It would be advisable to set an edge
rate in the c_meter simulation which is similar to what the buffer
will see from the signal.
 
I hope this helps,
 
Arpad Muranyi
Intel Corporation
=====================================================================
 
 
 
-----Original Message-----
From: Betty Luk [mailto:Betty@genesis-microchip.com]
Sent: Wednesday, November 29, 2000 11:33 AM
To: 'ibis-users@eda.org'
Cc: 'arpad.muranyi@intel.com'
Subject: measuring c_comp using simulation


Hi,
 
In Arpad Muranyi's "Introduction to IBIS Models" (available from IBIS
website), there was a sample Spice netlist for a simulation to obtain the
value of c_comp.  When I used this simulation for my buffer, the capacitance
ranged from 2pF to 8pF, with a mean of 5pF.  In the example, the range was
only between 2 to 3pF.  Should the mean value for the simulated capacitance
be used?    What about obtaining min and max values for c_comp?
 
I would really appreciate any feedback.  I have attached the sample Spice
file for reference.
 
Thanks very much,
Betty
 
 


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<DIV><FONT color=#0000ff face=Arial size=2>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=737222617-01122000>Hi 
Arpad,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=737222617-01122000>I'm 
still not clear on what you wrote in your first email about using the correct 
edge rate for my buffer.&nbsp; I am modelling an output buffer.&nbsp; Do you 
mean to use the output edge rate of my buffer (based on what load?) as the edge 
rate?</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=737222617-01122000>I have 
also tried to use CAPTAB, but as you said, the results are quite different from 
the c_meter simulation.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000>Thanks,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000>Betty</SPAN></FONT></DIV></FONT></DIV>
<BLOCKQUOTE 
style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Muranyi, Arpad 
  [mailto:arpad.muranyi@intel.com]<BR><B>Sent:</B> Wednesday, November 29, 2000 
  6:03 PM<BR><B>To:</B> 'Betty Luk'; 'ibis-users@eda.org'<BR><B>Cc:</B> Muranyi, 
  Arpad<BR><B>Subject:</B> RE: measuring c_comp using 
  simulation<BR><BR></DIV></FONT>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>Betty,</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I am not 
  sure what you mean by "my buffer" and "example", but if</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>your 
  buffer is a different design from what I used in the lab</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>exercises, 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I 
  wouldn't be surprised that the input capacitance</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>is 
  different.&nbsp; </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>However, I don't think that you would expect 
  them</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>to be the 
  same, </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>so I feel I have to look for a better 
  answer.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I just 
  looked up my lab example's result file "c_meter.mt0" and</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>got the 
  following data:</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>&nbsp;&nbsp;&nbsp; capv&nbsp;&nbsp;&nbsp; 
  sw_i1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sw_i2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
  cap<FONT face="Courier New" 
  size=2></FONT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;temper&nbsp;&nbsp;&nbsp;&nbsp; 
  alter#</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>&nbsp;&nbsp;&nbsp; 0.&nbsp;&nbsp;&nbsp;&nbsp; 
  -7.947e-04&nbsp; 8.069e-04&nbsp; 1.335e-12&nbsp;&nbsp; 
  25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; <BR>&nbsp;&nbsp;&nbsp; 0.2500 
  -1.182e-02 -9.822e-03&nbsp; 1.666e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 
  1.0000&nbsp; <BR>&nbsp;&nbsp;&nbsp; 0.5000 -2.149e-02 -1.903e-02&nbsp; 
  2.045e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 0.7500 -2.985e-02 -2.692e-02&nbsp; 
  2.442e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 1.0000 -3.699e-02 -3.358e-02&nbsp; 
  2.841e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 1.2500 -4.297e-02 -3.910e-02&nbsp; 
  3.230e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 1.5000 -4.786e-02 -4.354e-02&nbsp; 
  3.600e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 1.7500 -5.173e-02 -4.700e-02&nbsp; 
  3.943e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 2.0000 -5.464e-02 -4.955e-02&nbsp; 
  4.249e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 2.2500 -5.665e-02 -5.124e-02&nbsp; 
  4.512e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 2.5000 -5.781e-02 -5.207e-02&nbsp; 
  4.777e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 2.7500 -5.801e-02 -5.232e-02&nbsp; 
  4.742e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 3.0000 -5.801e-02 -5.259e-02&nbsp; 
  4.522e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 3.2500 -5.800e-02 -5.286e-02&nbsp; 
  4.280e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 3.5000 -5.796e-02 -5.314e-02&nbsp; 
  4.015e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 3.7500 -5.791e-02 -5.342e-02&nbsp; 
  3.737e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 4.0000 -5.783e-02 -5.367e-02&nbsp; 
  3.467e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 4.2500 -5.771e-02 -5.380e-02&nbsp; 
  3.259e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 4.5000 -5.765e-02 -5.389e-02&nbsp; 
  3.128e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  </SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>from which 
  the minimum is 1.335 pF and the maximum is 4.777 pF.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>These 
  values are clearly different from what is shown in the</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>plot in my 
  presentation.&nbsp; Looking at the dates I may have</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>corrected 
  something in the lab examples since I prepared that</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>plot for 
  the </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>presentation, or changed the buffer, or 
  something.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I also 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>noticed that I did not use the results of the 
  c_meter</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>simulation 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>for the IBIS files in the "solved" 
  directories,</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>which may 
  cause even more </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>confusion.&nbsp; I must have been in a 
  big</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>hurry when 
  I did those, but the point of preparing those files</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>was not 
  really to have correct content in them, it was just to</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>have 
  something so that my class attendees should be able to go</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>on to the 
  next step in case they </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>were not able to get that far.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000><FONT 
  face="Courier New" size=2><SPAN class=031372822-29112000>Please 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>do not get </SPAN></FONT></SPAN></FONT><FONT 
  face="Courier New" size=2><SPAN class=031372822-29112000><FONT 
  face="Courier New" size=2><SPAN class=031372822-29112000>hung up on these 
  differences.</SPAN></FONT></SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000><FONT 
  face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>To give 
  you an answer to which number to use, here is the rule I 
  use:</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>Take the 
  lowest number generated with the c_meter simulation file</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>with the 
  fast corner conditions </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>(usually low temp, high voltage,</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>fast 
  process) and use it for the </SPAN></FONT><FONT face="Courier New" 
  size=2><SPAN class=031372822-29112000>minimum C_comp, and take 
  the</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>highest 
  number from the c_meter simulation using the slow corner </SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>conditions 
  (high temp, low voltage, slow process).&nbsp; Average the</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>two for 
  the typical value for C_comp.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>It is 
  important that you only sweep the chip on that voltage 
  range</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>which 
  corresponds to the signal swing.&nbsp; For example, if you have 
  a</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>3.3 V 
  device with a GTL buffer, don't sweep it 0 to 3.3 V to 
  obtain</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>the 
  capacitance curve, sweep it only between 0 to 1.5 V.&nbsp; The 
  signal</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>will never 
  see the capacitance values that would occur on other</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>voltages.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>Also note 
  that the edge rate at which you sweep the buffer may also</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>influence 
  the results you get.&nbsp; It would be advisable to set an 
  edge</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>rate 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>in the c_meter simulation which is similar to what 
  the buffer</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>will see 
  from the signal.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I hope 
  this helps,</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>Arpad 
  Muranyi</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>Intel 
  Corporation</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>=====================================================================</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Betty Luk 
  [mailto:Betty@genesis-microchip.com]<BR><B>Sent:</B> Wednesday, November 29, 
  2000 11:33 AM<BR><B>To:</B> 'ibis-users@eda.org'<BR><B>Cc:</B> 
  'arpad.muranyi@intel.com'<BR><B>Subject:</B> measuring c_comp using 
  simulation<BR><BR></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000>Hi,</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2><SPAN class=960512719-29112000>In Arpad Muranyi's 
  "Introduction to IBIS Models" (available from IBIS website), there was a 
  sample Spice netlist for a simulation to obtain the value of c_comp.&nbsp; 
  When I used this simulation for my buffer, the capacitance ranged from 2pF to 
  8pF, with a mean of 5pF.&nbsp; In the example, the range was only between 2 to 
  3pF.&nbsp; Should the mean value for the simulated capacitance be 
  used?&nbsp;&nbsp;&nbsp; What about obtaining min and max values for 
  c_comp?</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2><SPAN class=960512719-29112000>I would really 
  appreciate any feedback.&nbsp; I have attached the sample Spice file for 
  reference.</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2><SPAN class=960512719-29112000>Thanks very 
  much,</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000>Betty</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV></BLOCKQUOTE></BODY></HTML>

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From owner-ibis Mon Dec  4 10:38:26 2000
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "'Betty Luk'" <Betty@genesis-microchip.com>,
   "'ibis-users@eda.org'"
	 <ibis-users@eda.org>
Subject: RE: measuring c_comp using simulation
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Betty,
 
You should use an edge rate that will be close to what the
signals will look like on the output of the buffer when it is
loaded with the load that it will drive.
 
Arpad
============================================================
-----Original Message-----
From: Betty Luk [mailto:Betty@genesis-microchip.com]
Sent: Monday, December 04, 2000 6:38 AM
To: 'Muranyi, Arpad'; 'ibis-users@eda.org'
Subject: RE: measuring c_comp using simulation


Hi Arpad,
 
I'm still not clear on what you wrote in your first email about using the
correct edge rate for my buffer.  I am modelling an output buffer.  Do you
mean to use the output edge rate of my buffer (based on what load?) as the
edge rate?
 
I have also tried to use CAPTAB, but as you said, the results are quite
different from the c_meter simulation.
 
Thanks,
Betty

-----Original Message-----
From: Muranyi, Arpad [mailto:arpad.muranyi@intel.com]
Sent: Wednesday, November 29, 2000 6:03 PM
To: 'Betty Luk'; 'ibis-users@eda.org'
Cc: Muranyi, Arpad
Subject: RE: measuring c_comp using simulation


Betty,
 
I am not sure what you mean by "my buffer" and "example", but if
your buffer is a different design from what I used in the lab
exercises, I wouldn't be surprised that the input capacitance
is different.  However, I don't think that you would expect them
to be the same, so I feel I have to look for a better answer.
 
I just looked up my lab example's result file "c_meter.mt0" and
got the following data:
 
    capv    sw_i1      sw_i2      cap         temper     alter#
 
    0.     -7.947e-04  8.069e-04  1.335e-12   25.0000    1.0000  
    0.2500 -1.182e-02 -9.822e-03  1.666e-12   25.0000    1.0000  
    0.5000 -2.149e-02 -1.903e-02  2.045e-12   25.0000    1.0000  
    0.7500 -2.985e-02 -2.692e-02  2.442e-12   25.0000    1.0000  
    1.0000 -3.699e-02 -3.358e-02  2.841e-12   25.0000    1.0000  
    1.2500 -4.297e-02 -3.910e-02  3.230e-12   25.0000    1.0000  
    1.5000 -4.786e-02 -4.354e-02  3.600e-12   25.0000    1.0000  
    1.7500 -5.173e-02 -4.700e-02  3.943e-12   25.0000    1.0000  
    2.0000 -5.464e-02 -4.955e-02  4.249e-12   25.0000    1.0000  
    2.2500 -5.665e-02 -5.124e-02  4.512e-12   25.0000    1.0000  
    2.5000 -5.781e-02 -5.207e-02  4.777e-12   25.0000    1.0000  
    2.7500 -5.801e-02 -5.232e-02  4.742e-12   25.0000    1.0000  
    3.0000 -5.801e-02 -5.259e-02  4.522e-12   25.0000    1.0000  
    3.2500 -5.800e-02 -5.286e-02  4.280e-12   25.0000    1.0000  
    3.5000 -5.796e-02 -5.314e-02  4.015e-12   25.0000    1.0000  
    3.7500 -5.791e-02 -5.342e-02  3.737e-12   25.0000    1.0000  
    4.0000 -5.783e-02 -5.367e-02  3.467e-12   25.0000    1.0000  
    4.2500 -5.771e-02 -5.380e-02  3.259e-12   25.0000    1.0000  
    4.5000 -5.765e-02 -5.389e-02  3.128e-12   25.0000    1.0000  
 
from which the minimum is 1.335 pF and the maximum is 4.777 pF.
These values are clearly different from what is shown in the
plot in my presentation.  Looking at the dates I may have
corrected something in the lab examples since I prepared that
plot for the presentation, or changed the buffer, or something.
I also noticed that I did not use the results of the c_meter
simulation for the IBIS files in the "solved" directories,
which may cause even more confusion.  I must have been in a big
hurry when I did those, but the point of preparing those files
was not really to have correct content in them, it was just to
have something so that my class attendees should be able to go
on to the next step in case they were not able to get that far.
Please do not get hung up on these differences.
 
To give you an answer to which number to use, here is the rule I use:
Take the lowest number generated with the c_meter simulation file
with the fast corner conditions (usually low temp, high voltage,
fast process) and use it for the minimum C_comp, and take the
highest number from the c_meter simulation using the slow corner 
conditions (high temp, low voltage, slow process).  Average the
two for the typical value for C_comp.
 
It is important that you only sweep the chip on that voltage range
which corresponds to the signal swing.  For example, if you have a
3.3 V device with a GTL buffer, don't sweep it 0 to 3.3 V to obtain
the capacitance curve, sweep it only between 0 to 1.5 V.  The signal
will never see the capacitance values that would occur on other
voltages.
 
Also note that the edge rate at which you sweep the buffer may also
influence the results you get.  It would be advisable to set an edge
rate in the c_meter simulation which is similar to what the buffer
will see from the signal.
 
I hope this helps,
 
Arpad Muranyi
Intel Corporation
=====================================================================
 
 
 
-----Original Message-----
From: Betty Luk [mailto:Betty@genesis-microchip.com]
Sent: Wednesday, November 29, 2000 11:33 AM
To: 'ibis-users@eda.org'
Cc: 'arpad.muranyi@intel.com'
Subject: measuring c_comp using simulation


Hi,
 
In Arpad Muranyi's "Introduction to IBIS Models" (available from IBIS
website), there was a sample Spice netlist for a simulation to obtain the
value of c_comp.  When I used this simulation for my buffer, the capacitance
ranged from 2pF to 8pF, with a mean of 5pF.  In the example, the range was
only between 2 to 3pF.  Should the mean value for the simulated capacitance
be used?    What about obtaining min and max values for c_comp?
 
I would really appreciate any feedback.  I have attached the sample Spice
file for reference.
 
Thanks very much,
Betty
 
 


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<DIV><FONT face="Courier New" size=2><SPAN 
class=211133318-04122000>Betty,</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=211133318-04122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=211133318-04122000>You should 
use an edge rate that will be close to what the</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=211133318-04122000>signals will 
look like on the output of the buffer when it is</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=211133318-04122000>loaded with 
the load that it will drive.</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=211133318-04122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=211133318-04122000>Arpad</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=211133318-04122000>============================================================</SPAN></FONT></DIV>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
size=2>-----Original Message-----<BR><B>From:</B> Betty Luk 
[mailto:Betty@genesis-microchip.com]<BR><B>Sent:</B> Monday, December 04, 2000 
6:38 AM<BR><B>To:</B> 'Muranyi, Arpad'; 'ibis-users@eda.org'<BR><B>Subject:</B> 
RE: measuring c_comp using simulation<BR><BR></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=737222617-01122000>Hi 
Arpad,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=737222617-01122000>I'm 
still not clear on what you wrote in your first email about using the correct 
edge rate for my buffer.&nbsp; I am modelling an output buffer.&nbsp; Do you 
mean to use the output edge rate of my buffer (based on what load?) as the edge 
rate?</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=737222617-01122000>I have 
also tried to use CAPTAB, but as you said, the results are quite different from 
the c_meter simulation.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000>Thanks,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737222617-01122000>Betty</SPAN></FONT></DIV></FONT></DIV>
<BLOCKQUOTE 
style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Muranyi, Arpad 
  [mailto:arpad.muranyi@intel.com]<BR><B>Sent:</B> Wednesday, November 29, 2000 
  6:03 PM<BR><B>To:</B> 'Betty Luk'; 'ibis-users@eda.org'<BR><B>Cc:</B> Muranyi, 
  Arpad<BR><B>Subject:</B> RE: measuring c_comp using 
  simulation<BR><BR></DIV></FONT>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>Betty,</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I am not 
  sure what you mean by "my buffer" and "example", but if</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>your 
  buffer is a different design from what I used in the lab</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>exercises, 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I 
  wouldn't be surprised that the input capacitance</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>is 
  different.&nbsp; </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>However, I don't think that you would expect 
  them</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>to be the 
  same, </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>so I feel I have to look for a better 
  answer.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I just 
  looked up my lab example's result file "c_meter.mt0" and</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>got the 
  following data:</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>&nbsp;&nbsp;&nbsp; capv&nbsp;&nbsp;&nbsp; 
  sw_i1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sw_i2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
  cap<FONT face="Courier New" 
  size=2></FONT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;temper&nbsp;&nbsp;&nbsp;&nbsp; 
  alter#</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>&nbsp;&nbsp;&nbsp; 0.&nbsp;&nbsp;&nbsp;&nbsp; 
  -7.947e-04&nbsp; 8.069e-04&nbsp; 1.335e-12&nbsp;&nbsp; 
  25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; <BR>&nbsp;&nbsp;&nbsp; 0.2500 
  -1.182e-02 -9.822e-03&nbsp; 1.666e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 
  1.0000&nbsp; <BR>&nbsp;&nbsp;&nbsp; 0.5000 -2.149e-02 -1.903e-02&nbsp; 
  2.045e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 0.7500 -2.985e-02 -2.692e-02&nbsp; 
  2.442e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 1.0000 -3.699e-02 -3.358e-02&nbsp; 
  2.841e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 1.2500 -4.297e-02 -3.910e-02&nbsp; 
  3.230e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 1.5000 -4.786e-02 -4.354e-02&nbsp; 
  3.600e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 1.7500 -5.173e-02 -4.700e-02&nbsp; 
  3.943e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 2.0000 -5.464e-02 -4.955e-02&nbsp; 
  4.249e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 2.2500 -5.665e-02 -5.124e-02&nbsp; 
  4.512e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 2.5000 -5.781e-02 -5.207e-02&nbsp; 
  4.777e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 2.7500 -5.801e-02 -5.232e-02&nbsp; 
  4.742e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 3.0000 -5.801e-02 -5.259e-02&nbsp; 
  4.522e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 3.2500 -5.800e-02 -5.286e-02&nbsp; 
  4.280e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 3.5000 -5.796e-02 -5.314e-02&nbsp; 
  4.015e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 3.7500 -5.791e-02 -5.342e-02&nbsp; 
  3.737e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 4.0000 -5.783e-02 -5.367e-02&nbsp; 
  3.467e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 4.2500 -5.771e-02 -5.380e-02&nbsp; 
  3.259e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  <BR>&nbsp;&nbsp;&nbsp; 4.5000 -5.765e-02 -5.389e-02&nbsp; 
  3.128e-12&nbsp;&nbsp; 25.0000&nbsp;&nbsp;&nbsp; 1.0000&nbsp; 
  </SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>from which 
  the minimum is 1.335 pF and the maximum is 4.777 pF.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>These 
  values are clearly different from what is shown in the</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>plot in my 
  presentation.&nbsp; Looking at the dates I may have</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>corrected 
  something in the lab examples since I prepared that</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>plot for 
  the </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>presentation, or changed the buffer, or 
  something.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I also 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>noticed that I did not use the results of the 
  c_meter</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>simulation 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>for the IBIS files in the "solved" 
  directories,</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>which may 
  cause even more </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>confusion.&nbsp; I must have been in a 
  big</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>hurry when 
  I did those, but the point of preparing those files</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>was not 
  really to have correct content in them, it was just to</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>have 
  something so that my class attendees should be able to go</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>on to the 
  next step in case they </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>were not able to get that far.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000><FONT 
  face="Courier New" size=2><SPAN class=031372822-29112000>Please 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>do not get </SPAN></FONT></SPAN></FONT><FONT 
  face="Courier New" size=2><SPAN class=031372822-29112000><FONT 
  face="Courier New" size=2><SPAN class=031372822-29112000>hung up on these 
  differences.</SPAN></FONT></SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000><FONT 
  face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>To give 
  you an answer to which number to use, here is the rule I 
  use:</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>Take the 
  lowest number generated with the c_meter simulation file</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>with the 
  fast corner conditions </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>(usually low temp, high voltage,</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>fast 
  process) and use it for the </SPAN></FONT><FONT face="Courier New" 
  size=2><SPAN class=031372822-29112000>minimum C_comp, and take 
  the</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>highest 
  number from the c_meter simulation using the slow corner </SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>conditions 
  (high temp, low voltage, slow process).&nbsp; Average the</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>two for 
  the typical value for C_comp.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>It is 
  important that you only sweep the chip on that voltage 
  range</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>which 
  corresponds to the signal swing.&nbsp; For example, if you have 
  a</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>3.3 V 
  device with a GTL buffer, don't sweep it 0 to 3.3 V to 
  obtain</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>the 
  capacitance curve, sweep it only between 0 to 1.5 V.&nbsp; The 
  signal</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>will never 
  see the capacitance values that would occur on other</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>voltages.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>Also note 
  that the edge rate at which you sweep the buffer may also</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>influence 
  the results you get.&nbsp; It would be advisable to set an 
  edge</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>rate 
  </SPAN></FONT><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>in the c_meter simulation which is similar to what 
  the buffer</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>will see 
  from the signal.</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>I hope 
  this helps,</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>Arpad 
  Muranyi</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN class=031372822-29112000>Intel 
  Corporation</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000>=====================================================================</SPAN></FONT></DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face="Courier New" size=2><SPAN 
  class=031372822-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Betty Luk 
  [mailto:Betty@genesis-microchip.com]<BR><B>Sent:</B> Wednesday, November 29, 
  2000 11:33 AM<BR><B>To:</B> 'ibis-users@eda.org'<BR><B>Cc:</B> 
  'arpad.muranyi@intel.com'<BR><B>Subject:</B> measuring c_comp using 
  simulation<BR><BR></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000>Hi,</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2><SPAN class=960512719-29112000>In Arpad Muranyi's 
  "Introduction to IBIS Models" (available from IBIS website), there was a 
  sample Spice netlist for a simulation to obtain the value of c_comp.&nbsp; 
  When I used this simulation for my buffer, the capacitance ranged from 2pF to 
  8pF, with a mean of 5pF.&nbsp; In the example, the range was only between 2 to 
  3pF.&nbsp; Should the mean value for the simulated capacitance be 
  used?&nbsp;&nbsp;&nbsp; What about obtaining min and max values for 
  c_comp?</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2><SPAN class=960512719-29112000>I would really 
  appreciate any feedback.&nbsp; I have attached the sample Spice file for 
  reference.</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2><SPAN class=960512719-29112000>Thanks very 
  much,</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000>Betty</SPAN></FONT></DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=Arial size=2><SPAN 
  class=960512719-29112000></SPAN></FONT>&nbsp;</DIV></BLOCKQUOTE></BODY></HTML>

------_=_NextPart_001_01C05E20.E5665FF0--

 
From owner-ibis Mon Dec  4 18:47:49 2000
Received: from dns.uti2000.co.jp ([211.11.196.34])
	by server.eda.org (8.11.0/8.11.0) with ESMTP id eB52lTj04546
	for <ibis-users@eda.org>; Mon, 4 Dec 2000 18:47:30 -0800 (PST)
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Date: Tue, 05 Dec 2000 11:40:50 +0900
To: si-list@silab.eng.sun.com, ibis-users@eda.org
From: Su Ming TAI <sm_tai@uti2000.co.jp>
Subject: Questions on the relationship between IBIS model & datasheet
Mime-Version: 1.0
Content-Type: multipart/mixed;	boundary="=====================_9361210==_"

--=====================_9361210==_
Content-Type: text/plain; charset="us-ascii"; format=flowed

Dear SI & IBIS gurus,

Hi! I'm a newbie in the world of SI and I have question that some of you 
may be able to explain it to me.
I have a datasheet and an IBIS model of a same device. On the datasheet 
(see pg 4), the Ioh and Iol values are -24mA and 24mA respectively when Vcc 
is 3V.
Now, on the IBIS model, at the pullup and pulldown section, when the 
voltage is at 3V, the current are not anything near to 24mA or -24mA at all.
My question is:
1) Why is that the datasheet values do not seem to correlate with the IBIS 
model?
2) How do we know that the IBIS model is correctly generated based on the 
values from the datasheet?

I welcome any comments or explanations on this issue. Thanks.



Regards,
Su Ming TAI

--=====================_9361210==_
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--=====================_9361210==_--

 
From owner-ibis Tue Dec  5 07:57:53 2000
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'Su Ming TAI'" <sm_tai@uti2000.co.jp>
Cc: "si-list@silab.eng.sun.com" <si-list@silab.Eng.Sun.COM>,
   ibis-users@eda.org
Subject: RE: Questions on the relationship between IBIS model & datasheet
Date: Tue, 5 Dec 2000 10:54:16 -0500 
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> I have a datasheet and an IBIS model of a same device. On the datasheet 
> (see pg 4), the Ioh and Iol values are -24mA and 24mA respectively when
> Vcc 
> is 3V.
 
Those particular values mean that they do not want you to sink or source
more than 24mA at Vcc=3V.  The device may be capable of sinking or sourcing
more than that, but those are the recommended maximum output currents.

> Now, on the IBIS model, at the pullup and pulldown section, when the 
> voltage is at 3V, the current are not anything near to 24mA or -24mA at
> all.
 
Careful here.  The "voltage" that is 3V, is Vcc, the supply voltage.  It is
NOT the axis or independent variable of the [Pullup] and [Pulldown] curves!

> My question is:
> 1) Why is that the datasheet values do not seem to correlate with the IBIS
> 
> model?
 
The IBIS datasheet (IBIS model) hopefully represents actual performance of
the device.  The Spec sheet (what you called datasheet but I need to call it
something else to differentiate it from the IBIS datasheet) describes how to
use the part.  Some of the information, for example page 4, puts constraints
on how you may use it.  Other sections, for example page 5, give the
absolute worst-case performance you can (hopefully) ever expect, even when
they migrate the part to a new IC fab which could result in a different IBIS
datasheet being generated.

There is almost always some "padding" included in the Spec sheet data.  For
example, the minimum tpd (according to all simulations and projections made
by the vendor) might be 1.7ns, hypothetically, but the vendor publishes 1ns
to be safe.  It's a marketing decision.  They might not add the same amount
of "padding" to their IBIS models, which are intended to better represent
actual performance.

In other words, when comparing "apples to apples" (identical
characteristics), I would not be surprised if the Spec sheet was more
conservative than the IBIS datasheet.

But let's take a closer look at your example.  The spec sheet on page 5 has:

  Voh(min) = 2.2V  @ Vcc = 3V, Ioh = -24mA
  Vol(max) = 0.55V @ Vcc = 3V, Iol =  24mA

Voh = 2.2V means Vcc-Voutput = 0.8V.  Checking the IBIS [Pullup] curve, when
Voltage = 0.8V, I(min) = -21.8948mA, which is close to -24mA.  It doesn't
quite meet the Spec.  At Ioh = -24mA, Vcc-Vout = slightly more than 0.9V, so
Vout = slightly less than 2.1V.  Not quite 2.2V minimum.

For Vol = 0.55V, the IBIS [Pulldown] curve says I(min) = between 32.8243mA
and 38.6213mA.  For Iol = 24mA, Vout = about 0.36V.  This meets the Spec
sheet (max. 0.55V).

> 2) How do we know that the IBIS model is correctly generated based on the 
> values from the datasheet?
 
I would hope that both the IBIS datasheet and the Spec sheet are generated
from simulations and/or measurements, not one from the other.  Neither sheet
alone has sufficient information to generate the other.

The IBIS datasheet has considerably more data about I vs. V, so it could
never be generated from a Spec sheet alone, but the IBIS datasheet usually
lacks the Absolute Maximum and Recommended Maximum conditions that are
included on the Spec sheet.

Regards,
Andy

 
From owner-ibis Tue Dec  5 12:04:51 2000
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From: "Dagostino, Tom" <tom_dagostino@mentorg.com>
To: "'Ingraham, Andrew'" <Andrew.Ingraham@compaq.com>,
   "'Su Ming TAI'"
	 <sm_tai@uti2000.co.jp>
Cc: "si-list@silab.eng.sun.com" <si-list@silab.Eng.Sun.COM>,
   ibis-users@eda.org
Subject: RE: Questions on the relationship between IBIS model & datasheet
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When Vol is specified at 0.55 volts and 24 mA it means the part will put out
less than 0.55 volts when 24 ma of current is being sunk into the output.
This is what the manufacturer "guarantees".  Since the manufacturer wants to
ship all possible die from a wafer the output spec is conservative, all
parts should meet this spec.  It is not unusual to see 2 to 5 time the spec
current at the specified output voltage. If the model shows less than the
specified current at the specified voltage I would be suspect of the model.
I have rarely seen a part that would not meet its Vol or Voh spec.  I have
seen many parts that would product more current at a given voltage than the
model said it should (measured Iol at Vol was greater than the Max in the
model).  

Tom Dagostino
IBIS and Tau Modeling Manager
SDD
Mentor Graphics Corp.
503-685-1613
tom_dagostino@mentor.com


-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
Sent: Tuesday, December 05, 2000 7:54 AM
To: 'Su Ming TAI'
Cc: si-list@silab.eng.sun.com; ibis-users@eda.org
Subject: RE: Questions on the relationship between IBIS model &
datasheet


> I have a datasheet and an IBIS model of a same device. On the datasheet 
> (see pg 4), the Ioh and Iol values are -24mA and 24mA respectively when
> Vcc 
> is 3V.
 
Those particular values mean that they do not want you to sink or source
more than 24mA at Vcc=3V.  The device may be capable of sinking or sourcing
more than that, but those are the recommended maximum output currents.

> Now, on the IBIS model, at the pullup and pulldown section, when the 
> voltage is at 3V, the current are not anything near to 24mA or -24mA at
> all.
 
Careful here.  The "voltage" that is 3V, is Vcc, the supply voltage.  It is
NOT the axis or independent variable of the [Pullup] and [Pulldown] curves!

> My question is:
> 1) Why is that the datasheet values do not seem to correlate with the IBIS
> 
> model?
 
The IBIS datasheet (IBIS model) hopefully represents actual performance of
the device.  The Spec sheet (what you called datasheet but I need to call it
something else to differentiate it from the IBIS datasheet) describes how to
use the part.  Some of the information, for example page 4, puts constraints
on how you may use it.  Other sections, for example page 5, give the
absolute worst-case performance you can (hopefully) ever expect, even when
they migrate the part to a new IC fab which could result in a different IBIS
datasheet being generated.

There is almost always some "padding" included in the Spec sheet data.  For
example, the minimum tpd (according to all simulations and projections made
by the vendor) might be 1.7ns, hypothetically, but the vendor publishes 1ns
to be safe.  It's a marketing decision.  They might not add the same amount
of "padding" to their IBIS models, which are intended to better represent
actual performance.

In other words, when comparing "apples to apples" (identical
characteristics), I would not be surprised if the Spec sheet was more
conservative than the IBIS datasheet.

But let's take a closer look at your example.  The spec sheet on page 5 has:

  Voh(min) = 2.2V  @ Vcc = 3V, Ioh = -24mA
  Vol(max) = 0.55V @ Vcc = 3V, Iol =  24mA

Voh = 2.2V means Vcc-Voutput = 0.8V.  Checking the IBIS [Pullup] curve, when
Voltage = 0.8V, I(min) = -21.8948mA, which is close to -24mA.  It doesn't
quite meet the Spec.  At Ioh = -24mA, Vcc-Vout = slightly more than 0.9V, so
Vout = slightly less than 2.1V.  Not quite 2.2V minimum.

For Vol = 0.55V, the IBIS [Pulldown] curve says I(min) = between 32.8243mA
and 38.6213mA.  For Iol = 24mA, Vout = about 0.36V.  This meets the Spec
sheet (max. 0.55V).

> 2) How do we know that the IBIS model is correctly generated based on the 
> values from the datasheet?
 
I would hope that both the IBIS datasheet and the Spec sheet are generated
from simulations and/or measurements, not one from the other.  Neither sheet
alone has sufficient information to generate the other.

The IBIS datasheet has considerably more data about I vs. V, so it could
never be generated from a Spec sheet alone, but the IBIS datasheet usually
lacks the Absolute Maximum and Recommended Maximum conditions that are
included on the Spec sheet.

Regards,
Andy

------_=_NextPart_001_01C05EF6.0B284C50
Content-Type: text/html;
	charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3DISO-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>RE: Questions on the relationship between IBIS model &amp; =
datasheet</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>When Vol is specified at 0.55 volts and 24 mA it =
means the part will put out less than 0.55 volts when 24 ma of current =
is being sunk into the output.&nbsp; This is what the manufacturer =
&quot;guarantees&quot;.&nbsp; Since the manufacturer wants to ship all =
possible die from a wafer the output spec is conservative, all parts =
should meet this spec.&nbsp; It is not unusual to see 2 to 5 time the =
spec current at the specified output voltage. If the model shows less =
than the specified current at the specified voltage I would be suspect =
of the model.&nbsp; I have rarely seen a part that would not meet its =
Vol or Voh spec.&nbsp; I have seen many parts that would product more =
current at a given voltage than the model said it should (measured Iol =
at Vol was greater than the Max in the model).&nbsp; </FONT></P>

<P><FONT SIZE=3D2>Tom Dagostino</FONT>
<BR><FONT SIZE=3D2>IBIS and Tau Modeling Manager</FONT>
<BR><FONT SIZE=3D2>SDD</FONT>
<BR><FONT SIZE=3D2>Mentor Graphics Corp.</FONT>
<BR><FONT SIZE=3D2>503-685-1613</FONT>
<BR><FONT SIZE=3D2>tom_dagostino@mentor.com</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Ingraham, Andrew [<A =
HREF=3D"mailto:Andrew.Ingraham@compaq.com">mailto:Andrew.Ingraham@compaq=
.com</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Tuesday, December 05, 2000 7:54 AM</FONT>
<BR><FONT SIZE=3D2>To: 'Su Ming TAI'</FONT>
<BR><FONT SIZE=3D2>Cc: si-list@silab.eng.sun.com; =
ibis-users@eda.org</FONT>
<BR><FONT SIZE=3D2>Subject: RE: Questions on the relationship between =
IBIS model &amp;</FONT>
<BR><FONT SIZE=3D2>datasheet</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>&gt; I have a datasheet and an IBIS model of a same =
device. On the datasheet </FONT>
<BR><FONT SIZE=3D2>&gt; (see pg 4), the Ioh and Iol values are -24mA =
and 24mA respectively when</FONT>
<BR><FONT SIZE=3D2>&gt; Vcc </FONT>
<BR><FONT SIZE=3D2>&gt; is 3V.</FONT>
<BR><FONT SIZE=3D2>&nbsp;</FONT>
<BR><FONT SIZE=3D2>Those particular values mean that they do not want =
you to sink or source</FONT>
<BR><FONT SIZE=3D2>more than 24mA at Vcc=3D3V.&nbsp; The device may be =
capable of sinking or sourcing</FONT>
<BR><FONT SIZE=3D2>more than that, but those are the recommended =
maximum output currents.</FONT>
</P>

<P><FONT SIZE=3D2>&gt; Now, on the IBIS model, at the pullup and =
pulldown section, when the </FONT>
<BR><FONT SIZE=3D2>&gt; voltage is at 3V, the current are not anything =
near to 24mA or -24mA at</FONT>
<BR><FONT SIZE=3D2>&gt; all.</FONT>
<BR><FONT SIZE=3D2>&nbsp;</FONT>
<BR><FONT SIZE=3D2>Careful here.&nbsp; The &quot;voltage&quot; that is =
3V, is Vcc, the supply voltage.&nbsp; It is</FONT>
<BR><FONT SIZE=3D2>NOT the axis or independent variable of the [Pullup] =
and [Pulldown] curves!</FONT>
</P>

<P><FONT SIZE=3D2>&gt; My question is:</FONT>
<BR><FONT SIZE=3D2>&gt; 1) Why is that the datasheet values do not seem =
to correlate with the IBIS</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; model?</FONT>
<BR><FONT SIZE=3D2>&nbsp;</FONT>
<BR><FONT SIZE=3D2>The IBIS datasheet (IBIS model) hopefully represents =
actual performance of</FONT>
<BR><FONT SIZE=3D2>the device.&nbsp; The Spec sheet (what you called =
datasheet but I need to call it</FONT>
<BR><FONT SIZE=3D2>something else to differentiate it from the IBIS =
datasheet) describes how to</FONT>
<BR><FONT SIZE=3D2>use the part.&nbsp; Some of the information, for =
example page 4, puts constraints</FONT>
<BR><FONT SIZE=3D2>on how you may use it.&nbsp; Other sections, for =
example page 5, give the</FONT>
<BR><FONT SIZE=3D2>absolute worst-case performance you can (hopefully) =
ever expect, even when</FONT>
<BR><FONT SIZE=3D2>they migrate the part to a new IC fab which could =
result in a different IBIS</FONT>
<BR><FONT SIZE=3D2>datasheet being generated.</FONT>
</P>

<P><FONT SIZE=3D2>There is almost always some &quot;padding&quot; =
included in the Spec sheet data.&nbsp; For</FONT>
<BR><FONT SIZE=3D2>example, the minimum tpd (according to all =
simulations and projections made</FONT>
<BR><FONT SIZE=3D2>by the vendor) might be 1.7ns, hypothetically, but =
the vendor publishes 1ns</FONT>
<BR><FONT SIZE=3D2>to be safe.&nbsp; It's a marketing decision.&nbsp; =
They might not add the same amount</FONT>
<BR><FONT SIZE=3D2>of &quot;padding&quot; to their IBIS models, which =
are intended to better represent</FONT>
<BR><FONT SIZE=3D2>actual performance.</FONT>
</P>

<P><FONT SIZE=3D2>In other words, when comparing &quot;apples to =
apples&quot; (identical</FONT>
<BR><FONT SIZE=3D2>characteristics), I would not be surprised if the =
Spec sheet was more</FONT>
<BR><FONT SIZE=3D2>conservative than the IBIS datasheet.</FONT>
</P>

<P><FONT SIZE=3D2>But let's take a closer look at your example.&nbsp; =
The spec sheet on page 5 has:</FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; Voh(min) =3D 2.2V&nbsp; @ Vcc =3D 3V, Ioh =3D =
-24mA</FONT>
<BR><FONT SIZE=3D2>&nbsp; Vol(max) =3D 0.55V @ Vcc =3D 3V, Iol =
=3D&nbsp; 24mA</FONT>
</P>

<P><FONT SIZE=3D2>Voh =3D 2.2V means Vcc-Voutput =3D 0.8V.&nbsp; =
Checking the IBIS [Pullup] curve, when</FONT>
<BR><FONT SIZE=3D2>Voltage =3D 0.8V, I(min) =3D -21.8948mA, which is =
close to -24mA.&nbsp; It doesn't</FONT>
<BR><FONT SIZE=3D2>quite meet the Spec.&nbsp; At Ioh =3D -24mA, =
Vcc-Vout =3D slightly more than 0.9V, so</FONT>
<BR><FONT SIZE=3D2>Vout =3D slightly less than 2.1V.&nbsp; Not quite =
2.2V minimum.</FONT>
</P>

<P><FONT SIZE=3D2>For Vol =3D 0.55V, the IBIS [Pulldown] curve says =
I(min) =3D between 32.8243mA</FONT>
<BR><FONT SIZE=3D2>and 38.6213mA.&nbsp; For Iol =3D 24mA, Vout =3D =
about 0.36V.&nbsp; This meets the Spec</FONT>
<BR><FONT SIZE=3D2>sheet (max. 0.55V).</FONT>
</P>

<P><FONT SIZE=3D2>&gt; 2) How do we know that the IBIS model is =
correctly generated based on the </FONT>
<BR><FONT SIZE=3D2>&gt; values from the datasheet?</FONT>
<BR><FONT SIZE=3D2>&nbsp;</FONT>
<BR><FONT SIZE=3D2>I would hope that both the IBIS datasheet and the =
Spec sheet are generated</FONT>
<BR><FONT SIZE=3D2>from simulations and/or measurements, not one from =
the other.&nbsp; Neither sheet</FONT>
<BR><FONT SIZE=3D2>alone has sufficient information to generate the =
other.</FONT>
</P>

<P><FONT SIZE=3D2>The IBIS datasheet has considerably more data about I =
vs. V, so it could</FONT>
<BR><FONT SIZE=3D2>never be generated from a Spec sheet alone, but the =
IBIS datasheet usually</FONT>
<BR><FONT SIZE=3D2>lacks the Absolute Maximum and Recommended Maximum =
conditions that are</FONT>
<BR><FONT SIZE=3D2>included on the Spec sheet.</FONT>
</P>

<P><FONT SIZE=3D2>Regards,</FONT>
<BR><FONT SIZE=3D2>Andy</FONT>
</P>

</BODY>
</HTML>
------_=_NextPart_001_01C05EF6.0B284C50--
 
From owner-ibis Tue Dec  5 12:41:25 2000
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From owner-ibis Tue Dec  5 12:56:34 2000
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     Hello All

   
     I am looking for information on courses for ibis modeling. I have been
to the ibis home page are reviewed
  the information but I still need more. I am new at this game, so I am
looking for as much help as I can get
  because I am only as good as my ibis models.


   Thanx Scot
 
From owner-ibis Wed Dec  6 02:54:01 2000
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From owner-ibis Wed Dec  6 03:07:15 2000
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From: "Bakshi Sandeep Trimbakrao(P00039)" <sandeep@ee.iitb.ernet.in>
Reply-To: "Bakshi Sandeep Trimbakrao(P00039)" <sandeep@ee.iitb.ernet.in>
To: ibis-users@eda.org
Subject: Help need !!
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 Hello,
       I am Mr. Sandeep T. Bakshi currently working as a Project Engg.
 in Indian Institute of Technology - Bombay Mumbai(India),Electrical
 Engg. Dept.
 Recently I am working on a EMI/EMC project which based on IBIS Modeling
 I want to start IBIS modeling from basic.Could you please guide me how
 I should start IBIS ie books,literature,S/W.
 
 Waiting for your kind reply,


 With Best Regrds.
 
  Sandeep

 
From owner-ibis Wed Dec  6 16:24:38 2000
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To: "Bakshi Sandeep Trimbakrao(P00039)" <sandeep@ee.iitb.ernet.in>
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Hello:

Your best approach is to start navigating through the IBIS
Home page:

  http://www.eigroup.org/ibis/ibis.htm

There are Articles, Models, Free Tools, Accuracy Info and
other links into which you can visit.  One strategy is to
look at the earlier information and specifications to get
the basic ideas and background.

Best Regards,
Bob Ross
Mentor Graphics



"Bakshi Sandeep Trimbakrao(P00039)" wrote:
> 
>  Hello,
>        I am Mr. Sandeep T. Bakshi currently working as a Project Engg.
>  in Indian Institute of Technology - Bombay Mumbai(India),Electrical
>  Engg. Dept.
>  Recently I am working on a EMI/EMC project which based on IBIS Modeling
>  I want to start IBIS modeling from basic.Could you please guide me how
>  I should start IBIS ie books,literature,S/W.
> 
>  Waiting for your kind reply,
> 
>  With Best Regrds.
> 
>   Sandeep
 
From owner-ibis Wed Dec  6 19:31:55 2000
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From: "Bakshi Sandeep Trimbakrao(P00039)" <sandeep@ee.iitb.ernet.in>
To: ibis-users@eda.org
Subject: Thanks for help.
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Hello,
   I am very thankful to you for suggesting for me regarding How to start
IBIS.I am going as per your guideline.

Thanking all of you.

With Best Regards

  Sandeep.

 
From owner-ibis Thu Dec  7 10:12:14 2000
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From: "Fisher, Thomas" <tomfisher@ti.com>
To: "'IBIS'" <ibis-users@eda.org>
Subject: Voltage Reference Pins
Date: Thu, 7 Dec 2000 12:05:10 -0600 
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Looking through the latest IBIS version I don't see any provision for pin(s)
that are used simply as a voltage reference.  Having said that, do we still
model these pins?  If so, how are they treated?  Thanks.


Regards,
Thomas Fisher

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<P><FONT SIZE=3D2 FACE=3D"Courier New">Looking through the latest IBIS =
version I don't see any provision for pin(s) that are used simply as a =
voltage reference.&nbsp; Having said that, do we still model these =
pins?&nbsp; If so, how are they treated?&nbsp; Thanks.</FONT></P>
<BR>

<P><FONT SIZE=3D2 FACE=3D"Courier New">Regards,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Thomas Fisher</FONT>
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From owner-ibis Thu Dec  7 10:36:30 2000
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Tom:

You are correct that IBIS Version 3.2 does not model the
reference voltage pins directly.

BIRD62.6 covers internal and external reference voltage
specification and interactions with other parameters.  So the
modeling effects will be covered in more detail in a future
version of IBIS.

For existing Version 3.2 models, I recommend that you designate
the reference voltage pins as NC or as POWER pins and capture
the reference voltage variations and threshold variations
with the [Voltage Range] or [Pullup Reference] keywords 
threshold subparameters.

Bob Ross
Mentor Graphics



"Fisher, Thomas" wrote:
> 
> Looking through the latest IBIS version I don't see any provision for pin(s)
> that are used simply as a voltage reference.  Having said that, do we still
> model these pins?  If so, how are they treated?  Thanks.
> 
> Regards,
> Thomas Fisher
 
From owner-ibis Sat Dec  9 05:20:52 2000
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Date: Sat, 9 Dec 2000 15:16:57 +0200 (IST)
From: Offer Kaye <sofferk@techst02.technion.ac.il>
To: ibis-users@eda.org
Subject: Rising/Falling waveform and Ramp keywords
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Hello IBIS gurus.
My question is this- in the IBIS spec, the Rising/Falling Waveform
keywords include the sub-parameters R/L/C/V_fixture and R/L/C_dut, while
the Ramp keyword does not.
I want to measure these parameters (from a packaged component), and I
don't understand why the difference in specs for keywords which it was my
understanding should be measured the same way (only different data used).

How should my test setup be different for the Waveforms vs. Ramp
measurements? Can someone explain in greater detail (than the spec) the
meaning of the R/L/C/V_fixture subparameters?

Thanks in advance,
Offer Kaye
sofferk@techst02.technion.ac.il

 
From owner-ibis Mon Dec 11 14:35:47 2000
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'Offer Kaye'" <sofferk@techst02.technion.ac.il>, ibis-users@eda.org
Subject: RE: Rising/Falling waveform and Ramp keywords
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Hello Offer:

   The [Ramp] keyword was in the original (IBIS ver 1.1) specification and,
at the time, only resistive loads to VCC and GND were allowed.  When the
waveform tables were introduced in ver 2.2 the L/C/R_dut and L/C/R_fixture
subparameters were added so that a model creator could document a test bench
setup.  However -- and this is important -- the IBIS cookbook strongly
recommends that the [Rising Waveform] and [Falling Waveform] data be taken
with 1) no package and 2) into a purely resistive load.  In other words, to
build the most accurate simulator model the waveform data should be taken
from a SPICE simulation of the buffer driving resistive loads only.  

(Data from a waveform taken with the buffer driving package and fixture
L/R/Cs can be included in the IBIS data file as a "Golden Waveform".  The
idea is that the user can set up a simulation with the buffer driving the
package and fixture L/R/Cs, then see how closely the simulated waveform
matches the expected waveform documented in the IBIS file.)

Note that for a standard CMOS buffer the cookbook recomends including four
waveforms: two rising, one with the buffer driving 50 ohms to VCC and
another with the buffer driving 50 ohms to gnd, and two falling, same
conditions.  For more info, check out the IBIS cookbook at

 http://www.eigroup.org/ibis/tools.htm

  Regards,
  Stephen Peters
  Intel Corp.

-----Original Message-----
From: Offer Kaye [mailto:sofferk@techst02.technion.ac.il]
Sent: Saturday, December 09, 2000 5:17 AM
To: ibis-users@eda.org
Subject: Rising/Falling waveform and Ramp keywords


Hello IBIS gurus.
My question is this- in the IBIS spec, the Rising/Falling Waveform
keywords include the sub-parameters R/L/C/V_fixture and R/L/C_dut, while
the Ramp keyword does not.
I want to measure these parameters (from a packaged component), and I
don't understand why the difference in specs for keywords which it was my
understanding should be measured the same way (only different data used).

How should my test setup be different for the Waveforms vs. Ramp
measurements? Can someone explain in greater detail (than the spec) the
meaning of the R/L/C/V_fixture subparameters?

Thanks in advance,
Offer Kaye
sofferk@techst02.technion.ac.il


 
From owner-ibis Thu Dec 14 09:30:52 2000
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From: "Haque, Moshiul" <mhaque@ti.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: IBIS BUSHOLD SUBMODEL.
Date: Thu, 14 Dec 2000 11:26:41 -0600
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Hi,
I am trying to create a separate bus-hold submodel for the IBIS file of a
device with bushold connected at the input.I have several questions.

1)The input of the device is an inverter with a feedback inverter connected
from output to input.The pulldown,pullup and ramp data that I got is by
disconnecting the feedback inverter from the input and get the data for only
the feedback inverter.Is this a correct procedure to get the bushold data?

2)For ramp data the feedback inverter does not have enough current to drive
a 50 ohm load.So if I use  C_fixture equal to C_in of the device will that
be correct?

3)V_trigger_r is the voltage when the output of the input buffer switches
from low to high.So if I want to get the V_trigger_f by simulation I have to
take the whole input buffer not just the feedback inverter.Is this correct?


Any comments or suggestions will be greatly appreciated.

Best Regards.
Moshiul  Haque
Application Engineer
Standard Linear and Logic Marketing
Texas Instruments 
Sherman , TX
Tel -(903) 868-7153
Fax-(903) 868-5980
e-mail- mhaque@ti.com

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<P><FONT SIZE=3D2>Hi,</FONT>
<BR><FONT SIZE=3D2>I am trying to create a separate bus-hold submodel =
for the IBIS file of a device with bushold connected at the input.I =
have several questions.</FONT></P>

<P><FONT SIZE=3D2>1)The input of the device is an inverter with a =
feedback inverter connected from output to input.The pulldown,pullup =
and ramp data that I got is by disconnecting the feedback inverter from =
the input and get the data for only the feedback inverter.Is this a =
correct procedure to get the bushold data?</FONT></P>

<P><FONT SIZE=3D2>2)For ramp data the feedback inverter does not have =
enough current to drive a 50 ohm load.So if I use&nbsp; C_fixture equal =
to C_in of the device will that be correct?</FONT></P>

<P><FONT SIZE=3D2>3)V_trigger_r is the voltage when the output of the =
input buffer switches from low to high.So if I want to get the =
V_trigger_f by simulation I have to take the whole input buffer not =
just the feedback inverter.Is this correct?&nbsp; </FONT></P>

<P><FONT SIZE=3D2>Any comments or suggestions will be greatly =
appreciated.</FONT>
</P>

<P><FONT SIZE=3D2>Best Regards.</FONT>
<BR><FONT SIZE=3D2>Moshiul&nbsp; Haque</FONT>
<BR><FONT SIZE=3D2>Application Engineer</FONT>
<BR><FONT SIZE=3D2>Standard Linear and Logic Marketing</FONT>
<BR><FONT SIZE=3D2>Texas Instruments </FONT>
<BR><FONT SIZE=3D2>Sherman , TX</FONT>
<BR><FONT SIZE=3D2>Tel -(903) 868-7153</FONT>
<BR><FONT SIZE=3D2>Fax-(903) 868-5980</FONT>
<BR><FONT SIZE=3D2>e-mail- mhaque@ti.com</FONT>
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From: "Haque, Moshiul" <mhaque@ti.com>
To: "'Su Ming TAI'" <sm_tai@uti2000.co.jp>
Cc: si-list@silab.eng.sun.com, ibis-users@eda.org
Subject: RE: Questions on the relationship between IBIS model & datasheet
Date: Thu, 14 Dec 2000 11:25:08 -0600
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Dear Su Ming TAI

When comparing the IBIS data to the datasheet spec 

Check the section that says electrical characteristics over recommended
operating  free air temperature range.

PARAMETER    TEST CONDITIONS    VCC  	MIN 
Vol		Iol=24 ma    	  3v    	0.55
Voh		Ioh=-24ma	 	  3v    	1.2

Now in the IBIS file in the pulldown data
[Voltage range]        3.3         3.0         3.6
500.00000mV            44.1271m    32.8243m    54.8473m
600.00000mV            52.2894m    38.6213m    65.2873m  

VCC  range is 
[Voltage range]        3.3         3.0         3.6

and the pullup current.
1.20000V           -41.5252m           -29.1685m           -52.8087m

[Voltage range]        3.3         		3.0	         	3.6



The Iol in datasheet is should be the addition of groundclamp current and
pulldown current in the IBIS file.Groundclamp current is negelegible in this
device.As you can see that at VCC=3.0 volt with 0.55v volt applied minimum
current is greater than 32 ma which agrees with the datasheet that says with
3v vcc and 0.55v applied at output in low state you should get atleast 24ma.



At the pullup
1.20000V           -41.5252m           -29.1685m           -52.8087m
[Voltage range]        3.3         		3.0	         	3.6

pullup data is VCC relative meaning that if its min 2.2v in datasheet that
actually is max 1.2v (3-1.2v) in the pullup data in IBIS file.The Ioh in
datasheet  should be the addition of pwrclamp current and pullup current in
the IBIS file.Pwrclamp current is negelegible in this device.As you can see
from the pullup data with 1.2v at output high state the current is at -29ma
which agrees with the datasheet.  


Best Regards.
Moshiul Haque
Application Engineer
Standard Linear and Logic Marketing
Texas Instruments 
Sherman , TX
Tel -(903) 868-7153
Fax-(903) 868-5980
e-mail- mhaque@ti.com



-----Original Message-----
From: Su Ming TAI [mailto:sm_tai@uti2000.co.jp]
Sent: Monday, December 04, 2000 8:41 PM
To: si-list@silab.eng.sun.com; ibis-users@eda.org
Subject: Questions on the relationship between IBIS model & datasheet


Dear SI & IBIS gurus,

Hi! I'm a newbie in the world of SI and I have question that some of you 
may be able to explain it to me.
I have a datasheet and an IBIS model of a same device. On the datasheet 
(see pg 4), the Ioh and Iol values are -24mA and 24mA respectively when Vcc 
is 3V.
Now, on the IBIS model, at the pullup and pulldown section, when the 
voltage is at 3V, the current are not anything near to 24mA or -24mA at all.
My question is:
1) Why is that the datasheet values do not seem to correlate with the IBIS 
model?
2) How do we know that the IBIS model is correctly generated based on the 
values from the datasheet?

I welcome any comments or explanations on this issue. Thanks.



Regards,
Su Ming TAI

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charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
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<TITLE>RE: Questions on the relationship between IBIS model &amp; =
datasheet</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>Dear Su Ming TAI</FONT>
</P>

<P><FONT SIZE=3D2>When comparing the IBIS data to the datasheet spec =
</FONT>
</P>

<P><FONT SIZE=3D2>Check the section that says electrical =
characteristics over recommended operating&nbsp; free air temperature =
range.</FONT>
</P>

<P><FONT SIZE=3D2>PARAMETER&nbsp;&nbsp;&nbsp; TEST =
CONDITIONS&nbsp;&nbsp;&nbsp; VCC&nbsp; &nbsp;&nbsp; MIN </FONT>
<BR><FONT SIZE=3D2>Vol&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Iol=3D24 =
ma&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp; 3v&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.55</FONT>
<BR><FONT SIZE=3D2>Voh&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Ioh=3D-24ma&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; 3v&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1.2</FONT>
</P>

<P><FONT SIZE=3D2>Now in the IBIS file in the pulldown data</FONT>
<BR><FONT SIZE=3D2>[Voltage =
range]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
3.3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
3.0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3.6</FONT>
<BR><FONT =
SIZE=3D2>500.00000mV&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp; 44.1271m&nbsp;&nbsp;&nbsp; 32.8243m&nbsp;&nbsp;&nbsp; =
54.8473m</FONT>
<BR><FONT =
SIZE=3D2>600.00000mV&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp; 52.2894m&nbsp;&nbsp;&nbsp; 38.6213m&nbsp;&nbsp;&nbsp; =
65.2873m&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>VCC&nbsp; range is </FONT>
<BR><FONT SIZE=3D2>[Voltage =
range]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
3.3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
3.0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3.6</FONT>
</P>

<P><FONT SIZE=3D2>and the pullup current.</FONT>
<BR><FONT =
SIZE=3D2>1.20000V&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp; =
-41.5252m&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
-29.1685m&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
-52.8087m</FONT>
</P>

<P><FONT SIZE=3D2>[Voltage =
range]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
3.3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
3.0&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3.6</FONT>
</P>
<BR>
<BR>

<P><FONT SIZE=3D2>The Iol in datasheet is should be the addition of =
groundclamp current and pulldown current in the IBIS file.Groundclamp =
current is negelegible in this device.As you can see that at VCC=3D3.0 =
volt with 0.55v volt applied minimum current is greater than 32 ma =
which agrees with the datasheet that says with 3v vcc and 0.55v applied =
at output in low state you should get atleast 24ma. </FONT></P>
<BR>

<P><FONT SIZE=3D2>At the pullup</FONT>
<BR><FONT =
SIZE=3D2>1.20000V&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp; =
-41.5252m&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
-29.1685m&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
-52.8087m</FONT>
<BR><FONT SIZE=3D2>[Voltage =
range]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
3.3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
3.0&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3.6</FONT>
</P>

<P><FONT SIZE=3D2>pullup data is VCC relative meaning that if its min =
2.2v in datasheet that actually is max 1.2v (3-1.2v) in the pullup data =
in IBIS file.The Ioh in datasheet&nbsp; should be the addition of =
pwrclamp current and pullup current in the IBIS file.Pwrclamp current =
is negelegible in this device.As you can see from the pullup data with =
1.2v at output high state the current is at -29ma which agrees with the =
datasheet.&nbsp; </FONT></P>
<BR>

<P><FONT SIZE=3D2>Best Regards.</FONT>
<BR><FONT SIZE=3D2>Moshiul Haque</FONT>
<BR><FONT SIZE=3D2>Application Engineer</FONT>
<BR><FONT SIZE=3D2>Standard Linear and Logic Marketing</FONT>
<BR><FONT SIZE=3D2>Texas Instruments </FONT>
<BR><FONT SIZE=3D2>Sherman , TX</FONT>
<BR><FONT SIZE=3D2>Tel -(903) 868-7153</FONT>
<BR><FONT SIZE=3D2>Fax-(903) 868-5980</FONT>
<BR><FONT SIZE=3D2>e-mail- mhaque@ti.com</FONT>
</P>
<BR>
<BR>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Su Ming TAI [<A =
HREF=3D"mailto:sm_tai@uti2000.co.jp">mailto:sm_tai@uti2000.co.jp</A>]</F=
ONT>
<BR><FONT SIZE=3D2>Sent: Monday, December 04, 2000 8:41 PM</FONT>
<BR><FONT SIZE=3D2>To: si-list@silab.eng.sun.com; =
ibis-users@eda.org</FONT>
<BR><FONT SIZE=3D2>Subject: Questions on the relationship between IBIS =
model &amp; datasheet</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Dear SI &amp; IBIS gurus,</FONT>
</P>

<P><FONT SIZE=3D2>Hi! I'm a newbie in the world of SI and I have =
question that some of you </FONT>
<BR><FONT SIZE=3D2>may be able to explain it to me.</FONT>
<BR><FONT SIZE=3D2>I have a datasheet and an IBIS model of a same =
device. On the datasheet </FONT>
<BR><FONT SIZE=3D2>(see pg 4), the Ioh and Iol values are -24mA and =
24mA respectively when Vcc </FONT>
<BR><FONT SIZE=3D2>is 3V.</FONT>
<BR><FONT SIZE=3D2>Now, on the IBIS model, at the pullup and pulldown =
section, when the </FONT>
<BR><FONT SIZE=3D2>voltage is at 3V, the current are not anything near =
to 24mA or -24mA at all.</FONT>
<BR><FONT SIZE=3D2>My question is:</FONT>
<BR><FONT SIZE=3D2>1) Why is that the datasheet values do not seem to =
correlate with the IBIS </FONT>
<BR><FONT SIZE=3D2>model?</FONT>
<BR><FONT SIZE=3D2>2) How do we know that the IBIS model is correctly =
generated based on the </FONT>
<BR><FONT SIZE=3D2>values from the datasheet?</FONT>
</P>

<P><FONT SIZE=3D2>I welcome any comments or explanations on this issue. =
Thanks.</FONT>
</P>
<BR>
<BR>

<P><FONT SIZE=3D2>Regards,</FONT>
<BR><FONT SIZE=3D2>Su Ming TAI</FONT>
</P>

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To: "Haque, Moshiul" <mhaque@ti.com>
CC: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: Re: IBIS BUSHOLD SUBMODEL.
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Moshiul:

Some responses are in your text.

In general, the IBIS model for a standard bus hold circuit
can be viewed as a reasonable first order adjustment.  It
is often build be construction from other information rather
than by actual measurement extraction.  In signal integrity
analysis, the effect of bus hold should be small, so the
"approximation" approach is reasonable.

Bob Ross
Mentor Graphics

"Haque, Moshiul" wrote:

>
>
> Hi,
> I am trying to create a separate bus-hold submodel for the IBIS file
> of a device with bushold connected at the input.I have several
> questions.
>
> 1)The input of the device is an inverter with a feedback inverter
> connected from output to input.The pulldown,pullup and ramp data that
> I got is by disconnecting the feedback inverter from the input and get
> the data for only the feedback inverter.Is this a correct procedure to
> get the bushold data?

I believe this should work.

>
>
> 2)For ramp data the feedback inverter does not have enough current to
> drive a 50 ohm load.So if I use  C_fixture equal to C_in of the device
> will that be correct?

I would still use a resistive load.  Even small transitions can be
processed
in IBIS models.  However a larger resistance might be used to avoid too
small of a transition and possible related numerical ambiguity..

>
>
> 3)V_trigger_r is the voltage when the output of the input buffer
> switches from low to high.So if I want to get the V_trigger_f by
> simulation I have to take the whole input buffer not just the feedback
> inverter.Is this correct?

Probably the overall simulation will provide an estimated V_trigger_r
value that is
good enough for the model.

>
>
> Any comments or suggestions will be greatly appreciated.
>
> Best Regards.
> Moshiul  Haque
> Application Engineer
> Standard Linear and Logic Marketing
> Texas Instruments
> Sherman , TX
> Tel -(903) 868-7153
> Fax-(903) 868-5980
> e-mail- mhaque@ti.com

 
From owner-ibis Fri Dec 15 11:23:30 2000
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Date: Fri, 15 Dec 2000 11:19:33 -0800
From: Alan Hilton-Nickel <ahilton@transmeta.com>
Organization: Transmeta Corp.
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To: "Peters, Stephen" <stephen.peters@intel.com>
CC: ibis-users@eda.org
Subject: Re: Rising/Falling waveform and Ramp keywords
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"Peters, Stephen" wrote:
> Note that for a standard CMOS buffer the cookbook recomends including four
> waveforms: two rising, one with the buffer driving 50 ohms to VCC and
> another with the buffer driving 50 ohms to gnd, and two falling, same
> conditions.  For more info, check out the IBIS cookbook at
> 

Stephen,

I am a little uncomfortable with specifying a waveform into a 50 ohm
load, when we tell our customers to use a 60 ohm characteristic
impedance on their board. Would it screw the IBIS modeller up if we gave
a waveform into a 60 ohm load? I would think it would be more
representative (if not more accurate) of what the driver would see in
normal use.

Alan Hilton-Nickel
Transmeta Corp
 
From owner-ibis Fri Dec 15 11:37:08 2000
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: ibis-users@eda.org
Subject: RE: Rising/Falling waveform and Ramp keywords
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Alan,

50 Ohm is not required only if you make an IBIS1.1 model.
In IBIS version 2.1 and above you can use anything you want,
you just have to specify what you used in the R_fixture and/or
R_load sub-parameters.

Arpad Muranyi
===========================================================

-----Original Message-----
From: Alan Hilton-Nickel [mailto:ahilton@transmeta.com]
Sent: Friday, December 15, 2000 11:20 AM
To: Peters, Stephen
Cc: ibis-users@eda.org
Subject: Re: Rising/Falling waveform and Ramp keywords


"Peters, Stephen" wrote:
> Note that for a standard CMOS buffer the cookbook recomends including four
> waveforms: two rising, one with the buffer driving 50 ohms to VCC and
> another with the buffer driving 50 ohms to gnd, and two falling, same
> conditions.  For more info, check out the IBIS cookbook at
> 

Stephen,

I am a little uncomfortable with specifying a waveform into a 50 ohm
load, when we tell our customers to use a 60 ohm characteristic
impedance on their board. Would it screw the IBIS modeller up if we gave
a waveform into a 60 ohm load? I would think it would be more
representative (if not more accurate) of what the driver would see in
normal use.

Alan Hilton-Nickel
Transmeta Corp

 
From owner-ibis Fri Dec 15 11:43:28 2000
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'Alan Hilton-Nickel'" <ahilton@transmeta.com>,
   "Peters, Stephen"
	 <stephen.peters@intel.com>
Cc: ibis-users@eda.org
Subject: RE: Rising/Falling waveform and Ramp keywords
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Hi Alan:

The 50 ohm load is a recommendation based on a "standard" CMOS buffer.  If
you are specifically specing your drivers to work into a 60 ohm load, then
by all mean -- take the ramp and V-T waveform data into 60 ohms. It
definatly shouldn't make the model invalid or cause the simulator tool
problems, as long as the load resistance under which the [Ramp] and V-T is
taken is documented properly (the R_load and R_fixture subparmeters
respectivly). 

  Regards,
  Stephen


-----Original Message-----
From: Alan Hilton-Nickel [mailto:ahilton@transmeta.com]
Sent: Friday, December 15, 2000 11:20 AM
To: Peters, Stephen
Cc: ibis-users@eda.org
Subject: Re: Rising/Falling waveform and Ramp keywords


"Peters, Stephen" wrote:
> Note that for a standard CMOS buffer the cookbook recomends including four
> waveforms: two rising, one with the buffer driving 50 ohms to VCC and
> another with the buffer driving 50 ohms to gnd, and two falling, same
> conditions.  For more info, check out the IBIS cookbook at
> 

Stephen,

I am a little uncomfortable with specifying a waveform into a 50 ohm
load, when we tell our customers to use a 60 ohm characteristic
impedance on their board. Would it screw the IBIS modeller up if we gave
a waveform into a 60 ohm load? I would think it would be more
representative (if not more accurate) of what the driver would see in
normal use.

Alan Hilton-Nickel
Transmeta Corp

 
From owner-ibis Tue Dec 19 06:43:19 2000
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Subject: waveform correlation calculator
To: ibis-users@vhdl.org, ibis@vhdl.org
X-Mailer: Lotus Notes Release 5.0.3 (Intl) 21 March 2000
Message-ID: <OFE4A26673.3E84DDEC-ON862569BA.00508E0A@RCHLAND.IBM.COM>
From: "Gregory R Edlund" <gedlund@us.ibm.com>
Date: Tue, 19 Dec 2000 08:41:18 -0600
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I have written a C program that is useful for overlaying two waveforms and
quantifying the differences between them.  The program reads two ASCII x-y
data files, slides the waveforms along the time axis until they overlay,
then examines the absolute and relative differences between each data
point.  This is pretty useful when doing I/O buffer model development work
or any simulation vs. lab correlation.

You can get a copy of the C code along with a user guide on the IBIS web
site.

http://www.vhdl.org/pub/ibis/accuracy/

The files are ack.zip and ack.tar.Z.  Instructions for compiling are in the
readme.txt file.  Don't worry about the disclaimer; I got approval from
IBM's lawyers to distribute this source code as freeware.  Hack to your
heart's content.

I tested the code when I wrote the I/O buffer accuracy report on the same
web site.  It worked fine for me, but that's not to say you won't find some
pathological cases that I haven't stumbled upon yet.  If you do, please let
me know so I can improve the algorithm.

Merry Christmas.


Greg Edlund
Advisory Engineer
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

 
From owner-ibis Tue Dec 19 07:02:24 2000
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Subject: example I/O buffer accuracy report
To: si-list@silab.eng.sun.com
Cc: ibis@vhdl.org, ibis-users@vhdl.org
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Date: Tue, 19 Dec 2000 09:00:21 -0600
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My colleagues and I have applied the procedures defined in the "I/O Buffer
Accuracy Handbook" to a real life part:  IDT's ALVCH16831 buffer.  We
compared IBIS, SPICE, and lab measurements.  The results look really good.
Of course, we had to use a coupled package model and lossy transmission
lines to make them look this good!  IDT was very cooperative with us; I was
most impressed by their willingness to work together.  They have an
impressive array of SPICE and IBIS model data on their web site, and I
would encourage you to have a look.  Incidentally, this particular I/O
buffer circuit is widely used in IDT's ALVCH family, so the test results
cover a lot of ground.

Why don't you grab a copy of this PDF file and email it to your favorite
semiconductor vendor?  Ask them if they can provide you this kind of data
for their parts!  I'll bet a few of them are doing this sort of thing
already, just in a different format.  We've made a lot of progress in the
model arena over the past few years, but we still have a lot of catching up
to do.

http://www.vhdl.org/pub/ibis/accuracy/

The file name is report.pdf.  Thanks to the IBIS Open Forum for hosting the
web site.  Thanks to all of you out there who contributed to this work.  It
was very much a cooperative effort.

Cheers.

Greg Edlund
Advisory Engineer
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

 
From owner-ibis Wed Dec 20 10:35:40 2000
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From: Betty Luk <Betty@genesis-microchip.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: confusion about c_comp
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Hi,
 
I am a bit confused about c_comp.  C_comp is the silicon die capacitance,
which includes the parasitic capacitance of the buffer, the bond wire and
the die pad capacitance.  When the Spice simulations are run to generate the
IBIS data, the effects of the c_comp parameter should already be included
(since you can't take away the parasitic capacitance of the circuit).  So
when the [c_comp] keyword is specified, isn't the effect of c_comp
double-counted?
 
For example, when I generated my IBIS model, I estimated the value of the
bond wire and die pad capacitance, and added that as an explicit capacitance
to the buffer output before using Spice to extract data.  Then I estimated
the value of parasitic capacitance of the buffer circuit (as described by
Arpad Muranyi).  The total [c_comp] value is the sum of bond wire and die
pad capacitance, and the parasitic capacitance of the circuit.  Is this
approach correct?
 
I would really appreciate any feedback.
 
Thanks very much,
Betty Luk

------_=_NextPart_001_01C06AB3.E7DB3BEE
Content-Type: text/html;
	charset="iso-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<BODY>
<DIV><FONT face=Arial size=2><SPAN 
class=856383118-20122000>Hi,</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN 
class=856383118-20122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=Arial size=2><SPAN class=856383118-20122000>I am a bit confused 
about c_comp.&nbsp; C_comp is the silicon die capacitance, which includes the 
parasitic capacitance of the buffer, the bond wire and the die pad 
capacitance.&nbsp; When the Spice simulations are run to generate the IBIS data, 
the effects of the c_comp parameter should already be included (since you can't 
take away the parasitic capacitance of the circuit).&nbsp; So when the [c_comp] 
keyword is specified, isn't the effect of c_comp 
double-counted?</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN 
class=856383118-20122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=Arial size=2><SPAN class=856383118-20122000>For example, when I 
generated my IBIS model, I estimated the value of the bond wire and die pad 
capacitance, and added that as an explicit capacitance to the buffer output 
before using Spice to extract data.&nbsp; Then I estimated the value of 
parasitic capacitance of the buffer circuit (as described by Arpad 
Muranyi).&nbsp; The total [c_comp] value is the sum of bond wire and die pad 
capacitance, and the parasitic capacitance of the circuit.&nbsp; Is this 
approach correct?</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN 
class=856383118-20122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=Arial size=2><SPAN class=856383118-20122000>I would really 
appreciate any feedback.</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN 
class=856383118-20122000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=Arial size=2><SPAN class=856383118-20122000>Thanks very 
much,</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=856383118-20122000>Betty 
Luk</SPAN></FONT></DIV></BODY></HTML>

------_=_NextPart_001_01C06AB3.E7DB3BEE--
 
From owner-ibis Wed Dec 20 12:11:39 2000
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: RE: confusion about c_comp
Date: Wed, 20 Dec 2000 15:07:51 -0500
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> I am a bit confused about c_comp.  C_comp is the silicon die capacitance,
> which includes the parasitic capacitance of the buffer, the bond wire and
> the die pad capacitance.
 
I would not have included the bond wire capacitance, because the bond wire
is part of the package (although the position of the capacitance relative to
L_pkg may make this debatable).  I think c_comp would apply to just the bare
die, even though the IBIS spec does not explicitly say so.


> When the Spice simulations are run to generate the IBIS data, the effects
> of the c_comp parameter should already be included (since you can't take
> away the parasitic capacitance of the circuit).  So when the [c_comp]
> keyword is specified, isn't the effect of c_comp double-counted?
 
By specifying the c_comp keyword, you are providing the IBIS-aware simulator
with the equivalent capacitance that you had in your SPICE simulations.
That is the only place in the IBIS data where this capacitance exists!  I
don't see how there is any double-counting.


> For example, when I generated my IBIS model, I estimated the value of the
> bond wire and die pad capacitance, and added that as an explicit
> capacitance to the buffer output before using Spice to extract data.  Then
> I estimated the value of parasitic capacitance of the buffer circuit (as
> described by Arpad Muranyi).  The total [c_comp] value is the sum of bond
> wire and die pad capacitance, and the parasitic capacitance of the
> circuit.  Is this approach correct?
 
If your SPICE model is complete enough to include die bonding pad
capacitance (and bond wire capacitance if you determine that it should be
part of c_comp too), then whatever value of capacitance you extract from
your SPICE simulations *IS* the value for c_comp.  You would not add a
correction factor to account for the die pad capacitance.  If, on the other
hand, your SPICE simulation doesn't include the die pad, then you should add
it to the extracted capacitance to get the c_comp value for the IBIS data.

However you do it, c_comp should represent the effective on-die capacitance.

Andy

 
From owner-ibis Wed Dec 20 13:31:57 2000
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From: Betty Luk <Betty@genesis-microchip.com>
To: "'Ingraham, Andrew'" <Andrew.Ingraham@compaq.com>,
   "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: RE: confusion about c_comp
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> > I am a bit confused about c_comp.  C_comp is the silicon 
> die capacitance,
> > which includes the parasitic capacitance of the buffer, the 
> bond wire and
> > the die pad capacitance.
>  
> I would not have included the bond wire capacitance, because 
> the bond wire
> is part of the package (although the position of the 
> capacitance relative to
> L_pkg may make this debatable).  I think c_comp would apply 
> to just the bare
> die, even though the IBIS spec does not explicitly say so.
>

I think I might have used the wrong terminology.  By "bond wire", I actually
meant the connection between the output of the buffer on the die to the die
pad.  That's why I think that it should be included in the c_comp.
 
> 
> > When the Spice simulations are run to generate the IBIS 
> data, the effects
> > of the c_comp parameter should already be included (since 
> you can't take
> > away the parasitic capacitance of the circuit).  So when 
> the [c_comp]
> > keyword is specified, isn't the effect of c_comp double-counted?
>  
> By specifying the c_comp keyword, you are providing the 
> IBIS-aware simulator
> with the equivalent capacitance that you had in your SPICE 
> simulations.
> That is the only place in the IBIS data where this 
> capacitance exists!  I
> don't see how there is any double-counting.
> 
> 

The effects of c_comp is already in the V/t waveform data.  The on-die
capacitance is what causes the ramp, right?  So if a simulator is not
careful enough, and uses the value of c_comp along with the V/t data in the
IBIS model, then the c_comp would be "double-counted".


> > For example, when I generated my IBIS model, I estimated 
> the value of the
> > bond wire and die pad capacitance, and added that as an explicit
> > capacitance to the buffer output before using Spice to 
> extract data.  Then
> > I estimated the value of parasitic capacitance of the 
> buffer circuit (as
> > described by Arpad Muranyi).  The total [c_comp] value is 
> the sum of bond
> > wire and die pad capacitance, and the parasitic capacitance of the
> > circuit.  Is this approach correct?
>  
> If your SPICE model is complete enough to include die bonding pad
> capacitance (and bond wire capacitance if you determine that 
> it should be
> part of c_comp too), then whatever value of capacitance you 
> extract from
> your SPICE simulations *IS* the value for c_comp.  You would not add a
> correction factor to account for the die pad capacitance.  
> If, on the other
> hand, your SPICE simulation doesn't include the die pad, then 
> you should add
> it to the extracted capacitance to get the c_comp value for 
> the IBIS data.
> 
> However you do it, c_comp should represent the effective 
> on-die capacitance.
> 
> Andy
>

Betty 
 
From owner-ibis Wed Dec 20 14:06:58 2000
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: RE: confusion about c_comp
Date: Wed, 20 Dec 2000 17:03:17 -0500
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> I think I might have used the wrong terminology.  By "bond wire", I
> actually
> meant the connection between the output of the buffer on the die to the
> die
> pad.  That's why I think that it should be included in the c_comp.
 
Yes, the "wiring" on the die should be part of c_comp.


> The effects of c_comp is already in the V/t waveform data.  The on-die
> capacitance is what causes the ramp, right?
 
It is part of it, but not all.  For example, capacitance in the pre-driver
stage may slow the edge rates of the waveforms at the gates of the output
transistors, causing the transistors to switch over a short time.  Even if
you could make them have a purely resistive load (i.e., make c_comp = 0),
the output edges would not be instantaneous.


> So if a simulator is not
> careful enough, and uses the value of c_comp along with the V/t data in
> the
> IBIS model, then the c_comp would be "double-counted".
 
Any simulator that uses the V/T data, must be careful enough to use it
correctly!

Whatever algorithm it uses, it must be able to duplicate the V/T data, by
simulating the device connected to the same elements (R_fixture, etc.).  If
it doesn't, the simulator's algorithm is wrong.

An explicit answer to your question is in the IBIS spec, in the section
about the V/T data:  "All tables assume that the die capacitance is
included."

Both c_comp and the V/T data do include the effects of on-die capacitance,
but that doesn't mean it is being double-counted.  
The V/T data includes the effects of many other parameters in the IBIS data
sheet, including the I/V data, the Voltage_Range, etc.  But the V/T data
doesn't REPLACE those other parameters.

Think of the V/T data as just another "measurement" of your device which is
already specified by all the other parameters.

Andy

 
From owner-ibis Wed Dec 20 21:40:53 2000
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From: Al Davis <aldavis@ieee.org>
To: <ibis-users@eda.org>
Subject: Re: confusion about c_comp
Date: Wed, 20 Dec 2000 17:10:35 -0800
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On Wed, 20 Dec 2000, Ingraham, Andrew wrote:
> Any simulator that uses the V/T data, must be careful enough to use
> it correctly!
>
> Whatever algorithm it uses, it must be able to duplicate the V/T
> data, by simulating the device connected to the same elements
> (R_fixture, etc.).  If it doesn't, the simulator's algorithm is
> wrong.

It is actually very difficult to implement it correctly.  I am 
curious how they all do in this matter.

C_comp is included in the V/T data, but it is not included in the 
pullup/pulldown data.  This means that to be truly correct, some kind 
of add and remove algorithm is needed, so it will be there at the 
ends, but not be double counted in the middle of the transition.  A 
truly correct implementation of c_comp will tend to magnify errors in 
the V/T data, making me believe that some kind of semi-correct 
implementation may actually be superior in practice.

Even without c_comp, the V/T support is trouble prone.  Sometimes it 
is necessary to tolerate some error in data matching in the interest 
of stability.  It is possible to supply multiple V/T tables that have 
conflicting data, or data that cannot actually happen with the simple 
topology of an IBIS model.  (Driver schedule, bus hold, dynamic clamp 
are all attempts to help in these cases.)  In these cases, often 
something needs to be sacrificed.  Some simulators try to fit the 
best they can, perhaps with some smoothing or other data munging.  
All reject waveforms that don't fit their algorithm.  Some are mpre 
picky than others.  Some just take the first one or two, regardless 
of what is best.  They all keep the details of the algorithm secret.
 
From owner-ibis Thu Dec 21 06:17:30 2000
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: ibis-users@eda.org
Subject: RE: confusion about c_comp
Date: Thu, 21 Dec 2000 09:13:45 -0500
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> > Any simulator that uses the V/T data, must be careful enough to use
> > it correctly!
> > ...
> 
> It is actually very difficult to implement it correctly.
 
Yes, I'm sure it is!


> C_comp is included in the V/T data, but it is not included in the 
> pullup/pulldown data.  This means that to be truly correct, some kind 
> of add and remove algorithm is needed,
 
?  The pullup/pulldown (I/V) data is DC data.  C_comp is irrelevant, it has
no effect on the pullup/pulldown data.  Maybe I misunderstood you.

Regards,
Andy

 
From owner-ibis Thu Dec 21 07:32:21 2000
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From: "Lorang, David D" <david.d.lorang@intel.com>
To: ibis-users@eda.org
Subject: RE: confusion about c_comp
Date: Thu, 21 Dec 2000 07:28:44 -0800
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This is a great thread!  I think many of us, both SI tool users and
simulator developers, have struggled with this Ccomp problem.  

It is possible to match up the V-T curves using a piecewise linear ramp
waveforms, various controlled voltage or current sources, and perhaps some
resistors, but no storage elements.  If the simulator produces its internal
model to match the waveform in this manner, then afterwards adds Ccomp to
the model, then the Ccomp has been double counted and the final model would
be in error.
  
What should happen is that the simulator should match the IBIS waveform
using all of the ramps, sources, resistors, but with Ccomp in place also.
Then, because Ccomp is already in place in the simulator's internal model,
it must not be added in again.  

I have seen this problem, when trying to correlate IBIS based models with
the transistor level simulations they were developed from.  You see the
problem when waveforms do not correlate unless the Ccomp is manually "zeroed
out" in the model.

I'm not sure we can fault the vendors too much because it is easy to get
wrong and the IBIS Specification standard does not spend a lot of words
explaining all of this.   Perhaps some more clarification in the IBIS
Specification standard is in order.  Further thoughts?

Best regards,
Dave Lorang 

-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
Sent: Thursday, December 21, 2000 7:14 AM
To: ibis-users@eda.org
Subject: RE: confusion about c_comp


> > Any simulator that uses the V/T data, must be careful enough to use
> > it correctly!
> > ...
> 
> It is actually very difficult to implement it correctly.
 
Yes, I'm sure it is!


> C_comp is included in the V/T data, but it is not included in the 
> pullup/pulldown data.  This means that to be truly correct, some kind 
> of add and remove algorithm is needed,
 
?  The pullup/pulldown (I/V) data is DC data.  C_comp is irrelevant, it has
no effect on the pullup/pulldown data.  Maybe I misunderstood you.

Regards,
Andy

 
From owner-ibis Thu Dec 21 09:06:22 2000
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From: Christopher Reid <chris_reid@mentorg.com>
Organization: Mentor Graphics Corporation
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Hello IBIS land,

I don't see this as confusing at all.  The VT curves are what the
simulator should produce under the load conditions specified in
the IBIS model for each curve.  The simulation vendor must devise
an algorithm to "make it so."

The C_comp must be in place during the actual simulation because
it will affect the results in different ways for different loading
conditions.

Chris Reid
Mentor Graphics

"Lorang, David D" wrote:
> 
> This is a great thread!  I think many of us, both SI tool users and
> simulator developers, have struggled with this Ccomp problem.
> 
> It is possible to match up the V-T curves using a piecewise linear ramp
> waveforms, various controlled voltage or current sources, and perhaps some
> resistors, but no storage elements.  If the simulator produces its internal
> model to match the waveform in this manner, then afterwards adds Ccomp to
> the model, then the Ccomp has been double counted and the final model would
> be in error.
> 
> What should happen is that the simulator should match the IBIS waveform
> using all of the ramps, sources, resistors, but with Ccomp in place also.
> Then, because Ccomp is already in place in the simulator's internal model,
> it must not be added in again.
> 
> I have seen this problem, when trying to correlate IBIS based models with
> the transistor level simulations they were developed from.  You see the
> problem when waveforms do not correlate unless the Ccomp is manually "zeroed
> out" in the model.
> 
> I'm not sure we can fault the vendors too much because it is easy to get
> wrong and the IBIS Specification standard does not spend a lot of words
> explaining all of this.   Perhaps some more clarification in the IBIS
> Specification standard is in order.  Further thoughts?
> 
> Best regards,
> Dave Lorang
> 
> -----Original Message-----
> From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
> Sent: Thursday, December 21, 2000 7:14 AM
> To: ibis-users@eda.org
> Subject: RE: confusion about c_comp
> 
> > > Any simulator that uses the V/T data, must be careful enough to use
> > > it correctly!
> > > ...
> >
> > It is actually very difficult to implement it correctly.
> 
> Yes, I'm sure it is!
> 
> > C_comp is included in the V/T data, but it is not included in the
> > pullup/pulldown data.  This means that to be truly correct, some kind
> > of add and remove algorithm is needed,
> 
> ?  The pullup/pulldown (I/V) data is DC data.  C_comp is irrelevant, it has
> no effect on the pullup/pulldown data.  Maybe I misunderstood you.
> 
> Regards,
> Andy
 
From owner-ibis Thu Dec 21 12:51:01 2000
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "'Christopher Reid'" <chris_reid@mentorg.com>
Cc: ibis-users@eda.org
Subject: RE: confusion about c_comp
Date: Thu, 21 Dec 2000 12:47:16 -0800
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Hello,

To sum this problem up, I usually say that C_comp needs to
be visible from the outside looking in, but invisible from
the inside looking out.

Here is how I did it in my HSPICE implementation (before the
B-element came out).  I used PWL sources to contain the I-V
and V-t tables and some additional controlled sources to do
the math between these.  C_comp was a normal capacitance
connected to the end of all this.  If I would have left it
this way, I would have indeed double counted for C_comp,
because the shape of the V-t curve in the PWL source already
includes its effect.  Yet I knew I had to have that capacitor
there, because a reflection that hits this (driving) buffer
will bounce back from it differently if it was not there.

This is what I did to remove the double counting.  I connected a
duplicate C_comp on the output of the PWL source(s) which had the
V-t curve(s).  Then I just simply included an additional term
in my math which combined the I-V and V-t curves so that the
current of this duplicate capacitance was subtracted from the
total result.  I know this will have some error as the actual
waveform deviates from the V-t curve, but this error is smaller
than double counting C_comp (zeroing it out).

Of course, when you write the code of your simulator you have
much more control over writing an algorithm that does a better
job than this.

Arpad Muranyi
Intel Corporation
================================================================

-----Original Message-----
From: Christopher Reid [mailto:chris_reid@mentorg.com]
Sent: Thursday, December 21, 2000 9:02 AM
Cc: ibis-users@eda.org
Subject: Re: confusion about c_comp


Hello IBIS land,

I don't see this as confusing at all.  The VT curves are what the
simulator should produce under the load conditions specified in
the IBIS model for each curve.  The simulation vendor must devise
an algorithm to "make it so."

The C_comp must be in place during the actual simulation because
it will affect the results in different ways for different loading
conditions.

Chris Reid
Mentor Graphics

"Lorang, David D" wrote:
> 
> This is a great thread!  I think many of us, both SI tool users and
> simulator developers, have struggled with this Ccomp problem.
> 
> It is possible to match up the V-T curves using a piecewise linear ramp
> waveforms, various controlled voltage or current sources, and perhaps some
> resistors, but no storage elements.  If the simulator produces its
internal
> model to match the waveform in this manner, then afterwards adds Ccomp to
> the model, then the Ccomp has been double counted and the final model
would
> be in error.
> 
> What should happen is that the simulator should match the IBIS waveform
> using all of the ramps, sources, resistors, but with Ccomp in place also.
> Then, because Ccomp is already in place in the simulator's internal model,
> it must not be added in again.
> 
> I have seen this problem, when trying to correlate IBIS based models with
> the transistor level simulations they were developed from.  You see the
> problem when waveforms do not correlate unless the Ccomp is manually
"zeroed
> out" in the model.
> 
> I'm not sure we can fault the vendors too much because it is easy to get
> wrong and the IBIS Specification standard does not spend a lot of words
> explaining all of this.   Perhaps some more clarification in the IBIS
> Specification standard is in order.  Further thoughts?
> 
> Best regards,
> Dave Lorang
> 
> -----Original Message-----
> From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
> Sent: Thursday, December 21, 2000 7:14 AM
> To: ibis-users@eda.org
> Subject: RE: confusion about c_comp
> 
> > > Any simulator that uses the V/T data, must be careful enough to use
> > > it correctly!
> > > ...
> >
> > It is actually very difficult to implement it correctly.
> 
> Yes, I'm sure it is!
> 
> > C_comp is included in the V/T data, but it is not included in the
> > pullup/pulldown data.  This means that to be truly correct, some kind
> > of add and remove algorithm is needed,
> 
> ?  The pullup/pulldown (I/V) data is DC data.  C_comp is irrelevant, it
has
> no effect on the pullup/pulldown data.  Maybe I misunderstood you.
> 
> Regards,
> Andy

 
From owner-ibis Fri Dec 22 12:24:13 2000
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From: "Baikuan Wang" <wangbk@sigrity.com>
To: "Betty Luk" <Betty@genesis-microchip.com>, <ibis-users@eda.org>
Subject: RE: confusion about c_comp
Date: Fri, 22 Dec 2000 12:20:30 -0800
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In-Reply-To: <85893468B47AD411818100306E00E18452BC95@NTTOEX1>

Hi,

Nice to read these discussion mails.

Since V-t curve is extracted from the circuit including C_comp,
the algorithm to handle IBIS inside software definitely considers
C_comp. When users use the black box of buffer linked with other
circuit, C_comp should not be added.

Regards.
Brian

-----Original Message-----
From: Betty Luk [mailto:Betty@genesis-microchip.com]
Sent: Wednesday, December 20, 2000 1:35 PM
To: 'Ingraham, Andrew'; 'ibis-users@eda.org'
Subject: RE: confusion about c_comp


> > I am a bit confused about c_comp.  C_comp is the silicon
> die capacitance,
> > which includes the parasitic capacitance of the buffer, the
> bond wire and
> > the die pad capacitance.
>
> I would not have included the bond wire capacitance, because
> the bond wire
> is part of the package (although the position of the
> capacitance relative to
> L_pkg may make this debatable).  I think c_comp would apply
> to just the bare
> die, even though the IBIS spec does not explicitly say so.
>

I think I might have used the wrong terminology.  By "bond wire", I actually
meant the connection between the output of the buffer on the die to the die
pad.  That's why I think that it should be included in the c_comp.

>
> > When the Spice simulations are run to generate the IBIS
> data, the effects
> > of the c_comp parameter should already be included (since
> you can't take
> > away the parasitic capacitance of the circuit).  So when
> the [c_comp]
> > keyword is specified, isn't the effect of c_comp double-counted?
>
> By specifying the c_comp keyword, you are providing the
> IBIS-aware simulator
> with the equivalent capacitance that you had in your SPICE
> simulations.
> That is the only place in the IBIS data where this
> capacitance exists!  I
> don't see how there is any double-counting.
>
>

The effects of c_comp is already in the V/t waveform data.  The on-die
capacitance is what causes the ramp, right?  So if a simulator is not
careful enough, and uses the value of c_comp along with the V/t data in the
IBIS model, then the c_comp would be "double-counted".


> > For example, when I generated my IBIS model, I estimated
> the value of the
> > bond wire and die pad capacitance, and added that as an explicit
> > capacitance to the buffer output before using Spice to
> extract data.  Then
> > I estimated the value of parasitic capacitance of the
> buffer circuit (as
> > described by Arpad Muranyi).  The total [c_comp] value is
> the sum of bond
> > wire and die pad capacitance, and the parasitic capacitance of the
> > circuit.  Is this approach correct?
>
> If your SPICE model is complete enough to include die bonding pad
> capacitance (and bond wire capacitance if you determine that
> it should be
> part of c_comp too), then whatever value of capacitance you
> extract from
> your SPICE simulations *IS* the value for c_comp.  You would not add a
> correction factor to account for the die pad capacitance.
> If, on the other
> hand, your SPICE simulation doesn't include the die pad, then
> you should add
> it to the extracted capacitance to get the c_comp value for
> the IBIS data.
>
> However you do it, c_comp should represent the effective
> on-die capacitance.
>
> Andy
>

Betty