
From owner-ibis  Wed Jul  5 09:21:05 2000
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Message-ID: <39635F30.DC32C39D@ti.com>
Date: Wed, 05 Jul 2000 11:15:44 -0500
From: Stephen Nolan <s-nolan1@ti.com>
Organization: Texas Instruments Incorporated
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Subject: Subtracting clamp curves from pull-up/down curves
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Hello IBIS gurus,

When creating a model for a three-state device, it is necessary to subtract the
clamp curves from the pull-up/down curves to avoid double counting, as the EDA
tool adds the clamp-curves back in to the pull-up/down curves to obtain the
devices output charactersitics in the enabled state. Right so far?

The question is this, do you only subtract the corresponding clamp curve from
the related pull-up/down curve, or do you subtract BOTH clamp curves from each
pull-up/down curve? 

For example, if I am creating the pull-down curve, do I subtract only the
ground-clamp curve, or do I subtract both the power-clamp and ground-clamp
curves? Does the EDA tool add only the ground-clamp data back in, or does it add
both curves back in?

-- 
Regards,
Stephen M. Nolan
From owner-ibis  Wed Jul  5 09:23:22 2000
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Message-ID: <39635FB9.3A79AA0C@ti.com>
Date: Wed, 05 Jul 2000 11:18:01 -0500
From: Stephen Nolan <s-nolan1@ti.com>
Organization: Texas Instruments Incorporated
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EDA tool vendors, this question is for you.

Does your simulation software COMPLETLY support IBIS 3.2 style FET switch
models?

If "no" then
{
Do you partially support them?
What is your schedule for full implementation?
}

Thanks.

-- 
Regards,
Stephen M. Nolan
From owner-ibis  Thu Jul  6 09:49:08 2000
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: ibis-users@eda.org
Subject: RE: Subtracting clamp curves from pull-up/down curves
Date: Thu, 6 Jul 2000 09:45:10 -0700 
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Stephen,

Here is how I do it.

When the buffer is 3-stated, I do two sweeps.  One GND relative,
and another one Vcc relative.  Notice that these two measurements
have the same information in them, they are just referenced
differently.

I also make two measurements when the buffer is driving (provided
it is complementary with both pullup and pulldown).  The pulldown
curve is swept GND relative, and the pullup is swept Vcc relative.

I do all four of these sweeps from -Vcc to 2*Vcc.  Because of this,
both GND and Vcc clamps will be present in all four of the curves.

When I subtract, I do

  pulldown_sweep - GND_rel_3state_sweep => this will be my [Pulldown]
  pulldup_sweep  - Vcc_rel_3state_sweep => this will be my [Pullup]

Then I cut off the power clamp part from the GND_rel_3state_sweep and
the ground clamp part from the Vcc_rel_3state_sweep data to avoid double
counting the clamp currents.

That's all you need to do if you have a simple CMOS buffer.
I hope this helps,

Arpad Muranyi
Intel Corporation
=====================================================================


-----Original Message-----
From: Stephen Nolan [mailto:s-nolan1@ti.com]
Sent: Wednesday, July 05, 2000 9:16 AM
To: ibis-users@eda.org
Subject: Subtracting clamp curves from pull-up/down curves


Hello IBIS gurus,

When creating a model for a three-state device, it is necessary to subtract
the
clamp curves from the pull-up/down curves to avoid double counting, as the
EDA
tool adds the clamp-curves back in to the pull-up/down curves to obtain the
devices output charactersitics in the enabled state. Right so far?

The question is this, do you only subtract the corresponding clamp curve
from
the related pull-up/down curve, or do you subtract BOTH clamp curves from
each
pull-up/down curve? 

For example, if I am creating the pull-down curve, do I subtract only the
ground-clamp curve, or do I subtract both the power-clamp and ground-clamp
curves? Does the EDA tool add only the ground-clamp data back in, or does it
add
both curves back in?

-- 
Regards,
Stephen M. Nolan

From owner-ibis  Fri Jul  7 05:30:32 2000
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Message-ID: <3965CCC6.E86F43A9@cadence.com>
Date: Fri, 07 Jul 2000 08:27:50 -0400
From: Mike LaBonte <mikelabonte@cadence.com>
Organization: Cadence Design Systems, Inc.
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Subject: Re: Subtracting clamp curves from pull-up/down curves
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Stephen,

Arpad's reply indicates that both clamp curves are indeed subtracted
to produce pullup and pulldown curves. I can verify the other side of
your question; that simulators (at least Cadence SPECCTRAQuest)
re-combine the curves as follows:

   low state:  pulldown + powerclamp + groundclamp
  high state:  pullup   + powerclamp + groundclamp

So the clamps are never disabled (unless Submodel is used).

Mike LaBonte
Cadence

Stephen Nolan wrote:
> 
> Hello IBIS gurus,
> 
> When creating a model for a three-state device, it is necessary to subtract the
> clamp curves from the pull-up/down curves to avoid double counting, as the EDA
> tool adds the clamp-curves back in to the pull-up/down curves to obtain the
> devices output charactersitics in the enabled state. Right so far?
> 
> The question is this, do you only subtract the corresponding clamp curve from
> the related pull-up/down curve, or do you subtract BOTH clamp curves from each
> pull-up/down curve?
> 
> For example, if I am creating the pull-down curve, do I subtract only the
> ground-clamp curve, or do I subtract both the power-clamp and ground-clamp
> curves? Does the EDA tool add only the ground-clamp data back in, or does it add
> both curves back in?
> 
> --
> Regards,
> Stephen M. Nolan
From owner-ibis  Fri Jul  7 07:21:07 2000
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Message-ID: <3D60630D3600D411896F0090278D4E483CC8C7@spawn.cereva.com>
From: "Haller, Robert" <rhaller@cereva.com>
To: "'Mike LaBonte'" <mikelabonte@cadence.com>
Cc: ibis-users@eda.org
Subject: RE: Subtracting clamp curves from pull-up/down curves
Date: Fri, 7 Jul 2000 10:16:56 -0400 
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Mike,
	Not trying to play devil's advocate, but I have always wondered 
why the model maker has to subtract the clamps out, then the software vendor

puts the clamps back in ?  Why not just have syntax (in IBIS) for a pullup 
and pulldown model WITH the clamp ? Thus reducing everyone's work ?

My old (internal) simulator and models were defined this way (IV curves
included clamps)
and it seemed a lot easier. We could feed bench data from a curve tracer (or
semiconductor analyzer)
directly into the model without any math, and when you looked model curves
they were intuitive.
I know its probably now water over the dam,  but I was just wondering....

regards,
Bob

Cereva Networks
100 Locke Drive
Marlboro MA. 01752
Phone: 508-486-9660 X 3365
FAX: 508-486-9661
Email: rhaller@cereva.com

-----Original Message-----
From: Mike LaBonte [mailto:mikelabonte@cadence.com]
Sent: Friday, July 07, 2000 8:28 AM
To: ibis-users@eda.org
Subject: Re: Subtracting clamp curves from pull-up/down curves


Stephen,

Arpad's reply indicates that both clamp curves are indeed subtracted
to produce pullup and pulldown curves. I can verify the other side of
your question; that simulators (at least Cadence SPECCTRAQuest)
re-combine the curves as follows:

   low state:  pulldown + powerclamp + groundclamp
  high state:  pullup   + powerclamp + groundclamp

So the clamps are never disabled (unless Submodel is used).

Mike LaBonte
Cadence

Stephen Nolan wrote:
> 
> Hello IBIS gurus,
> 
> When creating a model for a three-state device, it is necessary to
subtract the
> clamp curves from the pull-up/down curves to avoid double counting, as the
EDA
> tool adds the clamp-curves back in to the pull-up/down curves to obtain
the
> devices output charactersitics in the enabled state. Right so far?
> 
> The question is this, do you only subtract the corresponding clamp curve
from
> the related pull-up/down curve, or do you subtract BOTH clamp curves from
each
> pull-up/down curve?
> 
> For example, if I am creating the pull-down curve, do I subtract only the
> ground-clamp curve, or do I subtract both the power-clamp and ground-clamp
> curves? Does the EDA tool add only the ground-clamp data back in, or does
it add
> both curves back in?
> 
> --
> Regards,
> Stephen M. Nolan
From owner-ibis  Fri Jul  7 08:10:29 2000
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Date: Fri, 07 Jul 2000 11:07:31 -0400
From: Ian Dodd <idodd@cadence.com>
Organization: Cadence Design Systems, Inc.
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To: "Haller, Robert" <rhaller@cereva.com>
CC: "'Mike LaBonte'" <mikelabonte@cadence.com>, ibis-users@eda.org
Subject: Re: Subtracting clamp curves from pull-up/down curves
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Bob,

I think there are two obvious reasons for keeping the clamps separate:

1. It was intended that models be usable for a range of supply voltages
with the pull-up and power clamps tracking with the supply voltage
and the pull-down and ground clamps tracking with the ground rail.
This was also the rational for referencing the former to the supply voltage.

2. Separating the clamps from the pull-up/down allows modeling of
high/low/tristate
for devices that support these modes.

Recent feedback has indicated that the characteristics of many devices change
markedly with supply voltage, so using an IBIS model for a supply voltage
other than at which it was designed, can give inaccurate results

Ian Dodd
Cadence Design Systems




"Haller, Robert" wrote:
> 
> Mike,
>         Not trying to play devil's advocate, but I have always wondered
> why the model maker has to subtract the clamps out, then the software vendor
> 
> puts the clamps back in ?  Why not just have syntax (in IBIS) for a pullup
> and pulldown model WITH the clamp ? Thus reducing everyone's work ?
> 
> My old (internal) simulator and models were defined this way (IV curves
> included clamps)
> and it seemed a lot easier. We could feed bench data from a curve tracer (or
> semiconductor analyzer)
> directly into the model without any math, and when you looked model curves
> they were intuitive.
> I know its probably now water over the dam,  but I was just wondering....
> 
> regards,
> Bob
> 
> Cereva Networks
> 100 Locke Drive
> Marlboro MA. 01752
> Phone: 508-486-9660 X 3365
> FAX: 508-486-9661
> Email: rhaller@cereva.com
> 
> -----Original Message-----
> From: Mike LaBonte [mailto:mikelabonte@cadence.com]
> Sent: Friday, July 07, 2000 8:28 AM
> To: ibis-users@eda.org
> Subject: Re: Subtracting clamp curves from pull-up/down curves
> 
> Stephen,
> 
> Arpad's reply indicates that both clamp curves are indeed subtracted
> to produce pullup and pulldown curves. I can verify the other side of
> your question; that simulators (at least Cadence SPECCTRAQuest)
> re-combine the curves as follows:
> 
>    low state:  pulldown + powerclamp + groundclamp
>   high state:  pullup   + powerclamp + groundclamp
> 
> So the clamps are never disabled (unless Submodel is used).
> 
> Mike LaBonte
> Cadence
> 
> Stephen Nolan wrote:
> >
> > Hello IBIS gurus,
> >
> > When creating a model for a three-state device, it is necessary to
> subtract the
> > clamp curves from the pull-up/down curves to avoid double counting, as the
> EDA
> > tool adds the clamp-curves back in to the pull-up/down curves to obtain
> the
> > devices output charactersitics in the enabled state. Right so far?
> >
> > The question is this, do you only subtract the corresponding clamp curve
> from
> > the related pull-up/down curve, or do you subtract BOTH clamp curves from
> each
> > pull-up/down curve?
> >
> > For example, if I am creating the pull-down curve, do I subtract only the
> > ground-clamp curve, or do I subtract both the power-clamp and ground-clamp
> > curves? Does the EDA tool add only the ground-clamp data back in, or does
> it add
> > both curves back in?
> >
> > --
> > Regards,
> > Stephen M. Nolan
From owner-ibis  Fri Jul  7 08:56:17 2000
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: ibis-users@eda.org
Subject: RE: Subtracting clamp curves from pull-up/down curves
Date: Fri, 7 Jul 2000 08:54:00 -0700 
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Bob,

Even though Ian is correct, the real reason is TRANSIENT.  As it was
pointed out earlier, the clamp currents are static, i.e. they are not
changing while the buffer is 3-stated, driving high or low.  Now, think
how do you go from a 3-stated condition to driving low, for example.
You need to add something to the always present clamp currents to get
to the IV curve that is the SUM of the clamps and the pulldown device.
However, you have to add this extra driving current gradually, governed
by either the ramp, or Vt curve.  It is fairly easy to scale the difference
curve during this transition time while adding it to the constant clamp
curves.

If you, say, made a model with a clamp curve, and a SUM curve, as you
proposed, you would have to find a way to cross-fade the two during
this transition in such a way that the clamping portion would remain
constant during that time.  I am not sure if you can do that easily.

Of course, the fundamental question is how much should the model maker,
or the tool do.  It would be easier on the model maker to just generate
easy IV curves and let the tool do the subtraction and then summation.
The same way, it would have been easier to just describe all IV curves in
a ground relative manner and let the tool do the conversions.  When we
wrote the spec I was pushing for the difference curves and the Vcc
relative pullup and power clamp curves to make sure that the tools
use them correctly.  The neat thing about Vcc relative IV curve is that
they lend themselves to be used directly (easily) in situations when
power and ground bounce, return path, and power delivery are of interest.
These are big buzzwords in some circles today, yet many simulators are
still not able to deal with them correctly, BECAUSE they are ground
referenced for everything, even the pullup IV curves.  (Can you imagine
a pullup transistor, who's current comes from the ground pin?)

Another reason I was pushing for these types of IV curves was that I
had a behavioral model in HSPICE using controlled sources and it was
easier to use them if the IV curves were in this form.  I felt that
if it was easier to do it that way in HSPICE with the controlled
sources, it should also be easier in other tools.

In retrospect I feel that yes, we could have made it easier on the model
maker.  We would have been able to avoid all these questions and confusions.
But, I believe we would have had even more and bigger "tool differences",
opening the door for endless arguments and explanations on which tool
is doing things right or wrong.  Which one would you have preferred?  I
honestly don't know which situation would have been better.

I hope this helps to clarify your questions.

Arpad
=========================================================================



-----Original Message-----
From: Ian Dodd [mailto:idodd@cadence.com]
Sent: Friday, July 07, 2000 8:08 AM
To: Haller, Robert
Cc: 'Mike LaBonte'; ibis-users@eda.org
Subject: Re: Subtracting clamp curves from pull-up/down curves


Bob,

I think there are two obvious reasons for keeping the clamps separate:

1. It was intended that models be usable for a range of supply voltages
with the pull-up and power clamps tracking with the supply voltage
and the pull-down and ground clamps tracking with the ground rail.
This was also the rational for referencing the former to the supply voltage.

2. Separating the clamps from the pull-up/down allows modeling of
high/low/tristate
for devices that support these modes.

Recent feedback has indicated that the characteristics of many devices
change
markedly with supply voltage, so using an IBIS model for a supply voltage
other than at which it was designed, can give inaccurate results

Ian Dodd
Cadence Design Systems




"Haller, Robert" wrote:
> 
> Mike,
>         Not trying to play devil's advocate, but I have always wondered
> why the model maker has to subtract the clamps out, then the software
vendor
> 
> puts the clamps back in ?  Why not just have syntax (in IBIS) for a pullup
> and pulldown model WITH the clamp ? Thus reducing everyone's work ?
> 
> My old (internal) simulator and models were defined this way (IV curves
> included clamps)
> and it seemed a lot easier. We could feed bench data from a curve tracer
(or
> semiconductor analyzer)
> directly into the model without any math, and when you looked model curves
> they were intuitive.
> I know its probably now water over the dam,  but I was just wondering....
> 
> regards,
> Bob
> 
> Cereva Networks
> 100 Locke Drive
> Marlboro MA. 01752
> Phone: 508-486-9660 X 3365
> FAX: 508-486-9661
> Email: rhaller@cereva.com
> 
> -----Original Message-----
> From: Mike LaBonte [mailto:mikelabonte@cadence.com]
> Sent: Friday, July 07, 2000 8:28 AM
> To: ibis-users@eda.org
> Subject: Re: Subtracting clamp curves from pull-up/down curves
> 
> Stephen,
> 
> Arpad's reply indicates that both clamp curves are indeed subtracted
> to produce pullup and pulldown curves. I can verify the other side of
> your question; that simulators (at least Cadence SPECCTRAQuest)
> re-combine the curves as follows:
> 
>    low state:  pulldown + powerclamp + groundclamp
>   high state:  pullup   + powerclamp + groundclamp
> 
> So the clamps are never disabled (unless Submodel is used).
> 
> Mike LaBonte
> Cadence
> 
> Stephen Nolan wrote:
> >
> > Hello IBIS gurus,
> >
> > When creating a model for a three-state device, it is necessary to
> subtract the
> > clamp curves from the pull-up/down curves to avoid double counting, as
the
> EDA
> > tool adds the clamp-curves back in to the pull-up/down curves to obtain
> the
> > devices output charactersitics in the enabled state. Right so far?
> >
> > The question is this, do you only subtract the corresponding clamp curve
> from
> > the related pull-up/down curve, or do you subtract BOTH clamp curves
from
> each
> > pull-up/down curve?
> >
> > For example, if I am creating the pull-down curve, do I subtract only
the
> > ground-clamp curve, or do I subtract both the power-clamp and
ground-clamp
> > curves? Does the EDA tool add only the ground-clamp data back in, or
does
> it add
> > both curves back in?
> >
> > --
> > Regards,
> > Stephen M. Nolan

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To: Ian Dodd <idodd@cadence.com>, "Haller, Robert" <rhaller@cereva.com>
From: Todd Westerhoff <toddw@cadence.com>
Subject: Re: Subtracting clamp curves from pull-up/down curves
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My $0.02:

>2. Separating the clamps from the pull-up/down allows modeling of
>high/low/tristate for devices that support these modes.

Is the right answer.

Thanks, Ian!

Todd.



    Todd Westerhoff
    Product Marketing Director | High Speed Systems Design | Performance Engineering
    Cadence Design Systems | 270 Billerica Road | Chelmsford, MA  01824
    
    ph: (978) 262-6327
    fx: (978) 446-6798
    email: toddw@cadence.com
    internal information website: http://www-ma.cadence.com/~toddw 
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<html>
My $0.02:<br>
<br>
<font color="#FF0000"><b><blockquote type=cite cite>2. Separating the
clamps from the pull-up/down allows modeling of<br>
high/low/tristate for devices that support these
modes.</font></b></blockquote><br>
Is the right answer.<br>
<br>
Thanks, Ian!<br>
<br>
Todd.<br>
<br>
<br>
<br>
<div>&nbsp;&nbsp; Todd Westerhoff</div>
<div>&nbsp;&nbsp; Product Marketing Director | High Speed Systems Design
| Performance Engineering</div>
<div>&nbsp;&nbsp; Cadence Design Systems | 270 Billerica Road |
Chelmsford, MA&nbsp; 01824</div>
<div>&nbsp;&nbsp; </div>
<div>&nbsp;&nbsp; ph: (978) 262-6327</div>
<div>&nbsp;&nbsp; fx: (978) 446-6798</div>
<div>&nbsp;&nbsp; email: toddw@cadence.com</div>
&nbsp;&nbsp; internal information website:
<a href="http://www-ma.cadence.com/~toddw" EUDORA=AUTOURL>http://www-ma.cadence.com/~toddw</a>
</html>

--=====================_3491200==_.ALT--

From owner-ibis  Fri Jul  7 12:57:08 2000
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To: "Haller, Robert" <rhaller@cereva.com>, Ian Dodd <idodd@cadence.com>
From: Donald Telian <donaldt@cadence.com>
Subject: Re: Subtracting clamp curves from pull-up/down curves
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Bob,

Perhaps I can provide some background.

We knew we had to support models of devices in tri-state, so that required
the implementation of a standalone (not embedded in the output curves)
clamp section in IBIS.  If it was embedded, the EDA tool builder would not
have had enough data to figure out exactly how to remove the tri-state
clamp from the output characteristic.

Given that we had to have a clamp curve, the choice then was whether or not
to have the same curve embedded in the output curve too.  The decision on
this was based on our view at the time of how an IBIS "template" or "macro"
circuit would be built.  Our view was that the circuit would have separate
circuit elements for both "driver" and "clamp" primarily because one of
them had to have the ability to be turned "off" (for tri-state).  (And
actually, if you read closely, we did allow provision for an output only
device to have the embedding.)

So two curves were required, and we decided to NOT have overlap in the
clamp data.  That way the data could just be directly applied to the macro
circuit without anyone mucking with it.  Stepping back and looking at it,
either the model maker or the EDA tool would have to do the subtraction in
a typical macro implementation.  I guess we opted to put the burden on the
model maker.  In hindsight, this may have required 100 companies to have to
learn the process rather than 10.

What we have now is simply convention.  But this is the history, as I
recall it.

Donald T.
CADENCE



At 11:07 AM 07/07/2000 -0400, Ian Dodd wrote:
>Bob,
>
>I think there are two obvious reasons for keeping the clamps separate:
>
>1. It was intended that models be usable for a range of supply voltages
>with the pull-up and power clamps tracking with the supply voltage
>and the pull-down and ground clamps tracking with the ground rail.
>This was also the rational for referencing the former to the supply voltage.
>
>2. Separating the clamps from the pull-up/down allows modeling of
>high/low/tristate
>for devices that support these modes.
>
>Recent feedback has indicated that the characteristics of many devices change
>markedly with supply voltage, so using an IBIS model for a supply voltage
>other than at which it was designed, can give inaccurate results
>
>Ian Dodd
>Cadence Design Systems
>
>
>
>
>"Haller, Robert" wrote:
>> 
>> Mike,
>>         Not trying to play devil's advocate, but I have always wondered
>> why the model maker has to subtract the clamps out, then the software
vendor
>> 
>> puts the clamps back in ?  Why not just have syntax (in IBIS) for a pullup
>> and pulldown model WITH the clamp ? Thus reducing everyone's work ?
>> 
>> My old (internal) simulator and models were defined this way (IV curves
>> included clamps)
>> and it seemed a lot easier. We could feed bench data from a curve tracer
(or
>> semiconductor analyzer)
>> directly into the model without any math, and when you looked model curves
>> they were intuitive.
>> I know its probably now water over the dam,  but I was just wondering....
>> 
>> regards,
>> Bob
>> 
>> Cereva Networks
>> 100 Locke Drive
>> Marlboro MA. 01752
>> Phone: 508-486-9660 X 3365
>> FAX: 508-486-9661
>> Email: rhaller@cereva.com
>> 
>> -----Original Message-----
>> From: Mike LaBonte [mailto:mikelabonte@cadence.com]
>> Sent: Friday, July 07, 2000 8:28 AM
>> To: ibis-users@eda.org
>> Subject: Re: Subtracting clamp curves from pull-up/down curves
>> 
>> Stephen,
>> 
>> Arpad's reply indicates that both clamp curves are indeed subtracted
>> to produce pullup and pulldown curves. I can verify the other side of
>> your question; that simulators (at least Cadence SPECCTRAQuest)
>> re-combine the curves as follows:
>> 
>>    low state:  pulldown + powerclamp + groundclamp
>>   high state:  pullup   + powerclamp + groundclamp
>> 
>> So the clamps are never disabled (unless Submodel is used).
>> 
>> Mike LaBonte
>> Cadence
>> 
>> Stephen Nolan wrote:
>> >
>> > Hello IBIS gurus,
>> >
>> > When creating a model for a three-state device, it is necessary to
>> subtract the
>> > clamp curves from the pull-up/down curves to avoid double counting, as
the
>> EDA
>> > tool adds the clamp-curves back in to the pull-up/down curves to obtain
>> the
>> > devices output charactersitics in the enabled state. Right so far?
>> >
>> > The question is this, do you only subtract the corresponding clamp curve
>> from
>> > the related pull-up/down curve, or do you subtract BOTH clamp curves from
>> each
>> > pull-up/down curve?
>> >
>> > For example, if I am creating the pull-down curve, do I subtract only the
>> > ground-clamp curve, or do I subtract both the power-clamp and
ground-clamp
>> > curves? Does the EDA tool add only the ground-clamp data back in, or does
>> it add
>> > both curves back in?
>> >
>> > --
>> > Regards,
>> > Stephen M. Nolan
>
>
Donald Telian
PCB Systems Division
Cadence Design Systems
phone: 408-944-7791
donaldt@cadence.com
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Todd,
 
This is true, but we could have also decided to give curves
on "as measured" bases.  For 3-statable buffers then a model
would consist of a 3-stated curve, a Driving_Low curve, and
a Driving_High curve.  Note that the clamps are present in
each of these, and if nothing is done about it, double or
triple counting could happen.  This was one of the items
we worried about and wanted to prevent.
 
Don gave another good summary on the history, and why and how
this subtract stuff came about.
 
Arpad
==========================================================
 
 
 
-----Original Message-----
From: Todd Westerhoff [mailto:toddw@cadence.com]
Sent: Friday, July 07, 2000 12:32 PM
To: Ian Dodd; Haller, Robert
Cc: 'Mike LaBonte'; ibis-users@eda.org
Subject: Re: Subtracting clamp curves from pull-up/down curves


My $0.02:



2. Separating the clamps from the pull-up/down allows modeling of
high/low/tristate for devices that support these modes.


Is the right answer.

Thanks, Ian!

Todd.




   Todd Westerhoff
   Product Marketing Director | High Speed Systems Design | Performance
Engineering
   Cadence Design Systems | 270 Billerica Road | Chelmsford, MA  01824
   
   ph: (978) 262-6327
   fx: (978) 446-6798
   email: toddw@cadence.com
   internal information website: http://www-ma.cadence.com/~toddw
<http://www-ma.cadence.com/~toddw>  

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<META content="MSHTML 5.00.2920.0" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT face="Courier New" size=2><SPAN 
class=120521720-07072000>Todd,</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=120521720-07072000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=120521720-07072000>This is 
true, but we could have also decided to give curves</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=120521720-07072000>on "as 
measured" bases.&nbsp; For 3-statable buffers then a model</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=120521720-07072000>would 
consist of a 3-stated curve, a Driving_Low curve, and</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=120521720-07072000>a 
Driving_High curve.&nbsp; Note that the clamps are present 
in</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=120521720-07072000>each of 
these, and if nothing is done about it, double or</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=120521720-07072000>triple 
counting could happen.&nbsp; This was one of the items</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=120521720-07072000>we worried 
about and wanted to prevent.</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=120521720-07072000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=120521720-07072000>Don gave 
another good summary on the history, and why and how</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=120521720-07072000>this 
subtract stuff came about.</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=120521720-07072000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=120521720-07072000>Arpad</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=120521720-07072000>==========================================================</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=120521720-07072000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=120521720-07072000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=120521720-07072000></SPAN></FONT>&nbsp;</DIV>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
size=2>-----Original Message-----<BR><B>From:</B> Todd Westerhoff 
[mailto:toddw@cadence.com]<BR><B>Sent:</B> Friday, July 07, 2000 12:32 
PM<BR><B>To:</B> Ian Dodd; Haller, Robert<BR><B>Cc:</B> 'Mike LaBonte'; 
ibis-users@eda.org<BR><B>Subject:</B> Re: Subtracting clamp curves from 
pull-up/down curves<BR><BR></FONT></DIV>My $0.02:<BR><BR><FONT color=#ff0000><B>
<BLOCKQUOTE cite type="cite">2. Separating the clamps from the pull-up/down 
  allows modeling of<BR>high/low/tristate for devices that support these 
  modes.</FONT></B></BLOCKQUOTE><BR>Is the right answer.<BR><BR>Thanks, 
Ian!<BR><BR>Todd.<BR><BR><BR><BR>
<DIV>&nbsp;&nbsp; Todd Westerhoff</DIV>
<DIV>&nbsp;&nbsp; Product Marketing Director | High Speed Systems Design | 
Performance Engineering</DIV>
<DIV>&nbsp;&nbsp; Cadence Design Systems | 270 Billerica Road | Chelmsford, 
MA&nbsp; 01824</DIV>
<DIV>&nbsp;&nbsp; </DIV>
<DIV>&nbsp;&nbsp; ph: (978) 262-6327</DIV>
<DIV>&nbsp;&nbsp; fx: (978) 446-6798</DIV>
<DIV>&nbsp;&nbsp; email: toddw@cadence.com</DIV>&nbsp;&nbsp; internal 
information website: <A href="http://www-ma.cadence.com/~toddw" 
EUDORA="AUTOURL">http://www-ma.cadence.com/~toddw</A> </BODY></HTML>

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From: Al Davis <aldavis@ieee.org>
To: Stephen Nolan <s-nolan1@ti.com>, ibis-users@eda.org
Subject: Re: Subtracting clamp curves from pull-up/down curves
Date: Sun, 9 Jul 2000 00:15:09 -0700
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As everyone else said, subtract them both.

But there is more to it than that.  I have a comment and a question.

The comment .....

When you subtract, remember to consider the accuracy of the
measurements.  In the usual case, in the region where the clamp is
strong, the things you are subtracting are nearly equal and large,
producing a result near zero.  In most models, the
resulting pullup/pulldown in this region is ALL NOISE.  Those models
that look like they have a negative resistance region there are
WRONG.  The literature says that it doesn't matter because they are
added back by the simulator, but that is not the whole story.  You are
better off leaving these points out, even if it means not going the
full -Vcc to +2*Vcc.

So ...
Look at the curve!  Does it make sense?  At the ends, where the curve
looks like nonsense, throw those points away.  Those warnings from
the parser about "non-monotonic" are real.

The simulator will probably clean this up anyway, but your goal as a
model maker should be to make a model that doesn't need further
clean-up.


Now, the question ....

What should a simulator do with the clamps in the region where the
other clamp applies? 

Extend flat? (constant current) -- sure, if it is 0.  What if it
isn't?  The current at the splice is double counted.

Make it 0? -- what if they don't match?  The currents might not
match.  There might be a gap or overlap.  (Consider min or max with a
different reference voltage.)

Extend last slope? -- this makes sense totally outside, but not here.
From owner-ibis  Tue Jul 11 22:13:44 2000
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All,

I wanted to clarify and (possibly) confirm my understanding
of Dynamic clamp submodels.

My understanding is that the following submodel call will
activate the static Power Clamp only when the model is not a
driver (i.e. Input or 3-state mode).  When the driver is active
the Power clamp will not be activated.

Am I correct?



[Add Submodel]
Bleem       Non-Driving
...
...

[Submodel]     Bleem
Submodel_type   Dynamic_clamp
|
[POWER Clamp]
| voltage     I(typ)              I(min)              I(max)
|
power clamp curves removed for conciseness.


regards,

scott
--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


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Subject: Questions about Submodels
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Hi IBIS folks. I'm working on our procedures for creating IBIS models of devices
with Bus Hold, and struggling through this section 6a on Submodels. Help.

First of all, are submodels a section that is entirely contained within a model
section, or are they independant and inheritable by other models? For example,
if I have an input model:

|******************************************************************************
[Model]             LVTH244_DATAIN_33
Model_type          Input
Vinl = 0.8V
Vinh = 2.0V
C_comp              3.35pF       NA           NA
|
[Add Submodel]
BUS_HOLD_33         Non-Driving
|
|******************************************************************************

Does the submodel BUS_HOLD_33 have to follow the data in the LVTH244_DATAIN_33
model and be within that model, or can all of the submodels be at the end of a
file in a separate section following the models?

Further, once I have declared a "[Submodel] BUS_HOLD_33" submodel within the
LVTH244_DATA_IN_33 model, do I have to include the complete submodel again
within the LVTH244_OE_IN_33 model, or can I just simply call it and expect the
simulator to use it. If submodels do in fact turn out to be local instead of
global and inheritable, is there any namespace conflict?


Next is the question of data extraction for bus-hold. The clamp curves in the
main model contain all of the data on the VI characteristics of the bus
hold-circuitry. See the attached pdf file for an example. What is the purpose of
the trigger and pullup/down data in the submodel section? What information does
it provide that is not already available in the clamp curves of the main model?
How do you extract the Ramp data (test setup).


Finally, in the spec there is the following sentence:
> | The [Pullup] and [Pulldown] tables both are used to define an internal
> | buffer that is triggered switch to its opposite state.  
What does this mean and is this sentence grammatically correct? I can't figure
it out.


Thanks.
-- 
Regards,
Stephen M. Nolan
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--------------3BA6CD5C72C0AC53052914AD--

From owner-ibis  Wed Jul 12 09:42:23 2000
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From: "Le, Dat (dle)" <dle@sequent.com>
To: ibis-users@eda.org
Cc: "Le, Dat (dle)" <dle@sequent.com>
Subject: How to create AGTL+  Hspice  behavioral model 
Date: Wed, 12 Jul 2000 09:39:43 -0700
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All,

For preliminary SI investigation work, it might be beneficial to run
simulations with Hspice behavioral like I-V lookup tables, rather than Hspice
model itself.
I'm interested to hear suggestions on how to generate a behavioral Hspice
AGTL+ I/O buffer.

Thanks in advance.   
Dat Le

*****************************************
Signal Integrity Engineer
IBM Webservers (formerly Sequent)
dtle@us.ibm.com
(503)578-3412
*****************************************

From owner-ibis  Mon Jul 17 13:05:57 2000
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "'Le, Dat (dle)'" <dle@sequent.com>, ibis-users@eda.org
Subject: RE: How to create AGTL+  Hspice  behavioral model 
Date: Mon, 17 Jul 2000 13:03:27 -0700
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Did you try the B-element with IBIS models?

Arpad Muranyi
Intel Corporation
=============================================

-----Original Message-----
From: Le, Dat (dle) [mailto:dle@sequent.com]
Sent: Wednesday, July 12, 2000 9:40 AM
To: ibis-users@eda.org
Cc: Le, Dat (dle)
Subject: How to create AGTL+ Hspice behavioral model 


All,

For preliminary SI investigation work, it might be beneficial to run
simulations with Hspice behavioral like I-V lookup tables, rather than
Hspice
model itself.
I'm interested to hear suggestions on how to generate a behavioral Hspice
AGTL+ I/O buffer.

Thanks in advance.   
Dat Le

*****************************************
Signal Integrity Engineer
IBM Webservers (formerly Sequent)
dtle@us.ibm.com
(503)578-3412
*****************************************


From owner-ibis  Wed Jul 19 06:13:35 2000
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IBIS gurus, another puzzling question:

In IBIS 3.2 spec, the 100 points limit is worded as follows:

|               All four columns are required under these keywords.  However,
|               data is only required in the typical column.  If minimum
|               and/or maximum current values are not available, the reserved
|               word "NA" must be used.  "NA" can be used for currents in the
|               typical column, but numeric values MUST be specified for the
|               first and last voltage points on any I-V table.  Each I-V
|               table must have at least 2, but not more than 100, voltage
|               points.

When doing the best-100 points data-reduction algorithm, the data points that
are included should have the highest density around the areas of inflection in
the curves. However the inflection points for each of the three curves (typ,
min, max) might not be coincident on the x axis.

So the way I read this, if you have reduced the data to the best 100 points for
each curve, the x axis points may not be coincident for y axis data points on
each of the three curves. Therefore you will likely have several rows with data
points in only one of the three columns and NA in the other two.

Example:
|	V	Ityp	Imin	Imax
	-5	DATA	DATA	DATA	|The first line must always have data
	-4.9	DATA	NA	NA	|in all three columns.
	...
	-4.5	NA	DATA	NA
	...
	-4.1	NA	NA	DATA
	...
	10	DATA	DATA	DATA	|Last line must have data in all 3.

Now the question is in the interpretation of the line "Each I-V table must have
at least 2, but not more than 100, voltage points."

Does this mean that each aggregate table can only have a maximum of 100 rows of
data (100 x axis points)? Or does this mean that each column in the table can
contain a maximum of 100 y axis points? 

If the former, then you might end up with less than 33 useable data points in
any one of the three columns. If the latter, then you would have a full 100 data
points in each column, but the aggregate table would almost assuredly contain
more than 100 rows.

Thanks.	
-- 
Regards,
Stephen M. Nolan
From owner-ibis  Wed Jul 19 06:33:05 2000
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IBIS experts, please help with another question. When making an IBIS model of a
FET switch, the IBIS spec calls for the following model:

|               The model is:
|
|                                Table Current
|                                   ------->
|                               +     Vds     -
|                             Pin 1           Pin 2
|                               <---|     |--->  +
|                               d   |_____| - s
|                                    --+-- Vgs   Vs
|                                      | g  +
|                                                -
|
|                       Vg = [Voltage Range] = Vcc
|                       Vgs = Table Voltage = Vtable = Vcc - Vs
|                       Ids = Table Current for a given Vcc and Vds

The table voltage that is reported is Vgs, the voltage difference between pin 2
(in this example) and the gate voltage (usually Vcc). This is an entirely
adequate model for n-FET only series switches, however several FET switch
devices use a full transmission-gate (n-FET in parallel with p-FET). When the
switch is enabled [On] the gate of the n-FET is usually at Vcc and the gate of
the p-FET is usually at ground. 

        GND
         |
         o
       =====
      |     | p-FET
    --|     |--
    |         |
----+-|     |-+----
      |_____| n-FET
       --+--
         |
        Vcc

The question, obviously is "Which Vgs do I report in the table?"

-- 
Regards,
Stephen M. Nolan
From owner-ibis  Wed Jul 19 08:05:22 2000
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "'Stephen Nolan'" <s-nolan1@ti.com>, ibis-users@eda.org
Subject: RE: IBIS question - 100 points in a table
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Stephen,

This is exactly the same question I asked many years ago.
The specification does not say anything about it.  When I
brought it up in the Open Forum Teleconference, I believe
the answer was that to be safe we should count the X-axis
numbers.  That is what my program (Ibis Center) does.

However, I agree, that this way we may only get 33 points
in the Y-axis in the worst case, and I agree we should allow
100 points in the Y-axis.  However, the parser does not allow
that, even though in my opinion it is still legal according
to the spec.  That is why I have my algorithm written so that
with the flip of an internal constant I can count Y-axis numbers.

We did address this issue recently, when the 100 points
limitation came up again.  As a minimum, I would suggest that
we should count Y-axis numbers, but some also suggested that
we should eliminate this all together.

Arpad Muranyi
Intel Corporation
===============================================================



-----Original Message-----
From: Stephen Nolan [mailto:s-nolan1@ti.com]
Sent: Wednesday, July 19, 2000 6:11 AM
To: ibis-users@eda.org
Subject: IBIS question - 100 points in a table


IBIS gurus, another puzzling question:

In IBIS 3.2 spec, the 100 points limit is worded as follows:

|               All four columns are required under these keywords.
However,
|               data is only required in the typical column.  If minimum
|               and/or maximum current values are not available, the
reserved
|               word "NA" must be used.  "NA" can be used for currents in
the
|               typical column, but numeric values MUST be specified for the
|               first and last voltage points on any I-V table.  Each I-V
|               table must have at least 2, but not more than 100, voltage
|               points.

When doing the best-100 points data-reduction algorithm, the data points
that
are included should have the highest density around the areas of inflection
in
the curves. However the inflection points for each of the three curves (typ,
min, max) might not be coincident on the x axis.

So the way I read this, if you have reduced the data to the best 100 points
for
each curve, the x axis points may not be coincident for y axis data points
on
each of the three curves. Therefore you will likely have several rows with
data
points in only one of the three columns and NA in the other two.

Example:
|	V	Ityp	Imin	Imax
	-5	DATA	DATA	DATA	|The first line must always have
data
	-4.9	DATA	NA	NA	|in all three columns.
	...
	-4.5	NA	DATA	NA
	...
	-4.1	NA	NA	DATA
	...
	10	DATA	DATA	DATA	|Last line must have data in all 3.

Now the question is in the interpretation of the line "Each I-V table must
have
at least 2, but not more than 100, voltage points."

Does this mean that each aggregate table can only have a maximum of 100 rows
of
data (100 x axis points)? Or does this mean that each column in the table
can
contain a maximum of 100 y axis points? 

If the former, then you might end up with less than 33 useable data points
in
any one of the three columns. If the latter, then you would have a full 100
data
points in each column, but the aggregate table would almost assuredly
contain
more than 100 rows.

Thanks.	
-- 
Regards,
Stephen M. Nolan

From owner-ibis  Wed Jul 19 14:30:58 2000
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To: Scott McMorrow <scott@vasthorizons.com>
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Scott:

You are correct.

Bob Ross
Mentor Graphics


Scott McMorrow wrote:
> 
> All,
> 
> I wanted to clarify and (possibly) confirm my understanding
> of Dynamic clamp submodels.
> 
> My understanding is that the following submodel call will
> activate the static Power Clamp only when the model is not a
> driver (i.e. Input or 3-state mode).  When the driver is active
> the Power clamp will not be activated.
> 
> Am I correct?
> 
> [Add Submodel]
> Bleem       Non-Driving
> ...
> ...
> 
> [Submodel]     Bleem
> Submodel_type   Dynamic_clamp
> |
> [POWER Clamp]
> | voltage     I(typ)              I(min)              I(max)
> |
> power clamp curves removed for conciseness.
> 
> regards,
> 
> scott
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
From owner-ibis  Thu Jul 20 13:46:25 2000
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'Al Davis'" <aldavis@ieee.org>
Cc: ibis-users@eda.org
Subject: RE: Subtracting clamp curves from pull-up/down curves
Date: Thu, 20 Jul 2000 16:43:27 -0400
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From a few weeks ago....

Regarding "the comment":

>When you subtract, remember to consider the accuracy of the
>measurements.  In the usual case, in the region where the clamp is
>strong, the things you are subtracting are nearly equal and large,
>producing a result near zero.  In most models, the
>resulting pullup/pulldown in this region is ALL NOISE.  Those models
>that look like they have a negative resistance region there are
>WRONG.  The literature says that it doesn't matter because they are
>added back by the simulator, but that is not the whole story.  You are
>better off leaving these points out, even if it means not going the
>full -Vcc to +2*Vcc.
>
>So ...
>Look at the curve!  Does it make sense?  At the ends, where the curve
>looks like nonsense, throw those points away.  Those warnings from
>the parser about "non-monotonic" are real.
 
I don't entirely agree, or maybe I don't see your point.  Non-monotonicity
only matters for the total current, after the individual tables have been
summed together again.  If the total current is monotonic, but one of the
component curves isn't, it shouldn't really matter, should it?  Unless the
simulator uses the non-monotonic curve by itself somehow.  But you know more
about simulators than I do, so maybe you know something I don't.

OTOH, I doubt it hurts to smooth out (not LEAVE out!) those points, as long
as they really are "noise" and insignificant compared to the stronger clamp
current.


Regarding "the question":

>What should a simulator do with the clamps in the region where the
>other clamp applies? 
>
>Extend flat? (constant current) -- sure, if it is 0.  What if it
>isn't?  The current at the splice is double counted.
>
>Make it 0? -- what if they don't match?  The currents might not
>match.  There might be a gap or overlap.  (Consider min or max with a
>different reference voltage.)
>
>Extend last slope? -- this makes sense totally outside, but not here. 
 
Yes, this has bothered me for a while.

Personally, I think that all four curves ... Pullup, Pulldown, and both
Clamps ... should be defined in all IBIS models for I/O (pin) voltages over
the range from GND-POWER to POWER+POWER ... the whole works.  This would
force model makers into thinking about how to cut (and how the simulator
will splice) their two clamp currents.  The clamp tables might be zero over
half or more of this range, but far better to have it specified that way in
the IBIS data sheet, than to leave it up to chance, or to what the simulator
happens to do with a truncated table.

The mere fact that a table ends anywhere between GND-POWER and POWER+POWER,
is very troubling.  What if the current hasn't fallen smoothly to zero where
the table ends?

Regards,
Andy

From owner-ibis  Thu Jul 20 13:58:06 2000
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Reply-To: <tom_dagostino@mentorg.com>
From: "Tom Dagostino" <tom_dagostino@mentorg.com>
To: "'Ingraham, Andrew'" <Andrew.Ingraham@compaq.com>,
        "'Al Davis'" <aldavis@ieee.org>
Cc: <ibis-users@eda.org>
Subject: RE: Subtracting clamp curves from pull-up/down curves
Date: Thu, 20 Jul 2000 13:55:05 -0700
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I have a curiosity question.  What are the equations that describe the
current in the drain of a FET when Vds is negative for the n channel device
or Vds is positive for the p channel device?  I would like to know what the
drain current is, not the current in the diode.  I don't believe some of the
equations I have seen.

Tom Dagostino
IBIS and Tau Modeling Manager
BSD
Mentor Graphics Corp.
503-685-1613
tom_dagostino@mentor.com


-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
Sent: Thursday, July 20, 2000 1:43 PM
To: 'Al Davis'
Cc: ibis-users@eda.org
Subject: RE: Subtracting clamp curves from pull-up/down curves


>From a few weeks ago....

Regarding "the comment":

>When you subtract, remember to consider the accuracy of the
>measurements.  In the usual case, in the region where the clamp is
>strong, the things you are subtracting are nearly equal and large,
>producing a result near zero.  In most models, the
>resulting pullup/pulldown in this region is ALL NOISE.  Those models
>that look like they have a negative resistance region there are
>WRONG.  The literature says that it doesn't matter because they are
>added back by the simulator, but that is not the whole story.  You are
>better off leaving these points out, even if it means not going the
>full -Vcc to +2*Vcc.
>
>So ...
>Look at the curve!  Does it make sense?  At the ends, where the curve
>looks like nonsense, throw those points away.  Those warnings from
>the parser about "non-monotonic" are real.

I don't entirely agree, or maybe I don't see your point.  Non-monotonicity
only matters for the total current, after the individual tables have been
summed together again.  If the total current is monotonic, but one of the
component curves isn't, it shouldn't really matter, should it?  Unless the
simulator uses the non-monotonic curve by itself somehow.  But you know more
about simulators than I do, so maybe you know something I don't.

OTOH, I doubt it hurts to smooth out (not LEAVE out!) those points, as long
as they really are "noise" and insignificant compared to the stronger clamp
current.


Regarding "the question":

>What should a simulator do with the clamps in the region where the
>other clamp applies?
>
>Extend flat? (constant current) -- sure, if it is 0.  What if it
>isn't?  The current at the splice is double counted.
>
>Make it 0? -- what if they don't match?  The currents might not
>match.  There might be a gap or overlap.  (Consider min or max with a
>different reference voltage.)
>
>Extend last slope? -- this makes sense totally outside, but not here.

Yes, this has bothered me for a while.

Personally, I think that all four curves ... Pullup, Pulldown, and both
Clamps ... should be defined in all IBIS models for I/O (pin) voltages over
the range from GND-POWER to POWER+POWER ... the whole works.  This would
force model makers into thinking about how to cut (and how the simulator
will splice) their two clamp currents.  The clamp tables might be zero over
half or more of this range, but far better to have it specified that way in
the IBIS data sheet, than to leave it up to chance, or to what the simulator
happens to do with a truncated table.

The mere fact that a table ends anywhere between GND-POWER and POWER+POWER,
is very troubling.  What if the current hasn't fallen smoothly to zero where
the table ends?

Regards,
Andy

From owner-ibis  Thu Jul 20 14:25:58 2000
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Subject: Ver. 3.2 and Ver. 2.1 Models
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To Model Users and EDA Vendors:

Philips Semiconductors offers numerous standard logic Ver. 2.1 IBIS models.  We are planning to start generating Ver. 3.2 models but would like your feedback on an issue.  We are trying assess how many people have capability to run Ver 3.2 models and who 
can use only Ver 2.1 models.  Due to the number of logic families and products we have, we want to avoid maintaining 2 sets of libraries per product family for both versions, but we need to see that our customers' needs are met too.  Your comments would 
be greatly appreciated.

Mike Magdaluyo

Logic Products Group
Philips Semiconductors
(408) 991-2642
From owner-ibis  Thu Jul 20 16:26:52 2000
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Mike:

I would use and supply Version 3.2 models only when Version 3.2 features
are needed to accurately describe the part.  Otherwise, I would still
supply Version 2.1 models.

Bob Ross
Mentor Graphics

mike.magdaluyo@philips.com wrote:
> 
> To Model Users and EDA Vendors:
> 
> Philips Semiconductors offers numerous standard logic Ver. 2.1 IBIS models.  We are planning to start generating Ver. 3.2 models but would like your feedback on an issue.  We are trying assess how many people have capability to run Ver 3.2 models and who
> can use only Ver 2.1 models.  Due to the number of logic families and products we have, we want to avoid maintaining 2 sets of libraries per product family for both versions, but we need to see that our customers' needs are met too.  Your comments would
> be greatly appreciated.
> 
> Mike Magdaluyo
> 
> Logic Products Group
> Philips Semiconductors
> (408) 991-2642
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Subject: Re: Ver. 3.2 and Ver. 2.1 Models
Date: Thu, 20 Jul 2000 16:45:58 -0700
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Dear Mike Magdaluyo,

I concur with Bob Ross, except I would suggest still setting the IBIS_ver
keyword to 3.2.  If nothing else, that will cause IBISCHK3 to use it's most
strict syntax/semantic tests.

Best regards,
Matthew Flora


----- Original Message -----
From: "Bob Ross" <bob_ross@mentorg.com>
To: <mike.magdaluyo@philips.com>
Cc: <ibis-users@eda.org>
Sent: Thursday, July 20, 2000 4:23 PM
Subject: Re: Ver. 3.2 and Ver. 2.1 Models


> Mike:
>
> I would use and supply Version 3.2 models only when Version 3.2 features
> are needed to accurately describe the part.  Otherwise, I would still
> supply Version 2.1 models.
>
> Bob Ross
> Mentor Graphics
>
> mike.magdaluyo@philips.com wrote:
> >
> > To Model Users and EDA Vendors:
> >
> > Philips Semiconductors offers numerous standard logic Ver. 2.1 IBIS
models.  We are planning to start generating Ver. 3.2 models but would like
your feedback on an issue.  We are trying assess how many people have
capability to run Ver 3.2 models and who
> > can use only Ver 2.1 models.  Due to the number of logic families and
products we have, we want to avoid maintaining 2 sets of libraries per product
family for both versions, but we need to see that our customers' needs are met
too.  Your comments would
> > be greatly appreciated.
> >
> > Mike Magdaluyo
> >
> > Logic Products Group
> > Philips Semiconductors
> > (408) 991-2642
>

From owner-ibis  Thu Jul 20 17:22:19 2000
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Stephen:

At this time, I would pretend that this is still an n-FET
device and use Vgs based on the "Vcc" node.  However, the
setup and measurements would be for both the n-FET and p-FET
devices in parallel.

Bob Ross
Mentor Graphics



Stephen Nolan wrote:
> 
> IBIS experts, please help with another question. When making an IBIS model of a
> FET switch, the IBIS spec calls for the following model:
> 
> |               The model is:
> |
> |                                Table Current
> |                                   ------->
> |                               +     Vds     -
> |                             Pin 1           Pin 2
> |                               <---|     |--->  +
> |                               d   |_____| - s
> |                                    --+-- Vgs   Vs
> |                                      | g  +
> |                                                -
> |
> |                       Vg = [Voltage Range] = Vcc
> |                       Vgs = Table Voltage = Vtable = Vcc - Vs
> |                       Ids = Table Current for a given Vcc and Vds
> 
> The table voltage that is reported is Vgs, the voltage difference between pin 2
> (in this example) and the gate voltage (usually Vcc). This is an entirely
> adequate model for n-FET only series switches, however several FET switch
> devices use a full transmission-gate (n-FET in parallel with p-FET). When the
> switch is enabled [On] the gate of the n-FET is usually at Vcc and the gate of
> the p-FET is usually at ground.
> 
>         GND
>          |
>          o
>        =====
>       |     | p-FET
>     --|     |--
>     |         |
> ----+-|     |-+----
>       |_____| n-FET
>        --+--
>          |
>         Vcc
> 
> The question, obviously is "Which Vgs do I report in the table?"
> 
> --
> Regards,
> Stephen M. Nolan
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Stephen:

My responses are in your text.

Bob Ross
Mentor Graphics


Stephen Nolan wrote:
> 
> Hi IBIS folks. I'm working on our procedures for creating IBIS models of devices
> with Bus Hold, and struggling through this section 6a on Submodels. Help.
> 
> First of all, are submodels a section that is entirely contained within a model
> section, or are they independant and inheritable by other models? For example,
> if I have an input model:
> 
> |******************************************************************************
> [Model]             LVTH244_DATAIN_33
> Model_type          Input
> Vinl = 0.8V
> Vinh = 2.0V
> C_comp              3.35pF       NA           NA
> |
> [Add Submodel]
> BUS_HOLD_33         Non-Driving
> |
> |******************************************************************************
> 
> Does the submodel BUS_HOLD_33 have to follow the data in the LVTH244_DATAIN_33
> model and be within that model, or can all of the submodels be at the end of a
> file in a separate section following the models?

It can be in a separate section.

> 
> Further, once I have declared a "[Submodel] BUS_HOLD_33" submodel within the
> LVTH244_DATA_IN_33 model, do I have to include the complete submodel again
> within the LVTH244_OE_IN_33 model, or can I just simply call it and expect the
> simulator to use it. If submodels do in fact turn out to be local instead of
> global and inheritable, is there any namespace conflict?

They are global, so there is no namespace conflict.

> 
> Next is the question of data extraction for bus-hold. The clamp curves in the
> main model contain all of the data on the VI characteristics of the bus
> hold-circuitry. See the attached pdf file for an example. What is the purpose of
> the trigger and pullup/down data in the submodel section? What information does
> it provide that is not already available in the clamp curves of the main model?
> How do you extract the Ramp data (test setup).

The clamp information is in addition to the bus hold operation.  The clamp
tables should have 0 current in the normal operating regions (between 0 and
Vcc).
The Bus Hold circuitry which are really weak, triggered flip-flops are what
the submodel models.  The advantage of the submodel approach is that the
dynamic effects of the Bus Hold circuit are simulated.  The clamp approach
would capture only a static (DC) characteristic and assume instantenous
Bus Hold Operation.  

The Bus_hold operation can also be used for dynamic terminations.  That is
the main motivation for adding this to IBIS.

> 
> Finally, in the spec there is the following sentence:
> > | The [Pullup] and [Pulldown] tables both are used to define an internal
> > | buffer that is triggered switch to its opposite state.
> What does this mean and is this sentence grammatically correct? I can't figure
> it out.

It should read:
| The [Pullup] and [Pulldown] tables both are used to define an internal
| buffer that is triggered "to" switch to its opposite state.

> 
> Thanks.
> --
> Regards,
> Stephen M. Nolan
> 
>   --------------------------------------------------------------------------------
>                         Name: busholdcurves.pdf
>    busholdcurves.pdf    Type: Portable Document Format (application/pdf)
>                     Encoding: base64
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I wonder if this will hold true for all simulators. The currents that you get
will be unsolvable if you assume that it is only an nFET and you are seeing the
pFET in parallel with it. I'd be afraid on nonconvergance, or simulators giving
errors about erroneous currents.

The only alternate solution that I could provide is to use [Series current]
instead of [Series MOSFET].

Thanks, Bob, for answering my questions.
-- 
Regards,
Stephen M. Nolan


Bob Ross wrote:
> 
> Stephen:
> 
> At this time, I would pretend that this is still an n-FET
> device and use Vgs based on the "Vcc" node.  However, the
> setup and measurements would be for both the n-FET and p-FET
> devices in parallel.
> 
> Bob Ross
> Mentor Graphics
> 
> Stephen Nolan wrote:
> >
> > IBIS experts, please help with another question. When making an IBIS model of a
> > FET switch, the IBIS spec calls for the following model:
> >
> > |               The model is:
> > |
> > |                                Table Current
> > |                                   ------->
> > |                               +     Vds     -
> > |                             Pin 1           Pin 2
> > |                               <---|     |--->  +
> > |                               d   |_____| - s
> > |                                    --+-- Vgs   Vs
> > |                                      | g  +
> > |                                                -
> > |
> > |                       Vg = [Voltage Range] = Vcc
> > |                       Vgs = Table Voltage = Vtable = Vcc - Vs
> > |                       Ids = Table Current for a given Vcc and Vds
> >
> > The table voltage that is reported is Vgs, the voltage difference between pin 2
> > (in this example) and the gate voltage (usually Vcc). This is an entirely
> > adequate model for n-FET only series switches, however several FET switch
> > devices use a full transmission-gate (n-FET in parallel with p-FET). When the
> > switch is enabled [On] the gate of the n-FET is usually at Vcc and the gate of
> > the p-FET is usually at ground.
> >
> >         GND
> >          |
> >          o
> >        =====
> >       |     | p-FET
> >     --|     |--
> >     |         |
> > ----+-|     |-+----
> >       |_____| n-FET
> >        --+--
> >          |
> >         Vcc
> >
> > The question, obviously is "Which Vgs do I report in the table?"
> >
> > --
> > Regards,
> > Stephen M. Nolan
From owner-ibis  Thu Jul 20 20:26:42 2000
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Message-ID: <3977C245.D0EE5A6A@ti.com>
Date: Thu, 20 Jul 2000 22:23:49 -0500
From: Stephen Nolan <s-nolan1@ti.com>
Organization: Texas Instruments Incorporated
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So regarding data extraction, are the following statements correct?

To get the clamp curves of the top-level model, the bus-hold
feedback has to be removed from the input.

Then in the submodel:

For V_trigger:
 With the bus-hold output connected to the input, sweep the
 input voltage from low-to-high, and then from high to low and
 monitor the current at the voltage source. Where the bi-stable
 flip-flop (bus-hold circuit) transitions from opposing current
 to aiding current (passes through zero) is the V_trigger point.

For Pulldown:
 With the bus-hold output disconnected from the input,
 hold the input low, so that the bus-hold output node is low,
 and sweep the V/I curve of the bus-hold output.
 Or alternatively, you may be able to hold the input of the 
 bus-hold driver high (inverter) and the bus-hold output will
 go low. Then sweep the output VI curve.

For Pullup:
 With the bus-hold output disconnected from the input,
 hold the input high, so that the bus-hold output node is high,
 and sweep the V/I curve of the bus-hold output.
 Or alternatively, you may be able to hold the input of the 
 bus-hold driver low (inverter) and the bus-hold output will
 go high. Then sweep the output VI curve.

For Ramp:
 With the bus-hold output disconnected from the input,
 and a load capacitance connected to the output of the bus-hold
 to simulate the load of the input, ramp the input to read the
 dV/dt output edge-rates at the output of the bus-hold.
 Or alternatively, you could leave the bus-hold all hooked up and 
 provide the input stimulus at the input of the bus-hold driver stage.

For reference, assuming a buffer device ('244) with bus hold, the input stage
looks like this:


       Bus-hold output  /|
               +------o/ |----+
               |       \ |    |
               |        \|    |
               |     |\       |
PIN O----------+-----| \o-----+----------->off to rest of circuitry
      Device input   | / Input inverter/buffer
                     |/

-- 
Regards,
Stephen M. Nolan


Bob Ross wrote:
> 
> Stephen:
> 
> My responses are in your text.
> 
> Bob Ross
> Mentor Graphics
> 
> Stephen Nolan wrote:
> >
> > Hi IBIS folks. I'm working on our procedures for creating IBIS models of devices
> > with Bus Hold, and struggling through this section 6a on Submodels. Help.
> >
> > First of all, are submodels a section that is entirely contained within a model
> > section, or are they independant and inheritable by other models? For example,
> > if I have an input model:
> >
> > |******************************************************************************
> > [Model]             LVTH244_DATAIN_33
> > Model_type          Input
> > Vinl = 0.8V
> > Vinh = 2.0V
> > C_comp              3.35pF       NA           NA
> > |
> > [Add Submodel]
> > BUS_HOLD_33         Non-Driving
> > |
> > |******************************************************************************
> >
> > Does the submodel BUS_HOLD_33 have to follow the data in the LVTH244_DATAIN_33
> > model and be within that model, or can all of the submodels be at the end of a
> > file in a separate section following the models?
> 
> It can be in a separate section.
> 
> >
> > Further, once I have declared a "[Submodel] BUS_HOLD_33" submodel within the
> > LVTH244_DATA_IN_33 model, do I have to include the complete submodel again
> > within the LVTH244_OE_IN_33 model, or can I just simply call it and expect the
> > simulator to use it. If submodels do in fact turn out to be local instead of
> > global and inheritable, is there any namespace conflict?
> 
> They are global, so there is no namespace conflict.
> 
> >
> > Next is the question of data extraction for bus-hold. The clamp curves in the
> > main model contain all of the data on the VI characteristics of the bus
> > hold-circuitry. See the attached pdf file for an example. What is the purpose of
> > the trigger and pullup/down data in the submodel section? What information does
> > it provide that is not already available in the clamp curves of the main model?
> > How do you extract the Ramp data (test setup).
> 
> The clamp information is in addition to the bus hold operation.  The clamp
> tables should have 0 current in the normal operating regions (between 0 and
> Vcc).
> The Bus Hold circuitry which are really weak, triggered flip-flops are what
> the submodel models.  The advantage of the submodel approach is that the
> dynamic effects of the Bus Hold circuit are simulated.  The clamp approach
> would capture only a static (DC) characteristic and assume instantenous
> Bus Hold Operation.
> 
> The Bus_hold operation can also be used for dynamic terminations.  That is
> the main motivation for adding this to IBIS.
> 
> >
> > Finally, in the spec there is the following sentence:
> > > | The [Pullup] and [Pulldown] tables both are used to define an internal
> > > | buffer that is triggered switch to its opposite state.
> > What does this mean and is this sentence grammatically correct? I can't figure
> > it out.
> 
> It should read:
> | The [Pullup] and [Pulldown] tables both are used to define an internal
> | buffer that is triggered "to" switch to its opposite state.
> 
> >
> > Thanks.
> > --
> > Regards,
> > Stephen M. Nolan
> >
> >   --------------------------------------------------------------------------------
> >                         Name: busholdcurves.pdf
> >    busholdcurves.pdf    Type: Portable Document Format (application/pdf)
> >                     Encoding: base64
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From: Al Davis <aldavis@ieee.org>
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Subject: Re: Ver. 3.2 and Ver. 2.1 Models
Date: Thu, 20 Jul 2000 21:04:41 -0700
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Bob Ross wrote:
> > I would use and supply Version 3.2 models only when Version 3.2 features
> > are needed to accurately describe the part.  Otherwise, I would still
> > supply Version 2.1 models.

On Thu, 20 Jul 2000, Matthew Flora wrote:
> I concur with Bob Ross, except I would suggest still setting the IBIS_ver
> keyword to 3.2.  If nothing else, that will cause IBISCHK3 to use it's most
> strict syntax/semantic tests.

I suggest setting the IBIS_ver keyword to 2.1 if it is
really a 2.1 model.  If nothing else, it lets the reader
know that it will work on older simulators that only
support 2.1.

In any case, don't forget to test it.
e actually uses the "treat the drain as the
source" equivalent.

question lies the answer to whether
the non-monotonicity matters separately.  If you accept
that only the sum matters, you are accepting that they
cannot be considered separately, or the latter in the above
paragraph.  Then, why does the documentation show them as
separate elements?  Why are the names what they are? 
(which hints toward the two element meaning)

Making this assumption means you lose the distinction
between the where the other ends connect.  Now, what does
it mean when the "power clamp reference" and "pullup
reference" are different?  (another hint toward the two
element meaning)


> OTOH, I doubt it hurts to smooth out (not LEAVE out!) those points, as long
> as they really are "noise" and insignificant compared to the stronger clamp
> current.

Supplying too many points actually reduces accuracy.  For
the V/I curves, the derivative is actually more important
than the data provided.

Consider the following table:
1   2.995
2   2.995
3   2.995
4   2.996
5   2.996
6   2.996
7   2.997
8   2.997
...

you get the idea.  This is common toward the ends of a
table.  What it says is that it acts like a constant
current source from 1-3 volts, from 4-6 volts, etc.  and
has jumps between 3 and 4, and between 6 and 7.

Most likely, the real device is nearly flat, but the whole
region has a finite slope.  It would be better to just give
2 points.
From owner-ibis  Fri Jul 21 08:45:27 2000
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Organization: Cadence Design Systems
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Subject: Re: Ver. 3.2 and Ver. 2.1 Models
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Periodically I hear that IC vendors feel pressured by users to provide IBIS 3.2 models.
I concur with Bob's point, and would like to suggest that it is primarily up the IC vendor
to make this determination on a part-by-part basis. If a part can be modeled with reasonable
accuracy using only IBIS 2.1 features, then there may be no reason to utilize IBIS 3.2
features. So when customers ask for 3.2 models, it would be best to ask why. Hopefully
the reason is not "because it is the latest IBIS".

Mike LaBonte
Cadence Design Systems

Bob Ross wrote:
> 
> Mike:
> 
> I would use and supply Version 3.2 models only when Version 3.2 features
> are needed to accurately describe the part.  Otherwise, I would still
> supply Version 2.1 models.
> 
> Bob Ross
> Mentor Graphics
> 
> mike.magdaluyo@philips.com wrote:
> >
> > To Model Users and EDA Vendors:
> >
> > Philips Semiconductors offers numerous standard logic Ver. 2.1 IBIS models.  We are planning to start generating Ver. 3.2 models but would like your feedback on an issue.  We are trying assess how many people have capability to run Ver 3.2 models and who
> > can use only Ver 2.1 models.  Due to the number of logic families and products we have, we want to avoid maintaining 2 sets of libraries per product family for both versions, but we need to see that our customers' needs are met too.  Your comments would
> > be greatly appreciated.
> >
> > Mike Magdaluyo
> >
> > Logic Products Group
> > Philips Semiconductors
> > (408) 991-2642
From owner-ibis  Fri Jul 21 09:24:37 2000
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Yesterday, I wrote:

>OTOH, I doubt it hurts to smooth out (not LEAVE out!) those points, as long
>as they really are "noise" and insignificant compared to the stronger clamp
>current.
 
This was poorly worded.  What I meant to say, was that it is better to
smooth the points (for example by eliminating intermediate, noisy points),
rather than TRUNCATING them.  Don't throw all of them away; keep at least
the one on the end so that the simulator isn't left having to extrapolate
(the results of which are simulator-dependent).

Andy

From owner-ibis  Fri Jul 21 10:52:47 2000
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From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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Subject: Re: Ver. 3.2 and Ver. 2.1 Models
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We at SiQual provide IBIS version 3.2 models which
include only version 2.1 features quite often.  There are
two reasons for this:

1) This causes ibischk3 to perform it's highest level
of syntax checking.

2) Because it is our only leverage to encouraging
CAD vendors to update their simulators to support
3.2 features.

Recently, however, almost all of the models which we have
developed use IBIS 3.2 features.  Model Spec,
Dynamic Clamps and Model Selector come to mind.

Quite honestly, it is frustrating to us to find that only
one simulator vendor can consistently support these advanced
features in version 3.2.  As a result, I have no problem
in encouraging all vendors to provide version 3.2 models.

Anything we can do on the model creation end to
speed the adoption of 3.2 syntax in simulators is
goodness for the industry.

BTW, SiQual is also providing IBIS models which have
been correlated to the original Spice decks and include
the IBIS Accuracy Trailer as documentation.  I would
strongly encourage all model creators to do the same.


best regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com




Mike LaBonte wrote:

> Periodically I hear that IC vendors feel pressured by users to provide IBIS 3.2 models.
> I concur with Bob's point, and would like to suggest that it is primarily up the IC vendor
> to make this determination on a part-by-part basis. If a part can be modeled with reasonable
> accuracy using only IBIS 2.1 features, then there may be no reason to utilize IBIS 3.2
> features. So when customers ask for 3.2 models, it would be best to ask why. Hopefully
> the reason is not "because it is the latest IBIS".
>
> Mike LaBonte
> Cadence Design Systems
>
> Bob Ross wrote:
> >
> > Mike:
> >
> > I would use and supply Version 3.2 models only when Version 3.2 features
> > are needed to accurately describe the part.  Otherwise, I would still
> > supply Version 2.1 models.
> >
> > Bob Ross
> > Mentor Graphics
> >
> > mike.magdaluyo@philips.com wrote:
> > >
> > > To Model Users and EDA Vendors:
> > >
> > > Philips Semiconductors offers numerous standard logic Ver. 2.1 IBIS models.  We are planning to start generating Ver. 3.2 models but would like your feedback on an issue.  We are trying assess how many people have capability to run Ver 3.2 models and who
> > > can use only Ver 2.1 models.  Due to the number of logic families and products we have, we want to avoid maintaining 2 sets of libraries per product family for both versions, but we need to see that our customers' needs are met too.  Your comments would
> > > be greatly appreciated.
> > >
> > > Mike Magdaluyo
> > >
> > > Logic Products Group
> > > Philips Semiconductors
> > > (408) 991-2642



From owner-ibis  Fri Jul 21 12:10:23 2000
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Organization: SiQual
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Stephen,

Stephen Nolan wrote:
>What is "the IBIS Accuracy Trailer"?

Here is the directory for it on the IBIS website.

http://www.vhdl.org/pub/ibis/accuracy/


The Trailer is a bunch of comment lines at the end of
a model which are intended to document the correlation
of an IBIS model to actual measurements.  It was developed
by a number of IBIS users, along with the accuracy spec and
handbook, because of their frustration with poor model
quality.

We use the correlation metric which is defined by the
specification to compare IBIS simulations with SPICE
simulations and document these in the models we produce
with the Accuracy Trailer.

In our case, the standard test circuit we use is a driver
driving a 50 ohm microstrip transmission line which
is 8 inches long into a 5pF capacitive load.  This gives
us loads of information on the quality of IBIS simulations
into a fairly complex reflected wave environment.  Typically
our correlations are within 98 to 99% of the original
Spice waveform, according to the metric.

We now deliver all models with correlation data to the
orignal source.  Additionally, we provide reports with
pictures of the comparision waveforms to our end customers,
which are usually semiconductor manufacturers.


best regards,

scott


Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


From owner-ibis  Fri Jul 21 12:32:23 2000
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From: Stephen Nolan <s-nolan1@ti.com>
Organization: Texas Instruments Incorporated
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Thanks, Scott.

More questions:
It looks like the IBIS Accuracy Handbook simply advises that the user determine
the transmission-line parameters of the standard test board by doing lab-tests
(TDR measurements). I'm curious if anyone has done so and would be willing to
share those numbers. And/or has anyone used a 2D field solver on the board
design file to get the RLGC parameters for the "50 ohm microstrip transmission
line which is 8 inches long".

Thanks.
-- 
Regards,
Stephen M. Nolan


Scott McMorrow wrote:
> 
> Stephen,
> 
> Stephen Nolan wrote:
> >What is "the IBIS Accuracy Trailer"?
> 
> Here is the directory for it on the IBIS website.
> 
> http://www.vhdl.org/pub/ibis/accuracy/
> 
> The Trailer is a bunch of comment lines at the end of
> a model which are intended to document the correlation
> of an IBIS model to actual measurements.  It was developed
> by a number of IBIS users, along with the accuracy spec and
> handbook, because of their frustration with poor model
> quality.
> 
> We use the correlation metric which is defined by the
> specification to compare IBIS simulations with SPICE
> simulations and document these in the models we produce
> with the Accuracy Trailer.
> 
> In our case, the standard test circuit we use is a driver
> driving a 50 ohm microstrip transmission line which
> is 8 inches long into a 5pF capacitive load.  This gives
> us loads of information on the quality of IBIS simulations
> into a fairly complex reflected wave environment.  Typically
> our correlations are within 98 to 99% of the original
> Spice waveform, according to the metric.
> 
> We now deliver all models with correlation data to the
> orignal source.  Additionally, we provide reports with
> pictures of the comparision waveforms to our end customers,
> which are usually semiconductor manufacturers.
> 
> best regards,
> 
> scott
> 
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
From owner-ibis  Fri Jul 21 13:35:16 2000
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Organization: SiQual
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Stephen,

We have done some real system correlation work which we are not
at liberty to share.  However, when we do, we perform TDR measurements
of board parameters and use this to calibrate  both our field solver
results and in-circuit measurements of driver strength and edge-rate.


We then crank these into our modeling efforts.  Our results have been
very good with up to 1.5 Gbit/second data streams.

In most cases, however, we have neither the time, nor the allocated
funds to perform such a rigorous correlation.  Instead we make the
assumption that our customers are supplying validated Spice models,
which we use in further extraction and correlation work.  In many cases
we work with semiconductor vendors who do correlate their Spice
decks to real silicon.  Thus, an IBIS correlation to Spice is quite
valid.

The intent of the accuracy spec is that IBIS models be correlated
to actually measurement.  In reality, this is not always possible.  We
think that correlation to the Spice is the second best alternative
in most cases.

regards,

scott


Stephen Nolan wrote:

> Thanks, Scott.
>
> More questions:
> It looks like the IBIS Accuracy Handbook simply advises that the user determine
> the transmission-line parameters of the standard test board by doing lab-tests
> (TDR measurements). I'm curious if anyone has done so and would be willing to
> share those numbers. And/or has anyone used a 2D field solver on the board
> design file to get the RLGC parameters for the "50 ohm microstrip transmission
> line which is 8 inches long".
>
> Thanks.
> --
> Regards,
> Stephen M. Nolan
>
> Scott McMorrow wrote:
> >
> > Stephen,
> >
> > Stephen Nolan wrote:
> > >What is "the IBIS Accuracy Trailer"?
> >
> > Here is the directory for it on the IBIS website.
> >
> > http://www.vhdl.org/pub/ibis/accuracy/
> >
> > The Trailer is a bunch of comment lines at the end of
> > a model which are intended to document the correlation
> > of an IBIS model to actual measurements.  It was developed
> > by a number of IBIS users, along with the accuracy spec and
> > handbook, because of their frustration with poor model
> > quality.
> >
> > We use the correlation metric which is defined by the
> > specification to compare IBIS simulations with SPICE
> > simulations and document these in the models we produce
> > with the Accuracy Trailer.
> >
> > In our case, the standard test circuit we use is a driver
> > driving a 50 ohm microstrip transmission line which
> > is 8 inches long into a 5pF capacitive load.  This gives
> > us loads of information on the quality of IBIS simulations
> > into a fairly complex reflected wave environment.  Typically
> > our correlations are within 98 to 99% of the original
> > Spice waveform, according to the metric.
> >
> > We now deliver all models with correlation data to the
> > orignal source.  Additionally, we provide reports with
> > pictures of the comparision waveforms to our end customers,
> > which are usually semiconductor manufacturers.
> >
> > best regards,
> >
> > scott
> >
> > Scott McMorrow
> > Principal Engineer
> > SiQual, Signal Quality Engineering
> > 18735 SW Boones Ferry Road
> > Tualatin, OR  97062-3090
> > (503) 885-1231
> > http://www.siqual.com

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


From owner-ibis  Fri Jul 21 14:30:20 2000
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Organization: Cadence Design Systems
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The IBIS Models web page at http://www.eigroup.org/ibis/models.htm
has been updated. There is much more to be done on this page, but
at least it has fewer dead links now. My thanks to Jon Powell for
all the time that I now realize he has put into it over the years.

Any suggestions for corrections, additions, or enhancements to this
web page are welcome. Please send them to me (as IBIS Librarian).

Mike LaBonte
Cadence Design Systems
From owner-ibis  Fri Jul 21 17:15:02 2000
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Cc: <ibis-users@eda.org>
Subject: Re: Ver. 3.2 and Ver. 2.1 Models
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To Mike, Bob, and all,

Thanks for your advise on this issue.  We will determine which families will benefit from the enhanced features of
IBIS 3.2.  Looks like our newer families with staged outputs, dynamic output impedance, output feedback, etc.,
will be modeled more accurately using Ver. 3.2.

Regards,

Mike Magdaluyo

Logic Products Group
Philips Semiconductors
(408) 991-2642




mikelabonte@cadence.com@SMTP@cadence.com on 07/21/2000 09:45:58 AM
Sent by:	mrl@cadence.com
To:	ibis-users@eda.org@SMTP
cc:	 
Subject:	Re: Ver. 3.2 and Ver. 2.1 Models
Classification:	Restricted
Periodically I hear that IC vendors feel pressured by users to provide IBIS 3.2 models.
I concur with Bob's point, and would like to suggest that it is primarily up the IC vendor
to make this determination on a part-by-part basis. If a part can be modeled with reasonable
accuracy using only IBIS 2.1 features, then there may be no reason to utilize IBIS 3.2
features. So when customers ask for 3.2 models, it would be best to ask why. Hopefully
the reason is not "because it is the latest IBIS".

Mike LaBonte
Cadence Design Systems

Bob Ross wrote:
>
> Mike:
>
> I would use and supply Version 3.2 models only when Version 3.2 features
> are needed to accurately describe the part.  Otherwise, I would still
> supply Version 2.1 models.
>
> Bob Ross
> Mentor Graphics
>
> mike.magdaluyo@philips.com wrote:
> >
> > To Model Users and EDA Vendors:
> >
> > Philips Semiconductors offers numerous standard logic Ver. 2.1 IBIS models.  We are planning to start generating Ver. 3.2 models but would like your feedback on an issue.  We are trying assess how many people have capability to run Ver 3.2 models and
who > > can use only Ver 2.1 models.  Due to the number of logic families and products we have, we want to avoid maintaining 2 sets of libraries per product family for both versions, but we need to see that our customers' needs are met too.  Your comments
would > > be greatly appreciated.
> >
> > Mike Magdaluyo
> >
> > Logic Products Group
> > Philips Semiconductors
> > (408) 991-2642


From owner-ibis  Mon Jul 24 19:42:02 2000
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From: Dave Brand <brand@ssec.honeywell.com>
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Subject: 5 volt tolerant I/O
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Hello all,

I am trying to run a tristate output driver that will drive into ttl
inputs on 5v IC's but can tolerate
a 0v to 5v output swing if it's output is pulled there.  I did try using
voltage range, but didn't think
that would work since I wasn't sure how to get -5 to +10 for the clamps,
so I tried the pin mapping variable.

I can't seem to get the pin mapping syntax to work that allows me to
pull the output
from -5 to +10 for power clamp and ground clamp, while maintaining the
internal circuitry tied
to 3.3v. I do NOT have a pin tied to 5v going to my driver. When I go to
pin mapping, I also lose
my supply to vcc and gnd in the netlists. Maybe someone could send me
email as to
what else to try.

Thanks in advance, Dave Brand
Reply to dave.brand@honeywell.com

The input file below results in:

s2ibis2 v1.1 -- North Carolina State University
s2ibis2: Reading input file temp...done.
s2ibis2: Analyzing component TRI512_HX3000 .
s2ibis2: No POWER or GND pin associated with bus POWER_CLAMP.
         The bus has been specified as a power or ground bus in the
         [Pin Mapping] section of your input file, but it is not
         connected to a pin with model name POWER or GND.

Here is what I tried:

[pullup reference] 3.3 2.97 3.63
[pulldown reference] 0 0 0
[power clamp reference] 5 4.5 5.5
[gnd clamp reference] 0 0 0

[Pin Mapping]
1   NC          NC       GND_CLAMP   POWER_CLAMP
2   NC          DRV_VDD
3   DRV_GND     NC
4   DRV_GND     DRV_VDD
5   DRV_GND     DRV_VDD

[Pin]
1 20 PAD   TRI512
-> 4 5
2 1 VCC  POWER
3 0 GND  GND
4 10 IN  Input1  0 0 0
5 30 EN  Enable1 0 0 0

[Model]  TRI512
[Model type]  3-State
[Polarity] Non-Inverting
[Enable]        Active-Low
[Model File]  sm.soi5.nom sm.soi5.wc sm.soi5.bc
[sim time]  10.5n
[Rising waveform] 50 0 NA NA NA NA NA NA NA
[Rising waveform] 50 5 NA NA NA NA NA NA NA
[Falling waveform] 50 5 NA NA NA NA NA NA NA
[Falling waveform] 50 0 NA NA NA NA NA NA NA
[C_comp] 7.26pF 7.39pF 7.26pF

[Tr]  .7ns 1ns .5ns
[Tf]  .7ns 1ns .5ns

[Vmeas]   1.65V

[Model]  Input1
[Model type] Input
[Polarity] Non-Inverting
[Model File]  sm.soi5.nom sm.soi5.wc sm.soi5.bc
[Vinl]  0.0
[Vinh] 3.3

[Model]  Enable1
[Model type] Input
[Polarity] Inverting
[Model File]  sm.soi5.nom sm.soi5.wc sm.soi5.bc
[Vinl]  0.0
[Vinh] 3.3


From owner-ibis  Mon Jul 31 07:03:18 2000
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Message-ID: <398246BE.39DEAD26@ti.com>
Date: Fri, 28 Jul 2000 21:51:42 -0500
From: Stephen Nolan <s-nolan1@ti.com>
Organization: Texas Instruments Incorporated
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Subject: IBIS standard inconsistency
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In the IBIS standard, the keywords [IBIS Ver] and [File Rev] appear to the the
only keywords that have capitalized words other than the first word (the word
IBIS being completely capitalized accepted as an acronym). All other keyword
have the first word capitalized followed by the other words lower case. Eg.
[Comment char], [File name], [Voltage range]....

Why is there an inconsistency in the style of these keywords?

Also, some multiple-word keywords use an underscore between words instead of a
space. Eg. [GND_clamp], [POWER_clamp]. 

Again, why the inconsistency?
-- 
Regards,
Stephen M. Nolan

From owner-ibis  Mon Jul 31 07:40:55 2000
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Organization: Cadence Design Systems, Inc.
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Stephen,

My reading of the spec suggests you are free to use any of these styles..... 

| 1)  The content of the files is case sensitive, except for reserved
|     words and keywords.

| 6)  Keywords must be enclosed in square brackets, [], and must start in
|     column 1 of the line.  No space or tab is allowed immediately after the
|     opening bracket '[' or immediately before the closing bracket ']'.  If
|     used, only one space (' ') or underscore ('_') character separates the
|     parts of a multi-word keyword.

Have you experimented with the golden parser to see what it will accept?

Ian Dodd
Cadence Design Systems
idodd@cadence.com






Stephen Nolan wrote:
> 
> In the IBIS standard, the keywords [IBIS Ver] and [File Rev] appear to the the
> only keywords that have capitalized words other than the first word (the word
> IBIS being completely capitalized accepted as an acronym). All other keyword
> have the first word capitalized followed by the other words lower case. Eg.
> [Comment char], [File name], [Voltage range]....
> 
> Why is there an inconsistency in the style of these keywords?
> 
> Also, some multiple-word keywords use an underscore between words instead of a
> space. Eg. [GND_clamp], [POWER_clamp].
> 
> Again, why the inconsistency?
> --
> Regards,
> Stephen M. Nolan
From owner-ibis  Mon Jul 31 07:48:19 2000
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Subject: Re: IBIS standard inconsistency
Date: Mon, 31 Jul 2000 07:46:20 -0700
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Dear Stephen M. Nolan,

Section three of the specification does say:

| 1)  The content of the files is case sensitive, except for reserved
|     words and keywords.

and:

| 6)  Keywords must be enclosed in square brackets, [], and must start in
|     column 1 of the line.  No space or tab is allowed immediately after the
|     opening bracket '[' or immediately before the closing bracket ']'.  If
|     used, only one space (' ') or underscore ('_') character separates the
|     parts of a multi-word keyword.

So both forms you mentioned are legal.  Why the text of the specification
mixes the two is anyone's guess.

Best regards,
Matthew Flora


----- Original Message -----
From: "Stephen Nolan" <s-nolan1@ti.com>
To: <ibis-users@eda.org>
Sent: Friday, July 28, 2000 7:51 PM
Subject: IBIS standard inconsistency


> In the IBIS standard, the keywords [IBIS Ver] and [File Rev] appear to the
the
> only keywords that have capitalized words other than the first word (the
word
> IBIS being completely capitalized accepted as an acronym). All other keyword
> have the first word capitalized followed by the other words lower case. Eg.
> [Comment char], [File name], [Voltage range]....
>
> Why is there an inconsistency in the style of these keywords?
>
> Also, some multiple-word keywords use an underscore between words instead of
a
> space. Eg. [GND_clamp], [POWER_clamp].
>
> Again, why the inconsistency?
> --
> Regards,
> Stephen M. Nolan
>

From owner-ibis  Mon Jul 31 08:24:14 2000
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To: mbflora@mail.hyperlynx.com, s-nolan1@ti.com
Cc: ibis-users@eda.org
Subject: RE: IBIS standard inconsistency
Date: Mon, 31 Jul 2000 10:21:15 -0500
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I'm sure there was some intent to give examples of allowed variation! :-)

Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


> -----Original Message-----
> From: Matthew Flora [mailto:mbflora@mail.hyperlynx.com]
> Sent: Monday, July 31, 2000 9:46 AM
> To: Stephen Nolan; ibis-users@eda.org
> Subject: Re: IBIS standard inconsistency
> 
> 
> Dear Stephen M. Nolan,
> 
> Section three of the specification does say:
> 
> | 1)  The content of the files is case sensitive, except for reserved
> |     words and keywords.
> 
> and:
> 
> | 6)  Keywords must be enclosed in square brackets, [], and 
> must start in
> |     column 1 of the line.  No space or tab is allowed 
> immediately after the
> |     opening bracket '[' or immediately before the closing 
> bracket ']'.  If
> |     used, only one space (' ') or underscore ('_') 
> character separates the
> |     parts of a multi-word keyword.
> 
> So both forms you mentioned are legal.  Why the text of the 
> specification
> mixes the two is anyone's guess.
> 
> Best regards,
> Matthew Flora
> 
> 
> ----- Original Message -----
> From: "Stephen Nolan" <s-nolan1@ti.com>
> To: <ibis-users@eda.org>
> Sent: Friday, July 28, 2000 7:51 PM
> Subject: IBIS standard inconsistency
> 
> 
> > In the IBIS standard, the keywords [IBIS Ver] and [File 
> Rev] appear to the
> the
> > only keywords that have capitalized words other than the 
> first word (the
> word
> > IBIS being completely capitalized accepted as an acronym). 
> All other keyword
> > have the first word capitalized followed by the other words 
> lower case. Eg.
> > [Comment char], [File name], [Voltage range]....
> >
> > Why is there an inconsistency in the style of these keywords?
> >
> > Also, some multiple-word keywords use an underscore between 
> words instead of
> a
> > space. Eg. [GND_clamp], [POWER_clamp].
> >
> > Again, why the inconsistency?
> > --
> > Regards,
> > Stephen M. Nolan
> >
> 


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From owner-ibis  Mon Jul 31 08:33:05 2000
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From: "Hobbs, Will" <will.hobbs@intel.com>
To: "'Aubrey_Sparkman@Dell.com'" <Aubrey_Sparkman@dell.com>,
        mbflora@mail.hyperlynx.com, s-nolan1@ti.com
Cc: ibis-users@eda.org
Subject: RE: IBIS standard inconsistency
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My memory of this is a bit cloudy, but I do remember the 24-straight hour
session we spent hammering out the final version of IBIS 1.1; it's quite
possible that at 3:00 in the morning we missed it, and no one picked it
up in subsequent reviews. Fortunately, it is inconsequential.

Will

-----Original Message-----
From: Aubrey_Sparkman@Dell.com [mailto:Aubrey_Sparkman@Dell.com]
Sent: Monday, July 31, 2000 8:21 AM
To: mbflora@mail.hyperlynx.com; s-nolan1@ti.com
Cc: ibis-users@eda.org
Subject: RE: IBIS standard inconsistency


I'm sure there was some intent to give examples of allowed variation! :-)

Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


> -----Original Message-----
> From: Matthew Flora [mailto:mbflora@mail.hyperlynx.com]
> Sent: Monday, July 31, 2000 9:46 AM
> To: Stephen Nolan; ibis-users@eda.org
> Subject: Re: IBIS standard inconsistency
> 
> 
> Dear Stephen M. Nolan,
> 
> Section three of the specification does say:
> 
> | 1)  The content of the files is case sensitive, except for reserved
> |     words and keywords.
> 
> and:
> 
> | 6)  Keywords must be enclosed in square brackets, [], and 
> must start in
> |     column 1 of the line.  No space or tab is allowed 
> immediately after the
> |     opening bracket '[' or immediately before the closing 
> bracket ']'.  If
> |     used, only one space (' ') or underscore ('_') 
> character separates the
> |     parts of a multi-word keyword.
> 
> So both forms you mentioned are legal.  Why the text of the 
> specification
> mixes the two is anyone's guess.
> 
> Best regards,
> Matthew Flora
> 
> 
> ----- Original Message -----
> From: "Stephen Nolan" <s-nolan1@ti.com>
> To: <ibis-users@eda.org>
> Sent: Friday, July 28, 2000 7:51 PM
> Subject: IBIS standard inconsistency
> 
> 
> > In the IBIS standard, the keywords [IBIS Ver] and [File 
> Rev] appear to the
> the
> > only keywords that have capitalized words other than the 
> first word (the
> word
> > IBIS being completely capitalized accepted as an acronym). 
> All other keyword
> > have the first word capitalized followed by the other words 
> lower case. Eg.
> > [Comment char], [File name], [Voltage range]....
> >
> > Why is there an inconsistency in the style of these keywords?
> >
> > Also, some multiple-word keywords use an underscore between 
> words instead of
> a
> > space. Eg. [GND_clamp], [POWER_clamp].
> >
> > Again, why the inconsistency?
> > --
> > Regards,
> > Stephen M. Nolan
> >
> 


From owner-ibis  Mon Jul 31 10:27:55 2000
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------
IBIS SUMMIT 
	FIRST CALL FOR 
		PARTICIPATION, 
			PRESENTATIONS 
				& SPONSORSHIP!!!!
-------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

             I B I S   S U M M I T   M E E T I N G

Time/Date:      8:30 AM - 5:00 PM, Thursday, September 14, 2000

Location:       The Crowne Plaza Hotel (NEW LOCATION)
                10 Lincoln Square
                Worcester, MA
                Tel:  (508) 791-1600
                Fax:  (508) 791-1796
               
Content:        Presentations and Discussions

Purpose:        Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:       North East Systems Associates, Inc. (NESA),
                Cadence Design Systems,
                HyperLynx,
                Mentor Graphics, 
                IBIS Users Group
                Others to be determined
                WE ARE LOOKING FOR ADDITIONAL SPONSORS!
                  (contact Kathy Breda, breda@nesa.com
                  or Bob Ross, bob_ross@mentororg.com)

PCB Conference: September 11-15, 2000
East            Worcester's Centrum Centre
                Worcester, Massachusetts
                See http://www.pcbeast.com/ for more information.

BACKGROUND

The IBIS Users Group (IBIS East) has been formed under the leadership of  
Dr. Edward Sayre from North East Systems Associates, Inc. (NESA) and has
been meeting to consider and forward IBIS model user concerns.  As a result
of East coast meetings, the group has developed an IBIS Accuracy Handbook
document and has initiated the project to format Connector Models.  These
topics plus others of current interest to the EIA IBIS Open Forum will be
discussed at this meeting.

This meeting will be conducted as a formal IBIS Summit Meeting.  Presentation
are expected to be available and archived in an electronic format, and minutes
of the meeting will be issued.  Any pending formal decisions (votes) will be
announced at least two weeks prior to the meeting.


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and digital
circuit design are invited to participate to the Summit meeting.  If you plan
to participate, please register with the information below:

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Kathy Breda (breda@nesa.com)
  

CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.

Format of Presentation:  Overhead Projections
Time:                    15-30 Minutes
Electronic Archival:     We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees.  Formats used in
                         the past have been text, Power Point, Word, 
                         Postscript, and Acrobat.  Electronic presentations
                         should be made available by September 8, 2000.
                         Otherwise the presenter will be expected to provide
                         50 copies for distribution.


If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Kathy Breda (breda@nesa.com)


AGENDA

The agenda includes presentations, discussions, breaks, and a luncheon (which
will be provided).  This will be developed as presentation proposals are
received.  So far the following presentatation is planned:
  
  Roy Leventhal, 3Com, - "IBIS and SI at 3Com"
    (Presented by Mike LaBonte, Cadence)


LIST OF NEARBY HOTELS

See http://www.pcbeast.com for travel directions, hotels and other
information.

**************************************************************
From owner-ibis  Tue Aug  1 05:39:22 2000
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Date: Tue, 01 Aug 2000 08:36:31 -0400
From: Mike LaBonte <mikelabonte@cadence.com>
Organization: Cadence Design Systems
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Subject: Re: IBIS standard inconsistency
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The IBIS spec distinguishes between keywords and subparameters. Keywords are
enclosed within square brackets. The spec examples of keywords have space
separators, even though the spec says that underscores are allowed. The use of
opening and closing brackets makes it easy to parse these, even though they
may appear as multiple words. The spec also says that underscores and spaces
are equivalent. So even though the spec examples use [GND clamp], parsers
are supposed to recognize [GND_clamp] as being equivalent.

Subparameters have no brackets. The spec states "Spaces are not allowed in
subparameter names". An example of a subparameter name is Model_type.
Although parsers certainly can handle multiple word sequences, it works out
better that subparameters are always a single word (no spaces).

Mike LaBonte
Cadence Design Systems

Stephen Nolan wrote:
> 
> In the IBIS standard, the keywords [IBIS Ver] and [File Rev] appear to the the
> only keywords that have capitalized words other than the first word (the word
> IBIS being completely capitalized accepted as an acronym). All other keyword
> have the first word capitalized followed by the other words lower case. Eg.
> [Comment char], [File name], [Voltage range]....
> 
> Why is there an inconsistency in the style of these keywords?
> 
> Also, some multiple-word keywords use an underscore between words instead of a
> space. Eg. [GND_clamp], [POWER_clamp].
> 
> Again, why the inconsistency?
> --
> Regards,
> Stephen M. Nolan
