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_______________________________________________________________________

Vivek Mahajan           			EMC˛                    
Engineer, HW Engineering			171 South Street  
 *  (508) 435 1000 x 15347			Hopkinton, MA 01748 - 9103 
 *  vmahajan@emc.com     			http://www.emc.com
_______________________________________________________________________


 
From owner-ibis Tue Jun  5 08:17:38 2001
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Subject: How to determine per length RLC in a board
Date: Tue, 5 Jun 2001 10:16:43 -0500
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Hi, All:

If the stackup in a board is a symmetric stripline structure (GND-SIG-PWR),
the characteristic impedance is the same for switching high and low, and the
per length RLC are also the same for both switching cases.

How to determine the per length RLC in a board with a stackup like
SIG-GND-PWR? The characteristic impedance and per length RLC are
switching-dependent, but there is no way to put two values for each trace in
an ebd file.

Intel uses ebd to describe packages used for Pentium processors,I have the
same question there on the way to determine RLC values.

Your help is appreciated.

Thanks,

--
**************************************
Yaping Zhou (r3aadv)
(512) 933-5803
Motorola Semiconductor Products Sector
Final Manufacturing Technology Center
Ed Bluestein, Austin, Texas
**************************************


 
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To: Yaping Zhou <y.zhou@motorola.com>
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Subject: Re: How to determine per length RLC in a board
References: <IPEHLHEELKPPNKAMAFIPOEIDCCAA.kyoung@phaseiv.com> <00b801c0ce26$40014cc0$d2477da6@LocalHost> <3B15EAEA.E088C869@avanticorp.com> <02a901c0e9c5$6bb9c620$d2477da6@LocalHost> <001701c0edd2$8760d880$be3c0ba3@sps.mot.com>
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Yaping,

In the SIG-GND-PWR, the PWR plane is not a return path for the signal
layer. I suggest you model it as SIG-GND (microstrip). The high-speed
currents will always use the GND plane, assuming good decoupling between
PWR and GND.

Alan

Yaping Zhou wrote:
> 
> Hi, All:
> 
> If the stackup in a board is a symmetric stripline structure (GND-SIG-PWR),
> the characteristic impedance is the same for switching high and low, and the
> per length RLC are also the same for both switching cases.
> 
> How to determine the per length RLC in a board with a stackup like
> SIG-GND-PWR? The characteristic impedance and per length RLC are
> switching-dependent, but there is no way to put two values for each trace in
> an ebd file.
> 
> Intel uses ebd to describe packages used for Pentium processors,I have the
> same question there on the way to determine RLC values.
> 
> Your help is appreciated.
> 
> Thanks,
> 
> --
> **************************************
> Yaping Zhou (r3aadv)
> (512) 933-5803
> Motorola Semiconductor Products Sector
> Final Manufacturing Technology Center
> Ed Bluestein, Austin, Texas
> **************************************
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From owner-ibis Tue Jun  5 10:10:08 2001
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CC: ibis-users@eda.org
Subject: Re: How to determine per length RLC in a board
References: <IPEHLHEELKPPNKAMAFIPOEIDCCAA.kyoung@phaseiv.com> <00b801c0ce26$40014cc0$d2477da6@LocalHost> <3B15EAEA.E088C869@avanticorp.com> <02a901c0e9c5$6bb9c620$d2477da6@LocalHost> <001701c0edd2$8760d880$be3c0ba3@sps.mot.com>
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Yaping,

In both cases, the characteristic impedance and per length RLC are independent
of switching direction.

Thanks,
Vinu

Yaping Zhou wrote:

> Hi, All:
>
> If the stackup in a board is a symmetric stripline structure (GND-SIG-PWR),
> the characteristic impedance is the same for switching high and low, and the
> per length RLC are also the same for both switching cases.
>
> How to determine the per length RLC in a board with a stackup like
> SIG-GND-PWR? The characteristic impedance and per length RLC are
> switching-dependent, but there is no way to put two values for each trace in
> an ebd file.
>
> Intel uses ebd to describe packages used for Pentium processors,I have the
> same question there on the way to determine RLC values.
>
> Your help is appreciated.
>
> Thanks,
>
> --
> **************************************
> Yaping Zhou (r3aadv)
> (512) 933-5803
> Motorola Semiconductor Products Sector
> Final Manufacturing Technology Center
> Ed Bluestein, Austin, Texas
> **************************************

 
From owner-ibis Tue Jun  5 11:12:05 2001
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Subject: Re: How to determine per length RLC in a board
References: <IPEHLHEELKPPNKAMAFIPOEIDCCAA.kyoung@phaseiv.com> <00b801c0ce26$40014cc0$d2477da6@LocalHost> <3B15EAEA.E088C869@avanticorp.com> <02a901c0e9c5$6bb9c620$d2477da6@LocalHost> <001701c0edd2$8760d880$be3c0ba3@sps.mot.com> <3B1D1649.1671A295@transmeta.com>
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All,

Huh?

"Return path" as it is applied to AC Impedance, is the
instantaneous path that the fields take in traveling between multiple
conductors.

For balanced stripline, PWR-SIG-GND, the fields most absolutely
do propagate between the signal and both the power and ground
planes.  The field equally divides between the two.  As a result,
the high speed currents will use both planes.  Even a floating
conductor will "capture" fields and carry a "return current".
The fields don't know to stop until they reach a metalic object.
This follows from Maxwell's first Law.

The RLC characteristic of a stripline trace (with the same dimensions)
between two ground planes, two power planes, one power and one ground
plane are identical.  They are also identical for floating metal once
the fields are established.

The only difference in all of these configurations is in the "transition
region" to get onto the structure.  Here things get interesting.  However,
IBIS ebd models, and most of the Intel literature do not concern
themselves with modeling these effects, anyway.

regards,

scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


Alan Hilton-Nickel wrote:

> Yaping,
>
> In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> currents will always use the GND plane, assuming good decoupling between
> PWR and GND.
>
> Alan
>
> Yaping Zhou wrote:
> >
> > Hi, All:
> >
> > If the stackup in a board is a symmetric stripline structure (GND-SIG-PWR),
> > the characteristic impedance is the same for switching high and low, and the
> > per length RLC are also the same for both switching cases.
> >
> > How to determine the per length RLC in a board with a stackup like
> > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > switching-dependent, but there is no way to put two values for each trace in
> > an ebd file.
> >
> > Intel uses ebd to describe packages used for Pentium processors,I have the
> > same question there on the way to determine RLC values.
> >
> > Your help is appreciated.
> >
> > Thanks,
> >
> > --
> > **************************************
> > Yaping Zhou (r3aadv)
> > (512) 933-5803
> > Motorola Semiconductor Products Sector
> > Final Manufacturing Technology Center
> > Ed Bluestein, Austin, Texas
> > **************************************



 
From owner-ibis Tue Jun  5 11:01:16 2001
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From: "Yaping Zhou" <y.zhou@motorola.com>
To: "Alan Hilton-Nickel" <ahilton@transmeta.com>
Cc: <ibis-users@eda.org>
References: <IPEHLHEELKPPNKAMAFIPOEIDCCAA.kyoung@phaseiv.com> <00b801c0ce26$40014cc0$d2477da6@LocalHost> <3B15EAEA.E088C869@avanticorp.com> <02a901c0e9c5$6bb9c620$d2477da6@LocalHost> <001701c0edd2$8760d880$be3c0ba3@sps.mot.com> <3B1D1649.1671A295@transmeta.com>
Subject: Re: How to determine per length RLC in a board
Date: Tue, 5 Jun 2001 13:00:20 -0500
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Alan & Vinu:

Thank your for your reply.

I am actually interested in package modeling, is "good decoupling" usually a
good assumption in high-speed devices with a limited on-chip decoupling
capacitance?

Yaping

----- Original Message -----
From: "Alan Hilton-Nickel" <ahilton@transmeta.com>
To: "Yaping Zhou (r3aadv)" <y.zhou@motorola.com>
Cc: <ibis-users@eda.org>
Sent: Tuesday, June 05, 2001 12:26 PM
Subject: Re: How to determine per length RLC in a board


Yaping,

In the SIG-GND-PWR, the PWR plane is not a return path for the signal
layer. I suggest you model it as SIG-GND (microstrip). The high-speed
currents will always use the GND plane, assuming good decoupling between
PWR and GND.

Alan

Yaping Zhou wrote:
>
> Hi, All:
>
> If the stackup in a board is a symmetric stripline structure
(GND-SIG-PWR),
> the characteristic impedance is the same for switching high and low, and
the
> per length RLC are also the same for both switching cases.
>
> How to determine the per length RLC in a board with a stackup like
> SIG-GND-PWR? The characteristic impedance and per length RLC are
> switching-dependent, but there is no way to put two values for each trace
in
> an ebd file.
>
> Intel uses ebd to describe packages used for Pentium processors,I have the
> same question there on the way to determine RLC values.
>
> Your help is appreciated.
>
> Thanks,
>
> --
> **************************************
> Yaping Zhou (r3aadv)
> (512) 933-5803
> Motorola Semiconductor Products Sector
> Final Manufacturing Technology Center
> Ed Bluestein, Austin, Texas
> **************************************

 
From owner-ibis Tue Jun  5 11:33:08 2001
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References: <IPEHLHEELKPPNKAMAFIPOEIDCCAA.kyoung@phaseiv.com> <00b801c0ce26$40014cc0$d2477da6@LocalHost> <3B15EAEA.E088C869@avanticorp.com> <02a901c0e9c5$6bb9c620$d2477da6@LocalHost> <001701c0edd2$8760d880$be3c0ba3@sps.mot.com> <3B1D1649.1671A295@transmeta.com> <3B1D20BB.AFE5980E@vasthorizons.com>
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Scott,

I think you may want to re-read my reply to Yaping. He had the balanced
stripline case covered, although I agree with everything you say. 

My reply was meant to address his *other* stackup, SIG-GND-PWR. In that
case, he SIG layer is NOT between the planes. If the SIG is only
adjacent to the GND, and the PWR is on ther other side of the GND plane
from the SIG, the GND will be the dominant return path for the higher
frequency components, unless poor decoupling prevents the current from
reaching GND. 

Not wanting to argue with Maxwell (I'm under-armed) but I doubt it's
worth trying to figure out the current/frequency component of the return
current in the PWR plane in that case.

Alan

Scott McMorrow wrote:
> 
> All,
> 
> Huh?
> 
> "Return path" as it is applied to AC Impedance, is the
> instantaneous path that the fields take in traveling between multiple
> conductors.
> 
> For balanced stripline, PWR-SIG-GND, the fields most absolutely
> do propagate between the signal and both the power and ground
> planes.  The field equally divides between the two.  As a result,
> the high speed currents will use both planes.  Even a floating
> conductor will "capture" fields and carry a "return current".
> The fields don't know to stop until they reach a metalic object.
> This follows from Maxwell's first Law.
> 
> The RLC characteristic of a stripline trace (with the same dimensions)
> between two ground planes, two power planes, one power and one ground
> plane are identical.  They are also identical for floating metal once
> the fields are established.
> 
> The only difference in all of these configurations is in the "transition
> region" to get onto the structure.  Here things get interesting.  However,
> IBIS ebd models, and most of the Intel literature do not concern
> themselves with modeling these effects, anyway.
> 
> regards,
> 
> scott
> 
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
> 
> Alan Hilton-Nickel wrote:
> 
> > Yaping,
> >
> > In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> > layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> > currents will always use the GND plane, assuming good decoupling between
> > PWR and GND.
> >
> > Alan
> >
> > Yaping Zhou wrote:
> > >
> > > Hi, All:
> > >
> > > If the stackup in a board is a symmetric stripline structure (GND-SIG-PWR),
> > > the characteristic impedance is the same for switching high and low, and the
> > > per length RLC are also the same for both switching cases.
> > >
> > > How to determine the per length RLC in a board with a stackup like
> > > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > > switching-dependent, but there is no way to put two values for each trace in
> > > an ebd file.
> > >
> > > Intel uses ebd to describe packages used for Pentium processors,I have the
> > > same question there on the way to determine RLC values.
> > >
> > > Your help is appreciated.
> > >
> > > Thanks,
> > >
> > > --
> > > **************************************
> > > Yaping Zhou (r3aadv)
> > > (512) 933-5803
> > > Motorola Semiconductor Products Sector
> > > Final Manufacturing Technology Center
> > > Ed Bluestein, Austin, Texas
> > > **************************************
 
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From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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To: Yaping Zhou <y.zhou@motorola.com>
CC: Alan Hilton-Nickel <ahilton@transmeta.com>, ibis-users@eda.org
Subject: Re: How to determine per length RLC in a board
References: <IPEHLHEELKPPNKAMAFIPOEIDCCAA.kyoung@phaseiv.com> <00b801c0ce26$40014cc0$d2477da6@LocalHost> <3B15EAEA.E088C869@avanticorp.com> <02a901c0e9c5$6bb9c620$d2477da6@LocalHost> <001701c0edd2$8760d880$be3c0ba3@sps.mot.com> <3B1D1649.1671A295@transmeta.com> <003501c0ede9$62e7dfa0$be3c0ba3@sps.mot.com>
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Yaping,

Oh ...  packages become much more interesting, because
this is where the return path transitions occur.  An RLC package
model, even a multisectioned one, is based upon loop
inductances, rather than partial inductances.  As a result,
it is only an approximation ... which begins to fail with lots
of simultaneous switching.

The best that one can do is to characterize a package
section, including signals, powers and grounds with some
sort of 3D partial inductance method, and then perform the
appropriate mathematical transformations to develop
IBIS compatable models which use a loop formulation.
What you will end up with, is several different models,
rather then just one, since the problem is not unique and
depends upon the switching directions of the signals
and the power and grounds.

regards,

scott




--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



Yaping Zhou wrote:

> Alan & Vinu:
>
> Thank your for your reply.
>
> I am actually interested in package modeling, is "good decoupling" usually a
> good assumption in high-speed devices with a limited on-chip decoupling
> capacitance?
>
> Yaping
>
> ----- Original Message -----
> From: "Alan Hilton-Nickel" <ahilton@transmeta.com>
> To: "Yaping Zhou (r3aadv)" <y.zhou@motorola.com>
> Cc: <ibis-users@eda.org>
> Sent: Tuesday, June 05, 2001 12:26 PM
> Subject: Re: How to determine per length RLC in a board
>
> Yaping,
>
> In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> currents will always use the GND plane, assuming good decoupling between
> PWR and GND.
>
> Alan
>
> Yaping Zhou wrote:
> >
> > Hi, All:
> >
> > If the stackup in a board is a symmetric stripline structure
> (GND-SIG-PWR),
> > the characteristic impedance is the same for switching high and low, and
> the
> > per length RLC are also the same for both switching cases.
> >
> > How to determine the per length RLC in a board with a stackup like
> > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > switching-dependent, but there is no way to put two values for each trace
> in
> > an ebd file.
> >
> > Intel uses ebd to describe packages used for Pentium processors,I have the
> > same question there on the way to determine RLC values.
> >
> > Your help is appreciated.
> >
> > Thanks,
> >
> > --
> > **************************************
> > Yaping Zhou (r3aadv)
> > (512) 933-5803
> > Motorola Semiconductor Products Sector
> > Final Manufacturing Technology Center
> > Ed Bluestein, Austin, Texas
> > **************************************

 
From owner-ibis Tue Jun  5 13:48:25 2001
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From: "Mellitz, Richard" <richard.mellitz@intel.com>
To: ibis-users@eda.org
Subject: RE: How to determine per length RLC in a board
Date: Tue, 5 Jun 2001 13:47:27 -0700 
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SSO return paths and non-TEM effect have been compensated for in the Intel
Pentium(R)4 packages and models such that you can use gnd-sig-gnd for your
simulations. In fact you MUST use gnd-sig-vtt in a 4-way configuration.
Notice the ground-power-signal package pin pattern. This patterns assumes a
gnd-sig-vtt stackup for optimum performance. 

Richard Mellitz
Intel

-----Original Message-----
From: Scott McMorrow [mailto:scott@vasthorizons.com]
Sent: Tuesday, June 05, 2001 2:47 PM
To: Yaping Zhou
Cc: Alan Hilton-Nickel; ibis-users@eda.org
Subject: Re: How to determine per length RLC in a board


Yaping,

Oh ...  packages become much more interesting, because
this is where the return path transitions occur.  An RLC package
model, even a multisectioned one, is based upon loop
inductances, rather than partial inductances.  As a result,
it is only an approximation ... which begins to fail with lots
of simultaneous switching.

The best that one can do is to characterize a package
section, including signals, powers and grounds with some
sort of 3D partial inductance method, and then perform the
appropriate mathematical transformations to develop
IBIS compatable models which use a loop formulation.
What you will end up with, is several different models,
rather then just one, since the problem is not unique and
depends upon the switching directions of the signals
and the power and grounds.

regards,

scott




--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



Yaping Zhou wrote:

> Alan & Vinu:
>
> Thank your for your reply.
>
> I am actually interested in package modeling, is "good decoupling" usually
a
> good assumption in high-speed devices with a limited on-chip decoupling
> capacitance?
>
> Yaping
>
> ----- Original Message -----
> From: "Alan Hilton-Nickel" <ahilton@transmeta.com>
> To: "Yaping Zhou (r3aadv)" <y.zhou@motorola.com>
> Cc: <ibis-users@eda.org>
> Sent: Tuesday, June 05, 2001 12:26 PM
> Subject: Re: How to determine per length RLC in a board
>
> Yaping,
>
> In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> currents will always use the GND plane, assuming good decoupling between
> PWR and GND.
>
> Alan
>
> Yaping Zhou wrote:
> >
> > Hi, All:
> >
> > If the stackup in a board is a symmetric stripline structure
> (GND-SIG-PWR),
> > the characteristic impedance is the same for switching high and low, and
> the
> > per length RLC are also the same for both switching cases.
> >
> > How to determine the per length RLC in a board with a stackup like
> > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > switching-dependent, but there is no way to put two values for each
trace
> in
> > an ebd file.
> >
> > Intel uses ebd to describe packages used for Pentium processors,I have
the
> > same question there on the way to determine RLC values.
> >
> > Your help is appreciated.
> >
> > Thanks,
> >
> > --
> > **************************************
> > Yaping Zhou (r3aadv)
> > (512) 933-5803
> > Motorola Semiconductor Products Sector
> > Final Manufacturing Technology Center
> > Ed Bluestein, Austin, Texas
> > **************************************


 
From owner-ibis Tue Jun  5 13:48:45 2001
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Organization: Cisco Systems, Inc.
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To: Yaping Zhou <y.zhou@motorola.com>
CC: Alan Hilton-Nickel <ahilton@transmeta.com>, ibis-users@eda.org
Subject: Re: How to determine per length RLC in a board
References: <IPEHLHEELKPPNKAMAFIPOEIDCCAA.kyoung@phaseiv.com> <00b801c0ce26$40014cc0$d2477da6@LocalHost> <3B15EAEA.E088C869@avanticorp.com> <02a901c0e9c5$6bb9c620$d2477da6@LocalHost> <001701c0edd2$8760d880$be3c0ba3@sps.mot.com> <3B1D1649.1671A295@transmeta.com> <003501c0ede9$62e7dfa0$be3c0ba3@sps.mot.com>
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Yaping,

The recommended bump pattern for the SIG-GND-PWR package stackup would be as
follows:

GND bumps distributed uniformly throughout the package.
PWR bumps only at the center (area BGA) or only on the inner periphery
(perimeter BGA).

With the above pattern, since you have only one signal layer, the return
current will always flow on the nearest plane (GND in this case) even when
there is no decoupling capacitance on the chip/package between PWR and GND.

If the PWR bumps are distributed over the entire package, it gets complicated.
PWR-GND decoupling on the package may be important (depends on the
stack-up/routing/decoupling on the board on which the BGA is mounted). In any
case, the impedance will be independent of the signal transition direction.

Thanks,
Vinu

Yaping Zhou wrote:

> Alan & Vinu:
>
> Thank your for your reply.
>
> I am actually interested in package modeling, is "good decoupling" usually a
> good assumption in high-speed devices with a limited on-chip decoupling
> capacitance?
>
> Yaping
>
> ----- Original Message -----
> From: "Alan Hilton-Nickel" <ahilton@transmeta.com>
> To: "Yaping Zhou (r3aadv)" <y.zhou@motorola.com>
> Cc: <ibis-users@eda.org>
> Sent: Tuesday, June 05, 2001 12:26 PM
> Subject: Re: How to determine per length RLC in a board
>
> Yaping,
>
> In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> currents will always use the GND plane, assuming good decoupling between
> PWR and GND.
>
> Alan
>
> Yaping Zhou wrote:
> >
> > Hi, All:
> >
> > If the stackup in a board is a symmetric stripline structure
> (GND-SIG-PWR),
> > the characteristic impedance is the same for switching high and low, and
> the
> > per length RLC are also the same for both switching cases.
> >
> > How to determine the per length RLC in a board with a stackup like
> > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > switching-dependent, but there is no way to put two values for each trace
> in
> > an ebd file.
> >
> > Intel uses ebd to describe packages used for Pentium processors,I have the
> > same question there on the way to determine RLC values.
> >
> > Your help is appreciated.
> >
> > Thanks,
> >
> > --
> > **************************************
> > Yaping Zhou (r3aadv)
> > (512) 933-5803
> > Motorola Semiconductor Products Sector
> > Final Manufacturing Technology Center
> > Ed Bluestein, Austin, Texas
> > **************************************

 
From owner-ibis Tue Jun  5 22:38:04 2001
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Subject: How to model a voltage regulator.
To: ibis-users@vhdl.org
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Users,

       I am using a 3.3V, 500mA LDO regulator in a PCBA. How to model this
regulator and what are the required parameters?.

Thanks,
Anbazhagan.

 
From owner-ibis Wed Jun  6 05:00:40 2001
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From: "Mellitz, Richard" <richard.mellitz@intel.com>
To: ibis-users@eda.org
Subject: RE: How to determine per length RLC in a board
Date: Wed, 6 Jun 2001 04:59:43 -0700 
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Vinu,

PWG and GND bumps distributed within the signal bumps pattern minimizes the
non TEM discontinuity impact of the return structure of a GND-SIG-PWR board
stackup. Doesn't this sound good in theory? :-) You need to return the
current induced on all planes. One of those energy things 'ya know. Any
thing that is non TEM can be models with a lumped mesh. What you find out
when you do this is that you must add more on die PWR decoupling if the PWR
bumps are in the center of the BGA. This is especially true if IO PWR is not
the same as CORE power. 'Gotta keep core happy too, but that's another
story.  Of course you may be talking about a wire bond package... which has
another set of challenges. :-( In short, there is no general best way. There
are always trade offs. The challenge is to put good analysis data behind the
decision.

One simple approach is to model TEM structures with transmission lines and
non TEM with PEEC meshes and hope you can figure out how to ground the whole
mess so you don't have convergence problems. Then you can simplify and guard
band the bounding cases in ground referenced black boxed equivalent circuit
TEM simulation and be kind to your customers. ... enter stage right... IBIS.
It doesn't always work, but that's the challenge. :-)

... Rich

-----Original Message-----
From: Vinu Arumugham [mailto:vinu@cisco.com]
Sent: Tuesday, June 05, 2001 4:47 PM
To: Yaping Zhou
Cc: Alan Hilton-Nickel; ibis-users@eda.org
Subject: Re: How to determine per length RLC in a board


Yaping,

The recommended bump pattern for the SIG-GND-PWR package stackup would be as
follows:

GND bumps distributed uniformly throughout the package.
PWR bumps only at the center (area BGA) or only on the inner periphery
(perimeter BGA).

With the above pattern, since you have only one signal layer, the return
current will always flow on the nearest plane (GND in this case) even when
there is no decoupling capacitance on the chip/package between PWR and GND.

If the PWR bumps are distributed over the entire package, it gets
complicated.
PWR-GND decoupling on the package may be important (depends on the
stack-up/routing/decoupling on the board on which the BGA is mounted). In
any
case, the impedance will be independent of the signal transition direction.

Thanks,
Vinu

Yaping Zhou wrote:

> Alan & Vinu:
>
> Thank your for your reply.
>
> I am actually interested in package modeling, is "good decoupling" usually
a
> good assumption in high-speed devices with a limited on-chip decoupling
> capacitance?
>
> Yaping
>
> ----- Original Message -----
> From: "Alan Hilton-Nickel" <ahilton@transmeta.com>
> To: "Yaping Zhou (r3aadv)" <y.zhou@motorola.com>
> Cc: <ibis-users@eda.org>
> Sent: Tuesday, June 05, 2001 12:26 PM
> Subject: Re: How to determine per length RLC in a board
>
> Yaping,
>
> In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> currents will always use the GND plane, assuming good decoupling between
> PWR and GND.
>
> Alan
>
> Yaping Zhou wrote:
> >
> > Hi, All:
> >
> > If the stackup in a board is a symmetric stripline structure
> (GND-SIG-PWR),
> > the characteristic impedance is the same for switching high and low, and
> the
> > per length RLC are also the same for both switching cases.
> >
> > How to determine the per length RLC in a board with a stackup like
> > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > switching-dependent, but there is no way to put two values for each
trace
> in
> > an ebd file.
> >
> > Intel uses ebd to describe packages used for Pentium processors,I have
the
> > same question there on the way to determine RLC values.
> >
> > Your help is appreciated.
> >
> > Thanks,
> >
> > --
> > **************************************
> > Yaping Zhou (r3aadv)
> > (512) 933-5803
> > Motorola Semiconductor Products Sector
> > Final Manufacturing Technology Center
> > Ed Bluestein, Austin, Texas
> > **************************************


 
From owner-ibis Wed Jun  6 08:41:44 2001
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'Anbu@scmmicro.co.in'" <Anbu@scmmicro.co.in>, ibis-users@vhdl.org
Subject: RE: How to model a voltage regulator.
Date: Wed, 6 Jun 2001 08:40:27 -0700 
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Hello Anbezhagan:

  IBIS models are intended for modeling the input and output characteristics
of a digital I/O structure for use by a circuit or transmision line
simulator.  IBIS is not really intended for suppling modeling data for an
analog output such as a voltage regulator.

  Regards,
  Stephen
    

-----Original Message-----
From: Anbu@scmmicro.co.in [mailto:Anbu@scmmicro.co.in]
Sent: Tuesday, June 05, 2001 10:37 PM
To: ibis-users@vhdl.org
Subject: How to model a voltage regulator.


Users,

       I am using a 3.3V, 500mA LDO regulator in a PCBA. How to model this
regulator and what are the required parameters?.

Thanks,
Anbazhagan.


 
From owner-ibis Wed Jun  6 11:30:51 2001
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To: "Mellitz, Richard" <richard.mellitz@intel.com>
CC: ibis-users@eda.org
Subject: Re: How to determine per length RLC in a board
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Rich,

I am assuming a SIG-GND-PWR package stack-up and a board stack-up that may be 4
to say 20 layers (not GND-SIG-PWR). Boards usually have one to several ground
planes and a few power planes. With the number of different power supply
voltages on current boards, power planes tend to be split up into islands or
are implemented as shapes on surface layers. Hence power structures tend to be
poor references for signals and most routing is referenced to ground. Even if
signals were referenced to power planes, the plane voltage may not be the same
as PWR on the package. My bump pattern recommendation was based on the above.

Thanks,
Vinu


"Mellitz, Richard" wrote:

> Vinu,
>
> PWG and GND bumps distributed within the signal bumps pattern minimizes the
> non TEM discontinuity impact of the return structure of a GND-SIG-PWR board
> stackup. Doesn't this sound good in theory? :-) You need to return the
> current induced on all planes. One of those energy things 'ya know. Any
> thing that is non TEM can be models with a lumped mesh. What you find out
> when you do this is that you must add more on die PWR decoupling if the PWR
> bumps are in the center of the BGA. This is especially true if IO PWR is not
> the same as CORE power. 'Gotta keep core happy too, but that's another
> story.  Of course you may be talking about a wire bond package... which has
> another set of challenges. :-( In short, there is no general best way. There
> are always trade offs. The challenge is to put good analysis data behind the
> decision.
>
> One simple approach is to model TEM structures with transmission lines and
> non TEM with PEEC meshes and hope you can figure out how to ground the whole
> mess so you don't have convergence problems. Then you can simplify and guard
> band the bounding cases in ground referenced black boxed equivalent circuit
> TEM simulation and be kind to your customers. ... enter stage right... IBIS.
> It doesn't always work, but that's the challenge. :-)
>
> ... Rich
>
> -----Original Message-----
> From: Vinu Arumugham [mailto:vinu@cisco.com]
> Sent: Tuesday, June 05, 2001 4:47 PM
> To: Yaping Zhou
> Cc: Alan Hilton-Nickel; ibis-users@eda.org
> Subject: Re: How to determine per length RLC in a board
>
> Yaping,
>
> The recommended bump pattern for the SIG-GND-PWR package stackup would be as
> follows:
>
> GND bumps distributed uniformly throughout the package.
> PWR bumps only at the center (area BGA) or only on the inner periphery
> (perimeter BGA).
>
> With the above pattern, since you have only one signal layer, the return
> current will always flow on the nearest plane (GND in this case) even when
> there is no decoupling capacitance on the chip/package between PWR and GND.
>
> If the PWR bumps are distributed over the entire package, it gets
> complicated.
> PWR-GND decoupling on the package may be important (depends on the
> stack-up/routing/decoupling on the board on which the BGA is mounted). In
> any
> case, the impedance will be independent of the signal transition direction.
>
> Thanks,
> Vinu
>
> Yaping Zhou wrote:
>
> > Alan & Vinu:
> >
> > Thank your for your reply.
> >
> > I am actually interested in package modeling, is "good decoupling" usually
> a
> > good assumption in high-speed devices with a limited on-chip decoupling
> > capacitance?
> >
> > Yaping
> >
> > ----- Original Message -----
> > From: "Alan Hilton-Nickel" <ahilton@transmeta.com>
> > To: "Yaping Zhou (r3aadv)" <y.zhou@motorola.com>
> > Cc: <ibis-users@eda.org>
> > Sent: Tuesday, June 05, 2001 12:26 PM
> > Subject: Re: How to determine per length RLC in a board
> >
> > Yaping,
> >
> > In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> > layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> > currents will always use the GND plane, assuming good decoupling between
> > PWR and GND.
> >
> > Alan
> >
> > Yaping Zhou wrote:
> > >
> > > Hi, All:
> > >
> > > If the stackup in a board is a symmetric stripline structure
> > (GND-SIG-PWR),
> > > the characteristic impedance is the same for switching high and low, and
> > the
> > > per length RLC are also the same for both switching cases.
> > >
> > > How to determine the per length RLC in a board with a stackup like
> > > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > > switching-dependent, but there is no way to put two values for each
> trace
> > in
> > > an ebd file.
> > >
> > > Intel uses ebd to describe packages used for Pentium processors,I have
> the
> > > same question there on the way to determine RLC values.
> > >
> > > Your help is appreciated.
> > >
> > > Thanks,
> > >
> > > --
> > > **************************************
> > > Yaping Zhou (r3aadv)
> > > (512) 933-5803
> > > Motorola Semiconductor Products Sector
> > > Final Manufacturing Technology Center
> > > Ed Bluestein, Austin, Texas
> > > **************************************

 
From owner-ibis Wed Jun  6 14:36:09 2001
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From: "Mellitz, Richard" <richard.mellitz@intel.com>
To: ibis-users@eda.org
Subject: RE: How to determine per length RLC in a board
Date: Wed, 6 Jun 2001 14:35:08 -0700 
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Vinu,

I was refering to high speed degigns where the package and die (and bus)
were designed for GND-SIG-PWR. In any case, you should do return path
analysis for specific high speed buses with product constraints. There are
no general rules because there are no general boards.

... Rich

-----Original Message-----
From: Vinu Arumugham [mailto:vinu@cisco.com]
Sent: Wednesday, June 06, 2001 2:26 PM
To: Mellitz, Richard
Cc: ibis-users@eda.org
Subject: Re: How to determine per length RLC in a board


Rich,

I am assuming a SIG-GND-PWR package stack-up and a board stack-up that may
be 4
to say 20 layers (not GND-SIG-PWR). Boards usually have one to several
ground
planes and a few power planes. With the number of different power supply
voltages on current boards, power planes tend to be split up into islands or
are implemented as shapes on surface layers. Hence power structures tend to
be
poor references for signals and most routing is referenced to ground. Even
if
signals were referenced to power planes, the plane voltage may not be the
same
as PWR on the package. My bump pattern recommendation was based on the
above.

Thanks,
Vinu


"Mellitz, Richard" wrote:

> Vinu,
>
> PWG and GND bumps distributed within the signal bumps pattern minimizes
the
> non TEM discontinuity impact of the return structure of a GND-SIG-PWR
board
> stackup. Doesn't this sound good in theory? :-) You need to return the
> current induced on all planes. One of those energy things 'ya know. Any
> thing that is non TEM can be models with a lumped mesh. What you find out
> when you do this is that you must add more on die PWR decoupling if the
PWR
> bumps are in the center of the BGA. This is especially true if IO PWR is
not
> the same as CORE power. 'Gotta keep core happy too, but that's another
> story.  Of course you may be talking about a wire bond package... which
has
> another set of challenges. :-( In short, there is no general best way.
There
> are always trade offs. The challenge is to put good analysis data behind
the
> decision.
>
> One simple approach is to model TEM structures with transmission lines and
> non TEM with PEEC meshes and hope you can figure out how to ground the
whole
> mess so you don't have convergence problems. Then you can simplify and
guard
> band the bounding cases in ground referenced black boxed equivalent
circuit
> TEM simulation and be kind to your customers. ... enter stage right...
IBIS.
> It doesn't always work, but that's the challenge. :-)
>
> ... Rich
>
> -----Original Message-----
> From: Vinu Arumugham [mailto:vinu@cisco.com]
> Sent: Tuesday, June 05, 2001 4:47 PM
> To: Yaping Zhou
> Cc: Alan Hilton-Nickel; ibis-users@eda.org
> Subject: Re: How to determine per length RLC in a board
>
> Yaping,
>
> The recommended bump pattern for the SIG-GND-PWR package stackup would be
as
> follows:
>
> GND bumps distributed uniformly throughout the package.
> PWR bumps only at the center (area BGA) or only on the inner periphery
> (perimeter BGA).
>
> With the above pattern, since you have only one signal layer, the return
> current will always flow on the nearest plane (GND in this case) even when
> there is no decoupling capacitance on the chip/package between PWR and
GND.
>
> If the PWR bumps are distributed over the entire package, it gets
> complicated.
> PWR-GND decoupling on the package may be important (depends on the
> stack-up/routing/decoupling on the board on which the BGA is mounted). In
> any
> case, the impedance will be independent of the signal transition
direction.
>
> Thanks,
> Vinu
>
> Yaping Zhou wrote:
>
> > Alan & Vinu:
> >
> > Thank your for your reply.
> >
> > I am actually interested in package modeling, is "good decoupling"
usually
> a
> > good assumption in high-speed devices with a limited on-chip decoupling
> > capacitance?
> >
> > Yaping
> >
> > ----- Original Message -----
> > From: "Alan Hilton-Nickel" <ahilton@transmeta.com>
> > To: "Yaping Zhou (r3aadv)" <y.zhou@motorola.com>
> > Cc: <ibis-users@eda.org>
> > Sent: Tuesday, June 05, 2001 12:26 PM
> > Subject: Re: How to determine per length RLC in a board
> >
> > Yaping,
> >
> > In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> > layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> > currents will always use the GND plane, assuming good decoupling between
> > PWR and GND.
> >
> > Alan
> >
> > Yaping Zhou wrote:
> > >
> > > Hi, All:
> > >
> > > If the stackup in a board is a symmetric stripline structure
> > (GND-SIG-PWR),
> > > the characteristic impedance is the same for switching high and low,
and
> > the
> > > per length RLC are also the same for both switching cases.
> > >
> > > How to determine the per length RLC in a board with a stackup like
> > > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > > switching-dependent, but there is no way to put two values for each
> trace
> > in
> > > an ebd file.
> > >
> > > Intel uses ebd to describe packages used for Pentium processors,I have
> the
> > > same question there on the way to determine RLC values.
> > >
> > > Your help is appreciated.
> > >
> > > Thanks,
> > >
> > > --
> > > **************************************
> > > Yaping Zhou (r3aadv)
> > > (512) 933-5803
> > > Motorola Semiconductor Products Sector
> > > Final Manufacturing Technology Center
> > > Ed Bluestein, Austin, Texas
> > > **************************************


 
From owner-ibis Wed Jun  6 18:00:46 2001
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From: "Wang, Brian" <brian.wang@intel.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: Default value of Vmeas
Date: Wed, 6 Jun 2001 15:04:47 -0700 
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Hi, 

I checked the versin 3.2. There is no default value
of Vmeas. Should we set a default value in specification,
or something I missed ?

Thanks.

Brian Wang
Intel Corp

 
From owner-ibis Wed Jun  6 19:54:40 2001
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Date: Thu, 07 Jun 2001 10:53:43 +0800
From: Hailong Wang <hlwang@avanticorp.com>
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To: ibis-users@eda.org
Subject: Which pin should be connected by Pin 16
References: <B6E52B5EDFAFD411BA42009027AE9D580C8918AE@FMSMSX39> <3B1E75D0.A59039AC@cisco.com>
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--------------7F8E38A33C09264C9741BB75
Content-Type: text/plain; charset=gb2312
Content-Transfer-Encoding: 7bit

Hi,
    In Page 73 - Page 75 of the IBIS Specification Ver3.2, there are the following
lines:

[Path Description] CAS_2
Pin J25
Len = 0.5 L=8.35n C=3.34p R=0.01 /
Node u21.15
Len = 0.5 L=8.35n C=3.34p R=0.01 /
Node u22.15
Len = 0.5 L=8.35n C=3.34p R=0.01 /
Node u23.15

....

[Reference Designator Map]
|
| External Part References:
|
| Ref Des File name Component name
u23 pp100.ibs Pentium(R)__Pro_Processor
u24 simm.ebd 16Meg X 36 SIMM Module
u25 ls244.ibs National 74LS244a
u26 r10K.ibs My_10K_Pullup

I want to know which node of buffer in pp100.ibs(node of B element) pin u23.15
connects to.

Your help is appreciated very much.

--
Best Regards.
Hai-long Wang
Tel:021-62837026x228
Avant! Shanghai R&D Center,  16th Floor, SunTong InfoPort Plaza
No.55, West Huaihai Road, Shanghai, 200030, P.R.China



--------------7F8E38A33C09264C9741BB75
Content-Type: text/html; charset=gb2312
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hi,
<br>&nbsp;&nbsp;&nbsp; In Page 73 - Page 75 of the IBIS&nbsp;Specification
Ver3.2, there are the following lines:
<p>[Path Description] CAS_2
<br>Pin J25
<br>Len = 0.5 L=8.35n C=3.34p R=0.01 /
<br>Node u21.15
<br>Len = 0.5 L=8.35n C=3.34p R=0.01 /
<br>Node u22.15
<br>Len = 0.5 L=8.35n C=3.34p R=0.01 /
<br>Node u23.15
<p>....
<p>[Reference Designator Map]
<br>|
<br>| External Part References:
<br>|
<br>| Ref Des File name Component name
<br>u23 pp100.ibs Pentium(R)__Pro_Processor
<br>u24 simm.ebd 16Meg X 36 SIMM Module
<br>u25 ls244.ibs National 74LS244a
<br>u26 r10K.ibs My_10K_Pullup
<p>I want to know which node of buffer in pp100.ibs(node of B element)
pin u23.15 connects to.
<p>Your help is appreciated very much.
<pre>--&nbsp;
Best Regards.
Hai-long Wang
Tel:021-62837026x228
Avant! Shanghai R&amp;D Center,&nbsp; 16th Floor, SunTong InfoPort Plaza
No.55, West Huaihai Road, Shanghai, 200030, P.R.China</pre>
&nbsp;</html>

--------------7F8E38A33C09264C9741BB75--

 
From owner-ibis Thu Jun  7 07:44:12 2001
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Date: Thu, 7 Jun 2001 07:42:59 -0700
From: Kim Helliwell <kimgh@apple.com>
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	format=flowed;
	charset=us-ascii
Subject: Re: Default value of Vmeas
Cc: "'ibis-users@eda.org'" <ibis-users@eda.org>
To: "Wang, Brian" <brian.wang@intel.com>
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I believe it's left to the simulator vendor what to do about
Vmeas defaults.  At least one I know about defaults it to
midway between Vinl and Vinh.  And I suspect that's
what most simulators do; it's the obvious choice.

Kim

On Wednesday, June 6, 2001, at 03:04 PM, Wang, Brian wrote:

> Hi,
>
> I checked the versin 3.2. There is no default value
> of Vmeas. Should we set a default value in specification,
> or something I missed ?
>
> Thanks.
>
> Brian Wang
> Intel Corp
>

Kim Helliwell
Apple Computer
kimgh@apple.com
408 974 9936
 
From owner-ibis Thu Jun  7 08:48:01 2001
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From: "Todd Westerhoff" <twester@hhnetwk.com>
To: <ibis-users@eda.org>
Subject: RE: Default value of Vmeas
Date: Thu, 7 Jun 2001 11:47:22 -0400
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I don't see how there could be a default value.  Vmeas is the voltage the
semiconductor vendor guarantees the device timing numbers to, and there
can't be a "standard" value for this voltage across multiple technologies.
If the value is left unspecified in the IBIS model, tools shouldn't "hide"
the problem by assuming a default - they should red-flag it.

Make sense?

Todd.

Todd Westerhoff
SI Engineer
Hammerhead Networks
5 Federal Street
Billerica, MA  01821
twester@hhnetwk.com
ph: 978-671-5084

-----Original Message-----
From: Wang, Brian [mailto:brian.wang@intel.com]
Sent: Wednesday, June 06, 2001 6:05 PM
To: 'ibis-users@eda.org'
Subject: Default value of Vmeas


Hi,

I checked the versin 3.2. There is no default value
of Vmeas. Should we set a default value in specification,
or something I missed ?

Thanks.

Brian Wang
Intel Corp

 
From owner-ibis Thu Jun  7 09:30:28 2001
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'Hailong Wang'" <hlwang@avanticorp.com>, ibis-users@eda.org
Subject: RE: Which pin should be connected by Pin 16
Date: Thu, 7 Jun 2001 09:09:10 -0700 
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Hello Hailong:
 
I'm not entirely sure what you are asking, but...   Node "u23.15" represents
pin 15 on a component with the reference designation "U23".  In the IBIS
file that describes this component, the [Pin] keyword is used to associate
or 'tie' pin 15 to a particular IBIS model.  If this model were to be
implemented using an HSPICE B-element, pin 15 would connected to the input,
output or I/O port of the B-element.
 
Also, please note that the lines you copied out of the IBIS specification
are made up examples.  Their purpose is to illustrate what a [Path
Description] and [Reference Designator Map] look like.  The examples do NOT
represent any actual components or netlists.  I do not know if a pp100.ibs
file even exists. 
 
Regards,
Stephen Peters
Intel Corp.
 

-----Original Message-----
From: Hailong Wang [mailto:hlwang@avanticorp.com]
Sent: Wednesday, June 06, 2001 7:54 PM
To: ibis-users@eda.org
Subject: Which pin should be connected by Pin 16


Hi, 
    In Page 73 - Page 75 of the IBIS Specification Ver3.2, there are the
following lines: 

[Path Description] CAS_2 
Pin J25 
Len = 0.5 L=8.35n C=3.34p R=0.01 / 
Node u21.15 
Len = 0.5 L=8.35n C=3.34p R=0.01 / 
Node u22.15 
Len = 0.5 L=8.35n C=3.34p R=0.01 / 
Node u23.15 


.... 


[Reference Designator Map] 
| 
| External Part References: 
| 
| Ref Des File name Component name 
u23 pp100.ibs Pentium(R)__Pro_Processor 
u24 simm.ebd 16Meg X 36 SIMM Module 
u25 ls244.ibs National 74LS244a 
u26 r10K.ibs My_10K_Pullup 


I want to know which node of buffer in pp100.ibs(node of B element) pin u23.
15 connects to. 


Your help is appreciated very much. 

-- 

Best Regards.

Hai-long Wang

Tel:021-62837026x228

Avant! Shanghai R&D Center,  16th Floor, SunTong InfoPort Plaza

No.55, West Huaihai Road, Shanghai, 200030, P.R.China
  


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	charset="gb2312"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=gb2312">


<META content="MSHTML 5.00.2920.0" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=021084515-07062001>Hello 
Hailong:</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=021084515-07062001></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=021084515-07062001>I'm 
not entirely sure what you are asking, but...&nbsp;&nbsp;&nbsp;Node "u23.15"  
represents pin 15 on a component with the reference designation 
"U23".&nbsp;&nbsp;In the&nbsp;IBIS file that describes this component, the [Pin] 
keyword&nbsp;is used to associate or 'tie' pin 15 to a&nbsp;particular IBIS 
model.&nbsp; If this model were to be implemented using an HSPICE B-element, pin 
15 would connected to the input, output or I/O port of the 
B-element.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=021084515-07062001></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=021084515-07062001>Also, 
please note that the lines you copied out of the IBIS specification are made up 
examples.&nbsp; Their purpose is to illustrate what a [Path Description] and 
[Reference Designator Map] look like.&nbsp; The examples do&nbsp;NOT 
represent&nbsp;any actual&nbsp;components or netlists.&nbsp; I do not know if a 
pp100.ibs file&nbsp;even exists.&nbsp;</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=021084515-07062001></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=021084515-07062001>Regards,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=021084515-07062001>Stephen Peters</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=021084515-07062001>Intel 
Corp.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=021084515-07062001></SPAN></FONT>&nbsp;</DIV>
<BLOCKQUOTE>
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Hailong Wang 
  [mailto:hlwang@avanticorp.com]<BR><B>Sent:</B> Wednesday, June 06, 2001 7:54 
  PM<BR><B>To:</B> ibis-users@eda.org<BR><B>Subject:</B> Which pin should be 
  connected by Pin 16<BR><BR></DIV></FONT>Hi, <BR>&nbsp;&nbsp;&nbsp; In Page 73 
  - Page 75 of the IBIS&nbsp;Specification Ver3.2, there are the following 
  lines: 
  <P>[Path Description] CAS_2 <BR>Pin J25 <BR>Len = 0.5 L=8.35n C=3.34p R=0.01 / 
  <BR>Node u21.15 <BR>Len = 0.5 L=8.35n C=3.34p R=0.01 / <BR>Node u22.15 <BR>Len 
  = 0.5 L=8.35n C=3.34p R=0.01 / <BR>Node u23.15 
  <P>.... 
  <P>[Reference Designator Map] <BR>| <BR>| External Part References: <BR>| 
  <BR>| Ref Des File name Component name <BR>u23 pp100.ibs 
  Pentium(R)__Pro_Processor <BR>u24 simm.ebd 16Meg X 36 SIMM Module <BR>u25 
  ls244.ibs National 74LS244a <BR>u26 r10K.ibs My_10K_Pullup 
  <P>I want to know which node of buffer in pp100.ibs(node of B element) pin 
  u23.15 connects to. 
  <P>Your help is appreciated very much. <PRE>--&nbsp;
Best Regards.
Hai-long Wang
Tel:021-62837026x228
Avant! Shanghai R&amp;D Center,&nbsp; 16th Floor, SunTong InfoPort Plaza
No.55, West Huaihai Road, Shanghai, 200030, P.R.China</PRE>&nbsp; 
</BLOCKQUOTE></BODY></HTML>

------_=_NextPart_001_01C0EF6C.301D58F0--

 
From owner-ibis Thu Jun  7 10:15:43 2001
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Date: Thu, 7 Jun 2001 10:14:30 -0700
From: Kim Helliwell <kimgh@apple.com>
Content-Type: text/plain;
	format=flowed;
	charset=us-ascii
Subject: Re: Default value of Vmeas
Cc: ibis-users@eda.org
To: Todd Westerhoff <twester@hhnetwk.com>
X-Mailer: Apple Mail (2.388)
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It does make sense.   The tool I mentioned does provide a
warning and states what will be done about it, so it doesn't
"hide" anything.

Kim

On Thursday, June 7, 2001, at 08:47 AM, Todd Westerhoff wrote:

> I don't see how there could be a default value.  Vmeas is the voltage 
> the
> semiconductor vendor guarantees the device timing numbers to, and there
> can't be a "standard" value for this voltage across multiple 
> technologies.
> If the value is left unspecified in the IBIS model, tools shouldn't 
> "hide"
> the problem by assuming a default - they should red-flag it.
>
> Make sense?
>
> Todd.
>
> Todd Westerhoff
> SI Engineer
> Hammerhead Networks
> 5 Federal Street
> Billerica, MA  01821
> twester@hhnetwk.com
> ph: 978-671-5084
>
> -----Original Message-----
> From: Wang, Brian [mailto:brian.wang@intel.com]
> Sent: Wednesday, June 06, 2001 6:05 PM
> To: 'ibis-users@eda.org'
> Subject: Default value of Vmeas
>
>
> Hi,
>
> I checked the versin 3.2. There is no default value
> of Vmeas. Should we set a default value in specification,
> or something I missed ?
>
> Thanks.
>
> Brian Wang
> Intel Corp
>

Kim Helliwell
Apple Computer
kimgh@apple.com
408 974 9936
 
From owner-ibis Thu Jun  7 12:19:02 2001
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From: "Wang, Brian" <brian.wang@intel.com>
To: "'Todd Westerhoff'" <twester@hhnetwk.com>, ibis-users@eda.org
Subject: RE: Default value of Vmeas
Date: Thu, 7 Jun 2001 10:54:28 -0700 
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Todd,

OK, You are right. Also, when we use some tools,
we have to know whether the tool uses some default value, so that
we can evaluate the accuracy.

Thanks.

Brian
-----Original Message-----
From: Todd Westerhoff [mailto:twester@hhnetwk.com]
Sent: Thursday, June 07, 2001 8:47 AM
To: ibis-users@eda.org
Subject: RE: Default value of Vmeas


I don't see how there could be a default value.  Vmeas is the voltage the
semiconductor vendor guarantees the device timing numbers to, and there
can't be a "standard" value for this voltage across multiple technologies.
If the value is left unspecified in the IBIS model, tools shouldn't "hide"
the problem by assuming a default - they should red-flag it.

Make sense?

Todd.

Todd Westerhoff
SI Engineer
Hammerhead Networks
5 Federal Street
Billerica, MA  01821
twester@hhnetwk.com
ph: 978-671-5084

-----Original Message-----
From: Wang, Brian [mailto:brian.wang@intel.com]
Sent: Wednesday, June 06, 2001 6:05 PM
To: 'ibis-users@eda.org'
Subject: Default value of Vmeas


Hi,

I checked the versin 3.2. There is no default value
of Vmeas. Should we set a default value in specification,
or something I missed ?

Thanks.

Brian Wang
Intel Corp


 
From owner-ibis Fri Jun  8 13:11:20 2001
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Subject: ibis2spice

I've found the Ibis2spice that is offered by Intusoft, but I'm
wondering if there is a version of something similar for
Unix.  I'm particularly interested in a GPL version.  Is
there such a beast?


Kim Helliwell
Apple Computer
kimgh@apple.com
408 974 9936
 
From owner-ibis Fri Jun  8 13:31:06 2001
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To: Kim Helliwell <kimgh@apple.com>
Cc: "'ibis-Users@Eda.Org'" <ibis-users@eda.org>
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Kim,

Apsim has the IBIS ToolKit.

Adam Tambone






Kim Helliwell <kimgh@apple.com> on 06/08/2001 04:10:06 PM

To:   "'ibis-Users@Eda.Org'" <ibis-users@eda.org>
cc:

Subject:  ibis2spice


I've found the Ibis2spice that is offered by Intusoft, but I'm
wondering if there is a version of something similar for
Unix.  I'm particularly interested in a GPL version.  Is
there such a beast?


Kim Helliwell
Apple Computer
kimgh@apple.com
408 974 9936




 
From owner-ibis Fri Jun  8 13:47:15 2001
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From: "Bill Clifford" <bvc3@prodigy.net>
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Subject: Differential output buffers
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Hello.  I'm trying to convert a SPICE model of a differential output =
buffer to an IBIS model.  I've been using s2ibis2 for other models, but =
this doesn't work for the differential.  What other tools are available =
that would be able to do this?  Or do I just have to process the SPICE =
data myself into the IBIS format?  Any information is greatly =
appreciated.  Thanks in advance.

Bill Clifford

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<DIV><FONT face=3DArial size=3D2>Hello.&nbsp; I'm trying to convert a =
SPICE model of=20
a differential output buffer to an IBIS model.&nbsp; I've been using =
s2ibis2 for=20
other models, but this doesn't work for the differential.&nbsp; What =
other tools=20
are available that would be able to do this?&nbsp; Or do I just have to =
process=20
the SPICE data myself into the IBIS format?&nbsp; Any information is =
greatly=20
appreciated.&nbsp; Thanks in advance.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Bill =
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From: Al Davis <aldavis@ieee.org>
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On Fri, 08 Jun 2001, Kim Helliwell wrote:
> I've found the Ibis2spice that is offered by Intusoft, but I'm
> wondering if there is a version of something similar for
> Unix.  I'm particularly interested in a GPL version.  Is
> there such a beast?

There will be.  I'm working on it.  It is based on the new IBIS-X, 
and will also support the new connector standard.
 
From owner-ibis Fri Jun  8 14:54:11 2001
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From: Syed Huq <shuq@cisco.com>
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Subject: Re: Differential output buffers
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Bill,

If you can run a SPICE simulation for a Diff output, you can use s2ibis2 to do 
the translation. Even if s2ibis2 does not support a specific keyword to achieve 
this, you can put all the necessary SPICE syntax in the .sp file or even in
the .spi file generated by s2ibis2 to handle it.

It just takes a little bit more of an effort.

BTW, s2ibis2 was written to support IBISv2.1 which has poor support for any
type of Diff Outputs.

Syed
Cisco Systems, Inc

> From: "Bill Clifford" <bvc3@prodigy.net>
> To: <ibis-users@eda.org>
> Subject: Differential output buffers
> Date: Fri, 11 May 2001 13:40:21 -0700
> MIME-Version: 1.0
> X-Priority: 3
> X-MSMail-Priority: Normal
> X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6600
> 
> Hello.  I'm trying to convert a SPICE model of a differential output buffer to 
an IBIS model.  I've been using s2ibis2 for other models, but this doesn't work 
for the differential.  What other tools are available that would be able to do 
this?  Or do I just have to process the SPICE data myself into the IBIS format?  
Any information is greatly appreciated.  Thanks in advance.
> 
> Bill Clifford

 
From owner-ibis Mon Jun 11 06:19:42 2001
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Subject: connector ebd model
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Hello,

does anybody have a nice sample of an ebd model for a connector?
I cannot find anything recent at
http://www.eda.org/pub/ibis/connector/samples_v031/

Thanx,

Alex

------------------------------------------------------
Alex Hilbers          Email:      alex.hilbers@asml.nl
ASML                  Tel:        +31(0)402685587
P.O. Box 324          Fax:        +31(0)402685530
5500 AH  Veldhoven    Building    7K-1005
The Netherlands       Department: EDEV
to glow or not to, that is the e = mission  
------------------------------------------------------

 
From owner-ibis Mon Jun 11 15:11:36 2001
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Subject: Nice Chatting
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Hello.
     I enjoyed this informative forum for learnign more about the desing 
method and issued wiht the Ibis characterisation and modeling method for the 
I/O process description. Its helped alot in correlating observations in the 
design evaluation and review process of some work I had done on high speed 
development desings.
       Good luck as you transition and continually improve this spec and the 
standards.
        Ill be using Spice method, my background and workstyle promote me to 
not trust the answers that the Ibis method can provide for my future signal 
integrity needs.
     Jeff Mills
     Gecko Desing consulting
    G3E9C1K20 Electronics Consulting
   
 
From owner-ibis Mon Jun 11 21:38:42 2001
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subscribe

 
From owner-ibis Wed Jun 13 05:35:44 2001
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Date: Wed, 13 Jun 2001 14:34:44 +0200 (MET DST)
From: Alex Hilbers <alex.hilbers@asml.com>
Reply-To: Alex Hilbers <alex.hilbers@asml.com>
Subject: website www.eigroup.org protected or server down?
To: ibis-users@eda.org
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Hello,
I have tried to reach
http://www.eigroup.org/ibis/models.htm 
but got an error
Regards,
Alex

------------------------------------------------------
Alex Hilbers          Email:      alex.hilbers@asml.nl
ASML                  Tel:        +31(0)402685587
P.O. Box 324          Fax:        +31(0)402685530
5500 AH  Veldhoven    Building    7K-1005
The Netherlands       Department: EDEV
to glow or not to, that is the e = mission  
------------------------------------------------------

 
From owner-ibis Wed Jun 13 07:02:09 2001
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From: Aubrey_Sparkman@Dell.com
To: alex.hilbers@asml.com, ibis-users@eda.org
Subject: RE: website www.eigroup.org protected or server down?
Date: Wed, 13 Jun 2001 08:58:06 -0500
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I got
  Error: Access is Denied.

I also tried a saved bookmark that I have used before and got the same
message, so something has changed.  Don't know what or why.

Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


> -----Original Message-----
> From: Alex Hilbers [mailto:alex.hilbers@asml.com]
> Sent: Wednesday, June 13, 2001 7:35 AM
> To: ibis-users@eda.org
> Subject: website www.eigroup.org protected or server down?
> 
> 
> Hello,
> I have tried to reach
> http://www.eigroup.org/ibis/models.htm 
> but got an error
> Regards,
> Alex
> 
> ------------------------------------------------------
> Alex Hilbers          Email:      alex.hilbers@asml.nl
> ASML                  Tel:        +31(0)402685587
> P.O. Box 324          Fax:        +31(0)402685530
> 5500 AH  Veldhoven    Building    7K-1005
> The Netherlands       Department: EDEV
> to glow or not to, that is the e = mission  
> ------------------------------------------------------
> 
> 


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From owner-ibis Wed Jun 13 08:54:03 2001
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: alex.hilbers@asml.com, ibis-users@eda.org
Subject: RE: website www.eigroup.org protected or server down?
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Hi Alex, Aubrey:

  Mmm...I just tried it (8:30 Pacific coast time) and I had no problem.
Perhaps the server was temporarily down??  Try it again and let us know if
there are more problems.


  Regards,
  Stephen Peters
  Intel Corp.


-----Original Message-----
From: Aubrey_Sparkman@Dell.com [mailto:Aubrey_Sparkman@Dell.com]
Sent: Wednesday, June 13, 2001 6:58 AM
To: alex.hilbers@asml.com; ibis-users@eda.org
Subject: RE: website www.eigroup.org protected or server down?


I got
  Error: Access is Denied.

I also tried a saved bookmark that I have used before and got the same
message, so something has changed.  Don't know what or why.

Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


> -----Original Message-----
> From: Alex Hilbers [mailto:alex.hilbers@asml.com]
> Sent: Wednesday, June 13, 2001 7:35 AM
> To: ibis-users@eda.org
> Subject: website www.eigroup.org protected or server down?
> 
> 
> Hello,
> I have tried to reach
> http://www.eigroup.org/ibis/models.htm 
> but got an error
> Regards,
> Alex
> 
> ------------------------------------------------------
> Alex Hilbers          Email:      alex.hilbers@asml.nl
> ASML                  Tel:        +31(0)402685587
> P.O. Box 324          Fax:        +31(0)402685530
> 5500 AH  Veldhoven    Building    7K-1005
> The Netherlands       Department: EDEV
> to glow or not to, that is the e = mission  
> ------------------------------------------------------
> 
> 


 
From owner-ibis Wed Jun 13 09:27:10 2001
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Date: Wed, 13 Jun 2001 09:26:13 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: Re: website www.eigroup.org protected or server down?
To: ibis-users@eda.org, alex.hilbers@asml.com
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Alex,

Can you try the link again. I just tested it and it works.

The website does not require any login..

Syed

> Date: Wed, 13 Jun 2001 14:34:44 +0200 (MET DST)
> From: Alex Hilbers <alex.hilbers@asml.com>
> Subject: website www.eigroup.org protected or server down?
> To: ibis-users@eda.org
> MIME-Version: 1.0
> Content-MD5: uumLcLvh+OTH+JszrWOFaQ==
> 
> Hello,
> I have tried to reach
> http://www.eigroup.org/ibis/models.htm 
> but got an error
> Regards,
> Alex
> 
> ------------------------------------------------------
> Alex Hilbers          Email:      alex.hilbers@asml.nl
> ASML                  Tel:        +31(0)402685587
> P.O. Box 324          Fax:        +31(0)402685530
> 5500 AH  Veldhoven    Building    7K-1005
> The Netherlands       Department: EDEV
> to glow or not to, that is the e = mission  
> ------------------------------------------------------
> 

 
From owner-ibis Wed Jun 13 09:48:03 2001
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From: Aubrey_Sparkman@Dell.com
To: stephen.peters@intel.com, alex.hilbers@asml.com, ibis-users@eda.org
Subject: RE: website www.eigroup.org protected or server down?
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Must have been temporary.  Works now.

Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


> -----Original Message-----
> From: Peters, Stephen [mailto:stephen.peters@intel.com]
> Sent: Wednesday, June 13, 2001 10:33 AM
> To: alex.hilbers@asml.com; ibis-users@eda.org
> Subject: RE: website www.eigroup.org protected or server down?
> 
> 
> 
> Hi Alex, Aubrey:
> 
>   Mmm...I just tried it (8:30 Pacific coast time) and I had 
> no problem.
> Perhaps the server was temporarily down??  Try it again and 
> let us know if
> there are more problems.
> 
> 
>   Regards,
>   Stephen Peters
>   Intel Corp.
> 
> 
> -----Original Message-----
> From: Aubrey_Sparkman@Dell.com [mailto:Aubrey_Sparkman@Dell.com]
> Sent: Wednesday, June 13, 2001 6:58 AM
> To: alex.hilbers@asml.com; ibis-users@eda.org
> Subject: RE: website www.eigroup.org protected or server down?
> 
> 
> I got
>   Error: Access is Denied.
> 
> I also tried a saved bookmark that I have used before and got the same
> message, so something has changed.  Don't know what or why.
> 
> Aubrey Sparkman
> Signal Integrity
> Aubrey_Sparkman@Dell.com
> (512) 723-3592
> 
> 
> > -----Original Message-----
> > From: Alex Hilbers [mailto:alex.hilbers@asml.com]
> > Sent: Wednesday, June 13, 2001 7:35 AM
> > To: ibis-users@eda.org
> > Subject: website www.eigroup.org protected or server down?
> > 
> > 
> > Hello,
> > I have tried to reach
> > http://www.eigroup.org/ibis/models.htm 
> > but got an error
> > Regards,
> > Alex
> > 
> > ------------------------------------------------------
> > Alex Hilbers          Email:      alex.hilbers@asml.nl
> > ASML                  Tel:        +31(0)402685587
> > P.O. Box 324          Fax:        +31(0)402685530
> > 5500 AH  Veldhoven    Building    7K-1005
> > The Netherlands       Department: EDEV
> > to glow or not to, that is the e = mission  
> > ------------------------------------------------------
> > 
> > 
> 
> 
> 


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From owner-ibis Wed Jun 13 09:27:44 2001
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To: ibis-users@eda.org
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No problem for me!

Must have been a temporary problem.

Andy


> ----------
> I got
>   Error: Access is Denied.
> 
> I also tried a saved bookmark that I have used before and got the same
> message, so something has changed.  Don't know what or why.
> 
> Aubrey Sparkman
> Signal Integrity
> Aubrey_Sparkman@Dell.com
> (512) 723-3592
> 
> 
> > -----Original Message-----
> > From: Alex Hilbers [mailto:alex.hilbers@asml.com]
> > Sent: Wednesday, June 13, 2001 7:35 AM
> > To: ibis-users@eda.org
> > Subject: website www.eigroup.org protected or server down?
> > 
> > 
> > Hello,
> > I have tried to reach
> > http://www.eigroup.org/ibis/models.htm 
> > but got an error
> > Regards,
> > Alex
> > 
> > ------------------------------------------------------
> > Alex Hilbers          Email:      alex.hilbers@asml.nl
> > ASML                  Tel:        +31(0)402685587
> > P.O. Box 324          Fax:        +31(0)402685530
> > 5500 AH  Veldhoven    Building    7K-1005
> > The Netherlands       Department: EDEV
> > to glow or not to, that is the e = mission  
> > ------------------------------------------------------
> > 
> > 
> 
> 
 
From owner-ibis Wed Jun 13 10:22:57 2001
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Message-ID: <001f01c0f42d$94c94d20$e11dfea9@sb1>
From: "Bill Clifford" <bvc3@prodigy.net>
To: "Syed Huq" <shuq@cisco.com>, <ibis-users@eda.org>
References: <200106082153.AAS49148@mira-sjcd-4.cisco.com>
Subject: Re: Differential output buffers
Date: Wed, 13 Jun 2001 10:23:35 -0700
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Syed,

Thanks for the quick response.  Are there other tools out there that support
IBIS v3.2 which would be better for the differential?  Also, I misstated my
initial question.  I'm really interested in differential devices in general,
drivers and receivers.  I was able to at least get some results for a driver
using s2ibis2, although not very good ones.  But for the receiver I don't
see how it can work, because s2ibis2 only gives one input pulse.

Thanks again for any help you can give me on this.  I hope these questions
aren't too trivial, while I'm familiar with using IBIS models, I'm new to
actually trying to make my own.  I really appreciate the assistance.

Regards,
Bill Clifford

----- Original Message -----
From: "Syed Huq" <shuq@cisco.com>
To: <ibis-users@eda.org>; <bvc3@prodigy.net>
Sent: Friday, June 08, 2001 2:53 PM
Subject: Re: Differential output buffers


> Bill,
>
> If you can run a SPICE simulation for a Diff output, you can use s2ibis2
to do
> the translation. Even if s2ibis2 does not support a specific keyword to
achieve
> this, you can put all the necessary SPICE syntax in the .sp file or even
in
> the .spi file generated by s2ibis2 to handle it.
>
> It just takes a little bit more of an effort.
>
> BTW, s2ibis2 was written to support IBISv2.1 which has poor support for
any
> type of Diff Outputs.
>
> Syed
> Cisco Systems, Inc
>
> > From: "Bill Clifford" <bvc3@prodigy.net>
> > To: <ibis-users@eda.org>
> > Subject: Differential output buffers
> > Date: Fri, 11 May 2001 13:40:21 -0700
> > MIME-Version: 1.0
> > X-Priority: 3
> > X-MSMail-Priority: Normal
> > X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6600
> >
> > Hello.  I'm trying to convert a SPICE model of a differential output
buffer to
> an IBIS model.  I've been using s2ibis2 for other models, but this doesn't
work
> for the differential.  What other tools are available that would be able
to do
> this?  Or do I just have to process the SPICE data myself into the IBIS
format?
> Any information is greatly appreciated.  Thanks in advance.
> >
> > Bill Clifford
>
>

 
From owner-ibis Wed Jun 13 15:42:23 2001
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-- 
__________________________

Mehdi Mechaik
Cisco Systems, Inc

E-mail: mechaik@cisco.com
Phone:  408-527-3354
Pager:  408-787-8684
__________________________
 
From owner-ibis Thu Jun 14 11:57:10 2001
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To All:

Below is the planned agenda for the IBIS Summit Meeting to be held
on Thursday June 21, 2000 during the Design Automation Conference in
Las Vegas, Nevada.  The meeting consists of presentations
and discussions.

The meeting is free to people interested in IBIS modeling, digital
circuit design and related EDA tool development.  Refreshments and
lunch are included.

If you plan to attend, please contact Bob Ross or Guy de Burgh
at the addresses below (if you haven't already done so):

Bob Ross
Mentor Graphics
Chair, EIA IBIS Open Forum
bob_ross@mentor.com

Guy de Burgh
Innoveda
Secretary, EIA IBIS Open Forum
gdeburgh@innoveda.com
--------------8A96D7F1443FEFBE3FF401D3
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________________________________________________________________________

                   AGENDA, IBIS SUMMIT MEETING
                          June 21, 2001
                  Las Vegas Hilton Regency Hotel
                        Las Vegas, Nevada
  
8:30 AM   REFRESHMENTS AND SIGN-IN

9:00 AM   INTRODUCTIONS

9:10 AM   IBIS STATUS
          Bob Ross, Mentor Graphics

9:30 AM   PRE-EMPHSIS BUFFER MODELING
          Hazem Hegazy, Fady Galal, and Roshdy Hegazy, Mentor Graphics

10:00 AM  SCSI, FIBER CHANNEL IBIS MODELING OVERVIEW
          Larry Barnes, LSI Logic

10:30 AM  BREAK

10:45 AM  DRIVER SCHEDULE MODELING
          Chris Reid and Bob Ross, Mentor Graphics

11:05 AM  MAKING BEHAVIORAL MODELS FOR FREQUENCY DOMAIN ANALYSIS
          Arpad Muranyi, Intel

11:35 AM  ELECTION OF OFFICERS AND OTHER BUSINESS

12:00 PM  LUNCH (Provided to Attendees)

1:00 PM   IBIS-X and IBIS MACRO LANGUAGE PROGRESS
          Stephen Peters, Intel 

          IBIS-X AND IBIS-ML
          Stephen Peters, Intel

          APPLYING THE IBIS MACRO LANGUAGE TO NEW KEYWORDS
          Al Davis, Independent

3:00 PM   BREAK

3:15 PM   EMC PARAMETERS FOR IBIS
          Guy de Burgh, Innoveda

3:45 PM   OPEN DISCUSSION AND AD HOC PRESENTATIONS
          - Next Meetings
          - Etc.

5:00 PM   MEETING ENDS
________________________________________________________________________

--------------8A96D7F1443FEFBE3FF401D3--

 
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From: "Hirut Asfaw" <hasf@us.ibm.com>
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Hi Hegzay,
     Just wondering if you had a chance to add a more detailed description
to your March presentation on how to model "LVDS* I/Os with internal
(100ohm) resistance.

Thanks,
Hirut

Hirut Asfaw
ASIC I/O Developement
IBM Microelectronics Division
External:  (802) 769-0652   T/L: 6-0652
hasf@us.ibm.com



 
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unsubscribe

 
From owner-ibis Thu Jun 14 15:12:14 2001
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Date: Thu, 14 Jun 2001 15:11:15 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: Re: Differential output buffers
To: shuq@cisco.com, ibis-users@eda.org, bvc3@prodigy.net
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Bill,

For a Diff receiver, once s2ibis2 creates a .spi for one leg of
the Rx input(PAD_N), you have to add the E element for the other leg
of the input(PAD_P)..manually..

This works fine for s2ibis2..

Syed

======================================================================
.<extracted from a input spi file generated by s2ibis2>
.
VOUTS2I PAD_N 0 DC 0
E1      PAD_P 0 POLY(2) VDD 0 PAD_N 0 0 1 -1 <--- Manually added this line
VCLMPS2I VDD1 0 DC 1.5
VGCLMPS2I VSS 0 DC 0
.TEMP 55
.OPTIONS INGOLD=2
.DC VOUTS2I -1.5 1.5 0.1
.PRINT DC I(VOUTS2I)
.END
=======================================================================

> From: "Bill Clifford" <bvc3@prodigy.net>
> To: "Syed Huq" <shuq@cisco.com>, <ibis-users@eda.org>
> 
> Syed,
> 
> <<snip snip.....>>
> .......
> But for the receiver I don't
> see how it can work, because s2ibis2 only gives one input pulse.
> 
> Thanks again for any help you can give me on this.  I hope these questions
> aren't too trivial, while I'm familiar with using IBIS models, I'm new to
> actually trying to make my own.  I really appreciate the assistance.
> 
> Regards,
> Bill Clifford
> 

 
From owner-ibis Fri Jun 15 00:12:22 2001
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Date: Fri, 15 Jun 2001 09:11:08 +0200 (MET DST)
From: Alex Hilbers <alex.hilbers@asml.com>
Reply-To: Alex Hilbers <alex.hilbers@asml.com>
Subject: RE: website www.eigroup.org protected or server down?
To: ibis-users@eda.org
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All,
it works fine again, as always,
regards,
Alex

> From: "Peters, Stephen" <stephen.peters@intel.com>
> To: alex.hilbers@asml.nl, ibis-users@eda.org
> Subject: RE: website www.eigroup.org protected or server down?
> Date: Wed, 13 Jun 2001 08:33:23 -0700
> MIME-Version: 1.0
> 
> 
> Hi Alex, Aubrey:
> 
>   Mmm...I just tried it (8:30 Pacific coast time) and I had no problem.
> Perhaps the server was temporarily down??  Try it again and let us know if
> there are more problems.
> 
> 
>   Regards,
>   Stephen Peters
>   Intel Corp.
> 
> 
> -----Original Message-----
> From: Aubrey_Sparkman@Dell.com [mailto:Aubrey_Sparkman@Dell.com]
> Sent: Wednesday, June 13, 2001 6:58 AM
> To: alex.hilbers@asml.com; ibis-users@eda.org
> Subject: RE: website www.eigroup.org protected or server down?
> 
> 
> I got
>   Error: Access is Denied.
> 
> I also tried a saved bookmark that I have used before and got the same
> message, so something has changed.  Don't know what or why.
> 
> Aubrey Sparkman
> Signal Integrity
> Aubrey_Sparkman@Dell.com
> (512) 723-3592
> 
> 
> > -----Original Message-----
> > From: Alex Hilbers [mailto:alex.hilbers@asml.com]
> > Sent: Wednesday, June 13, 2001 7:35 AM
> > To: ibis-users@eda.org
> > Subject: website www.eigroup.org protected or server down?
> > 
> > 
> > Hello,
> > I have tried to reach
> > http://www.eigroup.org/ibis/models.htm 
> > but got an error
> > Regards,
> > Alex
> > 
> > ------------------------------------------------------
> > Alex Hilbers          Email:      alex.hilbers@asml.nl
> > ASML                  Tel:        +31(0)402685587
> > P.O. Box 324          Fax:        +31(0)402685530
> > 5500 AH  Veldhoven    Building    7K-1005
> > The Netherlands       Department: EDEV
> > to glow or not to, that is the e = mission  
> > ------------------------------------------------------
> > 
> > 
> 
> 

------------------------------------------------------
Alex Hilbers          Email:      alex.hilbers@asml.nl
ASML                  Tel:        +31(0)402685587
P.O. Box 324          Fax:        +31(0)402685530
5500 AH  Veldhoven    Building    7K-1005
The Netherlands       Department: EDEV
to glow or not to, that is the e = mission  
------------------------------------------------------

 
From owner-ibis Fri Jun 15 05:21:57 2001
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Hi All,
I have been looking into this recently. For those of us that did not
attend this presentation, can you forward a copy of the slides, and
elaborate on them? Any information is helpful.

Thanks,
Peter


-- 
Peter LaFlamme

Applied Micro Circuits Corp.
Staff System Applications Engineer
200 Minuteman Rd, 3rd Floor
Andover, MA 01810

978-247-8470 phone
978-623-0055 Fax
 
Hirut Asfaw wrote:
> 
> Hi Hegzay,
>      Just wondering if you had a chance to add a more detailed description
> to your March presentation on how to model "LVDS* I/Os with internal
> (100ohm) resistance.
> 
> Thanks,
> Hirut
> 
> Hirut Asfaw
> ASIC I/O Developement
> IBM Microelectronics Division
> External:  (802) 769-0652   T/L: 6-0652
> hasf@us.ibm.com
 
From owner-ibis Fri Jun 15 11:02:02 2001
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Subject: 
To: ibis-users@eda.org
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Hi Folks,
     A question regarding *LVDS* I/Os with internal terminations between
the diff pins.
          When characterizing the Series resistance between the diff pins,
is the intention to capture the current prior to IBIS generation.  Meaning,
is this part of Spice set up before the IBIS model is generated? or can we
just include this resistance (as a physical) model once the IBIS model is
genrated?


Thanks,
Hirut



Hirut Asfaw
ASIC I/O Developement
IBM Microelectronics Division
External:  (802) 769-0652   T/L: 6-0652
hasf@us.ibm.com



 
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Hi Hirut,
I had this discussion with Bob Ross a few weeks ago. This is the
information that he gave me. 

Use IBIS Version 3.2 and the [R Series] keyword to model internal
differential
resistor terminations for differential I/O models.  That means that you
will
also need the [Series Pin Mapping] keyword to show the connection of [R
Series].

Here is the example that I created using Bob's advice, starting with the
[pin] Keyword and modeling the series resistor between pins 1 and 2:

[Pin]        signal_name     model_name         R_pin   L_pin   C_pin
  1             PAD          lvds_drv            NA      NA      NA
  2             PADN         lvds_drv          NA      NA      NA
| 
[Series Pin Mapping]    pin_2   model_name      function_table_group
1                     2           rterm_100


| 
[Diff_pin]      inv_pin     vdiff     tdelay_typ    tdelay_min   
tdelay_max
| 
   1               2          NA          0             0             0

[Model]  rterm_100
C_comp                   0.1pF   0.1pF  0.1pF

Model_type  Series
|variable        R(typ)  R(min)  R(max)
[R Series]      100     80      120

[Temperature Range]     50.00    125.00    0.00
[Voltage Range]         1.800    1.650   1.950

I have tried it out and the syntax is correct, but you will need to use
a simulator that can understand it. I think that there is a way to do it
with a dynamic clamp, but I think that there may be potential problems
with that. I say this because the voltage at the true and complement
pins are dependent on each other. With the dynamic clamp implementation
I do not believe that this is  true.

Regards,
Peter




Hirut Asfaw wrote:
> 
> Hi Folks,
>      A question regarding *LVDS* I/Os with internal terminations between
> the diff pins.
>           When characterizing the Series resistance between the diff pins,
> is the intention to capture the current prior to IBIS generation.  Meaning,
> is this part of Spice set up before the IBIS model is generated? or can we
> just include this resistance (as a physical) model once the IBIS model is
> genrated?
> 
> Thanks,
> Hirut
> 
> Hirut Asfaw
> ASIC I/O Developement
> IBM Microelectronics Division
> External:  (802) 769-0652   T/L: 6-0652
> hasf@us.ibm.com

-- 
Peter LaFlamme

Applied Micro Circuits Corp.
Staff System Applications Engineer
200 Minuteman Rd, 3rd Floor
Andover, MA 01810

978-247-8470 phone
978-623-0055 Fax
 
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From: "Hegazy, Hazem" <hazem_hegazy@mentorg.com>
To: "'Hirut Asfaw '" <hasf@us.ibm.com>,
   "'ibis-users@eda.org '"
	 <ibis-users@eda.org>
Subject: LVDS
Date: Sat, 16 Jun 2001 01:38:09 +0300
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 Hi,
I'll write a detailed paper on that then send it to the IBIS users group.
But, it'snot in my short term plan.

BR,

-----Original Message-----
From: Hirut Asfaw
To: ibis-users@eda.org
Sent: 6/14/01 10:25 PM

Hi Hegzay,
     Just wondering if you had a chance to add a more detailed
description
to your March presentation on how to model "LVDS* I/Os with internal
(100ohm) resistance.

Thanks,
Hirut

Hirut Asfaw
ASIC I/O Developement
IBM Microelectronics Division
External:  (802) 769-0652   T/L: 6-0652
hasf@us.ibm.com



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<P><FONT SIZE=2>&nbsp;Hi,</FONT>
<BR><FONT SIZE=2>I'll write a detailed paper on that then send it to the IBIS users group.</FONT>
<BR><FONT SIZE=2>But, it'snot in my short term plan.</FONT>
</P>

<P><FONT SIZE=2>BR,</FONT>
</P>

<P><FONT SIZE=2>-----Original Message-----</FONT>
<BR><FONT SIZE=2>From: Hirut Asfaw</FONT>
<BR><FONT SIZE=2>To: ibis-users@eda.org</FONT>
<BR><FONT SIZE=2>Sent: 6/14/01 10:25 PM</FONT>
</P>

<P><FONT SIZE=2>Hi Hegzay,</FONT>
<BR><FONT SIZE=2>&nbsp;&nbsp;&nbsp;&nbsp; Just wondering if you had a chance to add a more detailed</FONT>
<BR><FONT SIZE=2>description</FONT>
<BR><FONT SIZE=2>to your March presentation on how to model &quot;LVDS* I/Os with internal</FONT>
<BR><FONT SIZE=2>(100ohm) resistance.</FONT>
</P>

<P><FONT SIZE=2>Thanks,</FONT>
<BR><FONT SIZE=2>Hirut</FONT>
</P>

<P><FONT SIZE=2>Hirut Asfaw</FONT>
<BR><FONT SIZE=2>ASIC I/O Developement</FONT>
<BR><FONT SIZE=2>IBM Microelectronics Division</FONT>
<BR><FONT SIZE=2>External:&nbsp; (802) 769-0652&nbsp;&nbsp; T/L: 6-0652</FONT>
<BR><FONT SIZE=2>hasf@us.ibm.com</FONT>
</P>
<BR>

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From owner-ibis Fri Jun 15 16:12:01 2001
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From: "Hegazy, Hazem" <hazem_hegazy@mentorg.com>
To: "'Hirut Asfaw '" <hasf@us.ibm.com>,
   "'ibis-users@eda.org '"
	 <ibis-users@eda.org>
Date: Sat, 16 Jun 2001 02:10:36 +0300
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 Hi,

We have two approaches to model LVDS:

- The first one:
         - The normal wave form will be included in this approach.(Generated
by Rload to Vref on both +ve and -ve PINs)
         - Operating point analysis with variable Rload to the same Vref
will generate the pull up/down.


This approach is a Global one; you can use it for any differential buffer
with whatever differential load (linear or non-linear). Because you extract
the V-I data in actual buffer operation.

By using this approach you got an IBIS model with the differential resistor
behavior embedded inside the model.

The second one:
       - You begin by extracting the differential load value (or if it is
stated in the data sheets)
       - If it is a linear resistance so you can go on in this approach, if
not you go back to the first one.
       - Extract the waveform and the DC curves by the setup stated in the
presentation.

We have now differential load decomposed IBIS model for that buffer. So you
should add the differential resistor to you model by series resistor element
to get the original behavior.

I hope that helps,
BR,

-----Original Message-----
From: Hirut Asfaw
To: ibis-users@eda.org
Sent: 6/15/01 7:01 PM

Hi Folks,
     A question regarding *LVDS* I/Os with internal terminations between
the diff pins.
          When characterizing the Series resistance between the diff
pins,
is the intention to capture the current prior to IBIS generation.
Meaning,
is this part of Spice set up before the IBIS model is generated? or can
we
just include this resistance (as a physical) model once the IBIS model
is
genrated?


Thanks,
Hirut



Hirut Asfaw
ASIC I/O Developement
IBM Microelectronics Division
External:  (802) 769-0652   T/L: 6-0652
hasf@us.ibm.com



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<P><FONT SIZE=3D2>&nbsp;Hi,</FONT>
</P>

<P><FONT SIZE=3D2>We have two approaches to model LVDS:</FONT>
</P>

<P><FONT SIZE=3D2>- The first one:</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - =
The normal wave form will be included in this approach.(Generated by =
Rload to Vref on both +ve and -ve PINs)</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - =
Operating point analysis with variable Rload to the same Vref will =
generate the pull up/down.</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>This approach is a Global one; you can use it for any =
differential buffer with whatever differential load (linear or =
non-linear). Because you extract the V-I data in actual buffer =
operation.</FONT></P>

<P><FONT SIZE=3D2>By using this approach you got an IBIS model with the =
differential resistor behavior embedded inside the model.</FONT>
</P>

<P><FONT SIZE=3D2>The second one:</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - You begin by =
extracting the differential load value (or if it is stated in the data =
sheets)</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - If it is a =
linear resistance so you can go on in this approach, if not you go back =
to the first one.</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - Extract the =
waveform and the DC curves by the setup stated in the =
presentation.</FONT>
</P>

<P><FONT SIZE=3D2>We have now differential load decomposed IBIS model =
for that buffer. So you should add the differential resistor to you =
model by series resistor element to get the original =
behavior.</FONT></P>

<P><FONT SIZE=3D2>I hope that helps,</FONT>
<BR><FONT SIZE=3D2>BR,</FONT>
</P>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Hirut Asfaw</FONT>
<BR><FONT SIZE=3D2>To: ibis-users@eda.org</FONT>
<BR><FONT SIZE=3D2>Sent: 6/15/01 7:01 PM</FONT>
</P>

<P><FONT SIZE=3D2>Hi Folks,</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp; A question regarding *LVDS* =
I/Os with internal terminations between</FONT>
<BR><FONT SIZE=3D2>the diff pins.</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; When =
characterizing the Series resistance between the diff</FONT>
<BR><FONT SIZE=3D2>pins,</FONT>
<BR><FONT SIZE=3D2>is the intention to capture the current prior to =
IBIS generation.</FONT>
<BR><FONT SIZE=3D2>Meaning,</FONT>
<BR><FONT SIZE=3D2>is this part of Spice set up before the IBIS model =
is generated? or can</FONT>
<BR><FONT SIZE=3D2>we</FONT>
<BR><FONT SIZE=3D2>just include this resistance (as a physical) model =
once the IBIS model</FONT>
<BR><FONT SIZE=3D2>is</FONT>
<BR><FONT SIZE=3D2>genrated?</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Thanks,</FONT>
<BR><FONT SIZE=3D2>Hirut</FONT>
</P>
<BR>
<BR>

<P><FONT SIZE=3D2>Hirut Asfaw</FONT>
<BR><FONT SIZE=3D2>ASIC I/O Developement</FONT>
<BR><FONT SIZE=3D2>IBM Microelectronics Division</FONT>
<BR><FONT SIZE=3D2>External:&nbsp; (802) 769-0652&nbsp;&nbsp; T/L: =
6-0652</FONT>
<BR><FONT SIZE=3D2>hasf@us.ibm.com</FONT>
</P>
<BR>

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</HTML>
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Date: Fri, 15 Jun 2001 17:31:17 -0600
To: ibis-users@eda.org
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Subject: Differential inputs
Cc: eharp@vitesse.com
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Could you please supply a couple of pointers on a method to model a 
differential input buffer containing both self biasing and differential 
termination.  In an application the inputs to the buffer are AC 
coupled.   The buffer will then swing about its bias value.  In 
addition,  the +/- signals are internally terminated with approximately 100 
ohms.

The bias point could vary with temp and voltage so I would prefer to derive 
the values from the spice model.   The 100 ohms is also a rough number and 
I would somehow prefer to capture the characteristics from the spice models.

Thanks
Charlie
719-867-6373

 
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Date: Tue, 19 Jun 2001 01:44:15 -0700 (PDT)
From: suresh np <suresh_np1@yahoo.com>
Subject: How can I do IBIS modeling
To: ibis-users@eda.org
MIME-Version: 1.0
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Hi
I am interested in doing IBIS modelling. But, i know
only IBIS File format.These are my basic doubts,
1> How can i start with IBIS modelling?(I know
PSpice).
2> Can i develope a IBIS model from the device data
sheet only? or do i require  IO buffer specification
sheet?
3> how far the tool SPECCTRAQuest is helpful in IBIS
modelling?
Pls help me out in this regard. Thanks in advance.
..Suresh

__________________________________________________
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Date: Tue, 19 Jun 2001 10:45:05 -0400
From: "Perry Qu" <perry.qu@alcatel.com>
Organization: Alcatel CID
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Subject: using IBIS in HSPICE 
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Hi!

I tried to do some simulation in HSPICE with a differential driver in
IBIS format. The driver is a HSTL output and by connecting the driver
just to a simple 50 ohm load, I observed unrealistic sharp falling edge.
When I check the HSPICE log file, I have the following message:

 ** warning** iob_eles2:102:
    Inconsistency between Ramp and PD/PU data is detected.
    dV_f=  3.2680E-01   V_fwf_max=  3.3000E+00   V_fwf_min=  3.3000E+00
    transition from 80% to 20% is not satisfied

 ** warning** iob_eles2:186:
    099  instances of out-of-range states at falling ramp
    this can detriment accuracy

Any idea how I can correct the problem?

Thanks in advance.

Perry Qu

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Subject: Re: using IBIS in HSPICE
To: "Perry Qu" <perry.qu@alcatel.com>
Cc: IBIS group <ibis-users@eda.org>
From: Adam.Tambone@fairchildsemi.com
Date: Tue, 19 Jun 2001 11:14:08 -0400
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Perry,

There are two options in HSPICE that allow you to use V-t data of the
rising and falling waveforms of the IBIS model instead of the Ramp data in
the IBIS model.  If you do not specify these options then by default HSPICE
will use the Ramp data.

They are...

ramp_fwf =  0 or 1 or 2
ramp_rwf =  0 or 1 or 2

If you specify 0 then ramp data will be used.
If you specify 1 then 1 waveform will be used.
If you specify 2 then 2 waveforms will be used.

See Chapter 19 of the most recent Star-HSPICE Manual (2000.4) for a full
explanation.

Adam Tambone






"Perry Qu" <perry.qu@alcatel.com> on 06/19/2001 10:45:05 AM

To:   IBIS group <ibis-users@eda.org>
cc:

Subject:  using IBIS in HSPICE


Hi!

I tried to do some simulation in HSPICE with a differential driver in
IBIS format. The driver is a HSTL output and by connecting the driver
just to a simple 50 ohm load, I observed unrealistic sharp falling edge.
When I check the HSPICE log file, I have the following message:

 ** warning** iob_eles2:102:
    Inconsistency between Ramp and PD/PU data is detected.
    dV_f=  3.2680E-01   V_fwf_max=  3.3000E+00   V_fwf_min=  3.3000E+00
    transition from 80% to 20% is not satisfied

 ** warning** iob_eles2:186:
    099  instances of out-of-range states at falling ramp
    this can detriment accuracy

Any idea how I can correct the problem?

Thanks in advance.

Perry Qu

(See attached file: perry.qu.vcf)



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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'suresh np'" <suresh_np1@yahoo.com>, ibis-users@eda.org
Subject: RE: How can I do IBIS modeling
Date: Tue, 19 Jun 2001 08:46:17 -0700
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Hi Suresh:


   To answer your question -- you *might* be able to develop an IBIS 1.1
model from a component data sheet, but most likely the resulting model would
not be very useful.  The best way to create a model is start with a
transistor level circuit and then do simulations into the proper test loads
to extract I-V and V-T curves for the output (among other information).
Alternatly, if you have a physical device, you can measure the revelent
parameters and create a model from measurment data.

   For more detailed information I encourage you to visit the IBIS website
and download a copy of the IBIS modeling cookbook.  It can be found at:

  http://www.eigroup.org/ibis/tools.htm

  Regards,
  Stephen Peters
  Intel Corp.


   

----Original Message-----
From: suresh np [mailto:suresh_np1@yahoo.com]
Sent: Tuesday, June 19, 2001 1:44 AM
To: ibis-users@eda.org
Subject: How can I do IBIS modeling


Hi
I am interested in doing IBIS modelling. But, i know
only IBIS File format.These are my basic doubts,
1> How can i start with IBIS modelling?(I know
PSpice).
2> Can i develope a IBIS model from the device data
sheet only? or do i require  IO buffer specification
sheet?
3> how far the tool SPECCTRAQuest is helpful in IBIS
modelling?
Pls help me out in this regard. Thanks in advance.
..Suresh

__________________________________________________
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From owner-ibis Tue Jun 19 10:18:54 2001
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Unsubscribe me.

thanks,

-- 
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From owner-ibis Tue Jun 19 10:27:47 2001
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Date: Tue, 19 Jun 2001 13:26:03 -0400
From: "Perry Qu" <perry.qu@alcatel.com>
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To: Adam.Tambone@fairchildsemi.com
CC: IBIS group <ibis-users@eda.org>
Subject: Re: using IBIS in HSPICE
References: <OF905FF963.CB9A549F-ON85256A70.005320F3@fairchildsemi.com>
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Hi! Adam:

Thanks a lot for your help. I did use ramp_fwf option in the beginning when I
use IBIS in HSPICE but I forgot to put that in this time as it's been a while
when I read the manual last time.

However, the waveform looks even stranger after I plug in the waveform option.
I have to look into that in more detail.

Regards

Perry

Adam.Tambone@fairchildsemi.com wrote:

> Perry,
>
> There are two options in HSPICE that allow you to use V-t data of the
> rising and falling waveforms of the IBIS model instead of the Ramp data in
> the IBIS model.  If you do not specify these options then by default HSPICE
> will use the Ramp data.
>
> They are...
>
> ramp_fwf =  0 or 1 or 2
> ramp_rwf =  0 or 1 or 2
>
> If you specify 0 then ramp data will be used.
> If you specify 1 then 1 waveform will be used.
> If you specify 2 then 2 waveforms will be used.
>
> See Chapter 19 of the most recent Star-HSPICE Manual (2000.4) for a full
> explanation.
>
> Adam Tambone
>
> "Perry Qu" <perry.qu@alcatel.com> on 06/19/2001 10:45:05 AM
>
> To:   IBIS group <ibis-users@eda.org>
> cc:
>
> Subject:  using IBIS in HSPICE
>
> Hi!
>
> I tried to do some simulation in HSPICE with a differential driver in
> IBIS format. The driver is a HSTL output and by connecting the driver
> just to a simple 50 ohm load, I observed unrealistic sharp falling edge.
> When I check the HSPICE log file, I have the following message:
>
>  ** warning** iob_eles2:102:
>     Inconsistency between Ramp and PD/PU data is detected.
>     dV_f=  3.2680E-01   V_fwf_max=  3.3000E+00   V_fwf_min=  3.3000E+00
>     transition from 80% to 20% is not satisfied
>
>  ** warning** iob_eles2:186:
>     099  instances of out-of-range states at falling ramp
>     this can detriment accuracy
>
> Any idea how I can correct the problem?
>
> Thanks in advance.
>
> Perry Qu
>
> (See attached file: perry.qu.vcf)

 
From owner-ibis Tue Jun 19 12:32:54 2001
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From: "Wang, Brian" <brian.wang@intel.com>
To: "'Adam.Tambone@fairchildsemi.com'" <Adam.Tambone@fairchildsemi.com>,
   Perry Qu <perry.qu@alcatel.com>
Cc: IBIS group <ibis-users@eda.org>
Subject: RE: using IBIS in HSPICE
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Perry,

Several possible reasons:

1. One is as Adam said.
2. How about your pulse width vs time span in V-t curve?
   If V-t curve time span is longer than pulse width, you may cut
   V-t curve time span as slightly shorter than pulse width.
3. Is 50 Ohms the load for V-t curve?

Best regards.

Brian 

-----Original Message-----
From: Adam.Tambone@fairchildsemi.com
[mailto:Adam.Tambone@fairchildsemi.com]
Sent: Tuesday, June 19, 2001 8:14 AM
To: Perry Qu
Cc: IBIS group
Subject: Re: using IBIS in HSPICE



Perry,

There are two options in HSPICE that allow you to use V-t data of the
rising and falling waveforms of the IBIS model instead of the Ramp data in
the IBIS model.  If you do not specify these options then by default HSPICE
will use the Ramp data.

They are...

ramp_fwf =  0 or 1 or 2
ramp_rwf =  0 or 1 or 2

If you specify 0 then ramp data will be used.
If you specify 1 then 1 waveform will be used.
If you specify 2 then 2 waveforms will be used.

See Chapter 19 of the most recent Star-HSPICE Manual (2000.4) for a full
explanation.

Adam Tambone






"Perry Qu" <perry.qu@alcatel.com> on 06/19/2001 10:45:05 AM

To:   IBIS group <ibis-users@eda.org>
cc:

Subject:  using IBIS in HSPICE


Hi!

I tried to do some simulation in HSPICE with a differential driver in
IBIS format. The driver is a HSTL output and by connecting the driver
just to a simple 50 ohm load, I observed unrealistic sharp falling edge.
When I check the HSPICE log file, I have the following message:

 ** warning** iob_eles2:102:
    Inconsistency between Ramp and PD/PU data is detected.
    dV_f=  3.2680E-01   V_fwf_max=  3.3000E+00   V_fwf_min=  3.3000E+00
    transition from 80% to 20% is not satisfied

 ** warning** iob_eles2:186:
    099  instances of out-of-range states at falling ramp
    this can detriment accuracy

Any idea how I can correct the problem?

Thanks in advance.

Perry Qu

(See attached file: perry.qu.vcf)



 
From owner-ibis Tue Jun 19 13:06:58 2001
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Hello,

Lately, some requests to subscribe or unsubscribe from IBIS reflectors have
been posted to ibis-users@eda.org.  For such requests, please use this
dedicated address instead:

ibis-request@eda.org

This prevents unnecessary administrative traffic on the reflectors.

Thanks,
John Angulo
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From owner-ibis Tue Jun 19 14:00:22 2001
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Unsubscribe me.

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From owner-ibis Tue Jun 19 17:07:05 2001
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'ibis@eda.org'" <ibis@eda.org>,
   "'ibis-users@eda.org'"
	 <ibis-users@eda.org>
Subject: IBIS-X spec rev 0.6 now available
Date: Tue, 19 Jun 2001 17:05:52 -0700
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Greetings:

  An updated copy of the IBIS-X specification is now available on the IBIS
web site.

   http://www.eda.org/pub/ibis/futures/

  This revision (rev 0.6a) has been updated (from rev 5.0) as follows:

  -- Added description of "class name" selector ([Model Selector] keyword)
and updated 
      keyword tree
  -- Moved revision history to just after the TOC and renumbered sections
  -- Corrected argument and description of [End] keyword.
  -- Editorial/typo corrections, including replacing occurrences of "CAE"
with "EDA"

  The IBIS-X document will be discussed and reviewed at Thursday's IBIS Open
Forum meeting at DAC in Las Vegas.  Note that if you are planning on
attending the summit, only a limited number of copies will be available at
the meeting, so download a copy to take with you.

  In addition to the IBIS-X specification, the working draft version of the
IBIS-ML Language Reference Manual (LRM) is available for download.  Note
that only sections 7 and 8 of the LRM have been reviewed by the IBIS futures
working group, and the document has a number of editorial and format issues.
In other words, this document is very much a work in progress, and is being
made available only to aid the IBIS-X discussion.  A much more complete
version of the LRM will be available after the summit.

  I'd also like to take this opportunity to extend a public thank you to the
members of the IBIS futures group for their hard work in making the IBIS-X
spec a reality.  Great job, folks! 


  Best Regards,
  Stephen Peters
  Intel Corp.
  Chair, IBIS Futures Working Group


 
From owner-ibis Tue Jun 26 13:19:02 2001
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Date: Tue, 26 Jun 2001 15:17:45 -0500
From: Ningyu Zhou <nyz@cypress.com>
Organization: Cypress Semiconductor
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To: ibis-users@eda.org
Subject: question about s2ibis2 utility usage.
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi, there!

I am recently learning the s2ibis2 utility. After I installed the
s2ibis2,
 and run the examples it provides, it always pop up the warning message
 under *.out file as

 "warning unknow hspice version for models"
 "warning: could not figure out the recommended Hspice version from the
 models"
 "warning: for input file pdtout.spi"
 "warning: the models and Hpsice version should both be pre-9503"
 "To run hspice anyway, set the environment variable HSPICEIGNOREMODEL
TO
 1"

 And it seems it doesn't actually run a hspice simulation, the *.ibs
file
 it finally generate contains all zeros for the I/O model.

 I am on a Sun workstation, running solaris operating system. And my
 spice simulator is Hspice.

 Can you tell me what is wrong with it and what kind of modifications I
 need to do or try in order to properly run this s2ibis2.solaris?

 Thanks a lot! Your reply will be much appreciated.

 Sincerely,

 Ningyu Zhou


 
From owner-ibis Tue Jun 26 15:27:14 2001
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Date: Tue, 26 Jun 2001 15:26:04 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: Re: question about s2ibis2 utility usage.
To: ibis-users@eda.org, nyz@cypress.com
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Hi Ningyu,

Which examples are you running. There are some set for Spectre and some for 
HSPICE.

Make sure that in the .s2i file, the following is correct:

[Spice type]            hspice

Even for a Solaris OS, you could run s2ibis2.sun4.fix version assuming that did
download the s2ibis2_fix binary as well.

Regards,
Syed


> Date: Tue, 26 Jun 2001 15:17:45 -0500
> From: Ningyu Zhou <nyz@cypress.com>
> X-Accept-Language: en
> MIME-Version: 1.0
> To: ibis-users@eda.org
> Subject: question about s2ibis2 utility usage.
> Content-Transfer-Encoding: 7bit
> 
> Hi, there!
> 
> I am recently learning the s2ibis2 utility. After I installed the
> s2ibis2,
>  and run the examples it provides, it always pop up the warning message
>  under *.out file as
> 
>  "warning unknow hspice version for models"
>  "warning: could not figure out the recommended Hspice version from the
>  models"
>  "warning: for input file pdtout.spi"
>  "warning: the models and Hpsice version should both be pre-9503"
>  "To run hspice anyway, set the environment variable HSPICEIGNOREMODEL
> TO
>  1"
> 
>  And it seems it doesn't actually run a hspice simulation, the *.ibs
> file
>  it finally generate contains all zeros for the I/O model.
> 
>  I am on a Sun workstation, running solaris operating system. And my
>  spice simulator is Hspice.
> 
>  Can you tell me what is wrong with it and what kind of modifications I
>  need to do or try in order to properly run this s2ibis2.solaris?
> 
>  Thanks a lot! Your reply will be much appreciated.
> 
>  Sincerely,
> 
>  Ningyu Zhou
> 
> 

 
From owner-ibis Tue Jun 26 20:34:49 2001
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Date: Tue, 26 Jun 2001 23:33:32 EDT
Subject: WOW
To: ibis-users@eda.org
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   Hey.
    Im still not workign this economic recession thing sucks. No bodies 
willing to pay me three hundred grand this month.
    Nice to take time off and wait for things to get back though. You guys 
working hard?  Lotta work out here it seams.
   Did you ever get a manicure? Theyre great, twenty minutes of thoughtful 
personalized care and deep tissue massage, $10 bucks.

  What a way to live it up.
   try it I really recommend it.


   Dont work too hard, things will get better.
    Goof Off in CA.