From owner-ibis  Thu Aug 22 13:51:37 1996
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Date: Thu, 22 Aug 96 13:40:09 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9608222040.AA27880@rockie.nsc.com>
To: ibis-users@vhdl.org
Subject: s2ibis2 and HSPICE

Hi,

I would like to talk to someone who has used the s2ibis2
translator on HSPICE. Can you pls drop me an E-mail ?

Regards,
Syed.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~         
~ Syed B. Huq 	    huq@rockie.nsc.com ~		  
~ Interface Applications Engineer      ~		  
~ National Semiconductor Corp.	       ~		  
~ Tel:(408)721-4874; Fax:(408)721-4785 ~		  	  
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

From owner-ibis  Fri Aug 23 11:10:33 1996
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Date: Fri, 23 Aug 96 11:00:03 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9608231800.AA23671@rockie.nsc.com>
To: ibis-users@vhdl.org
Subject: s2ibis2 on HSPICE

Hi,

The first thing I tried is run the s2ibis2 on the newtryme files in
the test dir. It worked.

I looked at the newtryme.s2i and newtryme.sp file. Here are some
questions:

1)Why does the newtryme.sp file have all that commented information at
the top of the netlist. I thought the newtryme.s2i defines all header
and component information and the .sp file should only have netlist info.

2)My model requires defining model type for '3-state' and 'I/O'. s2ibis2
requires you to indicate input_pin and enable_pin that drives the output
stage and these have to be defined in the pin list.

The input_pin and enable_pin are actually internal spice nodes that drive
the output stage. So, how do I create 'dummy' models to define these
internal nodes.

Regards,
Syed.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~         
~ Syed B. Huq 	    huq@rockie.nsc.com ~		  
~ Interface Applications Engineer      ~		  
~ National Semiconductor Corp.	       ~		  
~ Tel:(408)721-4874; Fax:(408)721-4785 ~		  	  
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


From owner-ibis  Mon Aug 26 14:13:20 1996
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Date: Mon, 26 Aug 96 14:02:55 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9608262102.AA25331@rockie.nsc.com>
To: ibis-users@vhdl.org, awglaser@eos.ncsu.edu
Subject: error msg from s2ibis2

Hi,

Can anyone comment on what these error message mean when I run
s2ibis2 ? I am showing the .msg, .st0, .su0 and the [Pin]
defination of my .s2i file.


THis is the .msg file the run keeps mentioning to see for error
messages. It hardly says anything ...
--------------------------------------------------------------------
>error          ***** hspice job aborted
       32.3 real        21.3 user         4.1 sys  
--------------------------------------------------------------------


This is the .st0 file. All I see is "***difficulty in reading input":
---------------------------------------------------------------------
*****  H S P I C E  --    95.3 (950711)   13:29:44  96/08/26    sun4
 Input File: pct1.spi
 lic: USER: huq HOSTNAME: kural HOSTID: 5721e015
 lic: contacting server: apollo
 lic: Server permit path: /usr/local/hspice/96/permit.hsp
 lic: Site: nat_ppg_sclara Created: 960328 Order#: 62311
 lic: token number 328 allocated_SJF
 Init: hspice initialization file: /usr/local/hspice/95/hspice.ini
 init: begin read circuit files,  cpu clock=  7.78E+00
       option icsweep  =        1
       option parhier  = global
       option ingold   =        2
       option artist   =        2
       option psf      =        2
       option probe    =        0
       option ingold   =        2
 init: end read circuit files,  cpu clock=  2.51E+01 memory=   1908 kb
 init: begin check errors,  cpu clock=  2.51E+01
>error   ***difficulty in reading input
>error          ***** hspice job aborted
 lic: Releasing license for hspice



This is the .su0 file. Not sure what the "node value" "fatal" means:
--------------------------------------------------------------------
header
"PSFversion" "1.00" 
"simulator" "HSPICE"
"version" "95.3" 
"rundate" "13:29:44 96/08/26"  
"runtitle" "* typ power clamp curve for model lm_input                      " 
"runtype" "Summary Information"
"op point time" "      0.00"  
"op point iterations" "     0"
"total cpu time" "       24.57"    
"node value" "fatal"
"operating point" "invalid"
"ac analysis" "invalid"
"dc sweep" "invalid"
"transient analysis" "invalid"
trailer
end
--------------------------------------------------------------------


THis is how my [Pin] section looks like in .s2i file:

From owner-ibis  Mon Aug 26 14:55:06 1996
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Date: Mon, 26 Aug 96 14:44:31 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9608262144.AA26163@rockie.nsc.com>
To: ibis-users@vhdl.org, awglaser@eos.ncsu.edu
Subject: error msg from s2ibis2 - retransmission

Sorry for re-transmission. The last one somehow lost the end of
my message.
Syed.

----- Begin Included Message -----

From huq Mon Aug 26 14:02:54 1996
To: ibis-users@vhdl.org, awglaser@eos.ncsu.edu
Subject: error msg from s2ibis2
Content-Length: 2692

Hi,

Can anyone comment on what these error message mean when I run
s2ibis2 ? I am showing the .msg, .st0, .su0 and the [Pin]
defination of my .s2i file.


THis is the .msg file the run keeps mentioning to see for error
messages. It hardly says anything ...
--------------------------------------------------------------------
>error          ***** hspice job aborted
       32.3 real        21.3 user         4.1 sys  
--------------------------------------------------------------------


This is the .st0 file. All I see is "***difficulty in reading input":
---------------------------------------------------------------------
*****  H S P I C E  --    95.3 (950711)   13:29:44  96/08/26    sun4
 Input File: pct1.spi
 lic: USER: huq HOSTNAME: kural HOSTID: 5721e015
 lic: contacting server: apollo
 lic: Server permit path: /usr/local/hspice/96/permit.hsp
 lic: Site: nat_ppg_sclara Created: 960328 Order#: 62311
 lic: token number 328 allocated_SJF
 Init: hspice initialization file: /usr/local/hspice/95/hspice.ini
 init: begin read circuit files,  cpu clock=  7.78E+00
       option icsweep  =        1
       option parhier  = global
       option ingold   =        2
       option artist   =        2
       option psf      =        2
       option probe    =        0
       option ingold   =        2
 init: end read circuit files,  cpu clock=  2.51E+01 memory=   1908 kb
 init: begin check errors,  cpu clock=  2.51E+01
>error   ***difficulty in reading input
>error          ***** hspice job aborted
 lic: Releasing license for hspice



This is the .su0 file. Not sure what the "node value" "fatal" means:
--------------------------------------------------------------------
header
"PSFversion" "1.00" 
"simulator" "HSPICE"
"version" "95.3" 
"rundate" "13:29:44 96/08/26"  
"runtitle" "* typ power clamp curve for model lm_input                      " 
"runtype" "Summary Information"
"op point time" "      0.00"  
"op point iterations" "     0"
"total cpu time" "       24.57"    
"node value" "fatal"
"operating point" "invalid"
"ac analysis" "invalid"
"dc sweep" "invalid"
"transient analysis" "invalid"
trailer
end
--------------------------------------------------------------------


THis is how my [Pin] section looks like in .s2i file:

From owner-ibis  Tue Aug 27 08:39:24 1996
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Date: Tue, 27 Aug 96 08:28:42 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9608271528.AA17878@rockie.nsc.com>
To: ibis-users@vhdl.org, awglaser@eos.ncsu.edu
Subject: error msg from s2ibis2 - PartII

Hi,

The last portion of my mail related to the errors I am getting
on using s2ibis2(HSPICE).

Let me know if anyone of you have encountered this before.




THis is how my [Pin] section looks like in .s2i file:

From owner-ibis  Tue Aug 27 14:37:11 1996
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9608272126.AA25298@rockie.nsc.com>
To: ibis-users@vhdl.org, awglaser@eos.ncsu.edu
Subject: error msg from s2ibis2 - PartII

Hi,

The last portion of my mail related to the errors I am getting
on using s2ibis2(HSPICE).

Let me know if anyone of you have encountered this before.

THis is how my [Pin] section looks like in .s2i file:

From owner-ibis  Wed Aug 28 15:59:12 1996
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From: harish.patel@tempe.vlsi.com
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Date: Wed, 28 Aug 1996 15:48:07 -0700
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To: ibis-users@vhdl.org
Subject: about s2ibis2
Mime-Version: 1.0
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I am trying ti generate IBIS model for bi-directional buffer with output
enable.

I have defined output-enable pin in my.s2i

[Pin]
1  vdd   VCC   POWER
2  0     GND   GND 
3  in    Inp   Input1
5  oen   En1   Enable1

[Model]		Enable1
[Model type]	Input
[Polarity]	Inverting
[Model File]	model.typ	model.min	model.max

When s2ibis2 generated diff spi files for diff runs, it does not set
DC conditions for oen pin.  So job fails due to this and it says in out file:

**error**:  no dc path to ground from node    0:oen       

When I manually edit a spice file and setup oen, job concludes.

Has anyone come across this problem?


=========================================================================
| Harish Patel                  | VLSI Technology, Inc.           ===   |
| Design Engineer               | Computing Products Group       /0 0\  | 
|                               | 8375 S River Parkway, MS 265  [  |  ] |
| harish.patel@tempe.vlsi.com   | Tempe, AZ 85284                \ ~ /  |
| 602-752-6202/Fax:602-752-6002 |                                 ---   |
-------------------------------------------------------------------------

From owner-ibis  Wed Aug 28 18:04:45 1996
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Date: Wed, 28 Aug 96 16:32 PDT
From: bob@icx.com ( Bob Ross)
To: ibis-users@vhdl.org
Subject: Forwarded: EDIF Version 4 0 0 changes

IBIS Committee

I am having problems with the ibis@vhdl.org reflector, so 
I am using the above reflector to get this message out.

Does anyone have inputs or concerns with the proposal
below for EDIF 4 0 0?

Bob Ross
Interconnectix, Inc.

Date: Tue, 27 Aug 1996 13:39:51 +0100
From: Alan R Williams <alanrw@cs.man.ac.uk>
Message-Id: <199608271239.NAA04794@cheetah.cs.man.ac.uk>
To: bob@icx.com
Subject: EDIF Version 4 0 0 changes


Hello Bob,

As part of finishing the EIA balloting process, we are notifying all
reviewers of the changes which were made as a result of their
comments.  With regard to the interfacing with IBIS files, the main
change has been the introduction on pcbPartCharacteristic for EDIF
parts.  The pcbPartCharacteristic can be either a
pcbPassivePartCharacteristic (RLC values) or a
pcbIbisPartCharacteristic which specifies the IBIS file, the IBIS
component within that file and matches up the terminals of the EDIF
part to the pins of the IBIS component.

I am enclosing the changes in the syntax which were made as a result
of your comment.  Could you please confirm by c.o.b. Friday 31st
August that you are satisfied with the outcome?  If we do not hear
otherwise, we will assume that you are satisfied with the changes
which have been made.

Alan Williams

-- ---------------------------------------------------------------------------
Alan Williams, Room IT301, Department of Computer Science,
University of Manchester, Oxford Road, Manchester, M13 9PL, U.K.
Tel: +44 161 275 6270      Fax: +44 161 275 6280
e-mail: alanrw@cs.man.ac.uk


pcbIbisComponentIdentification ::= '(' 'pcbIbisComponentIdentification'
	stringToken
	')'

pcbIbisFileIdentification ::= '(' 'pcbIbisFileIdentification'
	stringToken
	')'

pcbIbisFileInformation ::= '(' 'pcbIbisFileInformation'
	pcbIbisFileInformationNameDef
	pcbIbisFileIdentification
	{  <nameInformation>  |  property  }
	')'

pcbIbisFileInformationNameCaseSensitive ::= '(' 
'pcbIbisFileInformationNameCaseSensitive'
	booleanToken
	')'

pcbIbisFileInformationNameDef ::= nameDef

pcbIbisPartCharacteristic ::= '(' 'pcbIbisPartCharacteristic'
	pcbIbisFileInformation
	pcbIbisComponentIdentification
	{  pcbIbisPinBinding  }
	')'

pcbIbisPinBinding ::= '(' 'pcbIbisPinBinding'
	pcbIbisPinBindingNameDef
	( pcbElectricalPartTerminalRef | pcbJumperPartTerminalRef | 
pcbConnectorPartTerminalRef )
	pcbIbisPinIdentification
	{  property  }
	')'

pcbIbisPinBindingNameDef ::= nameDef

pcbIbisPinIdentification ::= '(' 'pcbIbisPinIdentification'
	stringToken
	')'

pcbJumperPart ::= '(' 'pcbJumperPart'
	libraryObjectNameDef
	pcbPartHeader
	( pcbPinPackageRef | pcbBallPackageRef | externalNoData )
	{  pcbJumperPartTerminal  |  <pcbPartCharacteristic>  }
	')'

pcbPackagedConnectorPart ::= '(' 'pcbPackagedConnectorPart'
	libraryObjectNameDef
	pcbPartHeader
	( pcbPinPackageRef | pcbBallPackageRef | externalNoData )
	( pcbSocket | pcbDiscreteConnector )
	{  pcbPackagedConnectorPartTerminal  |  <pcbPartCharacteristic>  }
	')'

pcbPackagedElectricalPart ::= '(' 'pcbPackagedElectricalPart'
	libraryObjectNameDef
	pcbPartHeader
	( pcbPinPackageRef | pcbBallPackageRef | externalNoData )
	pcbPackagedElectricalPartType
	{  <pcbPartCharacteristic>  }
	')'

pcbPartCharacteristic ::= '(' 'pcbPartCharacteristic'
	( pcbPassivePartCharacteristic | pcbIbisPartCharacteristic )
	')'

pcbPassivePartCapacitance ::= '(' 'pcbPassivePartCapacitance'
	capacitanceValue
	')'

pcbPassivePartCharacteristic ::= '(' 'pcbPassivePartCharacteristic'
	{  <pcbPassivePartCapacitance>  |  <pcbPassivePartInductance>  |  
<pcbPassivePartResistance>  }
	')'

pcbPassivePartInductance ::= '(' 'pcbPassivePartInductance'
	tolerancedInductanceValue
	')'

pcbPassivePartResistance ::= '(' 'pcbPassivePartResistance'
	tolerancedResistanceValue
	')'

pcbPrintedConnectorPart ::= '(' 'pcbPrintedConnectorPart'
	libraryObjectNameDef
	pcbPartHeader
	{  <pcbPartCharacteristic>  |  pcbPrintedConnectorPartTerminal  |  
pcbPrintedPartSymbol  }
	')'

pcbPrintedElectricalPart ::= '(' 'pcbPrintedElectricalPart'
	libraryObjectNameDef
	pcbPartHeader
	pcbPrintedElectricalPartType
	{  <pcbPartCharacteristic>  |  pcbPrintedPartSymbol  }
	')'




-------- End of Forwarded Message

From owner-ibis  Wed Aug 28 21:40:57 1996
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Date: Thu, 29 Aug 96 00:29:55 EDT
From: hoang@msai.mea.com (Hoang Nguyen)
Message-Id: <9608290429.AA07593@sbedrock.msai.mea.com>
To: ibis-users@vhdl.org, harish.patel@tempe.vlsi.com
Subject: Re: about s2ibis2

Harish,

I had the same problem.  For that, I need to provide a path to ground
from the node that gives me the error; i.e. connect node oen to a resistor
(~1K Ohm or so) which is grounded on one end.

Hoang Nguyen
Mitsubishi Semiconductor America, Inc.
Durham, North Carolina

> From owner-ibis@vhdl.vhdl.org Wed Aug 28 20:08:48 1996
> From: harish.patel@tempe.vlsi.com
> Date: Wed, 28 Aug 1996 15:48:07 -0700
> To: ibis-users@vhdl.org
> Subject: about s2ibis2
> Mime-Version: 1.0
> Content-Type> : > text/plain> ; > charset=us-ascii> 
> Content-Transfer-Encoding: 7bit
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> I am trying ti generate IBIS model for bi-directional buffer with output
> enable.
> 
> I have defined output-enable pin in my.s2i
> 
> [Pin]
> 1  vdd   VCC   POWER
> 2  0     GND   GND 
> 3  in    Inp   Input1
> 5  oen   En1   Enable1
> 
> [Model]		Enable1
> [Model type]	Input
> [Polarity]	Inverting
> [Model File]	model.typ	model.min	model.max
> 
> When s2ibis2 generated diff spi files for diff runs, it does not set
> DC conditions for oen pin.  So job fails due to this and it says in out file:
> 
> **error**:  no dc path to ground from node    0:oen       
> 
> When I manually edit a spice file and setup oen, job concludes.
> 
> Has anyone come across this problem?
> 
> 
> =========================================================================
> | Harish Patel                  | VLSI Technology, Inc.           ===   |
> | Design Engineer               | Computing Products Group       /0 0\  | 
> |                               | 8375 S River Parkway, MS 265  [  |  ] |
> | harish.patel@tempe.vlsi.com   | Tempe, AZ 85284                \ ~ /  |
> | 602-752-6202/Fax:602-752-6002 |                                 ---   |
> -------------------------------------------------------------------------
> 

