From owner-ibis Tue Jul 1 03:56:55 1997 Received: from nag.avisnet.or.jp (nag.avisnet.or.jp [202.247.192.33]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id DAA12812 for ; Tue, 1 Jul 1997 03:56:54 -0700 (PDT) Received: from olive (nmng045.avisnet.or.jp [202.247.200.45]) by nag.avisnet.or.jp (8.8.2/3.5W) with SMTP id TAA25493 for ; Tue, 1 Jul 1997 19:56:38 +0900 (JST) Message-Id: <199707011056.TAA25493@nag.avisnet.or.jp> X-Mailer: Microsoft Outlook Express 4.71.0544.0 From: "UtsumiEngineering" To: Subject: about s2ibis Date: Tue, 1 Jul 1997 19:59:33 +0900 X-Priority: 3 X-MSMail-Priority: Normal MIME-Version: 1.0 Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: 7bit X-MimeOLE: Produced By Microsoft MimeOLE Engine V4.71.0544.0 Dear Sir, I am from Utsumi Engineering, Japan. I had download s2ibis(s2ibis.zip.exe) but I couldn't see those subdirectory which indicated in README file. Also, I couldn't get tryme.ibs after testing tryme.txt with command s2ibis(s2ibis tryme tryme.ibs), it end with error massages. Those error massages are: s2ibis2: Error at line 1: parse error Token: *Lipa Current Buffer: *Lipa ^ s2ibis: Please begin s2ibis command file with [IBIS Ver] command. s2ibis: Errors in IBIS file prevent continuation. s2ibis: Opening file tryme.ibs for writing...done. What error massage mean(Error at line 1)? Could s2ibis run in Windows 95 or it should be run in UNIX environment? I hope you can help me to solve the problem. I am looking forward to hearing your answer. Thank you. Yours sincerely, K.T.Tham Utsume Engineering Japan From owner-ibis Mon Jul 7 15:26:41 1997 Received: from procyon.pmc-sierra.bc.ca (procyon.pmc-sierra.bc.ca [134.87.115.1]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id PAA00850 for ; Mon, 7 Jul 1997 15:26:40 -0700 (PDT) Received: from nt-server1.pmc-sierra.bc.ca (nt-server1.pmc-sierra.bc.ca [134.87.116.185]) by procyon.pmc-sierra.bc.ca (8.7.5/8.7.3) with SMTP id PAA07502 for ; Mon, 7 Jul 1997 15:25:17 -0700 (PDT) Received: by nt-server1.pmc-sierra.bc.ca with SMTP (Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63) id <01BC8AEA.11FC9EC0@nt-server1.pmc-sierra.bc.ca>; Mon, 7 Jul 1997 15:25:58 -0700 Message-ID: From: Roland Chang To: "'ibis-users@vhdl.org'" Subject: [model selector] keyword Date: Mon, 7 Jul 1997 15:25:57 -0700 X-Mailer: Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hello all, I was wondering, in the use of the model selector keyword, can one list POWER, GND, and NC? The reason I ask, is that in the case of pins that are usable in various modes, it often involves grounding, or leaving certain other pins open(NC). thanx, roland ****************************************** Roland Chang ext. 2647 PMC-Sierra Applications Department 105-8555 Baxter Place Burnaby, BC V5A 4V7 Tel: (604) 415-6000 email: chang@pmc-sierra.bc.ca ****************************************** eg: [Pin] signal_name model_name R_pin L_pin C_pin . . . 9 CLKI crystalbuf 10 CLKO crystalbuf . . . 19 IN(+) PECLbuf 20 IN(-) PECLbuf . . . [Model Selector] crystalbuf NC |default, CLKI, CLKO attached to a crystal pc5x03 |if CLKO left open (NC), feed external clock signal into CLKI [Model Selector] PECLbuf PECL_diff |default, IN(+), IN(-) function as PECL differential inputs PECL_single | IN(+) as single sided PECL, decouple IN(-) to ground. TTL_single | IN(+) as single sided TTL, IN(-) to ground. GND From owner-ibis Mon Jul 7 18:07:37 1997 Received: from fw.icx.com (root@fw.icx.com [205.238.6.33]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id SAA03295; Mon, 7 Jul 1997 18:07:36 -0700 (PDT) Received: by fw.icx.com (Smail-3.2.0.92 1997-Feb-9 #4) id ; Mon, 7 Jul 1997 18:06:27 -0700 (PDT) Received: by chane.icx.com (Smail-3.2.0.92 1997-Feb-9 #5) id ; Mon, 7 Jul 1997 18:06:19 -0700 (PDT) Received: by bob.icx.com via send-mail with stdio id for ibis@eda.org; Mon, 7 Jul 1997 18:06:20 -0700 (PDT) (Smail-3.2.0.92 1997-Feb-9 #7 built 1997-Jun-4) Message-Id: Date: Mon, 7 Jul 1997 18:06:20 -0700 (PDT) From: bob@icx.com ( Bob Ross) To: ibis-users@eda.org, roland_chang@pmc-sierra.bc.ca Subject: Re: [model selector] keyword Cc: ibis@eda.org Roland: I do not think we intended that the reserved words be used with [Model Selector]. As it stands, it looks like they could be used. We will need to raise this question as a clarification issue. As an alternative, the same effect could be accomplished by using a Terminator model to accomplish the same effect - a low resistance to ground or power for GND or POWER, and a high resistance for NC. In your example below, the [Model Selector] does not undo the differential association that may exist for the differential driver. Either the pins 19 and 20 will always be differential or be single ended based on the [Diff Pin] keyword. Best Regards, Bob Ross Interconnectix > From: Roland Chang > To: "'ibis-users@vhdl.org'" > Subject: [model selector] keyword > Date: Mon, 7 Jul 1997 15:25:57 -0700 > Hello all, > I was wondering, in the use of the model selector keyword, can one list > POWER, GND, and NC? > The reason I ask, is that in the case of pins that are usable in various > modes, it often involves grounding, or leaving certain other pins > open(NC). > thanx, > roland > ****************************************** > Roland Chang ext. 2647 > PMC-Sierra > Applications Department > 105-8555 Baxter Place > Burnaby, BC > V5A 4V7 > Tel: (604) 415-6000 > email: chang@pmc-sierra.bc.ca > ****************************************** > eg: > [Pin] signal_name model_name R_pin L_pin C_pin > . > . > . > 9 CLKI crystalbuf > 10 CLKO crystalbuf > . > . > . > 19 IN(+) PECLbuf > 20 IN(-) PECLbuf > . > . > . > [Model Selector] crystalbuf > NC |default, CLKI, CLKO attached to a crystal > pc5x03 |if CLKO left open (NC), feed external clock signal into CLKI > [Model Selector] PECLbuf > PECL_diff |default, IN(+), IN(-) function as PECL differential > inputs > PECL_single | IN(+) as single sided PECL, decouple IN(-) to ground. > TTL_single | IN(+) as single sided TTL, IN(-) to ground. > GND From owner-ibis Wed Jul 9 16:01:14 1997 Received: from procyon.pmc-sierra.bc.ca (procyon.pmc-sierra.bc.ca [134.87.115.1]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA14267 for ; Wed, 9 Jul 1997 16:01:13 -0700 (PDT) Received: from nt-server1.pmc-sierra.bc.ca (nt-server1.pmc-sierra.bc.ca [134.87.116.185]) by procyon.pmc-sierra.bc.ca (8.7.5/8.7.3) with SMTP id QAA29593 for ; Wed, 9 Jul 1997 16:00:04 -0700 (PDT) Received: by nt-server1.pmc-sierra.bc.ca with SMTP (Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63) id <01BC8C81.42509B60@nt-server1.pmc-sierra.bc.ca>; Wed, 9 Jul 1997 16:00:45 -0700 Message-ID: From: Roland Chang To: "'ibis-users@vhdl.org'" Subject: capacitor to ground, and terminator models Date: Wed, 9 Jul 1997 16:00:44 -0700 X-Mailer: Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hello all I am wondering about the use of the terminator model. I have a pair of pins that can be used either as a differential PECL pair, as a single PECL input, or as a single TTL input. When used as a single PECL input, the non-inverting pin is decoupled to ground through an externally connected 0.01uF capacitor in series. When used as a single TTL input, the non-inverting pin is connected to ground. My question is, when using the pair of pins in single sided PECL mode, what should I use as the model for the pin decoupled to ground? Should I use simply GND, or a TERMINATOR model? ie: [Pin] . . . |select pins 120 and 121 as either option A, B or C depending on which mode |the pair of pins are being used in. |A: Differential PECL pair mode. (DEFAULT) 120 TRCLKP pecl06a_PECL2 NA 26.6nH 1.20pF 121 TRCLKN pecl06a_PECL2 NA 26.6nH 1.20pF | |B: Single sided PECL mode. TRCLKP decoupled to ground through 0.01uF capacitor | Note that input is now inverting. |120 TRCLKP GND?? NA 26.6nH 1.20pF or |120 TRCLKP PECLterm?? NA 26.6nH 1.20pF |121 TRCLKN pecl06a_PECL1 NA 26.6nH 1.20pF | |C: Single sided TTL mode. TRCLKP connected to ground. | Note that input is now inverting. |120 TRCLKP GND NA 26.6nH 1.20pF |121 TRCLKN pecl06a_TTL NA 26.6nH 1.20pF | . . . Also, for TERMINATOR models, what exactly is required? are ground clamp and power clamp tables required? are [Rgnd] and [Rpower] required? or can I just simply list [Rac] and [Cac] (with NONE of [Rpower], [Rgnd], ground clamp, or power clamp curves)? thanx in advance, roland ****************************************** Roland Chang ext. 2647 PMC-Sierra Applications Department 105-8555 Baxter Place Burnaby, BC V5A 4V7 Tel: (604) 415-6000 email: chang@pmc-sierra.bc.ca ****************************************** From owner-ibis Wed Jul 9 16:51:12 1997 Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA14976 for ; Wed, 9 Jul 1997 16:51:11 -0700 (PDT) Received: from ichips.intel.com (ichips.intel.com [134.134.50.200]) by ormail.intel.com (8.8.4/8.8.4) with ESMTP id QAA08229 for ; Wed, 9 Jul 1997 16:49:45 -0700 (PDT) Received: from ichips.intel.com by ichips.intel.com (8.7.4/jIII) id QAA02802; Wed, 9 Jul 1997 16:50:03 -0700 (PDT) Message-Id: <199707092350.QAA02802@ichips.intel.com> To: ibis-users@vhdl.org Subject: capacitor to ground, and terminator models Date: Wed, 09 Jul 1997 16:50:03 -0700 From: Stephen Peters Hello Roland: In both cases it appears that in single sided mode pin 120 is not connected to another chip (i.e. it's at a static, non switching level) and so I would make that pin have a model type of NC. Yes, I know that 'strictly speaking' it is not a "No Connect", but for simulation purposes NC is the proper choice. Regards, Stephen Peters Intel Corp. -------------------------------------------------------- On Wed, 9 Jul 1997 16:00:44 -0700 Roland Chang wrote: Hello all I am wondering about the use of the terminator model. I have a pair of pins that can be used either as a differential PECL pair, as a single PECL input, or as a single TTL input. When used as a single PECL input, the non-inverting pin is decoupled to ground through an externally connected 0.01uF capacitor in series. When used as a single TTL input, the non-inverting pin is connected to ground. My question is, when using the pair of pins in single sided PECL mode, what should I use as the model for the pin decoupled to ground? Should I use simply GND, or a TERMINATOR model? ie: [Pin] . . . |select pins 120 and 121 as either option A, B or C depending on which mode |the pair of pins are being used in. |A: Differential PECL pair mode. (DEFAULT) 120 TRCLKP pecl06a_PECL2 NA 26.6nH 1.20pF 121 TRCLKN pecl06a_PECL2 NA 26.6nH 1.20pF | |B: Single sided PECL mode. TRCLKP decoupled to ground through 0.01uF capacitor | Note that input is now inverting. |120 TRCLKP GND?? NA 26.6nH 1.20pF or |120 TRCLKP PECLterm?? NA 26.6nH 1.20pF |121 TRCLKN pecl06a_PECL1 NA 26.6nH 1.20pF | |C: Single sided TTL mode. TRCLKP connected to ground. | Note that input is now inverting. |120 TRCLKP GND NA 26.6nH 1.20pF |121 TRCLKN pecl06a_TTL NA 26.6nH 1.20pF | . . . Also, for TERMINATOR models, what exactly is required? are ground clamp and power clamp tables required? are [Rgnd] and [Rpower] required? or can I just simply list [Rac] and [Cac] (with NONE of [Rpower], [Rgnd], ground clamp, or power clamp curves)? thanx in advance, roland ****************************************** Roland Chang ext. 2647 PMC-Sierra Applications Department 105-8555 Baxter Place Burnaby, BC V5A 4V7 Tel: (604) 415-6000 email: chang@pmc-sierra.bc.ca ****************************************** From owner-ibis Mon Jul 14 09:21:23 1997 Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id JAA07823; Mon, 14 Jul 1997 09:21:23 -0700 (PDT) Received: from ichips.intel.com (ichips.intel.com [134.134.50.200]) by ormail.intel.com (8.8.4/8.8.4) with ESMTP id JAA21637; Mon, 14 Jul 1997 09:19:58 -0700 (PDT) Received: from ichips.intel.com by ichips.intel.com (8.7.4/jIII) id JAA15012; Mon, 14 Jul 1997 09:20:16 -0700 (PDT) Message-Id: <199707141620.JAA15012@ichips.intel.com> To: ibis@vhdl.org, ibis-users@vhdl.org Subject: Persons needed for Golden Parser Development Date: Mon, 14 Jul 1997 09:20:15 -0700 From: Stephen Peters Greetings Fellow IBIS fans and users: As you are probably aware, IBIS version 3.0 was approved at the IBIS Open Forum face to face meeting on June 7. With the approval of the new IBIS version the Golden Parser program ("ibis_chk2") must now be upgraded. Unfortunately, the contractors (Paul Munsey and company) who wrote the first two versions of the golden parser are not available to work on a version 3.0 of ibis_chk. Therefore, the IBIS Open Forum is soliciting names of any companies or individuals who may be interested in bidding on this project. If you or your company are interested, or you know of a contractor who may be, please contact Stephen Peters (EIA IBIS Open Forum Secretary) at the address below. An informal request for quote is available for the asking. Thanks for your help. Best Regards, Stephen Peters EIA/IBIS Open Forum Secretary Intel Corp. --------------------------------------------------------------------- Stephen J. Peters MS JF1-55 Phone: (503) 264-4108 Intel Corporation Internet: sjpeters@ichips.intel.com 2111 N.E. 25th Ave. Fax: (503) 264-4515 Hillsboro, OR 97124-6497 Microprocessor Division 6 From owner-ibis Wed Jul 16 01:48:48 1997 Received: from jester.ti.com (jester.ti.com [192.94.94.1]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id BAA12404 for ; Wed, 16 Jul 1997 01:48:47 -0700 (PDT) Received: from robin.itg.ti.com ([172.25.2.75]) by jester.ti.com (8.8.5) with ESMTP id DAA05426 for ; Wed, 16 Jul 1997 03:47:11 -0500 (CDT) Received: from itg.ti.com (magic.itg.ti.com [172.25.2.76]) by robin.itg.ti.com (8.8.5/8.8.5) with SMTP id DAA09066 for ; Wed, 16 Jul 1997 03:47:09 -0500 (CDT) Received: from king.india.ti.com by itg.ti.com (4.1/ITG-1.1) id AA27464; Wed, 16 Jul 97 03:47:03 CDT Received: from dadsparc37.india.ti.com (dadsparc37 [134.183.191.27]) by king.india.ti.com (8.8.5/8.6.10) with ESMTP id OAA00728 for ; Wed, 16 Jul 1997 14:16:26 +0530 (IST) Received: (from vkumar@localhost) by dadsparc37.india.ti.com (8.6.12/8.6.10) id DAA25599; Wed, 16 Jul 1997 03:48:15 -0500 Date: Wed, 16 Jul 1997 03:48:15 -0500 Message-Id: <199707160848.DAA25599@dadsparc37.india.ti.com> From: Vipul Singhal Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit To: ibis-users@vhdl.org Cc: sram@india.ti.com, vkumar@india.ti.com, ngs@india.ti.com Subject: Process parameters X-Mailer: VM 6.30 under 19.15 XEmacs Lucid Hello all, I have a doubt regarding the method for obtaining the curves by simulation as outlined in IBIS COOKBOOK. The cookbook says ( under the section 3.3.1 : "OBTAINING CURVES BY SIMULATION - Simulation Specifics" ) that : "For both the rise/fall time and I-V curve measurements, use "typical" process parameters." "For CMOS: min = min VCC, max temperature, typ process parameters --- max = max VCC, min temperature, typ process parameters" --- Later it says that " To account for process variation, decrease the current values taken at min conditions, increase the current values taken at max, and derate the rise and fall time values by the appropriate percentages. " This seems to be a roundabout way of doing it. Why can't we directly use "typ" , "min" , and "max" process parameters, as appropriate, directly in the simulations ? For example, if SPICE is used for simulation, we can have three different SPICE models for transistors, corresponding to the process-variation corners. Why should "typical" be used in each case ? Regards, Vipul K. Singhal Texas Instruments From owner-ibis Wed Jul 16 05:48:00 1997 Received: from acy1hp03.mea.com (acy1hp03.mea.com [208.145.189.35]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id FAA16570 for ; Wed, 16 Jul 1997 05:47:59 -0700 (PDT) Received: from gatekeeper.msai.mea.com by acy1hp03.mea.com with ESMTP (8.7.1/16.2) id FAA02443; Wed, 16 Jul 1997 05:40:44 -0700 (PDT) Received: (from uucp@localhost) by gatekeeper.msai.mea.com (8.6.12/8.6.12) id IAA10081; Wed, 16 Jul 1997 08:43:23 -0400 Received: from unknown(198.28.5.20) by gatekeeper.msai.mea.com via smap (V1.3) id sma010065; Wed Jul 16 08:43:01 1997 Received: from sbedrock.msai.mea.com (shared [192.65.252.62]) by msai.mea.com (8.6.12/8.6.12) with SMTP id IAA00556; Wed, 16 Jul 1997 08:50:37 -0400 Received: from sfred.msaiasic by sbedrock.msai.mea.com (4.1/mh-version 2.4) id AA07901; Wed, 16 Jul 97 08:46:36 EDT Date: Wed, 16 Jul 97 08:46:36 EDT From: hoang@msai.mea.com (Hoang Nguyen) Message-Id: <9707161246.AA07901@sbedrock.msai.mea.com> To: ibis-users@vhdl.org, vkumar@india.ti.com Subject: Re: Process parameters Cc: sram@india.ti.com, ngs@india.ti.com Hello Vipul, Since we create our IBIS models from SPICE data, we would use "typ", "min", "max" process parameters if we have them all. Usually, the customers require us to have all the process- variation corners in the model. So I think the cookbook can include the case of "min", and "max" as well as "typ". Regards, Hoang Nguyen Mitsubishi Semiconductor America, Inc. > From owner-ibis@server.vhdl.org Wed Jul 16 05:50:44 1997 > Date: Wed, 16 Jul 1997 03:48:15 -0500 > From: Vipul Singhal > Mime-Version: 1.0 > Content-Type> : > text/plain> ; > charset=us-ascii> > Content-Transfer-Encoding: 7bit > To: ibis-users@vhdl.org > Cc: sram@india.ti.com, vkumar@india.ti.com, ngs@india.ti.com > Subject: Process parameters > X-Mailer: VM 6.30 under 19.15 XEmacs Lucid > Content-Length: 1268 > > > Hello all, > > I have a doubt regarding the method for obtaining the curves > by simulation as outlined in IBIS COOKBOOK. The cookbook says ( under > the section 3.3.1 : "OBTAINING CURVES BY SIMULATION - Simulation > Specifics" ) that : > > "For both the rise/fall time and I-V curve measurements, > use "typical" process parameters." > > "For CMOS: > min = min VCC, max temperature, typ process parameters > --- > max = max VCC, min temperature, typ process parameters" > --- > > Later it says that " To account for process variation, decrease the > current values taken at min conditions, increase the current values > taken at max, and derate the rise and fall time values by the > appropriate percentages. " > > This seems to be a roundabout way of doing it. Why can't we > directly use "typ" , "min" , and "max" process parameters, as > appropriate, directly in the simulations ? For example, if SPICE is > used for simulation, we can have three different SPICE models for > transistors, corresponding to the process-variation corners. Why > should "typical" be used in each case ? > > Regards, > Vipul K. Singhal > Texas Instruments > > From owner-ibis Wed Jul 16 07:08:25 1997 Received: from mail11.digital.com (mail11.digital.com [192.208.46.10]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id HAA17953 for ; Wed, 16 Jul 1997 07:08:25 -0700 (PDT) Received: from us8rmc.bb.dec.com (us8rmc.bb.dec.com [16.53.0.44]) by mail11.digital.com (8.7.5/UNX 1.5/1.0/WV) with SMTP id JAA29866; Wed, 16 Jul 1997 09:58:58 -0400 (EDT) Received: from wrksys.enet by us8rmc.bb.dec.com (5.65/rmc-17Jan97) id AA27525; Wed, 16 Jul 97 09:57:18 -0400 Message-Id: <9707161357.AA27525@us8rmc.bb.dec.com> Received: from wrksys.enet; by us8rmc.enet; Wed, 16 Jul 97 09:58:57 EDT Date: Wed, 16 Jul 97 09:58:57 EDT From: Andy Ingraham To: vkumar@india.ti.com Cc: ibis-users@vhdl.org, ingraham@wrksys.ENET.dec.com Apparently-To: ibis-users@vhdl.org, vkumar@india.ti.com Subject: Re: Process parameters Vipul, I have no idea why it says what it does in the cookbook. But I think you should always use best/worst case process models if you have them. If you don't have them, then you may need to fudge them by tweaking the typical process curves. This may be the case if you are characterizing actual devices where almost everything is typical. The IBIS spec itself (version 2.1) also has some discussion about using "typical process, minus 'X%'" and "typical process, plus 'X%'." As far as I am concerned, you should ignore such wording and just do the right thing. Use your min and max process parameters. Regards, Andy From owner-ibis Wed Jul 16 08:16:55 1997 Received: from palrel1.hp.com (palrel1.hp.com [156.153.255.235]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id IAA19202 for ; Wed, 16 Jul 1997 08:16:54 -0700 (PDT) From: JEAN-CHRISTOPHE_PAUTRAT@HP-France-om5.om.hp.com Received: from rossini.grenoble.hp.com (rossini.grenoble.hp.com [15.128.127.193]) by palrel1.hp.com (8.8.5/8.8.5) with ESMTP id IAA03426 for ; Wed, 16 Jul 1997 08:15:47 -0700 (PDT) Received: from localhost (root@localhost) by rossini.grenoble.hp.com with SMTP (8.7.6/8.7.3 TIS Messaging 5.0 Openmail) id RAA03325 for ibis-users@vhdl.org; Wed, 16 Jul 1997 17:15:44 +0200 (METDST) X-OpenMail-Hops: 1 Date: Wed, 16 Jul 97 17:15:36 +0200 Message-Id: Subject: voltage and temperature in corner cases MIME-Version: 1.0 TO: ibis-users@vhdl.org Content-Type: text/plain; charset=US-ASCII; name="cc:Mail" Content-Disposition: inline; filename="cc:Mail" Content-Transfer-Encoding: 7bit Hello, maybe someone already asked this question in the past, I don't know. I'm trying to figure out how to tweak all the parameters to exercise worst case simulations. Let's take the example of a strong and fast driver. The C_comp and parasitics will be the only parameters of the driver to be weak. All receiver parameters will be weak (parasitics and clamping diodes only). Let's say I tune the parameters of the PCB to be weak also. So far everything is logical. I've got a problem with the voltage and temperature parameters. Let's say I have ibis models for 5V cmos device, where min and max parameters were extracted in the following conditions : min = minimum voltage, max temp deg C max = maximum voltage, min temp deg C then, I would have to supply the driver with 5.5V and the receiver with 4.5V which is absolutely not realistic. This case never happens on a motherboard. Also what voltage should be used to connect the components tied to Vcc in between them ? Same thing for the temperature. There will never be let's say @ -50C on one side and +70C on the other side. Moreover, what temperature value shall I give to the simulation software for the components in between the driver and receiver ?... In summary : what are the Vcc and temp values I shall use for the corner case simulations ? thanks and best regards, Jean-Christophe PAUTRAT, R&D Engineer, Design Engineering Commercial Desktop Computer Division, H E W L E T T - P A C K A R D From owner-ibis Wed Jul 16 08:43:52 1997 Received: from calliope1.fm.intel.com (calliope1.fm.intel.com [132.233.247.10]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id IAA19481 for ; Wed, 16 Jul 1997 08:43:51 -0700 (PDT) Received: from fmmail.fm.intel.com by calliope1.fm.intel.com (8.8.6/10.0i); Wed, 16 Jul 1997 15:42:39 GMT Received: (from ccmgate@localhost) by fmmail.fm.intel.com (8.8.5/8.7.3) id IAA21752; Wed, 16 Jul 1997 08:41:21 -0700 (PDT) Received: by ccm.fm.intel.com (ccmgate 3.2 #2) Wed, 16 Jul 97 08:41:21 PDT Date: Wed, 16 Jul 97 08:13:00 PDT From: Arpad Muranyi Message-ID: To: ibis-users@vhdl.org, vkumar@india.ti.com cc: sram@india.ti.com, ngs@india.ti.com Subject: Re[2]: Process parameters Text item: To all, The reason we originally wrote those guidelines in the "notes on data derivation method" section was this: Many times the process files describe the absolute worst cases which result in very large variations. Most often such worst case conditions do not exist in real life. When you are working on a high speed system, you might not find a solution using such models. This is why we choose to recommend to use the typical process with temperature and supply variations only. The extra guardbanding factor is there to provide for additional derating which is to account for the process variations. You might ask why, if you could do the same with using the best and worst case process files. These guardbanding factors can be chosen so that your model would be more realistic than using the absolute best and worst case process files. For example, if your process files are made for 6 sigma variations, but you want only 3 sigma models, you can come up with a derating factor to make 3 sigma models using the typical process with voltage and temperature + derating factor. Of course, if you have a 3 sigma process file, you could just use them to convert to IBIS format without using the derating factor. It is really up to you which method you chose. The whole point is that we want to provide the means to be able to make realistic models for the devices. Arpad Muranyi Intel Corporation ============================================================================= Hello Vipul, Since we create our IBIS models from SPICE data, we would use "typ", "min", "max" process parameters if we have them all. Usually, the customers require us to have all the process- variation corners in the model. So I think the cookbook can include the case of "min", and "max" as well as "typ". Regards, Hoang Nguyen Mitsubishi Semiconductor America, Inc. > From owner-ibis@server.vhdl.org Wed Jul 16 05:50:44 1997 > Date: Wed, 16 Jul 1997 03:48:15 -0500 > From: Vipul Singhal > Mime-Version: 1.0 > Content-Type> : > text/plain> ; > charset=us-ascii> > Content-Transfer-Encoding: 7bit > To: ibis-users@vhdl.org > Cc: sram@india.ti.com, vkumar@india.ti.com, ngs@india.ti.com > Subject: Process parameters > X-Mailer: VM 6.30 under 19.15 XEmacs Lucid > Content-Length: 1268 > > > Hello all, > > I have a doubt regarding the method for obtaining the curves > by simulation as outlined in IBIS COOKBOOK. The cookbook says ( under > the section 3.3.1 : "OBTAINING CURVES BY SIMULATION - Simulation > Specifics" ) that : > > "For both the rise/fall time and I-V curve measurements, > use "typical" process parameters." > > "For CMOS: > min = min VCC, max temperature, typ process parameters > --- > max = max VCC, min temperature, typ process parameters" > --- > > Later it says that " To account for process variation, decrease the > current values taken at min conditions, increase the current values > taken at max, and derate the rise and fall time values by the > appropriate percentages. " > > This seems to be a roundabout way of doing it. Why can't we > directly use "typ" , "min" , and "max" process parameters, as > appropriate, directly in the simulations ? For example, if SPICE is > used for simulation, we can have three different SPICE models for > transistors, corresponding to the process-variation corners. Why > should "typical" be used in each case ? > > Regards, > Vipul K. Singhal > Texas Instruments > > Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Cc: sram@india.ti.com, ngs@india.ti.com Subject: Re: Process parameters To: ibis-users@vhdl.org, vkumar@india.ti.com Message-Id: <9707161246.AA07901@sbedrock.msai.mea.com> From: hoang@msai.mea.com (Hoang Nguyen) Date: Wed, 16 Jul 97 08:46:36 EDT Received: from sfred.msaiasic by sbedrock.msai.mea.com (4.1/mh-version 2.4) id AA07901; Wed, 16 Jul 97 08:46:36 EDT Received: from sbedrock.msai.mea.com (shared [192.65.252.62]) by msai.mea.com (8 .6.12/8.6.12) with SMTP id IAA00556; Wed, 16 Jul 1997 08:50:37 -0400 Received: from unknown(198.28.5.20) by gatekeeper.msai.mea.com via smap (V1.3) id sma010065; Wed Jul 16 08:43:01 1997 Received: (from uucp@localhost) by gatekeeper.msai.mea.com (8.6.12/8.6.12) id IA A10081; Wed, 16 Jul 1997 08:43:23 -0400 Received: from gatekeeper.msai.mea.com by acy1hp03.mea.com with ESMTP (8.7.1/16.2) id FAA02443; Wed, 16 Jul 1997 05:40:44 -0700 (PDT) Received: from acy1hp03.mea.com (acy1hp03.mea.com [208.145.189.35]) by server.vh dl.org (8.8.5/8.8.3) with ESMTP id FAA16570 for ; Wed, 16 J ul 1997 05:47:59 -0700 (PDT) Received: from server.vhdl.org (server.vhdl.org [198.31.14.3]) by mailbag.jf.intel.com (8.8.6/8.8.4) with ESMTP id GAA17896; Wed, 16 Jul 1997 06:06:02 -0700 (PDT) Received: from mailbag.jf.intel.com by relay.hf.intel.com with smtp (Smail3.1.28.1 #2) id m0woTl4-000qDJC; Wed, 16 Jul 97 06:04 PDT From owner-ibis Wed Jul 16 08:54:57 1997 Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id IAA19636 for ; Wed, 16 Jul 1997 08:54:56 -0700 (PDT) Received: from ichips.intel.com (ichips.intel.com [134.134.50.200]) by ormail.intel.com (8.8.6/8.8.4) with ESMTP id IAA23367 for ; Wed, 16 Jul 1997 08:53:27 -0700 (PDT) Received: from ichips.intel.com by ichips.intel.com (8.7.4/jIII) id IAA06667; Wed, 16 Jul 1997 08:53:46 -0700 (PDT) Message-Id: <199707161553.IAA06667@ichips.intel.com> To: ibis-users@vhdl.org Subject: Process parameters Date: Wed, 16 Jul 1997 08:53:44 -0700 From: Stephen Peters Hello All: Mr. Singhal raises a good point, and I thought I'd respond. In my experience the "min" and "max" process corners in a semicondutor model (especially for the early version processes I deal with) could be better labled "really, really min" and "absloluty, positivly, completly max". These corners are usually so far out there that a model built at those corners is unrealistic. By this I mean that by the time a part is speced and the useful yeilds determined the customer probably never ever sees a truly "min" and "max" part. There is also the problem of having to figure out how to correlate the parameters that are used in production testing of a part (Tco, power dissipation, etc.) with the parameters an I/O buffer model cares about (edge rate and drive strength). For example, does the min and max Tco really correspond to min and max drive strength? Given all that, one can resonable use an imperical % derating factor to determine the corners of an IBIS model. This is not to say that varying the process corners is not a useful way to make min and max models. One just has to understand that "min" and "max" process corners do not necesarly represent the worst and best case I/O buffers the customer receives. Best Regards, Stephen Peters Intel Corp. > On Wed, 16 Jul 1997 03:48:15 -0500, Vipul K. Singhal wrote: Hello all, I have a doubt regarding the method for obtaining the curves by simulation as outlined in IBIS COOKBOOK. The cookbook says ( under the section 3.3.1 : "OBTAINING CURVES BY SIMULATION - Simulation Specifics" ) that : "For both the rise/fall time and I-V curve measurements, use "typical" process parameters." "For CMOS: min = min VCC, max temperature, typ process parameters --- max = max VCC, min temperature, typ process parameters" --- Later it says that " To account for process variation, decrease the current values taken at min conditions, increase the current values taken at max, and derate the rise and fall time values by the appropriate percentages. " This seems to be a roundabout way of doing it. Why can't we directly use "typ" , "min" , and "max" process parameters, as appropriate, directly in the simulations ? For example, if SPICE is used for simulation, we can have three different SPICE models for transistors, corresponding to the process-variation corners. Why should "typical" be used in each case ? Regards, Vipul K. Singhal Texas Instruments From owner-ibis Wed Jul 16 09:05:54 1997 Received: from relayhost.vlsi.com (tweety.vlsi.com [134.27.20.23]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id JAA19818 for ; Wed, 16 Jul 1997 09:05:53 -0700 (PDT) From: harish.patel@tempe.vlsi.com Received: from relayhost.tempe.vlsi.com (anubis.tempe.vlsi.com [134.27.128.1]) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) with ESMTP id KAA17983; Wed, 16 Jul 1997 10:27:56 -0700 Received: from pcdmail.tempe.vlsi.com (hole.tempe.vlsi.com [134.27.128.11]) by relayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/101195) with ESMTP id JAA27535; Wed, 16 Jul 1997 09:04:07 -0700 Received: from mardi (mardi [134.27.133.22]) by pcdmail.tempe.vlsi.com (8.6.9/Hub-Perlotto/032095) with SMTP id JAA08442; Wed, 16 Jul 1997 09:04:06 -0700 Received: by mardi id AA22691; Wed, 16 Jul 1997 09:04:05 -0700 Date: Wed, 16 Jul 1997 09:04:05 -0700 Message-Id: <9707161604.AA22691@mardi> To: ibis-users@vhdl.org, vkumar@india.ti.com Subject: Process parameters Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-Md5: FPdBQGM4NR+QaXjIzm861g== Hi Vipul, If you have the process parameters for the three cases - typ, min and max, then you should use them to generate typ, min and max curves and include them in the model. If you have only typ process parameters, then you should create artifically min and max curves based on the typ curves. _______________________________________________________________ Harish Patel VLSI Technology, Inc. Sr. Design Engineer Computing Solutions Group harish.patel@tempe.vlsi.com 8375 S River Parkway 602-752-6202/Fax:602-752-6002 Tempe, Arizona 85284 _______________________________________________________________ A policy is a temporary creed liable to be changed, but while it holds good it has to be pursued with apostolic zeal. -- Mahatma Gandhi From owner-ibis Wed Jul 16 09:16:58 1997 Received: from fw.icx.com (root@fw.icx.com [205.238.6.33]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id JAA19975 for ; Wed, 16 Jul 1997 09:16:57 -0700 (PDT) Received: by fw.icx.com (Smail-3.2.0.92 1997-Feb-9 #4) id ; Wed, 16 Jul 1997 09:11:29 -0700 (PDT) Received: by chane.icx.com (Smail-3.2.0.92 1997-Feb-9 #5) id ; Wed, 16 Jul 1997 09:11:19 -0700 (PDT) Sender: chris Message-ID: <33CCF2AD.15FB7483@icx.com> Date: Wed, 16 Jul 1997 09:11:25 -0700 From: "Christopher E. Reid" Organization: Interconnectix X-Mailer: Mozilla 3.0Gold (X11; I; SunOS 4.1.4 sun4m) MIME-Version: 1.0 To: JEAN-CHRISTOPHE_PAUTRAT@hp-france-om5.om.hp.com CC: ibis-users@vhdl.org Subject: Re: voltage and temperature in corner cases References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Jean, The "worst case" depends entirely on what you are trying to measure and the topology of your nets. There is no easy way to define "worst case." However, some of your questions can be answered. Most likely your simulator ignores the temperature variations. The temperature range indicates a reasonable operating range for the part, and is supposed to have some connection to min and max corners, but there is no direct tie between the temperature you choose and the model that gets simulated unless your simulator specifically defines one, in which case you'd better ask the simulator vendor what is intended. If you want a weak driver then use the "min" of most everything, but use the "max" C_comp. If you want a high impedance receiver, you can figure out what to use as well as anyone. If you want the "worst case" for a particular net, all bets are off. If by worst case you mean the most ringing, or the longest time to "final settle", then that depends on the net topology as well as the driver and receiver characteristics. For example, if you are using a balanced topology, say a star, then the worst case is probably unbalanced receivers, some high impedance, some low impedance. There is no easy answer, although there is some theory behind this which can be used to get an idea of what might be "worst case." The only way to be sure is to run a Monte-Carlo type variation of all the drivers and receivers, not to mention process variations on you board, actual lengths of lines, etc. Christopher Reid Interconnectix http://www.icx.com JEAN-CHRISTOPHE_PAUTRAT@HP-France-om5.om.hp.com wrote: > > Hello, > > maybe someone already asked this question in the past, I don't know. > > I'm trying to figure out how to tweak all the parameters to exercise > worst case simulations. Let's take the example of a strong and fast > driver. The C_comp and parasitics will be the only parameters of the > driver to be weak. All receiver parameters will be weak (parasitics > and clamping diodes only). Let's say I tune the parameters of the PCB > to be weak also. So far everything is logical. > > I've got a problem with the voltage and temperature parameters. Let's > say I have ibis models for 5V cmos device, where min and max > parameters were extracted in the following conditions : > > min = minimum voltage, max temp deg C > max = maximum voltage, min temp deg C > > then, I would have to supply the driver with 5.5V and the receiver > with 4.5V which is absolutely not realistic. This case never happens > on a motherboard. Also what voltage should be used to connect the > components tied to Vcc in between them ? > > Same thing for the temperature. There will never be let's say @ -50C > on one side and +70C on the other side. Moreover, what temperature > value shall I give to the simulation software for the components in > between the driver and receiver ?... > > In summary : what are the Vcc and temp values I shall use for the > corner case simulations ? > > thanks and best regards, > > Jean-Christophe PAUTRAT, > R&D Engineer, Design Engineering > Commercial Desktop Computer Division, > H E W L E T T - P A C K A R D From owner-ibis Wed Jul 16 10:51:19 1997 Received: from VNET.IBM.COM (vnet.ibm.com [204.146.168.194]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id KAA21357 for ; Wed, 16 Jul 1997 10:50:18 -0700 (PDT) Message-Id: <199707161750.KAA21357@server.vhdl.org> Received: from RALVM29 by VNET.IBM.COM (IBM VM SMTP V2R3) with BSMTP id 8624; Wed, 16 Jul 97 13:48:47 EDT Date: Wed, 16 Jul 97 13:43:23 EDT From: "J. C. (Jay) Diepenbrock ((919)-543-8804)" X-Addr: Interconnect Technology & Quality, B8UA/061/R118 IBM Global Procurement P. O. Box 12195 Research Triangle Park, NC 27709 To: ibis_users@vhdl.org Subject: IBIS simulators Greetings all, After being away from the IBIS world for a while, I'm trying to get plugged back into the current state of things. Can someone fill me in on what my options are for what I would call standalone simulation? (By that I mean simulation of board nets using IBIS models with the input from a schematic, rather than a board layout database.) Meta-Software (now Avant!) had originally planned to support IBIS, then backed away, but I don't know what has happened since for those of us that want to do topology studies before boards are designed. Thanks for your nominations for "simulator of the week" awards. Jay Diepenbrock From owner-ibis Wed Jul 16 11:20:03 1997 Received: from ole.cdac.com (ole.cdac.com [199.5.216.26]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id LAA21663 for ; Wed, 16 Jul 1997 11:20:01 -0700 (PDT) Received: from ember.cdac.com (fwuser@cascade.cdac.com [199.5.216.206]) by ole.cdac.com (8.8.5/8.7.1) with ESMTP id LAA27524 for ; Wed, 16 Jul 1997 11:19:09 -0700 (PDT) Received: from quark.cdac.com (quark.cdac.com [10.0.10.112]) by ember.cdac.com (8.7.1/8.7.1) with ESMTP id LAA29084; Wed, 16 Jul 1997 11:18:41 -0700 (PDT) From: Lynne Green Received: (from lgreen@localhost) by quark.cdac.com (8.7.1/8.7.1) id LAA18497; Wed, 16 Jul 1997 11:18:36 -0700 (PDT) Date: Wed, 16 Jul 1997 11:18:36 -0700 (PDT) Message-Id: <199707161818.LAA18497@quark.cdac.com> To: ibis-users@vhdl.org Subject: Process parameters Cc: lgreen@ember.cdac.com re Process Corners: Delay and drive strength really need 4 process corners: Best N, Best P Worst N, Worst P Best N, Worst P Worst N, Best P You will often hear IC designers talk about 16-corner simulations: 2**4 process corners * 2 temperature corners * 2 VDD corners. Good luck. Lynne Green Cascade Design Automation ----- Begin Included Message ----- From owner-ibis@server.vhdl.org Wed Jul 16 10:26:57 1997 To: ibis-users@vhdl.org Subject: Process parameters Date: Wed, 16 Jul 1997 08:53:44 -0700 From: Stephen Peters Hello All: Mr. Singhal raises a good point, and I thought I'd respond. In my experience the "min" and "max" process corners in a semicondutor model (especially for the early version processes I deal with) could be better labled "really, really min" and "absloluty, positivly, completly max". These corners are usually so far out there that a model built at those corners is unrealistic. By this I mean that by the time a part is speced and the useful yeilds determined the customer probably never ever sees a truly "min" and "max" part. There is also the problem of having to figure out how to correlate the parameters that are used in production testing of a part (Tco, power dissipation, etc.) with the parameters an I/O buffer model cares about (edge rate and drive strength). For example, does the min and max Tco really correspond to min and max drive strength? Given all that, one can resonable use an imperical % derating factor to determine the corners of an IBIS model. This is not to say that varying the process corners is not a useful way to make min and max models. One just has to understand that "min" and "max" process corners do not necesarly represent the worst and best case I/O buffers the customer receives. Best Regards, Stephen Peters Intel Corp. > On Wed, 16 Jul 1997 03:48:15 -0500, Vipul K. Singhal wrote: Hello all, I have a doubt regarding the method for obtaining the curves by simulation as outlined in IBIS COOKBOOK. The cookbook says ( under the section 3.3.1 : "OBTAINING CURVES BY SIMULATION - Simulation Specifics" ) that : "For both the rise/fall time and I-V curve measurements, use "typical" process parameters." "For CMOS: min = min VCC, max temperature, typ process parameters --- max = max VCC, min temperature, typ process parameters" --- Later it says that " To account for process variation, decrease the current values taken at min conditions, increase the current values taken at max, and derate the rise and fall time values by the appropriate percentages. " This seems to be a roundabout way of doing it. Why can't we directly use "typ" , "min" , and "max" process parameters, as appropriate, directly in the simulations ? For example, if SPICE is used for simulation, we can have three different SPICE models for transistors, corresponding to the process-variation corners. Why should "typical" be used in each case ? Regards, Vipul K. Singhal Texas Instruments ----- End Included Message ----- From owner-ibis Wed Jul 16 12:46:04 1997 Received: from kaw.com ([206.155.177.89]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id MAA23049 for ; Wed, 16 Jul 1997 12:46:03 -0700 (PDT) Received: by kaw.com; id AA11371; Wed, 16 Jul 97 15:46:28 EDT Received: from audi.kaw.com(192.168.200.85) by explorer via smap (V3.1) id xma011369; Wed, 16 Jul 97 15:46:00 -0400 Received: from blazer.kaw.com (blazer [192.168.200.90]) by kaw.com (8.7.5/8.7.3) with SMTP id PAA00510; Wed, 18 Dec 1996 15:43:12 -0500 (EST) Received: by blazer.kaw.com (SMI-8.6/SMI-SVR4) id PAA00540; Wed, 18 Dec 1996 15:44:09 -0500 Date: Wed, 18 Dec 1996 15:44:09 -0500 From: dan@kaw.com (Dan Aleksandrowicz) Message-Id: <199612182044.PAA00540@blazer.kaw.com> To: jayd@vnet.ibm.com Subject: IBIS simulators Cc: ibis_users@vhdl.org X-Sun-Charset: US-ASCII Jay, As for standalone simulation tools/methodology I know you can do spice simulation using IBIS models using the Cadence tool SigExplore. This is a graphical interface that very useful for using before creating a new board database. And it can enable you to test different configurations and limitations of a net. Though SigExplore still has no direct interface from a front-end tool as like ViewLogic or Concept. I personaly use it for placement, however, the tool can standalone. I know that there are other good tools that can achieve this goal. Good luck Dan Aleksandrowicz Engineering Solutions Specialist Tel:(603)886 8711 email: dan@kaw.com http://www.kaw.com > From owner-ibis@server.vhdl.org Wed Dec 18 15:17 EST 1996 > Date: Wed, 16 Jul 97 13:43:23 EDT > From: "J. C. (Jay) Diepenbrock ((919)-543-8804)" > X-Addr: Interconnect Technology & Quality, B8UA/061/R118 > IBM Global Procurement > P. O. Box 12195 > Research Triangle Park, NC 27709 > To: ibis_users@vhdl.org > Subject: IBIS simulators > > Greetings all, > > After being away from the IBIS world for a while, I'm trying to get plugged > back into the current state of things. Can someone fill me in on what my > options are for what I would call standalone simulation? (By that I mean > simulation of board nets using IBIS models with the input from a schematic, > rather than a board layout database.) Meta-Software (now Avant!) had > originally planned to support IBIS, then backed away, but I don't know what > has happened since for those of us that want to do topology studies before > boards are designed. > > Thanks for your nominations for "simulator of the week" awards. > > Jay Diepenbrock > From owner-ibis Wed Jul 16 12:52:19 1997 Received: from mail11.digital.com (mail11.digital.com [192.208.46.10]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id MAA23074 for ; Wed, 16 Jul 1997 12:52:16 -0700 (PDT) Received: from us8rmc.bb.dec.com (us8rmc.bb.dec.com [16.53.0.44]) by mail11.digital.com (8.7.5/UNX 1.5/1.0/WV) with SMTP id PAA13719; Wed, 16 Jul 1997 15:42:53 -0400 (EDT) Received: from wrksys.enet by us8rmc.bb.dec.com (5.65/rmc-17Jan97) id AA24245; Wed, 16 Jul 97 15:39:23 -0400 Message-Id: <9707161939.AA24245@us8rmc.bb.dec.com> Received: from wrksys.enet; by us8rmc.enet; Wed, 16 Jul 97 15:42:52 EDT Date: Wed, 16 Jul 97 15:42:52 EDT From: Andy Ingraham To: jean-christophe_pautrat@hp-france-om5.om.hp.com Cc: ibis-users@vhdl.org, ingraham@wrksys.ENET.dec.com Apparently-To: ibis-users@vhdl.org, jean-christophe_pautrat@hp-france-om5.om.hp.com Subject: Re: voltage and temperature in corner cases > I'm trying to figure out how to tweak all the parameters to exercise > worst case simulations. ... In general, the driver has a much greater effect than the receiver; so I'd probably tailor the simulation parameters for the driver. I would expect (but don't know with certainty) that temperature has no effect whatsoever on IBIS models in a simulation. The [Temperature Range] keyword seems to be there only for documentation ... which is good because it's so often misused. The weak and strong parameters that are in the IBIS model, are already margined to the temperature extremes that the model designer chose to use. So if you were to do a simulation that had only IBIS (no SPICE) devices, varying the simulation temperature would be a no-op. That being the case, you can ignore it ... or set it as appropriate for your non-IBIS devices. The case with supply voltages is similar, but with a twist. Once again, the weak and strong IBIS models already have supply voltage figured into them, but only partly. Varying the supply voltage during simulation, will slide the high clamp and pullup curves up and down in direct proportion; but their shapes would not change. The shapes are already built into the weak, typical, and strong parameters; and simulators probably aren't going to "reverse engineer" the I/V curves to second-guess what they would have been, had the supply voltage been different. So ... while a strong model may have been CREATED using maximum supply voltage, it can be USED at any supply voltage. The results may not be 100% correct, but the curves will track Vdd as they should. For the driver, where you want the shapes of the curves (drive strengths) right, choose the supply voltage appropriately for the desired corner of the driver. Or do several simulations. Regards, Andy From owner-ibis Wed Jul 16 13:53:50 1997 Received: from ole.cdac.com (ole.cdac.com [199.5.216.26]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id NAA24013 for ; Wed, 16 Jul 1997 13:53:49 -0700 (PDT) Received: from ember.cdac.com (fwuser@cascade.cdac.com [199.5.216.206]) by ole.cdac.com (8.8.5/8.7.1) with ESMTP id NAA00799 for ; Wed, 16 Jul 1997 13:52:53 -0700 (PDT) Received: from quark.cdac.com (quark.cdac.com [10.0.10.112]) by ember.cdac.com (8.7.1/8.7.1) with ESMTP id NAA02885 for ; Wed, 16 Jul 1997 13:52:24 -0700 (PDT) From: Lynne Green Received: (from lgreen@localhost) by quark.cdac.com (8.7.1/8.7.1) id NAA18912 for ibis_users@vhdl.org; Wed, 16 Jul 1997 13:52:19 -0700 (PDT) Date: Wed, 16 Jul 1997 13:52:19 -0700 (PDT) Message-Id: <199707162052.NAA18912@quark.cdac.com> To: ibis_users@vhdl.org Subject: parasitic extractors I have had requests for parasitic extractors (L as well as R&C) for both multi-layer boards and ICs. Anyone have a company/university that they could suggest? Thanks, Lynne Green From owner-ibis Wed Jul 16 14:16:06 1997 Received: from scisysgw.sci.com (scisysgw.sci.com [143.116.116.253]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id OAA24355 for ; Wed, 16 Jul 1997 14:16:01 -0700 (PDT) From: Wray.Elliott@scismail.sci.com Received: from gcsnt.SCI.COM by scisysgw.sci.com with smtp (Smail3.1.28.1 #4) id m0woZZs-000AqjC; Wed, 16 Jul 97 13:17 CST Received: from scismail.sci.com ([143.116.24.32]) by gcsnt.SCI.COM (1.0.242) for ibis-users@vhdl.org; 16 Jul 1997 14:15:58 -0500 Message-ID: Date: 16 Jul 1997 14:15:58 -0500 Subject: which max/min model data for cor To: ibis-users@vhdl.org Cc: Wray.Elliott@scismail.sci.com MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="--MIME _=_ -2569-58ce-3a7c-" This is the preamble of a multipart MIME formatted message. If you are reading this text your mail system is most likely not capable of properly decoding MIME messages. To extract the contents of this message, save it to a file and then use an external MIME decoding utility. ----MIME _=_ -2569-58ce-3a7c- Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit ----MIME _=_ -2569-58ce-3a7c- Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit I am trying to determine the correct methodology for extracting data from IBIS models to simulate two corner cases: 1) flight time (slow/weak driver, max. receiver load) and 2) signal quality (fast/strong driver, min. receiver load). I would like to present the following table for review. ---begin parameters IBIS Model Parameter Values Used to Simulate Flight Time and Signal Quality Device Modeling Parameter Flight Time Signal Quality (Slow,Weak) (Fast, Strong) --------------------- ------------------ ----------- -------------- Input Buffer Cpkg Max Min Rpkg Max Min Lpkg Max Min Ccomp Max Min PowerClamp Max Min GroundClamp Max Min Output Buffer Ramp (dV/dt) Min Max PullUp Min Max PullDown Min Max PowerClamp Min Max GroundClamp Min Max Ccomp Max Min Lpkg Max Min Rpkg Max Min Cpkg Max Min Termination Rseries Max Min Rgnd Max Min Rpower Max Min Rac Max Min Cac Max Min Printed Circuit Board Zo Min Max S (ns/ft) Max Min Cvia Max Min Other Temperature Min Max Vcc Min Max References: Intel AP-481 "Designing with the Pentium Processor, ..." October 1993 I/O Buffer Information Specification (IBIS) Version 2.1, December 13, 1995 UniCAD UniSolve Course Notes "Modeling for ... Signal Integrity", January 1997 $Id: parameters,v 1.2 1997/07/16 18:26:34 welliott Exp welliott $ ---end parameters The following text from IBIS Specification Version 2.1 causes some confusion for me (in particular the [Power Clamp] and [Gnd Clamp] keywords): "For most [Model] keyword data, the "min" column describes slow, weak performance, and the "max" column describes the fast, strong performance." "The voltage and temperature keywords ... control the conditions which define the "typ", "min", and "max" column entries for all V/I table keywords [Pulldown], [Pullup], [Gnd Clamp], and [Power Clamp]; ..." My Four Questions: 1) For an IBIS output model, do the "min" [Power Clamp] and [Gnd Clamp] keyword column data entries represent the slow/weak driver condition? 2) For an IBIS input model, do the "max" [Power Clamp] and [Gnd Clamp] keyword column data entries represent the maximum receiver load condition? 3) For the IBIS input model, like the one listed below, do the "max" [Gnd Clamp] keyword data entries correspond to the supply voltage of 5.5 volts, as indicated in the [Voltage Range] keyword? ---begin edo.ibs (portion) | [Model] INPUT Model_type Input Vinl = 0.8 Vinh = 2.4 | |Variable typ min max C_comp 1.5p 0.82p 2.99p | |Variable typ min max [Voltage range] 5.0 4.5 5.5 | [GND_clamp] |Volts typ min max -5.00 -127.0m -115.6m -140.4m -4.00 -97.6m -88.3m -108.2m -3.00 -65.8m -59.2m -73.5m -2.00 -34.2m -30.8m -38.3m -1.00 -5.78m -5.77m -5.92m -0.800 -1.899m -2.17m -1.72m -0.600 -0.714m -0.290m -0.465m -0.400 -0.006m -0.0200m 0 -0.200 0 0 0 5 0 0 0 10 0 0 0 | ---end edo.ibs (portion) 4) Is there a simulation methodology problem running a flight time simulation using IBIS model data for the driver corresponding to Vcc = 4.5 volts and the IBIS model data for the receiver corresponding to Vcc = 5.5 volts? Thanks, Wray Elliott, Engineer wray.elliott@scismail.sci.com SCI Systems, Inc. MS/342 (205) 882-4107 Extension 3855 13000 S. Memorial Parkway Huntsville, Alabama 35803 ----MIME _=_ -2569-58ce-3a7c--- From owner-ibis Wed Jul 16 14:53:39 1997 Received: from relayhost.vlsi.com (tweety.vlsi.com [134.27.20.23]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id OAA24773 for ; Wed, 16 Jul 1997 14:53:38 -0700 (PDT) Received: from relayhost.tempe.vlsi.com (anubis.tempe.vlsi.com [134.27.128.1]) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) with ESMTP id QAA02167 for ; Wed, 16 Jul 1997 16:15:59 -0700 Received: from mailserver.tempe.vlsi.com (mailserver.tempe.vlsi.com [134.27.128.5]) by relayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/101195) with ESMTP id OAA01974 for ; Wed, 16 Jul 1997 14:52:02 -0700 Received: from witsend ([134.27.133.12]) by mailserver.tempe.vlsi.com (Netscape Mail Server v2.02) with SMTP id AAA4600; Wed, 16 Jul 1997 14:52:01 -0700 Sender: dc.sessions@tempe.vlsi.com (D.C. Sessions) Message-ID: <33CD4281.2F0F@tempe.vlsi.com> Date: Wed, 16 Jul 1997 14:52:01 -0700 From: "D. C. Sessions" Organization: VLSI Technology Inc. X-Mailer: Mozilla 3.0Gold (X11; I; SunOS 5.5.1 sun4m) MIME-Version: 1.0 To: Lynne Green CC: ibis_users@vhdl.org Subject: Re: parasitic extractors References: <199707162052.NAA18912@quark.cdac.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lynne Green wrote: > > I have had requests for parasitic extractors (L as well as R&C) > for both multi-layer boards and ICs. > > Anyone have a company/university that they could suggest? Funny you should ask. I was researching this exact point at DAC. Currently the list includes Ansoft, Lucent, and Viewlogic. More (maybe) shortly. -- D. C. Sessions dc.sessions@tempe.vlsi.com From owner-ibis Thu Jul 17 08:53:56 1997 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id IAA10780 for ; Thu, 17 Jul 1997 08:53:51 -0700 (PDT) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id IAA17785; Thu, 17 Jul 1997 08:51:52 -0700 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (3.2) id xma017709; Thu, 17 Jul 97 08:51:47 -0700 Received: from lightning.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA23741 for ibis_users@vhdl.org; Thu, 17 Jul 97 08:52:22 -0700 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA26996; Thu, 17 Jul 97 08:52:48 PDT Date: Thu, 17 Jul 97 08:52:48 PDT From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9707171552.AA26996@rockie.nsc.com> To: ibis_users@vhdl.org, lgreen@cdac.com Subject: Re: parasitic extractors Hi, You may also try www.optem.com OptEM Engineering Inc 100 Discovery Place One 3553-31 Street N.W Calgary, Canada T2L 2K7 (403)289-0499 Fax(403)282-1238 Regards, Syed National Semiconductor Corp. > From owner-ibis@server.vhdl.org Wed Jul 16 14:58:57 1997 > From: Lynne Green > Date: Wed, 16 Jul 1997 13:52:19 -0700 (PDT) > To: ibis_users@vhdl.org > Subject: parasitic extractors > > I have had requests for parasitic extractors (L as well as R&C) > for both multi-layer boards and ICs. > > Anyone have a company/university that they could suggest? > > Thanks, > Lynne Green > From owner-ibis Thu Jul 17 10:40:06 1997 Received: from tower.ti.com (tower.ti.com [192.94.94.5]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA12713 for ; Thu, 17 Jul 1997 10:40:05 -0700 (PDT) Received: from happy.memh.ti.com ([158.218.36.100]) by tower.ti.com (8.8.5) with ESMTP id MAA19179 for ; Thu, 17 Jul 1997 12:38:22 -0500 (CDT) Received: from r2d2.memh.ti.com by happy.memh.ti.com with ESMTP (1.37.109.16/16.2) id AA125951107; Thu, 17 Jul 1997 12:38:27 -0500 Received: from r2d2 (localhost [127.0.0.1]) by r2d2.memh.ti.com with SMTP (8.7.1/8.7.1) id MAA22359 for ; Thu, 17 Jul 1997 12:38:02 -0500 (CDT) Sender: vchang@memh.ti.com Message-Id: <33CE5879.73C9@memh.ti.com> Date: Thu, 17 Jul 1997 12:38:01 -0500 From: Vincent Chang X-Mailer: Mozilla 3.01Gold (X11; U; HP-UX B.10.20 9000/780) Mime-Version: 1.0 To: ibis_users@vhdl.org Subject: RLC Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit all, I am not quite understand what RLC_pkg is. Please help. What is the RLC_pkg? Is it the values from the Lead frame? How to measure the RLC's min,max values in Lead Frame? -- Best Regards, Vincent Chang ======================================================================= * Vincent Chang TI MSG ID: hui8 * * Design Automation mailto:vchang@memh.ti.com * * Memory Products Design http://www.memh.ti.com/~mcad * * Texas Instruments Inc. MS 657 Phone: (281) 274-3167 * * PO Box 1443, Houston, TX 77251 Fax: (281) 274-2067 * ======================================================================= From owner-ibis Thu Jul 17 10:45:20 1997 Received: from montana.nwlink.com (kellee@montana.nwlink.com [199.242.23.13]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA12885 for ; Thu, 17 Jul 1997 10:45:19 -0700 (PDT) Received: (from kellee@localhost) by montana.nwlink.com (8.8.5/8.8.5) id KAA19880; Thu, 17 Jul 1997 10:44:05 -0700 (PDT) Message-Id: <3.0.32.19970717104416.006ec4cc@mail.nwlink.com> X-Sender: kellee@mail.nwlink.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Thu, 17 Jul 1997 10:44:17 -0700 To: Lynne Green From: Kellee Crisafulli Subject: Re: parasitic extractors Cc: ibis_users@vhdl.org Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Hi Lynne, >you wrote: >> >> I have had requests for parasitic extractors (L as well as R&C) >> for both multi-layer boards and ICs. >> >> Anyone have a company/university that they could suggest? HyperLynx has several types of parasitic extractors including single line full board, and 2d field solvers. Please add us to the list (www.hyperlynx.com) PC platform (WindowsNT, Windows95) only. ------------------------------------------------------------------------- Have a great day... Kellee Crisafulli at HyperLynx kellee@hyperlynx.com http://www.hyperlynx.com ------------------------------------------------------------------------- From owner-ibis Thu Jul 17 14:20:43 1997 Received: from VNET.IBM.COM (vnet.ibm.com [204.146.168.194]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id OAA00796 for ; Thu, 17 Jul 1997 14:20:40 -0700 (PDT) Message-Id: <199707172120.OAA00796@server.vhdl.org> Received: from RALVM29 by VNET.IBM.COM (IBM VM SMTP V2R3) with BSMTP id 2356; Thu, 17 Jul 97 17:19:29 EDT Date: Thu, 17 Jul 97 17:17:15 EDT From: "J. C. (Jay) Diepenbrock ((919)-543-8804)" X-Addr: Interconnect Technology & Quality, B8UA/061/R118 IBM Global Procurement P. O. Box 12195 Research Triangle Park, NC 27709 To: ibis-users@vhdl.org Subject: IBIS simulators Greetings all, Thanks for the many responses to my query about the above. I'll follow up with the various folks shortly. Jay Diepenbrock (whew!) From owner-ibis Thu Jul 17 16:56:27 1997 Received: from procyon.pmc-sierra.bc.ca (procyon.pmc-sierra.bc.ca [134.87.115.1]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA01296 for ; Thu, 17 Jul 1997 16:56:25 -0700 (PDT) Received: from nt-server1.pmc-sierra.bc.ca (nt-server1.pmc-sierra.bc.ca [134.87.116.185]) by procyon.pmc-sierra.bc.ca (8.7.5/8.7.3) with SMTP id QAA09187 for ; Thu, 17 Jul 1997 16:55:14 -0700 (PDT) Received: by nt-server1.pmc-sierra.bc.ca with SMTP (Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63) id <01BC92D2.4BB28770@nt-server1.pmc-sierra.bc.ca>; Thu, 17 Jul 1997 16:55:57 -0700 Message-ID: From: Roland Chang To: "'ibis-users@vhdl.org'" Subject: slight bug in s2ibis2? Date: Thu, 17 Jul 1997 16:55:55 -0700 X-Mailer: Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Has anyone ever noticed in the s2ibis2 program that the ibis files that it creates sometimes leaves a space between a number and its scaling modifier? ie: (the space after the -0.2692 below) I am using s2ibis2 v1.1 on unix, with the fix incorporated for 4 decimal place accuracy. dV/dt_r 0.3586/0.4005n 1.2744u/-0.2692 p 0.5416/0.5104n dV/dt_f 0.6660/0.5058n 0.4140/0.7960n 0.8880/0.4919n thanx ****************************************** Roland Chang ext. 2647 PMC-Sierra Applications Department 105-8555 Baxter Place Burnaby, BC V5A 4V7 Tel: (604) 415-6000 email: chang@pmc-sierra.bc.ca ****************************************** From owner-ibis Fri Jul 18 11:16:06 1997 Received: from kaw.com ([206.155.177.89]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id LAA05943 for ; Fri, 18 Jul 1997 11:16:05 -0700 (PDT) Received: by kaw.com; id AA16816; Fri, 18 Jul 97 14:16:38 EDT Received: from audi.kaw.com(192.168.200.85) by explorer via smap (V3.1) id xma016814; Fri, 18 Jul 97 14:16:28 -0400 Received: from blazer.kaw.com (blazer [192.168.200.90]) by kaw.com (8.7.5/8.7.3) with SMTP id OAA06699 for ; Fri, 20 Dec 1996 14:14:16 -0500 (EST) Received: by blazer.kaw.com (SMI-8.6/SMI-SVR4) id OAA01014; Fri, 20 Dec 1996 14:14:16 -0500 Date: Fri, 20 Dec 1996 14:14:16 -0500 From: dan@kaw.com (Dan Aleksandrowicz) Message-Id: <199612201914.OAA01014@blazer.kaw.com> To: ibis_users@vhdl.org Subject: Diff. pair modeling X-Sun-Charset: US-ASCII Hello all, I am looking for a clear definition to the method of simulating a diff. pair. My main question is: When simulating the DC sweep of the "true" pin, should I ground the other pin? Thanks Dan Aleksandrowicz Engineering Solutions KAW/USA 39 Simon Street Nashua, NH 03060 http://www.kaw.com From owner-ibis Tue Jul 22 13:40:39 1997 Received: from dfw-ix4.ix.netcom.com (dfw-ix4.ix.netcom.com [206.214.98.4]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id NAA02968 for ; Tue, 22 Jul 1997 13:40:38 -0700 (PDT) Received: (from smap@localhost) by dfw-ix4.ix.netcom.com (8.8.4/8.8.4) id PAA06932; Tue, 22 Jul 1997 15:38:21 -0500 (CDT) Received: from sjx-ca74-35.ix.netcom.com(207.93.129.163) by dfw-ix4.ix.netcom.com via smap (V1.3) id smab22172; Tue Jul 22 14:25:00 1997 Message-Id: <3.0.32.19970722113355.007012b4@popd.ix.netcom.com> X-Sender: bogatina@popd.ix.netcom.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Tue, 22 Jul 1997 12:29:00 -0700 To: Lynne Green From: Eric Bogatin Subject: Re: parasitic extractors Cc: ibis_users@vhdl.org Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Lynne and others interested in parasitic extraction tools, Ansoft has a complete suite of parasitic extraction tools that includes 2D (great for board stackups), 3D for packages, connectors and passives and 3D full wave for either very high bandwidth models or EMI simulations. Our 3D tools create a package model that includes all the mutual inductance and coupling capacitance between leads. I would be happy to send more info to anyone who is interested. Please contact me off line. --eric bogatin At 01:52 PM 7/16/97 -0700, Lynne Green wrote: >I have had requests for parasitic extractors (L as well as R&C) >for both multi-layer boards and ICs. > >Anyone have a company/university that they could suggest? > >Thanks, >Lynne Green > > ********************************************************************** Eric Bogatin Product Manager, Signal Integrity Products Ansoft Corporation 4675 Stevens Creek Blvd Suite 208 Santa Clara CA 95051-6374 voice: 408-261-9095 x13 fax: 408-261-1245 email: bogatin@ansoft.com pager: 888-775-1138 "In God we trust, all others, show your data" ********************************************************************** From owner-ibis Wed Jul 23 09:17:47 1997 Received: from motgate.mot.com (motgate.mot.com [129.188.136.100]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id JAA20921 for ; Wed, 23 Jul 1997 09:17:45 -0700 (PDT) Received: from mothost.mot.com (mothost.mot.com [129.188.137.101]) by motgate.mot.com (8.8.5/8.6.10/MOT-3.8) with ESMTP id LAA10898 for ; Wed, 23 Jul 1997 11:16:30 -0500 (CDT) Comments: ( Received on motgate.mot.com from client mothost.mot.com, sender timmc@ecad2.corp.mot.com ) Received: from ecad2.corp.mot.com (ECAD2.corp.mot.com [199.2.141.202]) by mothost.mot.com (8.8.5/8.6.10/MOT-3.8) with ESMTP id LAA04703 for ; Wed, 23 Jul 1997 11:16:28 -0500 (CDT) Message-Id: <199707231616.LAA04703@mothost.mot.com> Received: by ecad2.corp.mot.com (1.39.111.2/16.2) id AA167272763; Wed, 23 Jul 1997 10:46:03 -0500 From: Tim McKinney Subject: rise & fall waveforms To: ibis-users@vhdl.org Date: Wed, 23 Jul 1997 10:46:03 CDT X-Mailer: Elm [revision: 111.1] My question is about rising and falling waveforms. In order to generate these curves with s2ibis2, you have to specify certain parameters for the test fixture. This makes it relevent to that specific fixture. So, should these curves be generated only when making actual measurements to produce an IBIS model, or should I generate them using s2ibis2 ? If I should generate them with the automatic conversion, what is a common fixture resistance? Tim Mcinney ecad2@corp.mot.com From owner-ibis Wed Jul 23 19:34:38 1997 Received: from mail13.digital.com (mail13.digital.com [192.208.46.30]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id TAA01429 for ; Wed, 23 Jul 1997 19:34:37 -0700 (PDT) Received: from us8rmc.bb.dec.com (us8rmc.bb.dec.com [16.53.0.44]) by mail13.digital.com (8.7.5/UNX 1.5/1.0/WV) with SMTP id WAA30477; Wed, 23 Jul 1997 22:26:47 -0400 (EDT) Received: from wrksys.enet by us8rmc.bb.dec.com (5.65/rmc-17Jan97) id AA11221; Wed, 23 Jul 97 22:25:00 -0400 Message-Id: <9707240225.AA11221@us8rmc.bb.dec.com> Received: from wrksys.enet; by us8rmc.enet; Wed, 23 Jul 97 22:26:46 EDT Date: Wed, 23 Jul 97 22:26:46 EDT From: Andy Ingraham To: timmc@ecad2.corp.mot.com Cc: ibis-users@vhdl.org, ingraham@wrksys.ENET.dec.com Apparently-To: ibis-users@vhdl.org, timmc@ecad2.corp.mot.com Subject: Re: rise & fall waveforms > My question is about rising and falling waveforms. > In order to generate these curves with s2ibis2, you have to specify > certain parameters for the test fixture. This makes it relevent to > that specific fixture. So, should these curves be generated > only when making actual measurements to produce an IBIS model, > or should I generate them using s2ibis2 ? They are meaningful whether generated by SPICE or measured data. Test fixture = test load (applied to the SPICE model, or to the real DUT via test fixtures.) > If I should generate them with the automatic conversion, > what is a common fixture resistance? For ordinary TTL/CMOS outputs, try 50 or 100 ohms to GND (for rising) and to POWER (for falling). Also a few other resistances, up to 1000 ohms or so. Do the same when you generate measured data. Regards, Andy From owner-ibis Thu Jul 24 15:23:22 1997 Received: from monsoon.dial.pipex.net (monsoon.dial.pipex.net [158.43.128.69]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id PAA19166 for ; Thu, 24 Jul 1997 15:23:21 -0700 (PDT) Received: (qmail 29556 invoked from network); 24 Jul 1997 22:22:10 -0000 Received: from ad065.du.pipex.com (HELO henty) (193.130.243.65) by smtp.dial.pipex.com with SMTP; 24 Jul 1997 22:22:10 -0000 Message-ID: <33D7D59A.3803739@quantic-emc.com> Date: Thu, 24 Jul 1997 23:22:18 +0100 From: Mike Ventham Organization: Quantic EMC Inc X-Mailer: Mozilla 4.01 [en] (WinNT; I) MIME-Version: 1.0 To: "J. C. (Jay) Diepenbrock ((919)-543-8804)" CC: ibis-users@vhdl.org Subject: Re: IBIS simulators X-Priority: 3 (Normal) References: <199707172120.OAA00796@server.vhdl.org> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit J. C. (Jay) Diepenbrock ((919)-543-8804) wrote: > > Greetings all, > > Thanks for the many responses to my query about the above. I'll > follow up > with the various folks shortly. > > Jay Diepenbrock > (whew!) Jay, I hope it is not too late to get our name on your list. We have been working in parasitic extraction since 1983 and have had a pre-layout simulator since 1985 allowing pre layout simulation. You can include IBIS models after running them through our Interface/Modellor Phidias to produce a behavioural model (I agree with Fred!). We also have board layout screener tools for both signal integrity and EMC problems, as well as full enclosure/boards/cables EMC analysis capability, not to mention 2D and 3D transmission line/parasitic extraction tools. -- Regards Mike ________________________________________________________________ | Mike Ventham - Vice-President Engineering, | | Quantic EMC Inc Headquarters | | Croft House, Chilcompton, 191 Lombard Ave, Winnipeg, | | Somerset, UK, BA3 4JA Manitoba, Canada R3B 0X1 | | Tel: 44 (0)1761 232191 Tel: (204) 942 4000 | | Fax: 44(0)1761 233549 Fax: (204) 957 1158 | | Email: ventham@quantic-emc.com http://www.quantic-emc.com | From owner-ibis Fri Jul 25 04:38:34 1997 Received: from pilgrim.cisco.com (pilgrim.cisco.com [171.69.204.12]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id EAA00252 for ; Fri, 25 Jul 1997 04:38:34 -0700 (PDT) Received: from twarneke-sun (twarneke-sun.cisco.com [171.69.208.231]) by pilgrim.cisco.com (8.8.5-Cisco.1/8.6.5) with SMTP id HAA29257; Fri, 25 Jul 1997 07:36:53 -0400 (EDT) Sender: twarneke@cisco.com Message-ID: <33D88FD4.2F1E@cisco.com> Date: Fri, 25 Jul 1997 07:36:52 -0400 From: Tom Warneke X-Mailer: Mozilla 3.0GoldC-CISCOENG (X11; I; SunOS 5.5.1 sun4u) MIME-Version: 1.0 To: "J. C. (Jay) Diepenbrock ((919)-543-8804)" CC: ibis_users@vhdl.org Subject: Re: IBIS simulators References: <199707161750.KAA21357@server.vhdl.org> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Jay, Anyone looking for easy to use, accurate and cost effective signal integrity analysis should look at the Hyperlynx products. Their LinSim product provides prelayout analysis for evaluating stack-up, termination strategies, and determining design rules. They support IBIS as well as their own unique modeling description. Take a look at their www site: http://www.hyperlynx.com for details. Good luck... Tom J. C. (Jay) Diepenbrock ((919)-543-8804) wrote: > > Greetings all, > > After being away from the IBIS world for a while, I'm trying to get plugged > back into the current state of things. Can someone fill me in on what my > options are for what I would call standalone simulation? (By that I mean > simulation of board nets using IBIS models with the input from a schematic, > rather than a board layout database.) Meta-Software (now Avant!) had > originally planned to support IBIS, then backed away, but I don't know what > has happened since for those of us that want to do topology studies before > boards are designed. > > Thanks for your nominations for "simulator of the week" awards. > > Jay Diepenbrock From owner-ibis Fri Jul 25 14:39:55 1997 Received: from gatekeep.ti.com (gatekeep.ti.com [192.94.94.61]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id OAA11492 for ; Fri, 25 Jul 1997 14:39:55 -0700 (PDT) Received: from happy.memh.ti.com ([158.218.36.100]) by gatekeep.ti.com (8.8.5) with ESMTP id QAA01169 for ; Fri, 25 Jul 1997 16:38:35 -0500 (CDT) Received: from r2d2.memh.ti.com by happy.memh.ti.com with ESMTP (1.37.109.16/16.2) id AA239196695; Fri, 25 Jul 1997 16:38:15 -0500 Received: from r2d2 (localhost [127.0.0.1]) by r2d2.memh.ti.com with SMTP (8.7.1/8.7.1) id QAA21144 for ; Fri, 25 Jul 1997 16:37:46 -0500 (CDT) Sender: vchang@memh.ti.com Message-Id: <33D91CA9.4D4C@memh.ti.com> Date: Fri, 25 Jul 1997 16:37:45 -0500 From: Vincent Chang X-Mailer: Mozilla 3.01Gold (X11; U; HP-UX B.10.20 9000/780) Mime-Version: 1.0 To: ibis-users@vhdl.org Subject: RLC Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit all, I am not quite understand the definition of RLC packages and how to obtain the max & min values for RLC packages. Please help me to clarify the questions that I had. -- Best Regards, Vincent Chang ======================================================================= * Vincent Chang TI MSG ID: hui8 * * Design Automation mailto:vchang@memh.ti.com * * Memory Products Design http://www.memh.ti.com/~mcad * * Texas Instruments Inc. MS 657 Phone: (281) 274-3167 * * PO Box 1443, Houston, TX 77251 Fax: (281) 274-2067 * ======================================================================= From owner-ibis Fri Jul 25 16:07:02 1997 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id QAA13083 for ; Fri, 25 Jul 1997 16:07:01 -0700 (PDT) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id QAA19872; Fri, 25 Jul 1997 16:04:31 -0700 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (3.2) id xma019621; Fri, 25 Jul 97 16:04:13 -0700 Received: from lightning.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA07501 for ; Fri, 25 Jul 97 15:38:22 -0700 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA29703; Fri, 25 Jul 97 15:38:48 PDT Date: Fri, 25 Jul 97 15:38:48 PDT From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9707252238.AA29703@rockie.nsc.com> To: ibis-users@vhdl.org, vchang@memh.ti.com Subject: Re: RLC Vincent, R_pkg, L_pkg and C_pkg are the default values of the resitance, inductance and capacitance of the package. If the values for individual pins are available, they should be specified under R_pin, L_pin and C_pin. These per pin values overrides the _pkg values. You can look at the distribution of resistance for the entire package and that should tell you what the min and max values are. Same applies for inductance and capacitance. Regards, Syed National Semiconductor Corp. > From owner-ibis@server.vhdl.org Fri Jul 25 15:32:32 1997 > Sender: vchang@memh.ti.com > Date: Fri, 25 Jul 1997 16:37:45 -0500 > From: Vincent Chang > X-Mailer: Mozilla 3.01Gold (X11; U; HP-UX B.10.20 9000/780) > To: ibis-users@vhdl.org > Subject: RLC > Content-Type> : > text/plain> ; > charset=us-ascii> > Content-Transfer-Encoding: 7bit > > all, > > I am not quite understand the definition of RLC packages > and how to obtain the max & min values for RLC packages. > Please help me to clarify the questions that I had. > > > -- > Best Regards, > > Vincent Chang > > > ======================================================================= > * Vincent Chang TI MSG ID: hui8 * > * Design Automation mailto:vchang@memh.ti.com * > * Memory Products Design http://www.memh.ti.com/~mcad * > * Texas Instruments Inc. MS 657 Phone: (281) 274-3167 * > * PO Box 1443, Houston, TX 77251 Fax: (281) 274-2067 * > ======================================================================= >