From owner-ibis  Mon Jun  2 10:49:13 1997
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From: scotts@actel.com (Scott Schlachter)
Message-Id: <9706021750.AA16843@ricky.sun_net>
To: chang@nexen.com, ibis-users@vhdl.org, ibis@vhdl.org
Subject: Re: Verifying IBIS models
Cc: jem@ricky.actel.com

Hi Luke,
My oppinions here are my own, and not necessarily those of my company.
I missed this when you first posted, but I feel compelled to input
my oppinion on this.  There has been discussion on the ibis reflector 
in the past regarding the accuracy of SPICE models, particularly in
the diode voltage regions.  For HSPICE in particular, we concluded
that the only way to provide a "non-ideal" set of clamping 
diodes (for CMOS), the transistors' inherent diodes needed to
be shut down (set IS=0, AD=0, and AS=0, I believe), and a descrete 
set of diodes placed on the drains of the transistors.  This problem
had something to do with the fact that there was no way to model 
the bulk resistance (the majority of the resistance that the 
inherent diodes should have experienced) without increasing 
channel resistance.  The reason that I am even bringing this up 
here, is that I wanted to provide at least one example of a 
potential source of innacuracy of a *very* commonly used
version of SPICE.  

We (painstakingly) developed our first IBIS model from a SPICE 
netlist, by attempting to add *all* possible parasitic components 
that we knew would exist in our actual silicon layout (resistance 
and capacitances in our metal interconnects, etc.).  We discovered
the above mentioned problem during this process, and sought
advice throught this email reflector.  What we found was that while
a few companies that were participating on the reflector knew about
and addressed this particular problem, there were definitely others 
that didn't. How well can you trust a vendors SPICE based IBIS model 
that you downloaded off the web?  Not to sound too harsh, but roll 
the dice. 

Our hope was to produce a IBIS model based on silicon measurments, 
and then check to see how accurately the SPICE versions corellated.  
If they matched well, we knew that we would have a very usefull method 
of providing an IBIS model file to our customers, potentially
even before we had silicon available.  In addition, we wanted
to be able to rely on the ramp data generated from the SPICE
models, because we knew that this data would be extremely hard
to extract from the Lab (on a packaged part, you have the 
package parasitics effecting the ramp; on an unpackaged 
die, you have parasitics added by the probe leads, etc.).

What we found after doing our lab measurements, was that there
was pretty good corellation between GND and VCC, but guess what?
The diode regions were close, but still had some discrepencies
(mostly around the knees).

This, in my oppinion, is the ultimate test that you are asking for.
However, when a vendor does this, they (like us) aren't going to 
bother releasing the SPICE based IBIS model - why should they, when
they now have (the more accurate) silicon measurement based version
that they can release instead?  I'm not saying that SPICED based
versions are untrustworthy; undoubtably there are some vendors that 
have developed extremely accurate SPICE models, even to the extent that
they may have done all sorts of tricks so as to accurate model their
netlists in the Voltage areas that are not traditionally dwelled in 
for development verification (more than a volt or 2 above VCC or below 
GND).  But a behavioral model can only be as accurate as the thing
that it's supposed to be behaving.  If that "thing" is a SPICE 
netlist...  I have just pointed out what I believe to be one definite 
shortcomming in one of the more popular SPICE versions out there. 
However, I also pointed out an unofficial workaround that *some* vendors 
are aware of.  I'll let you draw your own conclusions.

A last oppinion that I would like to make is this:  I personally 
think that SPICED based IBIS model files should only be used as
a last resort.  The case where SPICE models for a new process
are available, but the packaged silicon is not yet available,
might be a good example - you might be interested in a chip 
vendors product even before it has hit the market, and this provides
a way for you to initially simulate it's behavior on the new
board that you are designing, now - before it can even be purchased.  
Otherwise, why bother?  I am interested in hearing other vendors
response to this.  My conclusion was that extracting the data 
in the lab was 10x easier that struggling with trying to get the
SPICE netlist to be as accurate as possible; and, the lab data
is the "real thing" anyhow.  Consequently, lab data can be screwed-up
too, so ultimately you will need to either quiz the heck out of
the vendor who created the model file as to their methodology
(if they didn't describe it in total minute detail within the comments
of their IBIS model files), or you will just have to trust them...

-Scott Schlachter	Design Engineering
 scotts@actel.com	Actel Corporation
			Sunnyvale, CA

> From owner-ibis@server.vhdl.org Fri May 30 15:21:20 1997
> Luke Chang wrote:
> 
> > When IC vendors create IBIS models for their components, how do they
> > verify whether they are correct or not, compared to either the original
> > SPICE models or to physical measurement data?  Do they actually do this
> > comparison?  Is there a simulation methodology to do this comparison?
> > 
> > I am just a user of IBIS models and will never create them.  So I am
> > mainly interested in knowing whether I can always (blindly) trust the
> > models I get from the vendor Web sites or directly from the vendors.
> 
> I suppose the usual disclaimers (I can't, strictly speaking,
> speak for VLSI, much less other manufacturers) are in order.
> That said, here's a little about our approach:
> 
> 1) We SPICE the dickens out of I/O designs.
> 2) We verify the SPICE characteristics in design
>    validation and test against them.
> 3) We generate IBIS models from the SPICE models.
> 4) We spot-compare SPICE simulations made from
>    hand-translating IBIS back to SPICE.
> 
> We're in the process of converting the canonical
> model for testing purposes from old-fashioned data
> sheets to IBIS.  We *intensely* wish we had a
> working IBIS-to-SPICE translator that we could use
> for closing the loop, but at present there don't
> seem to be any around.
> 
> -- 
> D. C. Sessions
> dc.sessions@tempe.vlsi.com
> 
 
From owner-ibis  Tue Jun  3 04:45:28 1997
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From: "Mellitz, Richard" <mellitz@xgate.columbiasc.ncr.com>
To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>
Subject: RE: SPICE Convergence Tricks - Consequences?
Date: Tue, 3 Jun 1997 07:44:14 -0400
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Encoding: 70 TEXT

FWIW: The following HSpice options is where I start from.

.options interp reltol=0.0001 post=2 probe ingold=2 vntol=0.1u
+ lvltim=1 chgtol=0.01f brief nomod notop noelck nolist

As colleague of say "Its sort of like 'sour dough starter'"

Nothing seems to work "every time" for me. I usually have to twiddle
around based on the what was done at the transistor level models.  The
toughest ones are the "sanitized spice" models.  Many just do not work
accurately at DC.


... Rich Mellitz, NCR Corp
>----------
>From: 	Roland James Chang[SMTP:roland@sfu.ca]
>Sent: 	Tuesday, May 20, 1997 4:02 PM
>To: 	ibis-users@vhdl.org
>Subject: 	SPICE Convergence Tricks - Consequences?
>
>
>Once again, a big thanks to all who replied to my last question. :-)
>I've been using several tricks to try to solve SPICE convergence
>problems:
>
>-adding a 0.001ohm resistor in seris with the stimulating source
>-increasing the value of the ITL1 to 300-500. (more iterations allowed)
>-relaxing ABSTOL
>-decreasing the sweep of the stimulus (I couldn't quite get this one to
>work)
>
>Many people mentioned that convergence problems are quite common, I would
>like to know how common are they?
>
>Furthermore, I am curious if anyone has a convergence fix that works
>everytime, as it seems tedious to try to get things to converge everytime
>just by trial and error fixes.
>
>Also, what kinds of side-effects, or problems (in terms of IBIS
>modelling) have people encountered by forcing the analysis to converge via
>fancy SPICE tricks?
>
>One last question regards clarification about typ, min, and max
>curves.  When one is generating curves for the typical case,
>suppose the typical case passes but both the min and max fail, the columns
>should read NA for min and max right? Now should I go back and try to
>tweak the min and max to converge? OR are some curves meant to only work
>for the typical case? 
>
>
>Many thanks in advance,
>Regards,
>
>roland
>
>*************************************************************************
>*Roland Chang                          | email: roland@sfu.ca           *
>*Simon Fraser University               |        OR                      *
>*School of Engineering Science         |        chang@pmc-sierra.bc.ca  *
>*3rd year Computer Engineering Option  |                                *
>*************************************************************************
>
>
>
>
>
>
>
>

 
From owner-ibis  Wed Jun  4 04:19:44 1997
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Hello,

I need some help about Ibis Models.

I want to change PSice models into ibis models. 

Where can I get s2ibis for windows? And is there an instruction
included?
Or is there a possibility to take the output of a PSpice simulation and
read it into the s2ibis on a workstation?
 
From owner-ibis  Wed Jun  4 06:33:15 1997
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From: Tim McKinney <timmc@ecad2.corp.mot.com>
Subject: man pages
To: ibis-users@vhdl.orgsend, the@ecad2.corp.mot.com,
        message@ecad2.corp.mot.com, to:@ecad2.corp.mot.com,
        ibis-users@vhdl.org
Date: Wed, 04 Jun 1997 8:27:16 CDT
X-Mailer: Elm [revision: 111.1]

I have some questions about the s2ibis2 v1.1 conversion program.  First of all I
am new to IBIS, and am running into a few difficulties.  So far I have not been
able to successfully run the example files. I am encountering problems with dc
sweep convergence.  I read on a webpage to use the *[Iterate] switch, explained
in the man pages.  I haven't been able to find the man pages,
I was hoping someone could point me in the right direction.  I need to run the
s2ibis2 program with a previously generated hspice output in order to avoid the
dc convergence problems.  This is what the switch is for.
I also have the new s2iutil.c file which is suppossed to generate the data
with four decimal places.  It stated to replace the old file with the new one,
and simply recompile using
        make depend
        make <systype>
This is what I did using "make hpux", but received numerous errors.  Maybe
someone has an idea on how that is actually done.
I hope someone can offer some assistance.
I would also like to know where I can download the latest version of s2ibis2 
I was told it is v1.3
                Please reply directly to
                        timmc@ecad2.corp.mot.com


                                Thank you,
                                	Tim Mckinney
 
From owner-ibis  Wed Jun  4 08:28:29 1997
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From owner-ibis  Wed Jun  4 17:13:09 1997
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Date: Wed, 4 Jun 97 17:15:49 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9706050015.AA22691@rockie.nsc.com>
To: ibis@vhdl.org, ibis-users@vhdl.org
Subject: IBIS model download URL update - National
Cc: huq@rockie.nsc.com

IBISfans,

If you have bookmarked the National IBIS site, you need to 
update the URL. The new URL is:

	http://www.national.com/models

Previous link will send you to an old site. Sorry for this
inconvinience.

Regards,
Syed
National Semiconductor Corp.
 
From owner-ibis  Thu Jun  5 14:37:21 1997
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From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>,
        "'ibis-info@vhdl.org'"
	 <ibis-info@vhdl.org>
Subject: Help with s2ibis2 utility: pullups on input pins, bidirectional pin modelling, etc.
Date: Thu, 5 Jun 1997 14:36:53 -0700
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Hello, I have been toying around with IBIS for several weeks now, and am
starting to feel a little bit more comfortable with it, but I am still
new to it, and there are still many questions that I have.

I asked the IBIS mail list previously about pullup input pins, and the
following response
made me wonder more about exactly how to  model input pins with pull-up
mechanisms.

> 1.	Inputs with pull-up resistors?
> Are these treated in any special way? (ie: different than that of a 
> normal input pin?)

>>For general IBIS modeling purposes, I think not.  If the pull-up
>>resistors are a permanent part of the input structure (not switchable
>>on and off on-the-fly), then they just become a part of the [GND Clamp]
>>and [POWER Clamp] V/I curves.

>> Pullup resistors would appear in the Clamps.  They are not separated
>> out.  So there is probable that they will be double counted.
>> For Pullups, the contribution in the [Gnd Clamp] table should be
>> should be subtracted.  The [Power Clamp] table should be extended to
>> from 0 to Vcc (and possibly linearly extrapolated to 2Vcc) to provide
>> the separate Pullup resistor component.

>>> How about in S2ibis2 utility?  When S2ibis2 generates the tables=20
>>> automatically, are you saying that the tables will be incorrect for=20
>>> inputs with pull-ups on the input?  Does this mean that I would have=20
>>> to manually change the IBIS file after the s2ibis2 utility is run?  Or=20
>>> is there a way to correct for this in the s2ibis2 command file (*.s2I=20
>>> file)?

>>>>The capability of separating the pullup contribution using s2ibis2 was
>>>>not put in.  Yes, you have to do this separately.  The ranges of [Gnd
>>>>Clamp] from -Vcc to Vcc, and [Power Clamp] from Vcc to 2 Vcc actually
>>>>work only if the currents of both are at "0 mA" at Vcc and for some
>>>>simulators, their linear Extrapolation remain at 0.  Otherwise the
>>>>tables should go the full range from -Vcc to 2 Vcc each.  Some Spice
>>>>models for ASICs have a separate control to add Pullups or Pulldowns.
>>>>Again, the capability of dealing with this issue was not put into s2ibis2.

>>>>As a practical matter, most of the pullup contribution is low (e.g., 75
uA).
>>>>So for most analysis, the pullup contribution error is small.

I am dealing with SPICE netlists of an input configuration that uses
MOSFETs to provide the pull-up, not 'actual' resistors.  Just to make
sure I am completely clear on the matter, I would have to run s2ibis2 on
the netlist file, and then go back and edit the resulting IBIS file
manually, exactly what subtraction and manipulation would I have to
perform on the clamp tables?

2.  My second question pertains to how one would set up an s2ibis2 [pin]
list for creating a single bidirectional pin?  (in a similiar fashion as
the tri-state pin is modelled in example two that came with s2ibis2
utility)

3.  Following up on that point, I'm also wondering, when you generate
IBIS models for a whole component, do you use a CAD package to assemble
the individual pins (dummy models)?
I ask this because, at the moment I am thinking of the following
strategy of making an IBIS model for a component, and would appreciate
your comments on this:

component --> break down into BASIS SET of types of pins
                 --> create a simple IBIS model for EACH member of the 
                      BASIS SET of pins, using s2ibis2 and the
particular pin's
                      SPICE netlist representing the I/O cell structure.
                      (each pin type's  .s2i file will be really simple,
like
                      the examples provided with the s2ibis2 utility.)
	     --> import 'simple' INDIVIDUAL IBIS pin models into a higher level
                      graphical CAD package, in a modular library
fashion (the pin
                      models, once created can be used and reused
easily)
                 --> attach package model (containing data such as 
                      mutual inductances between every pin, etc.)
                      by linking individual pin models created earlier 
                      to pins on the component package
                 --> CAD program then creates the finished IBIS file
                      for the component,
                      which is more error-free, than if created by hand.

4. Monotonicity warnings:  How concerned should I be with these?  I
found these when I ran ibischk2 on an IBIS model
for a simple tri-state driver created using s2ibis2.  It gave the
following message:

Checking pt5t01.ibs for IBIS 2.1 Compatibility...

WARNING (line   57) - Pulldown Maximum data is non-monotonic
WARNING (line   63) - Pulldown Typical data is non-monotonic
WARNING (line   69) - Pulldown Minimum data is non-monotonic
WARNING (line  155) - Pullup Maximum data is non-monotonic
WARNING (line  157) - Pullup Typical data is non-monotonic
WARNING (line  164) - Pullup Minimum data is non-monotonic

Errors  : 0
Warnings: 6

File Passed

The IBISv2.1 spec says the following:

|                The clamp curves of an input or I/O buffer can be
measured
|                directly with a curve tracer, with the I/O buffer
3-stated.
|                However, sweeping enabled buffers results in curves
that are
|                the sum of the clamping curves and the output
structures.
|                Based on the assumption outlined above, the pull-up and
|                pull-down curves of an IBIS model must represent the
|                difference of the 3-stated and the enabled buffer's
curves.
|                (Note that the resulting difference curve can
demonstrate a
|                non-monotonic shape.)  This requirement enables the
simulator
|                to sum the curves, without the danger of double
counting, and
|                arrive at an accurate model in both the 3-stated and
enabled
|                conditions.
|

But the [Pullup] and [Pulldown] Curves that I generated were generated
using s2ibis2, not measured on the bench.  What should I do about the
monotonicity warnings?

I'm still relatively new to IBIS.  I would appreciate any comments you
can offer.  I thank you all for your help in the past few weeks, and
hope that you can help me again.  I have only approx 2 months left now
to finish creating IBIS models for all components at my company, so any
help at all is always greatly appreciated.

Best Regards,
Roland

******************************************
Roland Chang ext. 2647

PMC-Sierra 
Applications Department
105-8555 Baxter Place
Burnaby, BC
V5A 4V7
Tel: (604) 415-6000

email: chang@pmc-sierra.bc.ca
******************************************
 
From owner-ibis  Fri Jun  6 06:48:28 1997
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From: JEAN-MARC.J.M.C.CLAVEAU@RCM.thomson.fr
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Hello IBIS users,

I am searching for IBIS models of RS232 and RS422 components :

- MAX 232 AEWE
- DS96174CN
- DS96175CN

If somebody can help me, thanks to send me a message.

Best regards

J-M

*****************************
J-M Claveau
EMC department
THOMSON CSF RCM
1 bld Jean Moulin
78852 Elancourt cedex
France

e-mail : jean-marc.claveau@rcm.thomson.fr
 
From owner-ibis  Fri Jun  6 06:58:56 1997
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From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
To: roland_chang@pmc-sierra.bc.ca
Cc: ibis-users@vhdl.org, ingraham@wrksys.ENET.dec.com
Apparently-To: ibis-users@vhdl.org, roland_chang@pmc-sierra.bc.ca
Subject: Re: Help with s2ibis2 utility: pullups on input pins, bidirectional pin modelling, etc.

Again, these are comments from one who doesn't use the s2ibis*
utility.

> 1.	Inputs with pull-up resistors?

The two Clamp tables, [Gnd Clamp] and [Power Clamp], are supposed to
represent ALL currents when the device is not driving.  For an
input-only pin, that's everything, including pullup resistors. 
Don't let the "Clamp" in the name fool you into thinking they are
only for clamps; they aren't.

The reason there are two clamp tables rather than one, is that the
currents into a real power clamp diode are dependent on the power
supply voltage; they track it as it goes up and down.  The easiest
way to do that in a model is to split the current into two tables
and make one of them Vcc-relative, which is exactly what IBIS does.

Because the currents into a pullup resistor (or FET) connected to
Vcc, also track Vcc as it goes up and down, these currents
(associated with the pullup resistor/FET) also technically should
go in the [Power Clamp] table.

By the same token, if you had a pulldown resistor/FET, all of its
currents should technically go in the [Gnd Clamp] table and none of
it in the [Power Clamp] table.

Now if you take a real part, or a SPICE model as a black box, and
you sweep the input voltage and measure the current, you will get
one curve, which you want to split into [Gnd Clamp] and [Power
Clamp] tables.  With no further information, i.e., treating your
device as a black box, you can't tell how much is due to pullups,
pulldowns, transistors, clamp diodes, etc.  About all you can do is
split the curve at Vcc and put everything below Vcc in the [Gnd
Clamp] table, and everything above Vcc in the [Power Clamp] table.

This is probably what s2ibis* does.

On the other hand, if you have a way to separately measure or
characterize JUST the pullup FET current, and if you want to be
technically correct (which gives you a slightly more accurate IBIS
model), then what you should do is (a) subtract the pullup current
from the [Gnd Clamp] table since the pullup contributes no current
that is not Vcc-relative, (b) extend the [Power Clamp] table to both
sides of Vcc, probably all the way from -Vcc to 2*Vcc, and (c) put
the currents you subtracted from the [Gnd Clamp] table into the
[Power Clamp] table.

Just make sure that when you add the [Gnd Clamp] and Vcc-adjusted
[Power Clamp] currents, you always end up with the total current
into the input pin.

Whether you need to do this, depends on the magnitude of the pullup
current.  If it's a 100k resistor, the currents are in the 50uA
range.  The "error" happens only when Vcc is not the same as it was
when you ran s2ibis* (or measured a real part).  If the difference
in Vcc is about half a volt, and the MOSFET looks like a 100k
resistor, the error is around 5uA.  Is that enough to worry about? 
You decide.

(On the other hand, half a volt can make a HUGE difference with a
real clamp diode.)


> 2.  My second question pertains to how one would set up an s2ibis2 [pin]
> list for creating a single bidirectional pin?  (in a similiar fashion as
> the tri-state pin is modelled in example two that came with s2ibis2
> utility)

The entry in the [Pin] list should point to a model_name that is
bidirectional.

For example, in the IBIS spec "ver2_1.ibs":

> [Pin]   signal_name     model_name      R_pin   L_pin   C_pin
> |
>   1     RAS0#           Buffer1         200.0m  5.0nH   2.0pF
>   2     RAS1#           Buffer2         209.0m  NA      2.5pF
>   3     EN1#            Input1          NA      6.3nH   NA
>   4     A0              3-state

Pin 4 is probably a bidirectional pin.  Elsewhere in the IBIS model,
the "[Model] 3-state" section would define its characteristics. 
Bidirectional (I/O) just means tri-state with input capabilities.
Thus, Vinl and Vinh must be specified.


> 4. Monotonicity warnings:  How concerned should I be with these?

Monotonicity warnings are only warnings.  They are not errors.  Note
that IBIS does not require monotonicity!  IBIS talks about non-
monotonicity simply because some simulators don't like it; so it's
good to know at the time you create your models.

> {paragraph quoted from IBIS v2.1 spec}
>
> But the [Pullup] and [Pulldown] Curves that I generated were generated
> using s2ibis2, not measured on the bench.  What should I do about the
> monotonicity warnings?

The paragraph you quoted from the IBIS spec applies equally to
SPICE-generated models, as it does to lab-measured models.  It just
happens to have been written with a bias toward lab measurements.

The process of creating pull-up and pull-down curves that are "the
difference of the 3-stated and the enabled buffer's curves" is done
regardless of where the data comes from.  s2ibis* does it.

Don't worry if your individual tables are non-monotonic.  Look at
the overall curves (either the swept data before being picked apart
into IBIS tables, or after combining them back together again).  If
these are monotonic, don't worry.

 (It's unfortunate that ibischk* doesn't bother piecing the curves
 back together before checking for monotonicity ... and equally
 frustrating that the IBIS spec actually instructs ibischk* and
 any similar program to NOT piece the curves back together!  How
 bass-ackwards!)

IBIS models ought to be run through some tests on a simulator before
releasing them.  If there were monotonicity problems to worry about,
that MIGHT catch some of them.  (But it's no guarantee, since some
simulators don't care, while others do.)

Regards,
Andy
 
From owner-ibis  Fri Jun  6 07:29:59 1997
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Date: Fri, 6 Jun 1997 10:28:35 -0400 (EDT)
From: Luke Chang <chang@nexen.com>
Message-Id: <199706061428.KAA10232@bach.nexen.com>
To: JEAN-MARC.J.M.C.CLAVEAU@rcm.thomson.fr
Subject: Search for IBIs models
Cc: ibis-users@vhdl.org

Hi J-M,

H.A.S. Electronics, Inc. (Marlboro, MA USA) specializes in creating IBIS models.
Check out their Web site www.haselect.com and search their list of available 
models.  I think you have to pay for them.

Luke Chang
Ascom Nexion, Inc.
Acton, MA
U. S. A.


----- Begin Included Message -----

From owner-ibis@server.vhdl.org Fri Jun  6 10:05:21 1997
From: JEAN-MARC.J.M.C.CLAVEAU@RCM.thomson.fr
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Hello IBIS users,

I am searching for IBIS models of RS232 and RS422 components :

- MAX 232 AEWE
- DS96174CN
- DS96175CN

If somebody can help me, thanks to send me a message.

Best regards

J-M

*****************************
J-M Claveau
EMC department
THOMSON CSF RCM
1 bld Jean Moulin
78852 Elancourt cedex
France

e-mail : jean-marc.claveau@rcm.thomson.fr


----- End Included Message -----

 
From owner-ibis  Fri Jun  6 09:00:44 1997
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To: ibis@vhdl.org, ibis-users@vhdl.org
Subject: Re: examples needed for IBIS V3.1
Date: Fri, 06 Jun 1997 08:59:52 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>


Hello All:

    I've been reading the mail talking about adding examples to the 
spec and/or the cookbook.  It's a very good idea, especially in
regards to the cookbook.  Do you, the dedicated users of IBIS, have
some specific examples in mind?  Also, are there some specific areas of the
spec that needs explanation or was particularly difficult to understand?
I am in the process of updateing the cookbook for presentation at the
IBIS face to face at DAC next week and your suggestions for
cookbook improvement would be helpfull.

               Thanks,
               Stephen Peters
               Intel Corp.

 
From owner-ibis  Fri Jun  6 12:24:06 1997
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Date: Fri, 06 Jun 1997 12:22:41 -0700
From: "D. C. Sessions" <dc.sessions@tempe.vlsi.com>
Organization: VLSI Technology Inc.
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Subject: Re: examples needed for IBIS V3.1
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Syed Huq wrote:

> One helpful thing would be to put a model example that has
> data of almost all the model types and with all the optional
> parameters that IBIS supports. This may not be a 'true'
> device but would serve as a 'example' only. Model types
> meaning, open_drain, ECL, PECL, CMOS etc etc and there is
> a LOT of optional parameters ....

Just to be contrary, I'd think that it is better to have
several VERY simple examples rather than one complex one
where the (terrified) user has a hard time finding what 
she needs.

Some degree of compromise is probabably optimal.
but KISS.

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com
 
From owner-ibis  Fri Jun  6 12:44:43 1997
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From: Tim McKinney <timmc@ecad2.corp.mot.com>
Subject: multiple models
To: ibis-users@vhdl.org
Date: Fri, 06 Jun 1997 14:38:47 CDT
X-Mailer: Elm [revision: 111.1]

 
From owner-ibis  Fri Jun  6 10:38:00 1997
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Date: Fri, 6 Jun 97 10:39:04 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9706061739.AA11399@rockie.nsc.com>
To: ibis@vhdl.org, ibis-users@vhdl.org, sjpeters@ichips.intel.com
Subject: Re: examples needed for IBIS V3.1

Hi,

One helpful thing would be to put a model example that has 
data of almost all the model types and with all the optional
parameters that IBIS supports. This may not be a 'true' 
device but would serve as a 'example' only. Model types 
meaning, open_drain, ECL, PECL, CMOS etc etc and there is
a LOT of optional parameters ....

Regards,
Syed
National Semiconductor Corp.

> From owner-ibis@server.vhdl.org Fri Jun  6 10:31:04 1997
> To: ibis@vhdl.org, ibis-users@vhdl.org
> Subject: Re: examples needed for IBIS V3.1
> Date: Fri, 06 Jun 1997 08:59:52 -0700
> From: Stephen Peters <sjpeters@ichips.intel.com>
> 
> 
> Hello All:
> 
>     I've been reading the mail talking about adding examples to the 
> spec and/or the cookbook.  It's a very good idea, especially in
> regards to the cookbook.  Do you, the dedicated users of IBIS, have
> some specific examples in mind?  Also, are there some specific areas of the
> spec that needs explanation or was particularly difficult to understand?
> I am in the process of updateing the cookbook for presentation at the
> IBIS face to face at DAC next week and your suggestions for
> cookbook improvement would be helpfull.
> 
>                Thanks,
>                Stephen Peters
>                Intel Corp.
> 
> 
 
From owner-ibis  Sat Jun  7 14:02:58 1997
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Date: Sat, 7 Jun 97 16:58:32 EDT
From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
To: ibis-users@vhdl.org
Cc: ingraham@wrksys.ENET.dec.com
Apparently-To: ibis-users@vhdl.org
Subject: Re: examples needed for IBIS V3.1

D. C. Sessions wrote:

> Just to be contrary, I'd think that it is better to have
> several VERY simple examples rather than one complex one
> where the (terrified) user has a hard time finding what 
> she needs.

I whole-heartedly agree!

We already have example fragments with all the keywords and
many of the optional parameters, right in the IBIS spec
document itself.  What we need are plain and simple examples
with only what's needed to get started.  All the extra
keywords and parameters come with experience and fine-tuning.

There is/was an example file with the version 1.0 spec. 
In fact I think it's still there.  Try this URL:
ftp://ftp.vhdl.org/pub/ibis/ver1.0/n74f244n.ibs

Some of the models in the ibis/models/ directory also might
be worth using.  Unfortunately, that directory seems to have
fallen into disrepair these days....

Regards,
Andy Ingraham
 
From owner-ibis  Mon Jun  9 13:32:42 1997
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From: Tim McKinney <timmc@ecad2.corp.mot.com>
Subject: pin modeling
To: ibis-users@vhdl.org
Date: Mon, 09 Jun 1997 15:28:01 CDT
X-Mailer: Elm [revision: 111.1]

I am using s2ibis2 ver1.1 and am having trouble modeling pins.
I am not sure when to use the input and enable specifications.  The man pages
are not very clear with that description.  Does anyone have a better description
as how to model pins?  Any help would be much appreciated.
Thanks,
	Tim McKinney
 
From owner-ibis  Thu Jun 12 10:42:09 1997
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From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>,
        "'ibis-info@vhdl.org'"
	 <ibis-info@vhdl.org>
Subject: IBIS component generation, PECL differential inputs, analog I/O pins, Vmeas, Cref, Rref, Vref 
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Hello, I am using s2ibis2 and HSPICE netlists to generate IBIS files.  I
am using s2ibis2 to first generate IBIS models  for the inidividual
"types" of pins, and then cutting and pasting the [Model] portion of the
individual IBIS pin models into a larger "main" IBIS file which
describes the entire component.  This saves having to set up s2ibis2 for
generating the entire component all at once.  Once created, I can use
and reuse IBIS pin models for pins on the component that are identical
in nature.  Is there any problem with the IBIS model generation scheme
I've outlined above?  I would especially like to hear from other people
who have worked with s2ibis2 and SPICE to create their IBIS models.

Secondly, I am now faced with how to setup both the s2ibis2 *.s2i file
and the IBIS file for some PECL (Pseudo-ECL) differential inputs.  Has
anyone had to generate IBIS models for pins that are both differential
and Pseudo-ECL(or ECL) before?  How does s2ibis2 handle the [Diff pin]
Keyword, and associated pin list section? In the s2ibis2 manual, it says
that no processing is actually performed on the [Diff pin] list.  Does
this mean that I could create a single ECL input pin first using
s2ibis2, include the [Model] section of the single ECL input IBIS file
into a 'main' IBIS file for a component, connect the model name to
appropriate pins on the component, and then add the [Diff pin] pin list
later in the actual 'main' IBIS file for the component?

Thirdly, how are analog I/O pins treated in IBIS and s2ibis2?  How would
I setup an analog I/O pin in s2ibis2 and IBIS?

And finally, are the Vmeas, Cref, Rref, Vref parameters used for
anything in s2ibis2, or in IBIS files?  (are they actually processed? or
are they just for reference)


Thanx for your time,

Roland

******************************************
Roland Chang ext. 2647

PMC-Sierra 
Applications Department
105-8555 Baxter Place
Burnaby, BC
V5A 4V7
Tel: (604) 415-6000

email: chang@pmc-sierra.bc.ca
******************************************
 
From owner-ibis  Fri Jun 13 00:00:11 1997
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Date: Fri, 13 Jun 1997 12:30:21 +0531
From: Srinivas Gande <srinu@cadence.com>
Message-Id: <199706130659.MAA16875@lancer.cadence.com>
To: roland_chang@pmc-sierra.bc.ca
Subject: RE: IBIS component generation, PECL differential inputs, analog I/O pins, Vmeas, Cref, Rref, Vref
Cc: ibis-users@vhdl.org
X-Sun-Charset: US-ASCII



Hi chang, 
	
	Included inline comments. Please someone  correct me, if I made
	any mistake. 


>  Hello, I am using s2ibis2 and HSPICE netlists to generate IBIS files.  I
>  am using s2ibis2 to first generate IBIS models  for the inidividual
>  "types" of pins, and then cutting and pasting the [Model] portion of the
>  individual IBIS pin models into a larger "main" IBIS file which
>  describes the entire component.  This saves having to set up s2ibis2 for
>  generating the entire component all at once.  Once created, I can use
>  and reuse IBIS pin models for pins on the component that are identical
>  in nature.  Is there any problem with the IBIS model generation scheme
>  I've outlined above?  I would especially like to hear from other people
>  who have worked with s2ibis2 and SPICE to create their IBIS models.


	This is correct way of doing.  

>  
>  Secondly, I am now faced with how to setup both the s2ibis2 *.s2i file
>  and the IBIS file for some PECL (Pseudo-ECL) differential inputs.  Has
>  anyone had to generate IBIS models for pins that are both differential
>  and Pseudo-ECL(or ECL) before?  How does s2ibis2 handle the [Diff pin]
>  Keyword, and associated pin list section? In the s2ibis2 manual, it says
>  that no processing is actually performed on the [Diff pin] list.  Does
>  this mean that I could create a single ECL input pin first using
>  s2ibis2, include the [Model] section of the single ECL input IBIS file
>  into a 'main' IBIS file for a component, connect the model name to
>  appropriate pins on the component, and then add the [Diff pin] pin list
>  later in the actual 'main' IBIS file for the component?

	For PECL & ECL:--

	In s2i define [Pullup Reference] and [Pulldown Reference] to VCC. 
	[Model type] to be of Ouput_ECL or  Input_ECL. Rest of the s2i is 
	simillar (Voltage Range not required). The vout variation for 
	pullup and pulldown from VCC to  VCC-2.2 . In IBIS tablular format 
	you refer to VCC.  I encountered a problem in using s2ibis2 for 
	PECL (5V) device. You can edit the *.spi files set up by s2ibis2 
	and use [iterate] option to process SPICE input files in accordance 
	with specs. I also found problem in tabulating IBIS file by reading *.out
	files.  

	[Diff pin] is not processed by s2ibis2.  It's right to add [Diff] 
	section at the end.  

>  
>  Thirdly, how are analog I/O pins treated in IBIS and s2ibis2?  How would
>  I setup an analog I/O pin in s2ibis2 and IBIS?

	Scope of IBIS is restricted to analog behaviour of Digital ICS. 
	I am not sure what you really mean by analog I/O pin ?. 	
>  
>  And finally, are the Vmeas, Cref, Rref, Vref parameters used for
>  anything in s2ibis2, or in IBIS files?  (are they actually processed? or
>  are they just for reference)


	No they are not used.  This information is reference
	for IBIS based simulators.   
>


..srinu



                         .\\\.
                         (~ ~)
                         #0-0#
 __________________.oOo__( ! )__oOo.__________________
(_)                       \^/                       (_)
| |     Srinivas Gande                              | |
| |     CADENCE DESIGN SYSTEMS(INDIA)               | |
| |     B-9, N.E.P.Z                                | |
| |     NOIDA U.P.                                  | |
| |     Phone  : +91-11-8-544100(Home)              | |
| |     Phone  : +91-11-8-562842(Work)              | |
| |     Fax    : +91-11-8-562843                    | |
| |     email  : srinu@cadence.com                  | |
| |__________________.oooO_|_Oooo.__________________| |
(_)                  (   )   (   )                  (_)
                      \ (     ) /
                       \_)   (_/
 
From owner-ibis  Fri Jun 13 15:50:37 1997
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Date: Fri, 13 Jun 97 15:53:24 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9706132253.AA06155@rockie.nsc.com>
To: ibis-users@vhdl.org, roland_chang@pmc-sierra.bc.ca
Subject: Re: IBIS component generation, PECL differential inputs, analog I/O pins, Vmeas, Cref, Rref, Vref

Hi Roland,

I can share with you my experience regarding your first question.
I have developed IBIS models from HSPICE using the s2ibis2 and I
did exactly what you described. With this approach of translating 
individual 'types' of pins, you can solve problems easily if
they occur. But, as you pointed out, you do have to put all
the individually run models back into 'ONE' entire IBIS model.
The parser test will help you debug if any manual errors were
introduced during the cut and paste.

I believe the Vmeas, Cref, Rref, Vref are for timing information
for the simulator only.

Regards,
Syed
National Semiconductor Corp.

> From owner-ibis@server.vhdl.org Thu Jun 12 12:10:52 1997
> From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
> To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>,
>         "'ibis-info@vhdl.org'"
> 	 <ibis-info@vhdl.org>
> Subject: IBIS component generation, PECL differential inputs, analog I/O pins, Vmeas, Cref, Rref, Vref 
> Date: Thu, 12 Jun 1997 10:40:54 -0700
> X-Mailer:  Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63
> Content-Type> : > text/plain> ; > charset="us-ascii"> 
> Content-Transfer-Encoding: 7bit
> 
> Hello, I am using s2ibis2 and HSPICE netlists to generate IBIS files.  I
> am using s2ibis2 to first generate IBIS models  for the inidividual
> "types" of pins, and then cutting and pasting the [Model] portion of the
> individual IBIS pin models into a larger "main" IBIS file which
> describes the entire component.  This saves having to set up s2ibis2 for
> generating the entire component all at once.  Once created, I can use
> and reuse IBIS pin models for pins on the component that are identical
> in nature.  Is there any problem with the IBIS model generation scheme
> I've outlined above?  I would especially like to hear from other people
> who have worked with s2ibis2 and SPICE to create their IBIS models.
> 
> Secondly, I am now faced with how to setup both the s2ibis2 *.s2i file
> and the IBIS file for some PECL (Pseudo-ECL) differential inputs.  Has
> anyone had to generate IBIS models for pins that are both differential
> and Pseudo-ECL(or ECL) before?  How does s2ibis2 handle the [Diff pin]
> Keyword, and associated pin list section? In the s2ibis2 manual, it says
> that no processing is actually performed on the [Diff pin] list.  Does
> this mean that I could create a single ECL input pin first using
> s2ibis2, include the [Model] section of the single ECL input IBIS file
> into a 'main' IBIS file for a component, connect the model name to
> appropriate pins on the component, and then add the [Diff pin] pin list
> later in the actual 'main' IBIS file for the component?
> 
> Thirdly, how are analog I/O pins treated in IBIS and s2ibis2?  How would
> I setup an analog I/O pin in s2ibis2 and IBIS?
> 
> And finally, are the Vmeas, Cref, Rref, Vref parameters used for
> anything in s2ibis2, or in IBIS files?  (are they actually processed? or
> are they just for reference)
> 
> 
> Thanx for your time,
> 
> Roland
> 
> ******************************************
> Roland Chang ext. 2647
> 
> PMC-Sierra 
> Applications Department
> 105-8555 Baxter Place
> Burnaby, BC
> V5A 4V7
> Tel: (604) 415-6000
> 
> email: chang@pmc-sierra.bc.ca
> ******************************************
> 
 
From owner-ibis  Sun Jun 15 14:49:04 1997
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Date: Sun, 15 Jun 97 17:44:15 EDT
From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
To: roland_chang@pmc-sierra.bc.ca
Cc: ibis-users@vhdl.org, ingraham@wrksys.ENET.dec.com
Apparently-To: ibis-users@vhdl.org, roland_chang@pmc-sierra.bc.ca
Subject: RE: IBIS component generation, PECL differential inputs, analog I/O pins, Vmeas, Cref, Rref, Vref 

> >  Thirdly, how are analog I/O pins treated in IBIS and s2ibis2?  How would
> >  I setup an analog I/O pin in s2ibis2 and IBIS?
> 
> 	Scope of IBIS is restricted to analog behaviour of Digital ICS. 
> 	I am not sure what you really mean by analog I/O pin ?. 	

On a mixed-signal IC, analog pins would not have models in the IBIS
file.

It seems like one might use "NA" as the model_name under the [Pin]
keyword, to signify that these pins have no available IBIS data. 
However, that is not allowed.  Instead, use "NC".  Technically
incorrect, but it tells the IBIS parser to skip those pins.

[Pin]   signal_name     model_name      R_pin   L_pin   C_pin
|
  1     RAS0#           Buffer1         200.0m  5.0nH   2.0pF
  2     RAS1#           Buffer2         209.0m  NA      2.5pF
  3     Analog_out      NC
...

Regards,
Andy Ingraham
 
From owner-ibis  Mon Jun 16 09:10:05 1997
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From: Katja Zuleeg <zk3317@nbgm.siemens.de>
Organization: SIEMENS AG
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To: ibis-users@vhdl.org
Subject: differential driver
Content-Type: text/plain; charset=us-ascii
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Hi,

I am trying to generate an Ibis-model for a differential driver. Does
anybody know of an example for me to look at?
The device is the differential Bus Transceiver LSI-ALS176D.
Perhaps there exists a model yet?

thanks,

Katja Zuleeg
-- 
email: Katja.Zuleeg@nbgm.siemens.de und Katja.Zuleeg@uni-bayreuth.de
SIEMENS AG, AUT E 1373, Gleiwitzerstr. 555, 90475 Nuernberg, Germany
Tel.: (+49 911) 895-3317  Fax: (+49 911) 895-3055
 
From owner-ibis  Mon Jun 16 13:51:53 1997
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9706162054.AA26060@rockie.nsc.com>
To: ibis-users@vhdl.org, zk3317@nbgm.siemens.de
Subject: Re: differential driver

Katja

The National Semiconductor web site has various Differential
IBIS models under http://www.national.com/models

Select IBIS and then 'Interface'.

Regards,
Syed
National Semiconductor Corp.

> From owner-ibis@server.vhdl.org Mon Jun 16 10:54:39 1997
> Sender: zk3317@nbgm.siemens.de
> Date: Mon, 16 Jun 1997 18:07:55 +0200
> From: Katja Zuleeg <zk3317@nbgm.siemens.de>
> Organization: SIEMENS AG
> X-Mailer: Mozilla 3.0Gold (X11; I; SunOS 5.5 sun4u)
> To: ibis-users@vhdl.org
> Subject: differential driver
> Content-Type> : > text/plain> ; > charset=us-ascii> 
> Content-Transfer-Encoding: 7bit
> 
> Hi,
> 
> I am trying to generate an Ibis-model for a differential driver. Does
> anybody know of an example for me to look at?
> The device is the differential Bus Transceiver LSI-ALS176D.
> Perhaps there exists a model yet?
> 
> thanks,
> 
> Katja Zuleeg
> -- 
> email: Katja.Zuleeg@nbgm.siemens.de und Katja.Zuleeg@uni-bayreuth.de
> SIEMENS AG, AUT E 1373, Gleiwitzerstr. 555, 90475 Nuernberg, Germany
> Tel.: (+49 911) 895-3317  Fax: (+49 911) 895-3055
> 
 
From owner-ibis  Mon Jun 16 14:12:56 1997
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From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>,
        "'ibis-info@vhdl.org'"
	 <ibis-info@vhdl.org>
Subject: Wanted: Example ECL or PECL IBIS model
Date: Mon, 16 Jun 1997 14:12:27 -0700
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Hello again, 

I am not that familiar with ECL or PECL (Pseudo-ECL), and I have
received some help already on this matter, I am now seeking an example
IBIS file with ECL or PECL differential pins modelled?  Does anyone know
where to find one?

Again, I would especially like to hear from anyone who has had
experience with converting spice netlists of ECL or PECL pins to ibis
using the s2ibis2 utility, and what kind of special pitfalls, etc. that
I should be aware of.

thanks to all those who have helped me out with IBIS so far! I am glad
to say that I am almost finished my first complete IBIS file - I don't
know where I'd be without this maillist, I really appreciate everyone's
openness and willingness to help.

THANX

Roland

******************************************
Roland Chang ext. 2647

PMC-Sierra 
Applications Department
105-8555 Baxter Place
Burnaby, BC
V5A 4V7
Tel: (604) 415-6000

email: chang@pmc-sierra.bc.ca
******************************************
 
From owner-ibis  Mon Jun 16 15:54:35 1997
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Date: Mon, 16 Jun 1997 15:51:23 -0700 (PDT)
From: Milan Gandhi <milan@indusinc.com>
Message-Id: <199706162251.PAA04961@monterey.indusinc.com>
To: ibis-users@vhdl.org
Subject: Question on Ramp
X-Sun-Charset: US-ASCII

Hi,
	This is our first experience with IBIS, so this might
	be a trivial issue for you experienced folks !!

	We are getting Ramp (dV/dt) as 0 in ibis inspite of
	providing required Voltage values.
	What should we be looking for in order to get
	correct Ramp values in Ibis model.
	We are using tools from NC university.

-Thanks, Milan
 
From owner-ibis  Mon Jun 16 17:06:37 1997
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To: ibis-users@vhdl.org
Subject: Question on Ramp
Date: Mon, 16 Jun 1997 17:05:37 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>


Hello Milan:

   Well....the first thing that poped into my mind was: double check that 
you are supplying a stimulas waveform to the input (i.e. telling the output 
buffer to switch).  You might also check the state of any control inputs 
on the buffer and make sure that that buffer is not in 3-state mode or 
otherwise disabled.  I hope this helps.

              Regards,
              Stephen Peters
              Intel Corp.



Hi,
	This is our first experience with IBIS, so this might
	be a trivial issue for you experienced folks !!

	We are getting Ramp (dV/dt) as 0 in ibis inspite of
	providing required Voltage values.
	What should we be looking for in order to get
	correct Ramp values in Ibis model.
	We are using tools from NC university.

-Thanks, Milan
 
From owner-ibis  Tue Jun 17 08:34:48 1997
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Date: Tue, 17 Jun 97 08:36:47 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9706171536.AA24788@rockie.nsc.com>
To: ibis-users@vhdl.org, milan@indusinc.com
Subject: Re: Question on Ramp

Milan,

s2ibis2 will add 50Ohms pullup and pulldown to calculate 
dV/dt_f and dV/dt_r values. You can try changing these values
to see if your device will switch or not.

...in your .s2i file:

[Rising waveform] 500 0 NA NA NA NA NA NA NA
[Falling waveform] 500 3.3 NA NA NA NA NA NA NA

Try changing the sim time to a larger number too in your .s2i file

[sim time] 10ns

Regards,
Syed
National Semiconductor Corp.

> From owner-ibis@server.vhdl.org Mon Jun 16 17:27:09 1997
> Date: Mon, 16 Jun 1997 15:51:23 -0700 (PDT)
> From: Milan Gandhi <milan@indusinc.com>
> To: ibis-users@vhdl.org
> Subject: Question on Ramp
> X-Sun-Charset: US-ASCII
> 
> Hi,
> 	This is our first experience with IBIS, so this might
> 	be a trivial issue for you experienced folks !!
> 
> 	We are getting Ramp (dV/dt) as 0 in ibis inspite of
> 	providing required Voltage values.
> 	What should we be looking for in order to get
> 	correct Ramp values in Ibis model.
> 	We are using tools from NC university.
> 
> -Thanks, Milan
> 
 
From owner-ibis  Wed Jun 18 10:35:08 1997
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Message-ID: <c=US%a=_%p=PMC_Sierra_Inc.%l=NT-SERVER1-970618173433Z-24194@nt-server1.pmc-sierra.bc.ca>
From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
To: "'Arpad_Muranyi@ccm.fm.intel.com'" <Arpad_Muranyi@ccm.fm.intel.com>
Cc: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>
Subject: PECL and TTL programmable buffer?
Date: Wed, 18 Jun 1997 10:34:33 -0700
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Hello, 

thumbing through the BIRDs, I found BIRD30.2, which talks about
programmable buffers.

I have a pair of differential pins, which can accept PECL differential
inputs, or if the (-) pin is grounded, the (+) pin can be used as TTL
Logic level input.

How would I model this in IBIS? would I use programmable buffers? if so,
can you give an example of how I might model this pair of pins using
programmable buffers?

Also,  a general question, how many of the BIRDs are actually
incorporated into the ibischk syntax checker?

thanx,

Roland

******************************************
Roland Chang ext. 2647

PMC-Sierra 
Applications Department
105-8555 Baxter Place
Burnaby, BC
V5A 4V7
Tel: (604) 415-6000

email: chang@pmc-sierra.bc.ca
******************************************
 
From owner-ibis  Wed Jun 18 12:54:16 1997
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Date: Wed, 18 Jun 1997 12:53:08 -0700 (PDT)
From: bob@icx.com ( Bob Ross)
To: ibis-users@vhdl.org, ibis@vhdl.org
Subject: IBIS Version 3.0 on vhdl.org

To IBIS Committee:

I have uploaded the approved IBIS Version 3.0 specification to
vhdl.org under /pub/ibis/ver3.0/ver3_0.ibs (also ver3_0.txt).
Please destroy any prior versions you may have obtained under
the wip directory since they are not valid.

IBIS Version 3.0 was ratified at the June 12, 1997 EIA/IBIS
Open Forum Summit meeting.  The uploaded version contains some
minor editoral changes for format consistency and alignment and
some other changes such as replacing IV "curves" with "tables".

The new features based on approved BIRDs contained in Version 3.0
consists of these extensions:

  [Model Selector] keyword for programmable buffers (BIRD30.2)

  [TTgnd], [TTpower] keywords for stored charge effects (BIRD34.2)

  [Driver Schedule] keyword for multi-staged outputs (BIRD35.3)

  Electrical Board Description for .ebd file and keywords(BIRD36.3):
     [Begin Board Description], [Manufacturer], [Number Of Pins], [PIn List],
     [Path Description], [Reference Designator Map], [End Board Description]

  Package Model Extensions (BIRD28.3 and BIRD37.3):
     [Number Of Sections], [Pin Numbers] extension, 

  [Model Spec] keyword and subparameters (BIRD39 and BIRD40)

  Series and Series Switch Extensions (BIRD41.8) including keywords:
     Under [Component]:
       [Series Switch Groups], [Series Pin Mapping]
     Under [Model]
       [Series Current], [Series MOSFET] for IV data
       [R Series], [L Series], [Rl Series], [C Series], [Rc Series], 
           [Lc Series] for RLC series paths
       [On], [Off] for Series_switch models

  [Component] test point subparameters (BIRD43)
     
Bob Ross
Interconnectix


 
From owner-ibis  Thu Jun 19 13:21:25 1997
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Date: Thu, 19 Jun 1997 13:20:15 -0700 (PDT)
From: bob@icx.com ( Bob Ross)
To: ibis-users@vhdl.org
Subject: Re:  PECL and TTL programmable buffer?


Roland:

Some responses below.

Bob Ross
Interconnectix


> From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
> To: "'Arpad_Muranyi@ccm.fm.intel.com'" <Arpad_Muranyi@ccm.fm.intel.com>
> Cc: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>
> Subject: PECL and TTL programmable buffer?
> Date: Wed, 18 Jun 1997 10:34:33 -0700


> Hello, 

> thumbing through the BIRDs, I found BIRD30.2, which talks about
> programmable buffers.

> I have a pair of differential pins, which can accept PECL differential
> inputs, or if the (-) pin is grounded, the (+) pin can be used as TTL
> Logic level input.

> How would I model this in IBIS? would I use programmable buffers? if so,
> can you give an example of how I might model this pair of pins using
> programmable buffers?

I don't think that the BIRD30.2 extension covers situations of 
differential and non-differential inputs.  So I would construct two
IBIS Models, one with differential Inputs and the other without
the differential inputs, and load the appropriate models.

> Also,  a general question, how many of the BIRDs are actually
> incorporated into the ibischk syntax checker?

The ibischk2 parser should cover all of the functionality of Version 2.1.
This includes the functionality of Version 1.1 plus BIRDs 1-26 and BIRD29.2.
(Some of these were not approved).  Check
   http://www.vhdl.org/pub/ibis/birds/birddir.txt
for a history and of inclusions of BIRDs into the various Versions of IBIS.

> thanx,

> Roland

> ******************************************
> Roland Chang ext. 2647

> PMC-Sierra 
> Applications Department
> 105-8555 Baxter Place
> Burnaby, BC
> V5A 4V7
> Tel: (604) 415-6000

> email: chang@pmc-sierra.bc.ca
> ******************************************


 
From owner-ibis  Mon Jun 23 14:09:24 1997
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From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
To: "'Andy Ingraham'" <ingraham@wrksys.enet.dec.com>
Cc: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>,
        "'ibis-info@vhdl.org'"
	 <ibis-info@vhdl.org>
Subject: RE:analog pins in IBIS - request for clarification
Date: Mon, 23 Jun 1997 14:08:51 -0700
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As I understand it, I should put "NC" as the model name in the [Pin]
section for analog pins, but I have a few follow-up questions as well
that I hope people can answer for me.

What is the difference between including the analog pin under the [Pin]
keyword, and then putting "NC" beside it, 
versus omitting the pin altogether?  

Also, if I specify an analog pin in the [Pin] section with "NC" what
should I put in the [Pin Mapping] section for that pin?  (Incidentally,
I know which power buses power up the analog pins) For example, say I
knew that pins 5 and 9 are analog power and ground for pin 10( which is
an analog pin), would it hurt to list pins 5 and 9 as the pullup and
pulldown reference for pin 10?

What if the analog pins that I am dealing with are a set of differential
pins (+) and (-) pair, do I include them in the [Diff Pin] section as
well? even though they have no  vdiff specification? and have "NC" as
their model in the [Pin] section?

Finally, this may be a really stupid question, but I feel that I don't
quite understand why IBIS doesn't handle analog pins. Could someone
please enlighten me on this matter?  

Again, your help is much appreciated,

Roland Chang

******************************************
Roland Chang ext. 2647

PMC-Sierra 
Applications Department
105-8555 Baxter Place
Burnaby, BC
V5A 4V7
Tel: (604) 415-6000

email: chang@pmc-sierra.bc.ca
******************************************
>-----Original Message-----
>From:	Andy Ingraham [SMTP:ingraham@wrksys.ENET.dec.com]
>Sent:	June 15, 1997 2:44 PM
>To:	Roland Chang; Roland Chang; ibis-users@vhdl.org
>Cc:	ibis-users@vhdl.org; ingraham@wrksys.ENET.dec.com
>Subject:	RE: IBIS component generation, PECL differential inputs, analog I/O
>pins, Vmeas, Cref, Rref, Vref 
>
>> >  Thirdly, how are analog I/O pins treated in IBIS and s2ibis2?  How would
>> >  I setup an analog I/O pin in s2ibis2 and IBIS?
>> 
>> 	Scope of IBIS is restricted to analog behaviour of Digital ICS. 
>> 	I am not sure what you really mean by analog I/O pin ?. 	
>
>On a mixed-signal IC, analog pins would not have models in the IBIS
>file.
>
>It seems like one might use "NA" as the model_name under the [Pin]
>keyword, to signify that these pins have no available IBIS data. 
>However, that is not allowed.  Instead, use "NC".  Technically
>incorrect, but it tells the IBIS parser to skip those pins.
>
>[Pin]   signal_name     model_name      R_pin   L_pin   C_pin
>|
>  1     RAS0#           Buffer1         200.0m  5.0nH   2.0pF
>  2     RAS1#           Buffer2         209.0m  NA      2.5pF
>  3     Analog_out      NC
>...
>
>Regards,
>Andy Ingraham
 
From owner-ibis  Mon Jun 23 14:37:37 1997
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From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>,
        "'ibis-info@vhdl.org'"
	 <ibis-info@vhdl.org>
Subject: crystal oscillator inputs and outputs in IBIS
Date: Mon, 23 Jun 1997 14:37:14 -0700
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Hi,  I was wondering how crystal oscillator inputs and outputs are
specified in IBIS? 

thanx,

Roland

******************************************
Roland Chang ext. 2647

PMC-Sierra 
Applications Department
105-8555 Baxter Place
Burnaby, BC
V5A 4V7
Tel: (604) 415-6000

email: chang@pmc-sierra.bc.ca
******************************************
 
From owner-ibis  Wed Jun 25 06:44:16 1997
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From: Tim McKinney <timmc@ecad2.corp.mot.com>
Subject: i/o buffers
To: ibis-users@vhdl.org
Date: Wed, 25 Jun 1997 8:40:01 CDT
X-Mailer: Elm [revision: 111.1]

I have a question regarding modeling a component with seperate input and output buffers.
There is an internal output and input that I can't place in the pin list.  An output
pin must have its input specified as a pin.  My question is how do I model these two seperate
buffers in the same s2ibis2 conversion header file?  I have been able to run two seperate
models using the internal nodes, but not just one overall model.
Please advise,
	Tim McKinney

 
From owner-ibis  Wed Jun 25 14:46:16 1997
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From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>,
        "'ibis-info@vhdl.org'"
	 <ibis-info@vhdl.org>
Subject: correction of pullup resistor on bidirectional pin with pullup.
Date: Wed, 25 Jun 1997 14:45:52 -0700
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Hello all,

I am trying to model a bidirectional pin, with a pullup(transistor) on
the input.

I know that for an input-only pin, I can correct for the pullup
(transistor) current by subtracting the pullup current from the [GND
clamp] V/I curve, and placing it in the [POWER clamp] V/I curve
(extending the range the power clamp curve at the same time) but, 

how about a bidirectional (I/O) pin with a pullup on the input?
depending on how s2ibis2 calculates the pullup and pulldown curves, By
changing the power clamp and ground clamp curves(by manual text editing
after s2ibis2 has run)  it maybe that when the curves are added back
together by a simulator, that the curves will then be incorrect?

I would appreciate any comments on this,

Thanx in advance,

Roland Chang

******************************************
Roland Chang ext. 2647

PMC-Sierra 
Applications Department
105-8555 Baxter Place
Burnaby, BC
V5A 4V7
Tel: (604) 415-6000

email: chang@pmc-sierra.bc.ca
******************************************


