From owner-ibis  Sat May  3 16:03:05 1997
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From: jerry.isaac@amd.com
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Subject: Questions re: [Rising Waveform], [Falling Waveform]
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Hello, I'm seeking some advice about the subject keywords.  I have included
them in a model I've developed for a customer (since the drivers I'm modeling
do have slew rate control), but I'm not entirely sure how simulators use
the V/T tables versus using the [Ramp] data.  In particular, I have the
following questions:

1) What xxx_fixture values should I specify for my SPICE simulations (and
hence place into the IBIS model)?

2) Should the xxx_fixture values vary for each customer based on their
application?

3) What would happen (in other words, what would a simulator do?) if the
V/T tables use a different loading assumption than the assumptions used
to produce the dV/dt_r and dV/dt_f values? (a response that this is not
appropriate for an IBIS model would be acceptable to me).

4) Would the simulations be any less accurate if I simply didn't include
the V/T tables?

Any light shed on this topic (or a reference to an explanation) would
be most appreciated.

Thank you,
Jerry Isaac
 
From owner-ibis  Mon May  5 12:01:16 1997
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Date: Mon, 5 May 97 11:59 PDT
From: bob@icx.com ( Bob Ross)
To: ibis-users@vhdl.org, jerry.isaac@amd.com
Subject: Re:  Questions re: [Rising Waveform], [Falling Waveform]

Jerry:

I am providing you some thoughts related to how Interconnectix
processes the waveform data to add to the responses already
provided.

I suggest that you actually provide prototypes of your IBIS
models to various IBIS CAE vendors found on the IBIS roster
document to help validate the performance of your models.

Best Regards,
Bob Ross
Interconnectix


 Date: 03 May 1997 16:00:49 -0700
> Subject: Questions re: [Rising Waveform], [Falling Waveform]
> To: ibis-users@vhdl.org

> Hello, I'm seeking some advice about the subject keywords.  I have included
> them in a model I've developed for a customer (since the drivers I'm modeling
> do have slew rate control), but I'm not entirely sure how simulators use
> the V/T tables versus using the [Ramp] data.  In particular, I have the
> following questions:

> 1) What xxx_fixture values should I specify for my SPICE simulations (and
> hence place into the IBIS model)?

For CMOS, we also support typical 50 ohm loads to GND and to Vcc.  While
permissible, we will get BAD simulations in general if you include a
significant (such as 50 pF) C_fixture component.   The only cases where the
results will be reasonable is if the actual circuit contained that discrete
capactance.

> 2) Should the xxx_fixture values vary for each customer based on their
> application?

A major application of IBIS models is for simulation of high-speed
signals in transmission line networks that model printed circuit board
traces.  Such designs typically have transmission line impedances in the
30 to 100 ohm region, and 50 ohms seems like a good nominal value.

If you knew beforehand that the characteristic impendance environment
was at a different level, then you would get (probably) slighly more
accurate by tuning your waveform extractions to the actual characteristic
impendance.  However, I do not feel this is necessary for a model to 
be provided for multiple applications.

> 3) What would happen (in other words, what would a simulator do?) if the
> V/T tables use a different loading assumption than the assumptions used
> to produce the dV/dt_r and dV/dt_f values? (a response that this is not
> appropriate for an IBIS model would be acceptable to me).

In our simulator, the V/T tables always override the [Ramp] data.  We
use the first two [Rising Waveform] and first two [Falling Waveform]
tables encountered.  If two tables cause a mathematical inconsistency,
(or if the driver is an "Open_***"), then we use just the first table.
If there is a mathematical problem (e.g., some really bad data values)
then we default to the [Ramp] data, and use its loading assumptions.

In all cases, simultors should give a reasonable response for the actual
loading conditions that are seen, regardless of whether the time response
is V/T or Ramp based.  The beginning and ending amplitudes should be
based on actual loading conditions in conjunction with the internal
model I/V tables.

> 4) Would the simulations be any less accurate if I simply didn't include
> the V/T tables?

Our simulators are more accurate by including the V/T tables to capture some
some actual driver pulse shape details that would be seen in practice.

To the extent that much of the simulation detail is based on the network
topology and its set of distributed loads, a Ramp based driver with correct
dt_r and dt_f values also provide accurate simulations.

> Any light shed on this topic (or a reference to an explanation) would
> be most appreciated.

> Thank you,
> Jerry Isaac


 
From owner-ibis  Wed May  7 14:27:59 1997
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Subject: help with S2IBIS utility (fwd)
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From owner-ibis@server.vhdl.org Wed May  7 13:48 PDT 1997
From: Roland James Chang <roland@sfu.ca>
Message-Id: <199705071855.LAA20622@fraser>
Subject: help with S2IBIS utility
To: ibis@vhdl.org
Date: Wed, 7 May 1997 11:55:48 -0700 (PDT)
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Hello, I'm looking for any information on how to use the S2IBIS utility.
I have looked through some application notes from CADENCE, as well as some
of the syntatctical descriptions of IBIS files versions 1.0 to 2.1.

In particular, I'm having trouble with the syntax of the input files that
are fed into the S2IBIS utility.  Input files are to consist of 3 parts:

	1. Header
	2. Modified IBIS pin list
	3. Spice Input Deck

I am having trouble formulating sections 2 and 3.  I would be especially
interested in any examples that could be provided showing complete input
file/output file pairs that were applied to the S2IBIS conversion.

Once again, any help would be greatly appreciated, as I have been assigned
the task of SPICE to IBIS model conversion for many IC's at work.

thanx in advance,

roland
please send replies to roland@sfu.ca

 
From owner-ibis  Thu May  8 06:17:04 1997
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Please add me to the mailing list.
 
From owner-ibis  Thu May  8 06:30:14 1997
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I am having trouble using veribest's s2ibis2.exe on windows NT 4.0 (on
Pentium w/32Meg) using Hspice for windows. My problems are
1) I cannot automate the process-I need to give Hspice the file name and
rename it to a .out extension each time. 
2) There were no working examples supplied, and NCSU ex1-4 cause
convergence problems.

I would greatly appreciate any working example files, no matter how
trivial. I apologize if someone else has posted this concern before: I
just joined this mailing list today.
 
From owner-ibis  Thu May  8 16:55:04 1997
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From: jerry.isaac@amd.com
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Thanks to all who responded to my email...Jerry.
 
From owner-ibis  Tue May 13 13:17:22 1997
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Date: Tue, 13 May 97 13:16 PDT
From: bob@icx.com ( Bob Ross)
To: ibis-users@vhdl.org
Subject: s2ibis2 Version 1.1 Fix

Hello:

I have posted an interim fix to s2ibis2 version 1.1 to allow the
data to be printed with 4 decimal digits instead of 2.  This will
temporarily get around some of the existing 2-digit resolution
problems which can cause some abrupt jumps in the tables.

The fix is found on vhdl.org at

   /pub//ibis/s2ibis/s2ibis2_v1.1/s2ibis2_fix.tar.Z

Included is a Sun 4 executable.

Bob Ross
Inteconnectix
 
From owner-ibis  Tue May 13 16:51:39 1997
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Date: Tue, 13 May 1997 16:50:49 -0700 (PDT)
From: Roland James Chang <roland@sfu.ca>
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first of all, I would like to extend my thanx to all that replied to my
last email seeking help with the s2ibis2 utility.  I've now obtained the
s2ibis2 utility and have been playing with it for the past few days.  

I am a university student on a work term at a leading supplier of ATM
components, and am finding it quite challenging to learn the entire IBIS
modelling standard in the span of a couple of days, so please bear with
me, if any of my questions sound too simple (or even stupid) :-)

I've been working through the examples (1-4) provided with the s2ibis2
utility but I cannot get example 2 to work (which deals with a simple
tristate buffer) It seems to be running into DC convergence problems.
This is the output that I get when I run the s2ibis2 utility on example 2
(with tristate.s2i setup for HSPICE):

****************************************************************************
* session on an xterm follows
****************************************************************************
17 <chang> s2ibis2.sun4 tristate.s2i

s2ibis2.sun4 v1.1 -- North Carolina State University
s2ibis2.sun4: Reading input file tristate...done.
s2ibis2.sun4: Analyzing component MCM Trisate Driver .
s2ibis2.sun4: Starting HSpice job with input putout.spi.
s2ibis2.sun4: Starting HSpice job with input punout.spi.
s2ibis2.sun4: Starting HSpice job with input puxout.spi.
s2ibis2.sun4: Starting HSpice job with input dutout.spi.
s2ibis2.sun4: Starting HSpice job with input dunout.spi.
s2ibis2.sun4: Spice run (MIN) aborted.  See file dunout.msg for
information.
         continuing with MAX run.
s2ibis2.sun4: Starting HSpice job with input duxout.spi.
s2ibis2.sun4: Starting HSpice job with input pdtout.spi.
s2ibis2.sun4: Starting HSpice job with input pdnout.spi.
s2ibis2.sun4: Starting HSpice job with input pdxout.spi.
s2ibis2.sun4: Starting HSpice job with input ddtout.spi.
s2ibis2.sun4: Starting HSpice job with input ddnout.spi.
s2ibis2.sun4: Starting HSpice job with input ddxout.spi.
s2ibis2.sun4: Starting HSpice job with input pctout.spi.
s2ibis2.sun4: Spice run (TYP) aborted.  See file pctout.msg for
information.
         Curve power clamp not generated.
s2ibis2.sun4: Starting HSpice job with input gctout.spi.
s2ibis2.sun4: Starting HSpice job with input gcnout.spi.
s2ibis2.sun4: Starting HSpice job with input gcxout.spi.
s2ibis2.sun4: Starting HSpice job with input rutout.spi.
s2ibis2.sun4: Starting HSpice job with input runout.spi.
s2ibis2.sun4: Starting HSpice job with input ruxout.spi.
s2ibis2.sun4: Starting HSpice job with input rdtout.spi.
s2ibis2.sun4: Starting HSpice job with input rdnout.spi.
s2ibis2.sun4: Starting HSpice job with input rdxout.spi.
s2ibis2.sun4: Starting HSpice job with input a00out.spi.
s2ibis2.sun4: Starting HSpice job with input b00out.spi.
s2ibis2.sun4: Starting HSpice job with input c00out.spi.
s2ibis2.sun4: Starting HSpice job with input x00out.spi.
s2ibis2.sun4: Starting HSpice job with input y00out.spi.
s2ibis2.sun4: Starting HSpice job with input z00out.spi.
s2ibis2.sun4: Error in analysis for pin out.
s2ibis2.sun4: Opening file tristate.ibs for writing...done.
18 <chang> cat dunout.msg
>error          ***** hspice job aborted
        5.7 real         2.4 user         0.4 sys
19 <chang> cat pctout.msg
>error          ***** hspice job aborted
        4.1 real         1.3 user         0.2 sys
20 <chang>

***********************************************************************
* End Xterm session
***********************************************************************

I also found the following inside of dunout.out:


***********************************************************************
* excerpt from dunout.out
***********************************************************************
.
.
.
**warning** both nodes of source     0:vgnds2i
            are connected together

**warning** negative-mos conductance =     0:mx22             iter=   52
vds,vgs,vbs =      -2.74         0.109         0.861
 gm,gds,gmbs,ids=     2.147E-03     7.629E-05    -1.532E-04     3.768E-03
convergence problems in dc sweep curves at   3.5000
 resimulating with dc convergence controls


**diagnostic** dc convergence failure,
resetting dcon option to 1 and retrying


**diagnostic** dc convergence failure,
resetting dcon option to 2 and retrying.


**diagnostic** although this circuit has failed to converge
to gmindc=   1.000E-12, it did converge to a gmindc=   1.000E-10
for most circuits a value of gmindc 1e-7 or less,  is acceptable




*** error ***: no convergence in dc sweep curves at   3.5000

 ### note2  represents   cm**2*um/v**2-sec  ###

 ### @      represents   v**   ###

   2*** diffusion layer process parameters ***
    rshm=   2.10  ohms/sq      cjm= 931.91u f/m**2       cjw= 156.37p f/m
     ijs=  10.00n amp/m         pj= 850.00m volts        pjw= 850.00m
volts
     mj0= 487.07m              mjw= 478.48m              wdf=   0.
meters
      ds=   0.    meters

   3*** temperature coefficient parameters ***
     tcv=   0.    meters      ltcv=   0.    meters      wtcv=   0.
meters
     bex=  -1.50  meters      lbex=   0.    meters      wbex=   0.
meters
     fex=   0.    meters      lfex=   0.    meters      wfex=   0.
meters
     trs=   0.    meters      ltrs=   0.    meters      wtrs=   0.
meters
     trd=   0.    meters      ltrd=   0.    meters      wtrd=   0.
meters

**warning** both nodes of source     0:vgnds2i
     wnb=   0.    um/v         nd0=   0.    1/v          lnd=   0.    um/v
     wnd=   0.    um/v       k2lim=   0.             version=  95.20

 ### note1  represents   cm**2/v**2-sec   ###

 ### note2  represents   cm**2*um/v**2-sec  ###

 ### @      represents   v**   ###

   2*** diffusion layer process parameters ***
    rshm=   2.10  ohms/sq      cjm= 931.91u f/m**2       cjw= 156.37p f/m
     ijs=  10.00n amp/m         pj= 850.00m volts        pjw= 850.00m
volts
     mj0= 487.07m              mjw= 478.48m              wdf=   0.
meters
      ds=   0.    meters

   3*** temperature coefficient parameters ***
     tcv=   0.    meters      ltcv=   0.    meters      wtcv=   0.
meters
     bex=  -1.50  meters      lbex=   0.    meters      wbex=   0.
meters
     fex=   0.    meters      lfex=   0.    meters      wfex=   0.
meters
     trs=   0.    meters      ltrs=   0.    meters      wtrs=   0.
meters
     trd=   0.    meters      ltrd=   0.    meters      wtrd=   0.
meters

**warning** both nodes of source     0:vgnds2i
            are connected together

**warning** negative-mos conductance =     0:mx22             iter=   52
vds,vgs,vbs =      -2.74         0.109         0.861
 gm,gds,gmbs,ids=     2.147E-03     7.629E-05    -1.532E-04     3.768E-03
convergence problems in dc sweep curves at   3.5000
 resimulating with dc convergence controls


**diagnostic** dc convergence failure,
resetting dcon option to 1 and retrying


**diagnostic** dc convergence failure,
resetting dcon option to 2 and retrying.


**diagnostic** although this circuit has failed to converge
to gmindc=   1.000E-12, it did converge to a gmindc=   1.000E-10
for most circuits a value of gmindc 1e-7 or less,  is acceptable




*** error ***: no convergence in dc sweep curves at   3.5000



******
* min pullup (output disabled) curve for model tristate_driver
 ******  dc transfer curves               tnom=  25.000 temp= 100.000
******

.
.
.

*******************************************************************
* end excerpt from dunout.out
*******************************************************************

(I'm sorry for the length of this email)

I'm wondering if anyone else has had trouble running example 2?
If so, was the error the same? and if not does anyone have an explanation
for why example 2 doesn't run properly?

And finally, has anyone ever received this error message before?

"...
s2ibis2.sun4: Analyzing component S/UNI PLUS PM5347 .
s2ibis2.sun4: Starting HSpice job with input putoutpi.spi.
s2ibis2.sun4: Data begin marker transfer not found in output file
putoutpi.out.
s2ibis2.sun4: Curve pullup not generated.
s2ibis2.sun4: Starting HSpice job with input dutoutpi.spi.
s2ibis2.sun4: Data begin marker transfer not found in output file
dutoutpi.out.
s2ibis2.sun4: Curve pullup (output disabled) not generated.
..."

Thanx for all your time.
sincerely,

roland
*************************************************************************
*Roland Chang                          | email: roland@sfu.ca           *
*Simon Fraser University               |        OR                      *
*School of Engineering Science         |        chang@pmc-sierra.bc.ca  *
*3rd year Computer Engineering Option  |                                *
*************************************************************************

 
From owner-ibis  Tue May 13 17:13:11 1997
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Date: Tue, 13 May 97 17:02:53 PDT
From: rkarthik@lsil.com (Karthigeyan Ranganathan)
Message-Id: <9705140002.AA08739@useng04>
To: ibis-users@vhdl.org
Subject: Ibis model for a Differential input receiver
Cc: rkarthik@lsil.com

Hi

I have problems when running ibis on a differential input receiver.

I am not quite sure of how to set my <filename>.s2i input file correct, especially the
usage of [Diff Pin] option in correlation with [Pin] mapping.

could someone address my concerns? / mail me a example ibis model with differential inputs.

Thanks in advance.
Regards,
Karthik.
 
From owner-ibis  Wed May 14 06:45:28 1997
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From: chu@rock.enet.dec.com
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To: ibis-users@vhdl.org
Cc: chu@rock.enet.dec.com
Apparently-To: ibis-users@vhdl.org
Subject: Re: Ibis model for differential input from rkarthik@lsil.com

Karthik:  I had a similar problem a few months ago and I asked Alan Glaser for help. 
For your info, attached below is copy of my original question and his reply.  The way 
I got around it is exactly what he suggested.  I had to make a virtual inverter in 
front of the differential input to provide the out-of-phase signal. Since timing 
(prop delay) is not utilized in the IBIS model, it makes no difference in the final 
output. I am not sure if things have changed since.  If it has, I certainly would 
like to know about it.

Jeff Chu
Digital Equipment Corp.
77 Reed Road
Hudson, MA 01749
(508)568-4197
(508)568-5195 fax
=====================================================================================
=====================================================================================
Hi

I have problems when running ibis on a differential input receiver.

I am not quite sure of how to set my <filename>.s2i input file correct, especially 
the
usage of [Diff Pin] option in correlation with [Pin] mapping.

could someone address my concerns? / mail me a example ibis model with differential 
inputs.

Thanks in advance.
Regards,
Karthik.

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% Cc: rkarthik@lsil.com

====================================================================================
====================================================================================
     
From:	CRL::"awglaser@eos.ncsu.edu"   25-FEB-1997 11:48:57.33
To:	rock::chu
CC:	awglaser@eos.ncsu.edu (Alan Wolfram Glaser)
Subj:	Re: your mail

> Alan:  Please help me with the following on your spice to ibis conversion program.
> How do you specify differential inputs together with an enable pin in the pin list? 
 The 
> six valid input pin formats do not include the option of differential inputs.  In 
this 
> particular circuit I have, I need to control the two differential inputs to make 
the output   
> swing.  How do I do it?
> 
> Thank you very much for your help
> Jeff Chu
> Digital Equipment Corp.
> 77 Reed Rpad
> Hudson, MA
> 01749
> (508)568-4197
> (508)568-5195 fax  


Jeff:

Unfortunately, s2ibis2 doesn't have an automatic way to control two
inputs. The only thing I can suggest it to let s2ibis2 create the input
files, edit them by hand to insert the source for the second input,
delete the output files (*.out) then re-run s2ibis2. (It will use the
SPICE files that already exist.)

Hope this helps.

Regards,

-- 
Alan Glaser                         "It's not a competition,
ECE Dept.                            it's just a mint..." - K
North Carolina State University

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From owner-ibis  Wed May 14 08:57:27 1997
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From: huq@rockie.nsc.com (Syed Huq)
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To: ibis-users@vhdl.org, roland@sfu.ca
Subject: Re: s2ibis2 error messages
Cc: huq@rockie.nsc.com
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Roland,

I am attaching a mail msg from the reflector where this was
detected and solved earlier. It has to do with naming the
gnd node and decreasing the sweep ranges.(Pls refer to mail).

I also saw the 'Data Begin marker' msg before and I think
it related to wrong syntax in the .s2i file.

Regards,
Syed.

> From owner-ibis@server.vhdl.org Tue May 13 18:09:36 1997
> Date: Tue, 13 May 1997 16:50:49 -0700 (PDT)
> From: Roland James Chang <roland@sfu.ca>
> X-Sender: roland@fraser
> To: ibis-users@vhdl.org
> Subject: s2ibis2 error messages
> Content-Type> : > TEXT/PLAIN> ; > charset=US-ASCII> 
> Content-Transfer-Encoding: QUOTED-PRINTABLE
> 
> first of all, I would like to extend my thanx to all that replied to my
> last email seeking help with the s2ibis2 utility.  I've now obtained the
> s2ibis2 utility and have been playing with it for the past few days. =20
> 
> I am a university student on a work term at a leading supplier of ATM
> components, and am finding it quite challenging to learn the entire IBIS
> modelling standard in the span of a couple of days, so please bear with
> me, if any of my questions sound too simple (or even stupid) :-)
> 
> I've been working through the examples (1-4) provided with the s2ibis2
> utility but I cannot get example 2 to work (which deals with a simple
> tristate buffer) It seems to be running into DC convergence problems.
> This is the output that I get when I run the s2ibis2 utility on example 2
> (with tristate.s2i setup for HSPICE):
> 
> ***************************************************************************=
> *
> * session on an xterm follows
> ***************************************************************************=
> *
> 17 <chang> s2ibis2.sun4 tristate.s2i
> 
> s2ibis2.sun4 v1.1 -- North Carolina State University
> s2ibis2.sun4: Reading input file tristate...done.
> s2ibis2.sun4: Analyzing component MCM Trisate Driver .
> s2ibis2.sun4: Starting HSpice job with input putout.spi.
> s2ibis2.sun4: Starting HSpice job with input punout.spi.
> s2ibis2.sun4: Starting HSpice job with input puxout.spi.
> s2ibis2.sun4: Starting HSpice job with input dutout.spi.
> s2ibis2.sun4: Starting HSpice job with input dunout.spi.
> s2ibis2.sun4: Spice run (MIN) aborted.  See file dunout.msg for
> information.
>          continuing with MAX run.
> s2ibis2.sun4: Starting HSpice job with input duxout.spi.
> s2ibis2.sun4: Starting HSpice job with input pdtout.spi.
> s2ibis2.sun4: Starting HSpice job with input pdnout.spi.
> s2ibis2.sun4: Starting HSpice job with input pdxout.spi.
> s2ibis2.sun4: Starting HSpice job with input ddtout.spi.
> s2ibis2.sun4: Starting HSpice job with input ddnout.spi.
> s2ibis2.sun4: Starting HSpice job with input ddxout.spi.
> s2ibis2.sun4: Starting HSpice job with input pctout.spi.
> s2ibis2.sun4: Spice run (TYP) aborted.  See file pctout.msg for
> information.
>          Curve power clamp not generated.
> s2ibis2.sun4: Starting HSpice job with input gctout.spi.
> s2ibis2.sun4: Starting HSpice job with input gcnout.spi.
> s2ibis2.sun4: Starting HSpice job with input gcxout.spi.
> s2ibis2.sun4: Starting HSpice job with input rutout.spi.
> s2ibis2.sun4: Starting HSpice job with input runout.spi.
> s2ibis2.sun4: Starting HSpice job with input ruxout.spi.
> s2ibis2.sun4: Starting HSpice job with input rdtout.spi.
> s2ibis2.sun4: Starting HSpice job with input rdnout.spi.
> s2ibis2.sun4: Starting HSpice job with input rdxout.spi.
> s2ibis2.sun4: Starting HSpice job with input a00out.spi.
> s2ibis2.sun4: Starting HSpice job with input b00out.spi.
> s2ibis2.sun4: Starting HSpice job with input c00out.spi.
> s2ibis2.sun4: Starting HSpice job with input x00out.spi.
> s2ibis2.sun4: Starting HSpice job with input y00out.spi.
> s2ibis2.sun4: Starting HSpice job with input z00out.spi.
> s2ibis2.sun4: Error in analysis for pin out.
> s2ibis2.sun4: Opening file tristate.ibs for writing...done.
> 18 <chang> cat dunout.msg
> >error          ***** hspice job aborted
>         5.7 real         2.4 user         0.4 sys
> 19 <chang> cat pctout.msg
> >error          ***** hspice job aborted
>         4.1 real         1.3 user         0.2 sys
> 20 <chang>
> 
> ***********************************************************************
> * End Xterm session
> ***********************************************************************
> 
> I also found the following inside of dunout.out:
> 
> 
> ***********************************************************************
> * excerpt from dunout.out
> ***********************************************************************
> =2E
> =2E
> =2E
> **warning** both nodes of source     0:vgnds2i
>             are connected together
> 
> **warning** negative-mos conductance =3D     0:mx22             iter=3D   5=
> 2
> vds,vgs,vbs =3D      -2.74         0.109         0.861
>  gm,gds,gmbs,ids=3D     2.147E-03     7.629E-05    -1.532E-04     3.768E-03
> convergence problems in dc sweep curves at   3.5000
>  resimulating with dc convergence controls
> 
> 
> **diagnostic** dc convergence failure,
> resetting dcon option to 1 and retrying
> 
> 
> **diagnostic** dc convergence failure,
> resetting dcon option to 2 and retrying.
> 
> 
> **diagnostic** although this circuit has failed to converge
> to gmindc=3D   1.000E-12, it did converge to a gmindc=3D   1.000E-10
> for most circuits a value of gmindc 1e-7 or less,  is acceptable
> 
> 
> 
> 
> *** error ***: no convergence in dc sweep curves at   3.5000
> 
>  ### note2  represents   cm**2*um/v**2-sec  ###
> 
>  ### @      represents   v**   ###
> 
>    2*** diffusion layer process parameters ***
>     rshm=3D   2.10  ohms/sq      cjm=3D 931.91u f/m**2       cjw=3D 156.37p=
>  f/m
>      ijs=3D  10.00n amp/m         pj=3D 850.00m volts        pjw=3D 850.00m
> volts
>      mj0=3D 487.07m              mjw=3D 478.48m              wdf=3D   0.
> meters
>       ds=3D   0.    meters
> 
>    3*** temperature coefficient parameters ***
>      tcv=3D   0.    meters      ltcv=3D   0.    meters      wtcv=3D   0.
> meters
>      bex=3D  -1.50  meters      lbex=3D   0.    meters      wbex=3D   0.
> meters
>      fex=3D   0.    meters      lfex=3D   0.    meters      wfex=3D   0.
> meters
>      trs=3D   0.    meters      ltrs=3D   0.    meters      wtrs=3D   0.
> meters
>      trd=3D   0.    meters      ltrd=3D   0.    meters      wtrd=3D   0.
> meters
> 
> **warning** both nodes of source     0:vgnds2i
>      wnb=3D   0.    um/v         nd0=3D   0.    1/v          lnd=3D   0.   =
>  um/v
>      wnd=3D   0.    um/v       k2lim=3D   0.             version=3D  95.20
> 
>  ### note1  represents   cm**2/v**2-sec   ###
> 
>  ### note2  represents   cm**2*um/v**2-sec  ###
> 
>  ### @      represents   v**   ###
> 
>    2*** diffusion layer process parameters ***
>     rshm=3D   2.10  ohms/sq      cjm=3D 931.91u f/m**2       cjw=3D 156.37p=
>  f/m
>      ijs=3D  10.00n amp/m         pj=3D 850.00m volts        pjw=3D 850.00m
> volts
>      mj0=3D 487.07m              mjw=3D 478.48m              wdf=3D   0.
> meters
>       ds=3D   0.    meters
> 
>    3*** temperature coefficient parameters ***
>      tcv=3D   0.    meters      ltcv=3D   0.    meters      wtcv=3D   0.
> meters
>      bex=3D  -1.50  meters      lbex=3D   0.    meters      wbex=3D   0.
> meters
>      fex=3D   0.    meters      lfex=3D   0.    meters      wfex=3D   0.
> meters
>      trs=3D   0.    meters      ltrs=3D   0.    meters      wtrs=3D   0.
> meters
>      trd=3D   0.    meters      ltrd=3D   0.    meters      wtrd=3D   0.
> meters
> 
> **warning** both nodes of source     0:vgnds2i
>             are connected together
> 
> **warning** negative-mos conductance =3D     0:mx22             iter=3D   5=
> 2
> vds,vgs,vbs =3D      -2.74         0.109         0.861
>  gm,gds,gmbs,ids=3D     2.147E-03     7.629E-05    -1.532E-04     3.768E-03
> convergence problems in dc sweep curves at   3.5000
>  resimulating with dc convergence controls
> 
> 
> **diagnostic** dc convergence failure,
> resetting dcon option to 1 and retrying
> 
> 
> **diagnostic** dc convergence failure,
> resetting dcon option to 2 and retrying.
> 
> 
> **diagnostic** although this circuit has failed to converge
> to gmindc=3D   1.000E-12, it did converge to a gmindc=3D   1.000E-10
> for most circuits a value of gmindc 1e-7 or less,  is acceptable
> 
> 
> 
> 
> *** error ***: no convergence in dc sweep curves at   3.5000
> 
> 
> 
> ******
> * min pullup (output disabled) curve for model tristate_driver
>  ******  dc transfer curves               tnom=3D  25.000 temp=3D 100.000
> ******
> 
> =2E
> =2E
> =2E
> 
> *******************************************************************
> * end excerpt from dunout.out
> *******************************************************************
> 
> (I'm sorry for the length of this email)
> 
> I'm wondering if anyone else has had trouble running example 2?
> If so, was the error the same? and if not does anyone have an explanation
> for why example 2 doesn't run properly?
> 
> And finally, has anyone ever received this error message before?
> 
> "...
> s2ibis2.sun4: Analyzing component S/UNI PLUS PM5347 .
> s2ibis2.sun4: Starting HSpice job with input putoutpi.spi.
> s2ibis2.sun4: Data begin marker transfer not found in output file
> putoutpi.out.
> s2ibis2.sun4: Curve pullup not generated.
> s2ibis2.sun4: Starting HSpice job with input dutoutpi.spi.
> s2ibis2.sun4: Data begin marker transfer not found in output file
> dutoutpi.out.
> s2ibis2.sun4: Curve pullup (output disabled) not generated.
> =2E.."
> 
> Thanx for all your time.
> sincerely,
> 
> roland
> *************************************************************************
> *Roland Chang                          | email: roland@sfu.ca           *
> *Simon Fraser University               |        OR                      *
> *School of Engineering Science         |        chang@pmc-sierra.bc.ca  *
> *3rd year Computer Engineering Option  |                                *
> *************************************************************************
> 
> 
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M>71H:6YG(')A;BX@3V@L($D@:&%D('1O(&9I>"!T:&4@(F=N9"(*;F]D92!B
M>2!C86QL:6YG(&ET(")M>6=N9"(L('-T:6QL('1Y:6YG(&ET('1O(&YO9&4@
M,"!I;B!H<W!I8V4N(%1H:7,@=V%S"F9O<B!E>#(@:6X@=&AE(&5X86UP;&5S
M+@H*27,@=&AE<F4@86YY=V%Y('1O(&QI;6ET('1H92!A=71O;6%T:6-A;&QY
M(&=E;F5R871E9"!S=V5E<"!R86YG92!I;B!T:&4*+G,R:2!F:6QE/PH*5&AI
M<R!W87,@=VET:"!H<W!I8V4@.38N,2X@4V]L87)I<RX*"DUA<FL@4VEM<'-O
M;B!W<F]T92!T:&%T('1H92!D96-K($D@871T86-H960@<F%N(&9I;F4@:6X@
M:'-P:6-E(#DU+C(L"E-U;D]3+@H*0G)O8VL@2&%N;FEB86P@=W)O=&4Z"CX@
M"CX@2&DL"CX@"CX@22=V92!B965N('1R>6EN9R!T;R!R=6X@<V]M92!O9B!T
M:&4@97AA;7!L97,@:6X@=&AE('8Q+C$@9&ES=')I8G5T:6]N(&]F"CX@<S)I
M8FES,BX@22=M('5S:6YG($AS<&EC92X*/B!))VT@861M:71T961L>2!N;W0@
M=F5R>2!F86UI;&EA<B!W:71H($AS<&EC92!S:6YC92!W92!H879E(&]U<B!O
M=VX*/B!I;G1E<FYA;"!3<&EC92X@56YF;W)T=6YA=&5L>2!C;VYV97)I;G1I
M;F<@:'-P:6-E('1O(&]U<B!I;G1E<FYA;"!3<&EC90H^(&ES(&YO="!A;B!O
M<'1I;VX@870@=&AE(&UO;65N="Y)(&=E="!T:&4@9F]L;&]W:6YG('-T86YD
M87)D(&]U='!U=#H*/B */B!;<V%L;W!E.F5X,ET*/B O<')O:B]C864O8G)O
M8VMH+V1A=&$O:6-X+VEB:7,O=&]O;',O<S)I8FES,B]B:6XO<S)I8FES,BYS
M;VQA<FES"CX@=')I<W1A=&4N<S)I"CX@"CX@<S)I8FES,BYS;VQA<FES('8Q
M+C$@+2T@3F]R=&@@0V%R;VQI;F$@4W1A=&4@56YI=F5R<VET>0H^(',R:6)I
M<S(N<V]L87)I<SH@4F5A9&EN9R!I;G!U="!F:6QE('1R:7-T871E+BXN9&]N
M92X*/B!S,FEB:7,R+G-O;&%R:7,Z($%N86QY>FEN9R!C;VUP;VYE;G0@34--
M(%1R:7-A=&4@1')I=F5R("X*/B!S,FEB:7,R+G-O;&%R:7,Z(%-T87)T:6YG
M($A3<&EC92!J;V(@=VET:"!I;G!U="!P=71O=70N<W!I+@H^(',R:6)I<S(N
M<V]L87)I<SH@4W!I8V4@<G5N("A465 I(&%B;W)T960N("!3964@9FEL92!P
M=71O=70N;7-G(&9O<@H^(&EN9F]R;6%T:6]N+@H^(" @(" @(" @($-U<G9E
M('!U;&QU<"!N;W0@9V5N97)A=&5D+@H^(',R:6)I<S(N<V]L87)I<SH@4W1A
M<G1I;F<@2%-P:6-E(&IO8B!W:71H(&EN<'5T(&1U=&]U="YS<&DN"CX@<S)I
M8FES,BYS;VQA<FES.B!3<&EC92!R=6X@*%194"D@86)O<G1E9"X@(%-E92!F
M:6QE(&1U=&]U="YM<V<@9F]R"CX@:6YF;W)M871I;VXN"CX@(" @(" @(" @
M0W5R=F4@<'5L;'5P("AO=71P=70@9&ES86)L960I(&YO="!G96YE<F%T960N
M"CX@"CX@06YY(&-L=64@87,@=&\@=VAY('1H92!P=6QL=7 @86YD('!U;&QD
M;W=N(&-U<G9E<R!A<F5N)W0@9V5N97)A=&5D+B!)"CX@;&]O:V5D(&EN('1H
M92!P=71O=70N<W!I"CX@9FEL92!A;F0@:70@;&]O:W,@3TL@=&\@;64@8G5T
M($DG;&P@871T86-H(&ET+B!4:&4@9FEL92!P=71O=70N;7-G(&ES"CX@=F5R
M>2!S:&]R="!A;F0@;&]O:W,@;&EK90H^('1H:7,Z"CX@"CX@7D<^97)R;W(@
M(" @(" @(" @*BHJ*BH@:'-P:6-E(&IO8B!A8F]R=&5D"CX@"CX@<F5A;" @
M(" @(" @-RXP"CX@=7-E<B @(" @(" @,"XU"CX@<WES(" @(" @(" @,"XR
M"CX@"CX@5&AA;FMS(&9O<B!A;GD@:6YS:6=H="!Y;W4@;6%Y(&AA=F4N($DG
M=F4@9FED9&QE9"!A<F]U;F0@<75I=&4@82!B:70@86YD"CX@86T@:G5S="!N
M;W0@<V5E:6YG('1H90H^('!R;V)L96T@;W(@;W9E<G-I9VAT+@H*+2T@"D)R
M;V-K($AA;FYI8F%L"DAA<F1W87)E($1E<VEG;B!%;F=I;F5E<@I496MT<F]N
M:7@L($EN8RX*0F5A=F5R=&]N+"!/<F5G;VX*"@HB06YY(&ED96%S(&]R(&]P
M:6YI;VYS(&5X<')E<W-E9"!H97)E(&1O(&YO="!N96-E<W-A<FEL>0H@(" @
M(" @<F5F;&5C="!T:&4@:61E87,@;W(@;W!I;FEO;G,@;V8@;7D@96UP;&]Y
&97(N(@H*
 
end
 
From owner-ibis  Thu May 15 08:55:26 1997
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From: awglaser@eos.ncsu.edu
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          by c11167-343dan.ece.ncsu.edu (8.8.4/EC02Jan97)
	  id LAA19597; Thu, 15 May 1997 11:54:08 -0400 (EDT)
Message-Id: <199705151554.LAA19597@c11167-343dan.ece.ncsu.edu>
Subject: Re: s2ibis2 error messages
To: roland@sfu.ca (Roland James Chang)
Date: Thu, 15 May 1997 11:54:07 -0400 (EDT)
Cc: ibis-users@vhdl.org
In-Reply-To: <Pine.SGI.3.95.970513160650.2290A-100000@fraser> from "Roland James Chang" at May 13, 97 04:50:49 pm
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> And finally, has anyone ever received this error message before?
> 
> "...
> s2ibis2.sun4: Analyzing component S/UNI PLUS PM5347 .
> s2ibis2.sun4: Starting HSpice job with input putoutpi.spi.
> s2ibis2.sun4: Data begin marker transfer not found in output file
> putoutpi.out.
> s2ibis2.sun4: Curve pullup not generated.
> s2ibis2.sun4: Starting HSpice job with input dutoutpi.spi.
> s2ibis2.sun4: Data begin marker transfer not found in output file
> dutoutpi.out.
> s2ibis2.sun4: Curve pullup (output disabled) not generated.
> =2E.."

Roland:

S2ibis2 looks for certain "marker" words or symbols that denote the
start of the data in the output file. In this case, since you're using
HSPICE, s2ibis2 looks for the word "transfer" in the output file, and
marks where it finds it as the start of data. (It's not actually the
exact beginning of the data, but it allows s2ibis2 to skip over the
huge "prelude" portion of the output file.) Basically, the error
message just means that s2ibis2 couldn't find the marker it was
looking for.

You can find all of the markers it uses in the file s2istrng.h. The
variable names are VIDataBeginMarker, tranDataBeginMarker, and
dataEndMarker. Each variable has five possible values, corresponding
to the various flavors of SPICE simulator (HSPICE, PSpice, SPICE2,
Spice3 and Spectre, in that order).

Hope this helps.

Regards,

-- 
Alan Glaser                         "It's not a competition,
ECE Dept.                            it's just a mint..." - K
North Carolina State University
 
From owner-ibis  Thu May 15 11:10:52 1997
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From: harish.patel@tempe.vlsi.com
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Date: Thu, 15 May 1997 11:09:33 -0700
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To: ibis-users@vhdl.org
Subject: Problem regarding running s2ibis2 program
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--5ad_11f7-5662_7113-3429_28eb
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Content-MD5: 3LnrSh9LGFsZtcqD3DoPpw==
X-Sun-Data-Type: text

Hello,

NEED HELP...

I am trying to use s2ibis2 program and I am having problem executing it.

I created a file test.s2i and pad.sp and tried to run it and I am getting
following error:

s2ibis2.solaris v1.1 -- North Carolina State University
s2ibis2.solaris: Reading input file test...done.
s2ibis2.solaris: Analyzing component PHXIO .
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for pullup curve.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for pullup (output disabled) curve.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for pulldown curve.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for pulldown (output disabled) 
curve.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for power clamp curve.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for ground clamp curve.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Error in analysis for pin out.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for power clamp curve.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for ground clamp curve.
s2ibis2.solaris: Error in analysis for pin in.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for power clamp curve.
s2ibis2.solaris: Unable to open file pad.sp for reading.
s2ibis2.solaris: No such file or directory
s2ibis2.solaris: Couldn't set up Spice file for ground clamp curve.
s2ibis2.solaris: Error in analysis for pin oen.
s2ibis2.solaris: Opening file test.ibs for writing...done.


First of all it's not able to read file pad.sp from my working dir.

Can someone suggest something??

Thanks in advance.
--5ad_11f7-5662_7113-3429_28eb
Content-Type: application/octet-stream; name=test.s2i
Content-Transfer-Encoding: 7bit
Content-MD5: h8uE/ukx5zdeZN6RRt2HwQ==
Content-Description: test.s2i
Content-Disposition: attachment; filename=test.s2i

|
| s2ibis2 command file
|
[IBIS Ver]     2.1
[File rev]     0

[Spice type]		hspice

[Component] 	 PHXIO

[Spice file] 	pad.sp

[Voltage range]	     3.3   3.0   3.6


[Pin]
vdd  vdd   VCC   POWER
gnd  gnd   GND   GND 
out out out   ptx5c50z    200.0m  5.0nh  1.5pf
-> in oen
in  in   in   Input1
oen  oen  oen   Enable1



[Model] ptx5c50z
[Model type] 3-state
[Enable] Active-Low
[Model File]	model.typ	model.min	model.max
[Vinl]		0.8
[Vinh]		2.0


[Model]		Input1
[Model type]	Input
[Model File]	model.typ	model.min	model.max
[Vinl]		0.8
[Vinh]		2.0


[Model]		Enable1
[Model type]	Input
[Polarity]	Inverting
[Model File]	model.typ	model.min	model.max
[Vinl]		0.8
[Vinh]		2.0


--5ad_11f7-5662_7113-3429_28eb
Content-Type: application/octet-stream; name=pad.sp
Content-Transfer-Encoding: 7bit
Content-MD5: 0WGSXty9NbG67lSu3JoPYg==
Content-Description: pad.sp
Content-Disposition: attachment; filename=pad.sp

*****  s2ibis SPICE INPUT DECK   *****

.options LVLTIM=3 DVDT=2 ACCURATE gmindc = 1.0e-7

.inc "/home/hpatel/ibis/pad5_model/vsc7p38/vcmn5_rev2p1_diodes.inc"
.inc "/clibs/process/vlsi/cmn5/vcmn5_rev2p1.lib"
.include `/home/hpatel/bin/transistors.sub`

X11  vdd  gnd  in out11 oen ptx5c50z  
   
.include `spi/ptx5c50z.spi`

***.END
--5ad_11f7-5662_7113-3429_28eb--


___________________________________________________________________
  Harish Patel                           VLSI Technology, Inc.                 
  harish.patel@tempe.vlsi.com            Computing Products Group               
  602-752-6202/Fax:602-752-6002          Tempe, Arizona                        
___________________________________________________________________

A policy is a temporary creed liable to be changed, but while
it holds good it has to be pursued with apostolic zeal. 
                                            -- Mahatma Gandhi
 
From owner-ibis  Fri May 16 16:04:58 1997
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Date: Fri, 16 May 1997 16:04:02 -0700 (PDT)
From: Roland James Chang <roland@sfu.ca>
X-Sender: roland@fraser
To: ibis-users@vhdl.org
Subject: HSPICE incorrect V-I tables?
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Hello, I am having trouble trying to get output I obtained using
HSPICE to match the example files provided with the s2ibis2 utility
(generated with spectre supposedly)

there are four examples, and likewise four example .ibs files provided
with the s2ibis2 utility,

my_buf.ibs
my_tri.ibs
my_chip.ibs
my_mpow.ibs

Take for example my_chip.ibs,

When I generated the chip.ibs file for it, the tables for the model
--input-- matched the example my_chip.ibs file fine as shown below in
shortened form: (POWER_clamp matched as well)


******** my_chip.ibs file (included with s2ibis2 utility) *******
.
.
.

|************************************************************************
|                              Model input
|************************************************************************
|
[Model]          input
Model_type       Input
C_comp           5.00pF              5.00pF              5.00pF
|
|
[Temperature Range]       27.00               100.00              0.000
[Voltage Range]           3.30V               3.00V               3.60V
[GND_clamp]
| voltage     I(typ)              I(min)              I(max)
|
  -3.30      -30.81mA            -32.43mA            -30.24mA
  -3.20      -29.63mA            -31.24mA            -29.05mA
  -3.10      -28.44mA            -30.06mA            -27.86mA
  -3.00      -27.25mA            -28.87mA            -26.67mA
  -2.90      -26.07mA            -27.69mA            -25.48mA



******** chip.ibs which I generated using HSPICE *******
.
.
.

|************************************************************************
|                              Model input
|************************************************************************
|
[Model]          input
Model_type       Input
C_comp           5.00pF              5.00pF              5.00pF
|
|
[Temperature Range]       27.00               100.00              0.000
[Voltage Range]           3.30V               3.00V               3.60V
[GND_clamp]
| voltage     I(typ)              I(min)              I(max)
|
  -3.30      -30.91mA            -32.27mA            -30.42mA
  -3.20      -29.72mA            -31.09mA            -29.23mA
  -3.10      -28.53mA            -29.90mA            -28.04mA
  -3.00      -27.35mA            -28.72mA            -26.85mA
  -2.90      -26.16mA            -27.53mA            -25.67mA
  -2.80      -24.98mA            -26.35mA            -24.48mA



However, when I looked at the V_I tables generated for the model
--driver-- and --tristate driver-- I found that my HSPICE files had
ridiculously huge values:



******** my_chip.ibs file (included with s2ibis2 utility) *******
.
.
.

|************************************************************************
|                              Model driver
|************************************************************************
|
[Model]          driver
Model_type       Output
Polarity         Non-Inverting
C_comp           5.00pF              5.00pF              5.00pF
|
|
[Temperature Range]       27.00               100.00              0.000
[Voltage Range]           3.30V               3.00V               3.60V
[Pulldown]
| voltage     I(typ)              I(min)              I(max)
|
  -3.30       -1.94A              -1.61A              -2.12A
  -3.10       -1.78A              -1.48A              -1.94A
  -2.90       -1.62A              -1.35A              -1.76A
  -2.70       -1.46A              -1.22A              -1.59A
  -2.50       -1.30A              -1.10A              -1.41A
  -2.30       -1.14A              -0.97A              -1.23A
  -2.10       -0.98A              -0.84A              -1.06A
.
.
.
|
|************************************************************************
|                         Model tristate_driver
|************************************************************************
|
[Model]          tristate_driver
Model_type       3-state
Polarity         Non-Inverting
Enable           Active-Low
C_comp           5.00pF              5.00pF              5.00pF
|
[GND_clamp]
| voltage     I(typ)              I(min)              I(max)
|
  -3.30       -1.88A              -1.57A              -2.04A
  -3.20       -1.80A              -1.51A              -1.96A
  -3.10       -1.72A              -1.44A              -1.87A
  -3.00       -1.64A              -1.38A              -1.78A
  -2.90       -1.56A              -1.31A              -1.69A
  -2.80       -1.48A              -1.25A              -1.60A
  -2.70       -1.40A              -1.19A              -1.52A
  -2.60       -1.32A              -1.12A              -1.43A
  -2.50       -1.24A              -1.06A              -1.34A
.
.
.



******** chip.ibs which I generated using HSPICE *******
.
.
.

|************************************************************************
|                              Model driver
|************************************************************************
|
[Model]          driver
Model_type       Output
Polarity         Non-Inverting
C_comp           5.00pF              5.00pF              5.00pF
|
|
[Temperature Range]       27.00               100.00              0.000
[Voltage Range]           3.30V               3.00V               3.60V
[Pulldown]
| voltage     I(typ)              I(min)              I(max)
|
  -3.30     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -3.10     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -2.90     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -2.70     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -2.50     -3.777e+21A         -3.526e+24A         -3.957e+19A
  -2.30     -3.777e+21A         -7.015e+21A         -3.957e+19A
  -2.10     -3.777e+21A         -1.395e+19A         -3.957e+19A
.
.
.
|************************************************************************
|                         Model tristate_driver
|************************************************************************
|
[Model]          tristate_driver
Model_type       3-state
Polarity         Non-Inverting
Enable           Active-Low
C_comp           5.00pF              5.00pF              5.00pF
|
[GND_clamp]
| voltage     I(typ)              I(min)              I(max)
|
  -3.30     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -3.20     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -3.10     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -3.00     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -2.90     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -2.80     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -2.70     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -2.60     -3.777e+21A         -1.000e+25A         -3.957e+19A
  -2.50     -3.777e+21A         -3.526e+24A         -3.957e+19A
  -2.40     -3.777e+21A         -1.573e+23A         -3.957e+19A 
.
.
.

I think someone mentioned this in their replies to my previous posts, but
it was a short reply.  Anyone experience this problem?(and why does it
happen?) And if so, how did you correct it?

Once again, many thanx! 
(and sorry for all the traffic!)

roland


*************************************************************************
*Roland Chang                          | email: roland@sfu.ca           *
*Simon Fraser University               |        OR                      *
*School of Engineering Science         |        chang@pmc-sierra.bc.ca  *
*3rd year Computer Engineering Option  |                                *
*************************************************************************


 
From owner-ibis  Mon May 19 07:23:14 1997
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From: Girma Nebiyou <GirmaN@rnd3.indy.tce.com>
To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>
Subject: s2ibis2 for NT
Date: Mon, 19 May 97 09:21:00 CST
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Hello,
 Are there any working examples of  IBIS models generated using s2ibis2   
(NT ). I would appereciate it
if anyone who has used the program contacts me.
     Nebiyou Girma  
 
From owner-ibis  Tue May 20 13:02:58 1997
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Date: Tue, 20 May 1997 13:02:00 -0700 (PDT)
From: Roland James Chang <roland@sfu.ca>
X-Sender: roland@fraser
To: ibis-users@vhdl.org
Subject: SPICE Convergence Tricks - Consequences?
Message-ID: <Pine.SGI.3.95.970520130047.16424A-100000@fraser>
MIME-Version: 1.0
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Once again, a big thanks to all who replied to my last question. :-)
I've been using several tricks to try to solve SPICE convergence
problems:

-adding a 0.001ohm resistor in seris with the stimulating source
-increasing the value of the ITL1 to 300-500. (more iterations allowed)
-relaxing ABSTOL
-decreasing the sweep of the stimulus (I couldn't quite get this one to
work)

Many people mentioned that convergence problems are quite common, I would
like to know how common are they?

Furthermore, I am curious if anyone has a convergence fix that works
everytime, as it seems tedious to try to get things to converge everytime
just by trial and error fixes.

Also, what kinds of side-effects, or problems (in terms of IBIS
modelling) have people encountered by forcing the analysis to converge via
fancy SPICE tricks?

One last question regards clarification about typ, min, and max
curves.  When one is generating curves for the typical case,
suppose the typical case passes but both the min and max fail, the columns
should read NA for min and max right? Now should I go back and try to
tweak the min and max to converge? OR are some curves meant to only work
for the typical case? 


Many thanks in advance,
Regards,

roland

*************************************************************************
*Roland Chang                          | email: roland@sfu.ca           *
*Simon Fraser University               |        OR                      *
*School of Engineering Science         |        chang@pmc-sierra.bc.ca  *
*3rd year Computer Engineering Option  |                                *
*************************************************************************







 
From owner-ibis  Tue May 20 17:56:41 1997
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Date: Tue, 20 May 97 17:55 PDT
From: bob@icx.com ( Bob Ross)
To: ibis-users@vhdl.org
Subject: UPDATED ibischk2+ EXECUTABLES

To IBIS Users:

A new Version of ibischk2+ executables is now available on vhdl.org
under /pub/ibis/ibschk2+.  They are designated Version2.1.4.

The new versions replace the Version2.1.3 executables that were
stored in the respective operating system directories.

The new versions make the Open_* device Waveform endpoint testing
more robust.  They also issue warnings if [Pullup] or [Pulldown]
tables which are expected to contain values of 0 or not exist 
actually contain other numerical values.

Thanks to Chris Rokusek of Quad Design/Viewlogic for making these
fixes.

Bob Ross
Interconnectix
 
From owner-ibis  Wed May 21 05:57:47 1997
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Date: Wed, 21 May 97 08:31:00 EDT
From: Andy Ingraham  21-May-1997 0823 <ingraham@wrksys.ENET.dec.com>
To: mail11:;;@us8rmc.bb.dec.com@us8rmc.bb.dec.com@unknown.domain (us8rmc::"roland@sfu.ca roland james chang")
Cc: ibis-users@vhdl.org, ingraham@wrksys.ENET.dec.com
Apparently-To: ibis-users@vhdl.org, roland@sfu.ca (roland james chang)
Subject: Re: SPICE Convergence Tricks - Consequences?

Roland Chang asked:

> Many people mentioned that convergence problems are quite common, I would
> like to know how common are they?

Depends greatly on the semiconductor models, and on whose SPICE you
are using.  Everyone gets them eventually.


> Furthermore, I am curious if anyone has a convergence fix that works
> everytime, as it seems tedious to try to get things to converge everytime
> just by trial and error fixes.

You will never find a magic fix that works every time.  Well, I
suppose you could fully relax ABSTOL and the other *TOL parameters to
the point that SPICE just doesn't care about accuracy anymore; but
even then it might have convergence problems of a different nature.

There are all sorts of things lurking in SPICE simulations that cause
misconvergence.  Some may be called bugs in SPICE itself, or in the
semiconductor model equations and algorithms (such as discontinuities
in the formulas).  Others are artifacts of how we discretely sample a
continuous world, and how computers manipulate data.

Generally speaking, though, a few convergence tricks may work for most
problems you encounter with one set of semiconductor models.  Now if
your simulations involve models from several different vendors, then
SPICE may keep you on your toes.


> Also, what kinds of side-effects, or problems (in terms of IBIS
> modelling) have people encountered by forcing the analysis to converge via
> fancy SPICE tricks?

A general observation, not specific to IBIS modeling:  The results of
ANY SPICE simulation are never gospel.  Whether you use no "tricks" or
you use several, the results are just as circumspect.  Helping SPICE
converge can make its results more accurate, or less accurate. 
(Relaxing ABSTOL by orders of magnitude probably does not make it more
accurate.)

I have had SPICE simulations that converged to the wrong result (off
by several volts!), when no "tricks" were used.

Some of these "tricks" are already built into SPICE itself.  The SPICE
developers tailored its algorithms and parameters to give reasonable
results over a set of benchmark circuits they had.  The small resistor
in series with voltage sources is already used by SPICE to aid convergence
when you force initial conditions via the .NODESET or .IC statements.


> One last question regards clarification about typ, min, and max
> curves.  When one is generating curves for the typical case,
> suppose the typical case passes but both the min and max fail, the columns
> should read NA for min and max right? Now should I go back and try to
> tweak the min and max to converge? OR are some curves meant to only work
> for the typical case? 

Min and max curves ought to represent the extremes of what your device
will do.  If you can't get these by measurement or simulation, and you
care about having a model that shows those extremes, you need to
approximate, by whatever means possible.

If the best you can do is to shift the typ curves some amount,
up/down/left/right, it'll do.

Personally, I'd try to get the simulations to work.  Maybe this
problem points to something fundamentally wrong with the models
themselves, which could make even the typ curves wrong.

Regards,
Andy Ingraham
 
From owner-ibis  Wed May 21 11:32:07 1997
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From: zheng@symmetry.com (Zheng SHI)
Message-Id: <9705211718.AA29225@ symmetry.com>
To: roland@sfu.ca, ingraham@wrksys.enet.dec.com
Subject: Re: SPICE Convergence Tricks - Consequences?
Cc: ibis-users@vhdl.org


in my experince, the convergence problems are often caused by 
the SPICE models of the clamping diodes, which have ideal value 
RS=0. because the I/V curve of the diodes is a pure exp() function,
SPICE doesn't converge with the extreme large diode current,
for example, 1e+20A.

          o VCC
          |
        -----
         / \   <-------RS=0
        /___\
I/O port  |
o---------o <------Voltage Range:(-2*Vpower to +2*Vpower)
          |
        -----
         / \   <-------RS=0
        /___\
          |
          |
          o VEE or GND


 
From owner-ibis  Wed May 28 17:24:17 1997
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From: Roland Chang <roland_chang@pmc-sierra.bc.ca>
To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>,
        "'ibis-info@vhdl.org'"
	 <ibis-info@vhdl.org>
Subject: RE: S2ibis2 --  inputs with pull-up resistors, bi-directionals, Rising Waveforms, Falling Waveforms, etc.
Date: Wed, 28 May 1997 17:23:54 -0700
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Hello,

I need some help clarifying the creation of  models in IBIS.

1.	Inputs with pull-up resistors?
Are these treated in any special way? (ie: different than that of a 
normal input pin?)

2.	Bi-directionals?
I have a pad structure that has the following nodes:

Pad (the output)
Oen (ouput enable)
In (feeds the output when output enable is asserted, and Pad functions 
as an output)
Cin (feeds the core when output enable is deasserted, and Pad 
functions as an input)

What is the proper way of setting this up in s2ibis2?

3.	Rising and Falling Waveforms.
I understand that these are supposed to describe the rising and 
falling edge waveforms of a driver,  yet they are not required.  There 
is also a note in the IBISv2.1 specification that states: "...A 
maximum of 100 waveform tables are allowed per model. Note that for 
backwards compatibility, the existing [Ramp] keyword is still 
required.  The data in the waveform table is taken with the effects of 
the C_comp parameter included..."

From this, I was wondering, what would having 100 waveform tables be 
used for? Further, are the Rising and Falling Waveforms somehow a - 
replacement - for the [Ramp] keyword? Are the Rising and Falling 
waveforms usually generated in the lab at the bench, or can they be 
simulated?  When are they required, if at all?

4.	Analog and Digital VDD's and VSS's.
In the spice netlists of the files that I am dealing with, I often 
multiple VDD's, for example,  VDDac, and VDDdc, which are used to 
power up separately the I/O ring and the core.  Has anyone else out 
there had to deal with multiple VDD's like this? (I'm not talking 
about multiple VDD's such as 3.3 and 5 V, such that can be solved 
using pin mapping)

5.	Stimulus input voltage risetime and falltimes
How are these parameters used?  And for what curves are they used 
for?

Clarification of any of the above questions (1-5) would be greatly 
appreciated,
Thanx!

Best Regards,
Roland

***********************************************************************  
**
*Roland Chang                          | email: roland@sfu.ca 
          *
*Simon Fraser University               |        OR 
                     *
*School of Engineering Science         |        chang@pmc-sierra.bc.ca 
 *
*3rd year Computer Engineering Option  | 
                               *
***********************************************************************  
**
~




 
From owner-ibis  Thu May 29 15:12:40 1997
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Date: Thu, 29 May 97 15:11 PDT
From: bob@icx.com ( Bob Ross)
To: roland_chang@pmc-sierra.bc.ca
Subject: RE: S2ibis2 --  inputs with pull-up resistors, bi-directionals, Rising Waveforms, Falling Waveforms, etc.
Cc: ibis-users@vhdl.org

Roland:

You have raised some good questions.  I have put some responses to your
questions in your text.

Best Regards,
Bob Ross
Interconnectix


> To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>,
>         "'ibis-info@vhdl.org'"
> 	 <ibis-info@vhdl.org>
> Subject: RE: S2ibis2 --  inputs with pull-up resistors, bi-directionals, Rising Waveforms, Falling Waveforms, etc.
> Date: Wed, 28 May 1997 17:23:54 -0700

> Hello,

> I need some help clarifying the creation of  models in IBIS.

> 1.	Inputs with pull-up resistors?
> Are these treated in any special way? (ie: different than that of a 
> normal input pin?)

Pullup resistors would appear in the Clamps.  They are not separated
out.  So there is probable that they will be double counted.
For Pullups, the contribution in the [Gnd Clamp] table should be
should be subtracted.  The [Power Clamp] table should be extended to 
from 0 to Vcc (and possibly linearly extrapolated to 2Vcc) to provide
the separate Pullup resistor component.

> 2.	Bi-directionals?
> I have a pad structure that has the following nodes:

> Pad (the output)
> Oen (ouput enable)
> In (feeds the output when output enable is asserted, and Pad functions 
> as an output)
> Cin (feeds the core when output enable is deasserted, and Pad 
> functions as an input)

> What is the proper way of setting this up in s2ibis2?

I would need to see the circuit (and documentation, if any) to
understand better how to set this up.  My first idea would be
to tie Cin to any load such as 50 ohms to ground.  I would use In
as the Input node and model the Pad as an I/O.

> 3.	Rising and Falling Waveforms.
> I understand that these are supposed to describe the rising and 
> falling edge waveforms of a driver,  yet they are not required.  There 
> is also a note in the IBISv2.1 specification that states: "...A 
> maximum of 100 waveform tables are allowed per model. Note that for 
> backwards compatibility, the existing [Ramp] keyword is still 
> required.  The data in the waveform table is taken with the effects of 
> the C_comp parameter included..."

> >From this, I was wondering, what would having 100 waveform tables be 
> used for? 

I doubt if 100 waveforms is useful, but there was no reason to set a lower
limit which may conflict with an unanticipated need.  In most cases one
or two waveforms is sufficient, and some others might be provided to document
the response for a particular set of loads.  Several simulators will use at
most only two of the waveforms that are provided.

Further, are the Rising and Falling Waveforms somehow a - 
> replacement - for the [Ramp] keyword? 

The Waveforms replace the [Ramp] keyword.  Sometimes waveform data is
bad or several waveforms are inconsistent.  The [Ramp] keyword is 
provided so that the user can get still use the model and get a response.

Are the Rising and Falling 
> waveforms usually generated in the lab at the bench, or can they be 
> simulated?  When are they required, if at all?

Waveforms are never required.  They can be obtained from simulation
or from the lab.  There are some situations where the waveform
response gives a better model because it allows getting data that
is closer to the actual loading conditions of the buffer.  GTL is an example
where the loading conditions are, for example 25 ohms to 1.2 V, even though
the Open_drain buffer is powered by a 3.3 V supply - Implying that the
Ramp load is connected to 3.3 V.

> 4.	Analog and Digital VDD's and VSS's.
> In the spice netlists of the files that I am dealing with, I often 
> multiple VDD's, for example,  VDDac, and VDDdc, which are used to 
> power up separately the I/O ring and the core.  Has anyone else out 
> there had to deal with multiple VDD's like this? (I'm not talking 
> about multiple VDD's such as 3.3 and 5 V, such that can be solved 
> using pin mapping)

The IBIS model does not go into this detail.  I would apply the 
same voltage on all Vdd's to derive the IBIS model.

> 5.	Stimulus input voltage risetime and falltimes
> How are these parameters used?  And for what curves are they used 
> for?

The default is 0.1ns.  For very fast devices, even this may be too
slow.  In general, I have seen negligible variation in the 
output response due to input rise and fall times.  However, 
someone may still want to generate a model response based on an
anticipated or data book specified input response time of 2 or 3 ns,
for example.

> Clarification of any of the above questions (1-5) would be greatly 
> appreciated,
> Thanx!

> Best Regards,
> Roland

> ***********************************************************************  
> **
> *Roland Chang                          | email: roland@sfu.ca 
>           *
> *Simon Fraser University               |        OR 
>                      *
> *School of Engineering Science         |        chang@pmc-sierra.bc.ca 
>  *
> *3rd year Computer Engineering Option  | 
>                                *
> ***********************************************************************  
> **
> ~






 
From owner-ibis  Fri May 30 12:28:07 1997
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subscribe
 
From owner-ibis  Fri May 30 12:29:51 1997
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Date: Fri, 30 May 1997 15:28:32 -0400 (EDT)
From: Luke Chang <chang@nexen.com>
Message-Id: <199705301928.PAA04834@bach.nexen.com>
To: ibis-users@vhdl.org
Cc: hamp@nexen.com

Hi,

When IC vendors create IBIS models for their components, how do they
verify whether they are correct or not, compared to either the original
SPICE models or to physical measurement data?  Do they actually do this
comparison?  Is there a simulation methodology to do this comparison?

I am just a user of IBIS models and will never create them.  So I am
mainly interested in knowing whether I can always (blindly) trust the 
models I get from the vendor Web sites or directly from the vendors.

Thanks.

Luke Chang
Ascom Nexion, Inc.
Acton, MA
 
From owner-ibis  Fri May 30 13:27:06 1997
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To: Luke Chang <chang@nexen.com>
CC: ibis-users@vhdl.org
Subject: Re: Verifying IBIS models
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Luke Chang wrote:

> When IC vendors create IBIS models for their components, how do they
> verify whether they are correct or not, compared to either the original
> SPICE models or to physical measurement data?  Do they actually do this
> comparison?  Is there a simulation methodology to do this comparison?
> 
> I am just a user of IBIS models and will never create them.  So I am
> mainly interested in knowing whether I can always (blindly) trust the
> models I get from the vendor Web sites or directly from the vendors.

I suppose the usual disclaimers (I can't, strictly speaking,
speak for VLSI, much less other manufacturers) are in order.
That said, here's a little about our approach:

1) We SPICE the dickens out of I/O designs.
2) We verify the SPICE characteristics in design
   validation and test against them.
3) We generate IBIS models from the SPICE models.
4) We spot-compare SPICE simulations made from
   hand-translating IBIS back to SPICE.

We're in the process of converting the canonical
model for testing purposes from old-fashioned data
sheets to IBIS.  We *intensely* wish we had a
working IBIS-to-SPICE translator that we could use
for closing the loop, but at present there don't
seem to be any around.

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com
 
From owner-ibis  Fri May 30 13:30:34 1997
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From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
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To: ibis-users@vhdl.org
cc: hamp@nexen.com
Subject: Re: 


Text item: 

Luke,

We do test our IBIS models.  This is done by comparing the I-V curves with SPICE
simulated and/or lab measured curves.  We also check the edge rate by comparing 
the output waveform with SPICE and/or lab waveforms under the same loading 
conditions.

Arpad Muranyi
Intel Corporation
==============================================================================

Hi,

When IC vendors create IBIS models for their components, how do they
verify whether they are correct or not, compared to either the original
SPICE models or to physical measurement data?  Do they actually do this
comparison?  Is there a simulation methodology to do this comparison?

I am just a user of IBIS models and will never create them.  So I am
mainly interested in knowing whether I can always (blindly) trust the
models I get from the vendor Web sites or directly from the vendors.

Thanks.

Luke Chang
Ascom Nexion, Inc.
Acton, MA

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Cc: hamp@nexen.com
To: ibis-users@vhdl.org
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From: Luke Chang <chang@nexen.com>
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From owner-ibis  Fri May 30 13:52:38 1997
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To: ibis-users@vhdl.org
Cc: hamp@nexen.com
Subject: In models we trust
Date: Fri, 30 May 1997 13:51:33 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>


Hello Luke:

    Well, first off, I would never "blindly" trust ANY model -- spice,
IBIS, or otherwise.  Remember that all models are accurate only over
a given environment/operating range, and a model may only be good
for a specific kind of simulation.  For example, a model created
for signal integrety work is probably not approriate for doing EM 
simulations.  Before using any model one must understand it's
purpose and the conditions under which it gives accurate results.

  To answer your specific question -- the model vendor is responsible
for verifing the data in, and results obtained from, an IBIS model.  The IBIS
forum does make sure that the model passes the golden parser before
it's placed on our web site, but we don't have the capabilites to verify
that the model gives "good results".  If you have questions about a specific 
model you should contact the model supplier directly. 

                Regards,
                Stephen Peters
                Intel Corp.



Hi,

When IC vendors create IBIS models for their components, how do they
verify whether they are correct or not, compared to either the original
SPICE models or to physical measurement data?  Do they actually do this
comparison?  Is there a simulation methodology to do this comparison?

I am just a user of IBIS models and will never create them.  So I am
mainly interested in knowing whether I can always (blindly) trust the 
models I get from the vendor Web sites or directly from the vendors.

Thanks.

Luke Chang
Ascom Nexion, Inc.
Acton, MA
 
From owner-ibis  Fri May 30 14:40:28 1997
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From: huq@rockie.nsc.com (Syed Huq)
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To: ibis-users@vhdl.org, chang@nexen.com
Subject: Re:
Cc: hamp@nexen.com

Luke,

At National Semiconductor, we are generating IBIS models either
from bench measurements or from SPICE simulations. It depends
which product lines the models are generated from.

In either case, the final IBIS model is run on two seperate EDA
tools that support the IBIS format. Measurements made on IBIS
simulation are compared against  bench data or SPICE runs for
validation process.

Regards,
Syed
National Semiconductor.

> From owner-ibis@server.vhdl.org Fri May 30 13:36:58 1997
> Date: Fri, 30 May 1997 15:28:32 -0400 (EDT)
> From: Luke Chang <chang@nexen.com>
> To: ibis-users@vhdl.org
> Cc: hamp@nexen.com
> 
> Hi,
> 
> When IC vendors create IBIS models for their components, how do they
> verify whether they are correct or not, compared to either the original
> SPICE models or to physical measurement data?  Do they actually do this
> comparison?  Is there a simulation methodology to do this comparison?
> 
> I am just a user of IBIS models and will never create them.  So I am
> mainly interested in knowing whether I can always (blindly) trust the 
> models I get from the vendor Web sites or directly from the vendors.
> 
> Thanks.
> 
> Luke Chang
> Ascom Nexion, Inc.
> Acton, MA
> 
 
From owner-ibis  Fri May 30 14:44:04 1997
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From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
To: chang@nexen.com
Cc: ibis-users@vhdl.org, ingraham@wrksys.ENET.dec.com
Apparently-To: ibis-users@vhdl.org, chang@nexen.com
Subject: Verifying and trusting models

Luke Chang wrote:

> I am just a user of IBIS models and will never create them.  So I am
> mainly interested in knowing whether I can always (blindly) trust the 
> models I get from the vendor Web sites or directly from the vendors.

Whether it is an IBIS model or a SPICE model, it is wise to always
(blindly) distrust the models you get.  Chances are, there is
something grossly wrong with the model.

I have received models that went through lengthy testing before being
released to me, yet they were rather obviously wrong.

Just today I am looking at a vendor's SPICE model that has been
available for at least six months, yet it's wrong.  Fortunately there
happens to be a second model to compare it against, or I might have
never known.  Kind of a sad situation, wouldn't you say?

Regards,
Andy
 
From owner-ibis  Fri May 30 15:10:51 1997
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Subject: Re: In models we trust

     Hello all,
     
     Good comments Stephan!!!
     
     But it does bring up the question....
     
     Who verifies the performance of the simulation vendors products?
     
     
     My understanding (specifcally in regards to the potential connectors 
     models), that it is possible for each simulation vendors product to 
     handle passive models fdifferently.
     
     Therefore, a model I create for one IBIS model solver will look 
     differently on othe IBIS solvers.
     
     I would not want to be required to make a different passive component 
     (ie connector model) for each IBIS simulation vendor.
     
     Comments??  
     
     Regards,
     _gus panella
     molex, incorporated
     apanella@molex.com


______________________________ Reply Separator _________________________________
Subject: In models we trust
Author:  owner-ibis@server.vhdl.org at internet
Date:    97/05/30 1:51 PM


Hello Luke:
     
    Well, first off, I would never "blindly" trust ANY model -- spice,
IBIS, or otherwise.  Remember that all models are accurate only over 
a given environment/operating range, and a model may only be good 
for a specific kind of simulation.  For example, a model created
for signal integrety work is probably not approriate for doing EM 
simulations.  Before using any model one must understand it's 
purpose and the conditions under which it gives accurate results.
     
  To answer your specific question -- the model vendor is responsible
for verifing the data in, and results obtained from, an IBIS model.  The IBIS 
forum does make sure that the model passes the golden parser before
it's placed on our web site, but we don't have the capabilites to verify 
that the model gives "good results".  If you have questions about a specific 
model you should contact the model supplier directly.
     
                Regards,
                Stephen Peters
                Intel Corp.
     
     
     
Hi,
     
When IC vendors create IBIS models for their components, how do they 
verify whether they are correct or not, compared to either the original 
SPICE models or to physical measurement data?  Do they actually do this 
comparison?  Is there a simulation methodology to do this comparison?
     
I am just a user of IBIS models and will never create them.  So I am 
mainly interested in knowing whether I can always (blindly) trust the 
models I get from the vendor Web sites or directly from the vendors.
     
Thanks.
     
Luke Chang
Ascom Nexion, Inc.
Acton, MA
 
From owner-ibis  Fri May 30 15:36:21 1997
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Message-Id: <199705302235.SAA17026@hot>
To: ibis-users@vhdl.org, owner-ibis@server.vhdl.org, apanella@molex.com
Subject: Re: In models we trust
X-Sun-Charset: US-ASCII

Passsive models should yield identical results in different simulators. 
Only in active models (IBIS buffers) there may be differences due to interpolation/extrapolation schemes.


> From owner-ibis@server.vhdl.org Fri May 30 18:23 EDT 1997
> Received-Date: Fri, 30 May 1997 18:23:00 -0400
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> Subject: Re: In models we trust
> Content-Type: text
> Content-Length: 2529
> X-Lines: 72
> 
>      Hello all,
>      
>      Good comments Stephan!!!
>      
>      But it does bring up the question....
>      
>      Who verifies the performance of the simulation vendors products?
>      
>      
>      My understanding (specifcally in regards to the potential connectors 
>      models), that it is possible for each simulation vendors product to 
>      handle passive models fdifferently.
>      
>      Therefore, a model I create for one IBIS model solver will look 
>      differently on othe IBIS solvers.
>      
>      I would not want to be required to make a different passive component 
>      (ie connector model) for each IBIS simulation vendor.
>      
>      Comments??  
>      
>      Regards,
>      _gus panella
>      molex, incorporated
>      apanella@molex.com
> 
> 
> ______________________________ Reply Separator _________________________________
> Subject: In models we trust
> Author:  owner-ibis@server.vhdl.org at internet
> Date:    97/05/30 1:51 PM
> 
> 
> Hello Luke:
>      
>     Well, first off, I would never "blindly" trust ANY model -- spice,
> IBIS, or otherwise.  Remember that all models are accurate only over 
> a given environment/operating range, and a model may only be good 
> for a specific kind of simulation.  For example, a model created
> for signal integrety work is probably not approriate for doing EM 
> simulations.  Before using any model one must understand it's 
> purpose and the conditions under which it gives accurate results.
>      
>   To answer your specific question -- the model vendor is responsible
> for verifing the data in, and results obtained from, an IBIS model.  The IBIS 
> forum does make sure that the model passes the golden parser before
> it's placed on our web site, but we don't have the capabilites to verify 
> that the model gives "good results".  If you have questions about a specific 
> model you should contact the model supplier directly.
>      
>                 Regards,
>                 Stephen Peters
>                 Intel Corp.
>      
>      
>      
> Hi,
>      
> When IC vendors create IBIS models for their components, how do they 
> verify whether they are correct or not, compared to either the original 
> SPICE models or to physical measurement data?  Do they actually do this 
> comparison?  Is there a simulation methodology to do this comparison?
>      
> I am just a user of IBIS models and will never create them.  So I am 
> mainly interested in knowing whether I can always (blindly) trust the 
> models I get from the vendor Web sites or directly from the vendors.
>      
> Thanks.
>      
> Luke Chang
> Ascom Nexion, Inc.
> Acton, MA
> 
 
From owner-ibis  Fri May 30 17:32:57 1997
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Subject: Re: Model Accuracy
References: <199705301928.PAA04834@bach.nexen.com>
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The actual IBIS party line is (well, might be):

All models are always right, however it is astonishing how often they
point to actual design errors in the silicon....


:)

jon
 
From owner-ibis  Fri May 30 19:54:02 1997
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From: Joe Cahill <jjcahill@us.ibm.com>
To: <ibis-users@vhdl.org>
Subject: Re: model accuracy
Message-Id: <5010400003673616000002L062*@MHS>
Date: Fri, 30 May 1997 22:54:57 -0400
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I believe that the behavior a driver exhibits in an EDA tool's transmission
line simulator is a function of both the IBIS model and the tool's IBIS
simulation algorithms. The tool must translate the simple data points (I/V and
dv/dt tables) in the IBIS model into a complicated and dynamic behavioral
interaction with the behavior of the transmission line algorithms in the tool.
This is rocket science. There are quite a few transmission line algorithms in
use, and quite a few algorithms to get useful behavior from the IBIS model data
points. So far we haven't seen much discussion of the accuracy differences
between simulators, but I expect that to come as IBIS becomes a commodity.

Manufacturers can verify that the I/V curves and dv/dt curves match hardware or
spice, manufacturers can build spice models to mimic the IBIS model in spice
but unless they check the behavior of the IBIS model on a few diverse
transmission line networks in several transmission line simulation tools -
against spice or hardware - they are essentially only placing the data sheet in
electronic form. Unfortunately the form is so useful that you can extrapolate
some very realistic behavior form it. Realistic, but not necessarily
representative of the manufacturer's hardware.

Trust the IBIS model to tell you as much usefull information as the data sheet.
Do your own qualification of the transmission line simulator and the IBIS
models you wish to use against whatever other, more reliable information you
can obtain on a few benchmark networks before you push the edge of your design
using them.

Joe
 
