
From owner-ibis  Tue Dec  1 08:44:14 1998
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From: "Abla, John" <JAbla@level1.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: FW: multi level ibis
Date: Tue, 1 Dec 1998 08:37:38 -0800 
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> ----------
> From: 	Matthew Flora[SMTP:mbflora@hyperlynx.com]
> Sent: 	Tuesday, December 01, 1998 12:45 AM
> To: 	Abla, John
> Subject: 	Re: multi level ibis
> 
> Dear John Abla,
> 
> >I am new to ibis models and have two question.  I) I read an article
> >recently about multi level ibis.  What is the status of this, and where
> can
> >I retrieve data on this topic? 2) Can ibis models represent an Ethernet
> >802.3 TX and RX signals.
> 
> I'm afraid that I personally am not aware of the article you mention.
> However, someone on the IBIS Users' Group E-mail Reflector might.
> Therefore,
> I would recommend resending your message to the reflector at:
> ibis-users@eda.org
> 
> Before you do, I noticed that you are not a subscriber of that reflector
> nor
> are you a subscriber to the IBIS Open Forum's Reflector.  Would you like
> to
> be?  (That way, you could see any discussions that arise from your
> question.)
> There is no cost for the subscription, just send a message with the e-mail
> address you want used to:
> ibis-request@eda.com
> 
> Regards,
> Matthew Flora
> IBIS Open Forum Secretary
> (425) 869-2320 PH
> (425) 881-1008 FAX
> mbflora@hyperlynx.com
> HyperLynx, 17641 NE 67th Court, Redmond, WA 98052 USA
> 
From owner-ibis  Tue Dec  1 08:45:14 1998
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From: "Abla, John" <JAbla@level1.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: FW: multi level ibis
Date: Tue, 1 Dec 1998 08:38:33 -0800 
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> ----------
> From: 	Matthew Flora[SMTP:mbflora@hyperlynx.com]
> Sent: 	Tuesday, December 01, 1998 12:45 AM
> To: 	Abla, John
> Subject: 	Re: multi level ibis
> 
> Dear John Abla,
> 
> >I am new to ibis models and have two question.  I) I read an article
> >recently about multi level ibis.  What is the status of this, and where
> can
> >I retrieve data on this topic? 2) Can ibis models represent an Ethernet
> >802.3 TX and RX signals.
> 
> I'm afraid that I personally am not aware of the article you mention.
> However, someone on the IBIS Users' Group E-mail Reflector might.
> Therefore,
> I would recommend resending your message to the reflector at:
> ibis-users@eda.org
> 
> Before you do, I noticed that you are not a subscriber of that reflector
> nor
> are you a subscriber to the IBIS Open Forum's Reflector.  Would you like
> to
> be?  (That way, you could see any discussions that arise from your
> question.)
> There is no cost for the subscription, just send a message with the e-mail
> address you want used to:
> ibis-request@eda.com
> 
> Regards,
> Matthew Flora
> IBIS Open Forum Secretary
> (425) 869-2320 PH
> (425) 881-1008 FAX
> mbflora@hyperlynx.com
> HyperLynx, 17641 NE 67th Court, Redmond, WA 98052 USA
> 
From owner-ibis  Tue Dec  1 14:37:54 1998
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From: "Shaggy Gonzalez" <shaggy_gonzalez@hotmail.com>
To: shuq@cisco.com
Cc: ibis-users@vhdl.org
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Date: Tue, 01 Dec 1998 14:32:42 PST

Hi,
I have generated the Ibs model for a buffer cell from -Vcc to 2*Vcc.
The issue is that in the Pullup/Pull Down tables, all current entries(
Typ/Max/Min) are ZERO from -Vcc to Vcc.
What could be the cause for it?
Rgds,
shaggy


______________________________________________________
Get Your Private, Free Email at http://www.hotmail.com
From owner-ibis  Wed Dec  2 09:50:33 1998
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From owner-ibis  Wed Dec  2 10:54:20 1998
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From owner-ibis  Mon Dec  7 11:21:33 1998
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Subject: IBIS 3.0 model
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I am in the process of creating an IBIS 3.0 for our K6-2 processor.

When using ibischk3 It Gives me the following errors:
Pull down has decreasing current.
Gnd clamp has decreasing current.

Can anyone tell me what these mean? What charateristic of the data
should I look at? Is there a document that describes the error messages?
Most are self explanatory but this one stumped me.

Also is there a working IBIS 3.x model that I can use as an example?

Thanks in advance
Joe Brcich
Advanced Micro Devices
From owner-ibis  Tue Dec  8 08:10:03 1998
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Date: Tue, 8 Dec 98 09:16 CST
From: beal@lisbon.eng.hou.compaq.com (Weston Beal)
To: ibis-users@vhdl.org
Subject: curve merging

Dear Users,

I have two IBIS files which represent the min and max cases of a
model.  One file has the min characteristics in the typ column and the
other has the max characteristics in the typ column.  I would like to
merge them into one file in standard (typ, min, max) IBIS format.  Does
anyone have a utility to do this which they can share?

Thanks,
Weston Beal
From owner-ibis  Tue Dec  8 16:22:55 1998
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From: gedlund@us.ibm.com
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Subject: IBIS Accuracy minutes - 12/04/98
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IBIS Accuracy Subcommittee Minutes

Friday, December 4, 1998, held by conference call.

Participants

Greg Edlund, IBM (chair)
Bob Haller, Compaq
Bruce Heilbrunn
Peter LaFlamme, Fairchild Semiconductor

The next meeting is Friday, December 11, 1998 from 11:00 to 12:00 am EST


BUSINESS

The subcommittee has decided to conduct its business during a one-hour
conference call on Fridays opposite the IBIS Open Forum call.

Bob Haller reported that the final copy of our DesignCon99 paper, "A Tour
of the IBIS Accuracy Specification," was submitted and accepted.

List of work to be done:
1. Prepare the test board design files for publication – Greg, 12/31/98
2. Write an example "accuracy trailer" using test board data – Bob, Peter,
   12/31/98
3. Finish writing rev 1.0 of the spec – Greg, DesignCon99
4. Write an example "accuracy datasheet" using test board data – Greg, Bob,
   Peter, DesignCon99
5. Write the "IBIS Accuracy Test Board Application Note" – Greg, Fawn,
   DesignCon99
6. Write a Perl script to compute figures of merit – Bob, Fawn, DesignCon99


TECHNICAL

The subcommittee agrees on the need for some kind of accuracy trailer that
would be appended to an IBIS datasheet using comments.  In the very least,
the accuracy trailer would contain the accuracy figures of merit for
various measurements, i.e. the results of applying the correlation metrics.
Peter proposed indicating the existence of an accuracy trailer in an IBIS
datasheet using the [Source] keyword, which has an open-ended format.  Greg
favors adding a new IBIS keyword (in the long run) that could be used by
EDA vendors to set a flag somewhere in the GUI, indicating to the user that
the IBIS datasheet has been lab-verified.

In addition to an accuracy trailer, we may also put together an "IBIS
Accuracy Datasheet" that contains some of the same information as the
trailer but has the potential for more detail, such as simulation vs. lab
overlay plots.  Examples of both the trailer and the datasheet would be
based on data taken from the VCX16244 on the test board.

Bruce proposed adding some text to the disclaimer in the accuracy trailer
to the effect of, "accuracy does not imply syntactical correctness."  If a
user does not read the IBIS Accuracy Spec, he or she may have the notion
that accuracy and syntactical correctness are one in the same.

The subcommittee discussed the idea of amending the spec to include VT
tables.  This has been suggested by several people as a means for
circumventing simulation vs. hardware correlation.  We all agreed that we
would like to add VT tables to the spec in the future, but we don't have
the bandwidth to do it before DesignCon99.  VT tables would not replace
simulation results; they would be an alternative to simulation results.
The IBIS datasheet developer would be free to choose and would be
responsible for documenting this choice to the user.  Adding VT tables
would necessitate a BIRD to allow the three extra test loads called out in
the IBIS Accuracy Spec.  The subcommittee feels strongly that these loads
are necessary for insuring IBIS datasheet accuracy and has data to support
this statement.


Agenda for the next meeting:

Business

1. DesignCon99 paper and booth – 5 min.
2. Opening the conference call to interested parties after DesignCon99 – 5
   min.
3. The need for EIA approval of the IBIS Accuracy Specification – 20 min.

Technical

Review the accuracy trailer line by line.  Please read and offer comments
before hand. – 30 min.


Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com


From owner-ibis  Wed Dec  9 01:10:53 1998
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Date: Fri, 11 Dec 1998 14:50:08 +0800
To: ibis-users@vhdl.org
From: Frank Xiao <viewprc@public3.bta.net.cn>
Subject: Request IBIS Model For Chips!
Mime-Version: 1.0
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Hi, 
I'm now doing a high speed PCB design and I'm using SI tools for the
crosstalk analysis, would you please help me to get the IBIS models for the
bellow chips? Thanks for your care.

MPC750
MPC603RRX200
MPC106ARX66   belong to motorola company

SN74ALVCH16501(83MHZ)
SN74ALVCH162245(66MHZ)   belong to TI company

W83C553F   belong to winbond

Best Rgds 
Frank

From owner-ibis  Wed Dec  9 16:02:56 1998
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Date: Wed, 9 Dec 1998 15:57:41 -0800 (PST)
From: Syed Huq <shuq@cisco.com>
Message-Id: <199812092357.PAA18857@jasper.cisco.com>
To: ibis-users@vhdl.org, viewprc@public3.bta.net.cn
Subject: Re: Request IBIS Model For Chips!
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Frank,

You can try http://www.eia.org/eig/ibis/ibis.htm and Click on 'Models'.
Then select the vendor name and that will take you to the their IBIS models
website.

If you cannot find the model, then you may have to request the vendor 
directly. You could do that thru the sales rep or other channels..

Syed.
Cisco Systems, Inc

> From viewprc@public3.bta.net.cn Wed Dec  9 01:07:21 1998
> X-SMAP-Received-From: outside
> X-Sender: viewprc@public3.bta.net.cn
> Date: Fri, 11 Dec 1998 14:50:08 +0800
> To: ibis-users@vhdl.org
> From: Frank Xiao <viewprc@public3.bta.net.cn>
> Subject: Request IBIS Model For Chips!
> Mime-Version: 1.0
> 
> Hi, 
> I'm now doing a high speed PCB design and I'm using SI tools for the
> crosstalk analysis, would you please help me to get the IBIS models for the
> bellow chips? Thanks for your care.
> 
> MPC750
> MPC603RRX200
> MPC106ARX66   belong to motorola company
> 
> SN74ALVCH16501(83MHZ)
> SN74ALVCH162245(66MHZ)   belong to TI company
> 
> W83C553F   belong to winbond
> 
> Best Rgds 
> Frank
> 
From owner-ibis  Wed Dec  9 21:38:45 1998
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Date: Wed, 9 Dec 1998 21:31:50 -0800 (PST)
From: Syed Huq <shuq@cisco.com>
Message-Id: <199812100531.VAA05335@jasper.cisco.com>
To: ibis-users@vhdl.org, beal@lisbon.eng.hou.compaq.com
Subject: Re: curve merging
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Hi,

Yes it can be done with Xemacs. It's called 'Rectangle Operations' and I
think you could try the following key bindings:

^x r k, ^x r y, ^x r d	

emacs or Xemacs is a GNU editor(plus more)found on all Linux systems as 
well as UNIX.

Regards,
Syed
Cisco Systems, Inc.

> From beal@lisbon.eng.hou.compaq.com Tue Dec  8 08:06:46 1998
> X-SMAP-Received-From: outside
> Date: Tue, 8 Dec 98 09:16 CST
> From: beal@lisbon.eng.hou.compaq.com (Weston Beal)
> To: ibis-users@vhdl.org
> Subject: curve merging
> 
> Dear Users,
> 
> I have two IBIS files which represent the min and max cases of a
> model.  One file has the min characteristics in the typ column and the
> other has the max characteristics in the typ column.  I would like to
> merge them into one file in standard (typ, min, max) IBIS format.  Does
> anyone have a utility to do this which they can share?
> 
> Thanks,
> Weston Beal
From owner-ibis  Thu Dec 10 11:25:48 1998
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From: "D. C. Sessions" <dc.sessions@vlsi.com>
Reply-To: ibis-users@eda.org
Organization: VLSI Technology Inc.
X-Mailer: Mozilla 4.5 [en] (X11; U; SunOS 5.5.1 sun4m)
X-Accept-Language: en
MIME-Version: 1.0
To: ibis-users@eda.org
Subject: Re: IBIS 3.0 model
References: <366C2958.277E@amd.com>
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Joseph Brcich wrote:
> 
> I am in the process of creating an IBIS 3.0 for our K6-2 processor.
> 
> When using ibischk3 It Gives me the following errors:
> Pull down has decreasing current.
> Gnd clamp has decreasing current.

First off, these are warnings, not errors.

There are a lot of reasons why an I/V curve might be nonmonotonic,
ranging from numerical artifacts to inconsistent test conditions
to real nonmonotonicity due to feedback.  Many processors have weak
bus keepers on their I/O lines to prevent float, and that would do
the trick.

> Can anyone tell me what these mean? What charateristic of the data
> should I look at? Is there a document that describes the error messages?
> Most are self explanatory but this one stumped me.

What I'd do is copy & paste the I/V curves into a spreadsheet and
generate the sum and its differences.  That should show the effect
up pretty neatly and let you apply the grey colloidial debugger.

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Thu Dec 10 12:09:56 1998
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Date: Thu, 10 Dec 1998 12:05:59 -0100
To: "KOK TONG THAM" <kt_tham@hotmail.com>
From: Matthew Flora <mbflora@hyperlynx.com>
Subject: Re: Regarding IBIS
Cc: ibis-users@eda.org
In-Reply-To: <19981210055634.28953.qmail@hotmail.com>
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Dear Kok Tong Tham,

>I am a Shinshu University student in Japan.
>I am interesting in IBIS modeling. I had read over the IBIS version 3.1 
>spec.but some keyword still annoying me. Could you explain to me in 
>detail regarding some keyword? 
>
>1)What meaning of model_name and function_table_group 
>  in the third and fourth column of keyword [Series Pin Mapping]? 
>  and how to define it?
>
>2)How to define and what meaning of keyword [Series Switch Groups}?
>
>3)What relation between keyword [Model] and [Model Selector]?
>
>4)How to define the Model_name in keyword [Driver Schedule]?
>  what relation between Model_name and keyword [Model]?
>  what actually keyword [Driver Schedule] means?
>
>5)How to define keyword [Pin Mapping]?

I am forwarding your questions to the IBIS Users Group e-mail reflector and
have added you to that reflector so that you will receive any discussions
raised by your questions.  One suggestion that I have is to look at
ftp://ftp.eda.org/pub/ibis/birds/index.html.  There you will see a list of the
proposed changes to the IBIS standard (past and present).  They may be of
interest to you since they contain explanations not found in the standard
itself.  For instance, BIRD 52 might be of help to you.

Regards,

Matthew Flora
IBIS Open Forum Secretary
(425) 869-2320 PH
(425) 881-1008 FAX
mbflora@hyperlynx.com
HyperLynx, 17641 NE 67th Court, Redmond, WA 98052 USA

From owner-ibis  Fri Dec 11 00:11:44 1998
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Date: Fri, 11 Dec 1998 13:34:36 +0530
From: "R.Sanjeev" <presi@india.ti.com>
Organization: I.I.T.Madras
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To: Syed Huq <shuq@cisco.com>
CC: ibis-users@vhdl.org, beal@lisbon.eng.hou.compaq.com
Subject: Re: curve merging
References: <199812100531.VAA05335@jasper.cisco.com>
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--------------7E626D60A80A8E66353AB3BE
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Hi Beal,

I picked out the parts of the s2ibis code that does this merging. It'll work
for data files generated for the following types of spice:
                                "HSpice",
                                "PSpice",
                                "SPICE2",
                                "Spice3",
                                "Spectre"
I've added a spice type called "dummy" if you just have files with data and
nothing else.
(The first line of the input files should be empty)

if you are using spice other than these you need to add the following to the
code to take care of it:
1. spiceNameString :           your spice name(does not run it so just
something
                                             different from those already
there)
2. dataEndMarker :              When to stop reading the data in the file.
3. VIDataBeginMarker:       Where to start reading from the file for actual
data points.
4. VIDataConversionString: What format will the data be in(check the code
for examples)



The format to use it right now is:
combine <spiceType> <typFl> <minFl> <maxFl> <opFl>

Copy the two files in a dir and say make(in any Unix platform) on windows
just compile the combine.c

Please let me know if there are any problems.

regards,
presi
-----
Syed Huq wrote:

> Hi,
>
> Yes it can be done with Xemacs. It's called 'Rectangle Operations' and I
> think you could try the following key bindings:
>
> ^x r k, ^x r y, ^x r d
>
> emacs or Xemacs is a GNU editor(plus more)found on all Linux systems as
> well as UNIX.
>
> Regards,
> Syed
> Cisco Systems, Inc.
>
> > From beal@lisbon.eng.hou.compaq.com Tue Dec  8 08:06:46 1998
> > X-SMAP-Received-From: outside
> > Date: Tue, 8 Dec 98 09:16 CST
> > From: beal@lisbon.eng.hou.compaq.com (Weston Beal)
> > To: ibis-users@vhdl.org
> > Subject: curve merging
> >
> > Dear Users,
> >
> > I have two IBIS files which represent the min and max cases of a
> > model.  One file has the min characteristics in the typ column and the
> > other has the max characteristics in the typ column.  I would like to
> > merge them into one file in standard (typ, min, max) IBIS format.  Does
> > anyone have a utility to do this which they can share?
> >
> > Thanks,
> > Weston Beal



--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Cahn's Axiom: "When all else fails, read the instructions."
R.Sanjeev                   Home...
~~~~~~~~~                   hppt://members.tripod.com/~r_sanjeev
e-mail:    presi@india.ti.com
snail-mail:
           20, Karnan Street, Murugesha Naicken Nagar,
           Kodambakkam, Chennai-24.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



--------------7E626D60A80A8E66353AB3BE
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#
# makefile for mergeIBIS
#
##############################################################################
# Compilation and linking using GNU tools
#
CC = gcc
CFLAGS = -g
##############################################################################

PROGRAM = mergeIBIS

SRCS = mergeIBIS.c

ALL = $(SRCS) 

OBJS  =$(SRCS:.c=.o)

$(PROGRAM): $(OBJS)
	$(CC) -o $(PROGRAM) $(CFLAGS) $(OBJS)
	
clean :
	rm $(OBJS) $(PROGRAM)
depend	:
	makedepend -- $(CFLAGS)   $(SRCS)


# DO NOT DELETE THIS LINE -- make depend depends on it.

--------------7E626D60A80A8E66353AB3BE
Content-Type: text/plain; charset=us-ascii; name="mergeIBIS.c"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="mergeIBIS.c"

/********************************************************************
*                   Parts from s2ibis2 that came from:
*					North Carolina State University
*					Electronics Research Laboratory
*
*                   Modified by: Sanjeev Ranganathan
*                   Indian Institute of Technology Madras
*                   VLSI Design Laboratory.
*                   e-mail: presi@oyster.ee.iitm.ernet.in
********************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>

/*
 * ARGUMENT LABELS
 *
 * These are used to label function arguments.
 *
 * IN indicates that the argument data is read only by the function, and 
 * not written.
 *
 * INOUT indicates that the argument data is read and written by the
 * function.
 *
 * OUT indicates that the argument data is written by the function,
 * without reference to its previous value.
 *
 * INOUT and OUT apply only to pointer arguments, since there is no
 * direct pass-by-reference mechanism in C.
 */
#define	IN
#define OUT
#define INOUT
#define SHARED

/* MAX TABLE size :used as initial value*/
#define MAX_TAB_SIZE  600

/* Basic data Structures required a minTypMax table and its size */
typedef struct {
	double			typ,			/* typical value */
					min,			/* minimum value */
					max;			/* maximum value */
} ibisTypMinMax_t, *ibisTypMinMax_Pt;

typedef struct VIentryDef {
	double			v;
	ibisTypMinMax_t	i;
} ibisVItableEntry_t, *ibisVItableEntry_Pt;

typedef struct {
	int				size;
    ibisVItableEntry_Pt 
					VIs;
} ibisVItable_t, *ibisVItable_Pt;

/* The Kind of Spices that it can support */

char	*spiceNameString[] = 
				{
				"HSpice",
				"PSpice",
				"SPICE2",
				"Spice3",
				"Spectre",
				"dummy"
				};
/* The number of these */
#define NUM_SUPP_SPICE 6
/* It uses the following as the data begin marker i.e. these are present in 
 * the line before the data is actually displayed */
char	*VIDataBeginMarker[] = 
				{
				"transfer",
				"DC TRANSFER",
				"X",
				"Index",
				"Values",
				"\n"
				};

/* Stops reading with this */
char	*dataEndMarker[] =
				{
				"job",
				"",
				"Y",
				"CPU",
				"",
				"eof"
				};
                
/* The data is assumed to be %le and is read as that */                
char	*VIDataConversionString[] =
				{
				"%le %le \n",
				"%le %le \n",
				"%le %le \n",
				"%*d %le %le \n",
				"%*d %le %*le %le \n",
				"%le %le \n"
				};
        
/* Maps the given input name to an integer corresponding to that name */
int 
find_spice_type(char *spName)
{
  int i;
  for (i=0;i<NUM_SUPP_SPICE;i++)
    if (!strcmp(spName,spiceNameString[i]))
        return(i);
   
  return(0);
}

/* reads the typ min max files and generates the data-structure */
int
getSpiceVIData(	IN	ibisVItable_Pt 	VIData_P,
				IN	int				tableSize,
				IN	int				spiceType,
				IN	char			*spiceOutFile,
				IN	char			*command )
{
FILE	*outFile_P = NULL;
char	lineBuffer[256];
double	tempData[300][2];
int		rowIndex = 1,i = 0;


if ( ( outFile_P = fopen( spiceOutFile, "r" ) ) == NULL )
	{
	fprintf( stderr, "Unable to open file %s for reading.\n",
			 spiceOutFile );
	return( 1 );
	}

/*------------------------------------------------------------------------
*
*	Read lines until we hit the data begin marker or EOF.  If it's EOF, 
*	return an error.
*
*-----------------------------------------------------------------------*/
while ( ( fgets( lineBuffer, 256, outFile_P ) != NULL ) &&
		( strstr( lineBuffer, VIDataBeginMarker[spiceType] ) == NULL ) );

if ( strstr( lineBuffer, VIDataBeginMarker[spiceType] ) == NULL )
	{
	fprintf( stderr, "Data begin marker %s not found ",
			 VIDataBeginMarker[spiceType] );
	fprintf( stderr, "in output file %s.\n", spiceOutFile );
	return( 1 );
	}

/*------------------------------------------------------------------------
*
*	We're now at the line before the start of the VI data.  
*	Read lines until we get the correct number of columns.
*
*-----------------------------------------------------------------------*/
while ( ( fgets( lineBuffer, 256, outFile_P ) != NULL ) &&
		( sscanf( lineBuffer, VIDataConversionString[spiceType], 
				  &tempData[0][0], &tempData[0][1] ) != 2 ) );

if ( feof( outFile_P ) )
	{
	fprintf( stderr, "s2ibis2: No data in file %s\n", spiceOutFile );
	return( 1 );
	}

tempData[0][1] = -tempData[0][1];

/*------------------------------------------------------------------------
*
*	Now we read until we see the end-of-data marker or the end-of-file 
*	marker.  We include the data from any read that returns the correct 
*	number of columns read.  If we don't have an end-of-data marker for
*	this particular flavor of Spice, we just read to the end-of-file maker.
*
*-----------------------------------------------------------------------*/
if ( dataEndMarker[spiceType] == NULL )
	{
	while ( ( fgets( lineBuffer, 256, outFile_P ) != NULL ) )
		if ( sscanf(lineBuffer, VIDataConversionString[spiceType],
		   &tempData[rowIndex][0], &tempData[rowIndex][1]) == 2 )
			{
			tempData[rowIndex][1] = -tempData[rowIndex][1];
			rowIndex++;
			}
	}
else
	{
	while ( ( fgets( lineBuffer, 256, outFile_P ) != NULL ) &&
			( strstr( lineBuffer, dataEndMarker[spiceType] ) == NULL ) ) 
		if ( sscanf(lineBuffer, VIDataConversionString[spiceType],
		   &tempData[rowIndex][0], &tempData[rowIndex][1]) == 2 )
			{
			tempData[rowIndex][1] = -tempData[rowIndex][1];
			rowIndex++;
			}
	}

fclose( outFile_P );

rowIndex--;
if ( rowIndex > tableSize )
	{
	fprintf( stderr, "s2ibis2: Spice job returned too many data points.\n" );
	fprintf( stderr, "         May have to truncate table...\n" );
	}

/*------------------------------------------------------------------------
*
*	Now we transfer the data to the correct place, depending on the value
*	of command.
*
*-----------------------------------------------------------------------*/
if ( !( strcmp( command, "typ" ) ) )
{
	VIData_P->size = rowIndex + 1;
    /** Some way to create the size equivalent for the rowindex **/
	if( (VIData_P->VIs = (ibisVItableEntry_Pt) \
         malloc(sizeof(ibisVItableEntry_t) * VIData_P->size) ) == NULL)
    {
         printf("Out of memory");
         return(1);
    }        
    for ( i = 0; i <= rowIndex; i++ )
	{
		VIData_P->VIs[i].v = tempData[i][0];
		VIData_P->VIs[i].i.typ = tempData[i][1];
	}
}
else if ( !( strcmp( command, "min" ) ) )
	for ( i = 0; i <= rowIndex; i++ )
		VIData_P->VIs[i].i.min = tempData[i][1];
else
	for ( i = 0; i <= rowIndex; i++ )
		VIData_P->VIs[i].i.max = tempData[i][1];

return( 0 );
}

/* Does the final write into the Outfile of the Data Structure generated
 * earlier by getSpiceVIData function */
int writeSpiceVIData(IN char* Outfile, IN ibisVItable_Pt VIData_P)
{
    FILE * outFile_P;
    int j = 0;
    
    if ( ( outFile_P = fopen( Outfile, "w" ) ) == NULL )
	{
	    fprintf( stderr, "Unable to open file %s for writing.\n",
			 outFile_P );
	    perror( "s2ibis2");
	    return( 1 );
	}
    printf("%s Generated by program\n",Outfile);
    fprintf(outFile_P,"| Voltage\t I(typ)\t I(min)\t I(max)\n");
    for(j = 0 ;j < VIData_P->size;j++)
        fprintf(outFile_P,"%le %le %le %le\n",VIData_P->VIs[j].v, \
        VIData_P->VIs[j].i.typ, \
        VIData_P->VIs[j].i.min,VIData_P->VIs[j].i.max);
    fclose(outFile_P);
}
int 
main(int argc,char* argv[])
{
    /* Take the input and call get Spice VI Data in proper order 
    to get all the data required and then print quietly */
    ibisVItable_Pt 	VIData_P ;
    int spiceType;
    if (argc<2) 
    {
        printf("Usage %s <spiceType> <typFl> <minFl> <maxFl> <opFl>\n",argv[0]);
        return(1);
    }
    spiceType = find_spice_type(argv[1]);    
    getSpiceVIData(VIData_P,MAX_TAB_SIZE,spiceType,argv[2],"typ");
    getSpiceVIData(VIData_P,VIData_P->size,spiceType,argv[3],"min");
    getSpiceVIData(VIData_P,VIData_P->size,spiceType,argv[4],"max");
    writeSpiceVIData(argv[5],VIData_P);
}


--------------7E626D60A80A8E66353AB3BE--

From owner-ibis  Tue Dec 15 14:55:09 1998
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Date: Tue, 15 Dec 1998 14:50:50 -0100
To: Courtenay Johnson <courtena@newbridge.com>
From: Matthew Flora <mbflora@hyperlynx.com>
Subject: Re: Is there a template for the Intusoft IBIS to spice
  translator for PSPICE?
Cc: ibis-users@eda.org
In-Reply-To: <3676DDE4.8CCE5A64@newbridge.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

Dear Courtenay Johnson,

>Is there a template that works with the Intusoft IBIS to spice
>translator that will output Microsim PSPICE format, rather than for
>Intusoft's own flavor of spice. I am new to using spice, and am not yet
>capable of writing my own template.
>-- 
>Courtenay Johnson
>Senior Hardware Designer
>Broadband Copper Access - xDSL
>Newbridge Network Corp, 600 March Rd, Kanata, Ont, Canada K2K 2E6
>Phone: (613)599-3600 ext 6906
>Fax: (613) 599-3634
>E-mail: courtena@newbridge.com

I am forwarding your question to the IBIS Users Group e-mail reflector and
have added you to that reflector so that you will receive any discussions
raised by your question.

Regards,
Matthew Flora
IBIS Open Forum Secretary
(425) 869-2320 PH
(425) 881-1008 FAX
mbflora@hyperlynx.com
HyperLynx, 17641 NE 67th Court, Redmond, WA 98052 USA

From owner-ibis  Wed Dec 16 01:24:55 1998
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From owner-ibis  Wed Dec 16 08:37:19 1998
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "\"Courtenay Johnson\" " <courtena@newbridge.com>
Cc: "\"ibis-users@eda.org\" " <ibis-users@eda.org>
Subject: RE: Is there a template for the Intusoft IBIS to spice tr
Date: Wed, 16 Dec 1998 08:31:00 -0800
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PSPICE used to have a behavioral buffer which was based on the HSPICE
behavioral
buffer I developed years ago.  I am not a user of PSPICE, so I am not sure
what 
is included in the distribution libraries now, and I am not sure what
changed 
since Microsim was bought up by Orcad.

If you find one of these behavioral buffer, you may be able to use it as a 
template for the Intusoft translator, but I am not sure how that works,
since I 
haven't used that yet either.  Sorry for the vague answers, but that's all I
can
help you, which may be good enough to get you started looking in the right 
direction.

Arpad Muranyi
Intel Corporation
============================================================================
===


Dear Courtenay Johnson,

>Is there a template that works with the Intusoft IBIS to spice
>translator that will output Microsim PSPICE format, rather than for
>Intusoft's own flavor of spice. I am new to using spice, and am not yet
>capable of writing my own template.
>--
>Courtenay Johnson
>Senior Hardware Designer
>Broadband Copper Access - xDSL
>Newbridge Network Corp, 600 March Rd, Kanata, Ont, Canada K2K 2E6
>Phone: (613)599-3600 ext 6906
>Fax: (613) 599-3634
>E-mail: courtena@newbridge.com

I am forwarding your question to the IBIS Users Group e-mail reflector and
have added you to that reflector so that you will receive any discussions
raised by your question.

Regards,
Matthew Flora
IBIS Open Forum Secretary
(425) 869-2320 PH
(425) 881-1008 FAX
mbflora@hyperlynx.com
HyperLynx, 17641 NE 67th Court, Redmond, WA 98052 USA
From owner-ibis  Wed Dec 16 14:50:20 1998
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From: "Montoya, Silvia" <Silvia.Montoya@actel.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Cc: "Montoya, Silvia" <Silvia.Montoya@actel.com>
Subject: Power Supplies
Date: Wed, 16 Dec 1998 14:44:57 -0800
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  Hi,

    I am in the process of verifying IBIS models for our  PCI  compliant I/O
buffers  with  I/V  bench measurements.
  
    I will need two power supplies, a 3v and a 5v . The IBIS cockbook
recommends using power supplies which will 

    source and sink current while maintaining the required output voltage.
Can anyone recommend make/model of

    supplies which work well for this application ?

    Thanks,

      S. Montoya
From owner-ibis  Wed Dec 16 17:47:43 1998
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "\"'ibis-users@eda.org'\" " <ibis-users@eda.org>
Cc: "\"Montoya; Silvia\" " <Silvia.Montoya@actel.com>
Subject: RE: Power Supplies
Date: Wed, 16 Dec 1998 17:18:00 -0800
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HP has a few models, ask them to send you a catalog.

Arpad
============================================================================
=

  Hi,

    I am in the process of verifying IBIS models for our  PCI  compliant I/O
buffers  with  I/V  bench measurements.

    I will need two power supplies, a 3v and a 5v . The IBIS cockbook
recommends using power supplies which will

    source and sink current while maintaining the required output voltage.
Can anyone recommend make/model of

    supplies which work well for this application ?

    Thanks,

      S. Montoya
From owner-ibis  Wed Dec 16 23:45:33 1998
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HI, sir:
   I am a learner of XTK. I have some questions about XTK 
 and I hope you can give me an answer quickly.
1. What is the maximum frequency that XTK can analyze properly?
2. Could XTK be used to analyze the skin effect ? 
   if so,which parameter describe the degree of the skin effect?
3. I have performed a system level simulation with ISF2XTK. 
   I use a *.mxf file to match a model to a connector. When analyzed the net
  including the connector, XNS reported some errors such as :
  <a>Could not find model name matching JB8-1O2_TO_SON_3: U10_27
     may be encrypted model.
  And,  XNS do not use the connector model I defined,but 
  use the default connector model, what can I do with it?
4. When I translate IBIS MODEL into XTK with IBIS2XTK , the program 
   IBIS2XTK did not report any errors.But when analyze,XNS reported 
   some errors such as :
   <b>pin name no found for part son_3: c83 2 . This prevents package 
     capacitance connection.
   And package parameter has not been loaded  by the program XNS .
5. How to get the *.xf3 file which used as input file for program XFX3D?


--------------9DEDC6A3D6F200B06F092D1D--

From owner-ibis  Thu Dec 17 08:27:14 1998
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Date: Thu, 17 Dec 1998 08:22:04 -0100
To: Franck AZEMA <azema@sxb.bsf.alcatel.fr>, ibis-users@eda.org
From: Matthew Flora <mbflora@hyperlynx.com>
Subject: Re: IBIS pin mapping questions
Cc: PATRICK ANDRES <PATRICK.ANDRES@sxb.bsf.alcatel.fr>,
        PATRICK SCHEIBEL <PATRICK.SCHEIBEL@sxb.bsf.alcatel.fr>
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Dear Frank Azema,

> I try to simulate my electronics designs after layout design. I use QUAD
> ANALYZE simulator which include a converter from IBIS model to Quad model to a
> specific part : typ, min or max.
> The logic and physical symbol of the design tools i use are made with the
> specification pin mapping of the manufacturer of the component. In example on
> a microprocessor of Motorola ( the MPC823 microprocessor) the pin mapping is
> an alpha-numeric grid, so i associate the signal name of the data sheet with
> the pin alpha-numeric number in my symbols.
> I found the IBIS model of this microprocessor on the web of Motorola and i try
> to use it. Many errors appeared after converting manipulation to use this
> model. In fact the pin number of the symbol and the pin number of the model
> are different. So the simulator didn't look for the good [model] and the
> simulation gave bad result. So, i correct the pin number mapping and it was
> good for new simulation. 
> 
> In an other design i use the AMD microprocessor AM186er. I ask AMD for IBIS or
> simulation model and their give me the IBIS model AND the Quad model. So, i
> use it and errors appear because the pin number mapping doesn't correct with
> the manufacturer data sheet. Here the pin number mapping in only numeric in
> opposition of the motorola component. 
> 
> MY QUESTION is about the pin number mapping method of a IBIS model. How can i
> found the right method which explain how to make this ? WHY isn't it in phase
> with the data sheet ? i didn't found any application note on the subtract of
> it on your web site.
> My pivot table to correct the pin number mapping is the signal name mapping
> but it isn't every time exactly the same of the data sheet of the
> manufacturer. My contact on different manufacturer can not explain me how the
> ibis model make because it is very big company and the can't find the ibis
> creator. 
> 
> So, are there a method official from IBIS group for this syntax of pin number
> mapping and signal name mapping ? 
> 
> I thank you answer and i give you a merry christmas and a happy new year.
> Frank AZEMA                               ALCATEL BUSINESS SYSTEMS
> Technical direction                       1, route du Dr Albert Schweitzer
> Tel : +33(0)3 88 67 77 00                 F-67408 ILLKIRCH-GRAFFENSTADEN Cedex
> Fax : +33(0)3 88 67 70 83
> <mailto:Franck.Azema@sxb.bsf.alcatel.fr>

I am forwarding your question to the IBIS Users Group e-mail reflector and
have added you to that reflector so that you will receive any discussions
raised by your question.

If I understand your question correctly, it sounds like the creators of the
IBIS files did not give complete pinouts for the parts.  In my opinion, a
COMPLETE IBIS file lists every pin on the part in the [Pin] section of the
[Component].  If the part is available in multiple packages then the IBIS file
could contain multiple [Component] sections or multiple files may be created.
Furthermore, I believe it silly for the creators of the IBIS files to use pin
and signal names that are inconsistent with the datasheet.  (The IBIS
specification actually requires a full pinout for each [Component] and
specifically says that the pin/signal names should be as given on a
datasheet.)

Regards,

Matthew Flora
IBIS Open Forum Secretary
(425) 869-2320 PH
(425) 881-1008 FAX
mbflora@hyperlynx.com
HyperLynx, 17641 NE 67th Court, Redmond, WA 98052 USA

From owner-ibis  Thu Dec 17 09:49:00 1998
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From: Syed Huq <shuq@cisco.com>
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To: azema@sxb.bsf.alcatel.fr, ibis-users@eda.org, mbflora@hyperlynx.com
Subject: Re: IBIS pin mapping questions
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Frank,

I have seen the same issues that you have outlined. Sometimes you get a model
where the [Pin] numbering do not match up with the Datasheet defined numbering.
The Datasheet may have used aplha numerics(eg, BGA pkg) while the [Pin]
columns used sequential numbers.

Unfortunately, I had to fix this myself. The problem goes back to the source
of the IBIS model. They need to be consistent with Datasheet naming convention.
In some cases, the model developer and the Si Manufacturer are two seperate
groups and that could lead to this problem.

It is best you bring this up with your model provider.

Regards,
Syed.
Cisco Systems, Inc

>Frank writes:
> 
> MY QUESTION is about the pin number mapping method of a IBIS model. How can i
> found the right method which explain how to make this ? WHY isn't it in phase
> with the data sheet ? 
From owner-ibis  Thu Dec 17 10:00:16 1998
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I have read with interest the latest version of the
IBIS cookbook.  It details recommended characterization
conditions for simulating TTL, ECL, LVCMOS, etc.  It 
does not contain recommended conditions for measuring
newer I/Os, i.e. SSTL, HSTL, GTL, LVDS.

What are the recommended simulation conditions for these
I/Os?

Rob Eccles
Xilinx
rob.eccles@xilinx.com
From owner-ibis  Thu Dec 17 12:29:42 1998
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To: Rob Eccles <rob.eccles@xilinx.com>
cc: ibis@eda.org, ibis-users@eda.org
Subject: Re: Characterization Conditions 
In-reply-to: Your message of "Thu, 17 Dec 1998 09:54:34 PST."
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From: Stephen Peters <sjpeters@ichips.intel.com>


Hello Rob:

   By "recommended characterization conditions" I assume you mean
the output loads/voltages use to extract V/T waveforms.  Because the
GTL/GTL+ outputs are open-drain, I would extract the V/T waveforms
using the rules for open drain buffers -- a load resistor to 
Vterm, with the value of Rterm and Vterm determined by the 
specification or part manufacturer.  As for the other standards,
if the driver uses a standard push/pull structure use the rules for 
standard CMOS or TTL (depending on the technology of the buffer).  
Remember: by taking the V/T waveforms with a load tied
to Vcc then to ground, one can isolate the turn-on, turn-off and 
overlap times of the pullup and pulldown structures, thereby allowing
the simulator to construct an accurate model of the driver.  This
model should be accurate, even if the driver application calls for
the output to be terminated to Vcc/2, or series terminated, or whatever.

          Regards,
          Stephen Peters
          Intel Corp. 



> I have read with interest the latest version of the
> IBIS cookbook.  It details recommended characterization
> conditions for simulating TTL, ECL, LVCMOS, etc.  It 
> does not contain recommended conditions for measuring
> newer I/Os, i.e. SSTL, HSTL, GTL, LVDS.
> 
> What are the recommended simulation conditions for these
> I/Os?
> 
> Rob Eccles
> Xilinx
> rob.eccles@xilinx.com


From owner-ibis  Thu Dec 17 13:17:34 1998
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "\"KOK TONG THAM\" " <kt_tham@hotmail.com>
Cc: "\"ibis-users@eda.org\" " <ibis-users@eda.org>
Subject: RE: Regarding IBIS
Date: Thu, 17 Dec 1998 10:23:00 -0800
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Dear Kok Tong Tham,

I will try to answer one of your questions.

>I am a Shinshu University student in Japan.
>I am interesting in IBIS modeling. I had read over the IBIS version 3.1
>spec.but some keyword still annoying me. Could you explain to me in
>detail regarding some keyword?
>
>1)What meaning of model_name and function_table_group
>  in the third and fourth column of keyword [Series Pin Mapping]?
>  and how to define it?
>
>2)How to define and what meaning of keyword [Series Switch Groups}?
>
>3)What relation between keyword [Model] and [Model Selector]?

You need to use the [Model Selector] in cases when a pin of a device is
driven 
by a buffer which can have different characteristics based on some internal 
selection mechanizm.  A good example is a programmable buffer who's strength
can
be changed.  For a case like that you will have to make a different [Model]
for 
each strength of the buffer.  But the pin list of the IBIS model can only
call 
one [Model] (or model selector), that is why the [Model Seletor] is needed.

To sum it up, for buffers which can behave several different ways, you have
to 
make a different [Model] for each behavior.  You list these [Model]s in the 
[Model Selector] keyword.  The name of the [Model selector] is then used in
the 
pin list.

>
>4)How to define the Model_name in keyword [Driver Schedule]?
>  what relation between Model_name and keyword [Model]?
>  what actually keyword [Driver Schedule] means?
>
>5)How to define keyword [Pin Mapping]?
From owner-ibis  Thu Dec 17 18:05:27 1998
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To: Stephen Peters <sjpeters@ichips.intel.com>
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Hi Steve,

Thanks for your prompt reply!  

After reading your response, and giving it some more thought,
it looks like SSTL and HSTL should use the same methodology
given in Table 1 for CMOS (from the 2.0X version of the Cookbook).

In practise, not all boards will use 50 Ohm loads.  How sensitive
are the IBIS models to termination resistance?  I would expect
this to be significant.

Regards,
Rob Eccles
Xilinx

Stephen Peters wrote:
> 
> Hello Rob:
> 
>    By "recommended characterization conditions" I assume you mean
> the output loads/voltages use to extract V/T waveforms.  Because the
> GTL/GTL+ outputs are open-drain, I would extract the V/T waveforms
> using the rules for open drain buffers -- a load resistor to
> Vterm, with the value of Rterm and Vterm determined by the
> specification or part manufacturer.  As for the other standards,
> if the driver uses a standard push/pull structure use the rules for
> standard CMOS or TTL (depending on the technology of the buffer).
> Remember: by taking the V/T waveforms with a load tied
> to Vcc then to ground, one can isolate the turn-on, turn-off and
> overlap times of the pullup and pulldown structures, thereby allowing
> the simulator to construct an accurate model of the driver.  This
> model should be accurate, even if the driver application calls for
> the output to be terminated to Vcc/2, or series terminated, or whatever.
> 
>           Regards,
>           Stephen Peters
>           Intel Corp.
> 
> > I have read with interest the latest version of the
> > IBIS cookbook.  It details recommended characterization
> > conditions for simulating TTL, ECL, LVCMOS, etc.  It
> > does not contain recommended conditions for measuring
> > newer I/Os, i.e. SSTL, HSTL, GTL, LVDS.
> >
> > What are the recommended simulation conditions for these
> > I/Os?
> >
> > Rob Eccles
> > Xilinx
> > rob.eccles@xilinx.com
From owner-ibis  Fri Dec 18 05:51:30 1998
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Rob,

In the case of a classic GTL driver (which uses feedback), you may also
want to sweep the resistance to Vtt (Rterm) over its effective operational
range.  Then compare behavioral simulation waveforms against SPICE
waveforms and see how close you can get.  I found that the simulator I was
using wasn't able to track SPICE very well.  I've been told that multiple
VT tables for different values for Rterm is one approach to solving the
"GTL feedback behavioral modeling problem," but I've never actually heard
the circuit theory behind this.

I guess all I'm saying is run some SPICE vs. behavioral correlation and
"model developer beware..."

Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com



Rob Eccles <rob.eccles@xilinx.com> on 12/17/98 07:57:28 PM

To:   Stephen Peters <sjpeters@ichips.intel.com>
cc:   ibis@eda.org, ibis-users@eda.org (bcc: Gregory R
      Edlund/Rochester/IBM)
Subject:  Re: Characterization Conditions





Hi Steve,

Thanks for your prompt reply!

After reading your response, and giving it some more thought,
it looks like SSTL and HSTL should use the same methodology
given in Table 1 for CMOS (from the 2.0X version of the Cookbook).

In practise, not all boards will use 50 Ohm loads.  How sensitive
are the IBIS models to termination resistance?  I would expect
this to be significant.

Regards,
Rob Eccles
Xilinx

Stephen Peters wrote:
>
> Hello Rob:
>
>    By "recommended characterization conditions" I assume you mean
> the output loads/voltages use to extract V/T waveforms.  Because the
> GTL/GTL+ outputs are open-drain, I would extract the V/T waveforms
> using the rules for open drain buffers -- a load resistor to
> Vterm, with the value of Rterm and Vterm determined by the
> specification or part manufacturer.  As for the other standards,
> if the driver uses a standard push/pull structure use the rules for
> standard CMOS or TTL (depending on the technology of the buffer).
> Remember: by taking the V/T waveforms with a load tied
> to Vcc then to ground, one can isolate the turn-on, turn-off and
> overlap times of the pullup and pulldown structures, thereby allowing
> the simulator to construct an accurate model of the driver.  This
> model should be accurate, even if the driver application calls for
> the output to be terminated to Vcc/2, or series terminated, or whatever.
>
>           Regards,
>           Stephen Peters
>           Intel Corp.
>
> > I have read with interest the latest version of the
> > IBIS cookbook.  It details recommended characterization
> > conditions for simulating TTL, ECL, LVCMOS, etc.  It
> > does not contain recommended conditions for measuring
> > newer I/Os, i.e. SSTL, HSTL, GTL, LVDS.
> >
> > What are the recommended simulation conditions for these
> > I/Os?
> >
> > Rob Eccles
> > Xilinx
> > rob.eccles@xilinx.com



From owner-ibis  Fri Dec 18 09:50:34 1998
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From: "Chris Rokusek" <crokusek@viewlogic.com>
To: "Rob Eccles" <rob.eccles@xilinx.com>
Cc: <ibis@eda.org>, <ibis-users@eda.org>
Subject: Re: Characterization Conditions
Date: Fri, 18 Dec 1998 09:35:18 -0800
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Rob,

Many simulators are interested in using results of driving the TRACE
IMPEDANCE seen by the driver which is where the 50 came from.  Vaguely
speaking--using the range of the DC V-I curves exercised by the VT loading
conditions together with the AC waveform data as inputs, the driver may then
be applied to arbitrary loads (termination, capacitance, diodes, ...) in
simulation to produce accurate results.

So as long as the load is near (e.g. within .25X to 4X) the impedance that
the driver sees during switching, simulation results should be nearly
identical for most devices.

DISCLAIMER: Simulators are not required to use the waveform data in any
particular manner so the above may not be true for all simulators.  However
the cookbook recommendations were developed under consensus of simulator
companies on the IBIS committee.

Regards,

Chris Rokusek
Viewlogic Systems


-----Original Message-----
From: Rob Eccles <rob.eccles@xilinx.com>
To: Stephen Peters <sjpeters@ichips.intel.com>
Cc: ibis@eda.org <ibis@eda.org>; ibis-users@eda.org <ibis-users@eda.org>
Date: Thursday, December 17, 1998 6:43 PM
Subject: Re: Characterization Conditions


>Hi Steve,
>
>Thanks for your prompt reply!
>
>After reading your response, and giving it some more thought,
>it looks like SSTL and HSTL should use the same methodology
>given in Table 1 for CMOS (from the 2.0X version of the Cookbook).
>
>In practise, not all boards will use 50 Ohm loads.  How sensitive
>are the IBIS models to termination resistance?  I would expect
>this to be significant.
>
>Regards,
>Rob Eccles
>Xilinx

From owner-ibis  Fri Dec 18 10:28:35 1998
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Date: Fri, 18 Dec 1998 10:23:15 -0800 (PST)
From: Syed Huq <shuq@cisco.com>
Message-Id: <199812181823.KAA25918@jasper.cisco.com>
To: ibis-users@vhdl.org
Subject: IPA software status - update
Cc: shuq@cisco.com
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Hello,

Here is an update on the status of IPA-510 software for web distribution:

IPA Binary:
-----------
The binary version will be made available by Jan'99 timeframe. Resource has
been allocated to work on a dongle-free version.

Discussion in progress to provide documentation along with binary.

IPA Source:
-----------
Initiated discussion with the GNU Project to see if they would be willing
to be 'maintainer'. GNU Project had various questions about IBIS, Modeling,
IPA etc etc. They outlined a set of conditions that the IPA needs to meet
to be GNU complaint. This will allow all GNU software to interact easily.

Tek is not sure about working with GNU. They feel that the software has more
value for IBIS community than GNU. Basically, GNU's involement is only to
be the source maintainer and not source code development.

Discussion with GNU/Tek/IBIS in progress regarding this.

FSF(Free Software Foundation) is also interested to provide support for 
a FEE to the IPA users community. This is still under discussion.

Next Step:
---------
I would like to make a call to any EDA company who would like to volunteer
some software expertise to be the 'maintainer'. No product development is
required from you. Only need to incorporate all the developments that may
be made by various companies and release 'ONE' consolidated version.

Any other ideas of source code distribution is welcome.

THis IPA discussion will again be on the next IBIS teleconferece(Jan15th).

Regards,
Syed.
Cisco Systems, Inc.
From owner-ibis  Fri Dec 18 12:26:37 1998
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Date: Fri, 18 Dec 1998 12:22:55 -0100
To: ibis-users@eda.org
From: Matthew Flora <mbflora@hyperlynx.com>
Subject: Software update (Visual IBIS Editor) - FYI
Mime-Version: 1.0
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To those of you using the freebee Visual IBIS Editor,

You can now view the graphs of all the V/T tables in a model (not just the
first one).  The Check Model feature has been updated to IBISCHK3.1.

The latest version is at the usual place (http://www.hyperlynx.com/vis_ibis.html).

Regards,
Matthew Flora
HyperLynx
From owner-ibis  Fri Dec 18 23:37:32 1998
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From: "A. D. Shirpadaraj" <ads@cadence.com>
Message-Id: <199812190732.NAA00415@corona.cadence.com>
To: shuq@cisco.com
Subject: Re: IPA software status - update
Cc: ibis-users@vhdl.org
X-Sun-Charset: US-ASCII


Hi Syed,

What is IPA-510 software? Could you please elaborate on this and
send some pointer to find  more info on the said software?


Thanks

Shripad
From owner-ibis  Mon Dec 21 09:20:32 1998
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Date: Mon, 21 Dec 1998 09:15:03 -0800 (PST)
From: Syed Huq <shuq@cisco.com>
Message-Id: <199812211715.JAA26919@jasper.cisco.com>
To: shuq@cisco.com, ads@cadence.com
Subject: Re: IPA software status - update
Cc: ibis-users@vhdl.org
Mime-Version: 1.0
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Shripad,

IPA(Interconnect Parametric Analyzer)is a software from Tektronix. 
This software is used along with a TDR to analyze and model(SPICE) 
interconnects. The software captures the reflection profile of the 
interconnect under test when  the TDR pulse(35ps edge)hits it. 
The IPA software then creates an impedance profile of the captured 
waveform and uses this to generate various types of SPICE models
(distributed, RLC, Lossy)etc etc.

I have used this software to extract C_comp parameter as well as V/T
table data for measurement based IBIS modeling. This is also great to
extract package parasitcs.

Since this product will be discontinued, Tektronix wants to give this 
software to the IBIS community for FREE(Both Binary and Source). So that's 
what the E-mail update is all about.

The reason they are giving this up is because they no longer want to
support the software. The idea is for anyone can take the source code, modify 
it for enhancement purpose and give back both the new binary and source back 
to the IBIS community. The tool gets enhanced and IBIS users benefit from
it. 

There are various good Application Notes on the www.tek.com site. Do
a search on 'IPA' and you will get all of them.

More updates to follow after the holidays...

Regards,
Syed.
Cisco Systems,Inc

> 
> 
> Hi Syed,
> 
> What is IPA-510 software? Could you please elaborate on this and
> send some pointer to find  more info on the said software?
> 
> 
> Thanks
> 
> Shripad
From owner-ibis  Mon Dec 21 09:46:34 1998
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From: Ted Creedon <ted_creedon@mentorg.com>
To: "'Syed Huq'" <shuq@cisco.com>, "ads@cadence.com" <ads@cadence.com>
Cc: "ibis-users@vhdl.org" <ibis-users@vhdl.org>
Subject: RE: IPA software status - update
Date: Mon, 21 Dec 1998 09:40:30 -0800
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Why IBIS doesn't jump on this opportunity is beyond me.  Interconnect is more of a problem than IC models.

I've offered to deliver IPA CD's but Tek has not responded.  Perhaps IBIS will.

Just send a completed license agreement and a check for $250 for shipping and handling.

Same as getting Xspice from Georgia Tech.

Ted Creedon, P.E.
Mentor Graphics ICX Models Group

PS I have an 11800 and SD-24. 

-----Original Message-----
From:	Syed Huq [SMTP:shuq@cisco.com]
Sent:	Monday, December 21, 1998 9:15 AM
To:	shuq@cisco.com; ads@cadence.com
Cc:	ibis-users@vhdl.org
Subject:	Re: IPA software status - update

Shripad,

IPA(Interconnect Parametric Analyzer)is a software from Tektronix. 
This software is used along with a TDR to analyze and model(SPICE) 
interconnects. The software captures the reflection profile of the 
interconnect under test when  the TDR pulse(35ps edge)hits it. 
The IPA software then creates an impedance profile of the captured 
waveform and uses this to generate various types of SPICE models
(distributed, RLC, Lossy)etc etc.

I have used this software to extract C_comp parameter as well as V/T
table data for measurement based IBIS modeling. This is also great to
extract package parasitcs.

Since this product will be discontinued, Tektronix wants to give this 
software to the IBIS community for FREE(Both Binary and Source). So that's 
what the E-mail update is all about.

The reason they are giving this up is because they no longer want to
support the software. The idea is for anyone can take the source code, modify 
it for enhancement purpose and give back both the new binary and source back 
to the IBIS community. The tool gets enhanced and IBIS users benefit from
it. 

There are various good Application Notes on the www.tek.com site. Do
a search on 'IPA' and you will get all of them.

More updates to follow after the holidays...

Regards,
Syed.
Cisco Systems,Inc

> 
> 
> Hi Syed,
> 
> What is IPA-510 software? Could you please elaborate on this and
> send some pointer to find  more info on the said software?
> 
> 
> Thanks
> 
> Shripad

From owner-ibis  Mon Dec 21 11:26:57 1998
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "\"'Syed Huq'\" " <shuq@cisco.com>,
        "\"ads@cadence.com\" "
	 <ads@cadence.com>,
        "\"Ted Creedon\" " <ted_creedon@mentorg.com>
Cc: "\"ibis-users@vhdl.org\" " <ibis-users@vhdl.org>
Subject: RE: IPA software status - update
Date: Mon, 21 Dec 1998 11:20:00 -0800
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Content-Type: text/plain

I believe we (members of the IBIS Open Forum) all jumped on it, but got 
suspended in mid-air buy the legal and new feature addition process 
implications/requirements, etc.  What I wonder about is whether we are going
to 
continue flying our jump or fall on our face...

It seems, though, that Syed is doing an excellent job in trying to find the 
appropriate gatekeepers for this software.

Arpad
============================================================================
====

Why IBIS doesn't jump on this opportunity is beyond me.  Interconnect is
more of
a problem than IC models.

I've offered to deliver IPA CD's but Tek has not responded.  Perhaps IBIS
will.

Just send a completed license agreement and a check for $250 for shipping
and
handling.

Same as getting Xspice from Georgia Tech.

Ted Creedon, P.E.
Mentor Graphics ICX Models Group

PS I have an 11800 and SD-24.

-----Original Message-----
From:     Syed Huq [SMTP:shuq@cisco.com]
Sent:     Monday, December 21, 1998 9:15 AM
To:     shuq@cisco.com; ads@cadence.com
Cc:     ibis-users@vhdl.org
Subject:     Re: IPA software status - update

Shripad,

IPA(Interconnect Parametric Analyzer)is a software from Tektronix.
This software is used along with a TDR to analyze and model(SPICE)
interconnects. The software captures the reflection profile of the
interconnect under test when  the TDR pulse(35ps edge)hits it.
The IPA software then creates an impedance profile of the captured
waveform and uses this to generate various types of SPICE models
(distributed, RLC, Lossy)etc etc.

I have used this software to extract C_comp parameter as well as V/T
table data for measurement based IBIS modeling. This is also great to
extract package parasitcs.

Since this product will be discontinued, Tektronix wants to give this
software to the IBIS community for FREE(Both Binary and Source). So that's
what the E-mail update is all about.

The reason they are giving this up is because they no longer want to
support the software. The idea is for anyone can take the source code,
modify
it for enhancement purpose and give back both the new binary and source back
to the IBIS community. The tool gets enhanced and IBIS users benefit from
it.

There are various good Application Notes on the www.tek.com site. Do
a search on 'IPA' and you will get all of them.

More updates to follow after the holidays...

Regards,
Syed.
Cisco Systems,Inc

>
>
> Hi Syed,
>
> What is IPA-510 software? Could you please elaborate on this and
> send some pointer to find  more info on the said software?
>
>
> Thanks
>
> Shripad
From owner-ibis  Mon Dec 21 11:34:28 1998
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Date: Mon, 21 Dec 1998 11:28:28 -0800 (PST)
From: Syed Huq <shuq@cisco.com>
Message-Id: <199812211928.LAA06204@jasper.cisco.com>
To: shuq@cisco.com, ads@cadence.com, ted_creedon@mentorg.com,
        arpad.muranyi@intel.com
Subject: RE: IPA software status - update
Cc: ibis-users@vhdl.org
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I say we are flying...The ball is rolling and I am in touch with individuals
as well as the GNU project to resolve 'gatekeeper/maintainer' issues.

Thank you all for your support and more info to come after the New Year..

Happy Holidays..
Syed.
Cisco Systems, Inc

> 
> I believe we (members of the IBIS Open Forum) all jumped on it, but got 
> suspended in mid-air buy the legal and new feature addition process 
> implications/requirements, etc.  What I wonder about is whether we are going
> to 
> continue flying our jump or fall on our face...
> 
> It seems, though, that Syed is doing an excellent job in trying to find the 
> appropriate gatekeepers for this software.
> 
> Arpad
> ============================================================================
> ====
> 
> Why IBIS doesn't jump on this opportunity is beyond me.  Interconnect is
> more of
> a problem than IC models.
> 
> I've offered to deliver IPA CD's but Tek has not responded.  Perhaps IBIS
> will.
> 
> Just send a completed license agreement and a check for $250 for shipping
> and
> handling.
> 
> Same as getting Xspice from Georgia Tech.
> 
> Ted Creedon, P.E.
> Mentor Graphics ICX Models Group
> 
> PS I have an 11800 and SD-24.
> 
> -----Original Message-----
> From:     Syed Huq [SMTP:shuq@cisco.com]
> Sent:     Monday, December 21, 1998 9:15 AM
> To:     shuq@cisco.com; ads@cadence.com
> Cc:     ibis-users@vhdl.org
> Subject:     Re: IPA software status - update
> 
> Shripad,
> 
> IPA(Interconnect Parametric Analyzer)is a software from Tektronix.
> This software is used along with a TDR to analyze and model(SPICE)
> interconnects. The software captures the reflection profile of the
> interconnect under test when  the TDR pulse(35ps edge)hits it.
> The IPA software then creates an impedance profile of the captured
> waveform and uses this to generate various types of SPICE models
> (distributed, RLC, Lossy)etc etc.
> 
> I have used this software to extract C_comp parameter as well as V/T
> table data for measurement based IBIS modeling. This is also great to
> extract package parasitcs.
> 
> Since this product will be discontinued, Tektronix wants to give this
> software to the IBIS community for FREE(Both Binary and Source). So that's
> what the E-mail update is all about.
> 
> The reason they are giving this up is because they no longer want to
> support the software. The idea is for anyone can take the source code,
> modify
> it for enhancement purpose and give back both the new binary and source back
> to the IBIS community. The tool gets enhanced and IBIS users benefit from
> it.
> 
> There are various good Application Notes on the www.tek.com site. Do
> a search on 'IPA' and you will get all of them.
> 
> More updates to follow after the holidays...
> 
> Regards,
> Syed.
> Cisco Systems,Inc
> 
> >
> >
> > Hi Syed,
> >
> > What is IPA-510 software? Could you please elaborate on this and
> > send some pointer to find  more info on the said software?
> >
> >
> > Thanks
> >
> > Shripad
From owner-ibis  Mon Dec 21 12:09:44 1998
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From: Al Davis <al@al.dynip.com>
X-Sender: al@oliver
To: Syed Huq <shuq@cisco.com>
cc: ads@cadence.com, ted_creedon@mentorg.com, arpad.muranyi@intel.com,
        ibis-users@vhdl.org
Subject: RE: IPA software status - update
In-Reply-To: <199812211928.LAA06204@jasper.cisco.com>
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MIME-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII


The GNU people have lots to do and don't need the extra burden of
something like this that they don't understand.  You can maintain
ownership and distribute under the GNU public license without any
connection to the Free Software Foundation.  You don't need their
permission to do this.  Most software distributed under GPL is owned by
its creater, not FSF.

So ..  attach GPL.  post to IBIS site.


From owner-ibis  Wed Dec 23 04:55:38 1998
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Date: Wed, 23 Dec 1998 14:46:51 +0200
From: Dan Aleksandrowicz <dan@galileo.co.il>
Organization: GALILEO Technology Ltd.
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To: "ibis-users@eda.org" <ibis-users@eda.org>
Subject: IBIS model Accuracy 
Content-Type: multipart/alternative; boundary="------------6F9F2E3A366B7CB0D0F988B1"


--------------6F9F2E3A366B7CB0D0F988B1
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Hi there.

I would like to know if there is any new developments in
the accuracy issue.

I have recently started to receive PCB measurements
wave forms. And I would like to know if there is any
suggested standard to measure the accuracy of my IBIS
model. Especially VS the simulated wave forms.

Thanks

Dan.

--
                \\|//
                (o o)
~~~~~~~~~~~~oOOo~(_)~oOOo~~~~~~~~~~~~~~~~~~~
Dan Aleksandrowicz
Galileo Technology
Giron 15, Yahud - Israel
email:dan@galileo.co.il
Tel: +972 3 6320220    (-
     Ext. 324         |__|
                      |__|
                     #|oo| |--|   ___
           _  _    |--|  | |  |\ |oo|)        /\
       __  \\ \\   |------------\| #|--\     _||-
   ____\ \__\\_\\__|_||_________________\___|   |__v-___
   \                                                   /
    \      "Smoke on the water. Fire in the sky."     /
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



--------------6F9F2E3A366B7CB0D0F988B1
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<HTML>
Hi there.

<P>I would like to know if there is any new developments in
<BR>the accuracy issue.

<P>I have recently started to receive PCB measurements
<BR>wave forms. And I would like to know if there is any
<BR>suggested standard to measure the accuracy of my IBIS
<BR>model. Especially VS the simulated wave forms.

<P>Thanks

<P>Dan.
<PRE>--&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; \\|//
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (o o)
~~~~~~~~~~~~oOOo~(_)~oOOo~~~~~~~~~~~~~~~~~~~
Dan Aleksandrowicz
Galileo Technology&nbsp;
Giron 15, Yahud - Israel
email:dan@galileo.co.il
Tel: +972 3 6320220&nbsp;&nbsp;&nbsp; (-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp; Ext. 324&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |__|
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |__|
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #|oo| |--|&nbsp;&nbsp; ___
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; _&nbsp; _&nbsp;&nbsp;&nbsp; |--|&nbsp; | |&nbsp; |\ |oo|)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /\
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; __&nbsp; \\ \\&nbsp;&nbsp; |------------\| #|--\&nbsp;&nbsp;&nbsp;&nbsp; _||-
&nbsp;&nbsp; ____\ \__\\_\\__|_||_________________\___|&nbsp;&nbsp; |__v-___
&nbsp;&nbsp; \&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /
&nbsp;&nbsp;&nbsp; \&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "Smoke on the water. Fire in the sky."&nbsp;&nbsp;&nbsp;&nbsp; /
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~</PRE>
&nbsp;</HTML>

--------------6F9F2E3A366B7CB0D0F988B1--

From owner-ibis  Wed Dec 23 05:39:42 1998
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From: Robert Haller <Robert.Haller@digital.com>
To: "'Dan Aleksandrowicz'" <dan@galileo.co.il>
Cc: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: RE: IBIS model Accuracy 
Date: Wed, 23 Dec 1998 08:34:47 -0500
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Dan,
 A group of us (the IBIS accuracy Subcomittee) have been working on such
a document. We call it The IBIS Accuracy Specification.This is not a
standard yet, but we are presently working towards that end . Take a
look and feed us back any comments.
http://www.vhdl.org/pub/ibis/accuracy/ 
Regards,
Bob Haller




-----Original Message-----
From: Dan Aleksandrowicz [mailto:dan@galileo.co.il]
Sent: Wednesday, December 23, 1998 7:47 AM
To: ibis-users@eda.org
Subject: IBIS model Accuracy 


Hi there. 
I would like to know if there is any new developments in 
the accuracy issue. 
I have recently started to receive PCB measurements 
wave forms. And I would like to know if there is any 
suggested standard to measure the accuracy of my IBIS 
model. Especially VS the simulated wave forms. 
Thanks 
Dan. 
--
 \\|//
 (o o)
~~~~~~~~~~~~oOOo~(_)~oOOo~~~~~~~~~~~~~~~~~~~
Dan Aleksandrowicz
Galileo Technology
Giron 15, Yahud - Israel
email:dan@galileo.co.il
Tel: +972 3 6320220 (-
 Ext. 324 |__|
 |__|
 #|oo| |--| ___
 _ _ |--| | | |\ |oo|) /\
 __ \\ \\ |------------\| #|--\ _||-
 ____\ \__\\_\\__|_||_________________\___| |__v-___
 \ /
 \ Smoke on the water. Fire in the sky. /
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
From owner-ibis  Wed Dec 23 08:18:15 1998
Received: from jasper.cisco.com (jasper.cisco.com [171.69.198.63]) by server.eda.org (8.8.5/8.8.3) with ESMTP id IAA02349 for <ibis-users@vhdl.org>; Wed, 23 Dec 1998 08:18:15 -0800 (PST)
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Date: Wed, 23 Dec 1998 08:12:06 -0800 (PST)
From: Syed Huq <shuq@cisco.com>
Message-Id: <199812231612.IAA22524@jasper.cisco.com>
To: shuq@cisco.com, al@al.dynip.com
Subject: RE: IPA software status - update
Cc: ads@cadence.com, ted_creedon@mentorg.com, arpad.muranyi@intel.com,
        ibis-users@vhdl.org
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Distribution of the IPA is not an issue. We can do that from our website
with no problem. The issue is to find a maintainer(volunteer!)..That is
being worked on.

Syed.
Cisco Systems, Inc.

> From al@al.dynip.com Mon Dec 21 12:04:08 1998
> X-SMAP-Received-From: outside
> Date: Mon, 21 Dec 1998 12:04:16 -0800 (PST)
> From: Al Davis <al@al.dynip.com>
> X-Sender: al@oliver
> To: Syed Huq <shuq@cisco.com>
> cc: ads@cadence.com, ted_creedon@mentorg.com, arpad.muranyi@intel.com,
        ibis-users@vhdl.org
> Subject: RE: IPA software status - update
> MIME-Version: 1.0
> 
> 
> The GNU people have lots to do and don't need the extra burden of
> something like this that they don't understand.  You can maintain
> ownership and distribute under the GNU public license without any
> connection to the Free Software Foundation.  You don't need their
> permission to do this.  Most software distributed under GPL is owned by
> its creater, not FSF.
> 
> So ..  attach GPL.  post to IBIS site.
> 
> 
From owner-ibis  Wed Dec 23 10:39:13 1998
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Date: Wed, 23 Dec 1998 12:06:14 -0500
To: ibis-users@eda.org, si-list@silab.Eng.Sun.COM
From: Kathy Breda <breda@nesa.com>
Subject: IBIS Users Meeting - Thurs. 1/14/99, 3:00pm
Cc: slattery@nesa.com
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<bold><bigger>IBIS Users  Meeting - Thursday, January 14, 1999

</bigger></bold><bold><bigger>-----------------------------------------------


Date:</bigger></bold><bigger>     Thursday, January 14, 1998

<bold>Time:</bold>     3:00 PM to 5:00 PM

<bold>Place:</bold>	North East Systems Associates, Inc. (NESA)

		636 Great Rd. (otherwise known as Route 117)

		Stow, MA 01775

		TEL: (978) 897-8787 (do you want to conference link into meeting?)

		N.B. Directions to NESA at end of this message


<bold>Agenda:</bold>	* IBIS Accuracy Specification Status


		* IBIS Connector Model Status


		  Preparation for upcoming IBIS Summit 

            (at DesignCon99, Santa Clara, CA, February 1, 1999)


		* IBIS WEB page


		* Any other business

<bold>


What is IBIS**IBIS WEB Page**IBIS User Group Activities

</bold></bigger>

IBIS = I/O Buffer Information Specification

      The design community primarily uses electronic design tools and 

	SPICE (Simulation Program with Integrated Circuit Emphasis) 

	to develop and test the viability and performance characteristics of
their designs.

	The IBIS standard is an alternative method of simulation for high speed
designs that 

	uses behavioral models verses transistor level models.


IBIS Web page located at :  http://www.eigroup.org/ibis/ibis.htm



We had a well attended and informative IBIS Summit in October and now it
is

time to get going with the IBIS user meetings again.  The IBIS

Users group continues to move forward with the IBIS Accuracy
Specification

and test board,IBIS Connector modeling and training initiatives.  We

are hoping for additional involvement from the engineering community

in 1999 and are looking for input, involvement and ideas.


Do you want to come up to speed and learn about IBIS...?


   Do you want to develop/investigate a particular IBIS related idea

   that would assist with your system designs...?


	Do you want to share your experiences using IBIS models and get

	feedback...?


     	   Do you want to get generally involved in the current IBIS User
group discussions...?



Please feel free to join the IBIS User group meetings - all are 
welcome,

in person or by conference link!  Let Kathy Breda (breda@nesa.com) know

if you would like to attend so we have enough chairs and brownies! 
Also,

if you would like to connect via conference phone, please let Kathy 
know

and she will arrange the details.


Additional names have been added to the IBIS distribution list,

so if you did not attend the Summit and need copies of the
presentations,

you can get them off the IBIS web page (URL listed above) or contact
Kathy.


Directions to NESA:


		From 495, take exit 27 (route 117, towards Maynard)

		Follow 117 for about 3.5 miles

		NESA is located on the second floor of the 

		Stow Brook Offices, on the corner of 

		Route 117 and Hudson Rd.  Stow Brook Offices

		are located across the street from CW fuels.


		You can also reach Route 117 from Route 128.

		Once on Route 117 follow road until you reach

		Hudson Rd. in Stow, see details above.


Happy Holidays to All,



    		Kathy Breda


<<end>





+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

|       NORTH EAST SYSTEMS ASSOCIATES, INC.       |

|      -------------------------------------      |

|     "High Performance Engineering & Design"     |

+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

| Kathy Breda             e-mail: breda@nesa.com |

| NESA, Inc.              http://www.nesa.com/    |

| 636 Great Road          Tel +1.978.897-8787     |

| Stow, MA 01775 USA      Fax +1.978.897-5359     |

+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+


