From owner-ibis Fri May 1 16:49:30 1998 Received: from mail.nwlink.com (mail.nwlink.com [209.20.130.40]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA11300 for ; Fri, 1 May 1998 16:49:30 -0700 (PDT) Received: (from kellee@localhost) by mail.nwlink.com (8.8.8/8.8.8) id QAA09178; Fri, 1 May 1998 16:46:21 -0700 (PDT) Message-Id: <3.0.5.32.19980501164617.00e20100@mail.nwlink.com> X-Sender: kellee@mail.nwlink.com X-Mailer: QUALCOMM Windows Eudora Pro Version 3.0.5 (32) Date: Fri, 01 May 1998 16:46:17 -0700 To: ibis-users@eda.org From: Kellee Crisafulli Subject: Re: IBIS User Group Minutes - 4/23/98 In-Reply-To: <3.0.3.32.19980430160848.00774460@mail.nesa.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Hi all, I have 2 items: 1) HyperLynx was left out of the list of vendors supplying free simulation engines to IC vendors: We were the first to offer this back in Jan. at the Design Con IBIS meeting and I bet we have by far supplied the most free packages to IC vendors to date. I would very much appreciate being mentioned in the same list as those that also agreed at a later date to do the same. We have already supplied a large number of packages to IC vendors free of charge and have been doing so to various degrees since IBIS V0.9 was released years ago. > Request from Bruce Helbrunn to EDA vendors that free simulation >engine be made available to IC vendors has received >a positive response from Quad Design, Interconnectix/Mentor and Cadence 2) I reviewed the test loads that Greg Edlund sent out and noticed there might be some room for improvement I offer the following for your consideration. All the following assumes this validation is against a real test board you have. If the goal is to just compare the simulators than ignore this but there may be a problem determining just which simulator is correct. After listening to Greg's talk at the Jan. 1998 Design Con IBIS meeting I recall two goals for his test board: 1) To validate the IBIS model data matches the real device under test. 2) To insure all the simulators work with the models and provide the same simulation results into real boards (i.e. transmission lines). Hopefully I am not confusing his talk with one of the others. I believe the loads shown do a good job with item 2 but item 1 might benefit from a change. I would like to see two additional cases for push/pull that have pull up/down resistors without a transmission lines. This allows the V/T table to be validated without the interaction of the transmission lines. Also for the purposes real board validation the probing ground lead length, probe capacitance and probe locations should be specified. ------------------------------------------------------------------------- Have a great day... Kellee Crisafulli at HyperLynx kellee@hyperlynx.com http://www.hyperlynx.com ------------------------------------------------------------------------- From owner-ibis Mon May 4 05:22:46 1998 Received: from mail13.digital.com (mail13.digital.com [192.208.46.30]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id FAA05447 for ; Mon, 4 May 1998 05:22:44 -0700 (PDT) Received: from sbuamazko2ae.zko.dec.com (sbuamazko2ae.zko.dec.com [16.29.160.92]) by mail13.digital.com (8.8.8/8.8.8/WV1.0d) with ESMTP id IAA10936 for ; Mon, 4 May 1998 08:19:27 -0400 (EDT) Received: by sbuamazko2ae.zko.dec.com with Internet Mail Service (5.0.1458.49) id ; Mon, 4 May 1998 08:19:35 -0400 Message-ID: <71EEA9EA5129D1118EA30000F840EBF15379E3@sbuamapko3bc.eng.pko.dec.com> From: Greg Edlund To: "'ibis-users@eda.org'" Subject: RE: IBIS User Group Minutes - 4/23/98 Date: Mon, 4 May 1998 08:10:25 -0400 X-Priority: 3 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.0.1458.49) Content-Type: text/plain; charset="iso-8859-1" Kellee, I think the reason Hyperlynx was not on the list was that we were tracking the progress of EDA vendors who had NOT yet developed a free model development kit as Hyperlynx already has. Perhaps this wasn't real clear from the minutes. I can certainly make a note of this in the Accuracy Subcommittee minutes, which will come out this week. Thanks for looking at the test loads. Getting rid of the transmission line would certainly eliminate some variables. Electrically, an ideally terminated transmission line and a resistive load are identical, but real boards are not ideal. The reason we decided to put the probe point at the end of a transmission line in our test board is that we couldn't place all of our probe points right next to the DUT and still route around them. (We have twice as many loads as necessary on the test board to demonstrate different probing technologies.) I think we should mention in our documentation for the board that placing a resistive load right next to the DUT would be desirable. Good point about the probe parasitics, too. To add to what you said about the purpose of doing the test board, it is really an example of how one might implement the IBIS Accuracy Specification to demonstrate lab vs. simulation correlation. Other people will come up with other ways, but this is a start. We're hoping we can dodge the "simulation engine question" (i.e. where do the various engines begin to disagree with each other and SPICE?) by sticking to push-pull and open drain drivers at roughly IBIS 1.1 level for the first version of the spec. The reason we'd like every EDA vendor to distribute a model development kit is so that IC vendors can chose one that meets their needs as well as the needs of their customers. Thanks for taking the time to write. I really appreciate the input. Greg ---------- Greg Edlund, Principal Engineer Server Product Development Digital Equipment Corp. 129 Parker St. PKO3-1/20C Maynard, MA 01754 (978) 493-4157 voice (978) 493-0941 FAX greg.edlund@digital.com ---------- From: Kellee Crisafulli[SMTP:kellee@hyperlynx.com] Sent: Friday, May 01, 1998 7:46 PM To: ibis-users@eda.org Subject: Re: IBIS User Group Minutes - 4/23/98 Hi all, I have 2 items: 1) HyperLynx was left out of the list of vendors supplying free simulation engines to IC vendors: We were the first to offer this back in Jan. at the Design Con IBIS meeting and I bet we have by far supplied the most free packages to IC vendors to date. I would very much appreciate being mentioned in the same list as those that also agreed at a later date to do the same. We have already supplied a large number of packages to IC vendors free of charge and have been doing so to various degrees since IBIS V0.9 was released years ago. > Request from Bruce Helbrunn to EDA vendors that free simulation >engine be made available to IC vendors has received >a positive response from Quad Design, Interconnectix/Mentor and Cadence 2) I reviewed the test loads that Greg Edlund sent out and noticed there might be some room for improvement I offer the following for your consideration. All the following assumes this validation is against a real test board you have. If the goal is to just compare the simulators than ignore this but there may be a problem determining just which simulator is correct. After listening to Greg's talk at the Jan. 1998 Design Con IBIS meeting I recall two goals for his test board: 1) To validate the IBIS model data matches the real device under test. 2) To insure all the simulators work with the models and provide the same simulation results into real boards (i.e. transmission lines). Hopefully I am not confusing his talk with one of the others. I believe the loads shown do a good job with item 2 but item 1 might benefit from a change. I would like to see two additional cases for push/pull that have pull up/down resistors without a transmission lines. This allows the V/T table to be validated without the interaction of the transmission lines. Also for the purposes real board validation the probing ground lead length, probe capacitance and probe locations should be specified. ------------------------------------------------------------------------ - Have a great day... Kellee Crisafulli at HyperLynx kellee@hyperlynx.com http://www.hyperlynx.com ------------------------------------------------------------------------ - From owner-ibis Tue May 5 07:54:15 1998 Received: from wile.nesa.com ([204.240.29.30]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id HAA02688 for ; Tue, 5 May 1998 07:54:13 -0700 (PDT) Received: (from mail@localhost) by wile.nesa.com (8.8.5/8.8.5) id KAA12936; Tue, 5 May 1998 10:14:16 -0400 Received: from porky.nesa.com(204.240.29.45) by wile.nesa.com via smap (V1.3) id sma012931; Tue May 5 10:13:59 1998 Message-Id: <3.0.3.32.19980505101359.00c79898@mail.nesa.com> X-Sender: breda@mail.nesa.com X-Mailer: QUALCOMM Windows Eudora Pro Version 3.0.3 (32) Date: Tue, 05 May 1998 10:13:59 -0400 To: ibis-users@eda.org From: Kathy Breda Subject: IBIS USERS -NEW MEETING DATE Thur, 5/28/98 Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" IBIS Users Group Members: We're changing the date of the IBIS User Group meeting by moving it out one week, due to conference room availability issues. NEW MEETING DETAILS: DATE: Thursday, May 28, 1998 TIME: 3:00 PM LOCATION: Stratus, Marlboro MA Customer Conference Room 7, Visitor Center (The Visitor Center is located right by the main lobby) If you would let me know that you're attending we can send the list ahead to Stratus to avoid delays in signing in at their security desk. PROPOSED AGENDA: (always looking for input) * IBIS education topic - Review/Overview of IBIS versions * Update on Connector Modeling BIRD * Accuracy Specification and Test Board Update * More on IBIS education curriculum MAP and DIRECTIONS to STRATUS: A map and directions can be found: http://www.stratus.com/int/locations/home.html Directions: >From I-495 Take Exit 25A "To 85 / Marlboro". Travel on this road about 2 miles toward Route 85 and go to the second traffic light. Turn right on Route 85, at the 99 Restaurant. Follow 85 South just over 1 mile to the second traffic light, and turn right onto Hudson Street. (Look for a big sign for Golf Driving Range). Continue straight up the hill toward the large Stratus sign. Take the first right and follow the signs to Visitor Parking. There you will find the Main Lobby. Please check in here. 4 exit 25a | 9----------------------+- 5 | Route 8 X-+ 5 South Stratus \ | Building \ | ---Hudson St-+ | From owner-ibis Tue May 12 19:58:31 1998 Received: from ns1.digital.com.sg (ns1.digital.com.sg [203.127.158.130]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id TAA14085 for ; Tue, 12 May 1998 19:58:29 -0700 (PDT) Received: from hgobh1.hgo.dec.com (hgobh1.hgo.dec.com [16.169.80.250]) by ns1.digital.com.sg (8.8.8/8.8.8/WV1.0c) with ESMTP id KAA25321; Wed, 13 May 1998 10:53:21 +0800 (SST) Received: by hgobh1.hgo.dec.com with Internet Mail Service (5.5.1960.3) id ; Wed, 13 May 1998 10:54:38 +0800 Message-ID: <2689006BD5ACD011AE890000F82295EBE00DA3@taoexc1.tao.dec.com> From: John Lin - TAO To: "'IBIS_USER'" Cc: "'SI_LIST'" Subject: Does IBIS describe output transition which both MOS turned on? Date: Wed, 13 May 1998 10:54:34 +0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.1960.3) Content-Type: text/plain; charset="iso-8859-1" Dear IBIS fans/SI Experts, As I know for a CMOS device, during output transition, both PMOS and NMOS will turn on in a short period of time. I wonder if an IBIS model describes this behavior. If yes then how it does. Will the behavior affect the accuracy of simulation with IBIS model? Based on what I know the V-I curve for PULL UP or DOWN is obtained by turning one MOS off and then swift the V-fixture to get Current reading. It seems to me that the V_I curve doesn't contain the information to describe the transition, both PMOS and NMOS turned on. Any comment? Thanks, JOHNLIN CAE Engineer of EDA Department Digital Equipment Corp. Taiwan Branch Email: Linjohn@mail.dec.com TEL: 1-886-3-3900000 ext. 2152 From owner-ibis Tue May 12 23:07:25 1998 Received: from postoffice.cisco.com (postoffice-lane0.cisco.com [171.69.197.66]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id XAA16751 for ; Tue, 12 May 1998 23:07:24 -0700 (PDT) Received: from cisco.com (sj-dial-1-83.cisco.com [171.68.180.84]) by postoffice.cisco.com (8.8.5-Cisco.1/8.6.5) with ESMTP id WAA07364; Tue, 12 May 1998 22:53:46 -0700 (PDT) Sender: vinu@cisco.com Message-ID: <355935FC.4C5C94E3@cisco.com> Date: Tue, 12 May 1998 22:56:12 -0700 From: Vinu Arumugham X-Mailer: Mozilla 4.05 [en] (X11; I; Linux 2.0.27 i586) MIME-Version: 1.0 To: John Lin - TAO CC: "'IBIS_USER'" , "'SI_LIST'" Subject: Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? References: <2689006BD5ACD011AE890000F82295EBE00DA3@taoexc1.tao.dec.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit John, IBIS models also have V/T curves. These should cover overlapped conduction. Vinu John Lin - TAO wrote: > Dear IBIS fans/SI Experts, > > As I know for a CMOS device, during output transition, both PMOS and > NMOS will turn on in a short period of time. I wonder if an IBIS model > describes this behavior. If yes then how it does. Will the behavior > affect the accuracy of simulation with IBIS model? > > Based on what I know the V-I curve for PULL UP or DOWN is obtained by > turning one MOS off and then swift the V-fixture to get Current reading. > It seems to me that the V_I curve doesn't contain the information to > describe the transition, both PMOS and NMOS turned on. > > Any comment? > > Thanks, > > JOHNLIN > CAE Engineer of EDA Department > Digital Equipment Corp. Taiwan Branch > Email: Linjohn@mail.dec.com > TEL: 1-886-3-3900000 ext. 2152 From owner-ibis Wed May 13 00:07:21 1998 Received: from gatekeep.ti.com (gatekeep.ti.com [192.94.94.61]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id AAA17661 for ; Wed, 13 May 1998 00:07:20 -0700 (PDT) Received: from dncp01.itg.ti.com ([137.167.106.201]) by gatekeep.ti.com (8.8.8) with ESMTP id BAA16721; Wed, 13 May 1998 01:52:52 -0500 (CDT) Received: from ti (CNA0916056.tif.ti.com [137.167.98.242]) by dncp01.itg.ti.com (8.8.7/8.8.7) with SMTP id IAA04337; Wed, 13 May 1998 08:49:07 +0100 (WET DST) X-Mailer: BeyondMail for Windows/Professional 2.3 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit To: Vinu Arumugham From: Jean-Claude Perrin Subject: fwd: Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? Date: Wed, 13 May 1998 08:52:37 -0700 X-BeyondMail-Priority: 1 Message-Id: Conversation-Id: <355935FC.4C5C94E3@cisco.com> In-Reply-To: <355935FC.4C5C94E3@cisco.com> Reply-To: Jean-Claude Perrin Cc: Christian.Marot@TLSM70.tls1.siemens.net, claude.huet@avions.aerospatiale.fr, "'IBIS_USER'" , "W.John", "F.Saba", John Lin - TAO , lionel.dreux@siege.aerospatiale.fr, "PT. Jenen", "'SI_LIST'" X-Receipt-From-Agent: true Vinu, This is not really true. The V/T curve in the IBIS model definition does not give any information about the PMO/CMOS overlapped current. The V/T describes the behavior of the buffer output versus frequency but does not give any information on the current passing internaly through the output transistors. To know the value of the through current it is necessary to know the "Ron" variation of the two transistors during the transition periode. The value of this current depends upon the equivalent impedance of the two transistors, impedance which is connected between Vdd and Vss power supply. Jean Claude Perrin ------------------ Original text From: Vinu Arumugham , on 5/12/98 10:56 PM: To: John Lin - TAO Cc: "'IBIS_USER'" , "'SI_LIST'" John, IBIS models also have V/T curves. These should cover overlapped conduction. Vinu John Lin - TAO wrote: > Dear IBIS fans/SI Experts, > > As I know for a CMOS device, during output transition, both PMOS and > NMOS will turn on in a short period of time. I wonder if an IBIS model > describes this behavior. If yes then how it does. Will the behavior > affect the accuracy of simulation with IBIS model? > > Based on what I know the V-I curve for PULL UP or DOWN is obtained by > turning one MOS off and then swift the V-fixture to get Current reading. > It seems to me that the V_I curve doesn't contain the information to > describe the transition, both PMOS and NMOS turned on. > > Any comment? > > Thanks, > > JOHNLIN > CAE Engineer of EDA Department > Digital Equipment Corp. Taiwan Branch > Email: Linjohn@mail.dec.com > TEL: 1-886-3-3900000 ext. 2152 From owner-ibis Wed May 13 01:06:31 1998 Received: from mailgate.cadence.com (mailgate.Cadence.COM [158.140.2.1]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id BAA18473 for ; Wed, 13 May 1998 01:06:30 -0700 (PDT) Received: (from smap@localhost) by mailgate.cadence.com (8.8.5/8.6.8) id AAA04270; Wed, 13 May 1998 00:59:12 -0700 (PDT) Received: from corona.cadence.com(158.140.127.12) by mailgate.cadence.com via smap (mjr-v1.2) id xma895046349.004246; Wed, 13 May 98 00:59:09 -0700 Received: (from ads@localhost) by corona.cadence.com (8.8.5/8.8.5) id NAA26126; Wed, 13 May 1998 13:29:49 +0531 (IST) Date: Wed, 13 May 1998 13:29:49 +0531 (IST) From: "A. D. Shirpadaraj" Message-Id: <199805130758.NAA26126@corona.cadence.com> To: vinu@cisco.com, jc-perrin@ti.com Subject: Re: fwd: Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? Cc: Christian.Marot@TLSM70.tls1.siemens.net, claude.huet@avions.aerospatiale.fr, ibis-users@eda.org, john@c-lab.de, kaleu@c-lab.de, LinJohn@digital.com, lionel.dreux@siege.aerospatiale.fr, ptj@delta.dk, si-list@silab.Eng.Sun.COM X-Sun-Charset: US-ASCII Hi Jean, V-T curve implicitly contains the behaviour of a buffer during transition. If you want to know the magnitude of current passing through the transistors during transition, then it may not be possible from IBIS data directly. ^ VDD | ___| |------| | |__ | | -- ----| |-------0-----/\/\/\-----0VREF \ | | | \___ | ___| | -----o| ----- |__ ----- | | | | --------0 ___|___ _____ _ During transition current being drawn(or sunk) from Vref varies continously, which will be reflected in the output waveform. So in that way V-T curve does capture transition behaviour of a buffer. If you have more than one V-T curve, the transition can be modelled more accurately. Thanks Shripadaraj Cadence Design Systems NOIDA India ----- Begin Included Message ----- From owner-ibis@server.vhdl.org Wed May 13 12:36 IST 1998 MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit To: Vinu Arumugham From: Jean-Claude Perrin Subject: fwd: Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? Date: Wed, 13 May 1998 08:52:37 -0700 X-BeyondMail-Priority: 1 Conversation-Id: <355935FC.4C5C94E3@cisco.com> Cc: Christian.Marot@TLSM70.tls1.siemens.net, claude.huet@avions.aerospatiale.fr, "'IBIS_USER'" , "W.John", "F.Saba", John Lin - TAO , lionel.dreux@siege.aerospatiale.fr, "PT. Jenen", "'SI_LIST'" X-Receipt-From-Agent: true Vinu, This is not really true. The V/T curve in the IBIS model definition does not give any information about the PMO/CMOS overlapped current. The V/T describes the behavior of the buffer output versus frequency but does not give any information on the current passing internaly through the output transistors. To know the value of the through current it is necessary to know the "Ron" variation of the two transistors during the transition periode. The value of this current depends upon the equivalent impedance of the two transistors, impedance which is connected between Vdd and Vss power supply. Jean Claude Perrin ------------------ Original text From: Vinu Arumugham , on 5/12/98 10:56 PM: To: John Lin - TAO Cc: "'IBIS_USER'" , "'SI_LIST'" John, IBIS models also have V/T curves. These should cover overlapped conduction. Vinu John Lin - TAO wrote: > Dear IBIS fans/SI Experts, > > As I know for a CMOS device, during output transition, both PMOS and > NMOS will turn on in a short period of time. I wonder if an IBIS model > describes this behavior. If yes then how it does. Will the behavior > affect the accuracy of simulation with IBIS model? > > Based on what I know the V-I curve for PULL UP or DOWN is obtained by > turning one MOS off and then swift the V-fixture to get Current reading. > It seems to me that the V_I curve doesn't contain the information to > describe the transition, both PMOS and NMOS turned on. > > Any comment? > > Thanks, > > JOHNLIN > CAE Engineer of EDA Department > Digital Equipment Corp. Taiwan Branch > Email: Linjohn@mail.dec.com > TEL: 1-886-3-3900000 ext. 2152 ----- End Included Message ----- From owner-ibis Wed May 13 07:46:35 1998 Received: from relayhost.vlsi.com (relayhost.vlsi.com [134.27.20.23]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id HAA25169 for ; Wed, 13 May 1998 07:46:35 -0700 (PDT) Received: (from nobody@localhost) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) id HAA24328; Wed, 13 May 1998 07:42:51 -0700 Received: from unknown(134.27.128.26) by osiris via smap (V2.0) id xma024295; Wed, 13 May 98 07:42:36 -0700 Received: from vlsi.com (witsend.tempe.vlsi.com [134.27.133.12]) by tem-pbx1.tempe.vlsi.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.1960.3) id HGKMTS1Y; Wed, 13 May 1998 07:41:50 -0700 Sender: dsession@vlsi.com Message-ID: <3559B0FD.47C81480@vlsi.com> Date: Wed, 13 May 1998 07:41:02 -0700 From: "D. C. Sessions" Reply-To: "'IBIS_USER'" , "'SI_LIST'" Organization: VLSI Technology Inc. X-Mailer: Mozilla 4.05 [en] (X11; U; SunOS 5.5.1 sun4m) MIME-Version: 1.0 To: "'IBIS_USER'" , "'SI_LIST'" Subject: Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Jean-Claude Perrin wrote: [wrt: IBIS v/t curves modelling crowbar current in CMOS] > This is not really true. The V/T curve in the IBIS model definition does not > give any information about the PMO/CMOS overlapped current. > The V/T describes the behavior of the buffer output versus frequency but does > not give any information on the current passing internaly through the output > transistors. > To know the value of the through current it is necessary to know the "Ron" > variation of the two transistors during the transition periode. The value of > this current depends upon the equivalent impedance of the two transistors, > impedance which is connected between Vdd and Vss power supply. The IBIS v/t curves (four, note: one each with the load to power and one with the load to ground for both rising and falling edges) give the full picture. The turnon of the pullup device is given by the rising edge/grounded load curve; the turnoff of the pullup is given by the falling edge/grounded load curve. The turnon of the pulldown device is given by the rising edge/pullup load curve; the turnoff of the pulldown is given by the falling edge/pullup load curve. Crowbar current on the rising edge is just the overlap between the pullup turnon and pulldown turnoff, and on the falling edge between the pulldown turnon and pullup turnoff. Also, the crowbar current in CMOS outputs (esp. tristate ones, and for practical purposes that means all of them) is very low by design. At least the ones I design are, and I have yet to see any others that act differently. Unlike internal gates output drivers have separate paths for turning on the pullup, turning off the pulldown, turning on the pulldown, and turning off the pulldown. As a result it's easy to turn the driver devices OFF faster than ON, and since crowbar current not only wastes power but slows down the buffer I have a hard time imagining a competent designer shipping a driver that has more than trivial crowbar current. -- D. C. Sessions dc.sessions@tempe.vlsi.com From owner-ibis Wed May 13 11:05:30 1998 Received: from InterJet.apsimtech.com (apsimtech.com [209.21.21.35]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id LAA28250 for ; Wed, 13 May 1998 11:05:27 -0700 (PDT) Received: (from daemon@localhost) by InterJet.apsimtech.com (8.8.5/8.8.5) id KAA17458 for ; Wed, 13 May 1998 10:04:59 -0700 (PDT) Received: from UNKNOWN(), claiming to be "contec12" via SMTP by InterJet.apsimtech.com, id smtpd017455; Wed May 13 10:04:50 1998 Sender: fred@apsimtech.com Message-ID: <3559D300.784F@apsimtech.com> Date: Wed, 13 May 1998 10:06:08 -0700 From: Fred Balistreri Organization: Apsim X-Mailer: Mozilla 3.01 (X11; I; SunOS 5.3 sun4c) MIME-Version: 1.0 To: "\"'IBIS_USER'\" , \"'SI_LIST'\"" Subject: Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? References: <3559B0FD.47C81480@vlsi.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit D. C. Sessions wrote: > > Jean-Claude Perrin wrote: > > [wrt: IBIS v/t curves modelling crowbar current in CMOS] > > > This is not really true. The V/T curve in the IBIS model definition does not > > give any information about the PMO/CMOS overlapped current. > > The V/T describes the behavior of the buffer output versus frequency but does > > not give any information on the current passing internaly through the output > > transistors. > > To know the value of the through current it is necessary to know the "Ron" > > variation of the two transistors during the transition periode. The value of > > this current depends upon the equivalent impedance of the two transistors, > > impedance which is connected between Vdd and Vss power supply. > > The IBIS v/t curves (four, note: one each with the load to power > and one with the load to ground for both rising and falling edges) > give the full picture. The turnon of the pullup device is given > by the rising edge/grounded load curve; the turnoff of the pullup > is given by the falling edge/grounded load curve. The turnon of > the pulldown device is given by the rising edge/pullup load curve; > the turnoff of the pulldown is given by the falling edge/pullup > load curve. Crowbar current on the rising edge is just the > overlap between the pullup turnon and pulldown turnoff, and on > the falling edge between the pulldown turnon and pullup turnoff. > > Also, the crowbar current in CMOS outputs (esp. tristate ones, and for > practical purposes that means all of them) is very low by design. At > least the ones I design are, and I have yet to see any others that act > differently. Unlike internal gates output drivers have separate paths > for turning on the pullup, turning off the pulldown, turning on the > pulldown, and turning off the pulldown. As a result it's easy to turn > the driver devices OFF faster than ON, and since crowbar current not > only wastes power but slows down the buffer I have a hard time imagining > a competent designer shipping a driver that has more than trivial > crowbar current. > > -- > D. C. Sessions > dc.sessions@tempe.vlsi.com Excuse my ignorance D.C. but I thought the V/T curves are a function of voltage vs time during the respective tr/tf periods. By itself this represents a behavior for the given load and the given load only. In the past the V/T curves were used by the simulation vendors as a means to coorelate the data. In other words one could look at the v/t data and make it match IBIS under that load. Now enter 4 v/t curves. We can use the data to test and make that match IBIS. But now the final output wrt v/t will depend on the vendors interpretation, algorithms, topology, and the phase of the moon. There seems to be a lot of decisions that need to be made left up for grabs. Although my company attends the IBIS meetings I do not. Is there talk of publishing final V/T curves for say a resistively unloaded device for example. This would serve as a means of coorelation for the vendors sake. One problem I see is that the v/t information by itself does not contain the current information. That's buried in the I/V information. In fact we can only get the answer for the given loads not dynamically. Your presumption seems to be based on pullup/pulldown simple topologies. In fact I can tell you we are dealing with very complex I/O stages with feed backs, multiple current switching techniques, and the like. I don't see such a simple solution to this problem. Real devices seem to be much more complex and dynamic than IBIS can support. I am encouraged after reading 3.1 spec and the formation of an independent IBIS users group though. Best Regards, -- Fred Balistreri fred@apsimtech.com http://www.apsimtech.com From owner-ibis Wed May 13 15:18:58 1998 Received: from relayhost.vlsi.com (relayhost.vlsi.com [134.27.20.23]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id PAA01614 for ; Wed, 13 May 1998 15:18:57 -0700 (PDT) Received: (from nobody@localhost) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) id PAA05100; Wed, 13 May 1998 15:15:11 -0700 Received: from unknown(134.27.128.26) by osiris via smap (V2.0) id xma005067; Wed, 13 May 98 15:14:44 -0700 Received: from vlsi.com (witsend.tempe.vlsi.com [134.27.133.12]) by tem-pbx1.tempe.vlsi.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.1960.3) id HGKMTSNH; Wed, 13 May 1998 15:13:57 -0700 Sender: dsession@vlsi.com Message-ID: <355A1AF3.8FD2C1DA@vlsi.com> Date: Wed, 13 May 1998 15:13:07 -0700 From: "D. C. Sessions" Reply-To: ibis-users@vhdl.org, SI-List Organization: VLSI Technology Inc. X-Mailer: Mozilla 4.05 [en] (X11; U; SunOS 5.5.1 sun4m) MIME-Version: 1.0 To: ibis-users@eda.org, SI-List Subject: Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? References: <3559B0FD.47C81480@vlsi.com> <3559D300.784F@apsimtech.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Fred Balistreri wrote: > D. C. Sessions wrote: > > Jean-Claude Perrin wrote: > > [wrt: IBIS v/t curves modelling crowbar current in CMOS] > > > > > This is not really true. The V/T curve in the IBIS model definition does not > > > give any information about the PMO/CMOS overlapped current. > > > The V/T describes the behavior of the buffer output versus frequency but does > > > not give any information on the current passing internaly through the output > > > transistors. > > > To know the value of the through current it is necessary to know the "Ron" > > > variation of the two transistors during the transition periode. The value of > > > this current depends upon the equivalent impedance of the two transistors, > > > impedance which is connected between Vdd and Vss power supply. > > > > The IBIS v/t curves (four, note: one each with the load to power > > and one with the load to ground for both rising and falling edges) > > give the full picture. The turnon of the pullup device is given > > by the rising edge/grounded load curve; the turnoff of the pullup > > is given by the falling edge/grounded load curve. The turnon of > > the pulldown device is given by the rising edge/pullup load curve; > > the turnoff of the pulldown is given by the falling edge/pullup > > load curve. Crowbar current on the rising edge is just the > > overlap between the pullup turnon and pulldown turnoff, and on > > the falling edge between the pulldown turnon and pullup turnoff. > > > > Also, the crowbar current in CMOS outputs (esp. tristate ones, and for > > practical purposes that means all of them) is very low by design. At > > least the ones I design are, and I have yet to see any others that act > > differently. Unlike internal gates output drivers have separate paths > > for turning on the pullup, turning off the pulldown, turning on the > > pulldown, and turning off the pulldown. As a result it's easy to turn > > the driver devices OFF faster than ON, and since crowbar current not > > only wastes power but slows down the buffer I have a hard time imagining > > a competent designer shipping a driver that has more than trivial > > crowbar current. > Excuse my ignorance D.C. but I thought the V/T curves are a function of > voltage vs time during the respective tr/tf periods. Voltage vs. time *into a load*, and the timescales are supposed to match up. > By itself this > represents a behavior for the given load and the given load only. In the > past the V/T curves were used by the simulation vendors as a means to > coorelate the data. In other words one could look at the v/t data and > make it match IBIS under that load. Now enter 4 v/t curves. We can use > the data to test and make that match IBIS. But now the final output wrt > v/t will depend on the vendors interpretation, algorithms, topology, > and the phase of the moon. There seems to be a lot of decisions that > need to be made left up for grabs. Although my company attends the > IBIS meetings I do not. Is there talk of publishing final V/T curves > for say a resistively unloaded device for example. This would serve as > a means of coorelation for the vendors sake. One reason for loading the driver during derivation of v/t curves is that outputs typically go through a very high-impedance state when both devices are OFF. In this time other signal sources such as gate coupling can have a large effect on the output voltage despite the fact that the signal source doesn't have the v/i characteristics of the IBIS driver. Without going into the other uses of the v/t curves, they *can* be used to answer the present question, PROVIDED that the test load is heavy enough to be meaningful (A 10Kohm load isn't going to tell us much about the characteristics of a driver with an Rdson of twelve ohms.) The reason that this is so straightforward is that the crowbar current only flows for a brief time when both devices are nearly OFF anyway, so they are in deep saturation and thus the drain currents are pretty much independent of voltage. > One problem I see is that the v/t information by itself does not contain > the current information. Sure they do, it's just Ohm's Law: Id = Vout/Rload > That's buried in the I/V information. In fact > we can only get the answer for the given loads not dynamically. Without feedback, Norton models seem to work pretty well. > Your > presumption seems to be based on pullup/pulldown simple topologies. In > fact I can tell you we are dealing with very complex I/O stages with > feed backs, Eeeeyeew! Feedback! Feedback is evil. Bad driver, BAD. Go to bed without stability. Naughty, naughty, naughty. Well, OK, that's overstating it. Sometimes feedback is not only useful but necessary; it still makes behavioral modelling (a la IBIS) pretty well impossible. IMNSHO, this is more annoying than crippling since feedback has other properties that limit its usefulness in applications where signal integrity is a major concern, so giving up behavioral modelling of feedback-controlled drivers is (again, IMO) no great loss. > multiple current switching techniques, and the like. I don't > see such a simple solution to this problem. Real devices seem to be much > more complex and dynamic than IBIS can support. Well, that's certainly true -- for instance, IBIS can't really deal with JEDEC flexible-impedance drivers, and I'm writing THOSE into the IEEE 1394b spec. Great fun. Still, we need to keep in mind that the more exotic variants that you and I deal with are of very narrow application. Most people don't encounter anything but the vanilla CMOS device, and for *that* the simple v/t analysis I presented is quite adequate. Actually, even for the exotica you mentioned it will give a pretty good idea of the crowbar current. Oddly enough, the flex-z stuff is one of the ONLY cases it won't do well. -- D. C. Sessions dc.sessions@tempe.vlsi.com From owner-ibis Wed May 13 20:55:06 1998 Received: from relay6.UU.NET (relay6.UU.NET [192.48.96.16]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id UAA06315 for ; Wed, 13 May 1998 20:55:05 -0700 (PDT) Received: from uucp2.uu.net by relay6.UU.NET with SMTP (peer crosschecked as: uucp2.uu.net [192.48.96.82]) id QQepgx05513; Wed, 13 May 1998 23:51:49 -0400 (EDT) Received: from qdt.UUCP by uucp2.uu.net with UUCP/RMAIL ; Wed, 13 May 1998 23:51:50 -0400 Received: from viewlogic.com by qdt.viewlogic.com (4.1/SMI-4.1) id AA13947; Wed, 13 May 98 20:48:05 PDT Received: from f14 by qdt.com (4.1/SMI-4.1) id AA29826; Wed, 13 May 98 20:45:22 PDT Sender: crokusek@qdt.com Message-Id: <355A6777.42877E5C@viewlogic.com> Date: Wed, 13 May 1998 20:39:35 -0700 From: Chris Rokusek Organization: Viewlogic Systems X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m) Mime-Version: 1.0 To: ibis-users@eda.org, si-list@silab.Eng.Sun.COM Subject: Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on? References: <3559B0FD.47C81480@vlsi.com> <3559D300.784F@apsimtech.com> <355A1AF3.8FD2C1DA@vlsi.com> <355A35EB.181E@apsimtech.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Okay, can't resist here's my two cents... Fred Balistreri wrote: > Id is not crowbar. So you still have to go back to the I/V data and dig > it out as I already mentioned. V/t curves were originally intended to > model the ac or switching characteristics which IBIS was (is?) lacking. > Sure the information is there so is ground bounce to some degree. > Remember the 4 v/t curve information only got added recently, but the > single v/t curve has been in IBIS for quite some time. Chances are the > users haven't seen a 4 v/t model yet. Since IBIS V2.1 (circa 1995) there has been a limit of 100 waveform tables per model allowing many "arbitrary" loading conditions. One of the reasons multiple waveforms were allowed right from the start was to support a mechanism for estimating VCC, GND & the dreaded Crowbar currents. I've seen many 4 v/t models for quite a while but I also still see many 1 v/t models or multiple X v/t waveforms to useless loads. *** *** MODEL BUILDERS PLEASE READ ON... *** More recently an IBIS model building cookbook that details recommended loading conditions was posted for public download: http://www.eia.org/eig/ibis/tools.htm Click "IBIS Cookbook for V2.1 (Oct 13th '97)" Best Regards, Chris Rokusek Viewlogic Systems From owner-ibis Sun May 17 18:22:43 1998 Received: from TYO2.gate.nec.co.jp (TYO2.gate.nec.co.jp [203.180.98.33]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id SAA05496 for ; Sun, 17 May 1998 18:22:33 -0700 (PDT) From: shigeto@saed.tmg.nec.co.jp Received: from mailsv.nec.co.jp ([192.168.1.90]) by TYO2.gate.nec.co.jp (8.8.8+2.7Wbeta7/3.6Wbeta698051415) with ESMTP id KAA09334 for ; Mon, 18 May 1998 10:18:30 +0900 (JST) Received: from ktcgw6.saed.tmg.nec.co.jp ([133.202.42.18]) by mailsv.nec.co.jp (8.8.8+2.7Wbeta7/3.6Wbeta6-98051411) with ESMTP id KAA08692 for ; Mon, 18 May 1998 10:18:29 +0900 (JST) Received: from ktcgw2.saed.tmg.nec.co.jp (sajpc89.saed.tmg.nec.co.jp [133.202.148.249]) by ktcgw6.saed.tmg.nec.co.jp (8.8.7+2.7Wbeta7/3.5Wpl4-08/06/97) with SMTP id KAA17195 for ; Mon, 18 May 1998 10:11:40 +0900 (JST) Message-Id: <199805180111.KAA17195@ktcgw6.saed.tmg.nec.co.jp> To: ibis-users@eda.org Subject: About ibischk2+ Reply-To: shigeto@saed.tmg.nec.co.jp Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-2022-JP Content-Transfer-Encoding: 7bit Date: Mon, 18 May 1998 10:21:26 +0900 X-Mailer: WeMail32[1.41] ID:1E0011 Dear All, I checked IBIS models by ibischk2+. I have two questions. Could you support me ? 1) Dose ibischk2+ make errors when IV table is non-monotonic? 2) Why dose not ibischk2+ use "R_dut" value? ---- Example of "1)" --------------------------------------------------------- WARNING (line 47) - Pulldown Typical data is non-monotonic WARNING (line 49) - Pulldown Maximum data is non-monotonic <- WARNING (line 143) - Pullup Maximum data is non-monotonic WARNING (line 183) - Pullup Minimum data is non-monotonic WARNING (line 185) - Pullup Typical data is non-monotonic WARNING - Model 'Buffer1': TYP AC Falling Endpoints ( 0.87V, 3.30V) not within 0.049V (2%) of ( 0.77V, 3.30V) on VI curves for 50 Ohms to 3.3V WARNING - Model 'Buffer1': MIN AC Falling Endpoints ( 0.93V, 3.28V) not within 0.047V (2%) of ( 0.84V, 3.29V) on VI curves for 50 Ohms to 3.3V WARNING - Model 'Buffer1': MAX AC Rising Endpoints (-0.00V, 1.85V) not within 0.037V (2%) of (-13.50V, 1.87V) on VI curves for 50 Ohms to 0V ??????? WARNING - Model 'Buffer1': MAX AC Falling Endpoints ( 0.81V, 3.30V) not within 0.050V (2%) of (-15.70V, 3.30V) on VI curves for 50 Ohms to 3.3V ??????? Errors : 0 Warnings: 9 ---------------------------------------------------------------------------------- Pulldown Maximum data corrected. WARNING (line 47) - Pulldown Typical data is non-monotonic WARNING (line 143) - Pullup Maximum data is non-monotonic WARNING (line 183) - Pullup Minimum data is non-monotonic WARNING (line 185) - Pullup Typical data is non-monotonic WARNING - Model 'Buffer1': TYP AC Falling Endpoints ( 0.87V, 3.30V) not within 0.049V (2%) of ( 0.77V, 3.30V) on VI curves for 50 Ohms to 3.3V WARNING - Model 'Buffer1': MIN AC Falling Endpoints ( 0.93V, 3.28V) not within 0.047V (2%) of ( 0.84V, 3.29V) on VI curves for 50 Ohms to 3.3V WARNING - Model 'Buffer1': MAX AC Falling Endpoints ( 0.81V, 3.30V) not within 0.050V (2%) of ( 0.70V, 3.30V) on VI curves for 50 Ohms to 3.3V ^^^^^ Errors : 0 Warnings: 7 -------------------------------------------------------------------------------- Best regards. Shigeto Nakajima NEC Corpration shigeto@saed.tmg.nec.co.jp From owner-ibis Mon May 18 17:06:50 1998 Received: from ganymede.or.intel.com (ganymede.or.intel.com [134.134.248.3]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id RAA09924 for ; Mon, 18 May 1998 17:06:49 -0700 (PDT) Received: from ichips-jf.jf.intel.com (ichips-jf.jf.intel.com [134.134.50.200]) by ganymede.or.intel.com (8.8.6/8.8.5) with ESMTP id RAA29191; Mon, 18 May 1998 17:19:26 -0700 (PDT) Received: from xtg801 (xtg801.pdx.intel.com [134.134.120.169]) by ichips-jf.jf.intel.com (8.8.8/8.8.7) with ESMTP id RAA04499; Mon, 18 May 1998 17:03:30 -0700 (PDT) Received: from ichips.intel.com by xtg801 (8.8.8/WW2.1 (Jones Farm)) id RAA20753; Mon, 18 May 1998 17:03:29 -0700 (PDT) Message-Id: <199805190003.RAA20753@xtg801> X-Mailer: exmh version 2.0delta 6/3/97 To: shigeto@saed.tmg.nec.co.jp cc: ibis-users@eda.org Subject: Re: About ibischk2+ In-reply-to: Your message of "Mon, 18 May 1998 10:21:26 +0900." <199805180111.KAA17195@ktcgw6.saed.tmg.nec.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Mon, 18 May 1998 17:03:29 -0700 From: Stephen Peters Hello Nakajima-san: My answers are below. I hope this helps. Best Regards, Stephen Peters Intel Corp. > Dear All, > > I checked IBIS models by ibischk2+. > I have two questions. > Could you support me ? > > 1) Dose ibischk2+ make errors when IV table is non-monotonic? The ibischk2+ program checks for non-monotonic data because many simulators will not accept non-monotonic I/V data. Please note however these are warnings, not errors. Also be aware that the non-monotonic data may be in the result of subtracting the power/gnd clamp current from the pullup and pulldown currents, and that once the two curves are summed together (as the simulator will do) the data may be monotonic. I notice that there are also warning that indicate that the V/T curves in your model do not settle to within 2% of the final DC value predicted by the I/V curves. This may require some investigation. > 2) Why dose not ibischk2+ use "R_dut" value? The R_dut value represents part of the test load used when extracting the V/T curves. It is included to document the test/extraction conditions. > > ---- Example of "1)" --------------------------------------------------------- > WARNING (line 47) - Pulldown Typical data is non-monotonic > WARNING (line 49) - Pulldown Maximum data is non-monotonic <- > WARNING (line 143) - Pullup Maximum data is non-monotonic > WARNING (line 183) - Pullup Minimum data is non-monotonic > WARNING (line 185) - Pullup Typical data is non-monotonic > WARNING - Model 'Buffer1': TYP AC Falling Endpoints ( 0.87V, 3.30V) not within > 0.049V (2%) of ( 0.77V, 3.30V) on VI curves for 50 Ohms to 3.3V > WARNING - Model 'Buffer1': MIN AC Falling Endpoints ( 0.93V, 3.28V) not within > 0.047V (2%) of ( 0.84V, 3.29V) on VI curves for 50 Ohms to 3.3V > WARNING - Model 'Buffer1': MAX AC Rising Endpoints (-0.00V, 1.85V) not within > 0.037V (2%) of (-13.50V, 1.87V) on VI curves for 50 Ohms to 0V > ??????? > WARNING - Model 'Buffer1': MAX AC Falling Endpoints ( 0.81V, 3.30V) not within > 0.050V (2%) of (-15.70V, 3.30V) on VI curves for 50 Ohms to 3.3V > ??????? > Errors : 0 > Warnings: 9 > ---------------------------------------------------------------------------------- > > Pulldown Maximum data corrected. > > WARNING (line 47) - Pulldown Typical data is non-monotonic > WARNING (line 143) - Pullup Maximum data is non-monotonic > WARNING (line 183) - Pullup Minimum data is non-monotonic > WARNING (line 185) - Pullup Typical data is non-monotonic > WARNING - Model 'Buffer1': TYP AC Falling Endpoints ( 0.87V, 3.30V) not within > 0.049V (2%) of ( 0.77V, 3.30V) on VI curves for 50 Ohms to 3.3V > WARNING - Model 'Buffer1': MIN AC Falling Endpoints ( 0.93V, 3.28V) not within > 0.047V (2%) of ( 0.84V, 3.29V) on VI curves for 50 Ohms to 3.3V > WARNING - Model 'Buffer1': MAX AC Falling Endpoints ( 0.81V, 3.30V) not within > 0.050V (2%) of ( 0.70V, 3.30V) on VI curves for 50 Ohms to 3.3V > ^^^^^ > Errors : 0 > Warnings: 7 > -------------------------------------------------------------------------------- > > Best regards. > > Shigeto Nakajima > NEC Corpration > > shigeto@saed.tmg.nec.co.jp From owner-ibis Tue May 19 16:54:42 1998 Received: from relay5.UU.NET (relay5.UU.NET [192.48.96.15]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA03021; Tue, 19 May 1998 16:54:41 -0700 (PDT) Received: from uucp2.uu.net by relay5.UU.NET with SMTP (peer crosschecked as: uucp2.uu.net [192.48.96.82]) id QQeqcl03627; Tue, 19 May 1998 19:51:21 -0400 (EDT) Received: from qdt.UUCP by uucp2.uu.net with UUCP/RMAIL ; Tue, 19 May 1998 19:51:23 -0400 Received: from viewlogic.com by qdt.viewlogic.com (4.1/SMI-4.1) id AA14360; Tue, 19 May 98 16:53:05 PDT Received: from f14 by qdt.com (4.1/SMI-4.1) id AA25635; Tue, 19 May 98 16:51:28 PDT Sender: crokusek@qdt.com Message-Id: <3562199B.13728473@viewlogic.com> Date: Tue, 19 May 1998 16:45:31 -0700 From: Chris Rokusek Organization: Viewlogic Systems X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m) Mime-Version: 1.0 To: ibis@eda.org, ibis-users@eda.org Subject: Call for V3.0 Models References: <9805020022.AA12632@bob> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi All, I would like to request any models with V3.0 features to test against the checker and our translator. An NDA agreement is not a problem if it is neccessary. If you have V3.0 models but are unable to give them out I am still interested in the knowing which features you are using from V3.0. If others are interested in obtaining V3.0 models please respond to me or post to the list and I can add your name to a distribution list (assuming I actually get some replies from this email). Best Regards, Chris Rokusek Viewlogic Systems (805) 988-8250 (805) 988-8259 fax From owner-ibis Wed May 20 16:22:50 1998 Received: from ganymede.or.intel.com (ganymede.or.intel.com [134.134.248.3]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id QAA25430; Wed, 20 May 1998 16:22:50 -0700 (PDT) Received: from ichips-jf.jf.intel.com (ichips-jf.jf.intel.com [134.134.50.200]) by ganymede.or.intel.com (8.8.6/8.8.5) with ESMTP id QAA27899; Wed, 20 May 1998 16:30:58 -0700 (PDT) Received: from xtg801 (xtg801.pdx.intel.com [134.134.120.169]) by ichips-jf.jf.intel.com (8.8.8/8.8.7) with ESMTP id QAA12864; Wed, 20 May 1998 16:19:34 -0700 (PDT) Received: from ichips.intel.com by xtg801 (8.8.8/WW2.1 (Jones Farm)) id QAA05915; Wed, 20 May 1998 16:19:33 -0700 (PDT) Message-Id: <199805202319.QAA05915@xtg801> X-Mailer: exmh version 2.0delta 6/3/97 To: ibis@eda.org, ibis-users@eda.org Subject: EIA/IBIS Summit Meeting -- Call For Presentations Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Wed, 20 May 1998 16:19:32 -0700 From: Stephen Peters D A C I B I S S U M M I T M E E T I N G DATE: Thursday, June 18, 1998 TIME: 9 AM - Afternoon LOCATION: San Francisco Marriott Hotel, next to Moscone Center where the Design Automation Conference (DAC) is being held ROOM: Pacific 4-1 LUNCH: Refreshments and Lunch will be provided. AGENDA: The main focus is to continue face-to-face technical discussions on IBIS Version 3.1 ratification issues. We may ratify IBIS Version 3.1 at this time. Also, we will be electing EIA IBIS Open Forum Officers for 1997-1998. The formal agenda will be developed and published before the meeting. CALL FOR PRESENTATIONS: We are open for presentations on any subject and may solicit a few presentations. We are also open to technical presentations related to the recent BIRDs and IBIS Version 3.0 features. Contact Stephen Peters regarding your presentation: Presenter: Title: Estimated Time: We would like you to provide handouts for the meeting (about 25) and also have an electronic copy. CALL FOR ATTENDEES: Please let Stephen Peters know if you are planning to attend so we have an estimate on food requirements. CONTACT: Stephen Peters sjpeters@ichips.intel.com ------- End of Forwarded Message From owner-ibis Mon May 25 04:29:55 1998 Received: from mailgate.cadence.com (mailgate.Cadence.COM [158.140.2.1]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id EAA10619 for ; Mon, 25 May 1998 04:29:54 -0700 (PDT) Received: (from smap@localhost) by mailgate.cadence.com (8.8.5/8.6.8) id EAA18222 for ; Mon, 25 May 1998 04:26:33 -0700 (PDT) Received: from corona.cadence.com(158.140.127.12) by mailgate.cadence.com via smap (mjr-v1.2) id xma896095591.018219; Mon, 25 May 98 04:26:31 -0700 Received: (from ads@localhost) by corona.cadence.com (8.8.5/8.8.5) id QAA17032 for ibis-users@vhdl.org; Mon, 25 May 1998 16:57:08 +0531 (IST) Date: Mon, 25 May 1998 16:57:08 +0531 (IST) From: "A. D. Shirpadaraj" Message-Id: <199805251126.QAA17032@corona.cadence.com> To: ibis-users@vhdl.org Subject: IBIS 3.0: Series MOSFET under off condition X-Sun-Charset: US-ASCII Hi Guys, How to get V-I Table for Series MOSFET switch under OFF condition. Is it just keeping Vds at 0(or less than cutin)volt and measuring Ids? It means modelling for only leakage current. Am I right? IBIS 3.0 spec doesnot explain off state situation. Regards Shripad Cadence Design Systems (India0 Ltd., NOIDA, India From owner-ibis Tue May 26 14:56:25 1998 Received: from wile.nesa.com ([204.240.29.30]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id OAA16267 for ; Tue, 26 May 1998 14:56:23 -0700 (PDT) Received: (from mail@localhost) by wile.nesa.com (8.8.5/8.8.5) id RAA31793; Tue, 26 May 1998 17:19:43 -0400 Received: from porky.nesa.com(204.240.29.45) by wile.nesa.com via smap (V1.3) id sma031791; Tue May 26 17:19:34 1998 Message-Id: <3.0.3.32.19980526171941.00b92c10@mail.nesa.com> X-Sender: breda@mail.nesa.com X-Mailer: QUALCOMM Windows Eudora Pro Version 3.0.3 (32) Date: Tue, 26 May 1998 17:19:41 -0400 To: ibis-users@eda.org From: Kathy Breda Subject: IBIS User Group Meeting Reminder - Thurs. 5/28 @ 3:00pm Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" IBIS Users Group Members: ***MEETING REMINDER*** MEETING DETAIL: DATE: Thursday, May 28, 1998 TIME: 3:00 PM LOCATION: Stratus, Marlboro MA Customer Conference Room 7, Visitor Center (The Visitor Center is located right by the main lobby) If you would let me know that you're attending we can send the list ahead to Stratus to avoid delays in signing in at their security desk. PROPOSED AGENDA: (always looking for input) * IBIS education topic - Review to revise committee and program * Update on Connector Modeling BIRD * Accuracy Specification and Test Board Update * More on IBIS education curriculum MAP and DIRECTIONS to STRATUS: A map and directions can be found: http://www.stratus.com/int/locations/home.html Directions: >From I-495 Take Exit 25A "To 85 / Marlboro". Travel on this road about 2 miles toward Route 85 and go to the second traffic light. Turn right on Route 85, at the 99 Restaurant. Follow 85 South just over 1 mile to the second traffic light, and turn right onto Hudson Street. (Look for a big sign for Golf Driving Range). Continue straight up the hill toward the large Stratus sign. Take the first right and follow the signs to Visitor Parking. There you will find the Main Lobby. Please check in here. 4 exit 25a | 9----------------------+- 5 | Route 8 X-+ 5 South Stratus \ | Building \ | ---Hudson St-+ | From owner-ibis Wed May 27 11:15:37 1998 Received: from newsgw.mentorg.com (newsgw.mentorg.com [192.94.38.66]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id LAA07649 for ; Wed, 27 May 1998 11:15:37 -0700 (PDT) Received: from emicx.wv.mentorg.com by newsgw.mentorg.com (8.8.8/CF5.40F) id LAA10759; Wed, 27 May 1998 11:11:45 -0700 (PDT) Received: from bob by emicx.wv.mentorg.com (8.7.5/CF5.38R) id LAA17087; Wed, 27 May 1998 11:11:42 -0700 (PDT) From: bobr@emicx.mentorg.com (Bob Ross) Received: by bob (4.1/CF5.23L) id AA00228; Wed, 27 May 98 11:11:43 PDT Date: Wed, 27 May 98 11:11:43 PDT Message-Id: <9805271811.AA00228@bob> To: ads@cadence.com, ibis-users@eda.org Subject: Re: IBIS 3.0: Series MOSFET under off condition Shripad: Because the Off state should be mostly very low leakage current, I would not use the V-I table. I would approximate the off state with a large [R Series] value. Best Regards, Bob Ross Interconnectix/Mentor Graphics > Date: Mon, 25 May 1998 16:57:08 +0531 (IST) > From: "A. D. Shirpadaraj" > Message-Id: <199805251126.QAA17032@corona.cadence.com> > To: ibis-users@vhdl.org > Subject: IBIS 3.0: Series MOSFET under off condition > Hi Guys, > How to get V-I Table for Series MOSFET switch under OFF condition. > Is it just keeping Vds at 0(or less than cutin)volt and measuring Ids? > It means modelling for only leakage current. Am I right? > IBIS 3.0 spec doesnot explain off state situation. > Regards > Shripad > Cadence Design Systems (India0 Ltd., > NOIDA, > India