From owner-ibis  Thu Apr  1 18:08:10 1999
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From: "Montoya, Silvia" <Silvia.Montoya@actel.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Cc: "Montoya, Silvia" <Silvia.Montoya@actel.com>
Subject: ibschk2  Errors and Warnings
Date: Thu, 1 Apr 1999 18:02:15 -0800 
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Hi All,

    Is there a document which gives more detailed explanations of  'ibschk2'
error and warning messages ?
 
  Thanks,
        Silvia Montoya
        Actel Corporation
    
From owner-ibis  Mon Apr  5 12:42:14 1999
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Date: Mon, 5 Apr 1999 12:36:15 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: s2ibis3 for IBISv3.2
To: ibis-users@vhdl.org
Cc: shuq@cisco.com
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IBISfans:

I was in a discussion with a model developer and this question that has been 
on your mind for a while has come up again.

A majority of all models generated today use s2ibis2(from NCSU). IBIS has moved
onto ver3.2 and most of the data for the new features can only be generated
thru a SPICE conversion.

So, will the IBIS forum or the east coast users group come up with a funding
plan to generate a s2ibis3(for ver3.2) ?

The new ver3.2 is great but model providers need tools to generate such
models too. 

Regards,
Syed
Cisco Systems, Inc

From owner-ibis  Tue Apr  6 13:05:50 1999
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Date: Tue, 06 Apr 1999 16:00:11 -0400
From: "DORIN OPREA" <doprea@newbridge.com>
Organization: Newbridge Networks Corporation
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To: ibis-users@eda.org
Subject: SERIES MOSFET
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Hi,

I try to convert the IDT74FST163233 IBIS model into XTK (Viewlogic)
model. The IBIS file is for a multiplexer and has 7 VI tables for Vds =
0, 1, 2 ... 6. XTK supports only one table.
I don't understand what Vds means and what Vds = 0 through 6 represent.
In the IBIS documentation is mentioned that Vds must be > 0, so is the
model wrong ?
What would be the best value for Vds to take, since XTK allows only one
table.
I would appreciate any help.

Thanks,


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org:            Newbridge Networks Corporation
adr:            600 March Road;;;Kanata;Ontario;K2K 2E6;Canada
email;internet: doprea@newbridge.com
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From owner-ibis  Tue Apr  6 14:18:12 1999
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Date: Tue, 06 Apr 1999 14:09:47 -0700
To: "DORIN OPREA" <doprea@newbridge.com>, ibis-users@eda.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Re: SERIES MOSFET
In-Reply-To: <370A67CA.DD620EDC@newbridge.com>
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This sounds like a problem for you simulator vendor...

At 04:00 PM 4/6/99 -0400, DORIN OPREA wrote:
>Hi,
>
>I try to convert the IDT74FST163233 IBIS model into XTK (Viewlogic)
>model. The IBIS file is for a multiplexer and has 7 VI tables for Vds =
>0, 1, 2 ... 6. XTK supports only one table.
>I don't understand what Vds means and what Vds = 0 through 6 represent.
>In the IBIS documentation is mentioned that Vds must be > 0, so is the
>model wrong ?
>What would be the best value for Vds to take, since XTK allows only one
>table.
>I would appreciate any help.
>
>Thanks,
>
>
> 
From owner-ibis  Tue Apr  6 14:48:46 1999
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From owner-ibis  Wed Apr  7 01:30:03 1999
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-- 

                                    \\\|///
                                   0|-O-O-|0
( * )-------------------------ooO---| ( ) |---Ooo-------------------------( * )
 |*|                                   |      	                           |*|
 |*|  Mohamed A. Nasef                 |  Tel : (202)  414 13 06  (x.140)  |*|
 |*|  Development Engineer             |  Fax : (202)  418 69 45           |*|
 |*|  ICX Modeling Group               |  GSM : (2010) 140 47 06           |*|
 |*|  Mentor Graphics Egypt            |  53 Beirut St., Heliopolis,       |*|
 |*|  E-mail: Mohamed_Nasef@mentor.com |  Cairo 11341, Egypt.              |*|
 |*|                                   |                                   |*|
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From owner-ibis  Wed Apr  7 10:09:06 1999
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From: guy@camarillo.viewlogic.com
Message-Id: <199904071638.JAA28656@camarillo.viewlogic.com>
To: doprea@newbridge.com, ibis-users@eda.org
Subject: SERIES MOSFET

						7 April 1999

> I try to convert the IDT74FST163233 IBIS model into XTK (Viewlogic)
> model. The IBIS file is for a multiplexer and has 7 VI tables for Vds =
> 0, 1, 2 ... 6. XTK supports only one table.
> I don't understand what Vds means and what Vds = 0 through 6 represent.
> In the IBIS documentation is mentioned that Vds must be > 0, so is the
> model wrong ?
> What would be the best value for Vds to take, since XTK allows only one
> table.
> I would appreciate any help.

This is what I understand Vds to mean:

 
                        ----- Ids ---->
                            + Vds -
 
                      d o---+     +---o s
                            |     |
                            +-----+    -
                             -----   Vgs
                               |     +
                               g



   The IBIS format requires an IV curve of Ids vs. Vgs at a particular Vds.

   E.g. 2 curves shown. One at Vds = 1.7V, the other at Vds = 1.0V.
 
   Ids
   ^
   |
   |              +  Vds = 1.7V
   |             +
   |            +       * Vds = 1.0V
   |           +       *
   |          +       *
   |         +      *
   |        +     *
   |      +    *
   |    +   *
   |  + *
  -+**------------------------------------> Vgs
   |


From your email it would appear that the model has curves for Vds going from
0V to 6V in 1V steps. Does this answer your question?

Also XTK prefers multiple tables because they (multiple tables) mean a more
accurate model (assuming the data is accurate) and therefore a more accurate
XTK simulation.

Guy de Burgh
Viewlogic

From owner-ibis  Thu Apr  8 14:32:51 1999
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From: gedlund@us.ibm.com
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Date: Thu, 8 Apr 1999 16:26:33 -0500
Subject: IBIS Users conference call canceled
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We have decided to cancel tomorrow's IBIS Users conference call.  Several
people were unavailable, and this will give us more time to review 1.2 of
the Accuracy Spec.  We'll tentatively reschedule for 4/30.  Sorry for the
late notice.

Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com


From owner-ibis  Tue Apr 13 10:01:09 1999
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To All:

The official Version 3.2.5 ibischk3 executables are
now available under

  http://www.eda.org/pub/ibis/ibischk3/

(A linux version will be uploaded soon)

The official EIA IBIS Web Site already links to this
directory under the FREE Tools link.

Older ibischk3 executables are temporarily available
under:

  http://www.eda.org/pub/ibis/ibischk3_old/

Thanks to Chris Rokusek for compiling the Unix
executables and Matthew Flora for compiling the
dos32 executable.

Bob Ross
Mentor Graphics
From owner-ibis  Tue Apr 13 21:59:04 1999
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Date: Tue, 13 Apr 1999 21:53:00 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: Official ibischk3 executable - Linux
To: ibis@eda.org, ibis-users@eda.org
Cc: shuq@cisco.com
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To All:

The official version of 3.2.5 ibischk3 executable for Linux can be found
under:

http://www.eda.org/pub/ibis/ibischk3/linux

The parser can also be downloaded from the EIA IBIS Website under 'FREE tools'
(www.eia.org/eig/ibis/ibis.htm)

Regards,
Syed
Cisco Systems, Inc

From owner-ibis  Fri Apr 16 06:26:34 1999
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help


From owner-ibis  Fri Apr 16 08:41:29 1999
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From: "Nelson, Kerry" <kerry.nelson@intel.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>,
        "'ibis@eda.org'"
	 <ibis@eda.org>
Subject: Pentium(R) II, Pentium II Xeon(TM), and Pentium III Xeon IBIS mod
	els on the web
Date: Fri, 16 Apr 1999 08:35:54 -0700
Sensitivity: Company-Confidential
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Hello, fellow IBIS users.

I'm pleased to announce that Intel has placed IBIS models for the Pentium(R)
II, Pentium II Xeon(TM), and Pentium III Xeon products on the Intel
Developer web site:

http://developer.intel.com/
http://developer.intel.com/design/PentiumII/devtools/
http://developer.intel.com/design/pentiumii/xeon/devtools/
http://developer.intel.com/design/pentiumIII/xeon/devtools/

In addition to the buffers, these models use the EBD syntax to describe the
CPU package, cartridge, and connector. All of these models have been
correlated to lab measurements. I believe this announcement will also be
captured in the 4-16-99 Open Forum minutes.

Thanks for reading.

Kerry Nelson
Intel Corp.
Processor Product Development - DuPont, WA
kerry.nelson@intel.com

From owner-ibis  Mon Apr 19 11:26:59 1999
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From: "VENUGOPAL,PRASAD (HP-SanJose,ex1)"
	 <prasad_venugopal@am.exch.hp.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: SSTL-2 and SSTL-3
Date: Mon, 19 Apr 1999 12:15:54 -0600
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Hi, IBIS users.
 Is there a description in IBIS for SSTL-2 and SSTL-3 ?
Thanks
From owner-ibis  Mon Apr 19 13:26:55 1999
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From: "D. C. Sessions" <dc.sessions@vlsi.com>
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"VENUGOPAL,PRASAD (HP-SanJose,ex1)" wrote:
> 
> Hi, IBIS users.
>  Is there a description in IBIS for SSTL-2 and SSTL-3 ?

1) The JEDEC SSTL-2 and SSTL-3 specs in themselves don't contain
   enough information to fill out even a minimal IBIS model.
2) There are, of course, models for individual SSTL parts.
   Your best bet here would be the DDR-SDRAM parts now appearing.
3) JEDEC committees JC-42.3 and JC-16 are working on adding IBIS
   models to the DDR-SDRAM standard.  Work in progress.

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Tue Apr 20 07:02:06 1999
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Date: Tue, 20 Apr 1999 09:55:54 -0400
To: ibis-users@eda.org
From: Todd Westerhoff <toddw@cadence.com>
Subject: Re: Pentium(R) II, Pentium II Xeon(TM), and Pentium III Xeon
  IBIS models on the web
In-Reply-To: <B38DE02578EBD111AC4200A0C95D19EE01C78FF8@orsmsx30.jf.intel
 .com>
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I know this forum isn't for vendor stuff, so I'll keep this to a minimum.


First, thanks to Intel for publicly posting the above models in IBIS format.  This is a great step forward for IBIS, and will make model translation a lot easier.


We are currently testing the posted models for use with the Cadence SPECCTRAQuest 13.5 release.  I won't clutter the forum with Cadence information; however, I thought it would be appropriate to mention that you can email me ...


toddw@cadence.com


... if you'd like to be kept up to date on the latest details of our testing.  I'm developing an "email list" for this information and will try to post information weekly.  If people are interested, we could also set up an email alias as a discussion vehicle for the some of the Cadence-specific issues for these models.


Todd.




<excerpt><bold>

</bold></excerpt>   <bold>Todd Westerhoff

</bold><color><param>0000,0000,ffff</param>   Technical Marketing
Director | High Speed Systems Design | Performance Engineering

</color><color><param>ffff,0000,0000</param>   Cadence Design Systems |
270 Billerica Road | Chelmsford, MA  01824

</color>   

   ph: (978) 262-6327

   fx: (978) 446-6798

   email: toddw@cadence.com

   internal information website: http://www-ma.cadence.com/~toddw
From owner-ibis  Tue Apr 20 12:35:55 1999
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Date: Tue, 20 Apr 1999 12:27:46 -0700
To: :
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: New Intel Pent III models
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Hi all,

  There was no contact email in the new Intel Pent. Models
so I thought perhaps a question here is appropriate.

Anyone know why Intel used 2 separate ibis models for min /max
cases and left the min/max columns blank in each file instead of
doing one file and using the min/max columns as intended.

Kellee


From owner-ibis  Tue Apr 20 23:34:08 1999
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From: jxz <j07378@huawei.com.cn>
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Hi,
    I am a engineer of Huawei company in the city of ShenZhen in China.
    Now I am engaged in PCB signal analysis . I have met many IBIS
models .
    May I ask a question now?  Thank you .
    In IBIS model, there are definition of pullup ,pulldown and other
V/I curves . Other parameters such as C_comp and PKG parameters are also

listed.  So in my idea, if  a driver have these V/I curves and
parameters, when a square wave is input to the driver( it has an a
standard 50 ohm load ),  the output wave should be a trapeziform wave.
From this trapeziform wave , we can measure the tr and tf .
    Now I want to ask that though we can measure the tr and tf from the
output waveform, why should we define the ramp parameter in IBIS model?



From owner-ibis  Wed Apr 21 08:11:54 1999
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From: "D. C. Sessions" <dc.sessions@vlsi.com>
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To: ibis-users@eda.org
CC: jxz <j07378@huawei.com.cn>
Subject: Re: about IBIS model's ramp
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jxz wrote:
> 
> Hi,
>     I am a engineer of Huawei company in the city of ShenZhen in China.
>     Now I am engaged in PCB signal analysis . I have met many IBIS
> models .
>     May I ask a question now?  Thank you .
>     In IBIS model, there are definition of pullup ,pulldown and other
> V/I curves . Other parameters such as C_comp and PKG parameters are also
> 
> listed.  So in my idea, if  a driver have these V/I curves and
> parameters, when a square wave is input to the driver( it has an a
> standard 50 ohm load ),  the output wave should be a trapeziform wave.
> >From this trapeziform wave , we can measure the tr and tf .
>     Now I want to ask that though we can measure the tr and tf from the
> output waveform, why should we define the ramp parameter in IBIS model?

This would be true if the output waveforms were dominated by current
into a capacitive load.  In many signal-integrity applications this
assumption is not valid.

In the simplest case, the output is into a transmission line, which
acts as a real (nonreactive) load at high frequencies.  In that case,
the output waveform is determined by the I/T properties of the driver
which in turn are dictated by the design of the predriver stage.  The
V/I curves don't provide this information.

In more complex cases, the driver is connected to the PWB interconnect
through small inductors such as bond wires.  In that case, the output
waveform is even dependent on the dI/dT of the driver, which is even
farther removed from the V/I curves in an IBIS 1.x model.

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Wed Apr 21 09:20:28 1999
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To: ibis@eda.org, ibis-users@eda.org
Subject: The timing test load parameters
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Date: Wed, 21 Apr 1999 09:14:48 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>


Hello All:

   At last Fridays meeting I was asked to provide a write-up on the
Vmeas, Rref, Cref and Vref parameters.  Here it is.  This text will
also appear in the next edition of the cookbook.

    Regards,
    Stephen Peters
    Intel Corp.

--------
1. What are Vmeas, Rref, Cref and Vref?

Vmeas, Rref, Cref and Vref represent the output loading conditions under 
which a devices Tco (propagation delay or clock-to-output timing) is specified.
These parameters are sometimes referred to as the 'timing test load', and are
documented in a devices data sheet.  Please note that the timing test load does
not necessarily represent the load the device sees in a real application.
It is simply the output load the manufacture uses when characterizing a devices
performance. 


                         Vref
                         ------
                           |
                           \
                           / Rref
      +-------+            \
      |       |            |
 -----| DUT   |------------+  
      |       |            |
      +-------+           ----  
                          ---- Cref
                           |
                          gnd

As shown above, Vref represents a pullup voltage, Rref represents
a load resistance connected to Vref, and Cref is a load capacitance 
to ground.

Vmeas is the point on the output waveform at which a Tco measurement is 
referenced to. As an example, if Tco (clock to output) for a particular
device is 5ns, this means there is a 5ns delay from when input clock waveform
crosses a specific voltage level to when the output responds by crossing
'Vmeas' volts.  See the diagram below.


               +--- Tco ----+ 
               |            |
               | ___________|_____________
               |/           |
    Input      +            |
      ________/             |
                            |
                            | ______________________ 
                            |/
   Output                ---+------- Vmeas
      _____________________/                           




2. So why are these parameters included in an IBIS file?

The timing test load parameters are included in an IBIS file to aid the
user (or simulator) in doing system level timing analysis.  Given that a
device has a specified propagation delay into the timing test load, the user
can simulate the device as it drives this load and determine how long it takes
the output to switch from quiescence to crossing 'Vmeas' volts.  The user can 
then do a second simulation with the device driving the actual load, and by
noting the difference in time it takes to cross 'Vmeas' the user can 
determine the difference in device propagation delay due to output loading.
This is a major factor when doing system level timing analysis.



From owner-ibis  Wed Apr 21 11:18:28 1999
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From: Ken Wu <kenw@3dfx.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: question about ROSUB
Date: Wed, 21 Apr 1999 11:06:13 -0700
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Dear IBISian,

I converted an input buffer IBIS model to spice model using IntuitSoft's
free ibis2spice converter. When I checked the generated equivalent circuit,
it looks like this:


	     PAD
---------------|-----------------ROPKG----|--------LOPKG---------------|----
--clamping diode, etc
			       |
|--------ROSNB---------------|
			       |
|
			 COPKG to gnd
CCOMP to gnd		

Can anyone tell me what is this ROSNB? How to get its value? Thanks in
advance.

Ken Z. Wu
3Dfx Interactive, Inc.
4435 Fortran Drive
San Jose, CA 95134
Tel: (408)935-4309
Fax: (408)262-8602
Email: kenw@3dfx.com



------_=_NextPart_001_01BE8C21.A4A27FF8
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	charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2232.0">
<TITLE>question about ROSUB</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">Dear IBISian,</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">I converted an input buffer IBIS model =
to spice model using IntuitSoft's free ibis2spice converter. When I =
checked the generated equivalent circuit,</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">it looks like this:</FONT>
</P>
<BR>

<P>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp; PAD =
---------------|-----------------ROPKG----|--------LOPKG---------------|=
------clamping diode, etc</FONT></P>

<P>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
|--------ROSNB---------------|</FONT></P>

<P>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |</FONT></P>

<P>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;<FONT SIZE=3D2 =
FACE=3D"Arial"> COPKG to gnd&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; =
&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; CCOMP to =
gnd&nbsp;&nbsp;&nbsp; &nbsp; </FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Can anyone tell me what is this ROSNB? =
How to get its value? Thanks in advance.</FONT>
</P>

<P><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">Ken Z. =
Wu</FONT>
<BR><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">3Dfx =
Interactive, Inc.</FONT>
<BR><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">4435 =
Fortran Drive</FONT>
<BR><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">San Jose, =
CA 95134</FONT>
<BR><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">Tel: =
(408)935-4309</FONT>
<BR><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">Fax: =
(408)262-8602</FONT>
<BR><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">Email: =
kenw@3dfx.com</FONT>
</P>
<BR>

</BODY>
</HTML>
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From owner-ibis  Mon Apr 26 13:27:14 1999
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Date: Mon, 26 Apr 1999 15:19:46 -0500
Subject: IBIS Users Group Agenda 04/30/99
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IBIS Users Conference Call Agenda

Date:  4/30/99
Time:  8:00 - 9:55 am PST
Phone number:  (805) 240-9483
Pass code:  562512


8:00 CHECK-IN

Introduction of new participants
Date for next conference call
Announcements
Corrections to previous meeting's minutes
Additions to the agenda


MISC. USER TOPICS

Syed Huq recently posted a note to the reflector regarding s2ibis for IBIS
v3.2.  He suggested that someone in the Users Group may have an interest in
developing this tool.  Any interested parties?


8:15 IBIS ACCURACY SUBCOMMITTEE

Note:  The Accuracy Working Group should make decisions and assign work
during this meeting.  We should strive to conduct actual editing activities
off-line for the sake of productivity.

IBIS ACCURACY SPECIFICATION 1.2 REVISIONS

Approve or disapprove most recent changes to the IBIS Accuracy Spec.

ACCURACY-RELATED BIRD(S) - No activity.

APPROVAL - Propose schedule for IBIS Open Forum discussion.

IBIS ACCURACY SPECIFICATION 2.0 DEVELOPMENT - No activity.

TEST BOARD - Any updates from National Semiconductor?

WORK LIST:  5 open, 3 closed

1.  Status: CLOSED.  Opened: 2/26/99  Owner: Greg Edlund.  Edit measurement
and correlation sections of the IBIS Accuracy Specification and distribute
the new document.

2.  Status: CLOSED.  Opened: 2/26/99  Owner: Greg Edlund.  Write email to
the reflector soliciting input on the contents of an accuracy-related BIRD.
At issue is whether or not to include a machine-readable description of the
test loads described in the IBIS Accuracy Specification.

3.  Status: open.  Opened: 2/26/99  Owner: Peter LaFlamme.  Make VCX16244
SPICE model and IBIS datasheet available on the accuracy web page.

4.  Status: CLOSED.  Opened: 2/26/99  Owner: Bob Haller, Greg Edlund.
Discuss test board changes off-line.

5.  Status: open.  Opened: 2/26/99  Owner: Milt Schwarz.  Get quote for
building revision 3 of the test board.

6.  Status: open.  Opened: 2/26/99  Owner: Greg Edlund.  Write test board
application note.

7.  Status: open.  Opened: 2/26/99  Owner: Greg Edlund.  Send out a note to
the reflector suggesting possible candidates for accuracy development in
1999.

8.  Status: open:  Opened 3/19/99  Owner:  Bob Haller.  Call Ed Sayre to
set up next face-to-face Users Group meeting.


9:05 EDUCATION


9:55 SIGN-OFF


Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com


From owner-ibis  Tue Apr 27 07:22:46 1999
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Date: Tue, 27 Apr 1999 09:19:41 -0500
From: "Robert Goodrich" <ra3862@email.sps.mot.com>
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To: "ibis-users@eda.org" <ibis-users@eda.org>
Subject: s2ibis rising/falling waveform question.
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I am using a version of s2ibis2 which has been "updated" to work
directly with our version of spice.  It works great, but I have noticed
that for the rising/falling waveforms pulled to vdd (50 Ohms or
whatever) the resistor is always tied to the typ value of vdd.  Is this
the correct way to tie this for min and max simulations?  I would think
that the load res. should be tied to vdd(min) or vdd(max).  Can anyone
clear this up for me before I make changes to s2ibis2?
Thanks,
--Rob
--

Rob Goodrich
Circuit Design - Advanced Imaging Technology (AIT)
Motorola SPS, I&E Solutions
6501 William Cannon Drive West MD: OE37
Austin, TX 78735
ra3862@email.sps.mot.com
(512) 895-7341


From owner-ibis  Tue Apr 27 14:29:49 1999
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From: "Robert Goodrich" <ra3862@email.sps.mot.com>
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All:
I have noticed that s2ibis2 attaches the load resistor (Rload) between
the output
node and vdd(typ) for min and max as well as typ rising/falling waveform
simulations.
I'm guessing that the value for this vdd should track vdd(typ), vdd(min)
and vdd(max)
respectively.  If this assumption is true, then be warned - if not,
please let me know so
I can relax and quit bothering you all with this.
--Rob
--

Rob Goodrich
Circuit Design - Advanced Imaging Technology (AIT)
Motorola SPS, I&E Solutions
6501 William Cannon Drive West MD: OE37
Austin, TX 78735
ra3862@email.sps.mot.com
(512) 895-7341


From owner-ibis  Tue Apr 27 14:41:45 1999
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Date: Tue, 27 Apr 1999 14:35:37 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: Re: s2ibis2 error? in rising/falling waveform generation
To: ibis-users@eda.org, ra3862@email.sps.mot.com
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Rob,

If you use the V_f_min and V_f_max fields in [Rising waveform] and [Falling
waveform], then it will track vdd(min) and vdd(max) respectively. V_f field
tracks vdd(typ).

The syntax is as follows:

[Rising waveform] R_f V_f V_f_min V_f_max L_f C_f R_d C_d L_d

Regards,
Syed
Cisco Systems, Inc

> 
> All:
> I have noticed that s2ibis2 attaches the load resistor (Rload) between
> the output
> node and vdd(typ) for min and max as well as typ rising/falling waveform
> simulations.
> I'm guessing that the value for this vdd should track vdd(typ), vdd(min)
> and vdd(max)
> respectively.  If this assumption is true, then be warned - if not,
> please let me know so
> I can relax and quit bothering you all with this.
> --Rob
> --
> 
> Rob Goodrich
> Circuit Design - Advanced Imaging Technology (AIT)
> Motorola SPS, I&E Solutions
> 6501 William Cannon Drive West MD: OE37
> Austin, TX 78735
> ra3862@email.sps.mot.com
> (512) 895-7341
> 
> 

From owner-ibis  Tue Apr 27 13:25:16 1999
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To: ibis@eda.org, ibis-users@eda.org, si-list@silab.eng.sun.com
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Subject: Vote on IBIS Version 3.2 (Standards Proposal 4557)
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To All:

Standards Proposal 4557 is a proposed revision to EIA-656 "I/O Buffer
Information Specification (IBIS) to Version 3.2 to be pubished, if 
approved, as EIA-656-A and as an American National Standard.

Both the ballot form and the document to review are available on the
EIA IBIS home page for downloading:

  http://www.eia.org/eig/ibis/ibis.htm

Vote is by COMPANY only, and signed ballots may be returned by surface
mail or FAX to the address on the ballot.

The deadline for returning the ballot is June 23, 1999.

Bob Ross
Chair, EIA IBIS Open Forum
Mentor Graphics
From owner-ibis  Wed Apr 28 14:38:47 1999
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Subject: Re: s2ibis rising/falling waveform question.
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Rob,

I just looked this up in the spec.  It's under the sub-heading "[Rising
Waveform], [Falling Waveform]."  It looks like it's up to the modeling
engineer whether or not to use V_fixture_min and V_fixture_max.  Perhaps
s2ibis allows for this option somewhere in one of its control files?

Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com



"Robert Goodrich" <ra3862@email.sps.mot.com> on 04/27/99 09:19:41 AM

To:   "ibis-users@eda.org" <ibis-users@eda.org>
cc:    (bcc: Gregory R Edlund/Rochester/IBM)
Subject:  s2ibis rising/falling waveform question.





I am using a version of s2ibis2 which has been "updated" to work
directly with our version of spice.  It works great, but I have noticed
that for the rising/falling waveforms pulled to vdd (50 Ohms or
whatever) the resistor is always tied to the typ value of vdd.  Is this
the correct way to tie this for min and max simulations?  I would think
that the load res. should be tied to vdd(min) or vdd(max).  Can anyone
clear this up for me before I make changes to s2ibis2?
Thanks,
--Rob
--

Rob Goodrich
Circuit Design - Advanced Imaging Technology (AIT)
Motorola SPS, I&E Solutions
6501 William Cannon Drive West MD: OE37
Austin, TX 78735
ra3862@email.sps.mot.com
(512) 895-7341





From owner-ibis  Fri Apr 30 12:24:05 1999
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IBIS Users Group Minutes 4/30/99


Participants on 4/30/99

Greg Edlund, IBM
Bob Haller, Compaq
Bob Ross, Mentor Grpahics


Next conference call:  as needed.


CHECK-IN

There were no announcements, corrections to previous meeting's minutes, or
additions to the agenda.


GENERAL BUSINESS

Bob Ross:  This conference call seems to be falling below critical mass.
We should do away with regular conference calls and set them up on an
as-needed basis in the future.  General Users Group conference calls will
be held in association with the East Coast face-to-face IBIS Users Group
meetings.

Bob Haller:  The East Coast face-to-face IBIS Users Group meetings
resurrected.  Conference calling will be available at these meetings for
those who wish to use it.  NESA will be hosting the next face-to-face IBIS
Users Group meeting on May 13.

We did not cover the s2ibis for IBIS 3.2 topic since there were only three
people present.  Bob Haller will bring this topic up at the next IBIS Users
Group meeting on the East Coast.


PART I:  IBIS ACCURACY SUBCOMMITTEE

IBIS ACCURACY SPECIFICATION 1.2 REVISIONS

Bob Haller:  The new table 2 should include descriptions of measurements
and drivers.  Open drain drivers should require a pull-up curve measurement
but no tri-state curve.

Bob Haller:  Section 3.2.2 should include an example scope bandwidth
calculation.

Bob Haller:  Section 3.4.1 should clarify that EITHER a 50 Ohm resistor OR
a terminated 50 Ohm transmission line is acceptable.

Bob Ross:  Physical measurement is the "center of gravity" of the spec, but
the methods described in the Accuracy Spec are also applicable to SPICE vs.
hardware and SPICE vs. behavioral correlation.

Bob Ross:  Fast and slow samples are usually available during development
phase, if at all.

Bob Ross:  Where does the trailer go?  It could be associated with the
model keyword or added to the end of the IBIS file.

Greg Edlund:  We could change the name from "trailer" to something else to
allow the model engineer to locate this information wherever it makes
sense.

All:  How does one specify which I/O buffers need to be correlated?  Right
now, this is left up to the discretion of the modeling engineer, but we
should at least add this to the spec.


APPROVAL PROCESS

Bob Ross:  Industry acceptance is more important right now than EIA
approval.  Let's bring the document to the IBIS Open Forum on May 28 and
open discussion.

ACCURACY-RELATED BIRD(S)

There was no discussion related to an accuracy-related BIRD.

TEST BOARD

There was no discussion related to the test board.

IBIS ACCURACY SPECIFICATION DEVELOPMENT

There was no discussion related to future development of the IBIS Accuracy
Specification.

ACCURACY ACTION ITEMS:  4 open, 4 closed

1.  Status: CLOSED.  Opened: 2/26/99  Owner: Greg Edlund.  Edit measurement
and correlation sections of the IBIS Accuracy Specification and distribute
the new document.

2.  Status: CLOSED.  Opened: 2/26/99  Owner: Greg Edlund.  Write email to
the reflector soliciting input on the contents of an accuracy-related BIRD.
At issue is whether or not to include a machine-readable description of the
test loads described in the IBIS Accuracy Specification.

3.  Status: open.  Opened: 2/26/99  Owner: Peter LaFlamme.  Make VCX16244
SPICE model, IBIS datasheet, and trailer available on the accuracy web
page.

4.  Status: CLOSED.  Opened: 2/26/99  Owner: Bob Haller, Greg Edlund.
Discuss test board changes off-line.

5.  Status: open.  Opened: 2/26/99  Owner: Milt Schwarz.  Get quote for
building revision 3 of the test board.

6.  Status: open.  Opened: 2/26/99  Owner: Greg Edlund.  Write test board
application note.

7.  Status: open.  Opened: 2/26/99  Owner: Greg Edlund.  Send out a note to
the reflector suggesting possible candidates for accuracy development in
1999.

8.  Status: CLOSED:  Opened 3/19/99  Owner:  Bob Haller.  Call Ed Sayre to
set up next face-to-face Users Group meeting.


PART II:  EDUCATION SUBCOMMITTEE

There was no one present to discuss education.


Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com