From owner-ibis  Tue Jun  1 17:33:14 1999
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Date: 01 Jun 1999 17:26:23 -0700
From: Abdorrazagh Fereydouni <Abdorrazagh.Fereydouni@nsc.com>
To: ibis-users <ibis-users@eda.org>
Subject: analog driver

Hi, 
I'd like to know whether or not IBIS supports analog I/O drivers(such as 2B1Q 
signal).  If 
so, please direct me to some examples that show how it is done. 

rds, 
Abdi 
From owner-ibis  Wed Jun  2 11:09:39 1999
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From: "Robert Goodrich (ra3862)" <ra3862@email.sps.mot.com>
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All:

To my knowledge s2ibis2 cannot be used directly to model a
buffer that is powered internally at one potential, but will

drive externally at another.  For instance, I am required to

model I/O that internally is 1.8V, but drives a 3.3V
output.  I was wondering, first of all, if there were any
plans in the works for an "updated" s2ibis program (ver
3.2?).  Next, I was wondering if anyone had developed any
scripts or programs on their own that would help model a
buffer of this type.   If so, would you be open to sharing
them?

--Rob


--

Rob Goodrich
Circuit Design - Advanced Imaging Technology (AIT)
Motorola SPS, I&E Solutions
6501 William Cannon Drive West MD: OE37
Austin, TX 78735
ra3862@email.sps.mot.com
(512) 895-7341



From owner-ibis  Wed Jun  2 15:15:22 1999
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From: "Beal, Weston" <Weston.Beal@COMPAQ.com>
To: ibis-users@eda.org
Subject: RE: Multiple voltage levels and s2ibis2
Date: Wed, 2 Jun 1999 16:18:11 -0500 
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Rob,

Just connect your internal power node to a voltage source in your netlist.
The voltage that needs to be varied for case modeling is that of the output
stage (3.3V).  In the s2ibis control file you can set Vih to 1.8V for the
level of the input pulse.

Regards,
Weston Beal
Signal Integrity Engineer
Compaq Computer Corp.

		-----Original Message-----
		From:	Robert Goodrich (ra3862)
[mailto:ra3862@email.sps.mot.com]
		Sent:	Wednesday, 02 June, 1999 1:04 PM
		To:	ibis-users@eda.org
		Subject:	Multiple voltage levels and s2ibis2

		All:

		To my knowledge s2ibis2 cannot be used directly to model a
		buffer that is powered internally at one potential, but will

		drive externally at another.  For instance, I am required to

		model I/O that internally is 1.8V, but drives a 3.3V
		output.  I was wondering, first of all, if there were any
		plans in the works for an "updated" s2ibis program (ver
		3.2?).  Next, I was wondering if anyone had developed any
		scripts or programs on their own that would help model a
		buffer of this type.   If so, would you be open to sharing
		them?

		--Rob


		--

		Rob Goodrich
		Circuit Design - Advanced Imaging Technology (AIT)
		Motorola SPS, I&E Solutions
		6501 William Cannon Drive West MD: OE37
		Austin, TX 78735
		ra3862@email.sps.mot.com
		(512) 895-7341

		
From owner-ibis  Wed Jun  2 18:18:20 1999
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Date: Wed, 02 Jun 1999 18:12:22 +0000
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Subject: DAC IBIS Summit Meeting - Second Announcement
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                  D A C   I B I S   S U M M I T   M E E T I N G
                      S E C O N D   A N N O U N C E M E N T

DATE:      Monday, June 21, 1993
TIME:      8:30 AM - Afternoon

CITY:      New Orleans, Louisiana

LOCATION:  Hilton Hotel, New Orleans Riverside, next to Ernest N. Morial
           Convention Center where the Design Automation Conference (DAC)
           is being held.

ROOM:      Chequers

LUNCH:     Refreshments and Lunch will be provided.

AGENDA:    The agenda is being planned.  Some planned items are:

           Business & Discussions:

           - Election of Officers for 1999-2000
           - Open BIRDs Discussion
           - IBIS Version 3.2 Letter Ballot Response Issues
           - s2ibis2/3 Project Report
           - Version 4.X Features

           Expected Presentations to Date:
             
           - IBIS 98-99 Overview - Bob Ross, Mentor Graphics
           - Accuracy Specification Update - Bob Haller, Compaq
           - ECALS-2 and the EMI Problem - Atsushi Ito, Matsushita
           - Equation Based Modeling, Arpad Muranyi, Intel
           - Status of IMIC, Hideki Fukuda, Hitachi

DAC:       DAC is scheduled Monday - Friday, June 21 -25, 1999.  The
           exhibitor portion is open from 10 AM to 6 PM on Monday - Wednesday.
           So there should be time after the IBIS Summit meeting to visit the
           show.  For more information on DAC99 activities, housing, etc.
           visit the DAC99 URL.

DAC URL:   http://www.dac.com/


CALL FOR PRESENTATIONS:

           Along with the presentatations currently planned, we welcome other
           technical presentations related to any current IBIS activity and to
           future IBIS needs.
 
           Contact Matthew Flora (see below) regarding your presentation:

              Presenter:
              Title:
              Estimated Time:

           We would like you to provide handouts for the meeting (about 25)
           and also an electronic copy for archiving.
          

CALL FOR ATTENDEES:

           Please let Matthew Flora know if you are planning to attend so
           we have an estimate on food requirements. 

CONTACT:   Matthew Flora
           mbflora@hyperlynx.com
           (425) 869-2320


From owner-ibis  Wed Jun  2 23:10:34 1999
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From: Dan Aleksandrowicz <dan@galileo.co.il>
Organization: GALILEO Technology Ltd.
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To: Robert Goodrich <ra3862@email.sps.mot.com>, ibis-users@eda.org
Subject: Re: Multiple voltage levels and s2ibis2
References: <427351B4DEABD111A99400805F19E9BB02D62B14@exchou-prod0901.eng.hou.compaq.com>
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Rob,

I agree with  Beal's solution, and would like to add to it another aspect.

If you create in your spice stack a global voltage source of VDD1_8 - 1.8V
I would recommend you use voltage dependent source which is relevant to the
3.3V of your pad supply.

This will enable you to properly simulate the max & min cases were the
min voltage will be = (1.8-0.18)  and the max = (1.8 +0.18). I also recommend
you checking your [vil] and [vih] in the *s2i file that they fit the min and
max cases.

[vil] 0.6 0.4 0.8
[vih] 1.6 1.4 1.8


good luck.

Dan.

"Beal, Weston" wrote:

> Rob,
>
> Just connect your internal power node to a voltage source in your netlist.
> The voltage that needs to be varied for case modeling is that of the output
> stage (3.3V).  In the s2ibis control file you can set Vih to 1.8V for the
> level of the input pulse.
>
> Regards,
> Weston Beal
> Signal Integrity Engineer
> Compaq Computer Corp.
>
>                 -----Original Message-----
>                 From:   Robert Goodrich (ra3862)
>                 model I/O that internally is 1.8V, but drives a 3.3V
>                 output.  I was wondering, first of all, if there were any
>                 plans in the works for an "updated" s2ibis program (ver
>                 3.2?).  Next, I was wondering if anyone had developed any
>                 scripts or programs on their own that would help model a
>                 buffer of this type.   If so, would you be open to sharing
>                 them?
>
>

--
                \\|//
                (o o)
~~~~~~~~~~~~oOOo~(_)~oOOo~~~~~~~~~~~~~~~~~~~
Dan Aleksandrowicz
Galileo Technology
Mercaz Ofek 1   (Building B')
Northern Industrial Zone, LOD 71293,  ISRAEL
email:dan@galileo.co.il
Tel: +972 8 9247555    (-
     Ext. 324         |__|
                      |__|
                     #|oo| |--|   ___
           _  _    |--|  | |  |\ |oo|)        /\
       __  \\ \\   |------------\| #|--\     _||-
   ____\ \__\\_\\__|_||_________________\___|   |__v-___
   \                                                   /
    \      "Smoke on the water. Fire in the sky."     /
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



--------------3661227CD7BEE59CA69EA6AE
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Rob,
<p>I agree with&nbsp; Beal's solution, and would like to add to it another
aspect.
<p>If you create in your spice stack a global voltage source of VDD1_8
- 1.8V
<br>I would recommend you use voltage dependent source which is relevant
to the
<br>3.3V of your pad supply.
<p>This will enable you to properly simulate the max &amp; min cases were
the
<br>min voltage will be = (1.8-0.18)&nbsp; and the max = (1.8 +0.18). I
also recommend
<br>you checking your [vil] and [vih] in the *s2i file that they fit the
min and max cases.
<p>[vil] 0.6 0.4 0.8
<br>[vih] 1.6 1.4 1.8
<br>&nbsp;
<p>good luck.
<p>Dan.
<p>"Beal, Weston" wrote:
<blockquote TYPE=CITE>Rob,
<p>Just connect your internal power node to a voltage source in your netlist.
<br>The voltage that needs to be varied for case modeling is that of the
output
<br>stage (3.3V).&nbsp; In the s2ibis control file you can set Vih to 1.8V
for the
<br>level of the input pulse.
<p>Regards,
<br>Weston Beal
<br>Signal Integrity Engineer
<br>Compaq Computer Corp.
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-----Original Message-----
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
From:&nbsp;&nbsp; Robert Goodrich (ra3862)
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
model I/O that internally is 1.8V, but drives a 3.3V
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
output.&nbsp; I was wondering, first of all, if there were any
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
plans in the works for an "updated" s2ibis program (ver
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
3.2?).&nbsp; Next, I was wondering if anyone had developed any
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
scripts or programs on their own that would help model a
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
buffer of this type.&nbsp;&nbsp; If so, would you be open to sharing
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
them?
<br>&nbsp;
<br>&nbsp;</blockquote>

<pre>--&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; \\|//
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (o o)
~~~~~~~~~~~~oOOo~(_)~oOOo~~~~~~~~~~~~~~~~~~~
Dan Aleksandrowicz
Galileo Technology&nbsp;
Mercaz Ofek 1&nbsp;&nbsp; (Building B')&nbsp;
Northern Industrial Zone, LOD 71293,&nbsp; ISRAEL&nbsp;
email:dan@galileo.co.il
Tel: +972 8 9247555&nbsp;&nbsp;&nbsp; (-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp; Ext. 324&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |__|
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |__|
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; #|oo| |--|&nbsp;&nbsp; ___
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; _&nbsp; _&nbsp;&nbsp;&nbsp; |--|&nbsp; | |&nbsp; |\ |oo|)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /\
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; __&nbsp; \\ \\&nbsp;&nbsp; |------------\| #|--\&nbsp;&nbsp;&nbsp;&nbsp; _||-
&nbsp;&nbsp; ____\ \__\\_\\__|_||_________________\___|&nbsp;&nbsp; |__v-___
&nbsp;&nbsp; \&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /
&nbsp;&nbsp;&nbsp; \&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "Smoke on the water. Fire in the sky."&nbsp;&nbsp;&nbsp;&nbsp; /
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~</pre>
&nbsp;</html>

--------------3661227CD7BEE59CA69EA6AE--

From owner-ibis  Thu Jun  3 09:08:57 1999
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Date: Thu, 03 Jun 1999 11:13:53 -0400
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From: Kathy Breda <breda@nesa.com>
Subject: IBIS Users' Group - Change to day of meeting?
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Greetings:

I have had a request to change the IBIS Users' meetings from Thursday
to any other day of the week.  I'd like to suggest either 
Wednesday or Friday - same time, 3:00 PM.

Let me hear your feedback.
          IBIS needs your support and technical input.
                                      The majority vote picks the day!

Thanks,

   Kathy Breda
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
|       NORTH EAST SYSTEMS ASSOCIATES, INC.       |
|      -------------------------------------      |
|     "High Performance Engineering & Design"     |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| Kathy Breda             e-mail: breda@nesa.com |
| NESA, Inc.              http://www.nesa.com/    |
| 636 Great Road          Tel +1.978.897-8787     |
| Stow, MA 01775 USA      Fax +1.978.897-5359     |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

From owner-ibis  Wed Jun  9 10:40:35 1999
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subscribe  david_hanson@mentorg.com
 
---------------------------------------
David L. Hanson
Phone (503) 685-1121 FAX (503) 645-4897
david_hanson@mentorg.com
The fear of the Lord is the beginning!
---------------------------------------
From owner-ibis  Fri Jun 11 15:20:40 1999
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To All:

REMINDER TO VOTE ON SP-4557.

Download the ballot form from the EIA IBIS home page:

  http://www.eia.org/eig/ibis/ibis.htm

Return by surface mail or FAX the completed, signed form.  Vote is
by COMPANY only.

DEADLINE is June 23, 1999.

Standards Proposal 4557 is a proposed revision to EIA-656 "I/O Buffer
Information Specification (IBIS) to Version 3.2 to be pubished, if 
approved, as EIA-656-A and as an American National Standard.

Thank you
Bob Ross
Chair, EIA IBIS Open Forum
Mentor Graphics
From owner-ibis  Mon Jun 14 12:08:27 1999
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Date: Mon, 14 Jun 1999 12:00:44 -0700
From: Bob Ross <bob_ross@mentorg.com>
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To: ibis@eda.org, ibis-users@eda.org
CC: will.hobbs@intel.com
Subject: [Fwd: REMINDER TO VOTE ON IBIS SP-4557]
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Will:

Just to clarify, only one vote per COMPANY is allowed.
So if several votes are received from a company, and they
disagree, we will need to resolve any disagreement by 
identifying the selecting the vote from the primary 
representative.

However, we will officially review and respond to any comment
received.

Thanks,
Bob Ross
Mentor Graphics
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From: "Hobbs, Will" <will.hobbs@intel.com>
To: "'Bob Ross'" <bob_ross>
Subject: RE: REMINDER TO VOTE ON IBIS SP-4557
Date: Fri, 11 Jun 1999 16:32:44 -0700
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Bob,

You might want to mention EIA's policy concerning what votes
actually count. Is it one vote per member company, and all comments
will be reviewed and responded to, or do all votes count?

Will

-----Original Message-----
From: Bob Ross [mailto:bob_ross@mentorg.com]
Sent: Friday, June 11, 1999 3:14 PM
To: ibis@eda.org; ibis-users@eda.org; si-list@silab.eng.sun.com
Cc: cfleming@eia.org
Subject: REMINDER TO VOTE ON IBIS SP-4557


To All:

REMINDER TO VOTE ON SP-4557.

Download the ballot form from the EIA IBIS home page:

  http://www.eia.org/eig/ibis/ibis.htm

Return by surface mail or FAX the completed, signed form.  Vote is
by COMPANY only.

DEADLINE is June 23, 1999.

Standards Proposal 4557 is a proposed revision to EIA-656 "I/O Buffer
Information Specification (IBIS) to Version 3.2 to be pubished, if 
approved, as EIA-656-A and as an American National Standard.

Thank you
Bob Ross
Chair, EIA IBIS Open Forum
Mentor Graphics

--------------284FD0A2ACD1280186A12E34--

From owner-ibis  Tue Jun 15 00:00:54 1999
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From: wis_macomson@mentorg.com (Wis_macomson)
Message-Id: <199906150652.OAA27454@em-tw01.twt.mentorg.com>
Subject: timing on GTL+ bus
To: ibis-users@eda.org
Date: Tue, 15 Jun 1999 14:52:03 +0800 (CST)
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To All:

Be aware that when simulating a GTL+ bus using some processor
models, you must adjust the receiver input thresholds when the
driver has different slow and fast models and assumes different
termination voltages in them.

Some new processors have internal pull-up resistors for the GTL bus,
which reduces parts significantly, and result in extremely
attractive signal quality when the processor receives.  The
resistors are connected to separate termination voltage (Vtt) supply
pins.

When simulating slow corner for timing, one uses the low termination
voltage and high internal resistor values.  The fast corner uses
high Vtt and low resistance.  For the components with internal pull-
ups, this can be done with a model whose [Voltage Range] is set to
the termination voltage desired, and the V-I curves take care of the
resistor values.

Remember that Vinl and Vinh for the GTL bus are based on some
reference voltage, Vref, which is typically developed via a
resistive divider between Vtt and ground.  For a widely used GTL
variant called "GTL+", Vtt = +1.5V and Vref is nominally 2/3*Vtt =
+1.00V.  Often, Vinl and Vinh are specified as offsets from Vref,
such as:

	Vinl(max) = Vref - 200mV
	Vinh(min) = Vref + 200mV

In the nominal case listed above, then, Vinl would be +0.800V, and
Vinh would be +1.200V.  Indeed, a popular GTL+ bridge component has
these values listed in its IBIS model.

However, if Vtt is at its low margin level, for example +1.35V, then
Vref will be +0.900V, and the receiver thresholds should "reflect"
this.  Using the example, Vinl(max) = +0.700V, Vinh(min) = +1.100V.

In the case where a slow corner model includes the low Vtt value,
the output voltage step may not be able to incident wave switch
on the low to high transition, if one uses the Vinh value derived
from the nominal Vtt as the timing point on the receiver waveform.

In a specific instance, the existing model for a GTL+ bridge
component, with Vinl=+0.8V, Vinh=+1.2V, showed timing violations on
the slow corner.  The slow corner drivers on the processor showed a
shelf just below +1.2V, when the PCB trace impedance was at its low
value.  The voltage didn't cross the high threshold until after the
slow RC charging from the step up to Vtt, which violated timing.

Because Vtt and Vref were common to the processor and bridge, it is
reasonable to assume that the switching threshold at the bridge
would track the Vtt.  Setting Vinh to +1.1V showed that the timing
was acceptable.  (One just might think that they designed the
processor output buffers just big enough to handle the low trace
impedance case.)

This discussion extends to the fast corner, where the nominal
thresholds would give an overly conservative (smaller) hold time
estimate, because the thresholds would be lower than actual.

The unfortuate part of this is that you now need "slow" and "fast"
receiver models, as there is no "typ/min/max" for Vinl and Vinh.

The other point to keep in mind is that you need to be very careful
if you have a system design with separate Vtt supplies to the loads
on a GTL bus, or if you have separate Vref's to those loads.

	Note: for margin, one could take into account the
	tolerance of the divider resistors, and adust Vinl
	and Vinh up or down appropriately.

Regards,

-wis
-- 
Wis Macomson
SiQual
c/o Wis_Macomson@mentor.com
From owner-ibis  Tue Jun 15 20:22:16 1999
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From: "Beal, Weston" <Weston.Beal@COMPAQ.com>
To: "'wis_macomson@mentorg.com'" <wis_macomson@mentorg.com>,
        ibis-users@eda.org
Subject: RE: timing on GTL+ bus
Date: Tue, 15 Jun 1999 12:55:32 -0500
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Wis,

This is covered in IBIS 3.x with the vinl and vinh under [Model Spec].
There you can specify typ, min, max for these thresholds.

Regards,
Weston Beal
Signal Integrity Engineer
Compaq Computer Corp.

		-----Original Message-----
		From:	wis_macomson@mentorg.com
[mailto:wis_macomson@mentorg.com]
		Sent:	Tuesday, 15 June, 1999 1:52 AM
		To:	ibis-users@eda.org
		Subject:	timing on GTL+ bus

		To All:

		Be aware that when simulating a GTL+ bus using some
processor
		models, you must adjust the receiver input thresholds when
the
		driver has different slow and fast models and assumes
different
		termination voltages in them.

		Some new processors have internal pull-up resistors for the
GTL bus,
		which reduces parts significantly, and result in extremely
		attractive signal quality when the processor receives.  The
		resistors are connected to separate termination voltage
(Vtt) supply
		pins.

		When simulating slow corner for timing, one uses the low
termination
		voltage and high internal resistor values.  The fast corner
uses
		high Vtt and low resistance.  For the components with
internal pull-
		ups, this can be done with a model whose [Voltage Range] is
set to
		the termination voltage desired, and the V-I curves take
care of the
		resistor values.

		Remember that Vinl and Vinh for the GTL bus are based on
some
		reference voltage, Vref, which is typically developed via a
		resistive divider between Vtt and ground.  For a widely used
GTL
		variant called "GTL+", Vtt = +1.5V and Vref is nominally
2/3*Vtt =
		+1.00V.  Often, Vinl and Vinh are specified as offsets from
Vref,
		such as:

			Vinl(max) = Vref - 200mV
			Vinh(min) = Vref + 200mV

		In the nominal case listed above, then, Vinl would be
+0.800V, and
		Vinh would be +1.200V.  Indeed, a popular GTL+ bridge
component has
		these values listed in its IBIS model.

		However, if Vtt is at its low margin level, for example
+1.35V, then
		Vref will be +0.900V, and the receiver thresholds should
"reflect"
		this.  Using the example, Vinl(max) = +0.700V, Vinh(min) =
+1.100V.

		In the case where a slow corner model includes the low Vtt
value,
		the output voltage step may not be able to incident wave
switch
		on the low to high transition, if one uses the Vinh value
derived
		from the nominal Vtt as the timing point on the receiver
waveform.

		In a specific instance, the existing model for a GTL+ bridge
		component, with Vinl=+0.8V, Vinh=+1.2V, showed timing
violations on
		the slow corner.  The slow corner drivers on the processor
showed a
		shelf just below +1.2V, when the PCB trace impedance was at
its low
		value.  The voltage didn't cross the high threshold until
after the
		slow RC charging from the step up to Vtt, which violated
timing.

		Because Vtt and Vref were common to the processor and
bridge, it is
		reasonable to assume that the switching threshold at the
bridge
		would track the Vtt.  Setting Vinh to +1.1V showed that the
timing
		was acceptable.  (One just might think that they designed
the
		processor output buffers just big enough to handle the low
trace
		impedance case.)

		This discussion extends to the fast corner, where the
nominal
		thresholds would give an overly conservative (smaller) hold
time
		estimate, because the thresholds would be lower than actual.

		The unfortuate part of this is that you now need "slow" and
"fast"
		receiver models, as there is no "typ/min/max" for Vinl and
Vinh.

		The other point to keep in mind is that you need to be very
careful
		if you have a system design with separate Vtt supplies to
the loads
		on a GTL bus, or if you have separate Vref's to those loads.

			Note: for margin, one could take into account the
			tolerance of the divider resistors, and adust Vinl
			and Vinh up or down appropriately.

		Regards,

		-wis
		-- 
		Wis Macomson
		SiQual
		c/o Wis_Macomson@mentor.com
From owner-ibis  Sun Jun 20 20:58:30 1999
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From: Weber Chuang <WeberChuang@via.com.tw>
To: "'ibis-users'" <ibis-users@eda.org>
Subject: RE: analog driver
Date: Mon, 21 Jun 1999 11:32:53 +0800
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Hi ,

  Could I know what is 2B1Q? thanks in advance!

  Best Regards

     Weber 

-----Original Message-----
From: Abdorrazagh Fereydouni [mailto:Abdorrazagh.Fereydouni@nsc.com]
Sent: Wednesday, June 02, 1999 8:26 AM
To: ibis-users
Subject: analog driver


Hi, 
I'd like to know whether or not IBIS supports analog I/O drivers(such as
2B1Q 
signal).  If 
so, please direct me to some examples that show how it is done. 

rds, 
Abdi 
From owner-ibis  Mon Jun 21 11:25:18 1999
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Message-ID: <376E821A.132C8D64@staktek.com>
Date: Mon, 21 Jun 1999 13:19:07 -0500
From: Russell Rapport <rrapport@staktek.com>
Reply-To: rrapport@staktek.com
Organization: Staktek Corp.
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To: Weber Chuang <WeberChuang@via.com.tw>
CC: "'ibis-users'" <ibis-users@eda.org>
Subject: Re: analog driver
References: <9BADB79F06B3D211974800A0C92BD8A00810F0@EXCHANGE2>
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2B1Q is a bidirectional signaling scheme (a "line code") used on telephone
lines in which 2 binary bits are encoded in a single "quaternary" symbol,
containing 4 amplitude levels. This line code is used to limit the
bandwidth, thus reducing crosstalk problems inside cable bundles.

Weber Chuang wrote:

> Hi ,
>
>   Could I know what is 2B1Q? thanks in advance!
>
>   Best Regards
>
>      Weber
>
> -----Original Message-----
> From: Abdorrazagh Fereydouni [mailto:Abdorrazagh.Fereydouni@nsc.com]
> Sent: Wednesday, June 02, 1999 8:26 AM
> To: ibis-users
> Subject: analog driver
>
> Hi,
> I'd like to know whether or not IBIS supports analog I/O drivers(such as
> 2B1Q
> signal).  If
> so, please direct me to some examples that show how it is done.
>
> rds,
> Abdi

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begin:vcard 
n:Rapport;Russell
tel;fax:512-454-9409
tel;work:512-454-9531 x235
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org:Staktek Corporation
adr:version:2.1;;8900 Shoal Creek Blvd #125;Austin;Tx;78757;
version:2.1
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title:Senior Product Development Engineer
x-mozilla-cpt:;-9936
fn:Russell Rapport
end:vcard

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From owner-ibis  Fri Jun 25 17:13:05 1999
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From: "Montoya, Silvia" <Silvia.Montoya@actel.com>
To: ibis-users@eda.org
Subject: RE: Characterization Conditions
Date: Fri, 25 Jun 1999 17:06:51 -0700
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Hello fellow model makers ,

  Can someone please explain what   ' s2ibis2 ' utility  does with the
package RLC 
  [R_pkg], [L_pkg], [C_pkg]  specified  in the  s2ibis2 command file ?  Is
it used as 
  input to the Spice simulation of I/V data , Ramp data , Rising /Falling
waveform ?  
  Or is it mearly copied to the final IBIS Model file.

  Thanks !

 Silvia Montoya
 Actel Corporation
 silvia.montoya@actel.com


From owner-ibis  Sun Jun 27 13:43:43 1999
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From: cc123@boardermail.com
Message-Id: <199906272043.NAA23672@server.eda.org>
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From owner-ibis  Mon Jun 28 09:32:46 1999
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	Mon, 28 Jun 1999 09:26:08 -0700 (PDT)
Message-Id: <199906281626.JAA00401@jasper.cisco.com>
Date: Mon, 28 Jun 1999 09:26:08 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: RE: Characterization Conditions
To: ibis-users@eda.org, Silvia.Montoya@actel.com
MIME-Version: 1.0
Content-Type: TEXT/plain; charset=us-ascii
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Silvia,

The way I understand this, the package parameters are not added to the netlist 
for the I/V or Ramp or Rising/Falling waveform simulations. This is clear if
you look at any of the s2ibis2 generated input files(.spi).

I believe that's how it should be done anyways.

Regards,
Syed.
Cisco Systems, Inc

> X-SMAP-Received-From: outside
> From: "Montoya, Silvia" <Silvia.Montoya@actel.com>
> To: ibis-users@eda.org
> Subject: RE: Characterization Conditions
> Date: Fri, 25 Jun 1999 17:06:51 -0700
> MIME-Version: 1.0
> 
> Hello fellow model makers ,
> 
>   Can someone please explain what   ' s2ibis2 ' utility  does with the
> package RLC 
>   [R_pkg], [L_pkg], [C_pkg]  specified  in the  s2ibis2 command file ?  Is
> it used as 
>   input to the Spice simulation of I/V data , Ramp data , Rising /Falling
> waveform ?  
>   Or is it mearly copied to the final IBIS Model file.
> 
>   Thanks !
> 
>  Silvia Montoya
>  Actel Corporation
>  silvia.montoya@actel.com
> 
> 

