From owner-ibis  Fri Oct  1 14:51:47 1999
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Subject: Modeling question
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Date: Fri, 01 Oct 1999 17:51:03 -0400
From: Jerry Hayes <jhayes@btv.ibm.com>


I am attempting to create a v2.1 ibis model for a driver that is
essentially an I/O_open_drain with internal pullup termination.
I have created various ibis models for this driver ... however none
of them are correlating well to spice due to the internal pullup.
Can anyone suggest the proper modeling technique for this type of
driver?  Helpful suggestions are greatly appreciated.

Thanks,
Jerry Hayes
 

From owner-ibis  Fri Oct  1 16:28:31 1999
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Date: Fri, 01 Oct 1999 16:27:38 -0700
From: jonp@pacbell.net
Subject: Re: Modeling question
To: Jerry Hayes <jhayes@btv.ibm.com>
Cc: ibis-users@eda.org
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References: <199910012151.RAA32312@tornado.btv.ibm.com>

Jerry,
I think the problem is that the "pullup" part of the model is always
turned on. (IBIS simulators expect it to turn off during the falling
edge and this is probably happening by default in your model)

I have two ideas to try:

1) Remove the pullup, make the model, and then put the pullup in by hand
as a part of the shunt curve.

2) Make the model as regular but do not make a "pull-up" measurement (or
set it all to zero) and once again let the pull-up curve reside in the
shunt part of the model.

regards,
Jon Powell
Manager, High Speed Consulting Services, Viewlogic Systems


From owner-ibis  Fri Oct  1 16:57:25 1999
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Date: Fri, 01 Oct 1999 16:55:08 -0700
To: Jerry Hayes <jhayes@btv.ibm.com>
From: Donald Telian <donaldt@cadence.com>
Subject: Re: Modeling question
Cc: ibis-users@eda.org
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Jerry,


You can hide the pullup in the PowerClamp, such as:


<smaller><smaller>[POWER Clamp Reference]                2.5V       NA   
    NA

[POWER Clamp]

-2.5V  16.67mA  NA  NA | Use: V= -1*[POWER Clamp Reference], I=([POWER
Clamp Reference]/resistor_value)

 0.0V      0mA  NA  NA 

 2.5V -16.67mA  NA  NA | Use: V=[POWER Clamp Reference], I= -1*([POWER
Clamp Reference]/resistor_value)

</smaller></smaller>

This example ties a 150 Ohm resistor to 2.5 volts and leaves it there
even if the output tri-states.


Donald Telian

CADENCE



At 05:51 PM 10/01/1999 -0400, Jerry Hayes wrote:

>

>I am attempting to create a v2.1 ibis model for a driver that is

>essentially an I/O_open_drain with internal pullup termination.

>I have created various ibis models for this driver ... however none

>of them are correlating well to spice due to the internal pullup.

>Can anyone suggest the proper modeling technique for this type of

>driver?  Helpful suggestions are greatly appreciated.

>

>Thanks,

>Jerry Hayes

> 

>

>

>

Donald Telian

Cadence Design Systems

phone: 408-944-7791

email: donaldt@cadence.com
From owner-ibis  Fri Oct  1 16:10:54 1999
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Date: Fri, 01 Oct 1999 16:55:45 -0400
To: ibis-users@eda.org, ibis@eda.org
From: Kathy Breda <breda@nesa.com>
Subject: IBIS Summit - Thursday, 14-Oct-99 - updated AGENDA included
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Greetings,


If you are interested in attending the IBIS summit, and

have not responded, please reply to this message.


Attached you will find the Draft Agenda for the meeting.


************************************************************


<bold>I B I S   S U M M I T   M E E T I N G

</bold>


Time/Date:      8:30 AM - 5:00 PM, Thursday, October 14, 1999


Location:       Marlboro Holiday Inn <bold>(NOT AT THE BOXBORO HOLIDAY
INN THIS YEAR)

</bold>                265 Lakeside Ave. 

                Marlboro, MA

                Tel:  (508) 481-3000

               

Content:        Presentations and Discussions


Purpose:        Solicit and Exchange IBIS Model Related Information and
Ideas.


Sponsors:       North East Systems Associates, Inc. (NESA), Hyperlynx,
Praegitzer Design

       


PCB Conference: October 11-15, 1999

East            Royal Plaza Trade Center

                Marlborough, Massachusetts

                See http://www.pcbeast.com/ for more information.


************************************************************

<bold>PROPOSED AGENDA

</bold>

8:30 AM   MORNING REFRESHMENTS (from the Sponsors)


9:00 AM   Introductions and Business

          Bob Ross, Mentor Graphics

          Ed Sayre North East Systems Associates (NESA)


9:30 AM   "Making the IBIS Specification More Readable"

          Roy Leventhal, 3Com


10:00 AM  "Model Extraction Based on Differential TDR"

          Steven Corey, Time Domain Analysis Systems


10:30 AM  BREAK (Refreshments from Sponsors)


10:45 AM  Roundtable - Accuracy Specification

          Bob Haller, Compaq (Leader)


12:00 PM  LUNCH (Provided to Attendees by the Sponsors)


1:00 PM   Roundtable - Input Modeling Discussion 

          Stephen Peters, Intel (Leader)


2:00 PM   Roundtable - IBIS Version 4.0 Features Discussion

          Bob Ross, Mentor Graphics (Leader)


2:30 PM   BREAK (Refreshments from Praegitzer Design)


2:45 PM   "Proposed Improvements to the SPICE to IBIS Tool"

          Mohamed Nasef, Mentor Graphics


3:15 PM   Roundtable - Spice to IBIS Discussion

          Mike LaBonte, Cadence


4:00 PM   Roundtable - Future of User Group Discussion

          Ed Sayre, NESA (Leader)


5:00 PM   FINAL BUSINESS AND ADJORN



****************************************************************************

<bold>DIRECTIONS TO MEETING

</bold>

The Marlboro Holiday Inn

is located at the junction of Route 20 and I-495

(exit 24A off I-495 North or South)

Located 4 miles from the Massachusetts Turnpike and

One Mile from I-290.  Thirty miles from Boston and

Logan International Airport


****************************************************************************


<bold>LIST OF NEARBY HOTELS

</bold>

Marlboro Holiday Inn

265 Lakeside Ave. 

Marlboro, MA

Tel:  (508)481-3000


Boxboro Holiday Inn.  

One Adams Place

Boxboro, MA

Tel:  (978) 263-8701

Fax:  (978) 263-0518


Royal Plaza Hotel 

181 Boston Post road West

Marlborough, MA 01752

Tel:  (508) 460-0700


Radisson Inn

75 Felton St.

Marlboro, MA

Tel:  (508) 480-0015


Embassy Suites Hotels

123 Boston Post Rd.

West Marlboro, MA

(508) 485-5900


Amerscot House

61 West Acton Road

Stow, MA  01775

email: doreen@amerscot.com, web site http://www.amerscot.com

Tel: (508)897-0666, FAX (508)897-6914


Westford Regency Inn

219 Littleton Rd. (exit 32 off I-495)

Westford, MA

Tel:  (978) 692-8200



+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

|       NORTH EAST SYSTEMS ASSOCIATES, INC.       |

|      -------------------------------------      |

|     "High Performance Engineering & Design"     |

+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

| Kathy Breda             e-mail: breda@nesa.com  |

| NESA, Inc.              http://www.nesa.com/    |

| 636 Great Road          Tel +1.978.897-8787     |

| Stow, MA 01775 USA      Fax +1.978.897-5359     |

+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
From owner-ibis  Mon Oct  4 13:15:14 1999
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Date: Mon, 4 Oct 1999 13:14:31 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: s2ibis2 error msg
To: ibis-users@eda.org
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Hi,

I am running the fix version of s2ibis2 on HSPICE and Solaris OS and got
the following:

s2ibis2.sun4.fix: Data begin marker analysis not found in output file rdx8.out.

What does the above error msg mean ? 

Regards,
Syed
Cisco Systems, Inc

From owner-ibis  Mon Oct  4 13:59:53 1999
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From: "Ammar, Ramzi" <r-ammar@ti.com>
To: ibis-users@eda.org
Subject: LVDS differential output RampRise and RampFall
Date: Mon, 4 Oct 1999 15:59:08 -0500 
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I am generating an IBIS model for an lvds device that has differential
output. I was wondering if I should use the output as follows or I should
remove the 100 ohm load and treat the output as a stand alone? The 100 ohm
resistor is used as the test load with 10pf caps to GND at each output (that
I did not show).  Any suggetions.

Regards,
Ramzi Ammar
 



RampRise
---------------

                        		
       	I---- \	
	I       \ ---------------|----------------------------------|
<------ Pin under test
	I         \              |                                 	|
	I           \           /			/
	I            >         \			\   50 ohm 
	|          /            /  100ohm		/
	|        /              |			|
	|      /o--------------|--------------|		GND
	|----/			floating



RampFall
---------------


       	I---- \
	I       \ ---------------|----------------------------------|
<------  Pin under test
	I         \              |                                 	|
	I           \           /			/
	I            >         \			\   50 ohm 
	|          /            /  100ohm		/
	|        /              |			|
	|      /o--------------|--------------|		VDD
	|----/			floating


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<TITLE>LVDS differential output RampRise and RampFall</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">I am generating an IBIS model for an =
lvds device that has differential output. I was wondering if I should =
use the output as follows or I should remove the 100 ohm load and treat =
the output as a stand alone? The 100 ohm resistor is used as the test =
load with 10pf caps to GND at each output (that I did not show).&nbsp; =
Any suggetions.</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Regards,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Ramzi Ammar</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&nbsp;</FONT>
</P>
<BR>
<BR>

<P><FONT SIZE=3D2 FACE=3D"Arial">RampRise</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">---------------</FONT>
</P>

<P><FONT SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I---- \ =
</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">I&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; \ =
---------------|----------------------------------|&nbsp; &lt;------ =
Pin under test</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">I&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
\&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; =
|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp; |</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">I&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp; \&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">I&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp; &gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
\&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; \&nbsp;&nbsp; 50 ohm </FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/&nbsp; 100ohm&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/o--------------|--------------| =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; GND</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">|----/&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; floating</FONT>
</P>
<BR>
<BR>

<P><FONT SIZE=3D2 FACE=3D"Arial">RampFall</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">---------------</FONT>
</P>
<BR>

<P><FONT SIZE=3D2 =
FACE=3D"Arial">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I---- =
\</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">I&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; \ =
---------------|----------------------------------|&nbsp;&nbsp;&nbsp; =
&lt;------&nbsp; Pin under test</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">I&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
\&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; =
|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp; |</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">I&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp; \&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">I&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp; &gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
\&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; \&nbsp;&nbsp; 50 ohm </FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/&nbsp; 100ohm&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
/o--------------|--------------| =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VDD</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">|----/&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; floating</FONT>
</P>

</BODY>
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Date: Mon, 04 Oct 1999 14:45:39 -0700
From: Scott McMorrow <scott@vasthorizons.com>
Reply-To: scott@vasthorizons.com
Organization: SiQual
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To: Syed Huq <shuq@cisco.com>, ibis <ibis-users@eda.org>
Subject: Re: s2ibis2 error msg
References: <199910042014.NAA13288@jasper.cisco.com>
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Syed,

It means that when spice ran it produced no output.  This is
usually due to some spice error.  You should go to the
rdx8.spi file and run it standalone in Hspice to see what
the error or problem is.

regards,

scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

Syed Huq wrote:

> Hi,
>
> I am running the fix version of s2ibis2 on HSPICE and Solaris OS and got
> the following:
>
> s2ibis2.sun4.fix: Data begin marker analysis not found in output file rdx8.out.
>
> What does the above error msg mean ?
>
> Regards,
> Syed
> Cisco Systems, Inc



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From owner-ibis  Tue Oct  5 08:03:22 1999
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From: "Amir Shavit (r56010)" <r56010@email.sps.mot.com>
Organization: Motorola Semiconductors Israel
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Subject: Vmeas
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Hi,
I'm cuurrently working on an ibis model. I'v encountered some problem
with this parameter since it is different for rising and falling time. I
don't know what it should be equal to, since there are 2 different
values.
Thanks for your answers
Amir Shavit
Motorola Semiconductors Israel
From owner-ibis  Tue Oct  5 10:25:59 1999
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CC: "Amir Shavit (r56010)" <r56010@email.sps.mot.com>,
        "Udi Barel (r51365)" <r51365@email.sps.mot.com>
Subject: Re: Vmeas
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"Amir Shavit (r56010)" wrote:
> 
> Hi,
> I'm cuurrently working on an ibis model. I'v encountered some problem
> with this parameter since it is different for rising and falling time. I
> don't know what it should be equal to, since there are 2 different
> values.
> Thanks for your answers
> Amir Shavit
> Motorola Semiconductors Israel

Shalom Amir.

I'm a bit puzzled about the "different rising and falling" cases.
Are the defined timing points for the device you're working with
actually specified differently for the two directions?  The reason
I ask is because it's very hard to have a setup time, for instance,
which is different for rising and falling edges.

Vmeas _should_ be the point at which the characterized ("data sheet")
timing is defined.  This is usually 1.5v for LVCMOS, but is sometimes
50% of supply (a better way), 40% of supply (PCI and AGP), or an
external threshold (SSTL, HSTL, GTL, Rambus, etc.)

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Tue Oct  5 13:02:54 1999
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From: "Kern, Frank" <frank.kern@intel.com>
To: "'D. C. Sessions'" <dc.sessions@vlsi.com>, ibis-users@eda.org
Cc: "Amir Shavit (r56010)" <r56010@email.sps.mot.com>,
        "Udi Barel (r51365)" <r51365@email.sps.mot.com>
Subject: RE: Vmeas
Date: Tue, 5 Oct 1999 13:02:29 -0700 
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While on this topic...

Previous generations of IBIS forced Vinh, Vinl and Vmeas parameters to be
invariant across corner conditions. I build AGTL+ models where these
parameters vary with respect to Vtt, therefore across corners [i.e. Vtt +/-
10%, Vmeas =(2/3)*Vtt, Vih = Vmeas + 200mv, Vil = Vmeas - 200mv]. To keep
valid measurement points across the skew, I have to create separate model
files for fast, slow and typical conditions.  Does the new IBIS spec provide
flexibility to define Vinh, Vinl, and Vmeas for each corner??

Frank Kern


-----Original Message-----
From: D. C. Sessions [mailto:dc.sessions@vlsi.com]
Sent: Tuesday, October 05, 1999 10:24 AM
To: ibis-users@eda.org
Cc: Amir Shavit (r56010); Udi Barel (r51365)
Subject: Re: Vmeas


"Amir Shavit (r56010)" wrote:
> 
> Hi,
> I'm cuurrently working on an ibis model. I'v encountered some problem
> with this parameter since it is different for rising and falling time. I
> don't know what it should be equal to, since there are 2 different
> values.
> Thanks for your answers
> Amir Shavit
> Motorola Semiconductors Israel

Shalom Amir.

I'm a bit puzzled about the "different rising and falling" cases.
Are the defined timing points for the device you're working with
actually specified differently for the two directions?  The reason
I ask is because it's very hard to have a setup time, for instance,
which is different for rising and falling edges.

Vmeas _should_ be the point at which the characterized ("data sheet")
timing is defined.  This is usually 1.5v for LVCMOS, but is sometimes
50% of supply (a better way), 40% of supply (PCI and AGP), or an
external threshold (SSTL, HSTL, GTL, Rambus, etc.)

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Tue Oct  5 13:09:11 1999
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Organization: VLSI Technology Inc.
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To: "Kern, Frank" <frank.kern@intel.com>
CC: ibis-users@eda.org, "Amir Shavit (r56010)" <r56010@email.sps.mot.com>,
        "Udi Barel (r51365)" <r51365@email.sps.mot.com>
Subject: Re: Vmeas
References: <B38DE02578EBD111AC4200A0C95D19EE03138A7E@orsmsx30.jf.intel.com>
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"Kern, Frank" wrote:
> 
> While on this topic...
> 
> Previous generations of IBIS forced Vinh, Vinl and Vmeas parameters to be
> invariant across corner conditions. I build AGTL+ models where these
> parameters vary with respect to Vtt, therefore across corners [i.e. Vtt +/-
> 10%, Vmeas =(2/3)*Vtt, Vih = Vmeas + 200mv, Vil = Vmeas - 200mv]. To keep
> valid measurement points across the skew, I have to create separate model
> files for fast, slow and typical conditions.  Does the new IBIS spec provide
> flexibility to define Vinh, Vinl, and Vmeas for each corner?

[Model Spec] has made things a little bit better, but the real answer is that
we're working on it.  In particular, have a look at BIRD 62 and BIRD 63.

> -----Original Message-----
> From: D. C. Sessions [mailto:dc.sessions@vlsi.com]
> Sent: Tuesday, October 05, 1999 10:24 AM
> To: ibis-users@eda.org
> Cc: Amir Shavit (r56010); Udi Barel (r51365)
> Subject: Re: Vmeas
> 
> "Amir Shavit (r56010)" wrote:
> >
> > Hi,
> > I'm cuurrently working on an ibis model. I'v encountered some problem
> > with this parameter since it is different for rising and falling time. I
> > don't know what it should be equal to, since there are 2 different
> > values.
> > Thanks for your answers
> > Amir Shavit
> > Motorola Semiconductors Israel
> 
> Shalom Amir.
> 
> I'm a bit puzzled about the "different rising and falling" cases.
> Are the defined timing points for the device you're working with
> actually specified differently for the two directions?  The reason
> I ask is because it's very hard to have a setup time, for instance,
> which is different for rising and falling edges.
> 
> Vmeas _should_ be the point at which the characterized ("data sheet")
> timing is defined.  This is usually 1.5v for LVCMOS, but is sometimes
> 50% of supply (a better way), 40% of supply (PCI and AGP), or an
> external threshold (SSTL, HSTL, GTL, Rambus, etc.)
> 
> --
> D. C. Sessions
> dc.sessions@vlsi.com

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Tue Oct  5 23:22:26 1999
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From: "Amir Shavit" <r56010@email.sps.mot.com>
Organization: Motorola Semiconductors Israel
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To: "D. C. Sessions" <dc.sessions@vlsi.com>
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Hi,
Thanks for your answer. 
The data sheet takes the worst case between rising and falling, or
specifies falling (for strobes). The measurments were done from
clock=2.0v (active gigh) to either signal=2.0v (rising) or signal = 0.8v
(falling). These measurments are done so that the signal is active
(wither high or low), and not just mid way through the device voltage.
Thanks

D. C. Sessions wrote:
> 
> "Amir Shavit (r56010)" wrote:
> >
> > Hi,
> > I'm cuurrently working on an ibis model. I'v encountered some problem
> > with this parameter since it is different for rising and falling time. I
> > don't know what it should be equal to, since there are 2 different
> > values.
> > Thanks for your answers
> > Amir Shavit
> > Motorola Semiconductors Israel
> 
> Shalom Amir.
> 
> I'm a bit puzzled about the "different rising and falling" cases.
> Are the defined timing points for the device you're working with
> actually specified differently for the two directions?  The reason
> I ask is because it's very hard to have a setup time, for instance,
> which is different for rising and falling edges.
> 
> Vmeas _should_ be the point at which the characterized ("data sheet")
> timing is defined.  This is usually 1.5v for LVCMOS, but is sometimes
> 50% of supply (a better way), 40% of supply (PCI and AGP), or an
> external threshold (SSTL, HSTL, GTL, Rambus, etc.)
> 
> --
> D. C. Sessions
> dc.sessions@vlsi.com
From owner-ibis  Fri Oct  8 10:39:16 1999
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To IBIS Members:

I am sending some early DesignCon2000 information provided by the
DesignCon2000 staff for your planning and possible early registration
as noted below.

The IBIS Open Forum again plans to hold a Summit meeting at DesignCon2000
and also participate with a booth.

Bob Ross
Mentor Graphics

--------------------------------------------------------------------------

EIA IBIS Open Forum invites you to participate in DesignCon 2000

The EIA IBIS Open Forum is pleased to announce its associate sponsorship of
DesignCon 2000, and will again host the IBIS Summit Monday January 31, 2000
8:30 also at the Convention Center. We invite you and your organization to
participate in DesignCon 2000, the conference providing practical design
solutions from practicing engineers, to be held January 31-February 3, 2000
at the Santa Clara Convention Center, Santa Clara CA. 

The educational sessions of DesignCon support the IBIS model in design
engineering, Input/Output for system-on-chip, transmission line analysis,
high-speed printed circuit board design, and provide a multitude of other
conference sessions presented by engineers and engineering professionals
in intellectual property, high-performance system design, and wireless and
broadband design. In addition to the sessions, DesignCon 2000 will feature
5 panel discussions, half-day TecForums presented by professionals and
consultants, and a plenary panel on system and chip technology drivers for
third generation wireless.  The exhibit floor at DesignCon will feature
more than 100 exhibitors delivering technology solutions to the world's
design-engineering community.

DesignCon 2000: One Event-Four Conferences-All the Design Solutions

- System-on-Chip Design Conference
- High-Performance System Design Conference
- Wireless and Broadband Design Conference
- Intellectual Property (IP) World Forum

Register On-Line!   Visit

  http://www.designcon.com

for complete details, or access the DesignCon2000 link through the EIA IBIS
Open Forum home page Upcoming Events link

  http://www.eia.org/eig/ibis/ibis.htm

or click to download the DesignCon 2000 Advance Registration Brochure in
Adobe Acrobat format from:

  http://www.eda.org/pub/ibis/shows/designcon2000/ 

Select one of the discounts below and then follow one of the links to
register! 
 
Individuals of an IBIS Member Company receive a 15% discount on any
conference package.

Non-members registering by October 31 provides you with a 10% discount on
a three-day conference, entrance to the exhibits, and the conference
proceedings on CD Rom.  

Any returning attendee can receive a 20% discount, and the conference
proceedings on CD Rom. 

Featuring four conferences, DesignCon 2000 promises to be the leading
educational event in the design engineering industry. 

If you would like to receive a copy of of the complete DesignCon catalog
in November, e-mail our registration team at designcon@iec.org.
From owner-ibis  Fri Oct  8 11:59:07 1999
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Date: Fri, 08 Oct 1999 12:47:01 -0400
To: ibis-users@eda.org, ibis@eda.org
From: Kathy Breda <breda@nesa.com>
Subject: IBIS Summit - 10/14/99, Final Agenda
Mime-Version: 1.0
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Greetings,


If you are interested in attending the IBIS summit, and

have not responded, please reply to this message.


Attached you will find the Official Agenda for the meeting.


************************************************************


I B I S   S U M M I T   M E E T I N G   A G E N D A

Time/Date:      8:30 AM - 5:00 PM, Thursday, October 14, 1999


Location:       Marlboro Holiday Inn(NOT AT THE BOXBORO HOLIDAY
                                     INN THIS YEAR)

                265 Lakeside Ave. 
                Marlboro, MA
                Tel:  (508) 481-3000

              
Content:        IBIS Presentations and Discussions

Purpose:        Solicit and Exchange IBIS Model Related Information and
Ideas.

Sponsors:       Cadence
                Hyperlynx      
                North East Systems Associates, Inc.
                Praegitzer Design

  
PCB-East Conference: October 11-15, 1999

                Royal Plaza Trade Center
                Marlborough, Massachusetts
                See http://www.pcbeast.com/ for more information.


************************************************************

IBIS SUMMIT AGENDA



8:30 AM   MORNING REFRESHMENTS (from the Sponsors)


9:00 AM   Introductions and Business

          Bob Ross, Mentor Graphics

          Ed Sayre North East Systems Associates (NESA)


9:30 AM   "Navigating IBIS at 3Com"

          Roy Leventhal, 3Com


10:00 AM  "Model Extraction Based on Differential TDR"

          Steven Corey, Time Domain Analysis Systems


10:30 AM  BREAK (Refreshments from Sponsors)


10:45 AM  Roundtable - Accuracy Specification

          Bob Haller, Compaq (Leader)


12:00 PM  LUNCH (Provided to Attendees by the Sponsors)


1:00 PM   Roundtable - Input Modeling Discussion 

          Stephen Peters, Intel (Leader)


2:00 PM   Roundtable - IBIS Version 4.0 Features Discussion

          Bob Ross, Mentor Graphics (Leader)


2:30 PM   BREAK (Refreshments from Praegitzer Design)


2:45 PM   "Proposed Improvements to the SPICE to IBIS Tool"

          Mohamed Nasef, Mentor Graphics


3:15 PM   Roundtable - Spice to IBIS Discussion

          Mike LaBonte, Cadence


4:00 PM   Roundtable - Future of User Group Discussion

          Ed Sayre, NESA (Leader)


5:00 PM   FINAL BUSINESS AND ADJOURN



****************************************************************************

DIRECTIONS TO MEETING


The Marlboro Holiday Inn

is located at the junction of Route 20 and I-495

(exit 24A off I-495 North or South)

Located 4 miles from the Massachusetts Turnpike and

One Mile from I-290.  Thirty miles from Boston and

Logan International Airport


****************************************************************************


LIST OF NEARBY HOTELS

Marlboro Holiday Inn
265 Lakeside Ave. 
Marlboro, MA
Tel:  (508)481-3000

Boxboro Holiday Inn.  
One Adams Place
Boxboro, MA
Tel:  (978) 263-8701
Fax:  (978) 263-0518

Royal Plaza Hotel 
181 Boston Post road West
Marlborough, MA 01752
Tel:  (508) 460-0700

Radisson Inn
75 Felton St.
Marlboro, MA
Tel:  (508) 480-0015

Embassy Suites Hotels
123 Boston Post Rd.
West Marlboro, MA
Tel: (508) 485-5900

Amerscot House
61 West Acton Road
Stow, MA  01775
email: doreen@amerscot.com, web site http://www.amerscot.com
Tel: (978)897-0666, FAX (978)897-6914

Westford Regency Inn
219 Littleton Rd. (exit 32 off I-495)
Westford, MA
Tel:  (978) 692-8200

<end>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
|       NORTH EAST SYSTEMS ASSOCIATES, INC.       |
|      -------------------------------------      |
|     "High Performance Engineering & Design"     |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| Kathy Breda             e-mail: breda@nesa.com  |
| NESA, Inc.              http://www.nesa.com/    |
| 636 Great Road          Tel +1.978.897-8787     |
| Stow, MA 01775 USA      Fax +1.978.897-5359     |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
From owner-ibis  Fri Oct  8 17:03:34 1999
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Date: Sat, 09 Oct 1999 08:45:04 +0900
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I am Daniel Byun of Samsung Electronics in Korea.
I am responsible for signal integrity simulation of PC products.
I'd like to join IBIS Users' Group Reflector.
Thanks,
Daniel

From owner-ibis  Mon Oct 11 00:03:05 1999
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Dear Sirs,

I thank everybody for your help on IBIS modelisation.

Frank.


--
Frank AZEMA                      ALCATEL BUSINESS SYSTEM
Technical Direction             1 rt du Dr A. Schweitzer
Tel:+33(0)3.88.67.77.00    67000 ILLKIRCH Cedex - France
Fax:+33(0)3.88.67.70.83  Franck.Azema@sxb.bsf.alcatel.fr



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Dear Sirs,
<p>I thank everybody for your help on IBIS modelisation.
<p>Frank.
<br>&nbsp;
<pre>--&nbsp;
Frank AZEMA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ALCATEL BUSINESS SYSTEM
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From owner-ibis  Tue Oct 19 14:49:54 1999
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Message-ID: <380CE763.F8A4587F@cadence.com>
Date: Tue, 19 Oct 1999 17:49:23 -0400
From: Mike LaBonte <mikelabonte@cadence.com>
Organization: Cadence Design Systems
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The IBIS "Free Tools" web page has a link to the latest version of SpiTran, a
graphical user interface for s2ibis2 that is written in Java. Cadence is
contributing SpiTran to the IBIS community, so the public domain source code
is included. SpiTran 1.0 is designed to assist with the translation of SPICE
buffers to IBIS. It allows graphical editing of the s2ibis2 control file, produces
a properly connected SPICE wrapper circuit, and then runs s2ibis2.

You can go to the IBIS Free Tools web page at:
   http://www.eia.org/eig/ibis/tools.htm 
or go directly to the SpiTran download page at:
   http://www.eda.org/pub/ibis/s2ibis/spitran

The download includes Java components, documentation, examples, and source
code. You must install Java 1.2 and s2ibis2 to run it. 

Regards,

Mike LaBonte
Cadence Design Systems
From owner-ibis  Wed Oct 20 09:48:57 1999
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Date: Wed, 20 Oct 1999 12:49:01 -0400
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Hello,

I have a question about an IBIS model. I have created a chip level model
that is composed  numerous IBIS models. After I completed the model I
ran the ibischk program and it passed.  I will be providing this model 
to our customers, but want to make sure that it is filly tested. 

Are there any other tests that I should run to insure that it is
correct. I have reviewed the pin assignments, and that everything is
properly referenced.


Please reply to apalmieri@amcc.com

Thanks for your help,

Tony Palmieri

AMCC
Applications, IC Test and Verification Manager
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From owner-ibis  Wed Oct 20 10:58:23 1999
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From: "Beal, Weston" <Weston.Beal@compaq.com>
To: ibis-users@eda.org
Subject: RE: IBIS MOdel Question
Date: Wed, 20 Oct 1999 12:57:59 -0500
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Tony,

I commend you for at least checking your file with ibischk.  I've received
IBIS files from part vendors and the file doesn't even pass the syntax check
when I get it.

The first thing I look for in a new IBIS file is the timing reference load
(Vmeas, Cref, Rref, Vref) on all drivers.  Ibischk3 will issue warnings if
these don't exist.  If your customer is doing simulation for timing they
will need this information.

The second test I run is to look at the waveforms.  There are various tools
that will display your curves.  In general, all the I-V curves should pass
through 0.0A, 0.0V or very close thereunto.  Pullup and Pulldown curves
should be 0.0A through the normal operating voltage range.

Next, I would run an actual simulation with each of the drivers in the file.
It would be very impressive to your customer if you ran a simulation of your
models in the same simulator that they use.

If you did all that I would like to personally shake your hand and laud you
name across the internet!

Regards,
Weston Beal


		-----Original Message-----
		From:	Tony Palmieri [mailto:apalmieri@cimaron.com]
		Sent:	Wednesday, 20 October, 1999 11:49 AM
		To:	ibis-users@eda.org
		Subject:	IBIS MOdel Question

		 << File: Card for Tony Palmieri >> Hello,

		I have a question about an IBIS model. I have created a chip
level model
		that is composed  numerous IBIS models. After I completed
the model I
		ran the ibischk program and it passed.  I will be providing
this model 
		to our customers, but want to make sure that it is filly
tested. 

		Are there any other tests that I should run to insure that
it is
		correct. I have reviewed the pin assignments, and that
everything is
		properly referenced.


		Please reply to apalmieri@amcc.com

		Thanks for your help,

		Tony Palmieri

		AMCC
		Applications, IC Test and Verification Manager
From owner-ibis  Wed Oct 20 11:20:57 1999
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Make sure that:

1. The curves are continuous
2. The ramps (if any) cover the whole switching range
3. All pins are assigned to models

These are the three worst problems I've run into trying
to use IBIS models supplied by well-known parts vendors.

If you have access to one of the commercially available
signal integrity tools, try actually using the model
with it.  Your customers will thank you if you actually
make your model work in the simulators they are going
to use!

Kim Helliwell

Tony Palmieri wrote:
> 
> Hello,
> 
> I have a question about an IBIS model. I have created a chip level model
> that is composed  numerous IBIS models. After I completed the model I
> ran the ibischk program and it passed.  I will be providing this model
> to our customers, but want to make sure that it is filly tested.
> 
> Are there any other tests that I should run to insure that it is
> correct. I have reviewed the pin assignments, and that everything is
> properly referenced.
> 
> Please reply to apalmieri@amcc.com
> 
> Thanks for your help,
> 
> Tony Palmieri
> 
> AMCC
> Applications, IC Test and Verification Manager
> 
>   ------------------------------------------------------------------------
> 
>   Applications Manager
>   AMCC
> 
>   Applications Manager                                 <apalmieri@amcc.com>
>   AMCC
>   200 Brickstone Square ;Andover;Massachusetts;01810;  Fax: 978-623-0024
>                                                        Work: 978-623-0009 x3063
>   Additional Information:
>   Last Name    Palmieri
>   First Name   Anthony
>   Version      2.1

-- 
Kim Helliwell
Senior CAE Engineer
Acuson Corporation
Phone: 650 694 5030  FAX: 650 943 7260
From owner-ibis  Wed Oct 20 12:31:45 1999
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Message-ID: <D5210908318AD211A3F20000F8062CCD01C4C295@excpko-02.pko.dec.com>
From: "Haller, Robert" <Robert.Haller@compaq.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: FW: IBIS MOdel Question
Date: Wed, 20 Oct 1999 15:31:19 -0400
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 Great suggestions Weston.
I would like to add after performing syntax and various other sanity checks
I suggest you perform correlation between simulations and actual devices and
document those results (for you and your customer). The IBIS accuracy spec
(available on the IBIS web site http://www.eia.org/eig/ibis/ibis.htm) gives
some suggestions for loads and measurement techniques.  I also commend you
for due diligence in creating useful models for your semiconductor
customers. 

regards, bob

Robert J. Haller
Compaq Computer Corporation
AlphaServer Product Development
Phone:  (978) 493-4112
Fax:      (978) 493-0941
robert.haller@compaq.com



-----Original Message-----
From: Beal, Weston 
Sent: Wednesday, October 20, 1999 1:58 PM
To: ibis-users@eda.org
Subject: RE: IBIS MOdel Question


Tony,

I commend you for at least checking your file with ibischk.  I've received
IBIS files from part vendors and the file doesn't even pass the syntax check
when I get it.

The first thing I look for in a new IBIS file is the timing reference load
(Vmeas, Cref, Rref, Vref) on all drivers.  Ibischk3 will issue warnings if
these don't exist.  If your customer is doing simulation for timing they
will need this information.

The second test I run is to look at the waveforms.  There are various tools
that will display your curves.  In general, all the I-V curves should pass
through 0.0A, 0.0V or very close thereunto.  Pullup and Pulldown curves
should be 0.0A through the normal operating voltage range.

Next, I would run an actual simulation with each of the drivers in the file.
It would be very impressive to your customer if you ran a simulation of your
models in the same simulator that they use.

If you did all that I would like to personally shake your hand and laud you
name across the internet!

Regards,
Weston Beal


		-----Original Message-----
		From:	Tony Palmieri [mailto:apalmieri@cimaron.com]
		Sent:	Wednesday, 20 October, 1999 11:49 AM
		To:	ibis-users@eda.org
		Subject:	IBIS MOdel Question

		 << File: Card for Tony Palmieri >> Hello,

		I have a question about an IBIS model. I have created a chip
level model
		that is composed  numerous IBIS models. After I completed
the model I
		ran the ibischk program and it passed.  I will be providing
this model 
		to our customers, but want to make sure that it is filly
tested. 

		Are there any other tests that I should run to insure that
it is
		correct. I have reviewed the pin assignments, and that
everything is
		properly referenced.


		Please reply to apalmieri@amcc.com

		Thanks for your help,

		Tony Palmieri

		AMCC
		Applications, IC Test and Verification Manager
From owner-ibis  Thu Oct 21 07:37:57 1999
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Message-ID: <380F251C.F3EF88BF@cadence.com>
Date: Thu, 21 Oct 1999 10:37:16 -0400
From: Mike LaBonte <mikelabonte@cadence.com>
Organization: Cadence Design Systems
X-Mailer: Mozilla 4.6 [en] (WinNT; U)
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To: ibis-users@eda.org
Subject: Use of minimum and maximum Vcc reference
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We have seen Pullup curves in IBIS files where current falls to zero at 0V for typical,
0.5V for minimum, and at -0.5V (approximately) in the maximum column. My guess is that
these measurements are all relative to the *typical* value of Vcc.

The IBIS spec and the cookbook have adequate explanation of the fact that voltages
for [Pullup] and [POWER Clamp] are "relative to Vcc". It is implicit that the minimum
current column in a [Pullup] should be relative to the minimum Vcc, and likewise for
maximum. For example, if one has "[Voltage Range] 5.0V 4.5V 5.5V", and the Pullup
curve has 0 current at 0V for typical, minimum, and maximum, then one would interpret
this to mean that current falls to zero at 5.0V, 4.5V, and 5.5V for typical, minimum
and maximum case, respectively. Putting it another way, "relative to Vcc" means
"relative to typical Vcc for the typical current column, relative to minimum Vcc
for the minimum current column", etc. For "normal" devices I would expect current
to fall to zero in all 3 current columns at 0V, or at least nearly in the same row.

First of all, is my assumption correct? Either way, the correct interpretation should
be explicitly stated in the IBIS spec. Is it in there somewhere?

Mike
From owner-ibis  Thu Oct 21 08:27:05 1999
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Message-Id: <199910211526.IAA14946@jasper.cisco.com>
Date: Thu, 21 Oct 1999 08:26:15 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: Re: Use of minimum and maximum Vcc reference
To: ibis-users@eda.org, mikelabonte@cadence.com
MIME-Version: 1.0
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Mike,

Your assumptions are correct. This Vcc relative issues for each Typ, Min and
Max is handled well by s2ibis2(SPICE-to-IBIS)translator, BUT if the model 
developer is using a different tool or generating model from measurement, this
Vcc relative issues per-Vcc becomes critical.

I don't think this is clearly spelled out in the IBIS docs.

Regards,
Syed
Cisco Systems, Inc


> X-SMAP-Received-From: outside
> Date: Thu, 21 Oct 1999 10:37:16 -0400
> From: Mike LaBonte <mikelabonte@cadence.com>
> X-Accept-Language: en
> MIME-Version: 1.0
> To: ibis-users@eda.org
> Subject: Use of minimum and maximum Vcc reference
> Content-Transfer-Encoding: 7bit
> 
> We have seen Pullup curves in IBIS files where current falls to zero at 0V 
for typical,
> 0.5V for minimum, and at -0.5V (approximately) in the maximum column. My 
guess is that
> these measurements are all relative to the *typical* value of Vcc.
> 
> The IBIS spec and the cookbook have adequate explanation of the fact that 
voltages
> for [Pullup] and [POWER Clamp] are "relative to Vcc". It is implicit that the 
minimum
> current column in a [Pullup] should be relative to the minimum Vcc, and 
likewise for
> maximum. For example, if one has "[Voltage Range] 5.0V 4.5V 5.5V", and the 
Pullup
> curve has 0 current at 0V for typical, minimum, and maximum, then one would 
interpret
> this to mean that current falls to zero at 5.0V, 4.5V, and 5.5V for typical, 
minimum
> and maximum case, respectively. Putting it another way, "relative to Vcc" 
means
> "relative to typical Vcc for the typical current column, relative to minimum 
Vcc
> for the minimum current column", etc. For "normal" devices I would expect 
current
> to fall to zero in all 3 current columns at 0V, or at least nearly in the 
same row.
> 
> First of all, is my assumption correct? Either way, the correct 
interpretation should
> be explicitly stated in the IBIS spec. Is it in there somewhere?
> 
> Mike

From owner-ibis  Thu Oct 21 08:35:26 1999
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	for 
Reply-To: <rpryor@nortelnetworks.com>
From: "Ross Pryor" <rpryor@nortelnetworks.com>
To: "'Mike LaBonte'" <mikelabonte@cadence.com>, <ibis-users@eda.org>
Subject: RE: Use of minimum and maximum Vcc reference
Date: Thu, 21 Oct 1999 11:38:49 -0400
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Hi Mike,

My assumption is the same as yours - minimum current is relative to minimum VCC and maximum current is relative to maximum VCC.
Both SpecctraQuest and XTK operate under this assumption.  I too have seen many models from semiconductor suppliers where all pullup
and power clamp curves were adjusted relative to VCC typical, and consequently give incorrect VOH values  for min and max cases.  I
think this could be more explicitly covered in the spec so that there is no possibility of misinterpretation.

Ross
--------------
Ross Pryor
Nortel Networks
Billerica, MA
(978) 288-3811
ESN 248-3811
rpryor@nortelnetworks.com

-----Original Message-----
From: Mike LaBonte [mailto:mikelabonte@cadence.com]
Sent: Thursday, October 21, 1999 10:37 AM
To: ibis-users@eda.org
Subject: Use of minimum and maximum Vcc reference


We have seen Pullup curves in IBIS files where current falls to zero at 0V for typical,
0.5V for minimum, and at -0.5V (approximately) in the maximum column. My guess is that
these measurements are all relative to the *typical* value of Vcc.

The IBIS spec and the cookbook have adequate explanation of the fact that voltages
for [Pullup] and [POWER Clamp] are "relative to Vcc". It is implicit that the minimum
current column in a [Pullup] should be relative to the minimum Vcc, and likewise for
maximum. For example, if one has "[Voltage Range] 5.0V 4.5V 5.5V", and the Pullup
curve has 0 current at 0V for typical, minimum, and maximum, then one would interpret
this to mean that current falls to zero at 5.0V, 4.5V, and 5.5V for typical, minimum
and maximum case, respectively. Putting it another way, "relative to Vcc" means
"relative to typical Vcc for the typical current column, relative to minimum Vcc
for the minimum current column", etc. For "normal" devices I would expect current
to fall to zero in all 3 current columns at 0V, or at least nearly in the same row.

First of all, is my assumption correct? Either way, the correct interpretation should
be explicitly stated in the IBIS spec. Is it in there somewhere?

Mike

From owner-ibis  Fri Oct 22 11:12:58 1999
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Message-ID: <01BF1C7E.1E5E0B40.tom_dagostino@mentorg.com>
From: tomda <tom_dagostino@mentorg.com>
To: "'Kim Helliwell'" <khelliwe@acuson.com>,
        Tony Palmieri
	 <apalmieri@cimaron.com>
Cc: "ibis-users@eda.org" <ibis-users@eda.org>
Subject: RE: IBIS MOdel Question
Date: Fri, 22 Oct 1999 11:10:57 -0700
Organization: Mentor Graphics
X-Mailer: Microsoft Internet E-mail/MAPI - 8.0.0.4211
Encoding: 82 TEXT

There is one sanity check that I would like to see done on all models 
produced from SPICE data.  I have seen too many models that are constructed 
correctly fail this check.

Check to make sure the IV characteristics derived from SPICE match the IV 
characteristics of real parts.  The easiest was to do this is to put one of 
the buffers from each strength into both its high and low states.  Us a DC 
current meter and measure the output current to ground for the high state 
and to Vcc for the low state.  Then check to see if the measured current 
falls between the min and max values at the corresponding points on the IV 
curves.

Tom Dagostino

-----Original Message-----
From:	Kim Helliwell [SMTP:khelliwe@acuson.com]
Sent:	Wednesday, October 20, 1999 11:20 AM
To:	Tony Palmieri
Cc:	ibis-users@eda.org
Subject:	Re: IBIS MOdel Question

Make sure that:

1. The curves are continuous
2. The ramps (if any) cover the whole switching range
3. All pins are assigned to models

These are the three worst problems I've run into trying
to use IBIS models supplied by well-known parts vendors.

If you have access to one of the commercially available
signal integrity tools, try actually using the model
with it.  Your customers will thank you if you actually
make your model work in the simulators they are going
to use!

Kim Helliwell

Tony Palmieri wrote:
>
> Hello,
>
> I have a question about an IBIS model. I have created a chip level model
> that is composed  numerous IBIS models. After I completed the model I
> ran the ibischk program and it passed.  I will be providing this model
> to our customers, but want to make sure that it is filly tested.
>
> Are there any other tests that I should run to insure that it is
> correct. I have reviewed the pin assignments, and that everything is
> properly referenced.
>
> Please reply to apalmieri@amcc.com
>
> Thanks for your help,
>
> Tony Palmieri
>
> AMCC
> Applications, IC Test and Verification Manager
>
>   --------------------------------------------------------------------  
----
>
>   Applications Manager
>   AMCC
>
>   Applications Manager 
                                <apalmieri@amcc.com>
>   AMCC
>   200 Brickstone Square ;Andover;Massachusetts;01810;  Fax: 978-623-0024
>                                                        Work: 978-623-0009 
x3063
>   Additional Information:
>   Last Name    Palmieri
>   First Name   Anthony
>   Version      2.1

--
Kim Helliwell
Senior CAE Engineer
Acuson Corporation
Phone: 650 694 5030  FAX: 650 943 7260

From owner-ibis  Fri Oct 22 13:53:16 1999
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From: "D. C. Sessions" <dc.sessions@vlsi.com>
Organization: VLSI Technology Inc.
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To: "ibis-users@eda.org" <ibis-users@eda.org>
Subject: Re: IBIS MOdel Question
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tomda wrote:
> 
> There is one sanity check that I would like to see done on all models
> produced from SPICE data.  I have seen too many models that are constructed
> correctly fail this check.
> 
> Check to make sure the IV characteristics derived from SPICE match the IV
> characteristics of real parts.  The easiest was to do this is to put one of
> the buffers from each strength into both its high and low states.  Us a DC
> current meter and measure the output current to ground for the high state
> and to Vcc for the low state.  Then check to see if the measured current
> falls between the min and max values at the corresponding points on the IV
> curves.

Maybe I'm just a hard case, but why should this be a one-time exercise?
IBIS is perfectly suited to the job of specifying I/O characteristics to
manufacturing test.  They have to do drive-strength tests anyway to make
sure that there aren't any open output device legs, so instead of silly
stuff like "8.0 mA at 330 mV" or whatever just give them the IBIS model
and let them pick the best test points.

> -----Original Message-----
> From:   Kim Helliwell [SMTP:khelliwe@acuson.com]
> Sent:   Wednesday, October 20, 1999 11:20 AM
> To:     Tony Palmieri
> Cc:     ibis-users@eda.org
> Subject:        Re: IBIS MOdel Question
> 
> Make sure that:
> 
> 1. The curves are continuous
> 2. The ramps (if any) cover the whole switching range
> 3. All pins are assigned to models
> 
> These are the three worst problems I've run into trying
> to use IBIS models supplied by well-known parts vendors.
> 
> If you have access to one of the commercially available
> signal integrity tools, try actually using the model
> with it.  Your customers will thank you if you actually
> make your model work in the simulators they are going
> to use!
> 
> Kim Helliwell
> 
> Tony Palmieri wrote:
> >
> > Hello,
> >
> > I have a question about an IBIS model. I have created a chip level model
> > that is composed  numerous IBIS models. After I completed the model I
> > ran the ibischk program and it passed.  I will be providing this model
> > to our customers, but want to make sure that it is filly tested.
> >
> > Are there any other tests that I should run to insure that it is
> > correct. I have reviewed the pin assignments, and that everything is
> > properly referenced.
> >
> > Please reply to apalmieri@amcc.com
> >
> > Thanks for your help,
> >
> > Tony Palmieri
> >
> > AMCC
> > Applications, IC Test and Verification Manager
> >
> >   --------------------------------------------------------------------
> ----
> >
> >   Applications Manager
> >   AMCC
> >
> >   Applications Manager
>                                 <apalmieri@amcc.com>
> >   AMCC
> >   200 Brickstone Square ;Andover;Massachusetts;01810;  Fax: 978-623-0024
> >                                                        Work: 978-623-0009
> x3063
> >   Additional Information:
> >   Last Name    Palmieri
> >   First Name   Anthony
> >   Version      2.1
> 
> --
> Kim Helliwell
> Senior CAE Engineer
> Acuson Corporation
> Phone: 650 694 5030  FAX: 650 943 7260

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Tue Oct 26 11:39:11 1999
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Message-ID: <001501bf1fe0$b3f0c7a0$e299003e@a>
From: "eh" <elisimi@netvision.net.il>
To: <ibis-users@eda.org>
Subject: Technology Models vs. full IBIS models 
Date: Tue, 26 Oct 1999 20:33:25 +0200
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Dear friends,

We are evaluating a tool regarding signal integrity.
Our design is composed of modern devices ( DSP,DRAM,SRAM,FLASH,FCT etc).
Since we don't have the IBIS model for most of the parts, the supplier =
suggested that I use technology models.   I have a DSP, so I assigned it =
as FCT, for it was the closest choise.
The PCB crosstalk simulation showed problems we NEVER faced with five =
practical PCBs.
I assume that I have to get/order/develop IBIS models for all the parts, =
and not=20
use "technology models".
Is that true ?
Has anyone went through these ?
Has anyone a benchmark, comparing the major tools , offered this field =
of signal integrity (crosstalk...).

Regards,
Simi Eshkol
Sn Elec Eng.
VideoCom , Israel
=20


=20

------=_NextPart_000_0012_01BF1FF1.5A464FC0
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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT color=3D#000000 size=3D2>Dear friends,</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#000000 size=3D2>We are evaluating a tool regarding =
signal=20
integrity.</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>Our design is composed of modern =
devices (=20
DSP,DRAM,SRAM,FLASH,FCT etc).</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>Since we don't have the IBIS model =
for most of=20
the parts, the supplier suggested that I use technology =
models.&nbsp;&nbsp; I=20
have a DSP, so I assigned it as FCT, for it was the closest =
choise.</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>The PCB crosstalk simulation showed =
problems we=20
NEVER faced with five practical PCBs.</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>I assume that I have to =
get/order/develop IBIS=20
models for all the parts, and not&nbsp;</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>use &quot;technology =
models&quot;.</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2></FONT><FONT color=3D#000000 =
size=3D2>Is that true=20
?</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>Has anyone went through these =
?</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>Has anyone a benchmark, comparing =
the major=20
tools , offered this field of signal integrity =
(crosstalk...).</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2></FONT><FONT color=3D#000000=20
size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#000000 size=3D2>Regards,</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>Simi Eshkol</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>Sn Elec Eng.</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>VideoCom , Israel</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2>&nbsp;</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#000000 size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#000000 size=3D2>&nbsp;</FONT></DIV></BODY></HTML>

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From owner-ibis  Tue Oct 26 11:54:29 1999
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Message-ID: <3815F8AF.ACA0F119@mentor.com>
Date: Tue, 26 Oct 1999 11:53:35 -0700
From: Bob Ross <bob_ross@mentorg.com>
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To: eh <elisimi@netvision.net.il>
CC: ibis-users@eda.org
Subject: Re: Technology Models vs. full IBIS models
References: <001501bf1fe0$b3f0c7a0$e299003e@a>
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Hello:

In my opinion your best approach is to develop/obtain the actual
IBIS models.  Real buffers may differ significantly from generic
technology model buffers.  In some cases the differences occur
in parts or buffers from the same family of a manufacturer.

Regarding benchmarking major tools, this is a topic for the
Signal Integrity Reflector.  The IBIS reflector is not used
for Vendor Tool comparisons or business issues by EIA rules
and by the fact that the EIA IBIS Open Forum is funded by 
many vendors.

Best Regards,
Bob Ross
Mentor Graphics




> eh wrote:
> 
> Dear friends,
> 
> We are evaluating a tool regarding signal integrity.
> Our design is composed of modern devices ( DSP,DRAM,SRAM,FLASH,FCT etc).
> Since we don't have the IBIS model for most of the parts, the supplier
> suggested that I use technology models.   I have a DSP, so I assigned it as
> FCT, for it was the closest choise.
> The PCB crosstalk simulation showed problems we NEVER faced with five
> practical PCBs.
> I assume that I have to get/order/develop IBIS models for all the parts, and
> not
> use "technology models".
> Is that true ?
> Has anyone went through these ?
> Has anyone a benchmark, comparing the major tools , offered this field of
> signal integrity (crosstalk...).
> 
> Regards,
> Simi Eshkol
> Sn Elec Eng.
> VideoCom , Israel
> 
> 
> 
>
From owner-ibis  Tue Oct 26 13:12:54 1999
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Subject: Re: Technology Models vs. full IBIS models
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Bob Ross wrote:
> 
> Hello:
> 
> In my opinion your best approach is to develop/obtain the actual
> IBIS models.  Real buffers may differ significantly from generic
> technology model buffers.  In some cases the differences occur
> in parts or buffers from the same family of a manufacturer.
> 
> Regarding benchmarking major tools, this is a topic for the
> Signal Integrity Reflector.  The IBIS reflector is not used
> for Vendor Tool comparisons or business issues by EIA rules
> and by the fact that the EIA IBIS Open Forum is funded by
> many vendors.
> 
> Best Regards,
> Bob Ross
> Mentor Graphics
> 
> > eh wrote:
> >
> > Dear friends,
> >
> > We are evaluating a tool regarding signal integrity.
> > Our design is composed of modern devices ( DSP,DRAM,SRAM,FLASH,FCT etc).
> > Since we don't have the IBIS model for most of the parts, the supplier
> > suggested that I use technology models.   I have a DSP, so I assigned it as
> > FCT, for it was the closest choise.
> > The PCB crosstalk simulation showed problems we NEVER faced with five
> > practical PCBs.
> > I assume that I have to get/order/develop IBIS models for all the parts, and
> > not
> > use "technology models".
> > Is that true ?
> > Has anyone went through these ?
> > Has anyone a benchmark, comparing the major tools , offered this field of
> > signal integrity (crosstalk...).
> >
> > Regards,
> > Simi Eshkol
> > Sn Elec Eng.
> > VideoCom , Israel
> >
> >
> >
> >
I'm not sure what is meant by the technology models. I presume this
means the SPICE transistor level models based on the process. If that
is the case then obtaining the IBIS models of the same may not help
since IBIS models are mostly made from the SPICE models anyway. However
obtaining the correct models for the part number from the vendor may
get you more realistic results, this is independent of whether the model
is in SPICE or IBIS format.  

Best Regards, 
-- 
Fred Balistreri
fred@apsimtech.com

http://www.apsimtech.com
