| This file contains a description of Ibis 3.2 in the proposed language.
| It serves as proof that the new language is backward compatible,
| and provides a base from which extensions can be added.
| It would be provided with any implementation.
|
|---------------------------------------------------------------------
[Define Model] Series (pin1 pin2)
.node t1, t2, t3
resistor  Rseries  (pin1 pin2)	R = [R_Series]  || open
inductor  Lseries  (pin1 t1)	L = [L_Series]  || open
resistor  RLseries (t1   pin2)	R = [Rl_Series] || short
capacitor Cseries  (pin1 t2)	C = [C_Series]  || open
inductor  LCseries (t2   t3)	L = [Lc_Series] || short
resistor  RCseries (t3   pin2)	R = [Rc_Series] || short
resistor  Rsercur  (pin1 pin2)	I = [Series_Current](V) || open
vcg       Mosfet   (pin1 pin2 0 pin2) I = [Series_MOSFET](Vc,Vo=Vds) || open
.correlate fast/typ/slow=$2/$1/$3    [L*], [C*]
.correlate strong/typ/weak=$2/$1/$3  [R*]
.correlate strong/typ/weak=$3/$1/$2  [S*]
[End Define Model]
|---------------------------------------------------------------------
[Define Model] Series_switch (pin1 pin2 control)
.select (control)
  .case "[Off]"
    .inherit Series
  .end case
  .case "[On]"
    .inherit Series
  .end case
.end select
[End Define Model]
|---------------------------------------------------------------------
[Define Base] model_base (pin gnd control en 
			pullup_ref pulldown_ref power_clamp_ref gnd_clamp_ref)
.define VT = .86e-4 * [Temperature_Range] || .026
.if (!power_clamp_ref)
  .node power_clamp_ref
  vsource Vpcr (power_clamp_ref gnd)
				V = [POWER_Clamp_Reference] || [Voltage_Range]
.endif
.if (!gnd_clamp_ref)
  .node gnd_clamp_ref
  vsource Vgcr (gnd_clamp_ref gnd)  V = [GND_Clamp_Reference] || short
.endif
resistor  Rpc	 (pin power_clamp_ref)	I = [POWER_Clamp](-V)
resistor  Rgc	 (pin gnd_clamp_ref)	I = [GND_Clamp](V)
capacitor Cttpwr (pin power_clamp_ref)	
				C = [TTpower] * [POWER_Clamp](-V) / VT || open
capacitor Cttgnd (pin gnd_clamp_ref)
				C = [TTgnd]   * [GND_Clamp](V) / VT    || open
capacitor Ccomp	 (pin gnd)	C = C_comp

.array [Add_Submodel]
  .if ($1 == "Non_Driving")
    .node sm_enable
    inverter U1 (sm_enable gnd en)
  .else if ($1 == "All")
    .node sm_enable
    dsource U2 (sm_enable gnd) 1
  .else
    .assert ($1 == "Driving")
    .define sm_enable en
  .endif
  $0 X$0 (en=sm_enable ...)
.endarray

.correlate fast/typ/slow=$2/$1/$3	C*, [C*], [TT*]
.correlate strong/typ/weak=$2/$1/$3	[R*], [*Clamp], [Voltage_Range]
.correlate strong/weak=$3/$1/$2		[*Reference]
[End Define Base]
|---------------------------------------------------------------------
[Define Model] Terminator
.inherit model_base
.node t1
resistor  Rac	(pin t1)		R = [Rac] || short
capacitor Cac	(t1  gnd)		C = [Cac] || open
resistor  Rpwr	(pin power_clamp_ref)	R = [Rpower] || open
resistor  Rgnd	(pin gnd_clamp_ref)	R = [Rgnd] || open
[End Define Model]
|---------------------------------------------------------------------
[Define Model] Input
.inherit model_base
.if (Polarity == "Inverting")
  trigger switch_hi (V(pin) < [Model_Spec]Pulse_low ||
			(V(pin) < ([Model_Spec]Vmeas || Vmeas)
					for ([Model_Spec]Pulse_time || 0)))
  trigger switch_lo (V(pin) > [Model_Spec]Pulse_high ||
			(V(pin) > ([Model_Spec]Vmeas || Vmeas)
					for ([Model_Spec]Pulse_time || 0)))
.else
  .assert (Polarity == "Non-Inverting" || !Polarity)
  trigger switch_hi (V(pin) > [Model_Spec]Pulse_high ||
			(V(pin) > ([Model_Spec]Vmeas || Vmeas)
					for ([Model_Spec]Pulse_time || 0)))
  trigger switch_lo (V(pin) < [Model_Spec]Pulse_low ||
			(V(pin) < ([Model_Spec]Vmeas || Vmeas)
					for ([Model_Spec]Pulse_time || 0)))
.endif
alarm failure (
     V(pin) > [Model_Spec]D_overshoot_high ||
     V(pin) < [Model_Spec]D_overshoot_low  ||
     V(pin) > [Model_Spec]S_overshoot_high for [Model_Spec]D_overshoot_time ||
     V(pin) < [Model_Spec]S_overshoot_low  for [Model_Spec]D_overshoot_time ||
     never)
.export switch_hi, switch_lo, failure
|*** Keywords not covered: Vinl, Vinh, Vinh+, Vinh-, Vinl+, Vinl-
|*** Reason: too much typing.  Just more triggers and exports.
[End Define Model]
|---------------------------------------------------------------------
[Define Model] 3-state
.inherit model_base
.if (Enable == "Active-Low")
  .reverse en
.else
  .assert (Enable == "Active-High" || !Enable)
.endif  
.if (!pullup_ref)
  .node pullup_ref
  vsource Vpur (pullup_ref gnd)   V = [Pullup_Reference] || [Voltage_Range]
.endif
.if (!pulldown_ref)
  .node pulldown_ref
  vsource Vpdr (pulldown_ref gnd) V = [Pulldown_Reference] || short
.endif

.if ([Driver_Schedule])
  .array [Driver_Schedule]
    .node retrigger
    reshape U$0 (retrigger gnd control) $1 $2 $3 $4
    $0 X$0 (control=retrigger ...)
  .endarray
.else
  driver Udrv (pin gnd pullup_ref pulldown_ref tr tf en) (
	S1 = [Pullup](-V),  S0 = [Pulldown](V),
	T10 = [Falling_Waveform](T-TF,*) || [Ramp]dv/dt_f,
	T01 = [Rising_Waveform](T-TR,*)  || [Ramp]dv/dt_r,
	V1 = [Pullup_Reference] || [Voltage_Range],
	V0 = [Pulldown_Reference] || 0 )
  trigger  TR	(Logic(control) == 1)
  trigger  TF	(Logic(control) == 0)
.endif
.correlate strong/typ/weak=$2/$1/$3	[Pull*]
.correlate fast/typ/slow=$3/$1/$2	[*Waveform], [Ramp]*
[End Define Model]
|---------------------------------------------------------------------
[Define Model] Output
.inherit 3-state
.assert (!en)
.assert (!Enable)
.define en pullup_ref
[End Define Model]
|---------------------------------------------------------------------
[Define Model] Open_drain
.inherit Output
.define Pullup[V] = 0
[End Define Model]
|---------------------------------------------------------------------
[Define Model] Open_sink
.inherit Open_drain
[End Define Model]
|---------------------------------------------------------------------
[Define Model] Open_source
.inherit Output
.define Pulldown[V] = 0
[End Define Model]
|---------------------------------------------------------------------
[Define Model] I/O
.inherit 3-state
.inherit input
[End Define Model]
|---------------------------------------------------------------------
[Define Model] I/O_open_drain
.inherit I/O
.define Pullup[V] = 0
[End Define Model]
|---------------------------------------------------------------------
[Define Model] I/O_open_sink
.inherit I/O_open_drain
[End Define Model]
|---------------------------------------------------------------------
[Define Model] Input_ECL
.inherit Input
[End Define Model]
|---------------------------------------------------------------------
[Define Model] Output_ECL
.inherit Output
.define Pulldown[V] = Pulldown[-V]
[End Define Model]
|---------------------------------------------------------------------
[Define Model] 3-state_ECL
.inherit 3-state
.define Pulldown[V] = Pulldown[-V]
[End Define Model]
|---------------------------------------------------------------------
[Define Model] I/O_ECL
.inherit I/O
.define Pulldown[V] = Pulldown[-V]
[End Define Model]
|---------------------------------------------------------------------
[Define Submodel] Dynamic_clamp
.node t1 t2
resistor Rpc (pin t1)			I = [POWER_Clamp](-V)
resistor Rgc (pin t2)			I = [GND_Clamp](V)
vsource  Vpc (power_clamp_ref t1)	V = [POWER_Pulse_Table](T-TR) || short
vsource  Vgc (gnd_clamp_ref   t2)	V = [GND_Pulse_Table](T-TF)   || short
trigger  TR	(V(pin) > [Submodel_Spec]V_Trigger_r)
trigger  TF	(V(pin) < [Submodel_Spec]V_Trigger_f)
[End Define Submodel]
|---------------------------------------------------------------------
[Define Submodel] Bus_hold
driver Udrv (pin gnd pullup_ref pulldown_ref tr tf en) (
	S1 = [Pullup](-V),  S0 = [Pulldown](V),
	T10 = [Falling_Waveform](T-TF,*) || [Ramp]dv/dt_f,
	T01 = [Rising_Waveform](T-TR,*)  || [Ramp]dv/dt_r,
	V1 = [Pullup_Reference] || [Voltage_Range],
	V0 = [Pulldown_Reference] || 0 )
trigger  TRraw	 (V(pin) > [Submodel_Spec]V_Trigger_r)
trigger  TFraw	 (V(pin) < [Submodel_Spec]V_Trigger_f)
trigger  TR	 (TRraw || TFraw + [Submodel_Spec]Off_delay)
trigger  TF	 (TFraw || TRraw + [Submodel_Spec]Off_delay)
[End Define Model]
|---------------------------------------------------------------------
|---------------------------------------------------------------------
